PDU_FT25.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 00000188 08000000 08000000 00001000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 000070c4 08000188 08000188 00001188 2**3 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 00000038 0800724c 0800724c 0000824c 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 08007284 08007284 0000900c 2**0 CONTENTS 4 .ARM 00000000 08007284 08007284 0000900c 2**0 CONTENTS 5 .preinit_array 00000000 08007284 08007284 0000900c 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 08007284 08007284 00008284 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 7 .fini_array 00000004 08007288 08007288 00008288 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 8 .data 0000000c 20000000 0800728c 00009000 2**2 CONTENTS, ALLOC, LOAD, DATA 9 .bss 000002f4 2000000c 08007298 0000900c 2**2 ALLOC 10 ._user_heap_stack 00000600 20000300 08007298 00009300 2**0 ALLOC 11 .ARM.attributes 00000030 00000000 00000000 0000900c 2**0 CONTENTS, READONLY 12 .debug_info 00015a5c 00000000 00000000 0000903c 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_abbrev 00002f4b 00000000 00000000 0001ea98 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_aranges 00001148 00000000 00000000 000219e8 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_rnglists 00000d74 00000000 00000000 00022b30 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_macro 0001ea2e 00000000 00000000 000238a4 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .debug_line 000170a9 00000000 00000000 000422d2 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_str 000b7df6 00000000 00000000 0005937b 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .comment 00000043 00000000 00000000 00111171 2**0 CONTENTS, READONLY 20 .debug_frame 0000494c 00000000 00000000 001111b4 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS 21 .debug_line_str 00000071 00000000 00000000 00115b00 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 08000188 <__do_global_dtors_aux>: 8000188: b510 push {r4, lr} 800018a: 4c05 ldr r4, [pc, #20] @ (80001a0 <__do_global_dtors_aux+0x18>) 800018c: 7823 ldrb r3, [r4, #0] 800018e: b933 cbnz r3, 800019e <__do_global_dtors_aux+0x16> 8000190: 4b04 ldr r3, [pc, #16] @ (80001a4 <__do_global_dtors_aux+0x1c>) 8000192: b113 cbz r3, 800019a <__do_global_dtors_aux+0x12> 8000194: 4804 ldr r0, [pc, #16] @ (80001a8 <__do_global_dtors_aux+0x20>) 8000196: f3af 8000 nop.w 800019a: 2301 movs r3, #1 800019c: 7023 strb r3, [r4, #0] 800019e: bd10 pop {r4, pc} 80001a0: 2000000c .word 0x2000000c 80001a4: 00000000 .word 0x00000000 80001a8: 08007234 .word 0x08007234 080001ac : 80001ac: b508 push {r3, lr} 80001ae: 4b03 ldr r3, [pc, #12] @ (80001bc ) 80001b0: b11b cbz r3, 80001ba 80001b2: 4903 ldr r1, [pc, #12] @ (80001c0 ) 80001b4: 4803 ldr r0, [pc, #12] @ (80001c4 ) 80001b6: f3af 8000 nop.w 80001ba: bd08 pop {r3, pc} 80001bc: 00000000 .word 0x00000000 80001c0: 20000010 .word 0x20000010 80001c4: 08007234 .word 0x08007234 080001c8 <__aeabi_dmul>: 80001c8: b570 push {r4, r5, r6, lr} 80001ca: f04f 0cff mov.w ip, #255 @ 0xff 80001ce: f44c 6ce0 orr.w ip, ip, #1792 @ 0x700 80001d2: ea1c 5411 ands.w r4, ip, r1, lsr #20 80001d6: bf1d ittte ne 80001d8: ea1c 5513 andsne.w r5, ip, r3, lsr #20 80001dc: ea94 0f0c teqne r4, ip 80001e0: ea95 0f0c teqne r5, ip 80001e4: f000 f8de bleq 80003a4 <__aeabi_dmul+0x1dc> 80001e8: 442c add r4, r5 80001ea: ea81 0603 eor.w r6, r1, r3 80001ee: ea21 514c bic.w r1, r1, ip, lsl #21 80001f2: ea23 534c bic.w r3, r3, ip, lsl #21 80001f6: ea50 3501 orrs.w r5, r0, r1, lsl #12 80001fa: bf18 it ne 80001fc: ea52 3503 orrsne.w r5, r2, r3, lsl #12 8000200: f441 1180 orr.w r1, r1, #1048576 @ 0x100000 8000204: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 8000208: d038 beq.n 800027c <__aeabi_dmul+0xb4> 800020a: fba0 ce02 umull ip, lr, r0, r2 800020e: f04f 0500 mov.w r5, #0 8000212: fbe1 e502 umlal lr, r5, r1, r2 8000216: f006 4200 and.w r2, r6, #2147483648 @ 0x80000000 800021a: fbe0 e503 umlal lr, r5, r0, r3 800021e: f04f 0600 mov.w r6, #0 8000222: fbe1 5603 umlal r5, r6, r1, r3 8000226: f09c 0f00 teq ip, #0 800022a: bf18 it ne 800022c: f04e 0e01 orrne.w lr, lr, #1 8000230: f1a4 04ff sub.w r4, r4, #255 @ 0xff 8000234: f5b6 7f00 cmp.w r6, #512 @ 0x200 8000238: f564 7440 sbc.w r4, r4, #768 @ 0x300 800023c: d204 bcs.n 8000248 <__aeabi_dmul+0x80> 800023e: ea5f 0e4e movs.w lr, lr, lsl #1 8000242: 416d adcs r5, r5 8000244: eb46 0606 adc.w r6, r6, r6 8000248: ea42 21c6 orr.w r1, r2, r6, lsl #11 800024c: ea41 5155 orr.w r1, r1, r5, lsr #21 8000250: ea4f 20c5 mov.w r0, r5, lsl #11 8000254: ea40 505e orr.w r0, r0, lr, lsr #21 8000258: ea4f 2ece mov.w lr, lr, lsl #11 800025c: f1b4 0cfd subs.w ip, r4, #253 @ 0xfd 8000260: bf88 it hi 8000262: f5bc 6fe0 cmphi.w ip, #1792 @ 0x700 8000266: d81e bhi.n 80002a6 <__aeabi_dmul+0xde> 8000268: f1be 4f00 cmp.w lr, #2147483648 @ 0x80000000 800026c: bf08 it eq 800026e: ea5f 0e50 movseq.w lr, r0, lsr #1 8000272: f150 0000 adcs.w r0, r0, #0 8000276: eb41 5104 adc.w r1, r1, r4, lsl #20 800027a: bd70 pop {r4, r5, r6, pc} 800027c: f006 4600 and.w r6, r6, #2147483648 @ 0x80000000 8000280: ea46 0101 orr.w r1, r6, r1 8000284: ea40 0002 orr.w r0, r0, r2 8000288: ea81 0103 eor.w r1, r1, r3 800028c: ebb4 045c subs.w r4, r4, ip, lsr #1 8000290: bfc2 ittt gt 8000292: ebd4 050c rsbsgt r5, r4, ip 8000296: ea41 5104 orrgt.w r1, r1, r4, lsl #20 800029a: bd70 popgt {r4, r5, r6, pc} 800029c: f441 1180 orr.w r1, r1, #1048576 @ 0x100000 80002a0: f04f 0e00 mov.w lr, #0 80002a4: 3c01 subs r4, #1 80002a6: f300 80ab bgt.w 8000400 <__aeabi_dmul+0x238> 80002aa: f114 0f36 cmn.w r4, #54 @ 0x36 80002ae: bfde ittt le 80002b0: 2000 movle r0, #0 80002b2: f001 4100 andle.w r1, r1, #2147483648 @ 0x80000000 80002b6: bd70 pople {r4, r5, r6, pc} 80002b8: f1c4 0400 rsb r4, r4, #0 80002bc: 3c20 subs r4, #32 80002be: da35 bge.n 800032c <__aeabi_dmul+0x164> 80002c0: 340c adds r4, #12 80002c2: dc1b bgt.n 80002fc <__aeabi_dmul+0x134> 80002c4: f104 0414 add.w r4, r4, #20 80002c8: f1c4 0520 rsb r5, r4, #32 80002cc: fa00 f305 lsl.w r3, r0, r5 80002d0: fa20 f004 lsr.w r0, r0, r4 80002d4: fa01 f205 lsl.w r2, r1, r5 80002d8: ea40 0002 orr.w r0, r0, r2 80002dc: f001 4200 and.w r2, r1, #2147483648 @ 0x80000000 80002e0: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000 80002e4: eb10 70d3 adds.w r0, r0, r3, lsr #31 80002e8: fa21 f604 lsr.w r6, r1, r4 80002ec: eb42 0106 adc.w r1, r2, r6 80002f0: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 80002f4: bf08 it eq 80002f6: ea20 70d3 biceq.w r0, r0, r3, lsr #31 80002fa: bd70 pop {r4, r5, r6, pc} 80002fc: f1c4 040c rsb r4, r4, #12 8000300: f1c4 0520 rsb r5, r4, #32 8000304: fa00 f304 lsl.w r3, r0, r4 8000308: fa20 f005 lsr.w r0, r0, r5 800030c: fa01 f204 lsl.w r2, r1, r4 8000310: ea40 0002 orr.w r0, r0, r2 8000314: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 8000318: eb10 70d3 adds.w r0, r0, r3, lsr #31 800031c: f141 0100 adc.w r1, r1, #0 8000320: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 8000324: bf08 it eq 8000326: ea20 70d3 biceq.w r0, r0, r3, lsr #31 800032a: bd70 pop {r4, r5, r6, pc} 800032c: f1c4 0520 rsb r5, r4, #32 8000330: fa00 f205 lsl.w r2, r0, r5 8000334: ea4e 0e02 orr.w lr, lr, r2 8000338: fa20 f304 lsr.w r3, r0, r4 800033c: fa01 f205 lsl.w r2, r1, r5 8000340: ea43 0302 orr.w r3, r3, r2 8000344: fa21 f004 lsr.w r0, r1, r4 8000348: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 800034c: fa21 f204 lsr.w r2, r1, r4 8000350: ea20 0002 bic.w r0, r0, r2 8000354: eb00 70d3 add.w r0, r0, r3, lsr #31 8000358: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 800035c: bf08 it eq 800035e: ea20 70d3 biceq.w r0, r0, r3, lsr #31 8000362: bd70 pop {r4, r5, r6, pc} 8000364: f094 0f00 teq r4, #0 8000368: d10f bne.n 800038a <__aeabi_dmul+0x1c2> 800036a: f001 4600 and.w r6, r1, #2147483648 @ 0x80000000 800036e: 0040 lsls r0, r0, #1 8000370: eb41 0101 adc.w r1, r1, r1 8000374: f411 1f80 tst.w r1, #1048576 @ 0x100000 8000378: bf08 it eq 800037a: 3c01 subeq r4, #1 800037c: d0f7 beq.n 800036e <__aeabi_dmul+0x1a6> 800037e: ea41 0106 orr.w r1, r1, r6 8000382: f095 0f00 teq r5, #0 8000386: bf18 it ne 8000388: 4770 bxne lr 800038a: f003 4600 and.w r6, r3, #2147483648 @ 0x80000000 800038e: 0052 lsls r2, r2, #1 8000390: eb43 0303 adc.w r3, r3, r3 8000394: f413 1f80 tst.w r3, #1048576 @ 0x100000 8000398: bf08 it eq 800039a: 3d01 subeq r5, #1 800039c: d0f7 beq.n 800038e <__aeabi_dmul+0x1c6> 800039e: ea43 0306 orr.w r3, r3, r6 80003a2: 4770 bx lr 80003a4: ea94 0f0c teq r4, ip 80003a8: ea0c 5513 and.w r5, ip, r3, lsr #20 80003ac: bf18 it ne 80003ae: ea95 0f0c teqne r5, ip 80003b2: d00c beq.n 80003ce <__aeabi_dmul+0x206> 80003b4: ea50 0641 orrs.w r6, r0, r1, lsl #1 80003b8: bf18 it ne 80003ba: ea52 0643 orrsne.w r6, r2, r3, lsl #1 80003be: d1d1 bne.n 8000364 <__aeabi_dmul+0x19c> 80003c0: ea81 0103 eor.w r1, r1, r3 80003c4: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 80003c8: f04f 0000 mov.w r0, #0 80003cc: bd70 pop {r4, r5, r6, pc} 80003ce: ea50 0641 orrs.w r6, r0, r1, lsl #1 80003d2: bf06 itte eq 80003d4: 4610 moveq r0, r2 80003d6: 4619 moveq r1, r3 80003d8: ea52 0643 orrsne.w r6, r2, r3, lsl #1 80003dc: d019 beq.n 8000412 <__aeabi_dmul+0x24a> 80003de: ea94 0f0c teq r4, ip 80003e2: d102 bne.n 80003ea <__aeabi_dmul+0x222> 80003e4: ea50 3601 orrs.w r6, r0, r1, lsl #12 80003e8: d113 bne.n 8000412 <__aeabi_dmul+0x24a> 80003ea: ea95 0f0c teq r5, ip 80003ee: d105 bne.n 80003fc <__aeabi_dmul+0x234> 80003f0: ea52 3603 orrs.w r6, r2, r3, lsl #12 80003f4: bf1c itt ne 80003f6: 4610 movne r0, r2 80003f8: 4619 movne r1, r3 80003fa: d10a bne.n 8000412 <__aeabi_dmul+0x24a> 80003fc: ea81 0103 eor.w r1, r1, r3 8000400: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 8000404: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000 8000408: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000 800040c: f04f 0000 mov.w r0, #0 8000410: bd70 pop {r4, r5, r6, pc} 8000412: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000 8000416: f441 0178 orr.w r1, r1, #16252928 @ 0xf80000 800041a: bd70 pop {r4, r5, r6, pc} 0800041c <__aeabi_drsub>: 800041c: f081 4100 eor.w r1, r1, #2147483648 @ 0x80000000 8000420: e002 b.n 8000428 <__adddf3> 8000422: bf00 nop 08000424 <__aeabi_dsub>: 8000424: f083 4300 eor.w r3, r3, #2147483648 @ 0x80000000 08000428 <__adddf3>: 8000428: b530 push {r4, r5, lr} 800042a: ea4f 0441 mov.w r4, r1, lsl #1 800042e: ea4f 0543 mov.w r5, r3, lsl #1 8000432: ea94 0f05 teq r4, r5 8000436: bf08 it eq 8000438: ea90 0f02 teqeq r0, r2 800043c: bf1f itttt ne 800043e: ea54 0c00 orrsne.w ip, r4, r0 8000442: ea55 0c02 orrsne.w ip, r5, r2 8000446: ea7f 5c64 mvnsne.w ip, r4, asr #21 800044a: ea7f 5c65 mvnsne.w ip, r5, asr #21 800044e: f000 80e2 beq.w 8000616 <__adddf3+0x1ee> 8000452: ea4f 5454 mov.w r4, r4, lsr #21 8000456: ebd4 5555 rsbs r5, r4, r5, lsr #21 800045a: bfb8 it lt 800045c: 426d neglt r5, r5 800045e: dd0c ble.n 800047a <__adddf3+0x52> 8000460: 442c add r4, r5 8000462: ea80 0202 eor.w r2, r0, r2 8000466: ea81 0303 eor.w r3, r1, r3 800046a: ea82 0000 eor.w r0, r2, r0 800046e: ea83 0101 eor.w r1, r3, r1 8000472: ea80 0202 eor.w r2, r0, r2 8000476: ea81 0303 eor.w r3, r1, r3 800047a: 2d36 cmp r5, #54 @ 0x36 800047c: bf88 it hi 800047e: bd30 pophi {r4, r5, pc} 8000480: f011 4f00 tst.w r1, #2147483648 @ 0x80000000 8000484: ea4f 3101 mov.w r1, r1, lsl #12 8000488: f44f 1c80 mov.w ip, #1048576 @ 0x100000 800048c: ea4c 3111 orr.w r1, ip, r1, lsr #12 8000490: d002 beq.n 8000498 <__adddf3+0x70> 8000492: 4240 negs r0, r0 8000494: eb61 0141 sbc.w r1, r1, r1, lsl #1 8000498: f013 4f00 tst.w r3, #2147483648 @ 0x80000000 800049c: ea4f 3303 mov.w r3, r3, lsl #12 80004a0: ea4c 3313 orr.w r3, ip, r3, lsr #12 80004a4: d002 beq.n 80004ac <__adddf3+0x84> 80004a6: 4252 negs r2, r2 80004a8: eb63 0343 sbc.w r3, r3, r3, lsl #1 80004ac: ea94 0f05 teq r4, r5 80004b0: f000 80a7 beq.w 8000602 <__adddf3+0x1da> 80004b4: f1a4 0401 sub.w r4, r4, #1 80004b8: f1d5 0e20 rsbs lr, r5, #32 80004bc: db0d blt.n 80004da <__adddf3+0xb2> 80004be: fa02 fc0e lsl.w ip, r2, lr 80004c2: fa22 f205 lsr.w r2, r2, r5 80004c6: 1880 adds r0, r0, r2 80004c8: f141 0100 adc.w r1, r1, #0 80004cc: fa03 f20e lsl.w r2, r3, lr 80004d0: 1880 adds r0, r0, r2 80004d2: fa43 f305 asr.w r3, r3, r5 80004d6: 4159 adcs r1, r3 80004d8: e00e b.n 80004f8 <__adddf3+0xd0> 80004da: f1a5 0520 sub.w r5, r5, #32 80004de: f10e 0e20 add.w lr, lr, #32 80004e2: 2a01 cmp r2, #1 80004e4: fa03 fc0e lsl.w ip, r3, lr 80004e8: bf28 it cs 80004ea: f04c 0c02 orrcs.w ip, ip, #2 80004ee: fa43 f305 asr.w r3, r3, r5 80004f2: 18c0 adds r0, r0, r3 80004f4: eb51 71e3 adcs.w r1, r1, r3, asr #31 80004f8: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000 80004fc: d507 bpl.n 800050e <__adddf3+0xe6> 80004fe: f04f 0e00 mov.w lr, #0 8000502: f1dc 0c00 rsbs ip, ip, #0 8000506: eb7e 0000 sbcs.w r0, lr, r0 800050a: eb6e 0101 sbc.w r1, lr, r1 800050e: f5b1 1f80 cmp.w r1, #1048576 @ 0x100000 8000512: d31b bcc.n 800054c <__adddf3+0x124> 8000514: f5b1 1f00 cmp.w r1, #2097152 @ 0x200000 8000518: d30c bcc.n 8000534 <__adddf3+0x10c> 800051a: 0849 lsrs r1, r1, #1 800051c: ea5f 0030 movs.w r0, r0, rrx 8000520: ea4f 0c3c mov.w ip, ip, rrx 8000524: f104 0401 add.w r4, r4, #1 8000528: ea4f 5244 mov.w r2, r4, lsl #21 800052c: f512 0f80 cmn.w r2, #4194304 @ 0x400000 8000530: f080 809a bcs.w 8000668 <__adddf3+0x240> 8000534: f1bc 4f00 cmp.w ip, #2147483648 @ 0x80000000 8000538: bf08 it eq 800053a: ea5f 0c50 movseq.w ip, r0, lsr #1 800053e: f150 0000 adcs.w r0, r0, #0 8000542: eb41 5104 adc.w r1, r1, r4, lsl #20 8000546: ea41 0105 orr.w r1, r1, r5 800054a: bd30 pop {r4, r5, pc} 800054c: ea5f 0c4c movs.w ip, ip, lsl #1 8000550: 4140 adcs r0, r0 8000552: eb41 0101 adc.w r1, r1, r1 8000556: 3c01 subs r4, #1 8000558: bf28 it cs 800055a: f5b1 1f80 cmpcs.w r1, #1048576 @ 0x100000 800055e: d2e9 bcs.n 8000534 <__adddf3+0x10c> 8000560: f091 0f00 teq r1, #0 8000564: bf04 itt eq 8000566: 4601 moveq r1, r0 8000568: 2000 moveq r0, #0 800056a: fab1 f381 clz r3, r1 800056e: bf08 it eq 8000570: 3320 addeq r3, #32 8000572: f1a3 030b sub.w r3, r3, #11 8000576: f1b3 0220 subs.w r2, r3, #32 800057a: da0c bge.n 8000596 <__adddf3+0x16e> 800057c: 320c adds r2, #12 800057e: dd08 ble.n 8000592 <__adddf3+0x16a> 8000580: f102 0c14 add.w ip, r2, #20 8000584: f1c2 020c rsb r2, r2, #12 8000588: fa01 f00c lsl.w r0, r1, ip 800058c: fa21 f102 lsr.w r1, r1, r2 8000590: e00c b.n 80005ac <__adddf3+0x184> 8000592: f102 0214 add.w r2, r2, #20 8000596: bfd8 it le 8000598: f1c2 0c20 rsble ip, r2, #32 800059c: fa01 f102 lsl.w r1, r1, r2 80005a0: fa20 fc0c lsr.w ip, r0, ip 80005a4: bfdc itt le 80005a6: ea41 010c orrle.w r1, r1, ip 80005aa: 4090 lslle r0, r2 80005ac: 1ae4 subs r4, r4, r3 80005ae: bfa2 ittt ge 80005b0: eb01 5104 addge.w r1, r1, r4, lsl #20 80005b4: 4329 orrge r1, r5 80005b6: bd30 popge {r4, r5, pc} 80005b8: ea6f 0404 mvn.w r4, r4 80005bc: 3c1f subs r4, #31 80005be: da1c bge.n 80005fa <__adddf3+0x1d2> 80005c0: 340c adds r4, #12 80005c2: dc0e bgt.n 80005e2 <__adddf3+0x1ba> 80005c4: f104 0414 add.w r4, r4, #20 80005c8: f1c4 0220 rsb r2, r4, #32 80005cc: fa20 f004 lsr.w r0, r0, r4 80005d0: fa01 f302 lsl.w r3, r1, r2 80005d4: ea40 0003 orr.w r0, r0, r3 80005d8: fa21 f304 lsr.w r3, r1, r4 80005dc: ea45 0103 orr.w r1, r5, r3 80005e0: bd30 pop {r4, r5, pc} 80005e2: f1c4 040c rsb r4, r4, #12 80005e6: f1c4 0220 rsb r2, r4, #32 80005ea: fa20 f002 lsr.w r0, r0, r2 80005ee: fa01 f304 lsl.w r3, r1, r4 80005f2: ea40 0003 orr.w r0, r0, r3 80005f6: 4629 mov r1, r5 80005f8: bd30 pop {r4, r5, pc} 80005fa: fa21 f004 lsr.w r0, r1, r4 80005fe: 4629 mov r1, r5 8000600: bd30 pop {r4, r5, pc} 8000602: f094 0f00 teq r4, #0 8000606: f483 1380 eor.w r3, r3, #1048576 @ 0x100000 800060a: bf06 itte eq 800060c: f481 1180 eoreq.w r1, r1, #1048576 @ 0x100000 8000610: 3401 addeq r4, #1 8000612: 3d01 subne r5, #1 8000614: e74e b.n 80004b4 <__adddf3+0x8c> 8000616: ea7f 5c64 mvns.w ip, r4, asr #21 800061a: bf18 it ne 800061c: ea7f 5c65 mvnsne.w ip, r5, asr #21 8000620: d029 beq.n 8000676 <__adddf3+0x24e> 8000622: ea94 0f05 teq r4, r5 8000626: bf08 it eq 8000628: ea90 0f02 teqeq r0, r2 800062c: d005 beq.n 800063a <__adddf3+0x212> 800062e: ea54 0c00 orrs.w ip, r4, r0 8000632: bf04 itt eq 8000634: 4619 moveq r1, r3 8000636: 4610 moveq r0, r2 8000638: bd30 pop {r4, r5, pc} 800063a: ea91 0f03 teq r1, r3 800063e: bf1e ittt ne 8000640: 2100 movne r1, #0 8000642: 2000 movne r0, #0 8000644: bd30 popne {r4, r5, pc} 8000646: ea5f 5c54 movs.w ip, r4, lsr #21 800064a: d105 bne.n 8000658 <__adddf3+0x230> 800064c: 0040 lsls r0, r0, #1 800064e: 4149 adcs r1, r1 8000650: bf28 it cs 8000652: f041 4100 orrcs.w r1, r1, #2147483648 @ 0x80000000 8000656: bd30 pop {r4, r5, pc} 8000658: f514 0480 adds.w r4, r4, #4194304 @ 0x400000 800065c: bf3c itt cc 800065e: f501 1180 addcc.w r1, r1, #1048576 @ 0x100000 8000662: bd30 popcc {r4, r5, pc} 8000664: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000 8000668: f045 41fe orr.w r1, r5, #2130706432 @ 0x7f000000 800066c: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000 8000670: f04f 0000 mov.w r0, #0 8000674: bd30 pop {r4, r5, pc} 8000676: ea7f 5c64 mvns.w ip, r4, asr #21 800067a: bf1a itte ne 800067c: 4619 movne r1, r3 800067e: 4610 movne r0, r2 8000680: ea7f 5c65 mvnseq.w ip, r5, asr #21 8000684: bf1c itt ne 8000686: 460b movne r3, r1 8000688: 4602 movne r2, r0 800068a: ea50 3401 orrs.w r4, r0, r1, lsl #12 800068e: bf06 itte eq 8000690: ea52 3503 orrseq.w r5, r2, r3, lsl #12 8000694: ea91 0f03 teqeq r1, r3 8000698: f441 2100 orrne.w r1, r1, #524288 @ 0x80000 800069c: bd30 pop {r4, r5, pc} 800069e: bf00 nop 080006a0 <__aeabi_ui2d>: 80006a0: f090 0f00 teq r0, #0 80006a4: bf04 itt eq 80006a6: 2100 moveq r1, #0 80006a8: 4770 bxeq lr 80006aa: b530 push {r4, r5, lr} 80006ac: f44f 6480 mov.w r4, #1024 @ 0x400 80006b0: f104 0432 add.w r4, r4, #50 @ 0x32 80006b4: f04f 0500 mov.w r5, #0 80006b8: f04f 0100 mov.w r1, #0 80006bc: e750 b.n 8000560 <__adddf3+0x138> 80006be: bf00 nop 080006c0 <__aeabi_i2d>: 80006c0: f090 0f00 teq r0, #0 80006c4: bf04 itt eq 80006c6: 2100 moveq r1, #0 80006c8: 4770 bxeq lr 80006ca: b530 push {r4, r5, lr} 80006cc: f44f 6480 mov.w r4, #1024 @ 0x400 80006d0: f104 0432 add.w r4, r4, #50 @ 0x32 80006d4: f010 4500 ands.w r5, r0, #2147483648 @ 0x80000000 80006d8: bf48 it mi 80006da: 4240 negmi r0, r0 80006dc: f04f 0100 mov.w r1, #0 80006e0: e73e b.n 8000560 <__adddf3+0x138> 80006e2: bf00 nop 080006e4 <__aeabi_f2d>: 80006e4: 0042 lsls r2, r0, #1 80006e6: ea4f 01e2 mov.w r1, r2, asr #3 80006ea: ea4f 0131 mov.w r1, r1, rrx 80006ee: ea4f 7002 mov.w r0, r2, lsl #28 80006f2: bf1f itttt ne 80006f4: f012 437f andsne.w r3, r2, #4278190080 @ 0xff000000 80006f8: f093 4f7f teqne r3, #4278190080 @ 0xff000000 80006fc: f081 5160 eorne.w r1, r1, #939524096 @ 0x38000000 8000700: 4770 bxne lr 8000702: f032 427f bics.w r2, r2, #4278190080 @ 0xff000000 8000706: bf08 it eq 8000708: 4770 bxeq lr 800070a: f093 4f7f teq r3, #4278190080 @ 0xff000000 800070e: bf04 itt eq 8000710: f441 2100 orreq.w r1, r1, #524288 @ 0x80000 8000714: 4770 bxeq lr 8000716: b530 push {r4, r5, lr} 8000718: f44f 7460 mov.w r4, #896 @ 0x380 800071c: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000 8000720: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000 8000724: e71c b.n 8000560 <__adddf3+0x138> 8000726: bf00 nop 08000728 <__aeabi_ul2d>: 8000728: ea50 0201 orrs.w r2, r0, r1 800072c: bf08 it eq 800072e: 4770 bxeq lr 8000730: b530 push {r4, r5, lr} 8000732: f04f 0500 mov.w r5, #0 8000736: e00a b.n 800074e <__aeabi_l2d+0x16> 08000738 <__aeabi_l2d>: 8000738: ea50 0201 orrs.w r2, r0, r1 800073c: bf08 it eq 800073e: 4770 bxeq lr 8000740: b530 push {r4, r5, lr} 8000742: f011 4500 ands.w r5, r1, #2147483648 @ 0x80000000 8000746: d502 bpl.n 800074e <__aeabi_l2d+0x16> 8000748: 4240 negs r0, r0 800074a: eb61 0141 sbc.w r1, r1, r1, lsl #1 800074e: f44f 6480 mov.w r4, #1024 @ 0x400 8000752: f104 0432 add.w r4, r4, #50 @ 0x32 8000756: ea5f 5c91 movs.w ip, r1, lsr #22 800075a: f43f aed8 beq.w 800050e <__adddf3+0xe6> 800075e: f04f 0203 mov.w r2, #3 8000762: ea5f 0cdc movs.w ip, ip, lsr #3 8000766: bf18 it ne 8000768: 3203 addne r2, #3 800076a: ea5f 0cdc movs.w ip, ip, lsr #3 800076e: bf18 it ne 8000770: 3203 addne r2, #3 8000772: eb02 02dc add.w r2, r2, ip, lsr #3 8000776: f1c2 0320 rsb r3, r2, #32 800077a: fa00 fc03 lsl.w ip, r0, r3 800077e: fa20 f002 lsr.w r0, r0, r2 8000782: fa01 fe03 lsl.w lr, r1, r3 8000786: ea40 000e orr.w r0, r0, lr 800078a: fa21 f102 lsr.w r1, r1, r2 800078e: 4414 add r4, r2 8000790: e6bd b.n 800050e <__adddf3+0xe6> 8000792: bf00 nop 08000794 <__aeabi_d2uiz>: 8000794: 004a lsls r2, r1, #1 8000796: d211 bcs.n 80007bc <__aeabi_d2uiz+0x28> 8000798: f512 1200 adds.w r2, r2, #2097152 @ 0x200000 800079c: d211 bcs.n 80007c2 <__aeabi_d2uiz+0x2e> 800079e: d50d bpl.n 80007bc <__aeabi_d2uiz+0x28> 80007a0: f46f 7378 mvn.w r3, #992 @ 0x3e0 80007a4: ebb3 5262 subs.w r2, r3, r2, asr #21 80007a8: d40e bmi.n 80007c8 <__aeabi_d2uiz+0x34> 80007aa: ea4f 23c1 mov.w r3, r1, lsl #11 80007ae: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 80007b2: ea43 5350 orr.w r3, r3, r0, lsr #21 80007b6: fa23 f002 lsr.w r0, r3, r2 80007ba: 4770 bx lr 80007bc: f04f 0000 mov.w r0, #0 80007c0: 4770 bx lr 80007c2: ea50 3001 orrs.w r0, r0, r1, lsl #12 80007c6: d102 bne.n 80007ce <__aeabi_d2uiz+0x3a> 80007c8: f04f 30ff mov.w r0, #4294967295 80007cc: 4770 bx lr 80007ce: f04f 0000 mov.w r0, #0 80007d2: 4770 bx lr 080007d4 : extern uint32_t lastheartbeat; extern int inhibit_SDC; void can_init(CAN_HandleTypeDef* hcan){ 80007d4: b580 push {r7, lr} 80007d6: b082 sub sp, #8 80007d8: af00 add r7, sp, #0 80007da: 6078 str r0, [r7, #4] ftcan_init(hcan); 80007dc: 6878 ldr r0, [r7, #4] 80007de: f000 f953 bl 8000a88 ftcan_add_filter(0x00, 0x00); // no filter 80007e2: 2100 movs r1, #0 80007e4: 2000 movs r0, #0 80007e6: f000 f993 bl 8000b10 } 80007ea: bf00 nop 80007ec: 3708 adds r7, #8 80007ee: 46bd mov sp, r7 80007f0: bd80 pop {r7, pc} ... 080007f4 : void can_sendloop(){ 80007f4: b580 push {r7, lr} 80007f6: b084 sub sp, #16 80007f8: af00 add r7, sp, #0 static uint8_t additionaltxcounter = 0; uint8_t status_data[3]; status_data[0] = update_ports.porta.porta; 80007fa: 4b79 ldr r3, [pc, #484] @ (80009e0 ) 80007fc: 781b ldrb r3, [r3, #0] 80007fe: 733b strb r3, [r7, #12] status_data[1] = update_ports.portb.portb; 8000800: 4b77 ldr r3, [pc, #476] @ (80009e0 ) 8000802: 785b ldrb r3, [r3, #1] 8000804: 737b strb r3, [r7, #13] status_data[2] = !inhibit_SDC; 8000806: 4b77 ldr r3, [pc, #476] @ (80009e4 ) 8000808: 681b ldr r3, [r3, #0] 800080a: 2b00 cmp r3, #0 800080c: bf0c ite eq 800080e: 2301 moveq r3, #1 8000810: 2300 movne r3, #0 8000812: b2db uxtb r3, r3 8000814: 73bb strb r3, [r7, #14] ftcan_transmit(TX_STATUS_MSG_ID, status_data, 3); 8000816: f107 030c add.w r3, r7, #12 800081a: 2203 movs r2, #3 800081c: 4619 mov r1, r3 800081e: 20c9 movs r0, #201 @ 0xc9 8000820: f000 f952 bl 8000ac8 uint8_t data[8]; switch (additionaltxcounter) { 8000824: 4b70 ldr r3, [pc, #448] @ (80009e8 ) 8000826: 781b ldrb r3, [r3, #0] 8000828: 2b03 cmp r3, #3 800082a: f200 80c7 bhi.w 80009bc 800082e: a201 add r2, pc, #4 @ (adr r2, 8000834 ) 8000830: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8000834: 08000845 .word 0x08000845 8000838: 080008a3 .word 0x080008a3 800083c: 08000901 .word 0x08000901 8000840: 0800095f .word 0x0800095f case 0: data[0] = current_measurements_adc_val.alwayson >> 8; 8000844: 4b69 ldr r3, [pc, #420] @ (80009ec ) 8000846: 8a1b ldrh r3, [r3, #16] 8000848: 0a1b lsrs r3, r3, #8 800084a: b29b uxth r3, r3 800084c: b2db uxtb r3, r3 800084e: 713b strb r3, [r7, #4] data[1] = current_measurements_adc_val.alwayson & 0xFF; 8000850: 4b66 ldr r3, [pc, #408] @ (80009ec ) 8000852: 8a1b ldrh r3, [r3, #16] 8000854: b2db uxtb r3, r3 8000856: 717b strb r3, [r7, #5] data[2] = current_measurements_adc_val.misc >> 8; 8000858: 4b64 ldr r3, [pc, #400] @ (80009ec ) 800085a: 89db ldrh r3, [r3, #14] 800085c: 0a1b lsrs r3, r3, #8 800085e: b29b uxth r3, r3 8000860: b2db uxtb r3, r3 8000862: 71bb strb r3, [r7, #6] data[3] = current_measurements_adc_val.misc & 0xFF; 8000864: 4b61 ldr r3, [pc, #388] @ (80009ec ) 8000866: 89db ldrh r3, [r3, #14] 8000868: b2db uxtb r3, r3 800086a: 71fb strb r3, [r7, #7] data[4] = current_measurements_adc_val.inverter >> 8; 800086c: 4b5f ldr r3, [pc, #380] @ (80009ec ) 800086e: 895b ldrh r3, [r3, #10] 8000870: 0a1b lsrs r3, r3, #8 8000872: b29b uxth r3, r3 8000874: b2db uxtb r3, r3 8000876: 723b strb r3, [r7, #8] data[5] = current_measurements_adc_val.inverter & 0xFF; 8000878: 4b5c ldr r3, [pc, #368] @ (80009ec ) 800087a: 895b ldrh r3, [r3, #10] 800087c: b2db uxtb r3, r3 800087e: 727b strb r3, [r7, #9] data[6] = current_measurements_adc_val.sdc >> 8; 8000880: 4b5a ldr r3, [pc, #360] @ (80009ec ) 8000882: 8a5b ldrh r3, [r3, #18] 8000884: 0a1b lsrs r3, r3, #8 8000886: b29b uxth r3, r3 8000888: b2db uxtb r3, r3 800088a: 72bb strb r3, [r7, #10] data[7] = current_measurements_adc_val.sdc & 0xFF; 800088c: 4b57 ldr r3, [pc, #348] @ (80009ec ) 800088e: 8a5b ldrh r3, [r3, #18] 8000890: b2db uxtb r3, r3 8000892: 72fb strb r3, [r7, #11] ftcan_transmit(CUR_CHANNELS_1_ID, data, 8); 8000894: 1d3b adds r3, r7, #4 8000896: 2208 movs r2, #8 8000898: 4619 mov r1, r3 800089a: 20ca movs r0, #202 @ 0xca 800089c: f000 f914 bl 8000ac8 break; 80008a0: e08d b.n 80009be case 1: data[0] = current_measurements_adc_val.acc_cooling >> 8; 80008a2: 4b52 ldr r3, [pc, #328] @ (80009ec ) 80008a4: 881b ldrh r3, [r3, #0] 80008a6: 0a1b lsrs r3, r3, #8 80008a8: b29b uxth r3, r3 80008aa: b2db uxtb r3, r3 80008ac: 713b strb r3, [r7, #4] data[1] = current_measurements_adc_val.acc_cooling & 0xFF; 80008ae: 4b4f ldr r3, [pc, #316] @ (80009ec ) 80008b0: 881b ldrh r3, [r3, #0] 80008b2: b2db uxtb r3, r3 80008b4: 717b strb r3, [r7, #5] data[2] = current_measurements_adc_val.ts_cooling >> 8; 80008b6: 4b4d ldr r3, [pc, #308] @ (80009ec ) 80008b8: 885b ldrh r3, [r3, #2] 80008ba: 0a1b lsrs r3, r3, #8 80008bc: b29b uxth r3, r3 80008be: b2db uxtb r3, r3 80008c0: 71bb strb r3, [r7, #6] data[3] = current_measurements_adc_val.ts_cooling & 0xFF; 80008c2: 4b4a ldr r3, [pc, #296] @ (80009ec ) 80008c4: 885b ldrh r3, [r3, #2] 80008c6: b2db uxtb r3, r3 80008c8: 71fb strb r3, [r7, #7] data[4] = current_measurements_adc_val.acu >> 8; 80008ca: 4b48 ldr r3, [pc, #288] @ (80009ec ) 80008cc: 88db ldrh r3, [r3, #6] 80008ce: 0a1b lsrs r3, r3, #8 80008d0: b29b uxth r3, r3 80008d2: b2db uxtb r3, r3 80008d4: 723b strb r3, [r7, #8] data[5] = current_measurements_adc_val.acu & 0xFF; 80008d6: 4b45 ldr r3, [pc, #276] @ (80009ec ) 80008d8: 88db ldrh r3, [r3, #6] 80008da: b2db uxtb r3, r3 80008dc: 727b strb r3, [r7, #9] data[6] = current_measurements_adc_val.epsc >> 8; 80008de: 4b43 ldr r3, [pc, #268] @ (80009ec ) 80008e0: 891b ldrh r3, [r3, #8] 80008e2: 0a1b lsrs r3, r3, #8 80008e4: b29b uxth r3, r3 80008e6: b2db uxtb r3, r3 80008e8: 72bb strb r3, [r7, #10] data[7] = current_measurements_adc_val.epsc & 0xFF; 80008ea: 4b40 ldr r3, [pc, #256] @ (80009ec ) 80008ec: 891b ldrh r3, [r3, #8] 80008ee: b2db uxtb r3, r3 80008f0: 72fb strb r3, [r7, #11] ftcan_transmit(CUR_CHANNELS_2_ID, data, 8); 80008f2: 1d3b adds r3, r7, #4 80008f4: 2208 movs r2, #8 80008f6: 4619 mov r1, r3 80008f8: 20cb movs r0, #203 @ 0xcb 80008fa: f000 f8e5 bl 8000ac8 break; 80008fe: e05e b.n 80009be case 2: data[0] = current_measurements_adc_val.ebs1 >> 8; 8000900: 4b3a ldr r3, [pc, #232] @ (80009ec ) 8000902: 8a9b ldrh r3, [r3, #20] 8000904: 0a1b lsrs r3, r3, #8 8000906: b29b uxth r3, r3 8000908: b2db uxtb r3, r3 800090a: 713b strb r3, [r7, #4] data[1] = current_measurements_adc_val.ebs1 & 0xFF; 800090c: 4b37 ldr r3, [pc, #220] @ (80009ec ) 800090e: 8a9b ldrh r3, [r3, #20] 8000910: b2db uxtb r3, r3 8000912: 717b strb r3, [r7, #5] data[2] = current_measurements_adc_val.ebs2 >> 8; 8000914: 4b35 ldr r3, [pc, #212] @ (80009ec ) 8000916: 8adb ldrh r3, [r3, #22] 8000918: 0a1b lsrs r3, r3, #8 800091a: b29b uxth r3, r3 800091c: b2db uxtb r3, r3 800091e: 71bb strb r3, [r7, #6] data[3] = current_measurements_adc_val.ebs2 & 0xFF; 8000920: 4b32 ldr r3, [pc, #200] @ (80009ec ) 8000922: 8adb ldrh r3, [r3, #22] 8000924: b2db uxtb r3, r3 8000926: 71fb strb r3, [r7, #7] data[4] = current_measurements_adc_val.ebs3 >> 8; 8000928: 4b30 ldr r3, [pc, #192] @ (80009ec ) 800092a: 8b1b ldrh r3, [r3, #24] 800092c: 0a1b lsrs r3, r3, #8 800092e: b29b uxth r3, r3 8000930: b2db uxtb r3, r3 8000932: 723b strb r3, [r7, #8] data[5] = current_measurements_adc_val.ebs3 & 0xFF; 8000934: 4b2d ldr r3, [pc, #180] @ (80009ec ) 8000936: 8b1b ldrh r3, [r3, #24] 8000938: b2db uxtb r3, r3 800093a: 727b strb r3, [r7, #9] data[6] = current_measurements_adc_val.drs >> 8; 800093c: 4b2b ldr r3, [pc, #172] @ (80009ec ) 800093e: 889b ldrh r3, [r3, #4] 8000940: 0a1b lsrs r3, r3, #8 8000942: b29b uxth r3, r3 8000944: b2db uxtb r3, r3 8000946: 72bb strb r3, [r7, #10] data[7] = current_measurements_adc_val.drs & 0xFF; 8000948: 4b28 ldr r3, [pc, #160] @ (80009ec ) 800094a: 889b ldrh r3, [r3, #4] 800094c: b2db uxtb r3, r3 800094e: 72fb strb r3, [r7, #11] ftcan_transmit(CUR_CHANNELS_3_ID, data, 8); 8000950: 1d3b adds r3, r7, #4 8000952: 2208 movs r2, #8 8000954: 4619 mov r1, r3 8000956: 20cc movs r0, #204 @ 0xcc 8000958: f000 f8b6 bl 8000ac8 break; 800095c: e02f b.n 80009be case 3: data[0] = current_measurements_adc_val.lidar >> 8; 800095e: 4b23 ldr r3, [pc, #140] @ (80009ec ) 8000960: 899b ldrh r3, [r3, #12] 8000962: 0a1b lsrs r3, r3, #8 8000964: b29b uxth r3, r3 8000966: b2db uxtb r3, r3 8000968: 713b strb r3, [r7, #4] data[1] = current_measurements_adc_val.lidar & 0xFF; 800096a: 4b20 ldr r3, [pc, #128] @ (80009ec ) 800096c: 899b ldrh r3, [r3, #12] 800096e: b2db uxtb r3, r3 8000970: 717b strb r3, [r7, #5] data[2] = current_measurements_adc_val.lvms_v >> 8; 8000972: 4b1e ldr r3, [pc, #120] @ (80009ec ) 8000974: 8b9b ldrh r3, [r3, #28] 8000976: 0a1b lsrs r3, r3, #8 8000978: b29b uxth r3, r3 800097a: b2db uxtb r3, r3 800097c: 71bb strb r3, [r7, #6] data[3] = current_measurements_adc_val.lvms_v & 0xFF; 800097e: 4b1b ldr r3, [pc, #108] @ (80009ec ) 8000980: 8b9b ldrh r3, [r3, #28] 8000982: b2db uxtb r3, r3 8000984: 71fb strb r3, [r7, #7] data[4] = current_measurements_adc_val.asms_v >> 8; 8000986: 4b19 ldr r3, [pc, #100] @ (80009ec ) 8000988: 8bdb ldrh r3, [r3, #30] 800098a: 0a1b lsrs r3, r3, #8 800098c: b29b uxth r3, r3 800098e: b2db uxtb r3, r3 8000990: 723b strb r3, [r7, #8] data[5] = current_measurements_adc_val.asms_v & 0xFF; 8000992: 4b16 ldr r3, [pc, #88] @ (80009ec ) 8000994: 8bdb ldrh r3, [r3, #30] 8000996: b2db uxtb r3, r3 8000998: 727b strb r3, [r7, #9] data[6] = current_measurements_adc_val.epsc_precharge >> 8; // not used (transmits 313) 800099a: 4b14 ldr r3, [pc, #80] @ (80009ec ) 800099c: 8b5b ldrh r3, [r3, #26] 800099e: 0a1b lsrs r3, r3, #8 80009a0: b29b uxth r3, r3 80009a2: b2db uxtb r3, r3 80009a4: 72bb strb r3, [r7, #10] data[7] = current_measurements_adc_val.epsc_precharge & 0xFF; // not used (transmits 313) 80009a6: 4b11 ldr r3, [pc, #68] @ (80009ec ) 80009a8: 8b5b ldrh r3, [r3, #26] 80009aa: b2db uxtb r3, r3 80009ac: 72fb strb r3, [r7, #11] ftcan_transmit(CUR_CHANNELS_4_ID, data, 8); 80009ae: 1d3b adds r3, r7, #4 80009b0: 2208 movs r2, #8 80009b2: 4619 mov r1, r3 80009b4: 20cd movs r0, #205 @ 0xcd 80009b6: f000 f887 bl 8000ac8 break; 80009ba: e000 b.n 80009be default: break; 80009bc: bf00 nop } additionaltxcounter = (additionaltxcounter + 1) % 4; 80009be: 4b0a ldr r3, [pc, #40] @ (80009e8 ) 80009c0: 781b ldrb r3, [r3, #0] 80009c2: 3301 adds r3, #1 80009c4: 425a negs r2, r3 80009c6: f003 0303 and.w r3, r3, #3 80009ca: f002 0203 and.w r2, r2, #3 80009ce: bf58 it pl 80009d0: 4253 negpl r3, r2 80009d2: b2da uxtb r2, r3 80009d4: 4b04 ldr r3, [pc, #16] @ (80009e8 ) 80009d6: 701a strb r2, [r3, #0] } 80009d8: bf00 nop 80009da: 3710 adds r7, #16 80009dc: 46bd mov sp, r7 80009de: bd80 pop {r7, pc} 80009e0: 200002e8 .word 0x200002e8 80009e4: 200002f0 .word 0x200002f0 80009e8: 2000002d .word 0x2000002d 80009ec: 20000098 .word 0x20000098 080009f0 : void can_error_report(){ 80009f0: b580 push {r7, lr} 80009f2: b082 sub sp, #8 80009f4: af00 add r7, sp, #0 uint8_t error_data[2]; error_data[0] = error.group1.group1; 80009f6: 4b08 ldr r3, [pc, #32] @ (8000a18 ) 80009f8: 781b ldrb r3, [r3, #0] 80009fa: 713b strb r3, [r7, #4] error_data[1] = error.group2.group2; 80009fc: 4b06 ldr r3, [pc, #24] @ (8000a18 ) 80009fe: 785b ldrb r3, [r3, #1] 8000a00: 717b strb r3, [r7, #5] ftcan_transmit(ERROR_ID, error_data, 2); 8000a02: 1d3b adds r3, r7, #4 8000a04: 2202 movs r2, #2 8000a06: 4619 mov r1, r3 8000a08: 20ce movs r0, #206 @ 0xce 8000a0a: f000 f85d bl 8000ac8 } 8000a0e: bf00 nop 8000a10: 3708 adds r7, #8 8000a12: 46bd mov sp, r7 8000a14: bd80 pop {r7, pc} 8000a16: bf00 nop 8000a18: 200002f4 .word 0x200002f4 08000a1c : void ftcan_msg_received_cb(uint16_t id, size_t datalen, const uint8_t* data){ 8000a1c: b580 push {r7, lr} 8000a1e: b084 sub sp, #16 8000a20: af00 add r7, sp, #0 8000a22: 4603 mov r3, r0 8000a24: 60b9 str r1, [r7, #8] 8000a26: 607a str r2, [r7, #4] 8000a28: 81fb strh r3, [r7, #14] canmsg_received = 1; 8000a2a: 4b13 ldr r3, [pc, #76] @ (8000a78 ) 8000a2c: 2201 movs r2, #1 8000a2e: 701a strb r2, [r3, #0] if((id == RX_STATUS_MSG_ID) && (datalen == 3)){ 8000a30: 89fb ldrh r3, [r7, #14] 8000a32: 2bc8 cmp r3, #200 @ 0xc8 8000a34: d110 bne.n 8000a58 8000a36: 68bb ldr r3, [r7, #8] 8000a38: 2b03 cmp r3, #3 8000a3a: d10d bne.n 8000a58 rxstate.iostatus.porta.porta = data[0]; 8000a3c: 687b ldr r3, [r7, #4] 8000a3e: 781a ldrb r2, [r3, #0] 8000a40: 4b0e ldr r3, [pc, #56] @ (8000a7c ) 8000a42: 701a strb r2, [r3, #0] rxstate.iostatus.portb.portb = data[1]; 8000a44: 687b ldr r3, [r7, #4] 8000a46: 3301 adds r3, #1 8000a48: 781a ldrb r2, [r3, #0] 8000a4a: 4b0c ldr r3, [pc, #48] @ (8000a7c ) 8000a4c: 705a strb r2, [r3, #1] rxstate.checksum = data[2]; 8000a4e: 687b ldr r3, [r7, #4] 8000a50: 3302 adds r3, #2 8000a52: 781a ldrb r2, [r3, #0] 8000a54: 4b09 ldr r3, [pc, #36] @ (8000a7c ) 8000a56: 709a strb r2, [r3, #2] } if (id == RX_STATUS_HEARTBEAT){ 8000a58: 89fb ldrh r3, [r7, #14] 8000a5a: 2bc7 cmp r3, #199 @ 0xc7 8000a5c: d107 bne.n 8000a6e lastheartbeat = HAL_GetTick(); 8000a5e: f001 fc51 bl 8002304 8000a62: 4603 mov r3, r0 8000a64: 4a06 ldr r2, [pc, #24] @ (8000a80 ) 8000a66: 6013 str r3, [r2, #0] inhibit_SDC = 0; 8000a68: 4b06 ldr r3, [pc, #24] @ (8000a84 ) 8000a6a: 2200 movs r2, #0 8000a6c: 601a str r2, [r3, #0] } } 8000a6e: bf00 nop 8000a70: 3710 adds r7, #16 8000a72: 46bd mov sp, r7 8000a74: bd80 pop {r7, pc} 8000a76: bf00 nop 8000a78: 2000002c .word 0x2000002c 8000a7c: 20000028 .word 0x20000028 8000a80: 200002ec .word 0x200002ec 8000a84: 200002f0 .word 0x200002f0 08000a88 : #include #if defined(FTCAN_IS_BXCAN) static CAN_HandleTypeDef *hcan; HAL_StatusTypeDef ftcan_init(CAN_HandleTypeDef *handle) { 8000a88: b580 push {r7, lr} 8000a8a: b084 sub sp, #16 8000a8c: af00 add r7, sp, #0 8000a8e: 6078 str r0, [r7, #4] hcan = handle; 8000a90: 4a0c ldr r2, [pc, #48] @ (8000ac4 ) 8000a92: 687b ldr r3, [r7, #4] 8000a94: 6013 str r3, [r2, #0] HAL_StatusTypeDef status = HAL_CAN_ActivateNotification(hcan, CAN_IT_RX_FIFO0_MSG_PENDING); 8000a96: 4b0b ldr r3, [pc, #44] @ (8000ac4 ) 8000a98: 681b ldr r3, [r3, #0] 8000a9a: 2102 movs r1, #2 8000a9c: 4618 mov r0, r3 8000a9e: f003 f9bc bl 8003e1a 8000aa2: 4603 mov r3, r0 8000aa4: 73fb strb r3, [r7, #15] if (status != HAL_OK) { 8000aa6: 7bfb ldrb r3, [r7, #15] 8000aa8: 2b00 cmp r3, #0 8000aaa: d001 beq.n 8000ab0 return status; 8000aac: 7bfb ldrb r3, [r7, #15] 8000aae: e005 b.n 8000abc } return HAL_CAN_Start(hcan); 8000ab0: 4b04 ldr r3, [pc, #16] @ (8000ac4 ) 8000ab2: 681b ldr r3, [r3, #0] 8000ab4: 4618 mov r0, r3 8000ab6: f002 ff7a bl 80039ae 8000aba: 4603 mov r3, r0 } 8000abc: 4618 mov r0, r3 8000abe: 3710 adds r7, #16 8000ac0: 46bd mov sp, r7 8000ac2: bd80 pop {r7, pc} 8000ac4: 20000030 .word 0x20000030 08000ac8 : HAL_StatusTypeDef ftcan_transmit(uint16_t id, const uint8_t *data, size_t datalen) { 8000ac8: b580 push {r7, lr} 8000aca: b086 sub sp, #24 8000acc: af00 add r7, sp, #0 8000ace: 4603 mov r3, r0 8000ad0: 60b9 str r1, [r7, #8] 8000ad2: 607a str r2, [r7, #4] 8000ad4: 81fb strh r3, [r7, #14] static CAN_TxHeaderTypeDef header; header.StdId = id; 8000ad6: 89fb ldrh r3, [r7, #14] 8000ad8: 4a0b ldr r2, [pc, #44] @ (8000b08 ) 8000ada: 6013 str r3, [r2, #0] header.IDE = CAN_ID_STD; 8000adc: 4b0a ldr r3, [pc, #40] @ (8000b08 ) 8000ade: 2200 movs r2, #0 8000ae0: 609a str r2, [r3, #8] header.RTR = CAN_RTR_DATA; 8000ae2: 4b09 ldr r3, [pc, #36] @ (8000b08 ) 8000ae4: 2200 movs r2, #0 8000ae6: 60da str r2, [r3, #12] header.DLC = datalen; 8000ae8: 4a07 ldr r2, [pc, #28] @ (8000b08 ) 8000aea: 687b ldr r3, [r7, #4] 8000aec: 6113 str r3, [r2, #16] uint32_t mailbox; return HAL_CAN_AddTxMessage(hcan, &header, data, &mailbox); 8000aee: 4b07 ldr r3, [pc, #28] @ (8000b0c ) 8000af0: 6818 ldr r0, [r3, #0] 8000af2: f107 0314 add.w r3, r7, #20 8000af6: 68ba ldr r2, [r7, #8] 8000af8: 4903 ldr r1, [pc, #12] @ (8000b08 ) 8000afa: f002 ff9c bl 8003a36 8000afe: 4603 mov r3, r0 } 8000b00: 4618 mov r0, r3 8000b02: 3718 adds r7, #24 8000b04: 46bd mov sp, r7 8000b06: bd80 pop {r7, pc} 8000b08: 20000034 .word 0x20000034 8000b0c: 20000030 .word 0x20000030 08000b10 : HAL_StatusTypeDef ftcan_add_filter(uint16_t id, uint16_t mask) { 8000b10: b580 push {r7, lr} 8000b12: b084 sub sp, #16 8000b14: af00 add r7, sp, #0 8000b16: 4603 mov r3, r0 8000b18: 460a mov r2, r1 8000b1a: 80fb strh r3, [r7, #6] 8000b1c: 4613 mov r3, r2 8000b1e: 80bb strh r3, [r7, #4] static uint32_t next_filter_no = 0; static CAN_FilterTypeDef filter; if (next_filter_no % 2 == 0) { 8000b20: 4b26 ldr r3, [pc, #152] @ (8000bbc ) 8000b22: 681b ldr r3, [r3, #0] 8000b24: f003 0301 and.w r3, r3, #1 8000b28: 2b00 cmp r3, #0 8000b2a: d110 bne.n 8000b4e filter.FilterIdHigh = id << 5; 8000b2c: 88fb ldrh r3, [r7, #6] 8000b2e: 015b lsls r3, r3, #5 8000b30: 4a23 ldr r2, [pc, #140] @ (8000bc0 ) 8000b32: 6013 str r3, [r2, #0] filter.FilterMaskIdHigh = mask << 5; 8000b34: 88bb ldrh r3, [r7, #4] 8000b36: 015b lsls r3, r3, #5 8000b38: 4a21 ldr r2, [pc, #132] @ (8000bc0 ) 8000b3a: 6093 str r3, [r2, #8] filter.FilterIdLow = id << 5; 8000b3c: 88fb ldrh r3, [r7, #6] 8000b3e: 015b lsls r3, r3, #5 8000b40: 4a1f ldr r2, [pc, #124] @ (8000bc0 ) 8000b42: 6053 str r3, [r2, #4] filter.FilterMaskIdLow = mask << 5; 8000b44: 88bb ldrh r3, [r7, #4] 8000b46: 015b lsls r3, r3, #5 8000b48: 4a1d ldr r2, [pc, #116] @ (8000bc0 ) 8000b4a: 60d3 str r3, [r2, #12] 8000b4c: e007 b.n 8000b5e } else { // Leave high filter untouched from the last configuration filter.FilterIdLow = id << 5; 8000b4e: 88fb ldrh r3, [r7, #6] 8000b50: 015b lsls r3, r3, #5 8000b52: 4a1b ldr r2, [pc, #108] @ (8000bc0 ) 8000b54: 6053 str r3, [r2, #4] filter.FilterMaskIdLow = mask << 5; 8000b56: 88bb ldrh r3, [r7, #4] 8000b58: 015b lsls r3, r3, #5 8000b5a: 4a19 ldr r2, [pc, #100] @ (8000bc0 ) 8000b5c: 60d3 str r3, [r2, #12] } filter.FilterFIFOAssignment = CAN_FILTER_FIFO0; 8000b5e: 4b18 ldr r3, [pc, #96] @ (8000bc0 ) 8000b60: 2200 movs r2, #0 8000b62: 611a str r2, [r3, #16] filter.FilterBank = next_filter_no / 2; 8000b64: 4b15 ldr r3, [pc, #84] @ (8000bbc ) 8000b66: 681b ldr r3, [r3, #0] 8000b68: 085b lsrs r3, r3, #1 8000b6a: 4a15 ldr r2, [pc, #84] @ (8000bc0 ) 8000b6c: 6153 str r3, [r2, #20] if (filter.FilterBank > FTCAN_NUM_FILTERS + 1) { 8000b6e: 4b14 ldr r3, [pc, #80] @ (8000bc0 ) 8000b70: 695b ldr r3, [r3, #20] 8000b72: 2b0e cmp r3, #14 8000b74: d901 bls.n 8000b7a return HAL_ERROR; 8000b76: 2301 movs r3, #1 8000b78: e01c b.n 8000bb4 } filter.FilterMode = CAN_FILTERMODE_IDMASK; 8000b7a: 4b11 ldr r3, [pc, #68] @ (8000bc0 ) 8000b7c: 2200 movs r2, #0 8000b7e: 619a str r2, [r3, #24] filter.FilterScale = CAN_FILTERSCALE_16BIT; 8000b80: 4b0f ldr r3, [pc, #60] @ (8000bc0 ) 8000b82: 2200 movs r2, #0 8000b84: 61da str r2, [r3, #28] filter.FilterActivation = CAN_FILTER_ENABLE; 8000b86: 4b0e ldr r3, [pc, #56] @ (8000bc0 ) 8000b88: 2201 movs r2, #1 8000b8a: 621a str r2, [r3, #32] // Disable slave filters // TODO: Some STM32 have multiple CAN peripherals, and one uses the slave // filter bank filter.SlaveStartFilterBank = FTCAN_NUM_FILTERS; 8000b8c: 4b0c ldr r3, [pc, #48] @ (8000bc0 ) 8000b8e: 220d movs r2, #13 8000b90: 625a str r2, [r3, #36] @ 0x24 HAL_StatusTypeDef status = HAL_CAN_ConfigFilter(hcan, &filter); 8000b92: 4b0c ldr r3, [pc, #48] @ (8000bc4 ) 8000b94: 681b ldr r3, [r3, #0] 8000b96: 490a ldr r1, [pc, #40] @ (8000bc0 ) 8000b98: 4618 mov r0, r3 8000b9a: f002 fe3e bl 800381a 8000b9e: 4603 mov r3, r0 8000ba0: 73fb strb r3, [r7, #15] if (status == HAL_OK) { 8000ba2: 7bfb ldrb r3, [r7, #15] 8000ba4: 2b00 cmp r3, #0 8000ba6: d104 bne.n 8000bb2 next_filter_no++; 8000ba8: 4b04 ldr r3, [pc, #16] @ (8000bbc ) 8000baa: 681b ldr r3, [r3, #0] 8000bac: 3301 adds r3, #1 8000bae: 4a03 ldr r2, [pc, #12] @ (8000bbc ) 8000bb0: 6013 str r3, [r2, #0] } return status; 8000bb2: 7bfb ldrb r3, [r7, #15] } 8000bb4: 4618 mov r0, r3 8000bb6: 3710 adds r7, #16 8000bb8: 46bd mov sp, r7 8000bba: bd80 pop {r7, pc} 8000bbc: 2000004c .word 0x2000004c 8000bc0: 20000050 .word 0x20000050 8000bc4: 20000030 .word 0x20000030 08000bc8 : void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *handle) { 8000bc8: b580 push {r7, lr} 8000bca: b08c sub sp, #48 @ 0x30 8000bcc: af00 add r7, sp, #0 8000bce: 6078 str r0, [r7, #4] if (handle != hcan) { 8000bd0: 4b12 ldr r3, [pc, #72] @ (8000c1c ) 8000bd2: 681b ldr r3, [r3, #0] 8000bd4: 687a ldr r2, [r7, #4] 8000bd6: 429a cmp r2, r3 8000bd8: d117 bne.n 8000c0a return; } CAN_RxHeaderTypeDef header; uint8_t data[8]; if (HAL_CAN_GetRxMessage(hcan, CAN_RX_FIFO0, &header, data) != HAL_OK) { 8000bda: 4b10 ldr r3, [pc, #64] @ (8000c1c ) 8000bdc: 6818 ldr r0, [r3, #0] 8000bde: f107 030c add.w r3, r7, #12 8000be2: f107 0214 add.w r2, r7, #20 8000be6: 2100 movs r1, #0 8000be8: f002 fff5 bl 8003bd6 8000bec: 4603 mov r3, r0 8000bee: 2b00 cmp r3, #0 8000bf0: d10d bne.n 8000c0e return; } if (header.IDE != CAN_ID_STD) { 8000bf2: 69fb ldr r3, [r7, #28] 8000bf4: 2b00 cmp r3, #0 8000bf6: d10c bne.n 8000c12 return; } ftcan_msg_received_cb(header.StdId, header.DLC, data); 8000bf8: 697b ldr r3, [r7, #20] 8000bfa: b29b uxth r3, r3 8000bfc: 6a79 ldr r1, [r7, #36] @ 0x24 8000bfe: f107 020c add.w r2, r7, #12 8000c02: 4618 mov r0, r3 8000c04: f7ff ff0a bl 8000a1c 8000c08: e004 b.n 8000c14 return; 8000c0a: bf00 nop 8000c0c: e002 b.n 8000c14 return; 8000c0e: bf00 nop 8000c10: e000 b.n 8000c14 return; 8000c12: bf00 nop } 8000c14: 3730 adds r7, #48 @ 0x30 8000c16: 46bd mov sp, r7 8000c18: bd80 pop {r7, pc} 8000c1a: bf00 nop 8000c1c: 20000030 .word 0x20000030 08000c20 : extern current_measurements current_measurements_adc_val; extern int inhibit_SDC; volatile int prev_epsc_state; void ChannelControl_init(){ 8000c20: b580 push {r7, lr} 8000c22: af00 add r7, sp, #0 update_ports.porta.porta = 0; 8000c24: 4b09 ldr r3, [pc, #36] @ (8000c4c ) 8000c26: 2200 movs r2, #0 8000c28: 701a strb r2, [r3, #0] update_ports.portb.portb = 0; 8000c2a: 4b08 ldr r3, [pc, #32] @ (8000c4c ) 8000c2c: 2200 movs r2, #0 8000c2e: 705a strb r2, [r3, #1] update_ports.portb.alwayson = 1; 8000c30: 4a06 ldr r2, [pc, #24] @ (8000c4c ) 8000c32: 7853 ldrb r3, [r2, #1] 8000c34: f043 0301 orr.w r3, r3, #1 8000c38: 7053 strb r3, [r2, #1] ChannelControl_UpdateGPIOs(update_ports); 8000c3a: 4b04 ldr r3, [pc, #16] @ (8000c4c ) 8000c3c: 8818 ldrh r0, [r3, #0] 8000c3e: f000 f809 bl 8000c54 prev_epsc_state = 0; 8000c42: 4b03 ldr r3, [pc, #12] @ (8000c50 ) 8000c44: 2200 movs r2, #0 8000c46: 601a str r2, [r3, #0] } 8000c48: bf00 nop 8000c4a: bd80 pop {r7, pc} 8000c4c: 200002e8 .word 0x200002e8 8000c50: 20000078 .word 0x20000078 08000c54 : void ChannelControl_UpdateGPIOs(enable_gpios UpdatePorts){ 8000c54: b580 push {r7, lr} 8000c56: b082 sub sp, #8 8000c58: af00 add r7, sp, #0 8000c5a: 80b8 strh r0, [r7, #4] UpdatePorts.portb.alwayson = 1; // ensure always on stays always on 8000c5c: 797b ldrb r3, [r7, #5] 8000c5e: f043 0301 orr.w r3, r3, #1 8000c62: 717b strb r3, [r7, #5] if (inhibit_SDC == 1){ 8000c64: 4b76 ldr r3, [pc, #472] @ (8000e40 ) 8000c66: 681b ldr r3, [r3, #0] 8000c68: 2b01 cmp r3, #1 8000c6a: d109 bne.n 8000c80 UpdatePorts.portb.sdc = 0; 8000c6c: 797b ldrb r3, [r7, #5] 8000c6e: f36f 0341 bfc r3, #1, #1 8000c72: 717b strb r3, [r7, #5] HAL_GPIO_WritePin(LED1_GPIO_Port, LED1_Pin, 1); 8000c74: 2201 movs r2, #1 8000c76: f44f 7100 mov.w r1, #512 @ 0x200 8000c7a: 4872 ldr r0, [pc, #456] @ (8000e44 ) 8000c7c: f003 ff60 bl 8004b40 } HAL_GPIO_WritePin(IN1_GPIO_Port, IN1_Pin, (GPIO_PinState)UpdatePorts.porta.acc_cooling); // Acc-Cooling 8000c80: 793b ldrb r3, [r7, #4] 8000c82: f3c3 0300 ubfx r3, r3, #0, #1 8000c86: b2db uxtb r3, r3 8000c88: 461a mov r2, r3 8000c8a: f44f 7100 mov.w r1, #512 @ 0x200 8000c8e: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 8000c92: f003 ff55 bl 8004b40 HAL_GPIO_WritePin(IN2_GPIO_Port, IN2_Pin, (GPIO_PinState)UpdatePorts.porta.ts_cooling); // TS-Cooling 8000c96: 793b ldrb r3, [r7, #4] 8000c98: f3c3 0340 ubfx r3, r3, #1, #1 8000c9c: b2db uxtb r3, r3 8000c9e: 461a mov r2, r3 8000ca0: f44f 7180 mov.w r1, #256 @ 0x100 8000ca4: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 8000ca8: f003 ff4a bl 8004b40 HAL_GPIO_WritePin(IN3_GPIO_Port, IN3_Pin, (GPIO_PinState)UpdatePorts.porta.drs); // DRS 8000cac: 793b ldrb r3, [r7, #4] 8000cae: f3c3 0380 ubfx r3, r3, #2, #1 8000cb2: b2db uxtb r3, r3 8000cb4: 461a mov r2, r3 8000cb6: f44f 5180 mov.w r1, #4096 @ 0x1000 8000cba: 4863 ldr r0, [pc, #396] @ (8000e48 ) 8000cbc: f003 ff40 bl 8004b40 HAL_GPIO_WritePin(IN4_GPIO_Port, IN4_Pin, (GPIO_PinState)UpdatePorts.porta.acu); // ACU 8000cc0: 793b ldrb r3, [r7, #4] 8000cc2: f3c3 03c0 ubfx r3, r3, #3, #1 8000cc6: b2db uxtb r3, r3 8000cc8: 461a mov r2, r3 8000cca: f44f 4100 mov.w r1, #32768 @ 0x8000 8000cce: 485e ldr r0, [pc, #376] @ (8000e48 ) 8000cd0: f003 ff36 bl 8004b40 if (prev_epsc_state == 0 && UpdatePorts.porta.epsc == 1){ 8000cd4: 4b5d ldr r3, [pc, #372] @ (8000e4c ) 8000cd6: 681b ldr r3, [r3, #0] 8000cd8: 2b00 cmp r3, #0 8000cda: d135 bne.n 8000d48 8000cdc: 793b ldrb r3, [r7, #4] 8000cde: f003 0310 and.w r3, r3, #16 8000ce2: b2db uxtb r3, r3 8000ce4: 2b00 cmp r3, #0 8000ce6: d02f beq.n 8000d48 HAL_GPIO_WritePin(PC_EN_GPIO_Port, PC_EN_Pin, 1); // enable precharge 8000ce8: 2201 movs r2, #1 8000cea: 2140 movs r1, #64 @ 0x40 8000cec: 4856 ldr r0, [pc, #344] @ (8000e48 ) 8000cee: f003 ff27 bl 8004b40 if (current_measurements_adc_val.epsc_precharge >= (0.95f * current_measurements_adc_val.asms_v)) { // check if precharge is complete (no while loop needed, this function is called by the main while-loop) 8000cf2: 4b57 ldr r3, [pc, #348] @ (8000e50 ) 8000cf4: 8b5b ldrh r3, [r3, #26] 8000cf6: ee07 3a90 vmov s15, r3 8000cfa: eeb8 7ae7 vcvt.f32.s32 s14, s15 8000cfe: 4b54 ldr r3, [pc, #336] @ (8000e50 ) 8000d00: 8bdb ldrh r3, [r3, #30] 8000d02: ee07 3a90 vmov s15, r3 8000d06: eef8 7ae7 vcvt.f32.s32 s15, s15 8000d0a: eddf 6a52 vldr s13, [pc, #328] @ 8000e54 8000d0e: ee67 7aa6 vmul.f32 s15, s15, s13 8000d12: eeb4 7ae7 vcmpe.f32 s14, s15 8000d16: eef1 fa10 vmrs APSR_nzcv, fpscr 8000d1a: db15 blt.n 8000d48 HAL_GPIO_WritePin(IN5_GPIO_Port, IN5_Pin, (GPIO_PinState)UpdatePorts.porta.epsc); // switch on PROFET 8000d1c: 793b ldrb r3, [r7, #4] 8000d1e: f3c3 1300 ubfx r3, r3, #4, #1 8000d22: b2db uxtb r3, r3 8000d24: 461a mov r2, r3 8000d26: f44f 4180 mov.w r1, #16384 @ 0x4000 8000d2a: 4847 ldr r0, [pc, #284] @ (8000e48 ) 8000d2c: f003 ff08 bl 8004b40 HAL_GPIO_WritePin(PC_EN_GPIO_Port, PC_EN_Pin, 0); // disengage precharge 8000d30: 2200 movs r2, #0 8000d32: 2140 movs r1, #64 @ 0x40 8000d34: 4844 ldr r0, [pc, #272] @ (8000e48 ) 8000d36: f003 ff03 bl 8004b40 prev_epsc_state = UpdatePorts.porta.epsc; 8000d3a: 793b ldrb r3, [r7, #4] 8000d3c: f3c3 1300 ubfx r3, r3, #4, #1 8000d40: b2db uxtb r3, r3 8000d42: 461a mov r2, r3 8000d44: 4b41 ldr r3, [pc, #260] @ (8000e4c ) 8000d46: 601a str r2, [r3, #0] } } if ((prev_epsc_state == 1 && UpdatePorts.porta.epsc == 0) || (prev_epsc_state == UpdatePorts.porta.epsc)){ 8000d48: 4b40 ldr r3, [pc, #256] @ (8000e4c ) 8000d4a: 681b ldr r3, [r3, #0] 8000d4c: 2b01 cmp r3, #1 8000d4e: d105 bne.n 8000d5c 8000d50: 793b ldrb r3, [r7, #4] 8000d52: f003 0310 and.w r3, r3, #16 8000d56: b2db uxtb r3, r3 8000d58: 2b00 cmp r3, #0 8000d5a: d008 beq.n 8000d6e 8000d5c: 793b ldrb r3, [r7, #4] 8000d5e: f3c3 1300 ubfx r3, r3, #4, #1 8000d62: b2db uxtb r3, r3 8000d64: 461a mov r2, r3 8000d66: 4b39 ldr r3, [pc, #228] @ (8000e4c ) 8000d68: 681b ldr r3, [r3, #0] 8000d6a: 429a cmp r2, r3 8000d6c: d115 bne.n 8000d9a HAL_GPIO_WritePin(PC_EN_GPIO_Port, PC_EN_Pin, 0); // ensure precharge is disabled, when not needed or stopped before completion 8000d6e: 2200 movs r2, #0 8000d70: 2140 movs r1, #64 @ 0x40 8000d72: 4835 ldr r0, [pc, #212] @ (8000e48 ) 8000d74: f003 fee4 bl 8004b40 HAL_GPIO_WritePin(IN5_GPIO_Port, IN5_Pin, (GPIO_PinState)UpdatePorts.porta.epsc); 8000d78: 793b ldrb r3, [r7, #4] 8000d7a: f3c3 1300 ubfx r3, r3, #4, #1 8000d7e: b2db uxtb r3, r3 8000d80: 461a mov r2, r3 8000d82: f44f 4180 mov.w r1, #16384 @ 0x4000 8000d86: 4830 ldr r0, [pc, #192] @ (8000e48 ) 8000d88: f003 feda bl 8004b40 prev_epsc_state = UpdatePorts.porta.epsc; 8000d8c: 793b ldrb r3, [r7, #4] 8000d8e: f3c3 1300 ubfx r3, r3, #4, #1 8000d92: b2db uxtb r3, r3 8000d94: 461a mov r2, r3 8000d96: 4b2d ldr r3, [pc, #180] @ (8000e4c ) 8000d98: 601a str r2, [r3, #0] } HAL_GPIO_WritePin(IN6_GPIO_Port, IN6_Pin, (GPIO_PinState)UpdatePorts.porta.inverter); // inverter 8000d9a: 793b ldrb r3, [r7, #4] 8000d9c: f3c3 1340 ubfx r3, r3, #5, #1 8000da0: b2db uxtb r3, r3 8000da2: 461a mov r2, r3 8000da4: f44f 6180 mov.w r1, #1024 @ 0x400 8000da8: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 8000dac: f003 fec8 bl 8004b40 HAL_GPIO_WritePin(IN7_GPIO_Port, IN7_Pin, (GPIO_PinState)UpdatePorts.porta.lidar); // lidar 8000db0: 793b ldrb r3, [r7, #4] 8000db2: f3c3 1380 ubfx r3, r3, #6, #1 8000db6: b2db uxtb r3, r3 8000db8: 461a mov r2, r3 8000dba: f44f 7180 mov.w r1, #256 @ 0x100 8000dbe: 4822 ldr r0, [pc, #136] @ (8000e48 ) 8000dc0: f003 febe bl 8004b40 HAL_GPIO_WritePin(IN8_GPIO_Port, IN8_Pin, (GPIO_PinState)UpdatePorts.porta.misc); // MISC 8000dc4: 793b ldrb r3, [r7, #4] 8000dc6: f3c3 13c0 ubfx r3, r3, #7, #1 8000dca: b2db uxtb r3, r3 8000dcc: 461a mov r2, r3 8000dce: f44f 5100 mov.w r1, #8192 @ 0x2000 8000dd2: 481d ldr r0, [pc, #116] @ (8000e48 ) 8000dd4: f003 feb4 bl 8004b40 HAL_GPIO_WritePin(IN9_GPIO_Port, IN9_Pin, (GPIO_PinState)UpdatePorts.portb.alwayson); // always on 8000dd8: 797b ldrb r3, [r7, #5] 8000dda: f3c3 0300 ubfx r3, r3, #0, #1 8000dde: b2db uxtb r3, r3 8000de0: 461a mov r2, r3 8000de2: f44f 6100 mov.w r1, #2048 @ 0x800 8000de6: 4818 ldr r0, [pc, #96] @ (8000e48 ) 8000de8: f003 feaa bl 8004b40 HAL_GPIO_WritePin(IN10_GPIO_Port, IN10_Pin, (GPIO_PinState)UpdatePorts.portb.sdc); // SDC 8000dec: 797b ldrb r3, [r7, #5] 8000dee: f3c3 0340 ubfx r3, r3, #1, #1 8000df2: b2db uxtb r3, r3 8000df4: 461a mov r2, r3 8000df6: f44f 7100 mov.w r1, #512 @ 0x200 8000dfa: 4813 ldr r0, [pc, #76] @ (8000e48 ) 8000dfc: f003 fea0 bl 8004b40 HAL_GPIO_WritePin(IN11_GPIO_Port, IN11_Pin, (GPIO_PinState)UpdatePorts.portb.ebs1); // EBS 1 8000e00: 797b ldrb r3, [r7, #5] 8000e02: f3c3 0380 ubfx r3, r3, #2, #1 8000e06: b2db uxtb r3, r3 8000e08: 461a mov r2, r3 8000e0a: 2104 movs r1, #4 8000e0c: 480e ldr r0, [pc, #56] @ (8000e48 ) 8000e0e: f003 fe97 bl 8004b40 HAL_GPIO_WritePin(IN12_GPIO_Port, IN12_Pin, (GPIO_PinState)UpdatePorts.portb.ebs2); // EBS 2 8000e12: 797b ldrb r3, [r7, #5] 8000e14: f3c3 03c0 ubfx r3, r3, #3, #1 8000e18: b2db uxtb r3, r3 8000e1a: 461a mov r2, r3 8000e1c: 2102 movs r1, #2 8000e1e: 480a ldr r0, [pc, #40] @ (8000e48 ) 8000e20: f003 fe8e bl 8004b40 HAL_GPIO_WritePin(IN13_GPIO_Port, IN13_Pin, (GPIO_PinState)UpdatePorts.portb.ebs3); // EBS 3 8000e24: 797b ldrb r3, [r7, #5] 8000e26: f3c3 1300 ubfx r3, r3, #4, #1 8000e2a: b2db uxtb r3, r3 8000e2c: 461a mov r2, r3 8000e2e: f44f 6180 mov.w r1, #1024 @ 0x400 8000e32: 4805 ldr r0, [pc, #20] @ (8000e48 ) 8000e34: f003 fe84 bl 8004b40 } 8000e38: bf00 nop 8000e3a: 3708 adds r7, #8 8000e3c: 46bd mov sp, r7 8000e3e: bd80 pop {r7, pc} 8000e40: 200002f0 .word 0x200002f0 8000e44: 48000800 .word 0x48000800 8000e48: 48000400 .word 0x48000400 8000e4c: 20000078 .word 0x20000078 8000e50: 20000098 .word 0x20000098 8000e54: 3f733333 .word 0x3f733333 08000e58 : GPIO_PinState valve3 = GPIO_PIN_RESET; ADC_HandleTypeDef* adc1; ADC_HandleTypeDef* adc2; void current_monitor_init(ADC_HandleTypeDef* hadc1, ADC_HandleTypeDef* hadc2, TIM_HandleTypeDef* trigtim) { 8000e58: b580 push {r7, lr} 8000e5a: b084 sub sp, #16 8000e5c: af00 add r7, sp, #0 8000e5e: 60f8 str r0, [r7, #12] 8000e60: 60b9 str r1, [r7, #8] 8000e62: 607a str r2, [r7, #4] HAL_GPIO_WritePin(DSEL0_GPIO_Port, DSEL0_Pin, valve3); 8000e64: 4b12 ldr r3, [pc, #72] @ (8000eb0 ) 8000e66: 781b ldrb r3, [r3, #0] 8000e68: 461a mov r2, r3 8000e6a: 2110 movs r1, #16 8000e6c: 4811 ldr r0, [pc, #68] @ (8000eb4 ) 8000e6e: f003 fe67 bl 8004b40 HAL_GPIO_WritePin(DSEL1_GPIO_Port, DSEL1_Pin, valve2); 8000e72: 4b11 ldr r3, [pc, #68] @ (8000eb8 ) 8000e74: 781b ldrb r3, [r3, #0] 8000e76: 461a mov r2, r3 8000e78: 2120 movs r1, #32 8000e7a: 480e ldr r0, [pc, #56] @ (8000eb4 ) 8000e7c: f003 fe60 bl 8004b40 adc1 = hadc1; 8000e80: 4a0e ldr r2, [pc, #56] @ (8000ebc ) 8000e82: 68fb ldr r3, [r7, #12] 8000e84: 6013 str r3, [r2, #0] adc2 = hadc2; 8000e86: 4a0e ldr r2, [pc, #56] @ (8000ec0 ) 8000e88: 68bb ldr r3, [r7, #8] 8000e8a: 6013 str r3, [r2, #0] HAL_TIM_Base_Start(trigtim); 8000e8c: 6878 ldr r0, [r7, #4] 8000e8e: f005 fab9 bl 8006404 HAL_ADC_Start_DMA(hadc1, (uint32_t*)adc_channels1.adcbuffer, 8); 8000e92: 2208 movs r2, #8 8000e94: 490b ldr r1, [pc, #44] @ (8000ec4 ) 8000e96: 68f8 ldr r0, [r7, #12] 8000e98: f001 fc14 bl 80026c4 HAL_ADC_Start_DMA(hadc2, (uint32_t*)adc_channels2.adcbuffer, 6); 8000e9c: 2206 movs r2, #6 8000e9e: 490a ldr r1, [pc, #40] @ (8000ec8 ) 8000ea0: 68b8 ldr r0, [r7, #8] 8000ea2: f001 fc0f bl 80026c4 } 8000ea6: bf00 nop 8000ea8: 3710 adds r7, #16 8000eaa: 46bd mov sp, r7 8000eac: bd80 pop {r7, pc} 8000eae: bf00 nop 8000eb0: 200000b9 .word 0x200000b9 8000eb4: 48000400 .word 0x48000400 8000eb8: 200000b8 .word 0x200000b8 8000ebc: 200000bc .word 0x200000bc 8000ec0: 200000c0 .word 0x200000c0 8000ec4: 2000007c .word 0x2000007c 8000ec8: 2000008c .word 0x2000008c 08000ecc : uint8_t current_monitor_checklimits() {return 0;} // TODO: implement properly 8000ecc: b480 push {r7} 8000ece: af00 add r7, sp, #0 8000ed0: 2300 movs r3, #0 8000ed2: 4618 mov r0, r3 8000ed4: 46bd mov sp, r7 8000ed6: f85d 7b04 ldr.w r7, [sp], #4 8000eda: 4770 bx lr 8000edc: 0000 movs r0, r0 ... 08000ee0 : void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) { 8000ee0: b580 push {r7, lr} 8000ee2: b082 sub sp, #8 8000ee4: af00 add r7, sp, #0 8000ee6: 6078 str r0, [r7, #4] if (hadc == adc1){ 8000ee8: 4b30 ldr r3, [pc, #192] @ (8000fac ) 8000eea: 681b ldr r3, [r3, #0] 8000eec: 687a ldr r2, [r7, #4] 8000eee: 429a cmp r2, r3 8000ef0: d168 bne.n 8000fc4 if (valve2 == GPIO_PIN_RESET && valve3 == GPIO_PIN_RESET){ 8000ef2: 4b2f ldr r3, [pc, #188] @ (8000fb0 ) 8000ef4: 781b ldrb r3, [r3, #0] 8000ef6: 2b00 cmp r3, #0 8000ef8: d118 bne.n 8000f2c 8000efa: 4b2e ldr r3, [pc, #184] @ (8000fb4 ) 8000efc: 781b ldrb r3, [r3, #0] 8000efe: 2b00 cmp r3, #0 8000f00: d114 bne.n 8000f2c current_measurements_adc_val.ebs1 = adc_channels1.adcbank1.isense11 * CURR_SENSE_FACTOR_1A; 8000f02: 4b2d ldr r3, [pc, #180] @ (8000fb8 ) 8000f04: 881b ldrh r3, [r3, #0] 8000f06: b29b uxth r3, r3 8000f08: ee07 3a90 vmov s15, r3 8000f0c: eef8 7ae7 vcvt.f32.s32 s15, s15 8000f10: ed9f 7a2a vldr s14, [pc, #168] @ 8000fbc 8000f14: ee67 7a87 vmul.f32 s15, s15, s14 8000f18: eefc 7ae7 vcvt.u32.f32 s15, s15 8000f1c: ee17 3a90 vmov r3, s15 8000f20: b29a uxth r2, r3 8000f22: 4b27 ldr r3, [pc, #156] @ (8000fc0 ) 8000f24: 829a strh r2, [r3, #20] valve2 = GPIO_PIN_SET; 8000f26: 4b22 ldr r3, [pc, #136] @ (8000fb0 ) 8000f28: 2201 movs r2, #1 8000f2a: 701a strb r2, [r3, #0] } if (valve2 == GPIO_PIN_SET && valve3 == GPIO_PIN_RESET){ 8000f2c: 4b20 ldr r3, [pc, #128] @ (8000fb0 ) 8000f2e: 781b ldrb r3, [r3, #0] 8000f30: 2b01 cmp r3, #1 8000f32: d11b bne.n 8000f6c 8000f34: 4b1f ldr r3, [pc, #124] @ (8000fb4 ) 8000f36: 781b ldrb r3, [r3, #0] 8000f38: 2b00 cmp r3, #0 8000f3a: d117 bne.n 8000f6c current_measurements_adc_val.ebs2 = adc_channels1.adcbank1.isense11 * CURR_SENSE_FACTOR_1A; 8000f3c: 4b1e ldr r3, [pc, #120] @ (8000fb8 ) 8000f3e: 881b ldrh r3, [r3, #0] 8000f40: b29b uxth r3, r3 8000f42: ee07 3a90 vmov s15, r3 8000f46: eef8 7ae7 vcvt.f32.s32 s15, s15 8000f4a: ed9f 7a1c vldr s14, [pc, #112] @ 8000fbc 8000f4e: ee67 7a87 vmul.f32 s15, s15, s14 8000f52: eefc 7ae7 vcvt.u32.f32 s15, s15 8000f56: ee17 3a90 vmov r3, s15 8000f5a: b29a uxth r2, r3 8000f5c: 4b18 ldr r3, [pc, #96] @ (8000fc0 ) 8000f5e: 82da strh r2, [r3, #22] valve2 = GPIO_PIN_RESET; 8000f60: 4b13 ldr r3, [pc, #76] @ (8000fb0 ) 8000f62: 2200 movs r2, #0 8000f64: 701a strb r2, [r3, #0] valve3 = GPIO_PIN_SET; 8000f66: 4b13 ldr r3, [pc, #76] @ (8000fb4 ) 8000f68: 2201 movs r2, #1 8000f6a: 701a strb r2, [r3, #0] } if (valve2 == GPIO_PIN_RESET && valve3 == GPIO_PIN_SET){ 8000f6c: 4b10 ldr r3, [pc, #64] @ (8000fb0 ) 8000f6e: 781b ldrb r3, [r3, #0] 8000f70: 2b00 cmp r3, #0 8000f72: f040 80b9 bne.w 80010e8 8000f76: 4b0f ldr r3, [pc, #60] @ (8000fb4 ) 8000f78: 781b ldrb r3, [r3, #0] 8000f7a: 2b01 cmp r3, #1 8000f7c: f040 80b4 bne.w 80010e8 current_measurements_adc_val.ebs3 = adc_channels1.adcbank1.isense11 * CURR_SENSE_FACTOR_1A; 8000f80: 4b0d ldr r3, [pc, #52] @ (8000fb8 ) 8000f82: 881b ldrh r3, [r3, #0] 8000f84: b29b uxth r3, r3 8000f86: ee07 3a90 vmov s15, r3 8000f8a: eef8 7ae7 vcvt.f32.s32 s15, s15 8000f8e: ed9f 7a0b vldr s14, [pc, #44] @ 8000fbc 8000f92: ee67 7a87 vmul.f32 s15, s15, s14 8000f96: eefc 7ae7 vcvt.u32.f32 s15, s15 8000f9a: ee17 3a90 vmov r3, s15 8000f9e: b29a uxth r2, r3 8000fa0: 4b07 ldr r3, [pc, #28] @ (8000fc0 ) 8000fa2: 831a strh r2, [r3, #24] valve3 = GPIO_PIN_RESET; 8000fa4: 4b03 ldr r3, [pc, #12] @ (8000fb4 ) 8000fa6: 2200 movs r2, #0 8000fa8: 701a strb r2, [r3, #0] 8000faa: e09d b.n 80010e8 8000fac: 200000bc .word 0x200000bc 8000fb0: 200000b8 .word 0x200000b8 8000fb4: 200000b9 .word 0x200000b9 8000fb8: 2000007c .word 0x2000007c 8000fbc: 3d778f79 .word 0x3d778f79 8000fc0: 20000098 .word 0x20000098 } } else { current_measurements_adc_val.lvms_v = adc_channels1.adcbank1.lvms_vsense * LV_SENSE_FACTOR; 8000fc4: 4b88 ldr r3, [pc, #544] @ (80011e8 ) 8000fc6: 885b ldrh r3, [r3, #2] 8000fc8: b29b uxth r3, r3 8000fca: 4618 mov r0, r3 8000fcc: f7ff fb78 bl 80006c0 <__aeabi_i2d> 8000fd0: a383 add r3, pc, #524 @ (adr r3, 80011e0 ) 8000fd2: e9d3 2300 ldrd r2, r3, [r3] 8000fd6: f7ff f8f7 bl 80001c8 <__aeabi_dmul> 8000fda: 4602 mov r2, r0 8000fdc: 460b mov r3, r1 8000fde: 4610 mov r0, r2 8000fe0: 4619 mov r1, r3 8000fe2: f7ff fbd7 bl 8000794 <__aeabi_d2uiz> 8000fe6: 4603 mov r3, r0 8000fe8: b29a uxth r2, r3 8000fea: 4b80 ldr r3, [pc, #512] @ (80011ec ) 8000fec: 839a strh r2, [r3, #28] current_measurements_adc_val.acc_cooling = adc_channels1.adcbank1.isense1 * CURR_SENSE_FACTOR_9A; 8000fee: 4b7e ldr r3, [pc, #504] @ (80011e8 ) 8000ff0: 889b ldrh r3, [r3, #4] 8000ff2: b29b uxth r3, r3 8000ff4: ee07 3a90 vmov s15, r3 8000ff8: eef8 7ae7 vcvt.f32.s32 s15, s15 8000ffc: ed9f 7a7c vldr s14, [pc, #496] @ 80011f0 8001000: ee67 7a87 vmul.f32 s15, s15, s14 8001004: eefc 7ae7 vcvt.u32.f32 s15, s15 8001008: ee17 3a90 vmov r3, s15 800100c: b29a uxth r2, r3 800100e: 4b77 ldr r3, [pc, #476] @ (80011ec ) 8001010: 801a strh r2, [r3, #0] current_measurements_adc_val.ts_cooling = adc_channels1.adcbank1.isense2 * CURR_SENSE_FACTOR_9A; 8001012: 4b75 ldr r3, [pc, #468] @ (80011e8 ) 8001014: 88db ldrh r3, [r3, #6] 8001016: b29b uxth r3, r3 8001018: ee07 3a90 vmov s15, r3 800101c: eef8 7ae7 vcvt.f32.s32 s15, s15 8001020: ed9f 7a73 vldr s14, [pc, #460] @ 80011f0 8001024: ee67 7a87 vmul.f32 s15, s15, s14 8001028: eefc 7ae7 vcvt.u32.f32 s15, s15 800102c: ee17 3a90 vmov r3, s15 8001030: b29a uxth r2, r3 8001032: 4b6e ldr r3, [pc, #440] @ (80011ec ) 8001034: 805a strh r2, [r3, #2] current_measurements_adc_val.alwayson = adc_channels1.adcbank1.isense9 * CURR_SENSE_FACTOR_9A; 8001036: 4b6c ldr r3, [pc, #432] @ (80011e8 ) 8001038: 891b ldrh r3, [r3, #8] 800103a: b29b uxth r3, r3 800103c: ee07 3a90 vmov s15, r3 8001040: eef8 7ae7 vcvt.f32.s32 s15, s15 8001044: ed9f 7a6a vldr s14, [pc, #424] @ 80011f0 8001048: ee67 7a87 vmul.f32 s15, s15, s14 800104c: eefc 7ae7 vcvt.u32.f32 s15, s15 8001050: ee17 3a90 vmov r3, s15 8001054: b29a uxth r2, r3 8001056: 4b65 ldr r3, [pc, #404] @ (80011ec ) 8001058: 821a strh r2, [r3, #16] current_measurements_adc_val.asms_v = adc_channels1.adcbank1.asms_vsense * LV_SENSE_FACTOR; 800105a: 4b63 ldr r3, [pc, #396] @ (80011e8 ) 800105c: 895b ldrh r3, [r3, #10] 800105e: b29b uxth r3, r3 8001060: 4618 mov r0, r3 8001062: f7ff fb2d bl 80006c0 <__aeabi_i2d> 8001066: a35e add r3, pc, #376 @ (adr r3, 80011e0 ) 8001068: e9d3 2300 ldrd r2, r3, [r3] 800106c: f7ff f8ac bl 80001c8 <__aeabi_dmul> 8001070: 4602 mov r2, r0 8001072: 460b mov r3, r1 8001074: 4610 mov r0, r2 8001076: 4619 mov r1, r3 8001078: f7ff fb8c bl 8000794 <__aeabi_d2uiz> 800107c: 4603 mov r3, r0 800107e: b29a uxth r2, r3 8001080: 4b5a ldr r3, [pc, #360] @ (80011ec ) 8001082: 83da strh r2, [r3, #30] current_measurements_adc_val.sdc = adc_channels1.adcbank1.isense10 * CURR_SENSE_FACTOR_4_5A; 8001084: 4b58 ldr r3, [pc, #352] @ (80011e8 ) 8001086: 899b ldrh r3, [r3, #12] 8001088: b29b uxth r3, r3 800108a: ee07 3a90 vmov s15, r3 800108e: eef8 7ae7 vcvt.f32.s32 s15, s15 8001092: ed9f 7a58 vldr s14, [pc, #352] @ 80011f4 8001096: ee67 7a87 vmul.f32 s15, s15, s14 800109a: eefc 7ae7 vcvt.u32.f32 s15, s15 800109e: ee17 3a90 vmov r3, s15 80010a2: b29a uxth r2, r3 80010a4: 4b51 ldr r3, [pc, #324] @ (80011ec ) 80010a6: 825a strh r2, [r3, #18] current_measurements_adc_val.inverter = adc_channels1.adcbank1.isense6 * CURR_SENSE_FACTOR_9A; 80010a8: 4b4f ldr r3, [pc, #316] @ (80011e8 ) 80010aa: 89db ldrh r3, [r3, #14] 80010ac: b29b uxth r3, r3 80010ae: ee07 3a90 vmov s15, r3 80010b2: eef8 7ae7 vcvt.f32.s32 s15, s15 80010b6: ed9f 7a4e vldr s14, [pc, #312] @ 80011f0 80010ba: ee67 7a87 vmul.f32 s15, s15, s14 80010be: eefc 7ae7 vcvt.u32.f32 s15, s15 80010c2: ee17 3a90 vmov r3, s15 80010c6: b29a uxth r2, r3 80010c8: 4b48 ldr r3, [pc, #288] @ (80011ec ) 80010ca: 815a strh r2, [r3, #10] HAL_GPIO_WritePin(DSEL0_GPIO_Port, DSEL0_Pin, valve3); 80010cc: 4b4a ldr r3, [pc, #296] @ (80011f8 ) 80010ce: 781b ldrb r3, [r3, #0] 80010d0: 461a mov r2, r3 80010d2: 2110 movs r1, #16 80010d4: 4849 ldr r0, [pc, #292] @ (80011fc ) 80010d6: f003 fd33 bl 8004b40 HAL_GPIO_WritePin(DSEL1_GPIO_Port, DSEL1_Pin, valve2); 80010da: 4b49 ldr r3, [pc, #292] @ (8001200 ) 80010dc: 781b ldrb r3, [r3, #0] 80010de: 461a mov r2, r3 80010e0: 2120 movs r1, #32 80010e2: 4846 ldr r0, [pc, #280] @ (80011fc ) 80010e4: f003 fd2c bl 8004b40 } if (hadc == adc2){ 80010e8: 4b46 ldr r3, [pc, #280] @ (8001204 ) 80010ea: 681b ldr r3, [r3, #0] 80010ec: 687a ldr r2, [r7, #4] 80010ee: 429a cmp r2, r3 80010f0: d16e bne.n 80011d0 current_measurements_adc_val.drs = adc_channels2.adcbank2.isense3 * CURR_SENSE_FACTOR_4_5A; 80010f2: 4b45 ldr r3, [pc, #276] @ (8001208 ) 80010f4: 881b ldrh r3, [r3, #0] 80010f6: b29b uxth r3, r3 80010f8: ee07 3a90 vmov s15, r3 80010fc: eef8 7ae7 vcvt.f32.s32 s15, s15 8001100: ed9f 7a3c vldr s14, [pc, #240] @ 80011f4 8001104: ee67 7a87 vmul.f32 s15, s15, s14 8001108: eefc 7ae7 vcvt.u32.f32 s15, s15 800110c: ee17 3a90 vmov r3, s15 8001110: b29a uxth r2, r3 8001112: 4b36 ldr r3, [pc, #216] @ (80011ec ) 8001114: 809a strh r2, [r3, #4] current_measurements_adc_val.misc = adc_channels2.adcbank2.isense8 * CURR_SENSE_FACTOR_4_5A; 8001116: 4b3c ldr r3, [pc, #240] @ (8001208 ) 8001118: 885b ldrh r3, [r3, #2] 800111a: b29b uxth r3, r3 800111c: ee07 3a90 vmov s15, r3 8001120: eef8 7ae7 vcvt.f32.s32 s15, s15 8001124: ed9f 7a33 vldr s14, [pc, #204] @ 80011f4 8001128: ee67 7a87 vmul.f32 s15, s15, s14 800112c: eefc 7ae7 vcvt.u32.f32 s15, s15 8001130: ee17 3a90 vmov r3, s15 8001134: b29a uxth r2, r3 8001136: 4b2d ldr r3, [pc, #180] @ (80011ec ) 8001138: 81da strh r2, [r3, #14] current_measurements_adc_val.acu = adc_channels2.adcbank2.isense4 * CURR_SENSE_FACTOR_9A; 800113a: 4b33 ldr r3, [pc, #204] @ (8001208 ) 800113c: 889b ldrh r3, [r3, #4] 800113e: b29b uxth r3, r3 8001140: ee07 3a90 vmov s15, r3 8001144: eef8 7ae7 vcvt.f32.s32 s15, s15 8001148: ed9f 7a29 vldr s14, [pc, #164] @ 80011f0 800114c: ee67 7a87 vmul.f32 s15, s15, s14 8001150: eefc 7ae7 vcvt.u32.f32 s15, s15 8001154: ee17 3a90 vmov r3, s15 8001158: b29a uxth r2, r3 800115a: 4b24 ldr r3, [pc, #144] @ (80011ec ) 800115c: 80da strh r2, [r3, #6] current_measurements_adc_val.epsc = adc_channels2.adcbank2.isense5 * CURR_SENSE_FACTOR_9A; 800115e: 4b2a ldr r3, [pc, #168] @ (8001208 ) 8001160: 88db ldrh r3, [r3, #6] 8001162: b29b uxth r3, r3 8001164: ee07 3a90 vmov s15, r3 8001168: eef8 7ae7 vcvt.f32.s32 s15, s15 800116c: ed9f 7a20 vldr s14, [pc, #128] @ 80011f0 8001170: ee67 7a87 vmul.f32 s15, s15, s14 8001174: eefc 7ae7 vcvt.u32.f32 s15, s15 8001178: ee17 3a90 vmov r3, s15 800117c: b29a uxth r2, r3 800117e: 4b1b ldr r3, [pc, #108] @ (80011ec ) 8001180: 811a strh r2, [r3, #8] current_measurements_adc_val.epsc_precharge = adc_channels2.adcbank2.pc_read * LV_SENSE_FACTOR; 8001182: 4b21 ldr r3, [pc, #132] @ (8001208 ) 8001184: 891b ldrh r3, [r3, #8] 8001186: b29b uxth r3, r3 8001188: 4618 mov r0, r3 800118a: f7ff fa99 bl 80006c0 <__aeabi_i2d> 800118e: a314 add r3, pc, #80 @ (adr r3, 80011e0 ) 8001190: e9d3 2300 ldrd r2, r3, [r3] 8001194: f7ff f818 bl 80001c8 <__aeabi_dmul> 8001198: 4602 mov r2, r0 800119a: 460b mov r3, r1 800119c: 4610 mov r0, r2 800119e: 4619 mov r1, r3 80011a0: f7ff faf8 bl 8000794 <__aeabi_d2uiz> 80011a4: 4603 mov r3, r0 80011a6: b29a uxth r2, r3 80011a8: 4b10 ldr r3, [pc, #64] @ (80011ec ) 80011aa: 835a strh r2, [r3, #26] current_measurements_adc_val.lidar = adc_channels2.adcbank2.isense7 * CURR_SENSE_FACTOR_4_5A; 80011ac: 4b16 ldr r3, [pc, #88] @ (8001208 ) 80011ae: 895b ldrh r3, [r3, #10] 80011b0: b29b uxth r3, r3 80011b2: ee07 3a90 vmov s15, r3 80011b6: eef8 7ae7 vcvt.f32.s32 s15, s15 80011ba: ed9f 7a0e vldr s14, [pc, #56] @ 80011f4 80011be: ee67 7a87 vmul.f32 s15, s15, s14 80011c2: eefc 7ae7 vcvt.u32.f32 s15, s15 80011c6: ee17 3a90 vmov r3, s15 80011ca: b29a uxth r2, r3 80011cc: 4b07 ldr r3, [pc, #28] @ (80011ec ) 80011ce: 819a strh r2, [r3, #12] } check_plausibility(); 80011d0: f000 fc3a bl 8001a48 } 80011d4: bf00 nop 80011d6: 3708 adds r7, #8 80011d8: 46bd mov sp, r7 80011da: bd80 pop {r7, pc} 80011dc: f3af 8000 nop.w 80011e0: a56db813 .word 0xa56db813 80011e4: 401a0c2d .word 0x401a0c2d 80011e8: 2000007c .word 0x2000007c 80011ec: 20000098 .word 0x20000098 80011f0: 40279e79 .word 0x40279e79 80011f4: 3f9ab9ab .word 0x3f9ab9ab 80011f8: 200000b9 .word 0x200000b9 80011fc: 48000400 .word 0x48000400 8001200: 200000b8 .word 0x200000b8 8001204: 200000c0 .word 0x200000c0 8001208: 2000008c .word 0x2000008c 0800120c
: /** * @brief The application entry point. * @retval int */ int main(void) { 800120c: b580 push {r7, lr} 800120e: b082 sub sp, #8 8001210: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 8001212: f001 f81d bl 8002250 /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 8001216: f000 f8e5 bl 80013e4 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 800121a: f000 fb89 bl 8001930 MX_DMA_Init(); 800121e: f000 fb55 bl 80018cc MX_ADC1_Init(); 8001222: f000 f93b bl 800149c MX_ADC2_Init(); 8001226: f000 fa0d bl 8001644 MX_CAN_Init(); 800122a: f000 fab1 bl 8001790 MX_UART4_Init(); 800122e: f000 fb1d bl 800186c MX_TIM6_Init(); 8001232: f000 fae3 bl 80017fc /* USER CODE BEGIN 2 */ ChannelControl_init(); 8001236: f7ff fcf3 bl 8000c20 can_init(&hcan); 800123a: 4860 ldr r0, [pc, #384] @ (80013bc ) 800123c: f7ff faca bl 80007d4 current_monitor_init(&hadc1, &hadc2, &htim6); 8001240: 4a5f ldr r2, [pc, #380] @ (80013c0 ) 8001242: 4960 ldr r1, [pc, #384] @ (80013c4 ) 8001244: 4860 ldr r0, [pc, #384] @ (80013c8 ) 8001246: f7ff fe07 bl 8000e58 // begin start-up animation HAL_GPIO_WritePin(LED1_GPIO_Port, LED1_Pin, GPIO_PIN_SET); 800124a: 2201 movs r2, #1 800124c: f44f 7100 mov.w r1, #512 @ 0x200 8001250: 485e ldr r0, [pc, #376] @ (80013cc ) 8001252: f003 fc75 bl 8004b40 HAL_Delay(100); 8001256: 2064 movs r0, #100 @ 0x64 8001258: f001 f860 bl 800231c HAL_GPIO_WritePin(LED1_GPIO_Port, LED1_Pin, GPIO_PIN_RESET); 800125c: 2200 movs r2, #0 800125e: f44f 7100 mov.w r1, #512 @ 0x200 8001262: 485a ldr r0, [pc, #360] @ (80013cc ) 8001264: f003 fc6c bl 8004b40 HAL_GPIO_WritePin(LED2_GPIO_Port, LED2_Pin, GPIO_PIN_SET); 8001268: 2201 movs r2, #1 800126a: f44f 7180 mov.w r1, #256 @ 0x100 800126e: 4857 ldr r0, [pc, #348] @ (80013cc ) 8001270: f003 fc66 bl 8004b40 HAL_Delay(100); 8001274: 2064 movs r0, #100 @ 0x64 8001276: f001 f851 bl 800231c HAL_GPIO_WritePin(LED2_GPIO_Port, LED2_Pin, GPIO_PIN_RESET); 800127a: 2200 movs r2, #0 800127c: f44f 7180 mov.w r1, #256 @ 0x100 8001280: 4852 ldr r0, [pc, #328] @ (80013cc ) 8001282: f003 fc5d bl 8004b40 HAL_GPIO_WritePin(LED3_GPIO_Port, LED3_Pin, GPIO_PIN_SET); 8001286: 2201 movs r2, #1 8001288: 2180 movs r1, #128 @ 0x80 800128a: 4850 ldr r0, [pc, #320] @ (80013cc ) 800128c: f003 fc58 bl 8004b40 HAL_Delay(100); 8001290: 2064 movs r0, #100 @ 0x64 8001292: f001 f843 bl 800231c HAL_GPIO_WritePin(LED3_GPIO_Port, LED3_Pin, GPIO_PIN_RESET); 8001296: 2200 movs r2, #0 8001298: 2180 movs r1, #128 @ 0x80 800129a: 484c ldr r0, [pc, #304] @ (80013cc ) 800129c: f003 fc50 bl 8004b40 HAL_GPIO_WritePin(LED4_GPIO_Port, LED4_Pin, GPIO_PIN_SET); 80012a0: 2201 movs r2, #1 80012a2: 2140 movs r1, #64 @ 0x40 80012a4: 4849 ldr r0, [pc, #292] @ (80013cc ) 80012a6: f003 fc4b bl 8004b40 HAL_Delay(100); 80012aa: 2064 movs r0, #100 @ 0x64 80012ac: f001 f836 bl 800231c HAL_GPIO_WritePin(LED4_GPIO_Port, LED3_Pin, GPIO_PIN_SET); 80012b0: 2201 movs r2, #1 80012b2: 2180 movs r1, #128 @ 0x80 80012b4: 4845 ldr r0, [pc, #276] @ (80013cc ) 80012b6: f003 fc43 bl 8004b40 HAL_Delay(100); 80012ba: 2064 movs r0, #100 @ 0x64 80012bc: f001 f82e bl 800231c HAL_GPIO_WritePin(LED2_GPIO_Port, LED2_Pin, GPIO_PIN_SET); 80012c0: 2201 movs r2, #1 80012c2: f44f 7180 mov.w r1, #256 @ 0x100 80012c6: 4841 ldr r0, [pc, #260] @ (80013cc ) 80012c8: f003 fc3a bl 8004b40 HAL_Delay(100); 80012cc: 2064 movs r0, #100 @ 0x64 80012ce: f001 f825 bl 800231c HAL_GPIO_WritePin(LED1_GPIO_Port, LED1_Pin, GPIO_PIN_SET); 80012d2: 2201 movs r2, #1 80012d4: f44f 7100 mov.w r1, #512 @ 0x200 80012d8: 483c ldr r0, [pc, #240] @ (80013cc ) 80012da: f003 fc31 bl 8004b40 HAL_Delay(100); 80012de: 2064 movs r0, #100 @ 0x64 80012e0: f001 f81c bl 800231c HAL_GPIO_WritePin(LED1_GPIO_Port, LED1_Pin, GPIO_PIN_RESET); 80012e4: 2200 movs r2, #0 80012e6: f44f 7100 mov.w r1, #512 @ 0x200 80012ea: 4838 ldr r0, [pc, #224] @ (80013cc ) 80012ec: f003 fc28 bl 8004b40 HAL_GPIO_WritePin(LED2_GPIO_Port, LED2_Pin, GPIO_PIN_RESET); 80012f0: 2200 movs r2, #0 80012f2: f44f 7180 mov.w r1, #256 @ 0x100 80012f6: 4835 ldr r0, [pc, #212] @ (80013cc ) 80012f8: f003 fc22 bl 8004b40 HAL_GPIO_WritePin(LED3_GPIO_Port, LED3_Pin, GPIO_PIN_RESET); 80012fc: 2200 movs r2, #0 80012fe: 2180 movs r1, #128 @ 0x80 8001300: 4832 ldr r0, [pc, #200] @ (80013cc ) 8001302: f003 fc1d bl 8004b40 HAL_GPIO_WritePin(LED4_GPIO_Port, LED4_Pin, GPIO_PIN_RESET); 8001306: 2200 movs r2, #0 8001308: 2140 movs r1, #64 @ 0x40 800130a: 4830 ldr r0, [pc, #192] @ (80013cc ) 800130c: f003 fc18 bl 8004b40 // end start-up animation HAL_GPIO_WritePin(LED4_GPIO_Port, LED4_Pin, GPIO_PIN_SET); // indicates running STM 8001310: 2201 movs r2, #1 8001312: 2140 movs r1, #64 @ 0x40 8001314: 482d ldr r0, [pc, #180] @ (80013cc ) 8001316: f003 fc13 bl 8004b40 uint32_t lasttick = HAL_GetTick(); // time in ms since start 800131a: f000 fff3 bl 8002304 800131e: 6078 str r0, [r7, #4] inhibit_SDC = 0; // allow SDC to be closed 8001320: 4b2b ldr r3, [pc, #172] @ (80013d0 ) 8001322: 2200 movs r2, #0 8001324: 601a str r2, [r3, #0] while (1) { /* USER CODE END WHILE */ /* USER CODE BEGIN 3 */ if (canmsg_received){ 8001326: 4b2b ldr r3, [pc, #172] @ (80013d4 ) 8001328: 781b ldrb r3, [r3, #0] 800132a: b2db uxtb r3, r3 800132c: 2b00 cmp r3, #0 800132e: d006 beq.n 800133e canmsg_received = 0; 8001330: 4b28 ldr r3, [pc, #160] @ (80013d4 ) 8001332: 2200 movs r2, #0 8001334: 701a strb r2, [r3, #0] update_ports = rxstate.iostatus; 8001336: 4a28 ldr r2, [pc, #160] @ (80013d8 ) 8001338: 4b28 ldr r3, [pc, #160] @ (80013dc ) 800133a: 881b ldrh r3, [r3, #0] 800133c: 8013 strh r3, [r2, #0] } if ((HAL_GetTick() - lasttick) > 100u){ 800133e: f000 ffe1 bl 8002304 8001342: 4602 mov r2, r0 8001344: 687b ldr r3, [r7, #4] 8001346: 1ad3 subs r3, r2, r3 8001348: 2b64 cmp r3, #100 @ 0x64 800134a: d908 bls.n 800135e lasttick = HAL_GetTick(); 800134c: f000 ffda bl 8002304 8001350: 6078 str r0, [r7, #4] check_plausibility(); 8001352: f000 fb79 bl 8001a48 can_sendloop(); 8001356: f7ff fa4d bl 80007f4 can_error_report(); 800135a: f7ff fb49 bl 80009f0 } if (((HAL_GetTick() - lastheartbeat) > 200U) && (HAL_GetTick() > 1000U)) { 800135e: f000 ffd1 bl 8002304 8001362: 4602 mov r2, r0 8001364: 4b1e ldr r3, [pc, #120] @ (80013e0 ) 8001366: 681b ldr r3, [r3, #0] 8001368: 1ad3 subs r3, r2, r3 800136a: 2bc8 cmp r3, #200 @ 0xc8 800136c: d908 bls.n 8001380 800136e: f000 ffc9 bl 8002304 8001372: 4603 mov r3, r0 8001374: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 8001378: d902 bls.n 8001380 inhibit_SDC = 1; 800137a: 4b15 ldr r3, [pc, #84] @ (80013d0 ) 800137c: 2201 movs r2, #1 800137e: 601a str r2, [r3, #0] } HAL_GPIO_WritePin(LED1_GPIO_Port, LED1_Pin, (GPIO_PinState)!update_ports.portb.sdc); // indicates open SDC 8001380: 4b15 ldr r3, [pc, #84] @ (80013d8 ) 8001382: 785b ldrb r3, [r3, #1] 8001384: f3c3 0340 ubfx r3, r3, #1, #1 8001388: b2db uxtb r3, r3 800138a: f083 0301 eor.w r3, r3, #1 800138e: b2db uxtb r3, r3 8001390: 461a mov r2, r3 8001392: f44f 7100 mov.w r1, #512 @ 0x200 8001396: 480d ldr r0, [pc, #52] @ (80013cc ) 8001398: f003 fbd2 bl 8004b40 HAL_GPIO_WritePin(LED2_GPIO_Port, LED2_Pin, (GPIO_PinState)inhibit_SDC); // indicates watchdog-status 800139c: 4b0c ldr r3, [pc, #48] @ (80013d0 ) 800139e: 681b ldr r3, [r3, #0] 80013a0: b2db uxtb r3, r3 80013a2: 461a mov r2, r3 80013a4: f44f 7180 mov.w r1, #256 @ 0x100 80013a8: 4808 ldr r0, [pc, #32] @ (80013cc ) 80013aa: f003 fbc9 bl 8004b40 ChannelControl_UpdateGPIOs(update_ports); 80013ae: 4b0a ldr r3, [pc, #40] @ (80013d8 ) 80013b0: 8818 ldrh r0, [r3, #0] 80013b2: f7ff fc4f bl 8000c54 current_monitor_checklimits(); // currently not implemented 80013b6: f7ff fd89 bl 8000ecc if (canmsg_received){ 80013ba: e7b4 b.n 8001326 80013bc: 200001ec .word 0x200001ec 80013c0: 20000214 .word 0x20000214 80013c4: 20000114 .word 0x20000114 80013c8: 200000c4 .word 0x200000c4 80013cc: 48000800 .word 0x48000800 80013d0: 200002f0 .word 0x200002f0 80013d4: 2000002c .word 0x2000002c 80013d8: 200002e8 .word 0x200002e8 80013dc: 20000028 .word 0x20000028 80013e0: 200002ec .word 0x200002ec 080013e4 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 80013e4: b580 push {r7, lr} 80013e6: b09c sub sp, #112 @ 0x70 80013e8: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 80013ea: f107 0348 add.w r3, r7, #72 @ 0x48 80013ee: 2228 movs r2, #40 @ 0x28 80013f0: 2100 movs r1, #0 80013f2: 4618 mov r0, r3 80013f4: f005 fef1 bl 80071da RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 80013f8: f107 0334 add.w r3, r7, #52 @ 0x34 80013fc: 2200 movs r2, #0 80013fe: 601a str r2, [r3, #0] 8001400: 605a str r2, [r3, #4] 8001402: 609a str r2, [r3, #8] 8001404: 60da str r2, [r3, #12] 8001406: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; 8001408: 463b mov r3, r7 800140a: 2234 movs r2, #52 @ 0x34 800140c: 2100 movs r1, #0 800140e: 4618 mov r0, r3 8001410: f005 fee3 bl 80071da /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; 8001414: 2301 movs r3, #1 8001416: 64bb str r3, [r7, #72] @ 0x48 RCC_OscInitStruct.HSEState = RCC_HSE_ON; 8001418: f44f 3380 mov.w r3, #65536 @ 0x10000 800141c: 64fb str r3, [r7, #76] @ 0x4c RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1; 800141e: 2300 movs r3, #0 8001420: 653b str r3, [r7, #80] @ 0x50 RCC_OscInitStruct.HSIState = RCC_HSI_ON; 8001422: 2301 movs r3, #1 8001424: 65bb str r3, [r7, #88] @ 0x58 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 8001426: 2302 movs r3, #2 8001428: 667b str r3, [r7, #100] @ 0x64 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 800142a: f44f 3380 mov.w r3, #65536 @ 0x10000 800142e: 66bb str r3, [r7, #104] @ 0x68 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL4; 8001430: f44f 2300 mov.w r3, #524288 @ 0x80000 8001434: 66fb str r3, [r7, #108] @ 0x6c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 8001436: f107 0348 add.w r3, r7, #72 @ 0x48 800143a: 4618 mov r0, r3 800143c: f003 fb98 bl 8004b70 8001440: 4603 mov r3, r0 8001442: 2b00 cmp r3, #0 8001444: d001 beq.n 800144a { Error_Handler(); 8001446: f000 faf9 bl 8001a3c } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 800144a: 230f movs r3, #15 800144c: 637b str r3, [r7, #52] @ 0x34 |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE; 800144e: 2301 movs r3, #1 8001450: 63bb str r3, [r7, #56] @ 0x38 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 8001452: 2300 movs r3, #0 8001454: 63fb str r3, [r7, #60] @ 0x3c RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; 8001456: 2300 movs r3, #0 8001458: 643b str r3, [r7, #64] @ 0x40 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 800145a: 2300 movs r3, #0 800145c: 647b str r3, [r7, #68] @ 0x44 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) 800145e: f107 0334 add.w r3, r7, #52 @ 0x34 8001462: 2100 movs r1, #0 8001464: 4618 mov r0, r3 8001466: f004 fbc1 bl 8005bec 800146a: 4603 mov r3, r0 800146c: 2b00 cmp r3, #0 800146e: d001 beq.n 8001474 { Error_Handler(); 8001470: f000 fae4 bl 8001a3c } PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_UART4|RCC_PERIPHCLK_ADC12; 8001474: 2388 movs r3, #136 @ 0x88 8001476: 603b str r3, [r7, #0] PeriphClkInit.Uart4ClockSelection = RCC_UART4CLKSOURCE_PCLK1; 8001478: 2300 movs r3, #0 800147a: 617b str r3, [r7, #20] PeriphClkInit.Adc12ClockSelection = RCC_ADC12PLLCLK_DIV1; 800147c: f44f 7380 mov.w r3, #256 @ 0x100 8001480: 627b str r3, [r7, #36] @ 0x24 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 8001482: 463b mov r3, r7 8001484: 4618 mov r0, r3 8001486: f004 fdd3 bl 8006030 800148a: 4603 mov r3, r0 800148c: 2b00 cmp r3, #0 800148e: d001 beq.n 8001494 { Error_Handler(); 8001490: f000 fad4 bl 8001a3c } } 8001494: bf00 nop 8001496: 3770 adds r7, #112 @ 0x70 8001498: 46bd mov sp, r7 800149a: bd80 pop {r7, pc} 0800149c : * @brief ADC1 Initialization Function * @param None * @retval None */ static void MX_ADC1_Init(void) { 800149c: b580 push {r7, lr} 800149e: b08a sub sp, #40 @ 0x28 80014a0: af00 add r7, sp, #0 /* USER CODE BEGIN ADC1_Init 0 */ /* USER CODE END ADC1_Init 0 */ ADC_MultiModeTypeDef multimode = {0}; 80014a2: f107 031c add.w r3, r7, #28 80014a6: 2200 movs r2, #0 80014a8: 601a str r2, [r3, #0] 80014aa: 605a str r2, [r3, #4] 80014ac: 609a str r2, [r3, #8] ADC_ChannelConfTypeDef sConfig = {0}; 80014ae: 1d3b adds r3, r7, #4 80014b0: 2200 movs r2, #0 80014b2: 601a str r2, [r3, #0] 80014b4: 605a str r2, [r3, #4] 80014b6: 609a str r2, [r3, #8] 80014b8: 60da str r2, [r3, #12] 80014ba: 611a str r2, [r3, #16] 80014bc: 615a str r2, [r3, #20] /* USER CODE END ADC1_Init 1 */ /** Common config */ hadc1.Instance = ADC1; 80014be: 4b60 ldr r3, [pc, #384] @ (8001640 ) 80014c0: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 80014c4: 601a str r2, [r3, #0] hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1; 80014c6: 4b5e ldr r3, [pc, #376] @ (8001640 ) 80014c8: 2200 movs r2, #0 80014ca: 605a str r2, [r3, #4] hadc1.Init.Resolution = ADC_RESOLUTION_12B; 80014cc: 4b5c ldr r3, [pc, #368] @ (8001640 ) 80014ce: 2200 movs r2, #0 80014d0: 609a str r2, [r3, #8] hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE; 80014d2: 4b5b ldr r3, [pc, #364] @ (8001640 ) 80014d4: 2201 movs r2, #1 80014d6: 611a str r2, [r3, #16] hadc1.Init.ContinuousConvMode = DISABLE; 80014d8: 4b59 ldr r3, [pc, #356] @ (8001640 ) 80014da: 2200 movs r2, #0 80014dc: 765a strb r2, [r3, #25] hadc1.Init.DiscontinuousConvMode = DISABLE; 80014de: 4b58 ldr r3, [pc, #352] @ (8001640 ) 80014e0: 2200 movs r2, #0 80014e2: f883 2020 strb.w r2, [r3, #32] hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; 80014e6: 4b56 ldr r3, [pc, #344] @ (8001640 ) 80014e8: f44f 6280 mov.w r2, #1024 @ 0x400 80014ec: 62da str r2, [r3, #44] @ 0x2c hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_T6_TRGO; 80014ee: 4b54 ldr r3, [pc, #336] @ (8001640 ) 80014f0: f44f 7250 mov.w r2, #832 @ 0x340 80014f4: 629a str r2, [r3, #40] @ 0x28 hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; 80014f6: 4b52 ldr r3, [pc, #328] @ (8001640 ) 80014f8: 2200 movs r2, #0 80014fa: 60da str r2, [r3, #12] hadc1.Init.NbrOfConversion = 8; 80014fc: 4b50 ldr r3, [pc, #320] @ (8001640 ) 80014fe: 2208 movs r2, #8 8001500: 61da str r2, [r3, #28] hadc1.Init.DMAContinuousRequests = ENABLE; 8001502: 4b4f ldr r3, [pc, #316] @ (8001640 ) 8001504: 2201 movs r2, #1 8001506: f883 2030 strb.w r2, [r3, #48] @ 0x30 hadc1.Init.EOCSelection = ADC_EOC_SEQ_CONV; 800150a: 4b4d ldr r3, [pc, #308] @ (8001640 ) 800150c: 2208 movs r2, #8 800150e: 615a str r2, [r3, #20] hadc1.Init.LowPowerAutoWait = DISABLE; 8001510: 4b4b ldr r3, [pc, #300] @ (8001640 ) 8001512: 2200 movs r2, #0 8001514: 761a strb r2, [r3, #24] hadc1.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN; 8001516: 4b4a ldr r3, [pc, #296] @ (8001640 ) 8001518: 2200 movs r2, #0 800151a: 635a str r2, [r3, #52] @ 0x34 if (HAL_ADC_Init(&hadc1) != HAL_OK) 800151c: 4848 ldr r0, [pc, #288] @ (8001640 ) 800151e: f000 ff3f bl 80023a0 8001522: 4603 mov r3, r0 8001524: 2b00 cmp r3, #0 8001526: d001 beq.n 800152c { Error_Handler(); 8001528: f000 fa88 bl 8001a3c } /** Configure the ADC multi-mode */ multimode.Mode = ADC_MODE_INDEPENDENT; 800152c: 2300 movs r3, #0 800152e: 61fb str r3, [r7, #28] if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK) 8001530: f107 031c add.w r3, r7, #28 8001534: 4619 mov r1, r3 8001536: 4842 ldr r0, [pc, #264] @ (8001640 ) 8001538: f001 fe7e bl 8003238 800153c: 4603 mov r3, r0 800153e: 2b00 cmp r3, #0 8001540: d001 beq.n 8001546 { Error_Handler(); 8001542: f000 fa7b bl 8001a3c } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_5; 8001546: 2305 movs r3, #5 8001548: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_1; 800154a: 2301 movs r3, #1 800154c: 60bb str r3, [r7, #8] sConfig.SingleDiff = ADC_SINGLE_ENDED; 800154e: 2300 movs r3, #0 8001550: 613b str r3, [r7, #16] sConfig.SamplingTime = ADC_SAMPLETIME_61CYCLES_5; 8001552: 2305 movs r3, #5 8001554: 60fb str r3, [r7, #12] sConfig.OffsetNumber = ADC_OFFSET_NONE; 8001556: 2300 movs r3, #0 8001558: 617b str r3, [r7, #20] sConfig.Offset = 0; 800155a: 2300 movs r3, #0 800155c: 61bb str r3, [r7, #24] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 800155e: 1d3b adds r3, r7, #4 8001560: 4619 mov r1, r3 8001562: 4837 ldr r0, [pc, #220] @ (8001640 ) 8001564: f001 fbaa bl 8002cbc 8001568: 4603 mov r3, r0 800156a: 2b00 cmp r3, #0 800156c: d001 beq.n 8001572 { Error_Handler(); 800156e: f000 fa65 bl 8001a3c } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_6; 8001572: 2306 movs r3, #6 8001574: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_2; 8001576: 2302 movs r3, #2 8001578: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 800157a: 1d3b adds r3, r7, #4 800157c: 4619 mov r1, r3 800157e: 4830 ldr r0, [pc, #192] @ (8001640 ) 8001580: f001 fb9c bl 8002cbc 8001584: 4603 mov r3, r0 8001586: 2b00 cmp r3, #0 8001588: d001 beq.n 800158e { Error_Handler(); 800158a: f000 fa57 bl 8001a3c } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_2; 800158e: 2302 movs r3, #2 8001590: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_3; 8001592: 2303 movs r3, #3 8001594: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8001596: 1d3b adds r3, r7, #4 8001598: 4619 mov r1, r3 800159a: 4829 ldr r0, [pc, #164] @ (8001640 ) 800159c: f001 fb8e bl 8002cbc 80015a0: 4603 mov r3, r0 80015a2: 2b00 cmp r3, #0 80015a4: d001 beq.n 80015aa { Error_Handler(); 80015a6: f000 fa49 bl 8001a3c } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_3; 80015aa: 2303 movs r3, #3 80015ac: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_4; 80015ae: 2304 movs r3, #4 80015b0: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 80015b2: 1d3b adds r3, r7, #4 80015b4: 4619 mov r1, r3 80015b6: 4822 ldr r0, [pc, #136] @ (8001640 ) 80015b8: f001 fb80 bl 8002cbc 80015bc: 4603 mov r3, r0 80015be: 2b00 cmp r3, #0 80015c0: d001 beq.n 80015c6 { Error_Handler(); 80015c2: f000 fa3b bl 8001a3c } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_4; 80015c6: 2304 movs r3, #4 80015c8: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_5; 80015ca: 2305 movs r3, #5 80015cc: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 80015ce: 1d3b adds r3, r7, #4 80015d0: 4619 mov r1, r3 80015d2: 481b ldr r0, [pc, #108] @ (8001640 ) 80015d4: f001 fb72 bl 8002cbc 80015d8: 4603 mov r3, r0 80015da: 2b00 cmp r3, #0 80015dc: d001 beq.n 80015e2 { Error_Handler(); 80015de: f000 fa2d bl 8001a3c } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_1; 80015e2: 2301 movs r3, #1 80015e4: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_6; 80015e6: 2306 movs r3, #6 80015e8: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 80015ea: 1d3b adds r3, r7, #4 80015ec: 4619 mov r1, r3 80015ee: 4814 ldr r0, [pc, #80] @ (8001640 ) 80015f0: f001 fb64 bl 8002cbc 80015f4: 4603 mov r3, r0 80015f6: 2b00 cmp r3, #0 80015f8: d001 beq.n 80015fe { Error_Handler(); 80015fa: f000 fa1f bl 8001a3c } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_7; 80015fe: 2307 movs r3, #7 8001600: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_7; 8001602: 2307 movs r3, #7 8001604: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8001606: 1d3b adds r3, r7, #4 8001608: 4619 mov r1, r3 800160a: 480d ldr r0, [pc, #52] @ (8001640 ) 800160c: f001 fb56 bl 8002cbc 8001610: 4603 mov r3, r0 8001612: 2b00 cmp r3, #0 8001614: d001 beq.n 800161a { Error_Handler(); 8001616: f000 fa11 bl 8001a3c } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_8; 800161a: 2308 movs r3, #8 800161c: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_8; 800161e: 2308 movs r3, #8 8001620: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8001622: 1d3b adds r3, r7, #4 8001624: 4619 mov r1, r3 8001626: 4806 ldr r0, [pc, #24] @ (8001640 ) 8001628: f001 fb48 bl 8002cbc 800162c: 4603 mov r3, r0 800162e: 2b00 cmp r3, #0 8001630: d001 beq.n 8001636 { Error_Handler(); 8001632: f000 fa03 bl 8001a3c } /* USER CODE BEGIN ADC1_Init 2 */ /* USER CODE END ADC1_Init 2 */ } 8001636: bf00 nop 8001638: 3728 adds r7, #40 @ 0x28 800163a: 46bd mov sp, r7 800163c: bd80 pop {r7, pc} 800163e: bf00 nop 8001640: 200000c4 .word 0x200000c4 08001644 : * @brief ADC2 Initialization Function * @param None * @retval None */ static void MX_ADC2_Init(void) { 8001644: b580 push {r7, lr} 8001646: b086 sub sp, #24 8001648: af00 add r7, sp, #0 /* USER CODE BEGIN ADC2_Init 0 */ /* USER CODE END ADC2_Init 0 */ ADC_ChannelConfTypeDef sConfig = {0}; 800164a: 463b mov r3, r7 800164c: 2200 movs r2, #0 800164e: 601a str r2, [r3, #0] 8001650: 605a str r2, [r3, #4] 8001652: 609a str r2, [r3, #8] 8001654: 60da str r2, [r3, #12] 8001656: 611a str r2, [r3, #16] 8001658: 615a str r2, [r3, #20] /* USER CODE END ADC2_Init 1 */ /** Common config */ hadc2.Instance = ADC2; 800165a: 4b4b ldr r3, [pc, #300] @ (8001788 ) 800165c: 4a4b ldr r2, [pc, #300] @ (800178c ) 800165e: 601a str r2, [r3, #0] hadc2.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1; 8001660: 4b49 ldr r3, [pc, #292] @ (8001788 ) 8001662: 2200 movs r2, #0 8001664: 605a str r2, [r3, #4] hadc2.Init.Resolution = ADC_RESOLUTION_12B; 8001666: 4b48 ldr r3, [pc, #288] @ (8001788 ) 8001668: 2200 movs r2, #0 800166a: 609a str r2, [r3, #8] hadc2.Init.ScanConvMode = ADC_SCAN_ENABLE; 800166c: 4b46 ldr r3, [pc, #280] @ (8001788 ) 800166e: 2201 movs r2, #1 8001670: 611a str r2, [r3, #16] hadc2.Init.ContinuousConvMode = DISABLE; 8001672: 4b45 ldr r3, [pc, #276] @ (8001788 ) 8001674: 2200 movs r2, #0 8001676: 765a strb r2, [r3, #25] hadc2.Init.DiscontinuousConvMode = DISABLE; 8001678: 4b43 ldr r3, [pc, #268] @ (8001788 ) 800167a: 2200 movs r2, #0 800167c: f883 2020 strb.w r2, [r3, #32] hadc2.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; 8001680: 4b41 ldr r3, [pc, #260] @ (8001788 ) 8001682: f44f 6280 mov.w r2, #1024 @ 0x400 8001686: 62da str r2, [r3, #44] @ 0x2c hadc2.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_T6_TRGO; 8001688: 4b3f ldr r3, [pc, #252] @ (8001788 ) 800168a: f44f 7250 mov.w r2, #832 @ 0x340 800168e: 629a str r2, [r3, #40] @ 0x28 hadc2.Init.DataAlign = ADC_DATAALIGN_RIGHT; 8001690: 4b3d ldr r3, [pc, #244] @ (8001788 ) 8001692: 2200 movs r2, #0 8001694: 60da str r2, [r3, #12] hadc2.Init.NbrOfConversion = 6; 8001696: 4b3c ldr r3, [pc, #240] @ (8001788 ) 8001698: 2206 movs r2, #6 800169a: 61da str r2, [r3, #28] hadc2.Init.DMAContinuousRequests = ENABLE; 800169c: 4b3a ldr r3, [pc, #232] @ (8001788 ) 800169e: 2201 movs r2, #1 80016a0: f883 2030 strb.w r2, [r3, #48] @ 0x30 hadc2.Init.EOCSelection = ADC_EOC_SEQ_CONV; 80016a4: 4b38 ldr r3, [pc, #224] @ (8001788 ) 80016a6: 2208 movs r2, #8 80016a8: 615a str r2, [r3, #20] hadc2.Init.LowPowerAutoWait = DISABLE; 80016aa: 4b37 ldr r3, [pc, #220] @ (8001788 ) 80016ac: 2200 movs r2, #0 80016ae: 761a strb r2, [r3, #24] hadc2.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN; 80016b0: 4b35 ldr r3, [pc, #212] @ (8001788 ) 80016b2: 2200 movs r2, #0 80016b4: 635a str r2, [r3, #52] @ 0x34 if (HAL_ADC_Init(&hadc2) != HAL_OK) 80016b6: 4834 ldr r0, [pc, #208] @ (8001788 ) 80016b8: f000 fe72 bl 80023a0 80016bc: 4603 mov r3, r0 80016be: 2b00 cmp r3, #0 80016c0: d001 beq.n 80016c6 { Error_Handler(); 80016c2: f000 f9bb bl 8001a3c } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_1; 80016c6: 2301 movs r3, #1 80016c8: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_1; 80016ca: 2301 movs r3, #1 80016cc: 607b str r3, [r7, #4] sConfig.SingleDiff = ADC_SINGLE_ENDED; 80016ce: 2300 movs r3, #0 80016d0: 60fb str r3, [r7, #12] sConfig.SamplingTime = ADC_SAMPLETIME_61CYCLES_5; 80016d2: 2305 movs r3, #5 80016d4: 60bb str r3, [r7, #8] sConfig.OffsetNumber = ADC_OFFSET_NONE; 80016d6: 2300 movs r3, #0 80016d8: 613b str r3, [r7, #16] sConfig.Offset = 0; 80016da: 2300 movs r3, #0 80016dc: 617b str r3, [r7, #20] if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) 80016de: 463b mov r3, r7 80016e0: 4619 mov r1, r3 80016e2: 4829 ldr r0, [pc, #164] @ (8001788 ) 80016e4: f001 faea bl 8002cbc 80016e8: 4603 mov r3, r0 80016ea: 2b00 cmp r3, #0 80016ec: d001 beq.n 80016f2 { Error_Handler(); 80016ee: f000 f9a5 bl 8001a3c } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_2; 80016f2: 2302 movs r3, #2 80016f4: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_2; 80016f6: 2302 movs r3, #2 80016f8: 607b str r3, [r7, #4] if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) 80016fa: 463b mov r3, r7 80016fc: 4619 mov r1, r3 80016fe: 4822 ldr r0, [pc, #136] @ (8001788 ) 8001700: f001 fadc bl 8002cbc 8001704: 4603 mov r3, r0 8001706: 2b00 cmp r3, #0 8001708: d001 beq.n 800170e { Error_Handler(); 800170a: f000 f997 bl 8001a3c } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_3; 800170e: 2303 movs r3, #3 8001710: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_3; 8001712: 2303 movs r3, #3 8001714: 607b str r3, [r7, #4] if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) 8001716: 463b mov r3, r7 8001718: 4619 mov r1, r3 800171a: 481b ldr r0, [pc, #108] @ (8001788 ) 800171c: f001 face bl 8002cbc 8001720: 4603 mov r3, r0 8001722: 2b00 cmp r3, #0 8001724: d001 beq.n 800172a { Error_Handler(); 8001726: f000 f989 bl 8001a3c } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_4; 800172a: 2304 movs r3, #4 800172c: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_4; 800172e: 2304 movs r3, #4 8001730: 607b str r3, [r7, #4] if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) 8001732: 463b mov r3, r7 8001734: 4619 mov r1, r3 8001736: 4814 ldr r0, [pc, #80] @ (8001788 ) 8001738: f001 fac0 bl 8002cbc 800173c: 4603 mov r3, r0 800173e: 2b00 cmp r3, #0 8001740: d001 beq.n 8001746 { Error_Handler(); 8001742: f000 f97b bl 8001a3c } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_5; 8001746: 2305 movs r3, #5 8001748: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_5; 800174a: 2305 movs r3, #5 800174c: 607b str r3, [r7, #4] if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) 800174e: 463b mov r3, r7 8001750: 4619 mov r1, r3 8001752: 480d ldr r0, [pc, #52] @ (8001788 ) 8001754: f001 fab2 bl 8002cbc 8001758: 4603 mov r3, r0 800175a: 2b00 cmp r3, #0 800175c: d001 beq.n 8001762 { Error_Handler(); 800175e: f000 f96d bl 8001a3c } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_9; 8001762: 2309 movs r3, #9 8001764: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_6; 8001766: 2306 movs r3, #6 8001768: 607b str r3, [r7, #4] if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) 800176a: 463b mov r3, r7 800176c: 4619 mov r1, r3 800176e: 4806 ldr r0, [pc, #24] @ (8001788 ) 8001770: f001 faa4 bl 8002cbc 8001774: 4603 mov r3, r0 8001776: 2b00 cmp r3, #0 8001778: d001 beq.n 800177e { Error_Handler(); 800177a: f000 f95f bl 8001a3c } /* USER CODE BEGIN ADC2_Init 2 */ /* USER CODE END ADC2_Init 2 */ } 800177e: bf00 nop 8001780: 3718 adds r7, #24 8001782: 46bd mov sp, r7 8001784: bd80 pop {r7, pc} 8001786: bf00 nop 8001788: 20000114 .word 0x20000114 800178c: 50000100 .word 0x50000100 08001790 : * @brief CAN Initialization Function * @param None * @retval None */ static void MX_CAN_Init(void) { 8001790: b580 push {r7, lr} 8001792: af00 add r7, sp, #0 /* USER CODE END CAN_Init 0 */ /* USER CODE BEGIN CAN_Init 1 */ /* USER CODE END CAN_Init 1 */ hcan.Instance = CAN; 8001794: 4b17 ldr r3, [pc, #92] @ (80017f4 ) 8001796: 4a18 ldr r2, [pc, #96] @ (80017f8 ) 8001798: 601a str r2, [r3, #0] hcan.Init.Prescaler = 2; 800179a: 4b16 ldr r3, [pc, #88] @ (80017f4 ) 800179c: 2202 movs r2, #2 800179e: 605a str r2, [r3, #4] hcan.Init.Mode = CAN_MODE_NORMAL; 80017a0: 4b14 ldr r3, [pc, #80] @ (80017f4 ) 80017a2: 2200 movs r2, #0 80017a4: 609a str r2, [r3, #8] hcan.Init.SyncJumpWidth = CAN_SJW_1TQ; 80017a6: 4b13 ldr r3, [pc, #76] @ (80017f4 ) 80017a8: 2200 movs r2, #0 80017aa: 60da str r2, [r3, #12] hcan.Init.TimeSeg1 = CAN_BS1_13TQ; 80017ac: 4b11 ldr r3, [pc, #68] @ (80017f4 ) 80017ae: f44f 2240 mov.w r2, #786432 @ 0xc0000 80017b2: 611a str r2, [r3, #16] hcan.Init.TimeSeg2 = CAN_BS2_2TQ; 80017b4: 4b0f ldr r3, [pc, #60] @ (80017f4 ) 80017b6: f44f 1280 mov.w r2, #1048576 @ 0x100000 80017ba: 615a str r2, [r3, #20] hcan.Init.TimeTriggeredMode = DISABLE; 80017bc: 4b0d ldr r3, [pc, #52] @ (80017f4 ) 80017be: 2200 movs r2, #0 80017c0: 761a strb r2, [r3, #24] hcan.Init.AutoBusOff = DISABLE; 80017c2: 4b0c ldr r3, [pc, #48] @ (80017f4 ) 80017c4: 2200 movs r2, #0 80017c6: 765a strb r2, [r3, #25] hcan.Init.AutoWakeUp = DISABLE; 80017c8: 4b0a ldr r3, [pc, #40] @ (80017f4 ) 80017ca: 2200 movs r2, #0 80017cc: 769a strb r2, [r3, #26] hcan.Init.AutoRetransmission = DISABLE; 80017ce: 4b09 ldr r3, [pc, #36] @ (80017f4 ) 80017d0: 2200 movs r2, #0 80017d2: 76da strb r2, [r3, #27] hcan.Init.ReceiveFifoLocked = DISABLE; 80017d4: 4b07 ldr r3, [pc, #28] @ (80017f4 ) 80017d6: 2200 movs r2, #0 80017d8: 771a strb r2, [r3, #28] hcan.Init.TransmitFifoPriority = DISABLE; 80017da: 4b06 ldr r3, [pc, #24] @ (80017f4 ) 80017dc: 2200 movs r2, #0 80017de: 775a strb r2, [r3, #29] if (HAL_CAN_Init(&hcan) != HAL_OK) 80017e0: 4804 ldr r0, [pc, #16] @ (80017f4 ) 80017e2: f001 ff1f bl 8003624 80017e6: 4603 mov r3, r0 80017e8: 2b00 cmp r3, #0 80017ea: d001 beq.n 80017f0 { Error_Handler(); 80017ec: f000 f926 bl 8001a3c } /* USER CODE BEGIN CAN_Init 2 */ /* USER CODE END CAN_Init 2 */ } 80017f0: bf00 nop 80017f2: bd80 pop {r7, pc} 80017f4: 200001ec .word 0x200001ec 80017f8: 40006400 .word 0x40006400 080017fc : * @brief TIM6 Initialization Function * @param None * @retval None */ static void MX_TIM6_Init(void) { 80017fc: b580 push {r7, lr} 80017fe: b084 sub sp, #16 8001800: af00 add r7, sp, #0 /* USER CODE BEGIN TIM6_Init 0 */ /* USER CODE END TIM6_Init 0 */ TIM_MasterConfigTypeDef sMasterConfig = {0}; 8001802: 1d3b adds r3, r7, #4 8001804: 2200 movs r2, #0 8001806: 601a str r2, [r3, #0] 8001808: 605a str r2, [r3, #4] 800180a: 609a str r2, [r3, #8] /* USER CODE BEGIN TIM6_Init 1 */ /* USER CODE END TIM6_Init 1 */ htim6.Instance = TIM6; 800180c: 4b15 ldr r3, [pc, #84] @ (8001864 ) 800180e: 4a16 ldr r2, [pc, #88] @ (8001868 ) 8001810: 601a str r2, [r3, #0] htim6.Init.Prescaler = 400; 8001812: 4b14 ldr r3, [pc, #80] @ (8001864 ) 8001814: f44f 72c8 mov.w r2, #400 @ 0x190 8001818: 605a str r2, [r3, #4] htim6.Init.CounterMode = TIM_COUNTERMODE_UP; 800181a: 4b12 ldr r3, [pc, #72] @ (8001864 ) 800181c: 2200 movs r2, #0 800181e: 609a str r2, [r3, #8] htim6.Init.Period = 8000-1; 8001820: 4b10 ldr r3, [pc, #64] @ (8001864 ) 8001822: f641 723f movw r2, #7999 @ 0x1f3f 8001826: 60da str r2, [r3, #12] htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 8001828: 4b0e ldr r3, [pc, #56] @ (8001864 ) 800182a: 2200 movs r2, #0 800182c: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim6) != HAL_OK) 800182e: 480d ldr r0, [pc, #52] @ (8001864 ) 8001830: f004 fd90 bl 8006354 8001834: 4603 mov r3, r0 8001836: 2b00 cmp r3, #0 8001838: d001 beq.n 800183e { Error_Handler(); 800183a: f000 f8ff bl 8001a3c } sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE; 800183e: 2320 movs r3, #32 8001840: 607b str r3, [r7, #4] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 8001842: 2300 movs r3, #0 8001844: 60fb str r3, [r7, #12] if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig) != HAL_OK) 8001846: 1d3b adds r3, r7, #4 8001848: 4619 mov r1, r3 800184a: 4806 ldr r0, [pc, #24] @ (8001864 ) 800184c: f004 fff6 bl 800683c 8001850: 4603 mov r3, r0 8001852: 2b00 cmp r3, #0 8001854: d001 beq.n 800185a { Error_Handler(); 8001856: f000 f8f1 bl 8001a3c } /* USER CODE BEGIN TIM6_Init 2 */ /* USER CODE END TIM6_Init 2 */ } 800185a: bf00 nop 800185c: 3710 adds r7, #16 800185e: 46bd mov sp, r7 8001860: bd80 pop {r7, pc} 8001862: bf00 nop 8001864: 20000214 .word 0x20000214 8001868: 40001000 .word 0x40001000 0800186c : * @brief UART4 Initialization Function * @param None * @retval None */ static void MX_UART4_Init(void) { 800186c: b580 push {r7, lr} 800186e: af00 add r7, sp, #0 /* USER CODE END UART4_Init 0 */ /* USER CODE BEGIN UART4_Init 1 */ /* USER CODE END UART4_Init 1 */ huart4.Instance = UART4; 8001870: 4b14 ldr r3, [pc, #80] @ (80018c4 ) 8001872: 4a15 ldr r2, [pc, #84] @ (80018c8 ) 8001874: 601a str r2, [r3, #0] huart4.Init.BaudRate = 115200; 8001876: 4b13 ldr r3, [pc, #76] @ (80018c4 ) 8001878: f44f 32e1 mov.w r2, #115200 @ 0x1c200 800187c: 605a str r2, [r3, #4] huart4.Init.WordLength = UART_WORDLENGTH_8B; 800187e: 4b11 ldr r3, [pc, #68] @ (80018c4 ) 8001880: 2200 movs r2, #0 8001882: 609a str r2, [r3, #8] huart4.Init.StopBits = UART_STOPBITS_1; 8001884: 4b0f ldr r3, [pc, #60] @ (80018c4 ) 8001886: 2200 movs r2, #0 8001888: 60da str r2, [r3, #12] huart4.Init.Parity = UART_PARITY_NONE; 800188a: 4b0e ldr r3, [pc, #56] @ (80018c4 ) 800188c: 2200 movs r2, #0 800188e: 611a str r2, [r3, #16] huart4.Init.Mode = UART_MODE_TX_RX; 8001890: 4b0c ldr r3, [pc, #48] @ (80018c4 ) 8001892: 220c movs r2, #12 8001894: 615a str r2, [r3, #20] huart4.Init.HwFlowCtl = UART_HWCONTROL_NONE; 8001896: 4b0b ldr r3, [pc, #44] @ (80018c4 ) 8001898: 2200 movs r2, #0 800189a: 619a str r2, [r3, #24] huart4.Init.OverSampling = UART_OVERSAMPLING_16; 800189c: 4b09 ldr r3, [pc, #36] @ (80018c4 ) 800189e: 2200 movs r2, #0 80018a0: 61da str r2, [r3, #28] huart4.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; 80018a2: 4b08 ldr r3, [pc, #32] @ (80018c4 ) 80018a4: 2200 movs r2, #0 80018a6: 621a str r2, [r3, #32] huart4.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; 80018a8: 4b06 ldr r3, [pc, #24] @ (80018c4 ) 80018aa: 2200 movs r2, #0 80018ac: 625a str r2, [r3, #36] @ 0x24 if (HAL_UART_Init(&huart4) != HAL_OK) 80018ae: 4805 ldr r0, [pc, #20] @ (80018c4 ) 80018b0: f005 f856 bl 8006960 80018b4: 4603 mov r3, r0 80018b6: 2b00 cmp r3, #0 80018b8: d001 beq.n 80018be { Error_Handler(); 80018ba: f000 f8bf bl 8001a3c } /* USER CODE BEGIN UART4_Init 2 */ /* USER CODE END UART4_Init 2 */ } 80018be: bf00 nop 80018c0: bd80 pop {r7, pc} 80018c2: bf00 nop 80018c4: 20000260 .word 0x20000260 80018c8: 40004c00 .word 0x40004c00 080018cc : /** * Enable DMA controller clock */ static void MX_DMA_Init(void) { 80018cc: b580 push {r7, lr} 80018ce: b082 sub sp, #8 80018d0: af00 add r7, sp, #0 /* DMA controller clock enable */ __HAL_RCC_DMA1_CLK_ENABLE(); 80018d2: 4b16 ldr r3, [pc, #88] @ (800192c ) 80018d4: 695b ldr r3, [r3, #20] 80018d6: 4a15 ldr r2, [pc, #84] @ (800192c ) 80018d8: f043 0301 orr.w r3, r3, #1 80018dc: 6153 str r3, [r2, #20] 80018de: 4b13 ldr r3, [pc, #76] @ (800192c ) 80018e0: 695b ldr r3, [r3, #20] 80018e2: f003 0301 and.w r3, r3, #1 80018e6: 607b str r3, [r7, #4] 80018e8: 687b ldr r3, [r7, #4] __HAL_RCC_DMA2_CLK_ENABLE(); 80018ea: 4b10 ldr r3, [pc, #64] @ (800192c ) 80018ec: 695b ldr r3, [r3, #20] 80018ee: 4a0f ldr r2, [pc, #60] @ (800192c ) 80018f0: f043 0302 orr.w r3, r3, #2 80018f4: 6153 str r3, [r2, #20] 80018f6: 4b0d ldr r3, [pc, #52] @ (800192c ) 80018f8: 695b ldr r3, [r3, #20] 80018fa: f003 0302 and.w r3, r3, #2 80018fe: 603b str r3, [r7, #0] 8001900: 683b ldr r3, [r7, #0] /* DMA interrupt init */ /* DMA1_Channel1_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0); 8001902: 2200 movs r2, #0 8001904: 2100 movs r1, #0 8001906: 200b movs r0, #11 8001908: f002 fdb7 bl 800447a HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn); 800190c: 200b movs r0, #11 800190e: f002 fdd0 bl 80044b2 /* DMA2_Channel1_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA2_Channel1_IRQn, 0, 0); 8001912: 2200 movs r2, #0 8001914: 2100 movs r1, #0 8001916: 2038 movs r0, #56 @ 0x38 8001918: f002 fdaf bl 800447a HAL_NVIC_EnableIRQ(DMA2_Channel1_IRQn); 800191c: 2038 movs r0, #56 @ 0x38 800191e: f002 fdc8 bl 80044b2 } 8001922: bf00 nop 8001924: 3708 adds r7, #8 8001926: 46bd mov sp, r7 8001928: bd80 pop {r7, pc} 800192a: bf00 nop 800192c: 40021000 .word 0x40021000 08001930 : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { 8001930: b580 push {r7, lr} 8001932: b08a sub sp, #40 @ 0x28 8001934: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 8001936: f107 0314 add.w r3, r7, #20 800193a: 2200 movs r2, #0 800193c: 601a str r2, [r3, #0] 800193e: 605a str r2, [r3, #4] 8001940: 609a str r2, [r3, #8] 8001942: 60da str r2, [r3, #12] 8001944: 611a str r2, [r3, #16] /* USER CODE BEGIN MX_GPIO_Init_1 */ /* USER CODE END MX_GPIO_Init_1 */ /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOF_CLK_ENABLE(); 8001946: 4b3a ldr r3, [pc, #232] @ (8001a30 ) 8001948: 695b ldr r3, [r3, #20] 800194a: 4a39 ldr r2, [pc, #228] @ (8001a30 ) 800194c: f443 0380 orr.w r3, r3, #4194304 @ 0x400000 8001950: 6153 str r3, [r2, #20] 8001952: 4b37 ldr r3, [pc, #220] @ (8001a30 ) 8001954: 695b ldr r3, [r3, #20] 8001956: f403 0380 and.w r3, r3, #4194304 @ 0x400000 800195a: 613b str r3, [r7, #16] 800195c: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOC_CLK_ENABLE(); 800195e: 4b34 ldr r3, [pc, #208] @ (8001a30 ) 8001960: 695b ldr r3, [r3, #20] 8001962: 4a33 ldr r2, [pc, #204] @ (8001a30 ) 8001964: f443 2300 orr.w r3, r3, #524288 @ 0x80000 8001968: 6153 str r3, [r2, #20] 800196a: 4b31 ldr r3, [pc, #196] @ (8001a30 ) 800196c: 695b ldr r3, [r3, #20] 800196e: f403 2300 and.w r3, r3, #524288 @ 0x80000 8001972: 60fb str r3, [r7, #12] 8001974: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOA_CLK_ENABLE(); 8001976: 4b2e ldr r3, [pc, #184] @ (8001a30 ) 8001978: 695b ldr r3, [r3, #20] 800197a: 4a2d ldr r2, [pc, #180] @ (8001a30 ) 800197c: f443 3300 orr.w r3, r3, #131072 @ 0x20000 8001980: 6153 str r3, [r2, #20] 8001982: 4b2b ldr r3, [pc, #172] @ (8001a30 ) 8001984: 695b ldr r3, [r3, #20] 8001986: f403 3300 and.w r3, r3, #131072 @ 0x20000 800198a: 60bb str r3, [r7, #8] 800198c: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOB_CLK_ENABLE(); 800198e: 4b28 ldr r3, [pc, #160] @ (8001a30 ) 8001990: 695b ldr r3, [r3, #20] 8001992: 4a27 ldr r2, [pc, #156] @ (8001a30 ) 8001994: f443 2380 orr.w r3, r3, #262144 @ 0x40000 8001998: 6153 str r3, [r2, #20] 800199a: 4b25 ldr r3, [pc, #148] @ (8001a30 ) 800199c: 695b ldr r3, [r3, #20] 800199e: f403 2380 and.w r3, r3, #262144 @ 0x40000 80019a2: 607b str r3, [r7, #4] 80019a4: 687b ldr r3, [r7, #4] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOB, IN12_Pin|IN11_Pin|IN13_Pin|IN9_Pin 80019a6: 2200 movs r2, #0 80019a8: f64f 7176 movw r1, #65398 @ 0xff76 80019ac: 4821 ldr r0, [pc, #132] @ (8001a34 ) 80019ae: f003 f8c7 bl 8004b40 |IN3_Pin|IN8_Pin|IN5_Pin|IN4_Pin |DSEL0_Pin|DSEL1_Pin|PC_EN_Pin|IN7_Pin |IN10_Pin, GPIO_PIN_RESET); /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOC, LED4_Pin|LED3_Pin|LED2_Pin|LED1_Pin, GPIO_PIN_RESET); 80019b2: 2200 movs r2, #0 80019b4: f44f 7170 mov.w r1, #960 @ 0x3c0 80019b8: 481f ldr r0, [pc, #124] @ (8001a38 ) 80019ba: f003 f8c1 bl 8004b40 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOA, IN2_Pin|IN1_Pin|IN6_Pin, GPIO_PIN_RESET); 80019be: 2200 movs r2, #0 80019c0: f44f 61e0 mov.w r1, #1792 @ 0x700 80019c4: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 80019c8: f003 f8ba bl 8004b40 /*Configure GPIO pins : IN12_Pin IN11_Pin IN13_Pin IN9_Pin IN3_Pin IN8_Pin IN5_Pin IN4_Pin DSEL0_Pin DSEL1_Pin PC_EN_Pin IN7_Pin IN10_Pin */ GPIO_InitStruct.Pin = IN12_Pin|IN11_Pin|IN13_Pin|IN9_Pin 80019cc: f64f 7376 movw r3, #65398 @ 0xff76 80019d0: 617b str r3, [r7, #20] |IN3_Pin|IN8_Pin|IN5_Pin|IN4_Pin |DSEL0_Pin|DSEL1_Pin|PC_EN_Pin|IN7_Pin |IN10_Pin; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 80019d2: 2301 movs r3, #1 80019d4: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 80019d6: 2300 movs r3, #0 80019d8: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80019da: 2300 movs r3, #0 80019dc: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 80019de: f107 0314 add.w r3, r7, #20 80019e2: 4619 mov r1, r3 80019e4: 4813 ldr r0, [pc, #76] @ (8001a34 ) 80019e6: f002 ff31 bl 800484c /*Configure GPIO pins : LED4_Pin LED3_Pin LED2_Pin LED1_Pin */ GPIO_InitStruct.Pin = LED4_Pin|LED3_Pin|LED2_Pin|LED1_Pin; 80019ea: f44f 7370 mov.w r3, #960 @ 0x3c0 80019ee: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 80019f0: 2301 movs r3, #1 80019f2: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 80019f4: 2300 movs r3, #0 80019f6: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80019f8: 2300 movs r3, #0 80019fa: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 80019fc: f107 0314 add.w r3, r7, #20 8001a00: 4619 mov r1, r3 8001a02: 480d ldr r0, [pc, #52] @ (8001a38 ) 8001a04: f002 ff22 bl 800484c /*Configure GPIO pins : IN2_Pin IN1_Pin IN6_Pin */ GPIO_InitStruct.Pin = IN2_Pin|IN1_Pin|IN6_Pin; 8001a08: f44f 63e0 mov.w r3, #1792 @ 0x700 8001a0c: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8001a0e: 2301 movs r3, #1 8001a10: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001a12: 2300 movs r3, #0 8001a14: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8001a16: 2300 movs r3, #0 8001a18: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8001a1a: f107 0314 add.w r3, r7, #20 8001a1e: 4619 mov r1, r3 8001a20: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 8001a24: f002 ff12 bl 800484c /* USER CODE BEGIN MX_GPIO_Init_2 */ /* USER CODE END MX_GPIO_Init_2 */ } 8001a28: bf00 nop 8001a2a: 3728 adds r7, #40 @ 0x28 8001a2c: 46bd mov sp, r7 8001a2e: bd80 pop {r7, pc} 8001a30: 40021000 .word 0x40021000 8001a34: 48000400 .word 0x48000400 8001a38: 48000800 .word 0x48000800 08001a3c : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 8001a3c: b480 push {r7} 8001a3e: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 8001a40: b672 cpsid i } 8001a42: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 8001a44: bf00 nop 8001a46: e7fd b.n 8001a44 08001a48 : extern enable_gpios update_ports; extern current_measurements current_measurements_adc_val; volatile err_states error; extern int inhibit_SDC; void check_plausibility() { 8001a48: b480 push {r7} 8001a4a: af00 add r7, sp, #0 if (!update_ports.portb.sdc || inhibit_SDC == 1) {error.group1.sdc_open = 1;} 8001a4c: 4b9c ldr r3, [pc, #624] @ (8001cc0 ) 8001a4e: 785b ldrb r3, [r3, #1] 8001a50: f003 0302 and.w r3, r3, #2 8001a54: b2db uxtb r3, r3 8001a56: 2b00 cmp r3, #0 8001a58: d003 beq.n 8001a62 8001a5a: 4b9a ldr r3, [pc, #616] @ (8001cc4 ) 8001a5c: 681b ldr r3, [r3, #0] 8001a5e: 2b01 cmp r3, #1 8001a60: d105 bne.n 8001a6e 8001a62: 4a99 ldr r2, [pc, #612] @ (8001cc8 ) 8001a64: 7813 ldrb r3, [r2, #0] 8001a66: f043 0301 orr.w r3, r3, #1 8001a6a: 7013 strb r3, [r2, #0] 8001a6c: e004 b.n 8001a78 else {error.group1.sdc_open = 0;} 8001a6e: 4a96 ldr r2, [pc, #600] @ (8001cc8 ) 8001a70: 7813 ldrb r3, [r2, #0] 8001a72: f36f 0300 bfc r3, #0, #1 8001a76: 7013 strb r3, [r2, #0] if (update_ports.porta.acc_cooling == 1 && current_measurements_adc_val.acc_cooling == 0) { 8001a78: 4b91 ldr r3, [pc, #580] @ (8001cc0 ) 8001a7a: 781b ldrb r3, [r3, #0] 8001a7c: f003 0301 and.w r3, r3, #1 8001a80: b2db uxtb r3, r3 8001a82: 2b00 cmp r3, #0 8001a84: d009 beq.n 8001a9a 8001a86: 4b91 ldr r3, [pc, #580] @ (8001ccc ) 8001a88: 881b ldrh r3, [r3, #0] 8001a8a: 2b00 cmp r3, #0 8001a8c: d105 bne.n 8001a9a error.group1.noload_acc_cooling = 1; 8001a8e: 4a8e ldr r2, [pc, #568] @ (8001cc8 ) 8001a90: 7813 ldrb r3, [r2, #0] 8001a92: f043 0302 orr.w r3, r3, #2 8001a96: 7013 strb r3, [r2, #0] 8001a98: e004 b.n 8001aa4 } else { error.group1.noload_acc_cooling = 0; 8001a9a: 4a8b ldr r2, [pc, #556] @ (8001cc8 ) 8001a9c: 7813 ldrb r3, [r2, #0] 8001a9e: f36f 0341 bfc r3, #1, #1 8001aa2: 7013 strb r3, [r2, #0] } if (update_ports.porta.ts_cooling == 1 && current_measurements_adc_val.ts_cooling == 0) { 8001aa4: 4b86 ldr r3, [pc, #536] @ (8001cc0 ) 8001aa6: 781b ldrb r3, [r3, #0] 8001aa8: f003 0302 and.w r3, r3, #2 8001aac: b2db uxtb r3, r3 8001aae: 2b00 cmp r3, #0 8001ab0: d009 beq.n 8001ac6 8001ab2: 4b86 ldr r3, [pc, #536] @ (8001ccc ) 8001ab4: 885b ldrh r3, [r3, #2] 8001ab6: 2b00 cmp r3, #0 8001ab8: d105 bne.n 8001ac6 error.group1.noload_ts_cooling = 1; 8001aba: 4a83 ldr r2, [pc, #524] @ (8001cc8 ) 8001abc: 7813 ldrb r3, [r2, #0] 8001abe: f043 0304 orr.w r3, r3, #4 8001ac2: 7013 strb r3, [r2, #0] 8001ac4: e004 b.n 8001ad0 } else { error.group1.noload_ts_cooling = 0; 8001ac6: 4a80 ldr r2, [pc, #512] @ (8001cc8 ) 8001ac8: 7813 ldrb r3, [r2, #0] 8001aca: f36f 0382 bfc r3, #2, #1 8001ace: 7013 strb r3, [r2, #0] } if (update_ports.porta.drs == 1 && current_measurements_adc_val.drs == 0) { 8001ad0: 4b7b ldr r3, [pc, #492] @ (8001cc0 ) 8001ad2: 781b ldrb r3, [r3, #0] 8001ad4: f003 0304 and.w r3, r3, #4 8001ad8: b2db uxtb r3, r3 8001ada: 2b00 cmp r3, #0 8001adc: d009 beq.n 8001af2 8001ade: 4b7b ldr r3, [pc, #492] @ (8001ccc ) 8001ae0: 889b ldrh r3, [r3, #4] 8001ae2: 2b00 cmp r3, #0 8001ae4: d105 bne.n 8001af2 error.group1.noload_drs = 1; 8001ae6: 4a78 ldr r2, [pc, #480] @ (8001cc8 ) 8001ae8: 7813 ldrb r3, [r2, #0] 8001aea: f043 0308 orr.w r3, r3, #8 8001aee: 7013 strb r3, [r2, #0] 8001af0: e004 b.n 8001afc } else { error.group1.noload_drs = 0; 8001af2: 4a75 ldr r2, [pc, #468] @ (8001cc8 ) 8001af4: 7813 ldrb r3, [r2, #0] 8001af6: f36f 03c3 bfc r3, #3, #1 8001afa: 7013 strb r3, [r2, #0] } if (update_ports.porta.acu == 1 && current_measurements_adc_val.acu == 0) { 8001afc: 4b70 ldr r3, [pc, #448] @ (8001cc0 ) 8001afe: 781b ldrb r3, [r3, #0] 8001b00: f003 0308 and.w r3, r3, #8 8001b04: b2db uxtb r3, r3 8001b06: 2b00 cmp r3, #0 8001b08: d009 beq.n 8001b1e 8001b0a: 4b70 ldr r3, [pc, #448] @ (8001ccc ) 8001b0c: 88db ldrh r3, [r3, #6] 8001b0e: 2b00 cmp r3, #0 8001b10: d105 bne.n 8001b1e error.group1.noload_acu = 1; 8001b12: 4a6d ldr r2, [pc, #436] @ (8001cc8 ) 8001b14: 7813 ldrb r3, [r2, #0] 8001b16: f043 0310 orr.w r3, r3, #16 8001b1a: 7013 strb r3, [r2, #0] 8001b1c: e004 b.n 8001b28 } else { error.group1.noload_acu = 0; 8001b1e: 4a6a ldr r2, [pc, #424] @ (8001cc8 ) 8001b20: 7813 ldrb r3, [r2, #0] 8001b22: f36f 1304 bfc r3, #4, #1 8001b26: 7013 strb r3, [r2, #0] } if (update_ports.porta.epsc == 1 && current_measurements_adc_val.epsc == 0) { 8001b28: 4b65 ldr r3, [pc, #404] @ (8001cc0 ) 8001b2a: 781b ldrb r3, [r3, #0] 8001b2c: f003 0310 and.w r3, r3, #16 8001b30: b2db uxtb r3, r3 8001b32: 2b00 cmp r3, #0 8001b34: d009 beq.n 8001b4a 8001b36: 4b65 ldr r3, [pc, #404] @ (8001ccc ) 8001b38: 891b ldrh r3, [r3, #8] 8001b3a: 2b00 cmp r3, #0 8001b3c: d105 bne.n 8001b4a error.group1.noload_epsc = 1; 8001b3e: 4a62 ldr r2, [pc, #392] @ (8001cc8 ) 8001b40: 7813 ldrb r3, [r2, #0] 8001b42: f043 0320 orr.w r3, r3, #32 8001b46: 7013 strb r3, [r2, #0] 8001b48: e004 b.n 8001b54 } else { error.group1.noload_epsc = 0; 8001b4a: 4a5f ldr r2, [pc, #380] @ (8001cc8 ) 8001b4c: 7813 ldrb r3, [r2, #0] 8001b4e: f36f 1345 bfc r3, #5, #1 8001b52: 7013 strb r3, [r2, #0] } if (update_ports.porta.inverter == 1 && current_measurements_adc_val.inverter == 0) { 8001b54: 4b5a ldr r3, [pc, #360] @ (8001cc0 ) 8001b56: 781b ldrb r3, [r3, #0] 8001b58: f003 0320 and.w r3, r3, #32 8001b5c: b2db uxtb r3, r3 8001b5e: 2b00 cmp r3, #0 8001b60: d009 beq.n 8001b76 8001b62: 4b5a ldr r3, [pc, #360] @ (8001ccc ) 8001b64: 895b ldrh r3, [r3, #10] 8001b66: 2b00 cmp r3, #0 8001b68: d105 bne.n 8001b76 error.group1.noload_inverter = 1; 8001b6a: 4a57 ldr r2, [pc, #348] @ (8001cc8 ) 8001b6c: 7813 ldrb r3, [r2, #0] 8001b6e: f043 0340 orr.w r3, r3, #64 @ 0x40 8001b72: 7013 strb r3, [r2, #0] 8001b74: e004 b.n 8001b80 } else { error.group1.noload_inverter = 0; 8001b76: 4a54 ldr r2, [pc, #336] @ (8001cc8 ) 8001b78: 7813 ldrb r3, [r2, #0] 8001b7a: f36f 1386 bfc r3, #6, #1 8001b7e: 7013 strb r3, [r2, #0] } if (update_ports.porta.lidar == 1 && current_measurements_adc_val.lidar == 0) { 8001b80: 4b4f ldr r3, [pc, #316] @ (8001cc0 ) 8001b82: 781b ldrb r3, [r3, #0] 8001b84: f003 0340 and.w r3, r3, #64 @ 0x40 8001b88: b2db uxtb r3, r3 8001b8a: 2b00 cmp r3, #0 8001b8c: d009 beq.n 8001ba2 8001b8e: 4b4f ldr r3, [pc, #316] @ (8001ccc ) 8001b90: 899b ldrh r3, [r3, #12] 8001b92: 2b00 cmp r3, #0 8001b94: d105 bne.n 8001ba2 error.group1.noload_lidar = 1; 8001b96: 4a4c ldr r2, [pc, #304] @ (8001cc8 ) 8001b98: 7813 ldrb r3, [r2, #0] 8001b9a: f043 0380 orr.w r3, r3, #128 @ 0x80 8001b9e: 7013 strb r3, [r2, #0] 8001ba0: e004 b.n 8001bac } else { error.group1.noload_lidar = 0; 8001ba2: 4a49 ldr r2, [pc, #292] @ (8001cc8 ) 8001ba4: 7813 ldrb r3, [r2, #0] 8001ba6: f36f 13c7 bfc r3, #7, #1 8001baa: 7013 strb r3, [r2, #0] } if (update_ports.porta.misc == 1 && current_measurements_adc_val.misc == 0) { 8001bac: 4b44 ldr r3, [pc, #272] @ (8001cc0 ) 8001bae: 781b ldrb r3, [r3, #0] 8001bb0: f023 037f bic.w r3, r3, #127 @ 0x7f 8001bb4: b2db uxtb r3, r3 8001bb6: 2b00 cmp r3, #0 8001bb8: d009 beq.n 8001bce 8001bba: 4b44 ldr r3, [pc, #272] @ (8001ccc ) 8001bbc: 89db ldrh r3, [r3, #14] 8001bbe: 2b00 cmp r3, #0 8001bc0: d105 bne.n 8001bce error.group2.noload_misc = 1; 8001bc2: 4a41 ldr r2, [pc, #260] @ (8001cc8 ) 8001bc4: 7853 ldrb r3, [r2, #1] 8001bc6: f043 0301 orr.w r3, r3, #1 8001bca: 7053 strb r3, [r2, #1] 8001bcc: e004 b.n 8001bd8 } else { error.group2.noload_misc = 0; 8001bce: 4a3e ldr r2, [pc, #248] @ (8001cc8 ) 8001bd0: 7853 ldrb r3, [r2, #1] 8001bd2: f36f 0300 bfc r3, #0, #1 8001bd6: 7053 strb r3, [r2, #1] } if (update_ports.portb.alwayson == 1 && current_measurements_adc_val.alwayson == 0) { 8001bd8: 4b39 ldr r3, [pc, #228] @ (8001cc0 ) 8001bda: 785b ldrb r3, [r3, #1] 8001bdc: f003 0301 and.w r3, r3, #1 8001be0: b2db uxtb r3, r3 8001be2: 2b00 cmp r3, #0 8001be4: d009 beq.n 8001bfa 8001be6: 4b39 ldr r3, [pc, #228] @ (8001ccc ) 8001be8: 8a1b ldrh r3, [r3, #16] 8001bea: 2b00 cmp r3, #0 8001bec: d105 bne.n 8001bfa error.group2.noload_alwayson = 1; 8001bee: 4a36 ldr r2, [pc, #216] @ (8001cc8 ) 8001bf0: 7853 ldrb r3, [r2, #1] 8001bf2: f043 0302 orr.w r3, r3, #2 8001bf6: 7053 strb r3, [r2, #1] 8001bf8: e004 b.n 8001c04 } else { error.group2.noload_alwayson = 0; 8001bfa: 4a33 ldr r2, [pc, #204] @ (8001cc8 ) 8001bfc: 7853 ldrb r3, [r2, #1] 8001bfe: f36f 0341 bfc r3, #1, #1 8001c02: 7053 strb r3, [r2, #1] } if (update_ports.portb.sdc == 1 && current_measurements_adc_val.sdc == 0) { 8001c04: 4b2e ldr r3, [pc, #184] @ (8001cc0 ) 8001c06: 785b ldrb r3, [r3, #1] 8001c08: f003 0302 and.w r3, r3, #2 8001c0c: b2db uxtb r3, r3 8001c0e: 2b00 cmp r3, #0 8001c10: d009 beq.n 8001c26 8001c12: 4b2e ldr r3, [pc, #184] @ (8001ccc ) 8001c14: 8a5b ldrh r3, [r3, #18] 8001c16: 2b00 cmp r3, #0 8001c18: d105 bne.n 8001c26 error.group2.noload_sdc = 1; 8001c1a: 4a2b ldr r2, [pc, #172] @ (8001cc8 ) 8001c1c: 7853 ldrb r3, [r2, #1] 8001c1e: f043 0304 orr.w r3, r3, #4 8001c22: 7053 strb r3, [r2, #1] 8001c24: e004 b.n 8001c30 } else { error.group2.noload_sdc = 0; 8001c26: 4a28 ldr r2, [pc, #160] @ (8001cc8 ) 8001c28: 7853 ldrb r3, [r2, #1] 8001c2a: f36f 0382 bfc r3, #2, #1 8001c2e: 7053 strb r3, [r2, #1] } if (update_ports.portb.ebs1 == 1 && current_measurements_adc_val.ebs1 == 0) { 8001c30: 4b23 ldr r3, [pc, #140] @ (8001cc0 ) 8001c32: 785b ldrb r3, [r3, #1] 8001c34: f003 0304 and.w r3, r3, #4 8001c38: b2db uxtb r3, r3 8001c3a: 2b00 cmp r3, #0 8001c3c: d009 beq.n 8001c52 8001c3e: 4b23 ldr r3, [pc, #140] @ (8001ccc ) 8001c40: 8a9b ldrh r3, [r3, #20] 8001c42: 2b00 cmp r3, #0 8001c44: d105 bne.n 8001c52 error.group2.noload_ebs1 = 1; 8001c46: 4a20 ldr r2, [pc, #128] @ (8001cc8 ) 8001c48: 7853 ldrb r3, [r2, #1] 8001c4a: f043 0308 orr.w r3, r3, #8 8001c4e: 7053 strb r3, [r2, #1] 8001c50: e004 b.n 8001c5c } else { error.group2.noload_ebs1 = 0; 8001c52: 4a1d ldr r2, [pc, #116] @ (8001cc8 ) 8001c54: 7853 ldrb r3, [r2, #1] 8001c56: f36f 03c3 bfc r3, #3, #1 8001c5a: 7053 strb r3, [r2, #1] } if (update_ports.portb.ebs2 == 1 && current_measurements_adc_val.ebs2 == 0) { 8001c5c: 4b18 ldr r3, [pc, #96] @ (8001cc0 ) 8001c5e: 785b ldrb r3, [r3, #1] 8001c60: f003 0308 and.w r3, r3, #8 8001c64: b2db uxtb r3, r3 8001c66: 2b00 cmp r3, #0 8001c68: d009 beq.n 8001c7e 8001c6a: 4b18 ldr r3, [pc, #96] @ (8001ccc ) 8001c6c: 8adb ldrh r3, [r3, #22] 8001c6e: 2b00 cmp r3, #0 8001c70: d105 bne.n 8001c7e error.group2.noload_ebs2 = 1; 8001c72: 4a15 ldr r2, [pc, #84] @ (8001cc8 ) 8001c74: 7853 ldrb r3, [r2, #1] 8001c76: f043 0310 orr.w r3, r3, #16 8001c7a: 7053 strb r3, [r2, #1] 8001c7c: e004 b.n 8001c88 } else { error.group2.noload_ebs2 = 0; 8001c7e: 4a12 ldr r2, [pc, #72] @ (8001cc8 ) 8001c80: 7853 ldrb r3, [r2, #1] 8001c82: f36f 1304 bfc r3, #4, #1 8001c86: 7053 strb r3, [r2, #1] } if (update_ports.portb.ebs3 == 1 && current_measurements_adc_val.ebs3 == 0) { 8001c88: 4b0d ldr r3, [pc, #52] @ (8001cc0 ) 8001c8a: 785b ldrb r3, [r3, #1] 8001c8c: f003 0310 and.w r3, r3, #16 8001c90: b2db uxtb r3, r3 8001c92: 2b00 cmp r3, #0 8001c94: d009 beq.n 8001caa 8001c96: 4b0d ldr r3, [pc, #52] @ (8001ccc ) 8001c98: 8b1b ldrh r3, [r3, #24] 8001c9a: 2b00 cmp r3, #0 8001c9c: d105 bne.n 8001caa error.group2.noload_ebs3 = 1; 8001c9e: 4a0a ldr r2, [pc, #40] @ (8001cc8 ) 8001ca0: 7853 ldrb r3, [r2, #1] 8001ca2: f043 0320 orr.w r3, r3, #32 8001ca6: 7053 strb r3, [r2, #1] 8001ca8: e005 b.n 8001cb6 } else { error.group2.noload_ebs3 = 0; 8001caa: 4a07 ldr r2, [pc, #28] @ (8001cc8 ) 8001cac: 7853 ldrb r3, [r2, #1] 8001cae: f36f 1345 bfc r3, #5, #1 8001cb2: 7053 strb r3, [r2, #1] } } 8001cb4: bf00 nop 8001cb6: bf00 nop 8001cb8: 46bd mov sp, r7 8001cba: f85d 7b04 ldr.w r7, [sp], #4 8001cbe: 4770 bx lr 8001cc0: 200002e8 .word 0x200002e8 8001cc4: 200002f0 .word 0x200002f0 8001cc8: 200002f4 .word 0x200002f4 8001ccc: 20000098 .word 0x20000098 08001cd0 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 8001cd0: b480 push {r7} 8001cd2: b083 sub sp, #12 8001cd4: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 8001cd6: 4b0f ldr r3, [pc, #60] @ (8001d14 ) 8001cd8: 699b ldr r3, [r3, #24] 8001cda: 4a0e ldr r2, [pc, #56] @ (8001d14 ) 8001cdc: f043 0301 orr.w r3, r3, #1 8001ce0: 6193 str r3, [r2, #24] 8001ce2: 4b0c ldr r3, [pc, #48] @ (8001d14 ) 8001ce4: 699b ldr r3, [r3, #24] 8001ce6: f003 0301 and.w r3, r3, #1 8001cea: 607b str r3, [r7, #4] 8001cec: 687b ldr r3, [r7, #4] __HAL_RCC_PWR_CLK_ENABLE(); 8001cee: 4b09 ldr r3, [pc, #36] @ (8001d14 ) 8001cf0: 69db ldr r3, [r3, #28] 8001cf2: 4a08 ldr r2, [pc, #32] @ (8001d14 ) 8001cf4: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8001cf8: 61d3 str r3, [r2, #28] 8001cfa: 4b06 ldr r3, [pc, #24] @ (8001d14 ) 8001cfc: 69db ldr r3, [r3, #28] 8001cfe: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8001d02: 603b str r3, [r7, #0] 8001d04: 683b ldr r3, [r7, #0] /* System interrupt init*/ /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 8001d06: bf00 nop 8001d08: 370c adds r7, #12 8001d0a: 46bd mov sp, r7 8001d0c: f85d 7b04 ldr.w r7, [sp], #4 8001d10: 4770 bx lr 8001d12: bf00 nop 8001d14: 40021000 .word 0x40021000 08001d18 : * This function configures the hardware resources used in this example * @param hadc: ADC handle pointer * @retval None */ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) { 8001d18: b580 push {r7, lr} 8001d1a: b08e sub sp, #56 @ 0x38 8001d1c: af00 add r7, sp, #0 8001d1e: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8001d20: f107 0324 add.w r3, r7, #36 @ 0x24 8001d24: 2200 movs r2, #0 8001d26: 601a str r2, [r3, #0] 8001d28: 605a str r2, [r3, #4] 8001d2a: 609a str r2, [r3, #8] 8001d2c: 60da str r2, [r3, #12] 8001d2e: 611a str r2, [r3, #16] if(hadc->Instance==ADC1) 8001d30: 687b ldr r3, [r7, #4] 8001d32: 681b ldr r3, [r3, #0] 8001d34: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 8001d38: f040 808f bne.w 8001e5a { /* USER CODE BEGIN ADC1_MspInit 0 */ /* USER CODE END ADC1_MspInit 0 */ /* Peripheral clock enable */ HAL_RCC_ADC12_CLK_ENABLED++; 8001d3c: 4b86 ldr r3, [pc, #536] @ (8001f58 ) 8001d3e: 681b ldr r3, [r3, #0] 8001d40: 3301 adds r3, #1 8001d42: 4a85 ldr r2, [pc, #532] @ (8001f58 ) 8001d44: 6013 str r3, [r2, #0] if(HAL_RCC_ADC12_CLK_ENABLED==1){ 8001d46: 4b84 ldr r3, [pc, #528] @ (8001f58 ) 8001d48: 681b ldr r3, [r3, #0] 8001d4a: 2b01 cmp r3, #1 8001d4c: d10b bne.n 8001d66 __HAL_RCC_ADC12_CLK_ENABLE(); 8001d4e: 4b83 ldr r3, [pc, #524] @ (8001f5c ) 8001d50: 695b ldr r3, [r3, #20] 8001d52: 4a82 ldr r2, [pc, #520] @ (8001f5c ) 8001d54: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8001d58: 6153 str r3, [r2, #20] 8001d5a: 4b80 ldr r3, [pc, #512] @ (8001f5c ) 8001d5c: 695b ldr r3, [r3, #20] 8001d5e: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8001d62: 623b str r3, [r7, #32] 8001d64: 6a3b ldr r3, [r7, #32] } __HAL_RCC_GPIOC_CLK_ENABLE(); 8001d66: 4b7d ldr r3, [pc, #500] @ (8001f5c ) 8001d68: 695b ldr r3, [r3, #20] 8001d6a: 4a7c ldr r2, [pc, #496] @ (8001f5c ) 8001d6c: f443 2300 orr.w r3, r3, #524288 @ 0x80000 8001d70: 6153 str r3, [r2, #20] 8001d72: 4b7a ldr r3, [pc, #488] @ (8001f5c ) 8001d74: 695b ldr r3, [r3, #20] 8001d76: f403 2300 and.w r3, r3, #524288 @ 0x80000 8001d7a: 61fb str r3, [r7, #28] 8001d7c: 69fb ldr r3, [r7, #28] __HAL_RCC_GPIOA_CLK_ENABLE(); 8001d7e: 4b77 ldr r3, [pc, #476] @ (8001f5c ) 8001d80: 695b ldr r3, [r3, #20] 8001d82: 4a76 ldr r2, [pc, #472] @ (8001f5c ) 8001d84: f443 3300 orr.w r3, r3, #131072 @ 0x20000 8001d88: 6153 str r3, [r2, #20] 8001d8a: 4b74 ldr r3, [pc, #464] @ (8001f5c ) 8001d8c: 695b ldr r3, [r3, #20] 8001d8e: f403 3300 and.w r3, r3, #131072 @ 0x20000 8001d92: 61bb str r3, [r7, #24] 8001d94: 69bb ldr r3, [r7, #24] __HAL_RCC_GPIOF_CLK_ENABLE(); 8001d96: 4b71 ldr r3, [pc, #452] @ (8001f5c ) 8001d98: 695b ldr r3, [r3, #20] 8001d9a: 4a70 ldr r2, [pc, #448] @ (8001f5c ) 8001d9c: f443 0380 orr.w r3, r3, #4194304 @ 0x400000 8001da0: 6153 str r3, [r2, #20] 8001da2: 4b6e ldr r3, [pc, #440] @ (8001f5c ) 8001da4: 695b ldr r3, [r3, #20] 8001da6: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8001daa: 617b str r3, [r7, #20] 8001dac: 697b ldr r3, [r7, #20] PA1 ------> ADC1_IN2 PA2 ------> ADC1_IN3 PA3 ------> ADC1_IN4 PF4 ------> ADC1_IN5 */ GPIO_InitStruct.Pin = LVMS_Vsense_Pin|IS10_Pin|IS6_Pin; 8001dae: 2307 movs r3, #7 8001db0: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8001db2: 2303 movs r3, #3 8001db4: 62bb str r3, [r7, #40] @ 0x28 GPIO_InitStruct.Pull = GPIO_NOPULL; 8001db6: 2300 movs r3, #0 8001db8: 62fb str r3, [r7, #44] @ 0x2c HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8001dba: f107 0324 add.w r3, r7, #36 @ 0x24 8001dbe: 4619 mov r1, r3 8001dc0: 4867 ldr r0, [pc, #412] @ (8001f60 ) 8001dc2: f002 fd43 bl 800484c GPIO_InitStruct.Pin = ASMS_Vsense_Pin|IS1_Pin|IS2_Pin|IS9_Pin; 8001dc6: 230f movs r3, #15 8001dc8: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8001dca: 2303 movs r3, #3 8001dcc: 62bb str r3, [r7, #40] @ 0x28 GPIO_InitStruct.Pull = GPIO_NOPULL; 8001dce: 2300 movs r3, #0 8001dd0: 62fb str r3, [r7, #44] @ 0x2c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8001dd2: f107 0324 add.w r3, r7, #36 @ 0x24 8001dd6: 4619 mov r1, r3 8001dd8: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 8001ddc: f002 fd36 bl 800484c GPIO_InitStruct.Pin = IS11_Pin; 8001de0: 2310 movs r3, #16 8001de2: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8001de4: 2303 movs r3, #3 8001de6: 62bb str r3, [r7, #40] @ 0x28 GPIO_InitStruct.Pull = GPIO_NOPULL; 8001de8: 2300 movs r3, #0 8001dea: 62fb str r3, [r7, #44] @ 0x2c HAL_GPIO_Init(IS11_GPIO_Port, &GPIO_InitStruct); 8001dec: f107 0324 add.w r3, r7, #36 @ 0x24 8001df0: 4619 mov r1, r3 8001df2: 485c ldr r0, [pc, #368] @ (8001f64 ) 8001df4: f002 fd2a bl 800484c /* ADC1 DMA Init */ /* ADC1 Init */ hdma_adc1.Instance = DMA1_Channel1; 8001df8: 4b5b ldr r3, [pc, #364] @ (8001f68 ) 8001dfa: 4a5c ldr r2, [pc, #368] @ (8001f6c ) 8001dfc: 601a str r2, [r3, #0] hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY; 8001dfe: 4b5a ldr r3, [pc, #360] @ (8001f68 ) 8001e00: 2200 movs r2, #0 8001e02: 605a str r2, [r3, #4] hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE; 8001e04: 4b58 ldr r3, [pc, #352] @ (8001f68 ) 8001e06: 2200 movs r2, #0 8001e08: 609a str r2, [r3, #8] hdma_adc1.Init.MemInc = DMA_MINC_ENABLE; 8001e0a: 4b57 ldr r3, [pc, #348] @ (8001f68 ) 8001e0c: 2280 movs r2, #128 @ 0x80 8001e0e: 60da str r2, [r3, #12] hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; 8001e10: 4b55 ldr r3, [pc, #340] @ (8001f68 ) 8001e12: f44f 7280 mov.w r2, #256 @ 0x100 8001e16: 611a str r2, [r3, #16] hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; 8001e18: 4b53 ldr r3, [pc, #332] @ (8001f68 ) 8001e1a: f44f 6280 mov.w r2, #1024 @ 0x400 8001e1e: 615a str r2, [r3, #20] hdma_adc1.Init.Mode = DMA_CIRCULAR; 8001e20: 4b51 ldr r3, [pc, #324] @ (8001f68 ) 8001e22: 2220 movs r2, #32 8001e24: 619a str r2, [r3, #24] hdma_adc1.Init.Priority = DMA_PRIORITY_LOW; 8001e26: 4b50 ldr r3, [pc, #320] @ (8001f68 ) 8001e28: 2200 movs r2, #0 8001e2a: 61da str r2, [r3, #28] if (HAL_DMA_Init(&hdma_adc1) != HAL_OK) 8001e2c: 484e ldr r0, [pc, #312] @ (8001f68 ) 8001e2e: f002 fb5a bl 80044e6 8001e32: 4603 mov r3, r0 8001e34: 2b00 cmp r3, #0 8001e36: d001 beq.n 8001e3c { Error_Handler(); 8001e38: f7ff fe00 bl 8001a3c } __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc1); 8001e3c: 687b ldr r3, [r7, #4] 8001e3e: 4a4a ldr r2, [pc, #296] @ (8001f68 ) 8001e40: 639a str r2, [r3, #56] @ 0x38 8001e42: 4a49 ldr r2, [pc, #292] @ (8001f68 ) 8001e44: 687b ldr r3, [r7, #4] 8001e46: 6253 str r3, [r2, #36] @ 0x24 /* ADC1 interrupt Init */ HAL_NVIC_SetPriority(ADC1_2_IRQn, 0, 0); 8001e48: 2200 movs r2, #0 8001e4a: 2100 movs r1, #0 8001e4c: 2012 movs r0, #18 8001e4e: f002 fb14 bl 800447a HAL_NVIC_EnableIRQ(ADC1_2_IRQn); 8001e52: 2012 movs r0, #18 8001e54: f002 fb2d bl 80044b2 /* USER CODE BEGIN ADC2_MspInit 1 */ /* USER CODE END ADC2_MspInit 1 */ } } 8001e58: e07a b.n 8001f50 else if(hadc->Instance==ADC2) 8001e5a: 687b ldr r3, [r7, #4] 8001e5c: 681b ldr r3, [r3, #0] 8001e5e: 4a44 ldr r2, [pc, #272] @ (8001f70 ) 8001e60: 4293 cmp r3, r2 8001e62: d175 bne.n 8001f50 HAL_RCC_ADC12_CLK_ENABLED++; 8001e64: 4b3c ldr r3, [pc, #240] @ (8001f58 ) 8001e66: 681b ldr r3, [r3, #0] 8001e68: 3301 adds r3, #1 8001e6a: 4a3b ldr r2, [pc, #236] @ (8001f58 ) 8001e6c: 6013 str r3, [r2, #0] if(HAL_RCC_ADC12_CLK_ENABLED==1){ 8001e6e: 4b3a ldr r3, [pc, #232] @ (8001f58 ) 8001e70: 681b ldr r3, [r3, #0] 8001e72: 2b01 cmp r3, #1 8001e74: d10b bne.n 8001e8e __HAL_RCC_ADC12_CLK_ENABLE(); 8001e76: 4b39 ldr r3, [pc, #228] @ (8001f5c ) 8001e78: 695b ldr r3, [r3, #20] 8001e7a: 4a38 ldr r2, [pc, #224] @ (8001f5c ) 8001e7c: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8001e80: 6153 str r3, [r2, #20] 8001e82: 4b36 ldr r3, [pc, #216] @ (8001f5c ) 8001e84: 695b ldr r3, [r3, #20] 8001e86: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8001e8a: 613b str r3, [r7, #16] 8001e8c: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOC_CLK_ENABLE(); 8001e8e: 4b33 ldr r3, [pc, #204] @ (8001f5c ) 8001e90: 695b ldr r3, [r3, #20] 8001e92: 4a32 ldr r2, [pc, #200] @ (8001f5c ) 8001e94: f443 2300 orr.w r3, r3, #524288 @ 0x80000 8001e98: 6153 str r3, [r2, #20] 8001e9a: 4b30 ldr r3, [pc, #192] @ (8001f5c ) 8001e9c: 695b ldr r3, [r3, #20] 8001e9e: f403 2300 and.w r3, r3, #524288 @ 0x80000 8001ea2: 60fb str r3, [r7, #12] 8001ea4: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOA_CLK_ENABLE(); 8001ea6: 4b2d ldr r3, [pc, #180] @ (8001f5c ) 8001ea8: 695b ldr r3, [r3, #20] 8001eaa: 4a2c ldr r2, [pc, #176] @ (8001f5c ) 8001eac: f443 3300 orr.w r3, r3, #131072 @ 0x20000 8001eb0: 6153 str r3, [r2, #20] 8001eb2: 4b2a ldr r3, [pc, #168] @ (8001f5c ) 8001eb4: 695b ldr r3, [r3, #20] 8001eb6: f403 3300 and.w r3, r3, #131072 @ 0x20000 8001eba: 60bb str r3, [r7, #8] 8001ebc: 68bb ldr r3, [r7, #8] GPIO_InitStruct.Pin = IS7_Pin|PC_Read_Pin; 8001ebe: 2318 movs r3, #24 8001ec0: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8001ec2: 2303 movs r3, #3 8001ec4: 62bb str r3, [r7, #40] @ 0x28 GPIO_InitStruct.Pull = GPIO_NOPULL; 8001ec6: 2300 movs r3, #0 8001ec8: 62fb str r3, [r7, #44] @ 0x2c HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8001eca: f107 0324 add.w r3, r7, #36 @ 0x24 8001ece: 4619 mov r1, r3 8001ed0: 4823 ldr r0, [pc, #140] @ (8001f60 ) 8001ed2: f002 fcbb bl 800484c GPIO_InitStruct.Pin = IS3_Pin|IS8_Pin|IS4_Pin|IS5_Pin; 8001ed6: 23f0 movs r3, #240 @ 0xf0 8001ed8: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8001eda: 2303 movs r3, #3 8001edc: 62bb str r3, [r7, #40] @ 0x28 GPIO_InitStruct.Pull = GPIO_NOPULL; 8001ede: 2300 movs r3, #0 8001ee0: 62fb str r3, [r7, #44] @ 0x2c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8001ee2: f107 0324 add.w r3, r7, #36 @ 0x24 8001ee6: 4619 mov r1, r3 8001ee8: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 8001eec: f002 fcae bl 800484c hdma_adc2.Instance = DMA2_Channel1; 8001ef0: 4b20 ldr r3, [pc, #128] @ (8001f74 ) 8001ef2: 4a21 ldr r2, [pc, #132] @ (8001f78 ) 8001ef4: 601a str r2, [r3, #0] hdma_adc2.Init.Direction = DMA_PERIPH_TO_MEMORY; 8001ef6: 4b1f ldr r3, [pc, #124] @ (8001f74 ) 8001ef8: 2200 movs r2, #0 8001efa: 605a str r2, [r3, #4] hdma_adc2.Init.PeriphInc = DMA_PINC_DISABLE; 8001efc: 4b1d ldr r3, [pc, #116] @ (8001f74 ) 8001efe: 2200 movs r2, #0 8001f00: 609a str r2, [r3, #8] hdma_adc2.Init.MemInc = DMA_MINC_ENABLE; 8001f02: 4b1c ldr r3, [pc, #112] @ (8001f74 ) 8001f04: 2280 movs r2, #128 @ 0x80 8001f06: 60da str r2, [r3, #12] hdma_adc2.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; 8001f08: 4b1a ldr r3, [pc, #104] @ (8001f74 ) 8001f0a: f44f 7280 mov.w r2, #256 @ 0x100 8001f0e: 611a str r2, [r3, #16] hdma_adc2.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; 8001f10: 4b18 ldr r3, [pc, #96] @ (8001f74 ) 8001f12: f44f 6280 mov.w r2, #1024 @ 0x400 8001f16: 615a str r2, [r3, #20] hdma_adc2.Init.Mode = DMA_CIRCULAR; 8001f18: 4b16 ldr r3, [pc, #88] @ (8001f74 ) 8001f1a: 2220 movs r2, #32 8001f1c: 619a str r2, [r3, #24] hdma_adc2.Init.Priority = DMA_PRIORITY_LOW; 8001f1e: 4b15 ldr r3, [pc, #84] @ (8001f74 ) 8001f20: 2200 movs r2, #0 8001f22: 61da str r2, [r3, #28] if (HAL_DMA_Init(&hdma_adc2) != HAL_OK) 8001f24: 4813 ldr r0, [pc, #76] @ (8001f74 ) 8001f26: f002 fade bl 80044e6 8001f2a: 4603 mov r3, r0 8001f2c: 2b00 cmp r3, #0 8001f2e: d001 beq.n 8001f34 Error_Handler(); 8001f30: f7ff fd84 bl 8001a3c __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc2); 8001f34: 687b ldr r3, [r7, #4] 8001f36: 4a0f ldr r2, [pc, #60] @ (8001f74 ) 8001f38: 639a str r2, [r3, #56] @ 0x38 8001f3a: 4a0e ldr r2, [pc, #56] @ (8001f74 ) 8001f3c: 687b ldr r3, [r7, #4] 8001f3e: 6253 str r3, [r2, #36] @ 0x24 HAL_NVIC_SetPriority(ADC1_2_IRQn, 0, 0); 8001f40: 2200 movs r2, #0 8001f42: 2100 movs r1, #0 8001f44: 2012 movs r0, #18 8001f46: f002 fa98 bl 800447a HAL_NVIC_EnableIRQ(ADC1_2_IRQn); 8001f4a: 2012 movs r0, #18 8001f4c: f002 fab1 bl 80044b2 } 8001f50: bf00 nop 8001f52: 3738 adds r7, #56 @ 0x38 8001f54: 46bd mov sp, r7 8001f56: bd80 pop {r7, pc} 8001f58: 200002f8 .word 0x200002f8 8001f5c: 40021000 .word 0x40021000 8001f60: 48000800 .word 0x48000800 8001f64: 48001400 .word 0x48001400 8001f68: 20000164 .word 0x20000164 8001f6c: 40020008 .word 0x40020008 8001f70: 50000100 .word 0x50000100 8001f74: 200001a8 .word 0x200001a8 8001f78: 40020408 .word 0x40020408 08001f7c : * This function configures the hardware resources used in this example * @param hcan: CAN handle pointer * @retval None */ void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan) { 8001f7c: b580 push {r7, lr} 8001f7e: b08a sub sp, #40 @ 0x28 8001f80: af00 add r7, sp, #0 8001f82: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8001f84: f107 0314 add.w r3, r7, #20 8001f88: 2200 movs r2, #0 8001f8a: 601a str r2, [r3, #0] 8001f8c: 605a str r2, [r3, #4] 8001f8e: 609a str r2, [r3, #8] 8001f90: 60da str r2, [r3, #12] 8001f92: 611a str r2, [r3, #16] if(hcan->Instance==CAN) 8001f94: 687b ldr r3, [r7, #4] 8001f96: 681b ldr r3, [r3, #0] 8001f98: 4a20 ldr r2, [pc, #128] @ (800201c ) 8001f9a: 4293 cmp r3, r2 8001f9c: d139 bne.n 8002012 { /* USER CODE BEGIN CAN_MspInit 0 */ /* USER CODE END CAN_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_CAN1_CLK_ENABLE(); 8001f9e: 4b20 ldr r3, [pc, #128] @ (8002020 ) 8001fa0: 69db ldr r3, [r3, #28] 8001fa2: 4a1f ldr r2, [pc, #124] @ (8002020 ) 8001fa4: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 8001fa8: 61d3 str r3, [r2, #28] 8001faa: 4b1d ldr r3, [pc, #116] @ (8002020 ) 8001fac: 69db ldr r3, [r3, #28] 8001fae: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8001fb2: 613b str r3, [r7, #16] 8001fb4: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); 8001fb6: 4b1a ldr r3, [pc, #104] @ (8002020 ) 8001fb8: 695b ldr r3, [r3, #20] 8001fba: 4a19 ldr r2, [pc, #100] @ (8002020 ) 8001fbc: f443 3300 orr.w r3, r3, #131072 @ 0x20000 8001fc0: 6153 str r3, [r2, #20] 8001fc2: 4b17 ldr r3, [pc, #92] @ (8002020 ) 8001fc4: 695b ldr r3, [r3, #20] 8001fc6: f403 3300 and.w r3, r3, #131072 @ 0x20000 8001fca: 60fb str r3, [r7, #12] 8001fcc: 68fb ldr r3, [r7, #12] /**CAN GPIO Configuration PA11 ------> CAN_RX PA12 ------> CAN_TX */ GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12; 8001fce: f44f 53c0 mov.w r3, #6144 @ 0x1800 8001fd2: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001fd4: 2302 movs r3, #2 8001fd6: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001fd8: 2300 movs r3, #0 8001fda: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8001fdc: 2303 movs r3, #3 8001fde: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF9_CAN; 8001fe0: 2309 movs r3, #9 8001fe2: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8001fe4: f107 0314 add.w r3, r7, #20 8001fe8: 4619 mov r1, r3 8001fea: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 8001fee: f002 fc2d bl 800484c /* CAN interrupt Init */ HAL_NVIC_SetPriority(USB_LP_CAN_RX0_IRQn, 0, 0); 8001ff2: 2200 movs r2, #0 8001ff4: 2100 movs r1, #0 8001ff6: 2014 movs r0, #20 8001ff8: f002 fa3f bl 800447a HAL_NVIC_EnableIRQ(USB_LP_CAN_RX0_IRQn); 8001ffc: 2014 movs r0, #20 8001ffe: f002 fa58 bl 80044b2 HAL_NVIC_SetPriority(CAN_RX1_IRQn, 0, 0); 8002002: 2200 movs r2, #0 8002004: 2100 movs r1, #0 8002006: 2015 movs r0, #21 8002008: f002 fa37 bl 800447a HAL_NVIC_EnableIRQ(CAN_RX1_IRQn); 800200c: 2015 movs r0, #21 800200e: f002 fa50 bl 80044b2 /* USER CODE END CAN_MspInit 1 */ } } 8002012: bf00 nop 8002014: 3728 adds r7, #40 @ 0x28 8002016: 46bd mov sp, r7 8002018: bd80 pop {r7, pc} 800201a: bf00 nop 800201c: 40006400 .word 0x40006400 8002020: 40021000 .word 0x40021000 08002024 : * This function configures the hardware resources used in this example * @param htim_base: TIM_Base handle pointer * @retval None */ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) { 8002024: b580 push {r7, lr} 8002026: b084 sub sp, #16 8002028: af00 add r7, sp, #0 800202a: 6078 str r0, [r7, #4] if(htim_base->Instance==TIM6) 800202c: 687b ldr r3, [r7, #4] 800202e: 681b ldr r3, [r3, #0] 8002030: 4a0d ldr r2, [pc, #52] @ (8002068 ) 8002032: 4293 cmp r3, r2 8002034: d113 bne.n 800205e { /* USER CODE BEGIN TIM6_MspInit 0 */ /* USER CODE END TIM6_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_TIM6_CLK_ENABLE(); 8002036: 4b0d ldr r3, [pc, #52] @ (800206c ) 8002038: 69db ldr r3, [r3, #28] 800203a: 4a0c ldr r2, [pc, #48] @ (800206c ) 800203c: f043 0310 orr.w r3, r3, #16 8002040: 61d3 str r3, [r2, #28] 8002042: 4b0a ldr r3, [pc, #40] @ (800206c ) 8002044: 69db ldr r3, [r3, #28] 8002046: f003 0310 and.w r3, r3, #16 800204a: 60fb str r3, [r7, #12] 800204c: 68fb ldr r3, [r7, #12] /* TIM6 interrupt Init */ HAL_NVIC_SetPriority(TIM6_DAC_IRQn, 0, 0); 800204e: 2200 movs r2, #0 8002050: 2100 movs r1, #0 8002052: 2036 movs r0, #54 @ 0x36 8002054: f002 fa11 bl 800447a HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn); 8002058: 2036 movs r0, #54 @ 0x36 800205a: f002 fa2a bl 80044b2 /* USER CODE END TIM6_MspInit 1 */ } } 800205e: bf00 nop 8002060: 3710 adds r7, #16 8002062: 46bd mov sp, r7 8002064: bd80 pop {r7, pc} 8002066: bf00 nop 8002068: 40001000 .word 0x40001000 800206c: 40021000 .word 0x40021000 08002070 : * This function configures the hardware resources used in this example * @param huart: UART handle pointer * @retval None */ void HAL_UART_MspInit(UART_HandleTypeDef* huart) { 8002070: b580 push {r7, lr} 8002072: b08a sub sp, #40 @ 0x28 8002074: af00 add r7, sp, #0 8002076: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8002078: f107 0314 add.w r3, r7, #20 800207c: 2200 movs r2, #0 800207e: 601a str r2, [r3, #0] 8002080: 605a str r2, [r3, #4] 8002082: 609a str r2, [r3, #8] 8002084: 60da str r2, [r3, #12] 8002086: 611a str r2, [r3, #16] if(huart->Instance==UART4) 8002088: 687b ldr r3, [r7, #4] 800208a: 681b ldr r3, [r3, #0] 800208c: 4a17 ldr r2, [pc, #92] @ (80020ec ) 800208e: 4293 cmp r3, r2 8002090: d128 bne.n 80020e4 { /* USER CODE BEGIN UART4_MspInit 0 */ /* USER CODE END UART4_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_UART4_CLK_ENABLE(); 8002092: 4b17 ldr r3, [pc, #92] @ (80020f0 ) 8002094: 69db ldr r3, [r3, #28] 8002096: 4a16 ldr r2, [pc, #88] @ (80020f0 ) 8002098: f443 2300 orr.w r3, r3, #524288 @ 0x80000 800209c: 61d3 str r3, [r2, #28] 800209e: 4b14 ldr r3, [pc, #80] @ (80020f0 ) 80020a0: 69db ldr r3, [r3, #28] 80020a2: f403 2300 and.w r3, r3, #524288 @ 0x80000 80020a6: 613b str r3, [r7, #16] 80020a8: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOC_CLK_ENABLE(); 80020aa: 4b11 ldr r3, [pc, #68] @ (80020f0 ) 80020ac: 695b ldr r3, [r3, #20] 80020ae: 4a10 ldr r2, [pc, #64] @ (80020f0 ) 80020b0: f443 2300 orr.w r3, r3, #524288 @ 0x80000 80020b4: 6153 str r3, [r2, #20] 80020b6: 4b0e ldr r3, [pc, #56] @ (80020f0 ) 80020b8: 695b ldr r3, [r3, #20] 80020ba: f403 2300 and.w r3, r3, #524288 @ 0x80000 80020be: 60fb str r3, [r7, #12] 80020c0: 68fb ldr r3, [r7, #12] /**UART4 GPIO Configuration PC10 ------> UART4_TX PC11 ------> UART4_RX */ GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11; 80020c2: f44f 6340 mov.w r3, #3072 @ 0xc00 80020c6: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80020c8: 2302 movs r3, #2 80020ca: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 80020cc: 2300 movs r3, #0 80020ce: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 80020d0: 2303 movs r3, #3 80020d2: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF5_UART4; 80020d4: 2305 movs r3, #5 80020d6: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 80020d8: f107 0314 add.w r3, r7, #20 80020dc: 4619 mov r1, r3 80020de: 4805 ldr r0, [pc, #20] @ (80020f4 ) 80020e0: f002 fbb4 bl 800484c /* USER CODE END UART4_MspInit 1 */ } } 80020e4: bf00 nop 80020e6: 3728 adds r7, #40 @ 0x28 80020e8: 46bd mov sp, r7 80020ea: bd80 pop {r7, pc} 80020ec: 40004c00 .word 0x40004c00 80020f0: 40021000 .word 0x40021000 80020f4: 48000800 .word 0x48000800 080020f8 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 80020f8: b480 push {r7} 80020fa: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 80020fc: bf00 nop 80020fe: e7fd b.n 80020fc 08002100 : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 8002100: b480 push {r7} 8002102: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 8002104: bf00 nop 8002106: e7fd b.n 8002104 08002108 : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 8002108: b480 push {r7} 800210a: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 800210c: bf00 nop 800210e: e7fd b.n 800210c 08002110 : /** * @brief This function handles Pre-fetch fault, memory access fault. */ void BusFault_Handler(void) { 8002110: b480 push {r7} 8002112: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 8002114: bf00 nop 8002116: e7fd b.n 8002114 08002118 : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 8002118: b480 push {r7} 800211a: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 800211c: bf00 nop 800211e: e7fd b.n 800211c 08002120 : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 8002120: b480 push {r7} 8002122: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 8002124: bf00 nop 8002126: 46bd mov sp, r7 8002128: f85d 7b04 ldr.w r7, [sp], #4 800212c: 4770 bx lr 0800212e : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 800212e: b480 push {r7} 8002130: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 8002132: bf00 nop 8002134: 46bd mov sp, r7 8002136: f85d 7b04 ldr.w r7, [sp], #4 800213a: 4770 bx lr 0800213c : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 800213c: b480 push {r7} 800213e: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 8002140: bf00 nop 8002142: 46bd mov sp, r7 8002144: f85d 7b04 ldr.w r7, [sp], #4 8002148: 4770 bx lr 0800214a : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 800214a: b580 push {r7, lr} 800214c: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 800214e: f000 f8c5 bl 80022dc /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 8002152: bf00 nop 8002154: bd80 pop {r7, pc} ... 08002158 : /** * @brief This function handles DMA1 channel1 global interrupt. */ void DMA1_Channel1_IRQHandler(void) { 8002158: b580 push {r7, lr} 800215a: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Channel1_IRQn 0 */ /* USER CODE END DMA1_Channel1_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_adc1); 800215c: 4802 ldr r0, [pc, #8] @ (8002168 ) 800215e: f002 fa68 bl 8004632 /* USER CODE BEGIN DMA1_Channel1_IRQn 1 */ /* USER CODE END DMA1_Channel1_IRQn 1 */ } 8002162: bf00 nop 8002164: bd80 pop {r7, pc} 8002166: bf00 nop 8002168: 20000164 .word 0x20000164 0800216c : /** * @brief This function handles ADC1 and ADC2 interrupts. */ void ADC1_2_IRQHandler(void) { 800216c: b580 push {r7, lr} 800216e: af00 add r7, sp, #0 /* USER CODE BEGIN ADC1_2_IRQn 0 */ /* USER CODE END ADC1_2_IRQn 0 */ HAL_ADC_IRQHandler(&hadc1); 8002170: 4803 ldr r0, [pc, #12] @ (8002180 ) 8002172: f000 fb81 bl 8002878 HAL_ADC_IRQHandler(&hadc2); 8002176: 4803 ldr r0, [pc, #12] @ (8002184 ) 8002178: f000 fb7e bl 8002878 /* USER CODE BEGIN ADC1_2_IRQn 1 */ /* USER CODE END ADC1_2_IRQn 1 */ } 800217c: bf00 nop 800217e: bd80 pop {r7, pc} 8002180: 200000c4 .word 0x200000c4 8002184: 20000114 .word 0x20000114 08002188 : /** * @brief This function handles USB low priority or CAN_RX0 interrupts. */ void USB_LP_CAN_RX0_IRQHandler(void) { 8002188: b580 push {r7, lr} 800218a: af00 add r7, sp, #0 /* USER CODE BEGIN USB_LP_CAN_RX0_IRQn 0 */ /* USER CODE END USB_LP_CAN_RX0_IRQn 0 */ HAL_CAN_IRQHandler(&hcan); 800218c: 4802 ldr r0, [pc, #8] @ (8002198 ) 800218e: f001 fe6a bl 8003e66 /* USER CODE BEGIN USB_LP_CAN_RX0_IRQn 1 */ /* USER CODE END USB_LP_CAN_RX0_IRQn 1 */ } 8002192: bf00 nop 8002194: bd80 pop {r7, pc} 8002196: bf00 nop 8002198: 200001ec .word 0x200001ec 0800219c : /** * @brief This function handles CAN RX1 interrupt. */ void CAN_RX1_IRQHandler(void) { 800219c: b580 push {r7, lr} 800219e: af00 add r7, sp, #0 /* USER CODE BEGIN CAN_RX1_IRQn 0 */ /* USER CODE END CAN_RX1_IRQn 0 */ HAL_CAN_IRQHandler(&hcan); 80021a0: 4802 ldr r0, [pc, #8] @ (80021ac ) 80021a2: f001 fe60 bl 8003e66 /* USER CODE BEGIN CAN_RX1_IRQn 1 */ /* USER CODE END CAN_RX1_IRQn 1 */ } 80021a6: bf00 nop 80021a8: bd80 pop {r7, pc} 80021aa: bf00 nop 80021ac: 200001ec .word 0x200001ec 080021b0 : /** * @brief This function handles Timer 6 interrupt and DAC underrun interrupts. */ void TIM6_DAC_IRQHandler(void) { 80021b0: b580 push {r7, lr} 80021b2: af00 add r7, sp, #0 /* USER CODE BEGIN TIM6_DAC_IRQn 0 */ /* USER CODE END TIM6_DAC_IRQn 0 */ HAL_TIM_IRQHandler(&htim6); 80021b4: 4802 ldr r0, [pc, #8] @ (80021c0 ) 80021b6: f004 f97f bl 80064b8 /* USER CODE BEGIN TIM6_DAC_IRQn 1 */ /* USER CODE END TIM6_DAC_IRQn 1 */ } 80021ba: bf00 nop 80021bc: bd80 pop {r7, pc} 80021be: bf00 nop 80021c0: 20000214 .word 0x20000214 080021c4 : /** * @brief This function handles DMA2 channel1 global interrupt. */ void DMA2_Channel1_IRQHandler(void) { 80021c4: b580 push {r7, lr} 80021c6: af00 add r7, sp, #0 /* USER CODE BEGIN DMA2_Channel1_IRQn 0 */ /* USER CODE END DMA2_Channel1_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_adc2); 80021c8: 4802 ldr r0, [pc, #8] @ (80021d4 ) 80021ca: f002 fa32 bl 8004632 /* USER CODE BEGIN DMA2_Channel1_IRQn 1 */ /* USER CODE END DMA2_Channel1_IRQn 1 */ } 80021ce: bf00 nop 80021d0: bd80 pop {r7, pc} 80021d2: bf00 nop 80021d4: 200001a8 .word 0x200001a8 080021d8 : * @brief Setup the microcontroller system * @param None * @retval None */ void SystemInit(void) { 80021d8: b480 push {r7} 80021da: af00 add r7, sp, #0 /* FPU settings --------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ 80021dc: 4b06 ldr r3, [pc, #24] @ (80021f8 ) 80021de: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 80021e2: 4a05 ldr r2, [pc, #20] @ (80021f8 ) 80021e4: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000 80021e8: f8c2 3088 str.w r3, [r2, #136] @ 0x88 /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ #endif /* USER_VECT_TAB_ADDRESS */ } 80021ec: bf00 nop 80021ee: 46bd mov sp, r7 80021f0: f85d 7b04 ldr.w r7, [sp], #4 80021f4: 4770 bx lr 80021f6: bf00 nop 80021f8: e000ed00 .word 0xe000ed00 080021fc : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr sp, =_estack /* Atollic update: set stack pointer */ 80021fc: f8df d034 ldr.w sp, [pc, #52] @ 8002234 /* Call the clock system initialization function.*/ bl SystemInit 8002200: f7ff ffea bl 80021d8 /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 8002204: 480c ldr r0, [pc, #48] @ (8002238 ) ldr r1, =_edata 8002206: 490d ldr r1, [pc, #52] @ (800223c ) ldr r2, =_sidata 8002208: 4a0d ldr r2, [pc, #52] @ (8002240 ) movs r3, #0 800220a: 2300 movs r3, #0 b LoopCopyDataInit 800220c: e002 b.n 8002214 0800220e : CopyDataInit: ldr r4, [r2, r3] 800220e: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 8002210: 50c4 str r4, [r0, r3] adds r3, r3, #4 8002212: 3304 adds r3, #4 08002214 : LoopCopyDataInit: adds r4, r0, r3 8002214: 18c4 adds r4, r0, r3 cmp r4, r1 8002216: 428c cmp r4, r1 bcc CopyDataInit 8002218: d3f9 bcc.n 800220e /* Zero fill the bss segment. */ ldr r2, =_sbss 800221a: 4a0a ldr r2, [pc, #40] @ (8002244 ) ldr r4, =_ebss 800221c: 4c0a ldr r4, [pc, #40] @ (8002248 ) movs r3, #0 800221e: 2300 movs r3, #0 b LoopFillZerobss 8002220: e001 b.n 8002226 08002222 : FillZerobss: str r3, [r2] 8002222: 6013 str r3, [r2, #0] adds r2, r2, #4 8002224: 3204 adds r2, #4 08002226 : LoopFillZerobss: cmp r2, r4 8002226: 42a2 cmp r2, r4 bcc FillZerobss 8002228: d3fb bcc.n 8002222 /* Call static constructors */ bl __libc_init_array 800222a: f004 ffdf bl 80071ec <__libc_init_array> /* Call the application's entry point.*/ bl main 800222e: f7fe ffed bl 800120c
08002232 : LoopForever: b LoopForever 8002232: e7fe b.n 8002232 ldr sp, =_estack /* Atollic update: set stack pointer */ 8002234: 20008000 .word 0x20008000 ldr r0, =_sdata 8002238: 20000000 .word 0x20000000 ldr r1, =_edata 800223c: 2000000c .word 0x2000000c ldr r2, =_sidata 8002240: 0800728c .word 0x0800728c ldr r2, =_sbss 8002244: 2000000c .word 0x2000000c ldr r4, =_ebss 8002248: 20000300 .word 0x20000300 0800224c : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 800224c: e7fe b.n 800224c ... 08002250 : * In the default implementation,Systick is used as source of time base. * The tick variable is incremented each 1ms in its ISR. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 8002250: b580 push {r7, lr} 8002252: af00 add r7, sp, #0 /* Configure Flash prefetch */ #if (PREFETCH_ENABLE != 0U) __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 8002254: 4b08 ldr r3, [pc, #32] @ (8002278 ) 8002256: 681b ldr r3, [r3, #0] 8002258: 4a07 ldr r2, [pc, #28] @ (8002278 ) 800225a: f043 0310 orr.w r3, r3, #16 800225e: 6013 str r3, [r2, #0] #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 8002260: 2003 movs r0, #3 8002262: f002 f8ff bl 8004464 /* Enable systick and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 8002266: 200f movs r0, #15 8002268: f000 f808 bl 800227c /* Init the low level hardware */ HAL_MspInit(); 800226c: f7ff fd30 bl 8001cd0 /* Return function status */ return HAL_OK; 8002270: 2300 movs r3, #0 } 8002272: 4618 mov r0, r3 8002274: bd80 pop {r7, pc} 8002276: bf00 nop 8002278: 40022000 .word 0x40022000 0800227c : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 800227c: b580 push {r7, lr} 800227e: b082 sub sp, #8 8002280: af00 add r7, sp, #0 8002282: 6078 str r0, [r7, #4] /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 8002284: 4b12 ldr r3, [pc, #72] @ (80022d0 ) 8002286: 681a ldr r2, [r3, #0] 8002288: 4b12 ldr r3, [pc, #72] @ (80022d4 ) 800228a: 781b ldrb r3, [r3, #0] 800228c: 4619 mov r1, r3 800228e: f44f 737a mov.w r3, #1000 @ 0x3e8 8002292: fbb3 f3f1 udiv r3, r3, r1 8002296: fbb2 f3f3 udiv r3, r2, r3 800229a: 4618 mov r0, r3 800229c: f002 f917 bl 80044ce 80022a0: 4603 mov r3, r0 80022a2: 2b00 cmp r3, #0 80022a4: d001 beq.n 80022aa { return HAL_ERROR; 80022a6: 2301 movs r3, #1 80022a8: e00e b.n 80022c8 } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 80022aa: 687b ldr r3, [r7, #4] 80022ac: 2b0f cmp r3, #15 80022ae: d80a bhi.n 80022c6 { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 80022b0: 2200 movs r2, #0 80022b2: 6879 ldr r1, [r7, #4] 80022b4: f04f 30ff mov.w r0, #4294967295 80022b8: f002 f8df bl 800447a uwTickPrio = TickPriority; 80022bc: 4a06 ldr r2, [pc, #24] @ (80022d8 ) 80022be: 687b ldr r3, [r7, #4] 80022c0: 6013 str r3, [r2, #0] else { return HAL_ERROR; } /* Return function status */ return HAL_OK; 80022c2: 2300 movs r3, #0 80022c4: e000 b.n 80022c8 return HAL_ERROR; 80022c6: 2301 movs r3, #1 } 80022c8: 4618 mov r0, r3 80022ca: 3708 adds r7, #8 80022cc: 46bd mov sp, r7 80022ce: bd80 pop {r7, pc} 80022d0: 20000000 .word 0x20000000 80022d4: 20000008 .word 0x20000008 80022d8: 20000004 .word 0x20000004 080022dc : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 80022dc: b480 push {r7} 80022de: af00 add r7, sp, #0 uwTick += uwTickFreq; 80022e0: 4b06 ldr r3, [pc, #24] @ (80022fc ) 80022e2: 781b ldrb r3, [r3, #0] 80022e4: 461a mov r2, r3 80022e6: 4b06 ldr r3, [pc, #24] @ (8002300 ) 80022e8: 681b ldr r3, [r3, #0] 80022ea: 4413 add r3, r2 80022ec: 4a04 ldr r2, [pc, #16] @ (8002300 ) 80022ee: 6013 str r3, [r2, #0] } 80022f0: bf00 nop 80022f2: 46bd mov sp, r7 80022f4: f85d 7b04 ldr.w r7, [sp], #4 80022f8: 4770 bx lr 80022fa: bf00 nop 80022fc: 20000008 .word 0x20000008 8002300: 200002fc .word 0x200002fc 08002304 : * @note The function is declared as __Weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 8002304: b480 push {r7} 8002306: af00 add r7, sp, #0 return uwTick; 8002308: 4b03 ldr r3, [pc, #12] @ (8002318 ) 800230a: 681b ldr r3, [r3, #0] } 800230c: 4618 mov r0, r3 800230e: 46bd mov sp, r7 8002310: f85d 7b04 ldr.w r7, [sp], #4 8002314: 4770 bx lr 8002316: bf00 nop 8002318: 200002fc .word 0x200002fc 0800231c : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 800231c: b580 push {r7, lr} 800231e: b084 sub sp, #16 8002320: af00 add r7, sp, #0 8002322: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 8002324: f7ff ffee bl 8002304 8002328: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 800232a: 687b ldr r3, [r7, #4] 800232c: 60fb str r3, [r7, #12] /* Add freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 800232e: 68fb ldr r3, [r7, #12] 8002330: f1b3 3fff cmp.w r3, #4294967295 8002334: d005 beq.n 8002342 { wait += (uint32_t)(uwTickFreq); 8002336: 4b0a ldr r3, [pc, #40] @ (8002360 ) 8002338: 781b ldrb r3, [r3, #0] 800233a: 461a mov r2, r3 800233c: 68fb ldr r3, [r7, #12] 800233e: 4413 add r3, r2 8002340: 60fb str r3, [r7, #12] } while((HAL_GetTick() - tickstart) < wait) 8002342: bf00 nop 8002344: f7ff ffde bl 8002304 8002348: 4602 mov r2, r0 800234a: 68bb ldr r3, [r7, #8] 800234c: 1ad3 subs r3, r2, r3 800234e: 68fa ldr r2, [r7, #12] 8002350: 429a cmp r2, r3 8002352: d8f7 bhi.n 8002344 { } } 8002354: bf00 nop 8002356: bf00 nop 8002358: 3710 adds r7, #16 800235a: 46bd mov sp, r7 800235c: bd80 pop {r7, pc} 800235e: bf00 nop 8002360: 20000008 .word 0x20000008 08002364 : * @brief Conversion DMA half-transfer callback in non blocking mode * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) { 8002364: b480 push {r7} 8002366: b083 sub sp, #12 8002368: af00 add r7, sp, #0 800236a: 6078 str r0, [r7, #4] UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file. */ } 800236c: bf00 nop 800236e: 370c adds r7, #12 8002370: 46bd mov sp, r7 8002372: f85d 7b04 ldr.w r7, [sp], #4 8002376: 4770 bx lr 08002378 : * @brief Analog watchdog callback in non blocking mode. * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) { 8002378: b480 push {r7} 800237a: b083 sub sp, #12 800237c: af00 add r7, sp, #0 800237e: 6078 str r0, [r7, #4] UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_LevelOoutOfWindowCallback must be implemented in the user file. */ } 8002380: bf00 nop 8002382: 370c adds r7, #12 8002384: 46bd mov sp, r7 8002386: f85d 7b04 ldr.w r7, [sp], #4 800238a: 4770 bx lr 0800238c : * (ADC conversion with interruption or transfer by DMA) * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) { 800238c: b480 push {r7} 800238e: b083 sub sp, #12 8002390: af00 add r7, sp, #0 8002392: 6078 str r0, [r7, #4] UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ErrorCallback must be implemented in the user file. */ } 8002394: bf00 nop 8002396: 370c adds r7, #12 8002398: 46bd mov sp, r7 800239a: f85d 7b04 ldr.w r7, [sp], #4 800239e: 4770 bx lr 080023a0 : * without disabling the other ADCs sharing the same common group. * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) { 80023a0: b580 push {r7, lr} 80023a2: b09a sub sp, #104 @ 0x68 80023a4: af00 add r7, sp, #0 80023a6: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 80023a8: 2300 movs r3, #0 80023aa: f887 3067 strb.w r3, [r7, #103] @ 0x67 ADC_Common_TypeDef *tmpADC_Common; ADC_HandleTypeDef tmphadcSharingSameCommonRegister; uint32_t tmpCFGR = 0U; 80023ae: 2300 movs r3, #0 80023b0: 663b str r3, [r7, #96] @ 0x60 __IO uint32_t wait_loop_index = 0U; 80023b2: 2300 movs r3, #0 80023b4: 60bb str r3, [r7, #8] /* Check ADC handle */ if(hadc == NULL) 80023b6: 687b ldr r3, [r7, #4] 80023b8: 2b00 cmp r3, #0 80023ba: d101 bne.n 80023c0 { return HAL_ERROR; 80023bc: 2301 movs r3, #1 80023be: e172 b.n 80026a6 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests)); assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait)); if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) 80023c0: 687b ldr r3, [r7, #4] 80023c2: 691b ldr r3, [r3, #16] 80023c4: 2b00 cmp r3, #0 assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion)); } } /* Configuration of ADC core parameters and ADC MSP related parameters */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) 80023c6: 687b ldr r3, [r7, #4] 80023c8: 6c1b ldr r3, [r3, #64] @ 0x40 80023ca: f003 0310 and.w r3, r3, #16 80023ce: 2b00 cmp r3, #0 80023d0: d176 bne.n 80024c0 /* procedure. */ /* Actions performed only if ADC is coming from state reset: */ /* - Initialization of ADC MSP */ /* - ADC voltage regulator enable */ if (hadc->State == HAL_ADC_STATE_RESET) 80023d2: 687b ldr r3, [r7, #4] 80023d4: 6c1b ldr r3, [r3, #64] @ 0x40 80023d6: 2b00 cmp r3, #0 80023d8: d152 bne.n 8002480 { /* Initialize ADC error code */ ADC_CLEAR_ERRORCODE(hadc); 80023da: 687b ldr r3, [r7, #4] 80023dc: 2200 movs r2, #0 80023de: 645a str r2, [r3, #68] @ 0x44 /* Initialize HAL ADC API internal variables */ hadc->InjectionConfig.ChannelCount = 0U; 80023e0: 687b ldr r3, [r7, #4] 80023e2: 2200 movs r2, #0 80023e4: 64da str r2, [r3, #76] @ 0x4c hadc->InjectionConfig.ContextQueue = 0U; 80023e6: 687b ldr r3, [r7, #4] 80023e8: 2200 movs r2, #0 80023ea: 649a str r2, [r3, #72] @ 0x48 /* Allocate lock resource and initialize it */ hadc->Lock = HAL_UNLOCKED; 80023ec: 687b ldr r3, [r7, #4] 80023ee: 2200 movs r2, #0 80023f0: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Init the low level hardware */ hadc->MspInitCallback(hadc); #else /* Init the low level hardware */ HAL_ADC_MspInit(hadc); 80023f4: 6878 ldr r0, [r7, #4] 80023f6: f7ff fc8f bl 8001d18 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Enable voltage regulator (if disabled at this step) */ if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN_0)) 80023fa: 687b ldr r3, [r7, #4] 80023fc: 681b ldr r3, [r3, #0] 80023fe: 689b ldr r3, [r3, #8] 8002400: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8002404: 2b00 cmp r3, #0 8002406: d13b bne.n 8002480 /* enabling the ADC. This temporization must be implemented by */ /* software and is equal to 10 us in the worst case */ /* process/temperature/power supply. */ /* Disable the ADC (if not already disabled) */ tmp_hal_status = ADC_Disable(hadc); 8002408: 6878 ldr r0, [r7, #4] 800240a: f001 f8a5 bl 8003558 800240e: 4603 mov r3, r0 8002410: f887 3067 strb.w r3, [r7, #103] @ 0x67 /* Check if ADC is effectively disabled */ /* Configuration of ADC parameters if previous preliminary actions */ /* are correctly completed. */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && 8002414: 687b ldr r3, [r7, #4] 8002416: 6c1b ldr r3, [r3, #64] @ 0x40 8002418: f003 0310 and.w r3, r3, #16 800241c: 2b00 cmp r3, #0 800241e: d12f bne.n 8002480 8002420: f897 3067 ldrb.w r3, [r7, #103] @ 0x67 8002424: 2b00 cmp r3, #0 8002426: d12b bne.n 8002480 (tmp_hal_status == HAL_OK) ) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 8002428: 687b ldr r3, [r7, #4] 800242a: 6c1b ldr r3, [r3, #64] @ 0x40 800242c: f423 5388 bic.w r3, r3, #4352 @ 0x1100 8002430: f023 0302 bic.w r3, r3, #2 8002434: f043 0202 orr.w r2, r3, #2 8002438: 687b ldr r3, [r7, #4] 800243a: 641a str r2, [r3, #64] @ 0x40 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_BUSY_INTERNAL); /* Set the intermediate state before moving the ADC voltage */ /* regulator to state enable. */ CLEAR_BIT(hadc->Instance->CR, (ADC_CR_ADVREGEN_1 | ADC_CR_ADVREGEN_0)); 800243c: 687b ldr r3, [r7, #4] 800243e: 681b ldr r3, [r3, #0] 8002440: 689a ldr r2, [r3, #8] 8002442: 687b ldr r3, [r7, #4] 8002444: 681b ldr r3, [r3, #0] 8002446: f022 5240 bic.w r2, r2, #805306368 @ 0x30000000 800244a: 609a str r2, [r3, #8] /* Set ADVREGEN bits to 0x01U */ SET_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN_0); 800244c: 687b ldr r3, [r7, #4] 800244e: 681b ldr r3, [r3, #0] 8002450: 689a ldr r2, [r3, #8] 8002452: 687b ldr r3, [r7, #4] 8002454: 681b ldr r3, [r3, #0] 8002456: f042 5280 orr.w r2, r2, #268435456 @ 0x10000000 800245a: 609a str r2, [r3, #8] /* Delay for ADC stabilization time. */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); 800245c: 4b94 ldr r3, [pc, #592] @ (80026b0 ) 800245e: 681b ldr r3, [r3, #0] 8002460: 4a94 ldr r2, [pc, #592] @ (80026b4 ) 8002462: fba2 2303 umull r2, r3, r2, r3 8002466: 0c9a lsrs r2, r3, #18 8002468: 4613 mov r3, r2 800246a: 009b lsls r3, r3, #2 800246c: 4413 add r3, r2 800246e: 005b lsls r3, r3, #1 8002470: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 8002472: e002 b.n 800247a { wait_loop_index--; 8002474: 68bb ldr r3, [r7, #8] 8002476: 3b01 subs r3, #1 8002478: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 800247a: 68bb ldr r3, [r7, #8] 800247c: 2b00 cmp r3, #0 800247e: d1f9 bne.n 8002474 } /* Verification that ADC voltage regulator is correctly enabled, whether */ /* or not ADC is coming from state reset (if any potential problem of */ /* clocking, voltage regulator would not be enabled). */ if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN_0) || 8002480: 687b ldr r3, [r7, #4] 8002482: 681b ldr r3, [r3, #0] 8002484: 689b ldr r3, [r3, #8] 8002486: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 800248a: 2b00 cmp r3, #0 800248c: d007 beq.n 800249e HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADVREGEN_1) ) 800248e: 687b ldr r3, [r7, #4] 8002490: 681b ldr r3, [r3, #0] 8002492: 689b ldr r3, [r3, #8] 8002494: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN_0) || 8002498: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800249c: d110 bne.n 80024c0 { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 800249e: 687b ldr r3, [r7, #4] 80024a0: 6c1b ldr r3, [r3, #64] @ 0x40 80024a2: f023 0312 bic.w r3, r3, #18 80024a6: f043 0210 orr.w r2, r3, #16 80024aa: 687b ldr r3, [r7, #4] 80024ac: 641a str r2, [r3, #64] @ 0x40 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 80024ae: 687b ldr r3, [r7, #4] 80024b0: 6c5b ldr r3, [r3, #68] @ 0x44 80024b2: f043 0201 orr.w r2, r3, #1 80024b6: 687b ldr r3, [r7, #4] 80024b8: 645a str r2, [r3, #68] @ 0x44 tmp_hal_status = HAL_ERROR; 80024ba: 2301 movs r3, #1 80024bc: f887 3067 strb.w r3, [r7, #103] @ 0x67 /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed and if there is no conversion on going on regular */ /* group (ADC may already be enabled at this point if HAL_ADC_Init() is */ /* called to update a parameter on the fly). */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && 80024c0: 687b ldr r3, [r7, #4] 80024c2: 6c1b ldr r3, [r3, #64] @ 0x40 80024c4: f003 0310 and.w r3, r3, #16 80024c8: 2b00 cmp r3, #0 80024ca: f040 80df bne.w 800268c 80024ce: f897 3067 ldrb.w r3, [r7, #103] @ 0x67 80024d2: 2b00 cmp r3, #0 80024d4: f040 80da bne.w 800268c (tmp_hal_status == HAL_OK) && (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) ) 80024d8: 687b ldr r3, [r7, #4] 80024da: 681b ldr r3, [r3, #0] 80024dc: 689b ldr r3, [r3, #8] 80024de: f003 0304 and.w r3, r3, #4 (tmp_hal_status == HAL_OK) && 80024e2: 2b00 cmp r3, #0 80024e4: f040 80d2 bne.w 800268c { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 80024e8: 687b ldr r3, [r7, #4] 80024ea: 6c1b ldr r3, [r3, #64] @ 0x40 80024ec: f423 7381 bic.w r3, r3, #258 @ 0x102 80024f0: f043 0202 orr.w r2, r3, #2 80024f4: 687b ldr r3, [r7, #4] 80024f6: 641a str r2, [r3, #64] @ 0x40 /* Configuration of common ADC parameters */ /* Pointer to the common control register to which is belonging hadc */ /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */ /* control registers) */ tmpADC_Common = ADC_COMMON_REGISTER(hadc); 80024f8: 4b6f ldr r3, [pc, #444] @ (80026b8 ) 80024fa: 65fb str r3, [r7, #92] @ 0x5c /* Set handle of the other ADC sharing the same common register */ ADC_COMMON_ADC_OTHER(hadc, &tmphadcSharingSameCommonRegister); 80024fc: 687b ldr r3, [r7, #4] 80024fe: 681b ldr r3, [r3, #0] 8002500: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 8002504: d102 bne.n 800250c 8002506: 4b6d ldr r3, [pc, #436] @ (80026bc ) 8002508: 60fb str r3, [r7, #12] 800250a: e002 b.n 8002512 800250c: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 8002510: 60fb str r3, [r7, #12] /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - Multimode clock configuration */ if ((ADC_IS_ENABLE(hadc) == RESET) && 8002512: 687b ldr r3, [r7, #4] 8002514: 681b ldr r3, [r3, #0] 8002516: 689b ldr r3, [r3, #8] 8002518: f003 0303 and.w r3, r3, #3 800251c: 2b01 cmp r3, #1 800251e: d108 bne.n 8002532 8002520: 687b ldr r3, [r7, #4] 8002522: 681b ldr r3, [r3, #0] 8002524: 681b ldr r3, [r3, #0] 8002526: f003 0301 and.w r3, r3, #1 800252a: 2b01 cmp r3, #1 800252c: d101 bne.n 8002532 800252e: 2301 movs r3, #1 8002530: e000 b.n 8002534 8002532: 2300 movs r3, #0 8002534: 2b00 cmp r3, #0 8002536: d11c bne.n 8002572 ((tmphadcSharingSameCommonRegister.Instance == NULL) || 8002538: 68fb ldr r3, [r7, #12] if ((ADC_IS_ENABLE(hadc) == RESET) && 800253a: 2b00 cmp r3, #0 800253c: d010 beq.n 8002560 (ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) ) ) 800253e: 68fb ldr r3, [r7, #12] 8002540: 689b ldr r3, [r3, #8] 8002542: f003 0303 and.w r3, r3, #3 8002546: 2b01 cmp r3, #1 8002548: d107 bne.n 800255a 800254a: 68fb ldr r3, [r7, #12] 800254c: 681b ldr r3, [r3, #0] 800254e: f003 0301 and.w r3, r3, #1 8002552: 2b01 cmp r3, #1 8002554: d101 bne.n 800255a 8002556: 2301 movs r3, #1 8002558: e000 b.n 800255c 800255a: 2300 movs r3, #0 ((tmphadcSharingSameCommonRegister.Instance == NULL) || 800255c: 2b00 cmp r3, #0 800255e: d108 bne.n 8002572 /* into HAL_ADCEx_MultiModeConfigChannel() ) */ /* - internal measurement paths: Vbat, temperature sensor, Vref */ /* (set into HAL_ADC_ConfigChannel() or */ /* HAL_ADCEx_InjectedConfigChannel() ) */ MODIFY_REG(tmpADC_Common->CCR , 8002560: 6dfb ldr r3, [r7, #92] @ 0x5c 8002562: 689b ldr r3, [r3, #8] 8002564: f423 3240 bic.w r2, r3, #196608 @ 0x30000 8002568: 687b ldr r3, [r7, #4] 800256a: 685b ldr r3, [r3, #4] 800256c: 431a orrs r2, r3 800256e: 6dfb ldr r3, [r7, #92] @ 0x5c 8002570: 609a str r2, [r3, #8] /* - external trigger to start conversion */ /* - external trigger polarity */ /* - continuous conversion mode */ /* - overrun */ /* - discontinuous mode */ SET_BIT(tmpCFGR, ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 8002572: 687b ldr r3, [r7, #4] 8002574: 7e5b ldrb r3, [r3, #25] 8002576: 035b lsls r3, r3, #13 8002578: 687a ldr r2, [r7, #4] 800257a: 6b52 ldr r2, [r2, #52] @ 0x34 800257c: 2a01 cmp r2, #1 800257e: d002 beq.n 8002586 8002580: f44f 5280 mov.w r2, #4096 @ 0x1000 8002584: e000 b.n 8002588 8002586: 2200 movs r2, #0 8002588: 431a orrs r2, r3 800258a: 687b ldr r3, [r7, #4] 800258c: 68db ldr r3, [r3, #12] 800258e: 431a orrs r2, r3 8002590: 687b ldr r3, [r7, #4] 8002592: 689b ldr r3, [r3, #8] 8002594: 4313 orrs r3, r2 8002596: 6e3a ldr r2, [r7, #96] @ 0x60 8002598: 4313 orrs r3, r2 800259a: 663b str r3, [r7, #96] @ 0x60 ADC_CFGR_OVERRUN(hadc->Init.Overrun) | hadc->Init.DataAlign | hadc->Init.Resolution ); /* Enable discontinuous mode only if continuous mode is disabled */ if (hadc->Init.DiscontinuousConvMode == ENABLE) 800259c: 687b ldr r3, [r7, #4] 800259e: f893 3020 ldrb.w r3, [r3, #32] 80025a2: 2b01 cmp r3, #1 80025a4: d11b bne.n 80025de { if (hadc->Init.ContinuousConvMode == DISABLE) 80025a6: 687b ldr r3, [r7, #4] 80025a8: 7e5b ldrb r3, [r3, #25] 80025aa: 2b00 cmp r3, #0 80025ac: d109 bne.n 80025c2 { /* Enable the selected ADC regular discontinuous mode */ /* Set the number of channels to be converted in discontinuous mode */ SET_BIT(tmpCFGR, ADC_CFGR_DISCEN | 80025ae: 687b ldr r3, [r7, #4] 80025b0: 6a5b ldr r3, [r3, #36] @ 0x24 80025b2: 3b01 subs r3, #1 80025b4: 045a lsls r2, r3, #17 80025b6: 6e3b ldr r3, [r7, #96] @ 0x60 80025b8: 4313 orrs r3, r2 80025ba: f443 3380 orr.w r3, r3, #65536 @ 0x10000 80025be: 663b str r3, [r7, #96] @ 0x60 80025c0: e00d b.n 80025de /* ADC regular group discontinuous was intended to be enabled, */ /* but ADC regular group modes continuous and sequencer discontinuous */ /* cannot be enabled simultaneously. */ /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 80025c2: 687b ldr r3, [r7, #4] 80025c4: 6c1b ldr r3, [r3, #64] @ 0x40 80025c6: f023 0322 bic.w r3, r3, #34 @ 0x22 80025ca: f043 0220 orr.w r2, r3, #32 80025ce: 687b ldr r3, [r7, #4] 80025d0: 641a str r2, [r3, #64] @ 0x40 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_CONFIG); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 80025d2: 687b ldr r3, [r7, #4] 80025d4: 6c5b ldr r3, [r3, #68] @ 0x44 80025d6: f043 0201 orr.w r2, r3, #1 80025da: 687b ldr r3, [r7, #4] 80025dc: 645a str r2, [r3, #68] @ 0x44 /* Enable external trigger if trigger selection is different of software */ /* start. */ /* Note: This configuration keeps the hardware feature of parameter */ /* ExternalTrigConvEdge "trigger edge none" equivalent to */ /* software start. */ if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) 80025de: 687b ldr r3, [r7, #4] 80025e0: 6a9b ldr r3, [r3, #40] @ 0x28 80025e2: 2b01 cmp r3, #1 80025e4: d007 beq.n 80025f6 { SET_BIT(tmpCFGR, ADC_CFGR_EXTSEL_SET(hadc, hadc->Init.ExternalTrigConv) | 80025e6: 687b ldr r3, [r7, #4] 80025e8: 6a9a ldr r2, [r3, #40] @ 0x28 80025ea: 687b ldr r3, [r7, #4] 80025ec: 6adb ldr r3, [r3, #44] @ 0x2c 80025ee: 4313 orrs r3, r2 80025f0: 6e3a ldr r2, [r7, #96] @ 0x60 80025f2: 4313 orrs r3, r2 80025f4: 663b str r3, [r7, #96] @ 0x60 /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular and injected groups: */ /* - DMA continuous request */ /* - LowPowerAutoWait feature */ if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) 80025f6: 687b ldr r3, [r7, #4] 80025f8: 681b ldr r3, [r3, #0] 80025fa: 689b ldr r3, [r3, #8] 80025fc: f003 030c and.w r3, r3, #12 8002600: 2b00 cmp r3, #0 8002602: d114 bne.n 800262e { CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_AUTDLY | 8002604: 687b ldr r3, [r7, #4] 8002606: 681b ldr r3, [r3, #0] 8002608: 68db ldr r3, [r3, #12] 800260a: 687a ldr r2, [r7, #4] 800260c: 6812 ldr r2, [r2, #0] 800260e: f423 4380 bic.w r3, r3, #16384 @ 0x4000 8002612: f023 0302 bic.w r3, r3, #2 8002616: 60d3 str r3, [r2, #12] ADC_CFGR_DMACFG ); SET_BIT(tmpCFGR, ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | 8002618: 687b ldr r3, [r7, #4] 800261a: 7e1b ldrb r3, [r3, #24] 800261c: 039a lsls r2, r3, #14 800261e: 687b ldr r3, [r7, #4] 8002620: f893 3030 ldrb.w r3, [r3, #48] @ 0x30 8002624: 005b lsls r3, r3, #1 8002626: 4313 orrs r3, r2 8002628: 6e3a ldr r2, [r7, #96] @ 0x60 800262a: 4313 orrs r3, r2 800262c: 663b str r3, [r7, #96] @ 0x60 ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests) ); } /* Update ADC configuration register with previous settings */ MODIFY_REG(hadc->Instance->CFGR, 800262e: 687b ldr r3, [r7, #4] 8002630: 681b ldr r3, [r3, #0] 8002632: 68da ldr r2, [r3, #12] 8002634: 4b22 ldr r3, [pc, #136] @ (80026c0 ) 8002636: 4013 ands r3, r2 8002638: 687a ldr r2, [r7, #4] 800263a: 6812 ldr r2, [r2, #0] 800263c: 6e39 ldr r1, [r7, #96] @ 0x60 800263e: 430b orrs r3, r1 8002640: 60d3 str r3, [r2, #12] /* Parameter "NbrOfConversion" is discarded. */ /* Note: Scan mode is not present by hardware on this device, but */ /* emulated by software for alignment over all STM32 devices. */ /* - if scan mode is enabled, regular channels sequence length is set to */ /* parameter "NbrOfConversion" */ if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE) 8002642: 687b ldr r3, [r7, #4] 8002644: 691b ldr r3, [r3, #16] 8002646: 2b01 cmp r3, #1 8002648: d10c bne.n 8002664 { /* Set number of ranks in regular group sequencer */ MODIFY_REG(hadc->Instance->SQR1 , 800264a: 687b ldr r3, [r7, #4] 800264c: 681b ldr r3, [r3, #0] 800264e: 6b1b ldr r3, [r3, #48] @ 0x30 8002650: f023 010f bic.w r1, r3, #15 8002654: 687b ldr r3, [r7, #4] 8002656: 69db ldr r3, [r3, #28] 8002658: 1e5a subs r2, r3, #1 800265a: 687b ldr r3, [r7, #4] 800265c: 681b ldr r3, [r3, #0] 800265e: 430a orrs r2, r1 8002660: 631a str r2, [r3, #48] @ 0x30 8002662: e007 b.n 8002674 ADC_SQR1_L , (hadc->Init.NbrOfConversion - (uint8_t)1U) ); } else { CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L); 8002664: 687b ldr r3, [r7, #4] 8002666: 681b ldr r3, [r3, #0] 8002668: 6b1a ldr r2, [r3, #48] @ 0x30 800266a: 687b ldr r3, [r7, #4] 800266c: 681b ldr r3, [r3, #0] 800266e: f022 020f bic.w r2, r2, #15 8002672: 631a str r2, [r3, #48] @ 0x30 } /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); 8002674: 687b ldr r3, [r7, #4] 8002676: 2200 movs r2, #0 8002678: 645a str r2, [r3, #68] @ 0x44 /* Set the ADC state */ ADC_STATE_CLR_SET(hadc->State, 800267a: 687b ldr r3, [r7, #4] 800267c: 6c1b ldr r3, [r3, #64] @ 0x40 800267e: f023 0303 bic.w r3, r3, #3 8002682: f043 0201 orr.w r2, r3, #1 8002686: 687b ldr r3, [r7, #4] 8002688: 641a str r2, [r3, #64] @ 0x40 800268a: e00a b.n 80026a2 HAL_ADC_STATE_READY); } else { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 800268c: 687b ldr r3, [r7, #4] 800268e: 6c1b ldr r3, [r3, #64] @ 0x40 8002690: f023 0312 bic.w r3, r3, #18 8002694: f043 0210 orr.w r2, r3, #16 8002698: 687b ldr r3, [r7, #4] 800269a: 641a str r2, [r3, #64] @ 0x40 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); tmp_hal_status = HAL_ERROR; 800269c: 2301 movs r3, #1 800269e: f887 3067 strb.w r3, [r7, #103] @ 0x67 } /* Return function status */ return tmp_hal_status; 80026a2: f897 3067 ldrb.w r3, [r7, #103] @ 0x67 } 80026a6: 4618 mov r0, r3 80026a8: 3768 adds r7, #104 @ 0x68 80026aa: 46bd mov sp, r7 80026ac: bd80 pop {r7, pc} 80026ae: bf00 nop 80026b0: 20000000 .word 0x20000000 80026b4: 431bde83 .word 0x431bde83 80026b8: 50000300 .word 0x50000300 80026bc: 50000100 .word 0x50000100 80026c0: fff0c007 .word 0xfff0c007 080026c4 : * @param pData The destination Buffer address. * @param Length The length of data to be transferred from ADC peripheral to memory. * @retval None */ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) { 80026c4: b580 push {r7, lr} 80026c6: b086 sub sp, #24 80026c8: af00 add r7, sp, #0 80026ca: 60f8 str r0, [r7, #12] 80026cc: 60b9 str r1, [r7, #8] 80026ce: 607a str r2, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 80026d0: 2300 movs r3, #0 80026d2: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Perform ADC enable and conversion start if no conversion is on going */ if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) 80026d4: 68fb ldr r3, [r7, #12] 80026d6: 681b ldr r3, [r3, #0] 80026d8: 689b ldr r3, [r3, #8] 80026da: f003 0304 and.w r3, r3, #4 80026de: 2b00 cmp r3, #0 80026e0: f040 80b9 bne.w 8002856 { /* Process locked */ __HAL_LOCK(hadc); 80026e4: 68fb ldr r3, [r7, #12] 80026e6: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 80026ea: 2b01 cmp r3, #1 80026ec: d101 bne.n 80026f2 80026ee: 2302 movs r3, #2 80026f0: e0b4 b.n 800285c 80026f2: 68fb ldr r3, [r7, #12] 80026f4: 2201 movs r2, #1 80026f6: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Verification if multimode is disabled (for devices with several ADC) */ /* If multimode is enabled, dedicated function multimode conversion */ /* start DMA must be used. */ if(ADC_COMMON_CCR_MULTI(hadc) == RESET) 80026fa: 4b5a ldr r3, [pc, #360] @ (8002864 ) 80026fc: 689b ldr r3, [r3, #8] 80026fe: f003 031f and.w r3, r3, #31 8002702: 2b00 cmp r3, #0 8002704: f040 80a0 bne.w 8002848 { /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); 8002708: 68f8 ldr r0, [r7, #12] 800270a: f000 fec1 bl 8003490 800270e: 4603 mov r3, r0 8002710: 75fb strb r3, [r7, #23] /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) 8002712: 7dfb ldrb r3, [r7, #23] 8002714: 2b00 cmp r3, #0 8002716: f040 8092 bne.w 800283e { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ /* - Set state bitfield related to regular operation */ ADC_STATE_CLR_SET(hadc->State, 800271a: 68fb ldr r3, [r7, #12] 800271c: 6c1b ldr r3, [r3, #64] @ 0x40 800271e: f423 6370 bic.w r3, r3, #3840 @ 0xf00 8002722: f023 0301 bic.w r3, r3, #1 8002726: f443 7280 orr.w r2, r3, #256 @ 0x100 800272a: 68fb ldr r3, [r7, #12] 800272c: 641a str r2, [r3, #64] @ 0x40 HAL_ADC_STATE_REG_BUSY); /* Set group injected state (from auto-injection) and multimode state */ /* for all cases of multimode: independent mode, multimode ADC master */ /* or multimode ADC slave (for devices with several ADCs): */ if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) 800272e: 4b4d ldr r3, [pc, #308] @ (8002864 ) 8002730: 689b ldr r3, [r3, #8] 8002732: f003 031f and.w r3, r3, #31 8002736: 2b00 cmp r3, #0 8002738: d004 beq.n 8002744 800273a: 68fb ldr r3, [r7, #12] 800273c: 681b ldr r3, [r3, #0] 800273e: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 8002742: d115 bne.n 8002770 { /* Set ADC state (ADC independent or master) */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 8002744: 68fb ldr r3, [r7, #12] 8002746: 6c1b ldr r3, [r3, #64] @ 0x40 8002748: f423 1280 bic.w r2, r3, #1048576 @ 0x100000 800274c: 68fb ldr r3, [r7, #12] 800274e: 641a str r2, [r3, #64] @ 0x40 /* If conversions on group regular are also triggering group injected,*/ /* update ADC state. */ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET) 8002750: 68fb ldr r3, [r7, #12] 8002752: 681b ldr r3, [r3, #0] 8002754: 68db ldr r3, [r3, #12] 8002756: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800275a: 2b00 cmp r3, #0 800275c: d027 beq.n 80027ae { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); 800275e: 68fb ldr r3, [r7, #12] 8002760: 6c1b ldr r3, [r3, #64] @ 0x40 8002762: f423 5340 bic.w r3, r3, #12288 @ 0x3000 8002766: f443 5280 orr.w r2, r3, #4096 @ 0x1000 800276a: 68fb ldr r3, [r7, #12] 800276c: 641a str r2, [r3, #64] @ 0x40 if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET) 800276e: e01e b.n 80027ae } } else { /* Set ADC state (ADC slave) */ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 8002770: 68fb ldr r3, [r7, #12] 8002772: 6c1b ldr r3, [r3, #64] @ 0x40 8002774: f443 1280 orr.w r2, r3, #1048576 @ 0x100000 8002778: 68fb ldr r3, [r7, #12] 800277a: 641a str r2, [r3, #64] @ 0x40 /* If conversions on group regular are also triggering group injected,*/ /* update ADC state. */ if (ADC_MULTIMODE_AUTO_INJECTED(hadc)) 800277c: 68fb ldr r3, [r7, #12] 800277e: 681b ldr r3, [r3, #0] 8002780: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 8002784: d004 beq.n 8002790 8002786: 68fb ldr r3, [r7, #12] 8002788: 681b ldr r3, [r3, #0] 800278a: 4a37 ldr r2, [pc, #220] @ (8002868 ) 800278c: 4293 cmp r3, r2 800278e: d10e bne.n 80027ae 8002790: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 8002794: 68db ldr r3, [r3, #12] 8002796: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800279a: 2b00 cmp r3, #0 800279c: d007 beq.n 80027ae { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); 800279e: 68fb ldr r3, [r7, #12] 80027a0: 6c1b ldr r3, [r3, #64] @ 0x40 80027a2: f423 5340 bic.w r3, r3, #12288 @ 0x3000 80027a6: f443 5280 orr.w r2, r3, #4096 @ 0x1000 80027aa: 68fb ldr r3, [r7, #12] 80027ac: 641a str r2, [r3, #64] @ 0x40 } } /* State machine update: Check if an injected conversion is ongoing */ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 80027ae: 68fb ldr r3, [r7, #12] 80027b0: 6c1b ldr r3, [r3, #64] @ 0x40 80027b2: f403 5380 and.w r3, r3, #4096 @ 0x1000 80027b6: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 80027ba: d106 bne.n 80027ca { /* Reset ADC error code fields related to conversions on group regular*/ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); 80027bc: 68fb ldr r3, [r7, #12] 80027be: 6c5b ldr r3, [r3, #68] @ 0x44 80027c0: f023 0206 bic.w r2, r3, #6 80027c4: 68fb ldr r3, [r7, #12] 80027c6: 645a str r2, [r3, #68] @ 0x44 80027c8: e002 b.n 80027d0 } else { /* Reset ADC all error code fields */ ADC_CLEAR_ERRORCODE(hadc); 80027ca: 68fb ldr r3, [r7, #12] 80027cc: 2200 movs r2, #0 80027ce: 645a str r2, [r3, #68] @ 0x44 } /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); 80027d0: 68fb ldr r3, [r7, #12] 80027d2: 2200 movs r2, #0 80027d4: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Set the DMA transfer complete callback */ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; 80027d8: 68fb ldr r3, [r7, #12] 80027da: 6b9b ldr r3, [r3, #56] @ 0x38 80027dc: 4a23 ldr r2, [pc, #140] @ (800286c ) 80027de: 629a str r2, [r3, #40] @ 0x28 /* Set the DMA half transfer complete callback */ hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; 80027e0: 68fb ldr r3, [r7, #12] 80027e2: 6b9b ldr r3, [r3, #56] @ 0x38 80027e4: 4a22 ldr r2, [pc, #136] @ (8002870 ) 80027e6: 62da str r2, [r3, #44] @ 0x2c /* Set the DMA error callback */ hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; 80027e8: 68fb ldr r3, [r7, #12] 80027ea: 6b9b ldr r3, [r3, #56] @ 0x38 80027ec: 4a21 ldr r2, [pc, #132] @ (8002874 ) 80027ee: 631a str r2, [r3, #48] @ 0x30 /* start (in case of SW start): */ /* Clear regular group conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC */ /* operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); 80027f0: 68fb ldr r3, [r7, #12] 80027f2: 681b ldr r3, [r3, #0] 80027f4: 221c movs r2, #28 80027f6: 601a str r2, [r3, #0] /* Enable ADC overrun interrupt */ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); 80027f8: 68fb ldr r3, [r7, #12] 80027fa: 681b ldr r3, [r3, #0] 80027fc: 685a ldr r2, [r3, #4] 80027fe: 68fb ldr r3, [r7, #12] 8002800: 681b ldr r3, [r3, #0] 8002802: f042 0210 orr.w r2, r2, #16 8002806: 605a str r2, [r3, #4] /* Enable ADC DMA mode */ SET_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN); 8002808: 68fb ldr r3, [r7, #12] 800280a: 681b ldr r3, [r3, #0] 800280c: 68da ldr r2, [r3, #12] 800280e: 68fb ldr r3, [r7, #12] 8002810: 681b ldr r3, [r3, #0] 8002812: f042 0201 orr.w r2, r2, #1 8002816: 60da str r2, [r3, #12] /* Start the DMA channel */ HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); 8002818: 68fb ldr r3, [r7, #12] 800281a: 6b98 ldr r0, [r3, #56] @ 0x38 800281c: 68fb ldr r3, [r7, #12] 800281e: 681b ldr r3, [r3, #0] 8002820: 3340 adds r3, #64 @ 0x40 8002822: 4619 mov r1, r3 8002824: 68ba ldr r2, [r7, #8] 8002826: 687b ldr r3, [r7, #4] 8002828: f001 fea4 bl 8004574 /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately.*/ /* If external trigger has been selected, conversion will start at */ /* next trigger event. */ SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART); 800282c: 68fb ldr r3, [r7, #12] 800282e: 681b ldr r3, [r3, #0] 8002830: 689a ldr r2, [r3, #8] 8002832: 68fb ldr r3, [r7, #12] 8002834: 681b ldr r3, [r3, #0] 8002836: f042 0204 orr.w r2, r2, #4 800283a: 609a str r2, [r3, #8] 800283c: e00d b.n 800285a } else { /* Process unlocked */ __HAL_UNLOCK(hadc); 800283e: 68fb ldr r3, [r7, #12] 8002840: 2200 movs r2, #0 8002842: f883 203c strb.w r2, [r3, #60] @ 0x3c 8002846: e008 b.n 800285a } } else { tmp_hal_status = HAL_ERROR; 8002848: 2301 movs r3, #1 800284a: 75fb strb r3, [r7, #23] /* Process unlocked */ __HAL_UNLOCK(hadc); 800284c: 68fb ldr r3, [r7, #12] 800284e: 2200 movs r2, #0 8002850: f883 203c strb.w r2, [r3, #60] @ 0x3c 8002854: e001 b.n 800285a } } else { tmp_hal_status = HAL_BUSY; 8002856: 2302 movs r3, #2 8002858: 75fb strb r3, [r7, #23] } /* Return function status */ return tmp_hal_status; 800285a: 7dfb ldrb r3, [r7, #23] } 800285c: 4618 mov r0, r3 800285e: 3718 adds r7, #24 8002860: 46bd mov sp, r7 8002862: bd80 pop {r7, pc} 8002864: 50000300 .word 0x50000300 8002868: 50000100 .word 0x50000100 800286c: 080033c5 .word 0x080033c5 8002870: 0800343f .word 0x0800343f 8002874: 0800345b .word 0x0800345b 08002878 : * @brief Handles ADC interrupt request. * @param hadc ADC handle * @retval None */ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) { 8002878: b580 push {r7, lr} 800287a: b088 sub sp, #32 800287c: af00 add r7, sp, #0 800287e: 6078 str r0, [r7, #4] uint32_t overrun_error = 0U; /* flag set if overrun occurrence has to be considered as an error */ 8002880: 2300 movs r3, #0 8002882: 61fb str r3, [r7, #28] ADC_Common_TypeDef *tmpADC_Common; uint32_t tmp_cfgr = 0x0U; 8002884: 2300 movs r3, #0 8002886: 61bb str r3, [r7, #24] uint32_t tmp_cfgr_jqm = 0x0U; 8002888: 2300 movs r3, #0 800288a: 617b str r3, [r7, #20] uint32_t tmp_isr = hadc->Instance->ISR; 800288c: 687b ldr r3, [r7, #4] 800288e: 681b ldr r3, [r3, #0] 8002890: 681b ldr r3, [r3, #0] 8002892: 613b str r3, [r7, #16] uint32_t tmp_ier = hadc->Instance->IER; 8002894: 687b ldr r3, [r7, #4] 8002896: 681b ldr r3, [r3, #0] 8002898: 685b ldr r3, [r3, #4] 800289a: 60fb str r3, [r7, #12] assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); /* ========== Check End of Conversion flag for regular group ========== */ if( (((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) || 800289c: 693b ldr r3, [r7, #16] 800289e: f003 0304 and.w r3, r3, #4 80028a2: 2b00 cmp r3, #0 80028a4: d004 beq.n 80028b0 80028a6: 68fb ldr r3, [r7, #12] 80028a8: f003 0304 and.w r3, r3, #4 80028ac: 2b00 cmp r3, #0 80028ae: d109 bne.n 80028c4 (((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS)) ) 80028b0: 693b ldr r3, [r7, #16] 80028b2: f003 0308 and.w r3, r3, #8 if( (((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) || 80028b6: 2b00 cmp r3, #0 80028b8: d076 beq.n 80029a8 (((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS)) ) 80028ba: 68fb ldr r3, [r7, #12] 80028bc: f003 0308 and.w r3, r3, #8 80028c0: 2b00 cmp r3, #0 80028c2: d071 beq.n 80029a8 { /* Update state machine on conversion status if not in error state */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) 80028c4: 687b ldr r3, [r7, #4] 80028c6: 6c1b ldr r3, [r3, #64] @ 0x40 80028c8: f003 0310 and.w r3, r3, #16 80028cc: 2b00 cmp r3, #0 80028ce: d105 bne.n 80028dc { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 80028d0: 687b ldr r3, [r7, #4] 80028d2: 6c1b ldr r3, [r3, #64] @ 0x40 80028d4: f443 7200 orr.w r2, r3, #512 @ 0x200 80028d8: 687b ldr r3, [r7, #4] 80028da: 641a str r2, [r3, #64] @ 0x40 } /* Get relevant register CFGR in ADC instance of ADC master or slave */ /* in function of multimode state (for devices with multimode */ /* available). */ if (ADC_NONMULTIMODE_REG_OR_MULTIMODEMASTER(hadc)) 80028dc: 4b82 ldr r3, [pc, #520] @ (8002ae8 ) 80028de: 689b ldr r3, [r3, #8] 80028e0: f003 031f and.w r3, r3, #31 80028e4: 2b00 cmp r3, #0 80028e6: d010 beq.n 800290a 80028e8: 4b7f ldr r3, [pc, #508] @ (8002ae8 ) 80028ea: 689b ldr r3, [r3, #8] 80028ec: f003 031f and.w r3, r3, #31 80028f0: 2b05 cmp r3, #5 80028f2: d00a beq.n 800290a 80028f4: 4b7c ldr r3, [pc, #496] @ (8002ae8 ) 80028f6: 689b ldr r3, [r3, #8] 80028f8: f003 031f and.w r3, r3, #31 80028fc: 2b09 cmp r3, #9 80028fe: d004 beq.n 800290a 8002900: 687b ldr r3, [r7, #4] 8002902: 681b ldr r3, [r3, #0] 8002904: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 8002908: d104 bne.n 8002914 { tmp_cfgr = READ_REG(hadc->Instance->CFGR); 800290a: 687b ldr r3, [r7, #4] 800290c: 681b ldr r3, [r3, #0] 800290e: 68db ldr r3, [r3, #12] 8002910: 61bb str r3, [r7, #24] 8002912: e003 b.n 800291c } else { tmp_cfgr = READ_REG(ADC_MASTER_INSTANCE(hadc)->CFGR); 8002914: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 8002918: 68db ldr r3, [r3, #12] 800291a: 61bb str r3, [r7, #24] } /* Disable interruption if no further conversion upcoming by regular */ /* external trigger or by continuous mode, */ /* and if scan sequence if completed. */ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 800291c: 687b ldr r3, [r7, #4] 800291e: 681b ldr r3, [r3, #0] 8002920: 68db ldr r3, [r3, #12] 8002922: f403 6340 and.w r3, r3, #3072 @ 0xc00 8002926: 2b00 cmp r3, #0 8002928: d137 bne.n 800299a (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == RESET) ) 800292a: 69bb ldr r3, [r7, #24] 800292c: f403 5300 and.w r3, r3, #8192 @ 0x2000 if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 8002930: 2b00 cmp r3, #0 8002932: d132 bne.n 800299a { /* If End of Sequence is reached, disable interrupts */ if((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) 8002934: 693b ldr r3, [r7, #16] 8002936: f003 0308 and.w r3, r3, #8 800293a: 2b00 cmp r3, #0 800293c: d02d beq.n 800299a { /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */ /* ADSTART==0 (no conversion on going) */ if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) 800293e: 687b ldr r3, [r7, #4] 8002940: 681b ldr r3, [r3, #0] 8002942: 689b ldr r3, [r3, #8] 8002944: f003 0304 and.w r3, r3, #4 8002948: 2b00 cmp r3, #0 800294a: d11a bne.n 8002982 { /* Disable ADC end of sequence conversion interrupt */ /* Note: Overrun interrupt was enabled with EOC interrupt in */ /* HAL_Start_IT(), but is not disabled here because can be used */ /* by overrun IRQ process below. */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS); 800294c: 687b ldr r3, [r7, #4] 800294e: 681b ldr r3, [r3, #0] 8002950: 685a ldr r2, [r3, #4] 8002952: 687b ldr r3, [r7, #4] 8002954: 681b ldr r3, [r3, #0] 8002956: f022 020c bic.w r2, r2, #12 800295a: 605a str r2, [r3, #4] /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 800295c: 687b ldr r3, [r7, #4] 800295e: 6c1b ldr r3, [r3, #64] @ 0x40 8002960: f423 7280 bic.w r2, r3, #256 @ 0x100 8002964: 687b ldr r3, [r7, #4] 8002966: 641a str r2, [r3, #64] @ 0x40 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 8002968: 687b ldr r3, [r7, #4] 800296a: 6c1b ldr r3, [r3, #64] @ 0x40 800296c: f403 5380 and.w r3, r3, #4096 @ 0x1000 8002970: 2b00 cmp r3, #0 8002972: d112 bne.n 800299a { SET_BIT(hadc->State, HAL_ADC_STATE_READY); 8002974: 687b ldr r3, [r7, #4] 8002976: 6c1b ldr r3, [r3, #64] @ 0x40 8002978: f043 0201 orr.w r2, r3, #1 800297c: 687b ldr r3, [r7, #4] 800297e: 641a str r2, [r3, #64] @ 0x40 8002980: e00b b.n 800299a } } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8002982: 687b ldr r3, [r7, #4] 8002984: 6c1b ldr r3, [r3, #64] @ 0x40 8002986: f043 0210 orr.w r2, r3, #16 800298a: 687b ldr r3, [r7, #4] 800298c: 641a str r2, [r3, #64] @ 0x40 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 800298e: 687b ldr r3, [r7, #4] 8002990: 6c5b ldr r3, [r3, #68] @ 0x44 8002992: f043 0201 orr.w r2, r3, #1 8002996: 687b ldr r3, [r7, #4] 8002998: 645a str r2, [r3, #68] @ 0x44 /* from EOC or EOS, possibility to use: */ /* " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvCpltCallback(hadc); #else HAL_ADC_ConvCpltCallback(hadc); 800299a: 6878 ldr r0, [r7, #4] 800299c: f7fe faa0 bl 8000ee0 /* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of */ /* conversion flags clear induces the release of the preserved */ /* data. */ /* Therefore, if the preserved data value is needed, it must be */ /* read preliminarily into HAL_ADC_ConvCpltCallback(). */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS) ); 80029a0: 687b ldr r3, [r7, #4] 80029a2: 681b ldr r3, [r3, #0] 80029a4: 220c movs r2, #12 80029a6: 601a str r2, [r3, #0] } /* ========== Check End of Conversion flag for injected group ========== */ if( (((tmp_isr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) && ((tmp_ier & ADC_IT_JEOC) == ADC_IT_JEOC)) || 80029a8: 693b ldr r3, [r7, #16] 80029aa: f003 0320 and.w r3, r3, #32 80029ae: 2b00 cmp r3, #0 80029b0: d004 beq.n 80029bc 80029b2: 68fb ldr r3, [r7, #12] 80029b4: f003 0320 and.w r3, r3, #32 80029b8: 2b00 cmp r3, #0 80029ba: d10b bne.n 80029d4 (((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) && ((tmp_ier & ADC_IT_JEOS) == ADC_IT_JEOS)) ) 80029bc: 693b ldr r3, [r7, #16] 80029be: f003 0340 and.w r3, r3, #64 @ 0x40 if( (((tmp_isr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) && ((tmp_ier & ADC_IT_JEOC) == ADC_IT_JEOC)) || 80029c2: 2b00 cmp r3, #0 80029c4: f000 80a5 beq.w 8002b12 (((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) && ((tmp_ier & ADC_IT_JEOS) == ADC_IT_JEOS)) ) 80029c8: 68fb ldr r3, [r7, #12] 80029ca: f003 0340 and.w r3, r3, #64 @ 0x40 80029ce: 2b00 cmp r3, #0 80029d0: f000 809f beq.w 8002b12 { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); 80029d4: 687b ldr r3, [r7, #4] 80029d6: 6c1b ldr r3, [r3, #64] @ 0x40 80029d8: f443 5200 orr.w r2, r3, #8192 @ 0x2000 80029dc: 687b ldr r3, [r7, #4] 80029de: 641a str r2, [r3, #64] @ 0x40 /* Get relevant register CFGR in ADC instance of ADC master or slave */ /* in function of multimode state (for devices with multimode */ /* available). */ if (ADC_NONMULTIMODE_REG_OR_MULTIMODEMASTER(hadc)) 80029e0: 4b41 ldr r3, [pc, #260] @ (8002ae8 ) 80029e2: 689b ldr r3, [r3, #8] 80029e4: f003 031f and.w r3, r3, #31 80029e8: 2b00 cmp r3, #0 80029ea: d010 beq.n 8002a0e 80029ec: 4b3e ldr r3, [pc, #248] @ (8002ae8 ) 80029ee: 689b ldr r3, [r3, #8] 80029f0: f003 031f and.w r3, r3, #31 80029f4: 2b05 cmp r3, #5 80029f6: d00a beq.n 8002a0e 80029f8: 4b3b ldr r3, [pc, #236] @ (8002ae8 ) 80029fa: 689b ldr r3, [r3, #8] 80029fc: f003 031f and.w r3, r3, #31 8002a00: 2b09 cmp r3, #9 8002a02: d004 beq.n 8002a0e 8002a04: 687b ldr r3, [r7, #4] 8002a06: 681b ldr r3, [r3, #0] 8002a08: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 8002a0c: d104 bne.n 8002a18 { tmp_cfgr = READ_REG(hadc->Instance->CFGR); 8002a0e: 687b ldr r3, [r7, #4] 8002a10: 681b ldr r3, [r3, #0] 8002a12: 68db ldr r3, [r3, #12] 8002a14: 61bb str r3, [r7, #24] 8002a16: e003 b.n 8002a20 } else { tmp_cfgr = READ_REG(ADC_MASTER_INSTANCE(hadc)->CFGR); 8002a18: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 8002a1c: 68db ldr r3, [r3, #12] 8002a1e: 61bb str r3, [r7, #24] /* Disable interruption if no further conversion upcoming by injected */ /* external trigger or by automatic injected conversion with regular */ /* group having no further conversion upcoming (same conditions as */ /* regular group interruption disabling above), */ /* and if injected scan sequence is completed. */ if(ADC_IS_SOFTWARE_START_INJECTED(hadc)) 8002a20: 687b ldr r3, [r7, #4] 8002a22: 681b ldr r3, [r3, #0] 8002a24: 6cdb ldr r3, [r3, #76] @ 0x4c 8002a26: f003 03c0 and.w r3, r3, #192 @ 0xc0 8002a2a: 2b00 cmp r3, #0 8002a2c: d16a bne.n 8002b04 { if((READ_BIT (tmp_cfgr, ADC_CFGR_JAUTO) == RESET) || 8002a2e: 69bb ldr r3, [r7, #24] 8002a30: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8002a34: 2b00 cmp r3, #0 8002a36: d00b beq.n 8002a50 (ADC_IS_SOFTWARE_START_REGULAR(hadc) && 8002a38: 687b ldr r3, [r7, #4] 8002a3a: 681b ldr r3, [r3, #0] 8002a3c: 68db ldr r3, [r3, #12] 8002a3e: f403 6340 and.w r3, r3, #3072 @ 0xc00 if((READ_BIT (tmp_cfgr, ADC_CFGR_JAUTO) == RESET) || 8002a42: 2b00 cmp r3, #0 8002a44: d15e bne.n 8002b04 (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) == RESET) ) ) 8002a46: 69bb ldr r3, [r7, #24] 8002a48: f403 5300 and.w r3, r3, #8192 @ 0x2000 (ADC_IS_SOFTWARE_START_REGULAR(hadc) && 8002a4c: 2b00 cmp r3, #0 8002a4e: d159 bne.n 8002b04 { /* If End of Sequence is reached, disable interrupts */ if((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) 8002a50: 693b ldr r3, [r7, #16] 8002a52: f003 0340 and.w r3, r3, #64 @ 0x40 8002a56: 2b00 cmp r3, #0 8002a58: d054 beq.n 8002b04 { /* Get relevant register CFGR in ADC instance of ADC master or slave */ /* in function of multimode state (for devices with multimode */ /* available). */ if (ADC_NONMULTIMODE_INJ_OR_MULTIMODEMASTER(hadc)) 8002a5a: 4b23 ldr r3, [pc, #140] @ (8002ae8 ) 8002a5c: 689b ldr r3, [r3, #8] 8002a5e: f003 031f and.w r3, r3, #31 8002a62: 2b00 cmp r3, #0 8002a64: d010 beq.n 8002a88 8002a66: 4b20 ldr r3, [pc, #128] @ (8002ae8 ) 8002a68: 689b ldr r3, [r3, #8] 8002a6a: f003 031f and.w r3, r3, #31 8002a6e: 2b06 cmp r3, #6 8002a70: d00a beq.n 8002a88 8002a72: 4b1d ldr r3, [pc, #116] @ (8002ae8 ) 8002a74: 689b ldr r3, [r3, #8] 8002a76: f003 031f and.w r3, r3, #31 8002a7a: 2b07 cmp r3, #7 8002a7c: d004 beq.n 8002a88 8002a7e: 687b ldr r3, [r7, #4] 8002a80: 681b ldr r3, [r3, #0] 8002a82: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 8002a86: d104 bne.n 8002a92 { tmp_cfgr_jqm = READ_REG(hadc->Instance->CFGR); 8002a88: 687b ldr r3, [r7, #4] 8002a8a: 681b ldr r3, [r3, #0] 8002a8c: 68db ldr r3, [r3, #12] 8002a8e: 617b str r3, [r7, #20] 8002a90: e003 b.n 8002a9a } else { tmp_cfgr_jqm = READ_REG(ADC_MASTER_INSTANCE(hadc)->CFGR); 8002a92: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 8002a96: 68db ldr r3, [r3, #12] 8002a98: 617b str r3, [r7, #20] /* when the last context has been fully processed, JSQR is reset */ /* by the hardware. Even if no injected conversion is planned to come */ /* (queue empty, triggers are ignored), it can start again */ /* immediately after setting a new context (JADSTART is still set). */ /* Therefore, state of HAL ADC injected group is kept to busy. */ if(READ_BIT(tmp_cfgr_jqm, ADC_CFGR_JQM) == RESET) 8002a9a: 697b ldr r3, [r7, #20] 8002a9c: f403 1300 and.w r3, r3, #2097152 @ 0x200000 8002aa0: 2b00 cmp r3, #0 8002aa2: d12f bne.n 8002b04 { /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */ /* JADSTART==0 (no conversion on going) */ if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET) 8002aa4: 687b ldr r3, [r7, #4] 8002aa6: 681b ldr r3, [r3, #0] 8002aa8: 689b ldr r3, [r3, #8] 8002aaa: f003 0308 and.w r3, r3, #8 8002aae: 2b00 cmp r3, #0 8002ab0: d11c bne.n 8002aec { /* Disable ADC end of sequence conversion interrupt */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS); 8002ab2: 687b ldr r3, [r7, #4] 8002ab4: 681b ldr r3, [r3, #0] 8002ab6: 685a ldr r2, [r3, #4] 8002ab8: 687b ldr r3, [r7, #4] 8002aba: 681b ldr r3, [r3, #0] 8002abc: f022 0260 bic.w r2, r2, #96 @ 0x60 8002ac0: 605a str r2, [r3, #4] /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); 8002ac2: 687b ldr r3, [r7, #4] 8002ac4: 6c1b ldr r3, [r3, #64] @ 0x40 8002ac6: f423 5280 bic.w r2, r3, #4096 @ 0x1000 8002aca: 687b ldr r3, [r7, #4] 8002acc: 641a str r2, [r3, #64] @ 0x40 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) 8002ace: 687b ldr r3, [r7, #4] 8002ad0: 6c1b ldr r3, [r3, #64] @ 0x40 8002ad2: f403 7380 and.w r3, r3, #256 @ 0x100 8002ad6: 2b00 cmp r3, #0 8002ad8: d114 bne.n 8002b04 { SET_BIT(hadc->State, HAL_ADC_STATE_READY); 8002ada: 687b ldr r3, [r7, #4] 8002adc: 6c1b ldr r3, [r3, #64] @ 0x40 8002ade: f043 0201 orr.w r2, r3, #1 8002ae2: 687b ldr r3, [r7, #4] 8002ae4: 641a str r2, [r3, #64] @ 0x40 8002ae6: e00d b.n 8002b04 8002ae8: 50000300 .word 0x50000300 } } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8002aec: 687b ldr r3, [r7, #4] 8002aee: 6c1b ldr r3, [r3, #64] @ 0x40 8002af0: f043 0210 orr.w r2, r3, #16 8002af4: 687b ldr r3, [r7, #4] 8002af6: 641a str r2, [r3, #64] @ 0x40 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8002af8: 687b ldr r3, [r7, #4] 8002afa: 6c5b ldr r3, [r3, #68] @ 0x44 8002afc: f043 0201 orr.w r2, r3, #1 8002b00: 687b ldr r3, [r7, #4] 8002b02: 645a str r2, [r3, #68] @ 0x44 /* from JEOC or JEOS, possibility to use: */ /* " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOS)) " */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->InjectedConvCpltCallback(hadc); #else HAL_ADCEx_InjectedConvCpltCallback(hadc); 8002b04: 6878 ldr r0, [r7, #4] 8002b06: f000 f8b1 bl 8002c6c #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear injected group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC | ADC_FLAG_JEOS); 8002b0a: 687b ldr r3, [r7, #4] 8002b0c: 681b ldr r3, [r3, #0] 8002b0e: 2260 movs r2, #96 @ 0x60 8002b10: 601a str r2, [r3, #0] } /* ========== Check analog watchdog 1 flag ========== */ if(((tmp_isr & ADC_FLAG_AWD1) == ADC_FLAG_AWD1) && ((tmp_ier & ADC_IT_AWD1) == ADC_IT_AWD1)) 8002b12: 693b ldr r3, [r7, #16] 8002b14: f003 0380 and.w r3, r3, #128 @ 0x80 8002b18: 2b00 cmp r3, #0 8002b1a: d011 beq.n 8002b40 8002b1c: 68fb ldr r3, [r7, #12] 8002b1e: f003 0380 and.w r3, r3, #128 @ 0x80 8002b22: 2b00 cmp r3, #0 8002b24: d00c beq.n 8002b40 { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); 8002b26: 687b ldr r3, [r7, #4] 8002b28: 6c1b ldr r3, [r3, #64] @ 0x40 8002b2a: f443 3280 orr.w r2, r3, #65536 @ 0x10000 8002b2e: 687b ldr r3, [r7, #4] 8002b30: 641a str r2, [r3, #64] @ 0x40 /* Level out of window 1 callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->LevelOutOfWindowCallback(hadc); #else HAL_ADC_LevelOutOfWindowCallback(hadc); 8002b32: 6878 ldr r0, [r7, #4] 8002b34: f7ff fc20 bl 8002378 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear ADC analog watchdog flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1); 8002b38: 687b ldr r3, [r7, #4] 8002b3a: 681b ldr r3, [r3, #0] 8002b3c: 2280 movs r2, #128 @ 0x80 8002b3e: 601a str r2, [r3, #0] } /* ========== Check analog watchdog 2 flag ========== */ if(((tmp_isr & ADC_FLAG_AWD2) == ADC_FLAG_AWD2) && ((tmp_ier & ADC_IT_AWD2) == ADC_IT_AWD2)) 8002b40: 693b ldr r3, [r7, #16] 8002b42: f403 7380 and.w r3, r3, #256 @ 0x100 8002b46: 2b00 cmp r3, #0 8002b48: d012 beq.n 8002b70 8002b4a: 68fb ldr r3, [r7, #12] 8002b4c: f403 7380 and.w r3, r3, #256 @ 0x100 8002b50: 2b00 cmp r3, #0 8002b52: d00d beq.n 8002b70 { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_AWD2); 8002b54: 687b ldr r3, [r7, #4] 8002b56: 6c1b ldr r3, [r3, #64] @ 0x40 8002b58: f443 3200 orr.w r2, r3, #131072 @ 0x20000 8002b5c: 687b ldr r3, [r7, #4] 8002b5e: 641a str r2, [r3, #64] @ 0x40 /* Level out of window 2 callback */ HAL_ADCEx_LevelOutOfWindow2Callback(hadc); 8002b60: 6878 ldr r0, [r7, #4] 8002b62: f000 f897 bl 8002c94 /* Clear ADC analog watchdog flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2); 8002b66: 687b ldr r3, [r7, #4] 8002b68: 681b ldr r3, [r3, #0] 8002b6a: f44f 7280 mov.w r2, #256 @ 0x100 8002b6e: 601a str r2, [r3, #0] } /* ========== Check analog watchdog 3 flag ========== */ if(((tmp_isr & ADC_FLAG_AWD3) == ADC_FLAG_AWD3) && ((tmp_ier & ADC_IT_AWD3) == ADC_IT_AWD3)) 8002b70: 693b ldr r3, [r7, #16] 8002b72: f403 7300 and.w r3, r3, #512 @ 0x200 8002b76: 2b00 cmp r3, #0 8002b78: d012 beq.n 8002ba0 8002b7a: 68fb ldr r3, [r7, #12] 8002b7c: f403 7300 and.w r3, r3, #512 @ 0x200 8002b80: 2b00 cmp r3, #0 8002b82: d00d beq.n 8002ba0 { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_AWD3); 8002b84: 687b ldr r3, [r7, #4] 8002b86: 6c1b ldr r3, [r3, #64] @ 0x40 8002b88: f443 2280 orr.w r2, r3, #262144 @ 0x40000 8002b8c: 687b ldr r3, [r7, #4] 8002b8e: 641a str r2, [r3, #64] @ 0x40 /* Level out of window 3 callback */ HAL_ADCEx_LevelOutOfWindow3Callback(hadc); 8002b90: 6878 ldr r0, [r7, #4] 8002b92: f000 f889 bl 8002ca8 /* Clear ADC analog watchdog flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3); 8002b96: 687b ldr r3, [r7, #4] 8002b98: 681b ldr r3, [r3, #0] 8002b9a: f44f 7200 mov.w r2, #512 @ 0x200 8002b9e: 601a str r2, [r3, #0] } /* ========== Check Overrun flag ========== */ if(((tmp_isr & ADC_FLAG_OVR) == ADC_FLAG_OVR) && ((tmp_ier & ADC_IT_OVR) == ADC_IT_OVR)) 8002ba0: 693b ldr r3, [r7, #16] 8002ba2: f003 0310 and.w r3, r3, #16 8002ba6: 2b00 cmp r3, #0 8002ba8: d03b beq.n 8002c22 8002baa: 68fb ldr r3, [r7, #12] 8002bac: f003 0310 and.w r3, r3, #16 8002bb0: 2b00 cmp r3, #0 8002bb2: d036 beq.n 8002c22 /* overrun event is not considered as an error. */ /* (cf ref manual "Managing conversions without using the DMA and */ /* without overrun ") */ /* Exception for usage with DMA overrun event always considered as an */ /* error. */ if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) 8002bb4: 687b ldr r3, [r7, #4] 8002bb6: 6b5b ldr r3, [r3, #52] @ 0x34 8002bb8: 2b01 cmp r3, #1 8002bba: d102 bne.n 8002bc2 { overrun_error = 1U; 8002bbc: 2301 movs r3, #1 8002bbe: 61fb str r3, [r7, #28] 8002bc0: e019 b.n 8002bf6 else { /* Pointer to the common control register to which is belonging hadc */ /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */ /* control registers) */ tmpADC_Common = ADC_COMMON_REGISTER(hadc); 8002bc2: 4b29 ldr r3, [pc, #164] @ (8002c68 ) 8002bc4: 60bb str r3, [r7, #8] /* Check DMA configuration, depending on MultiMode set or not */ if (READ_BIT(tmpADC_Common->CCR, ADC_CCR_MULTI) == ADC_MODE_INDEPENDENT) 8002bc6: 68bb ldr r3, [r7, #8] 8002bc8: 689b ldr r3, [r3, #8] 8002bca: f003 031f and.w r3, r3, #31 8002bce: 2b00 cmp r3, #0 8002bd0: d109 bne.n 8002be6 { if (HAL_IS_BIT_SET(hadc->Instance->CFGR, ADC_CFGR_DMAEN)) 8002bd2: 687b ldr r3, [r7, #4] 8002bd4: 681b ldr r3, [r3, #0] 8002bd6: 68db ldr r3, [r3, #12] 8002bd8: f003 0301 and.w r3, r3, #1 8002bdc: 2b01 cmp r3, #1 8002bde: d10a bne.n 8002bf6 { overrun_error = 1U; 8002be0: 2301 movs r3, #1 8002be2: 61fb str r3, [r7, #28] 8002be4: e007 b.n 8002bf6 } } else { /* MultiMode is enabled, Common Control Register MDMA bits must be checked */ if (READ_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA) != RESET) 8002be6: 68bb ldr r3, [r7, #8] 8002be8: 689b ldr r3, [r3, #8] 8002bea: f403 4340 and.w r3, r3, #49152 @ 0xc000 8002bee: 2b00 cmp r3, #0 8002bf0: d001 beq.n 8002bf6 { overrun_error = 1U; 8002bf2: 2301 movs r3, #1 8002bf4: 61fb str r3, [r7, #28] } } } if (overrun_error == 1U) 8002bf6: 69fb ldr r3, [r7, #28] 8002bf8: 2b01 cmp r3, #1 8002bfa: d10e bne.n 8002c1a { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR); 8002bfc: 687b ldr r3, [r7, #4] 8002bfe: 6c1b ldr r3, [r3, #64] @ 0x40 8002c00: f443 6280 orr.w r2, r3, #1024 @ 0x400 8002c04: 687b ldr r3, [r7, #4] 8002c06: 641a str r2, [r3, #64] @ 0x40 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); 8002c08: 687b ldr r3, [r7, #4] 8002c0a: 6c5b ldr r3, [r3, #68] @ 0x44 8002c0c: f043 0202 orr.w r2, r3, #2 8002c10: 687b ldr r3, [r7, #4] 8002c12: 645a str r2, [r3, #68] @ 0x44 /* Error callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ErrorCallback(hadc); #else HAL_ADC_ErrorCallback(hadc); 8002c14: 6878 ldr r0, [r7, #4] 8002c16: f7ff fbb9 bl 800238c #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } /* Clear the Overrun flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); 8002c1a: 687b ldr r3, [r7, #4] 8002c1c: 681b ldr r3, [r3, #0] 8002c1e: 2210 movs r2, #16 8002c20: 601a str r2, [r3, #0] } /* ========== Check Injected context queue overflow flag ========== */ if(((tmp_isr & ADC_FLAG_JQOVF) == ADC_FLAG_JQOVF) && ((tmp_ier & ADC_IT_JQOVF) == ADC_IT_JQOVF)) 8002c22: 693b ldr r3, [r7, #16] 8002c24: f403 6380 and.w r3, r3, #1024 @ 0x400 8002c28: 2b00 cmp r3, #0 8002c2a: d018 beq.n 8002c5e 8002c2c: 68fb ldr r3, [r7, #12] 8002c2e: f403 6380 and.w r3, r3, #1024 @ 0x400 8002c32: 2b00 cmp r3, #0 8002c34: d013 beq.n 8002c5e { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF); 8002c36: 687b ldr r3, [r7, #4] 8002c38: 6c1b ldr r3, [r3, #64] @ 0x40 8002c3a: f443 4280 orr.w r2, r3, #16384 @ 0x4000 8002c3e: 687b ldr r3, [r7, #4] 8002c40: 641a str r2, [r3, #64] @ 0x40 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF); 8002c42: 687b ldr r3, [r7, #4] 8002c44: 6c5b ldr r3, [r3, #68] @ 0x44 8002c46: f043 0208 orr.w r2, r3, #8 8002c4a: 687b ldr r3, [r7, #4] 8002c4c: 645a str r2, [r3, #68] @ 0x44 /* Clear the Injected context queue overflow flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF); 8002c4e: 687b ldr r3, [r7, #4] 8002c50: 681b ldr r3, [r3, #0] 8002c52: f44f 6280 mov.w r2, #1024 @ 0x400 8002c56: 601a str r2, [r3, #0] /* Error callback */ HAL_ADCEx_InjectedQueueOverflowCallback(hadc); 8002c58: 6878 ldr r0, [r7, #4] 8002c5a: f000 f811 bl 8002c80 } } 8002c5e: bf00 nop 8002c60: 3720 adds r7, #32 8002c62: 46bd mov sp, r7 8002c64: bd80 pop {r7, pc} 8002c66: bf00 nop 8002c68: 50000300 .word 0x50000300 08002c6c : * @brief Injected conversion complete callback in non blocking mode * @param hadc ADC handle * @retval None */ __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc) { 8002c6c: b480 push {r7} 8002c6e: b083 sub sp, #12 8002c70: af00 add r7, sp, #0 8002c72: 6078 str r0, [r7, #4] UNUSED(hadc); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_ADCEx_InjectedConvCpltCallback could be implemented in the user file */ } 8002c74: bf00 nop 8002c76: 370c adds r7, #12 8002c78: 46bd mov sp, r7 8002c7a: f85d 7b04 ldr.w r7, [sp], #4 8002c7e: 4770 bx lr 08002c80 : contexts). * @param hadc ADC handle * @retval None */ __weak void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef* hadc) { 8002c80: b480 push {r7} 8002c82: b083 sub sp, #12 8002c84: af00 add r7, sp, #0 8002c86: 6078 str r0, [r7, #4] /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADCEx_InjectedQueueOverflowCallback must be implemented in the user file. */ } 8002c88: bf00 nop 8002c8a: 370c adds r7, #12 8002c8c: 46bd mov sp, r7 8002c8e: f85d 7b04 ldr.w r7, [sp], #4 8002c92: 4770 bx lr 08002c94 : * @brief Analog watchdog 2 callback in non blocking mode. * @param hadc ADC handle * @retval None */ __weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef* hadc) { 8002c94: b480 push {r7} 8002c96: b083 sub sp, #12 8002c98: af00 add r7, sp, #0 8002c9a: 6078 str r0, [r7, #4] UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_LevelOoutOfWindow2Callback must be implemented in the user file. */ } 8002c9c: bf00 nop 8002c9e: 370c adds r7, #12 8002ca0: 46bd mov sp, r7 8002ca2: f85d 7b04 ldr.w r7, [sp], #4 8002ca6: 4770 bx lr 08002ca8 : * @brief Analog watchdog 3 callback in non blocking mode. * @param hadc ADC handle * @retval None */ __weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef* hadc) { 8002ca8: b480 push {r7} 8002caa: b083 sub sp, #12 8002cac: af00 add r7, sp, #0 8002cae: 6078 str r0, [r7, #4] UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_LevelOoutOfWindow3Callback must be implemented in the user file. */ } 8002cb0: bf00 nop 8002cb2: 370c adds r7, #12 8002cb4: 46bd mov sp, r7 8002cb6: f85d 7b04 ldr.w r7, [sp], #4 8002cba: 4770 bx lr 08002cbc : * @param hadc ADC handle * @param sConfig Structure ADC channel for regular group. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) { 8002cbc: b480 push {r7} 8002cbe: b09b sub sp, #108 @ 0x6c 8002cc0: af00 add r7, sp, #0 8002cc2: 6078 str r0, [r7, #4] 8002cc4: 6039 str r1, [r7, #0] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8002cc6: 2300 movs r3, #0 8002cc8: f887 3067 strb.w r3, [r7, #103] @ 0x67 ADC_Common_TypeDef *tmpADC_Common; ADC_HandleTypeDef tmphadcSharingSameCommonRegister; uint32_t tmpOffsetShifted; __IO uint32_t wait_loop_index = 0U; 8002ccc: 2300 movs r3, #0 8002cce: 60bb str r3, [r7, #8] { assert_param(IS_ADC_DIFF_CHANNEL(sConfig->Channel)); } /* Process locked */ __HAL_LOCK(hadc); 8002cd0: 687b ldr r3, [r7, #4] 8002cd2: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8002cd6: 2b01 cmp r3, #1 8002cd8: d101 bne.n 8002cde 8002cda: 2302 movs r3, #2 8002cdc: e2a1 b.n 8003222 8002cde: 687b ldr r3, [r7, #4] 8002ce0: 2201 movs r2, #1 8002ce2: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - Channel number */ /* - Channel rank */ if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) 8002ce6: 687b ldr r3, [r7, #4] 8002ce8: 681b ldr r3, [r3, #0] 8002cea: 689b ldr r3, [r3, #8] 8002cec: f003 0304 and.w r3, r3, #4 8002cf0: 2b00 cmp r3, #0 8002cf2: f040 8285 bne.w 8003200 { /* Regular sequence configuration */ /* For Rank 1 to 4U */ if (sConfig->Rank < 5U) 8002cf6: 683b ldr r3, [r7, #0] 8002cf8: 685b ldr r3, [r3, #4] 8002cfa: 2b04 cmp r3, #4 8002cfc: d81c bhi.n 8002d38 { MODIFY_REG(hadc->Instance->SQR1, 8002cfe: 687b ldr r3, [r7, #4] 8002d00: 681b ldr r3, [r3, #0] 8002d02: 6b19 ldr r1, [r3, #48] @ 0x30 8002d04: 683b ldr r3, [r7, #0] 8002d06: 685a ldr r2, [r3, #4] 8002d08: 4613 mov r3, r2 8002d0a: 005b lsls r3, r3, #1 8002d0c: 4413 add r3, r2 8002d0e: 005b lsls r3, r3, #1 8002d10: 461a mov r2, r3 8002d12: 231f movs r3, #31 8002d14: 4093 lsls r3, r2 8002d16: 43db mvns r3, r3 8002d18: 4019 ands r1, r3 8002d1a: 683b ldr r3, [r7, #0] 8002d1c: 6818 ldr r0, [r3, #0] 8002d1e: 683b ldr r3, [r7, #0] 8002d20: 685a ldr r2, [r3, #4] 8002d22: 4613 mov r3, r2 8002d24: 005b lsls r3, r3, #1 8002d26: 4413 add r3, r2 8002d28: 005b lsls r3, r3, #1 8002d2a: fa00 f203 lsl.w r2, r0, r3 8002d2e: 687b ldr r3, [r7, #4] 8002d30: 681b ldr r3, [r3, #0] 8002d32: 430a orrs r2, r1 8002d34: 631a str r2, [r3, #48] @ 0x30 8002d36: e063 b.n 8002e00 ADC_SQR1_RK(ADC_SQR2_SQ5, sConfig->Rank) , ADC_SQR1_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 5 to 9U */ else if (sConfig->Rank < 10U) 8002d38: 683b ldr r3, [r7, #0] 8002d3a: 685b ldr r3, [r3, #4] 8002d3c: 2b09 cmp r3, #9 8002d3e: d81e bhi.n 8002d7e { MODIFY_REG(hadc->Instance->SQR2, 8002d40: 687b ldr r3, [r7, #4] 8002d42: 681b ldr r3, [r3, #0] 8002d44: 6b59 ldr r1, [r3, #52] @ 0x34 8002d46: 683b ldr r3, [r7, #0] 8002d48: 685a ldr r2, [r3, #4] 8002d4a: 4613 mov r3, r2 8002d4c: 005b lsls r3, r3, #1 8002d4e: 4413 add r3, r2 8002d50: 005b lsls r3, r3, #1 8002d52: 3b1e subs r3, #30 8002d54: 221f movs r2, #31 8002d56: fa02 f303 lsl.w r3, r2, r3 8002d5a: 43db mvns r3, r3 8002d5c: 4019 ands r1, r3 8002d5e: 683b ldr r3, [r7, #0] 8002d60: 6818 ldr r0, [r3, #0] 8002d62: 683b ldr r3, [r7, #0] 8002d64: 685a ldr r2, [r3, #4] 8002d66: 4613 mov r3, r2 8002d68: 005b lsls r3, r3, #1 8002d6a: 4413 add r3, r2 8002d6c: 005b lsls r3, r3, #1 8002d6e: 3b1e subs r3, #30 8002d70: fa00 f203 lsl.w r2, r0, r3 8002d74: 687b ldr r3, [r7, #4] 8002d76: 681b ldr r3, [r3, #0] 8002d78: 430a orrs r2, r1 8002d7a: 635a str r2, [r3, #52] @ 0x34 8002d7c: e040 b.n 8002e00 ADC_SQR2_RK(ADC_SQR2_SQ5, sConfig->Rank) , ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 10 to 14U */ else if (sConfig->Rank < 15U) 8002d7e: 683b ldr r3, [r7, #0] 8002d80: 685b ldr r3, [r3, #4] 8002d82: 2b0e cmp r3, #14 8002d84: d81e bhi.n 8002dc4 { MODIFY_REG(hadc->Instance->SQR3 , 8002d86: 687b ldr r3, [r7, #4] 8002d88: 681b ldr r3, [r3, #0] 8002d8a: 6b99 ldr r1, [r3, #56] @ 0x38 8002d8c: 683b ldr r3, [r7, #0] 8002d8e: 685a ldr r2, [r3, #4] 8002d90: 4613 mov r3, r2 8002d92: 005b lsls r3, r3, #1 8002d94: 4413 add r3, r2 8002d96: 005b lsls r3, r3, #1 8002d98: 3b3c subs r3, #60 @ 0x3c 8002d9a: 221f movs r2, #31 8002d9c: fa02 f303 lsl.w r3, r2, r3 8002da0: 43db mvns r3, r3 8002da2: 4019 ands r1, r3 8002da4: 683b ldr r3, [r7, #0] 8002da6: 6818 ldr r0, [r3, #0] 8002da8: 683b ldr r3, [r7, #0] 8002daa: 685a ldr r2, [r3, #4] 8002dac: 4613 mov r3, r2 8002dae: 005b lsls r3, r3, #1 8002db0: 4413 add r3, r2 8002db2: 005b lsls r3, r3, #1 8002db4: 3b3c subs r3, #60 @ 0x3c 8002db6: fa00 f203 lsl.w r2, r0, r3 8002dba: 687b ldr r3, [r7, #4] 8002dbc: 681b ldr r3, [r3, #0] 8002dbe: 430a orrs r2, r1 8002dc0: 639a str r2, [r3, #56] @ 0x38 8002dc2: e01d b.n 8002e00 ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 15 to 16U */ else { MODIFY_REG(hadc->Instance->SQR4 , 8002dc4: 687b ldr r3, [r7, #4] 8002dc6: 681b ldr r3, [r3, #0] 8002dc8: 6bd9 ldr r1, [r3, #60] @ 0x3c 8002dca: 683b ldr r3, [r7, #0] 8002dcc: 685a ldr r2, [r3, #4] 8002dce: 4613 mov r3, r2 8002dd0: 005b lsls r3, r3, #1 8002dd2: 4413 add r3, r2 8002dd4: 005b lsls r3, r3, #1 8002dd6: 3b5a subs r3, #90 @ 0x5a 8002dd8: 221f movs r2, #31 8002dda: fa02 f303 lsl.w r3, r2, r3 8002dde: 43db mvns r3, r3 8002de0: 4019 ands r1, r3 8002de2: 683b ldr r3, [r7, #0] 8002de4: 6818 ldr r0, [r3, #0] 8002de6: 683b ldr r3, [r7, #0] 8002de8: 685a ldr r2, [r3, #4] 8002dea: 4613 mov r3, r2 8002dec: 005b lsls r3, r3, #1 8002dee: 4413 add r3, r2 8002df0: 005b lsls r3, r3, #1 8002df2: 3b5a subs r3, #90 @ 0x5a 8002df4: fa00 f203 lsl.w r2, r0, r3 8002df8: 687b ldr r3, [r7, #4] 8002dfa: 681b ldr r3, [r3, #0] 8002dfc: 430a orrs r2, r1 8002dfe: 63da str r2, [r3, #60] @ 0x3c /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - Channel sampling time */ /* - Channel offset */ if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) 8002e00: 687b ldr r3, [r7, #4] 8002e02: 681b ldr r3, [r3, #0] 8002e04: 689b ldr r3, [r3, #8] 8002e06: f003 030c and.w r3, r3, #12 8002e0a: 2b00 cmp r3, #0 8002e0c: f040 80e5 bne.w 8002fda { /* Channel sampling time configuration */ /* For channels 10 to 18U */ if (sConfig->Channel >= ADC_CHANNEL_10) 8002e10: 683b ldr r3, [r7, #0] 8002e12: 681b ldr r3, [r3, #0] 8002e14: 2b09 cmp r3, #9 8002e16: d91c bls.n 8002e52 { MODIFY_REG(hadc->Instance->SMPR2 , 8002e18: 687b ldr r3, [r7, #4] 8002e1a: 681b ldr r3, [r3, #0] 8002e1c: 6999 ldr r1, [r3, #24] 8002e1e: 683b ldr r3, [r7, #0] 8002e20: 681a ldr r2, [r3, #0] 8002e22: 4613 mov r3, r2 8002e24: 005b lsls r3, r3, #1 8002e26: 4413 add r3, r2 8002e28: 3b1e subs r3, #30 8002e2a: 2207 movs r2, #7 8002e2c: fa02 f303 lsl.w r3, r2, r3 8002e30: 43db mvns r3, r3 8002e32: 4019 ands r1, r3 8002e34: 683b ldr r3, [r7, #0] 8002e36: 6898 ldr r0, [r3, #8] 8002e38: 683b ldr r3, [r7, #0] 8002e3a: 681a ldr r2, [r3, #0] 8002e3c: 4613 mov r3, r2 8002e3e: 005b lsls r3, r3, #1 8002e40: 4413 add r3, r2 8002e42: 3b1e subs r3, #30 8002e44: fa00 f203 lsl.w r2, r0, r3 8002e48: 687b ldr r3, [r7, #4] 8002e4a: 681b ldr r3, [r3, #0] 8002e4c: 430a orrs r2, r1 8002e4e: 619a str r2, [r3, #24] 8002e50: e019 b.n 8002e86 ADC_SMPR2(ADC_SMPR2_SMP10, sConfig->Channel) , ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) ); } else /* For channels 1 to 9U */ { MODIFY_REG(hadc->Instance->SMPR1 , 8002e52: 687b ldr r3, [r7, #4] 8002e54: 681b ldr r3, [r3, #0] 8002e56: 6959 ldr r1, [r3, #20] 8002e58: 683b ldr r3, [r7, #0] 8002e5a: 681a ldr r2, [r3, #0] 8002e5c: 4613 mov r3, r2 8002e5e: 005b lsls r3, r3, #1 8002e60: 4413 add r3, r2 8002e62: 2207 movs r2, #7 8002e64: fa02 f303 lsl.w r3, r2, r3 8002e68: 43db mvns r3, r3 8002e6a: 4019 ands r1, r3 8002e6c: 683b ldr r3, [r7, #0] 8002e6e: 6898 ldr r0, [r3, #8] 8002e70: 683b ldr r3, [r7, #0] 8002e72: 681a ldr r2, [r3, #0] 8002e74: 4613 mov r3, r2 8002e76: 005b lsls r3, r3, #1 8002e78: 4413 add r3, r2 8002e7a: fa00 f203 lsl.w r2, r0, r3 8002e7e: 687b ldr r3, [r7, #4] 8002e80: 681b ldr r3, [r3, #0] 8002e82: 430a orrs r2, r1 8002e84: 615a str r2, [r3, #20] /* Configure the offset: offset enable/disable, channel, offset value */ /* Shift the offset in function of the selected ADC resolution. */ /* Offset has to be left-aligned on bit 11U, the LSB (right bits) are set */ /* to 0. */ tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfig->Offset); 8002e86: 683b ldr r3, [r7, #0] 8002e88: 695a ldr r2, [r3, #20] 8002e8a: 687b ldr r3, [r7, #4] 8002e8c: 681b ldr r3, [r3, #0] 8002e8e: 68db ldr r3, [r3, #12] 8002e90: 08db lsrs r3, r3, #3 8002e92: f003 0303 and.w r3, r3, #3 8002e96: 005b lsls r3, r3, #1 8002e98: fa02 f303 lsl.w r3, r2, r3 8002e9c: 663b str r3, [r7, #96] @ 0x60 /* Configure the selected offset register: */ /* - Enable offset */ /* - Set channel number */ /* - Set offset value */ switch (sConfig->OffsetNumber) 8002e9e: 683b ldr r3, [r7, #0] 8002ea0: 691b ldr r3, [r3, #16] 8002ea2: 3b01 subs r3, #1 8002ea4: 2b03 cmp r3, #3 8002ea6: d84f bhi.n 8002f48 8002ea8: a201 add r2, pc, #4 @ (adr r2, 8002eb0 ) 8002eaa: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8002eae: bf00 nop 8002eb0: 08002ec1 .word 0x08002ec1 8002eb4: 08002ee3 .word 0x08002ee3 8002eb8: 08002f05 .word 0x08002f05 8002ebc: 08002f27 .word 0x08002f27 { case ADC_OFFSET_1: /* Configure offset register 1U */ MODIFY_REG(hadc->Instance->OFR1 , 8002ec0: 687b ldr r3, [r7, #4] 8002ec2: 681b ldr r3, [r3, #0] 8002ec4: 6e1a ldr r2, [r3, #96] @ 0x60 8002ec6: 4b9c ldr r3, [pc, #624] @ (8003138 ) 8002ec8: 4013 ands r3, r2 8002eca: 683a ldr r2, [r7, #0] 8002ecc: 6812 ldr r2, [r2, #0] 8002ece: 0691 lsls r1, r2, #26 8002ed0: 6e3a ldr r2, [r7, #96] @ 0x60 8002ed2: 430a orrs r2, r1 8002ed4: 431a orrs r2, r3 8002ed6: 687b ldr r3, [r7, #4] 8002ed8: 681b ldr r3, [r3, #0] 8002eda: f042 4200 orr.w r2, r2, #2147483648 @ 0x80000000 8002ede: 661a str r2, [r3, #96] @ 0x60 ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1 , ADC_OFR1_OFFSET1_EN | ADC_OFR_CHANNEL(sConfig->Channel) | tmpOffsetShifted ); break; 8002ee0: e07b b.n 8002fda case ADC_OFFSET_2: /* Configure offset register 2U */ MODIFY_REG(hadc->Instance->OFR2 , 8002ee2: 687b ldr r3, [r7, #4] 8002ee4: 681b ldr r3, [r3, #0] 8002ee6: 6e5a ldr r2, [r3, #100] @ 0x64 8002ee8: 4b93 ldr r3, [pc, #588] @ (8003138 ) 8002eea: 4013 ands r3, r2 8002eec: 683a ldr r2, [r7, #0] 8002eee: 6812 ldr r2, [r2, #0] 8002ef0: 0691 lsls r1, r2, #26 8002ef2: 6e3a ldr r2, [r7, #96] @ 0x60 8002ef4: 430a orrs r2, r1 8002ef6: 431a orrs r2, r3 8002ef8: 687b ldr r3, [r7, #4] 8002efa: 681b ldr r3, [r3, #0] 8002efc: f042 4200 orr.w r2, r2, #2147483648 @ 0x80000000 8002f00: 665a str r2, [r3, #100] @ 0x64 ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2 , ADC_OFR2_OFFSET2_EN | ADC_OFR_CHANNEL(sConfig->Channel) | tmpOffsetShifted ); break; 8002f02: e06a b.n 8002fda case ADC_OFFSET_3: /* Configure offset register 3U */ MODIFY_REG(hadc->Instance->OFR3 , 8002f04: 687b ldr r3, [r7, #4] 8002f06: 681b ldr r3, [r3, #0] 8002f08: 6e9a ldr r2, [r3, #104] @ 0x68 8002f0a: 4b8b ldr r3, [pc, #556] @ (8003138 ) 8002f0c: 4013 ands r3, r2 8002f0e: 683a ldr r2, [r7, #0] 8002f10: 6812 ldr r2, [r2, #0] 8002f12: 0691 lsls r1, r2, #26 8002f14: 6e3a ldr r2, [r7, #96] @ 0x60 8002f16: 430a orrs r2, r1 8002f18: 431a orrs r2, r3 8002f1a: 687b ldr r3, [r7, #4] 8002f1c: 681b ldr r3, [r3, #0] 8002f1e: f042 4200 orr.w r2, r2, #2147483648 @ 0x80000000 8002f22: 669a str r2, [r3, #104] @ 0x68 ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3 , ADC_OFR3_OFFSET3_EN | ADC_OFR_CHANNEL(sConfig->Channel) | tmpOffsetShifted ); break; 8002f24: e059 b.n 8002fda case ADC_OFFSET_4: /* Configure offset register 4U */ MODIFY_REG(hadc->Instance->OFR4 , 8002f26: 687b ldr r3, [r7, #4] 8002f28: 681b ldr r3, [r3, #0] 8002f2a: 6eda ldr r2, [r3, #108] @ 0x6c 8002f2c: 4b82 ldr r3, [pc, #520] @ (8003138 ) 8002f2e: 4013 ands r3, r2 8002f30: 683a ldr r2, [r7, #0] 8002f32: 6812 ldr r2, [r2, #0] 8002f34: 0691 lsls r1, r2, #26 8002f36: 6e3a ldr r2, [r7, #96] @ 0x60 8002f38: 430a orrs r2, r1 8002f3a: 431a orrs r2, r3 8002f3c: 687b ldr r3, [r7, #4] 8002f3e: 681b ldr r3, [r3, #0] 8002f40: f042 4200 orr.w r2, r2, #2147483648 @ 0x80000000 8002f44: 66da str r2, [r3, #108] @ 0x6c ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4 , ADC_OFR4_OFFSET4_EN | ADC_OFR_CHANNEL(sConfig->Channel) | tmpOffsetShifted ); break; 8002f46: e048 b.n 8002fda /* Case ADC_OFFSET_NONE */ default : /* Scan OFR1, OFR2, OFR3, OFR4 to check if the selected channel is */ /* enabled. If this is the case, offset OFRx is disabled. */ if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) 8002f48: 687b ldr r3, [r7, #4] 8002f4a: 681b ldr r3, [r3, #0] 8002f4c: 6e1b ldr r3, [r3, #96] @ 0x60 8002f4e: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 8002f52: 683b ldr r3, [r7, #0] 8002f54: 681b ldr r3, [r3, #0] 8002f56: 069b lsls r3, r3, #26 8002f58: 429a cmp r2, r3 8002f5a: d107 bne.n 8002f6c { /* Disable offset OFR1*/ CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN); 8002f5c: 687b ldr r3, [r7, #4] 8002f5e: 681b ldr r3, [r3, #0] 8002f60: 6e1a ldr r2, [r3, #96] @ 0x60 8002f62: 687b ldr r3, [r7, #4] 8002f64: 681b ldr r3, [r3, #0] 8002f66: f022 4200 bic.w r2, r2, #2147483648 @ 0x80000000 8002f6a: 661a str r2, [r3, #96] @ 0x60 } if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) 8002f6c: 687b ldr r3, [r7, #4] 8002f6e: 681b ldr r3, [r3, #0] 8002f70: 6e5b ldr r3, [r3, #100] @ 0x64 8002f72: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 8002f76: 683b ldr r3, [r7, #0] 8002f78: 681b ldr r3, [r3, #0] 8002f7a: 069b lsls r3, r3, #26 8002f7c: 429a cmp r2, r3 8002f7e: d107 bne.n 8002f90 { /* Disable offset OFR2*/ CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN); 8002f80: 687b ldr r3, [r7, #4] 8002f82: 681b ldr r3, [r3, #0] 8002f84: 6e5a ldr r2, [r3, #100] @ 0x64 8002f86: 687b ldr r3, [r7, #4] 8002f88: 681b ldr r3, [r3, #0] 8002f8a: f022 4200 bic.w r2, r2, #2147483648 @ 0x80000000 8002f8e: 665a str r2, [r3, #100] @ 0x64 } if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) 8002f90: 687b ldr r3, [r7, #4] 8002f92: 681b ldr r3, [r3, #0] 8002f94: 6e9b ldr r3, [r3, #104] @ 0x68 8002f96: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 8002f9a: 683b ldr r3, [r7, #0] 8002f9c: 681b ldr r3, [r3, #0] 8002f9e: 069b lsls r3, r3, #26 8002fa0: 429a cmp r2, r3 8002fa2: d107 bne.n 8002fb4 { /* Disable offset OFR3*/ CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN); 8002fa4: 687b ldr r3, [r7, #4] 8002fa6: 681b ldr r3, [r3, #0] 8002fa8: 6e9a ldr r2, [r3, #104] @ 0x68 8002faa: 687b ldr r3, [r7, #4] 8002fac: 681b ldr r3, [r3, #0] 8002fae: f022 4200 bic.w r2, r2, #2147483648 @ 0x80000000 8002fb2: 669a str r2, [r3, #104] @ 0x68 } if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) 8002fb4: 687b ldr r3, [r7, #4] 8002fb6: 681b ldr r3, [r3, #0] 8002fb8: 6edb ldr r3, [r3, #108] @ 0x6c 8002fba: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 8002fbe: 683b ldr r3, [r7, #0] 8002fc0: 681b ldr r3, [r3, #0] 8002fc2: 069b lsls r3, r3, #26 8002fc4: 429a cmp r2, r3 8002fc6: d107 bne.n 8002fd8 { /* Disable offset OFR4*/ CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN); 8002fc8: 687b ldr r3, [r7, #4] 8002fca: 681b ldr r3, [r3, #0] 8002fcc: 6eda ldr r2, [r3, #108] @ 0x6c 8002fce: 687b ldr r3, [r7, #4] 8002fd0: 681b ldr r3, [r3, #0] 8002fd2: f022 4200 bic.w r2, r2, #2147483648 @ 0x80000000 8002fd6: 66da str r2, [r3, #108] @ 0x6c } break; 8002fd8: bf00 nop /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - Single or differential mode */ /* - Internal measurement channels: Vbat/VrefInt/TempSensor */ if (ADC_IS_ENABLE(hadc) == RESET) 8002fda: 687b ldr r3, [r7, #4] 8002fdc: 681b ldr r3, [r3, #0] 8002fde: 689b ldr r3, [r3, #8] 8002fe0: f003 0303 and.w r3, r3, #3 8002fe4: 2b01 cmp r3, #1 8002fe6: d108 bne.n 8002ffa 8002fe8: 687b ldr r3, [r7, #4] 8002fea: 681b ldr r3, [r3, #0] 8002fec: 681b ldr r3, [r3, #0] 8002fee: f003 0301 and.w r3, r3, #1 8002ff2: 2b01 cmp r3, #1 8002ff4: d101 bne.n 8002ffa 8002ff6: 2301 movs r3, #1 8002ff8: e000 b.n 8002ffc 8002ffa: 2300 movs r3, #0 8002ffc: 2b00 cmp r3, #0 8002ffe: f040 810a bne.w 8003216 { /* Configuration of differential mode */ if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED) 8003002: 683b ldr r3, [r7, #0] 8003004: 68db ldr r3, [r3, #12] 8003006: 2b01 cmp r3, #1 8003008: d00f beq.n 800302a { /* Disable differential mode (default mode: single-ended) */ CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfig->Channel)); 800300a: 687b ldr r3, [r7, #4] 800300c: 681b ldr r3, [r3, #0] 800300e: f8d3 10b0 ldr.w r1, [r3, #176] @ 0xb0 8003012: 683b ldr r3, [r7, #0] 8003014: 681b ldr r3, [r3, #0] 8003016: 2201 movs r2, #1 8003018: fa02 f303 lsl.w r3, r2, r3 800301c: 43da mvns r2, r3 800301e: 687b ldr r3, [r7, #4] 8003020: 681b ldr r3, [r3, #0] 8003022: 400a ands r2, r1 8003024: f8c3 20b0 str.w r2, [r3, #176] @ 0xb0 8003028: e049 b.n 80030be } else { /* Enable differential mode */ SET_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfig->Channel)); 800302a: 687b ldr r3, [r7, #4] 800302c: 681b ldr r3, [r3, #0] 800302e: f8d3 10b0 ldr.w r1, [r3, #176] @ 0xb0 8003032: 683b ldr r3, [r7, #0] 8003034: 681b ldr r3, [r3, #0] 8003036: 2201 movs r2, #1 8003038: 409a lsls r2, r3 800303a: 687b ldr r3, [r7, #4] 800303c: 681b ldr r3, [r3, #0] 800303e: 430a orrs r2, r1 8003040: f8c3 20b0 str.w r2, [r3, #176] @ 0xb0 /* Channel sampling time configuration (channel ADC_INx +1 */ /* corresponding to differential negative input). */ /* For channels 10 to 18U */ if (sConfig->Channel >= ADC_CHANNEL_10) 8003044: 683b ldr r3, [r7, #0] 8003046: 681b ldr r3, [r3, #0] 8003048: 2b09 cmp r3, #9 800304a: d91c bls.n 8003086 { MODIFY_REG(hadc->Instance->SMPR2, 800304c: 687b ldr r3, [r7, #4] 800304e: 681b ldr r3, [r3, #0] 8003050: 6999 ldr r1, [r3, #24] 8003052: 683b ldr r3, [r7, #0] 8003054: 681a ldr r2, [r3, #0] 8003056: 4613 mov r3, r2 8003058: 005b lsls r3, r3, #1 800305a: 4413 add r3, r2 800305c: 3b1b subs r3, #27 800305e: 2207 movs r2, #7 8003060: fa02 f303 lsl.w r3, r2, r3 8003064: 43db mvns r3, r3 8003066: 4019 ands r1, r3 8003068: 683b ldr r3, [r7, #0] 800306a: 6898 ldr r0, [r3, #8] 800306c: 683b ldr r3, [r7, #0] 800306e: 681a ldr r2, [r3, #0] 8003070: 4613 mov r3, r2 8003072: 005b lsls r3, r3, #1 8003074: 4413 add r3, r2 8003076: 3b1b subs r3, #27 8003078: fa00 f203 lsl.w r2, r0, r3 800307c: 687b ldr r3, [r7, #4] 800307e: 681b ldr r3, [r3, #0] 8003080: 430a orrs r2, r1 8003082: 619a str r2, [r3, #24] 8003084: e01b b.n 80030be ADC_SMPR2(ADC_SMPR2_SMP10, sConfig->Channel +1U) , ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel +1U) ); } else /* For channels 1 to 9U */ { MODIFY_REG(hadc->Instance->SMPR1, 8003086: 687b ldr r3, [r7, #4] 8003088: 681b ldr r3, [r3, #0] 800308a: 6959 ldr r1, [r3, #20] 800308c: 683b ldr r3, [r7, #0] 800308e: 681b ldr r3, [r3, #0] 8003090: 1c5a adds r2, r3, #1 8003092: 4613 mov r3, r2 8003094: 005b lsls r3, r3, #1 8003096: 4413 add r3, r2 8003098: 2207 movs r2, #7 800309a: fa02 f303 lsl.w r3, r2, r3 800309e: 43db mvns r3, r3 80030a0: 4019 ands r1, r3 80030a2: 683b ldr r3, [r7, #0] 80030a4: 6898 ldr r0, [r3, #8] 80030a6: 683b ldr r3, [r7, #0] 80030a8: 681b ldr r3, [r3, #0] 80030aa: 1c5a adds r2, r3, #1 80030ac: 4613 mov r3, r2 80030ae: 005b lsls r3, r3, #1 80030b0: 4413 add r3, r2 80030b2: fa00 f203 lsl.w r2, r0, r3 80030b6: 687b ldr r3, [r7, #4] 80030b8: 681b ldr r3, [r3, #0] 80030ba: 430a orrs r2, r1 80030bc: 615a str r2, [r3, #20] /* Configuration of common ADC parameters */ /* Pointer to the common control register to which is belonging hadc */ /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */ /* control registers) */ tmpADC_Common = ADC_COMMON_REGISTER(hadc); 80030be: 4b1f ldr r3, [pc, #124] @ (800313c ) 80030c0: 65fb str r3, [r7, #92] @ 0x5c /* If the requested internal measurement path has already been enabled, */ /* bypass the configuration processing. */ if (( (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && 80030c2: 683b ldr r3, [r7, #0] 80030c4: 681b ldr r3, [r3, #0] 80030c6: 2b10 cmp r3, #16 80030c8: d105 bne.n 80030d6 (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_TSEN)) ) || 80030ca: 6dfb ldr r3, [r7, #92] @ 0x5c 80030cc: 689b ldr r3, [r3, #8] 80030ce: f403 0300 and.w r3, r3, #8388608 @ 0x800000 if (( (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && 80030d2: 2b00 cmp r3, #0 80030d4: d015 beq.n 8003102 ( (sConfig->Channel == ADC_CHANNEL_VBAT) && 80030d6: 683b ldr r3, [r7, #0] 80030d8: 681b ldr r3, [r3, #0] (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_TSEN)) ) || 80030da: 2b11 cmp r3, #17 80030dc: d105 bne.n 80030ea (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VBATEN)) ) || 80030de: 6dfb ldr r3, [r7, #92] @ 0x5c 80030e0: 689b ldr r3, [r3, #8] 80030e2: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 ( (sConfig->Channel == ADC_CHANNEL_VBAT) && 80030e6: 2b00 cmp r3, #0 80030e8: d00b beq.n 8003102 ( (sConfig->Channel == ADC_CHANNEL_VREFINT) && 80030ea: 683b ldr r3, [r7, #0] 80030ec: 681b ldr r3, [r3, #0] (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VBATEN)) ) || 80030ee: 2b12 cmp r3, #18 80030f0: f040 8091 bne.w 8003216 (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VREFEN))) 80030f4: 6dfb ldr r3, [r7, #92] @ 0x5c 80030f6: 689b ldr r3, [r3, #8] 80030f8: f403 0380 and.w r3, r3, #4194304 @ 0x400000 ( (sConfig->Channel == ADC_CHANNEL_VREFINT) && 80030fc: 2b00 cmp r3, #0 80030fe: f040 808a bne.w 8003216 ) { /* Configuration of common ADC parameters (continuation) */ /* Set handle of the other ADC sharing the same common register */ ADC_COMMON_ADC_OTHER(hadc, &tmphadcSharingSameCommonRegister); 8003102: 687b ldr r3, [r7, #4] 8003104: 681b ldr r3, [r3, #0] 8003106: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 800310a: d102 bne.n 8003112 800310c: 4b0c ldr r3, [pc, #48] @ (8003140 ) 800310e: 60fb str r3, [r7, #12] 8003110: e002 b.n 8003118 8003112: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 8003116: 60fb str r3, [r7, #12] /* Software is allowed to change common parameters only when all ADCs */ /* of the common group are disabled. */ if ((ADC_IS_ENABLE(hadc) == RESET) && 8003118: 687b ldr r3, [r7, #4] 800311a: 681b ldr r3, [r3, #0] 800311c: 689b ldr r3, [r3, #8] 800311e: f003 0303 and.w r3, r3, #3 8003122: 2b01 cmp r3, #1 8003124: d10e bne.n 8003144 8003126: 687b ldr r3, [r7, #4] 8003128: 681b ldr r3, [r3, #0] 800312a: 681b ldr r3, [r3, #0] 800312c: f003 0301 and.w r3, r3, #1 8003130: 2b01 cmp r3, #1 8003132: d107 bne.n 8003144 8003134: 2301 movs r3, #1 8003136: e006 b.n 8003146 8003138: 83fff000 .word 0x83fff000 800313c: 50000300 .word 0x50000300 8003140: 50000100 .word 0x50000100 8003144: 2300 movs r3, #0 8003146: 2b00 cmp r3, #0 8003148: d150 bne.n 80031ec ( (tmphadcSharingSameCommonRegister.Instance == NULL) || 800314a: 68fb ldr r3, [r7, #12] if ((ADC_IS_ENABLE(hadc) == RESET) && 800314c: 2b00 cmp r3, #0 800314e: d010 beq.n 8003172 (ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) ) ) 8003150: 68fb ldr r3, [r7, #12] 8003152: 689b ldr r3, [r3, #8] 8003154: f003 0303 and.w r3, r3, #3 8003158: 2b01 cmp r3, #1 800315a: d107 bne.n 800316c 800315c: 68fb ldr r3, [r7, #12] 800315e: 681b ldr r3, [r3, #0] 8003160: f003 0301 and.w r3, r3, #1 8003164: 2b01 cmp r3, #1 8003166: d101 bne.n 800316c 8003168: 2301 movs r3, #1 800316a: e000 b.n 800316e 800316c: 2300 movs r3, #0 ( (tmphadcSharingSameCommonRegister.Instance == NULL) || 800316e: 2b00 cmp r3, #0 8003170: d13c bne.n 80031ec { /* If Channel_16 is selected, enable Temp. sensor measurement path */ /* Note: Temp. sensor internal channels available on ADC1 only */ if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && (hadc->Instance == ADC1)) 8003172: 683b ldr r3, [r7, #0] 8003174: 681b ldr r3, [r3, #0] 8003176: 2b10 cmp r3, #16 8003178: d11d bne.n 80031b6 800317a: 687b ldr r3, [r7, #4] 800317c: 681b ldr r3, [r3, #0] 800317e: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 8003182: d118 bne.n 80031b6 { SET_BIT(tmpADC_Common->CCR, ADC_CCR_TSEN); 8003184: 6dfb ldr r3, [r7, #92] @ 0x5c 8003186: 689b ldr r3, [r3, #8] 8003188: f443 0200 orr.w r2, r3, #8388608 @ 0x800000 800318c: 6dfb ldr r3, [r7, #92] @ 0x5c 800318e: 609a str r2, [r3, #8] /* Delay for temperature sensor stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); 8003190: 4b27 ldr r3, [pc, #156] @ (8003230 ) 8003192: 681b ldr r3, [r3, #0] 8003194: 4a27 ldr r2, [pc, #156] @ (8003234 ) 8003196: fba2 2303 umull r2, r3, r2, r3 800319a: 0c9a lsrs r2, r3, #18 800319c: 4613 mov r3, r2 800319e: 009b lsls r3, r3, #2 80031a0: 4413 add r3, r2 80031a2: 005b lsls r3, r3, #1 80031a4: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 80031a6: e002 b.n 80031ae { wait_loop_index--; 80031a8: 68bb ldr r3, [r7, #8] 80031aa: 3b01 subs r3, #1 80031ac: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 80031ae: 68bb ldr r3, [r7, #8] 80031b0: 2b00 cmp r3, #0 80031b2: d1f9 bne.n 80031a8 if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && (hadc->Instance == ADC1)) 80031b4: e02e b.n 8003214 } } /* If Channel_17 is selected, enable VBAT measurement path */ /* Note: VBAT internal channels available on ADC1 only */ else if ((sConfig->Channel == ADC_CHANNEL_VBAT) && (hadc->Instance == ADC1)) 80031b6: 683b ldr r3, [r7, #0] 80031b8: 681b ldr r3, [r3, #0] 80031ba: 2b11 cmp r3, #17 80031bc: d10b bne.n 80031d6 80031be: 687b ldr r3, [r7, #4] 80031c0: 681b ldr r3, [r3, #0] 80031c2: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 80031c6: d106 bne.n 80031d6 { SET_BIT(tmpADC_Common->CCR, ADC_CCR_VBATEN); 80031c8: 6dfb ldr r3, [r7, #92] @ 0x5c 80031ca: 689b ldr r3, [r3, #8] 80031cc: f043 7280 orr.w r2, r3, #16777216 @ 0x1000000 80031d0: 6dfb ldr r3, [r7, #92] @ 0x5c 80031d2: 609a str r2, [r3, #8] if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && (hadc->Instance == ADC1)) 80031d4: e01e b.n 8003214 } /* If Channel_18 is selected, enable VREFINT measurement path */ /* Note: VrefInt internal channels available on all ADCs, but only */ /* one ADC is allowed to be connected to VrefInt at the same */ /* time. */ else if (sConfig->Channel == ADC_CHANNEL_VREFINT) 80031d6: 683b ldr r3, [r7, #0] 80031d8: 681b ldr r3, [r3, #0] 80031da: 2b12 cmp r3, #18 80031dc: d11a bne.n 8003214 { SET_BIT(tmpADC_Common->CCR, ADC_CCR_VREFEN); 80031de: 6dfb ldr r3, [r7, #92] @ 0x5c 80031e0: 689b ldr r3, [r3, #8] 80031e2: f443 0280 orr.w r2, r3, #4194304 @ 0x400000 80031e6: 6dfb ldr r3, [r7, #92] @ 0x5c 80031e8: 609a str r2, [r3, #8] if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && (hadc->Instance == ADC1)) 80031ea: e013 b.n 8003214 /* enabled and other ADC of the common group are enabled, internal */ /* measurement paths cannot be enabled. */ else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 80031ec: 687b ldr r3, [r7, #4] 80031ee: 6c1b ldr r3, [r3, #64] @ 0x40 80031f0: f043 0220 orr.w r2, r3, #32 80031f4: 687b ldr r3, [r7, #4] 80031f6: 641a str r2, [r3, #64] @ 0x40 tmp_hal_status = HAL_ERROR; 80031f8: 2301 movs r3, #1 80031fa: f887 3067 strb.w r3, [r7, #103] @ 0x67 80031fe: e00a b.n 8003216 /* channel could be done on neither of the channel configuration structure */ /* parameters. */ else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8003200: 687b ldr r3, [r7, #4] 8003202: 6c1b ldr r3, [r3, #64] @ 0x40 8003204: f043 0220 orr.w r2, r3, #32 8003208: 687b ldr r3, [r7, #4] 800320a: 641a str r2, [r3, #64] @ 0x40 tmp_hal_status = HAL_ERROR; 800320c: 2301 movs r3, #1 800320e: f887 3067 strb.w r3, [r7, #103] @ 0x67 8003212: e000 b.n 8003216 if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && (hadc->Instance == ADC1)) 8003214: bf00 nop } /* Process unlocked */ __HAL_UNLOCK(hadc); 8003216: 687b ldr r3, [r7, #4] 8003218: 2200 movs r2, #0 800321a: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Return function status */ return tmp_hal_status; 800321e: f897 3067 ldrb.w r3, [r7, #103] @ 0x67 } 8003222: 4618 mov r0, r3 8003224: 376c adds r7, #108 @ 0x6c 8003226: 46bd mov sp, r7 8003228: f85d 7b04 ldr.w r7, [sp], #4 800322c: 4770 bx lr 800322e: bf00 nop 8003230: 20000000 .word 0x20000000 8003234: 431bde83 .word 0x431bde83 08003238 : * @param hadc ADC handle * @param multimode Structure of ADC multimode configuration * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode) { 8003238: b480 push {r7} 800323a: b099 sub sp, #100 @ 0x64 800323c: af00 add r7, sp, #0 800323e: 6078 str r0, [r7, #4] 8003240: 6039 str r1, [r7, #0] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8003242: 2300 movs r3, #0 8003244: f887 305f strb.w r3, [r7, #95] @ 0x5f assert_param(IS_ADC_DMA_ACCESS_MODE(multimode->DMAAccessMode)); assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay)); } /* Set handle of the other ADC sharing the same common register */ ADC_COMMON_ADC_OTHER(hadc, &tmphadcSharingSameCommonRegister); 8003248: 687b ldr r3, [r7, #4] 800324a: 681b ldr r3, [r3, #0] 800324c: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 8003250: d102 bne.n 8003258 8003252: 4b5a ldr r3, [pc, #360] @ (80033bc ) 8003254: 60bb str r3, [r7, #8] 8003256: e002 b.n 800325e 8003258: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 800325c: 60bb str r3, [r7, #8] if (tmphadcSharingSameCommonRegister.Instance == NULL) 800325e: 68bb ldr r3, [r7, #8] 8003260: 2b00 cmp r3, #0 8003262: d101 bne.n 8003268 { /* Return function status */ return HAL_ERROR; 8003264: 2301 movs r3, #1 8003266: e0a2 b.n 80033ae } /* Process locked */ __HAL_LOCK(hadc); 8003268: 687b ldr r3, [r7, #4] 800326a: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 800326e: 2b01 cmp r3, #1 8003270: d101 bne.n 8003276 8003272: 2302 movs r3, #2 8003274: e09b b.n 80033ae 8003276: 687b ldr r3, [r7, #4] 8003278: 2201 movs r2, #1 800327a: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - Multimode DMA configuration */ /* - Multimode DMA mode */ if ( (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) 800327e: 687b ldr r3, [r7, #4] 8003280: 681b ldr r3, [r3, #0] 8003282: 689b ldr r3, [r3, #8] 8003284: f003 0304 and.w r3, r3, #4 8003288: 2b00 cmp r3, #0 800328a: d17f bne.n 800338c && (ADC_IS_CONVERSION_ONGOING_REGULAR(&tmphadcSharingSameCommonRegister) == RESET) ) 800328c: 68bb ldr r3, [r7, #8] 800328e: 689b ldr r3, [r3, #8] 8003290: f003 0304 and.w r3, r3, #4 8003294: 2b00 cmp r3, #0 8003296: d179 bne.n 800338c { /* Pointer to the common control register to which is belonging hadc */ /* (Depending on STM32F3 product, there may have up to 4 ADC and 2 common */ /* control registers) */ tmpADC_Common = ADC_COMMON_REGISTER(hadc); 8003298: 4b49 ldr r3, [pc, #292] @ (80033c0 ) 800329a: 65bb str r3, [r7, #88] @ 0x58 /* If multimode is selected, configure all multimode parameters. */ /* Otherwise, reset multimode parameters (can be used in case of */ /* transition from multimode to independent mode). */ if(multimode->Mode != ADC_MODE_INDEPENDENT) 800329c: 683b ldr r3, [r7, #0] 800329e: 681b ldr r3, [r3, #0] 80032a0: 2b00 cmp r3, #0 80032a2: d040 beq.n 8003326 { /* Configuration of ADC common group ADC1&ADC2, ADC3&ADC4 if available */ /* (ADC2, ADC3, ADC4 availability depends on STM32 product) */ /* - DMA access mode */ MODIFY_REG(tmpADC_Common->CCR , 80032a4: 6dbb ldr r3, [r7, #88] @ 0x58 80032a6: 689b ldr r3, [r3, #8] 80032a8: f423 4260 bic.w r2, r3, #57344 @ 0xe000 80032ac: 683b ldr r3, [r7, #0] 80032ae: 6859 ldr r1, [r3, #4] 80032b0: 687b ldr r3, [r7, #4] 80032b2: f893 3030 ldrb.w r3, [r3, #48] @ 0x30 80032b6: 035b lsls r3, r3, #13 80032b8: 430b orrs r3, r1 80032ba: 431a orrs r2, r3 80032bc: 6dbb ldr r3, [r7, #88] @ 0x58 80032be: 609a str r2, [r3, #8] /* parameters, their setting is bypassed without error reporting */ /* (as it can be the expected behaviour in case of intended action */ /* to update parameter above (which fulfills the ADC state */ /* condition: no conversion on going on group regular) */ /* on the fly). */ if ((ADC_IS_ENABLE(hadc) == RESET) && 80032c0: 687b ldr r3, [r7, #4] 80032c2: 681b ldr r3, [r3, #0] 80032c4: 689b ldr r3, [r3, #8] 80032c6: f003 0303 and.w r3, r3, #3 80032ca: 2b01 cmp r3, #1 80032cc: d108 bne.n 80032e0 80032ce: 687b ldr r3, [r7, #4] 80032d0: 681b ldr r3, [r3, #0] 80032d2: 681b ldr r3, [r3, #0] 80032d4: f003 0301 and.w r3, r3, #1 80032d8: 2b01 cmp r3, #1 80032da: d101 bne.n 80032e0 80032dc: 2301 movs r3, #1 80032de: e000 b.n 80032e2 80032e0: 2300 movs r3, #0 80032e2: 2b00 cmp r3, #0 80032e4: d15c bne.n 80033a0 (ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) ) 80032e6: 68bb ldr r3, [r7, #8] 80032e8: 689b ldr r3, [r3, #8] 80032ea: f003 0303 and.w r3, r3, #3 80032ee: 2b01 cmp r3, #1 80032f0: d107 bne.n 8003302 80032f2: 68bb ldr r3, [r7, #8] 80032f4: 681b ldr r3, [r3, #0] 80032f6: f003 0301 and.w r3, r3, #1 80032fa: 2b01 cmp r3, #1 80032fc: d101 bne.n 8003302 80032fe: 2301 movs r3, #1 8003300: e000 b.n 8003304 8003302: 2300 movs r3, #0 if ((ADC_IS_ENABLE(hadc) == RESET) && 8003304: 2b00 cmp r3, #0 8003306: d14b bne.n 80033a0 { MODIFY_REG(tmpADC_Common->CCR , 8003308: 6dbb ldr r3, [r7, #88] @ 0x58 800330a: 689b ldr r3, [r3, #8] 800330c: f423 6371 bic.w r3, r3, #3856 @ 0xf10 8003310: f023 030f bic.w r3, r3, #15 8003314: 683a ldr r2, [r7, #0] 8003316: 6811 ldr r1, [r2, #0] 8003318: 683a ldr r2, [r7, #0] 800331a: 6892 ldr r2, [r2, #8] 800331c: 430a orrs r2, r1 800331e: 431a orrs r2, r3 8003320: 6dbb ldr r3, [r7, #88] @ 0x58 8003322: 609a str r2, [r3, #8] if(multimode->Mode != ADC_MODE_INDEPENDENT) 8003324: e03c b.n 80033a0 multimode->TwoSamplingDelay ); } } else /* ADC_MODE_INDEPENDENT */ { CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG); 8003326: 6dbb ldr r3, [r7, #88] @ 0x58 8003328: 689b ldr r3, [r3, #8] 800332a: f423 4260 bic.w r2, r3, #57344 @ 0xe000 800332e: 6dbb ldr r3, [r7, #88] @ 0x58 8003330: 609a str r2, [r3, #8] /* Parameters that can be updated only when ADC is disabled: */ /* - Multimode mode selection */ /* - Multimode delay */ if ((ADC_IS_ENABLE(hadc) == RESET) && 8003332: 687b ldr r3, [r7, #4] 8003334: 681b ldr r3, [r3, #0] 8003336: 689b ldr r3, [r3, #8] 8003338: f003 0303 and.w r3, r3, #3 800333c: 2b01 cmp r3, #1 800333e: d108 bne.n 8003352 8003340: 687b ldr r3, [r7, #4] 8003342: 681b ldr r3, [r3, #0] 8003344: 681b ldr r3, [r3, #0] 8003346: f003 0301 and.w r3, r3, #1 800334a: 2b01 cmp r3, #1 800334c: d101 bne.n 8003352 800334e: 2301 movs r3, #1 8003350: e000 b.n 8003354 8003352: 2300 movs r3, #0 8003354: 2b00 cmp r3, #0 8003356: d123 bne.n 80033a0 (ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) ) 8003358: 68bb ldr r3, [r7, #8] 800335a: 689b ldr r3, [r3, #8] 800335c: f003 0303 and.w r3, r3, #3 8003360: 2b01 cmp r3, #1 8003362: d107 bne.n 8003374 8003364: 68bb ldr r3, [r7, #8] 8003366: 681b ldr r3, [r3, #0] 8003368: f003 0301 and.w r3, r3, #1 800336c: 2b01 cmp r3, #1 800336e: d101 bne.n 8003374 8003370: 2301 movs r3, #1 8003372: e000 b.n 8003376 8003374: 2300 movs r3, #0 if ((ADC_IS_ENABLE(hadc) == RESET) && 8003376: 2b00 cmp r3, #0 8003378: d112 bne.n 80033a0 { CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_MULTI | ADC_CCR_DELAY); 800337a: 6dbb ldr r3, [r7, #88] @ 0x58 800337c: 689b ldr r3, [r3, #8] 800337e: f423 6371 bic.w r3, r3, #3856 @ 0xf10 8003382: f023 030f bic.w r3, r3, #15 8003386: 6dba ldr r2, [r7, #88] @ 0x58 8003388: 6093 str r3, [r2, #8] if(multimode->Mode != ADC_MODE_INDEPENDENT) 800338a: e009 b.n 80033a0 /* If one of the ADC sharing the same common group is enabled, no update */ /* could be done on neither of the multimode structure parameters. */ else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 800338c: 687b ldr r3, [r7, #4] 800338e: 6c1b ldr r3, [r3, #64] @ 0x40 8003390: f043 0220 orr.w r2, r3, #32 8003394: 687b ldr r3, [r7, #4] 8003396: 641a str r2, [r3, #64] @ 0x40 tmp_hal_status = HAL_ERROR; 8003398: 2301 movs r3, #1 800339a: f887 305f strb.w r3, [r7, #95] @ 0x5f 800339e: e000 b.n 80033a2 if(multimode->Mode != ADC_MODE_INDEPENDENT) 80033a0: bf00 nop } /* Process unlocked */ __HAL_UNLOCK(hadc); 80033a2: 687b ldr r3, [r7, #4] 80033a4: 2200 movs r2, #0 80033a6: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Return function status */ return tmp_hal_status; 80033aa: f897 305f ldrb.w r3, [r7, #95] @ 0x5f } 80033ae: 4618 mov r0, r3 80033b0: 3764 adds r7, #100 @ 0x64 80033b2: 46bd mov sp, r7 80033b4: f85d 7b04 ldr.w r7, [sp], #4 80033b8: 4770 bx lr 80033ba: bf00 nop 80033bc: 50000100 .word 0x50000100 80033c0: 50000300 .word 0x50000300 080033c4 : * @brief DMA transfer complete callback. * @param hdma pointer to DMA handle. * @retval None */ static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) { 80033c4: b580 push {r7, lr} 80033c6: b084 sub sp, #16 80033c8: af00 add r7, sp, #0 80033ca: 6078 str r0, [r7, #4] /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; 80033cc: 687b ldr r3, [r7, #4] 80033ce: 6a5b ldr r3, [r3, #36] @ 0x24 80033d0: 60fb str r3, [r7, #12] /* Update state machine on conversion status if not in error state */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) 80033d2: 68fb ldr r3, [r7, #12] 80033d4: 6c1b ldr r3, [r3, #64] @ 0x40 80033d6: f003 0350 and.w r3, r3, #80 @ 0x50 80033da: 2b00 cmp r3, #0 80033dc: d126 bne.n 800342c { /* Update ADC state machine */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 80033de: 68fb ldr r3, [r7, #12] 80033e0: 6c1b ldr r3, [r3, #64] @ 0x40 80033e2: f443 7200 orr.w r2, r3, #512 @ 0x200 80033e6: 68fb ldr r3, [r7, #12] 80033e8: 641a str r2, [r3, #64] @ 0x40 /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going. */ /* Note: On STM32F3 devices, in case of sequencer enabled */ /* (several ranks selected), end of conversion flag is raised */ /* at the end of the sequence. */ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 80033ea: 68fb ldr r3, [r7, #12] 80033ec: 681b ldr r3, [r3, #0] 80033ee: 68db ldr r3, [r3, #12] 80033f0: f403 6340 and.w r3, r3, #3072 @ 0xc00 80033f4: 2b00 cmp r3, #0 80033f6: d115 bne.n 8003424 (hadc->Init.ContinuousConvMode == DISABLE) ) 80033f8: 68fb ldr r3, [r7, #12] 80033fa: 7e5b ldrb r3, [r3, #25] if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 80033fc: 2b00 cmp r3, #0 80033fe: d111 bne.n 8003424 { /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 8003400: 68fb ldr r3, [r7, #12] 8003402: 6c1b ldr r3, [r3, #64] @ 0x40 8003404: f423 7280 bic.w r2, r3, #256 @ 0x100 8003408: 68fb ldr r3, [r7, #12] 800340a: 641a str r2, [r3, #64] @ 0x40 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 800340c: 68fb ldr r3, [r7, #12] 800340e: 6c1b ldr r3, [r3, #64] @ 0x40 8003410: f403 5380 and.w r3, r3, #4096 @ 0x1000 8003414: 2b00 cmp r3, #0 8003416: d105 bne.n 8003424 { SET_BIT(hadc->State, HAL_ADC_STATE_READY); 8003418: 68fb ldr r3, [r7, #12] 800341a: 6c1b ldr r3, [r3, #64] @ 0x40 800341c: f043 0201 orr.w r2, r3, #1 8003420: 68fb ldr r3, [r7, #12] 8003422: 641a str r2, [r3, #64] @ 0x40 /* Conversion complete callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvCpltCallback(hadc); #else HAL_ADC_ConvCpltCallback(hadc); 8003424: 68f8 ldr r0, [r7, #12] 8003426: f7fd fd5b bl 8000ee0 else { /* Call DMA error callback */ hadc->DMA_Handle->XferErrorCallback(hdma); } } 800342a: e004 b.n 8003436 hadc->DMA_Handle->XferErrorCallback(hdma); 800342c: 68fb ldr r3, [r7, #12] 800342e: 6b9b ldr r3, [r3, #56] @ 0x38 8003430: 6b1b ldr r3, [r3, #48] @ 0x30 8003432: 6878 ldr r0, [r7, #4] 8003434: 4798 blx r3 } 8003436: bf00 nop 8003438: 3710 adds r7, #16 800343a: 46bd mov sp, r7 800343c: bd80 pop {r7, pc} 0800343e : * @brief DMA half transfer complete callback. * @param hdma pointer to DMA handle. * @retval None */ static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) { 800343e: b580 push {r7, lr} 8003440: b084 sub sp, #16 8003442: af00 add r7, sp, #0 8003444: 6078 str r0, [r7, #4] /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; 8003446: 687b ldr r3, [r7, #4] 8003448: 6a5b ldr r3, [r3, #36] @ 0x24 800344a: 60fb str r3, [r7, #12] /* Half conversion callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvHalfCpltCallback(hadc); #else HAL_ADC_ConvHalfCpltCallback(hadc); 800344c: 68f8 ldr r0, [r7, #12] 800344e: f7fe ff89 bl 8002364 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } 8003452: bf00 nop 8003454: 3710 adds r7, #16 8003456: 46bd mov sp, r7 8003458: bd80 pop {r7, pc} 0800345a : * @brief DMA error callback * @param hdma pointer to DMA handle. * @retval None */ static void ADC_DMAError(DMA_HandleTypeDef *hdma) { 800345a: b580 push {r7, lr} 800345c: b084 sub sp, #16 800345e: af00 add r7, sp, #0 8003460: 6078 str r0, [r7, #4] /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; 8003462: 687b ldr r3, [r7, #4] 8003464: 6a5b ldr r3, [r3, #36] @ 0x24 8003466: 60fb str r3, [r7, #12] /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); 8003468: 68fb ldr r3, [r7, #12] 800346a: 6c1b ldr r3, [r3, #64] @ 0x40 800346c: f043 0240 orr.w r2, r3, #64 @ 0x40 8003470: 68fb ldr r3, [r7, #12] 8003472: 641a str r2, [r3, #64] @ 0x40 /* Set ADC error code to DMA error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA); 8003474: 68fb ldr r3, [r7, #12] 8003476: 6c5b ldr r3, [r3, #68] @ 0x44 8003478: f043 0204 orr.w r2, r3, #4 800347c: 68fb ldr r3, [r7, #12] 800347e: 645a str r2, [r3, #68] @ 0x44 /* Error callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ErrorCallback(hadc); #else HAL_ADC_ErrorCallback(hadc); 8003480: 68f8 ldr r0, [r7, #12] 8003482: f7fe ff83 bl 800238c #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } 8003486: bf00 nop 8003488: 3710 adds r7, #16 800348a: 46bd mov sp, r7 800348c: bd80 pop {r7, pc} ... 08003490 : * and voltage regulator must be enabled (done into HAL_ADC_Init()). * @param hadc ADC handle * @retval HAL status. */ static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) { 8003490: b580 push {r7, lr} 8003492: b084 sub sp, #16 8003494: af00 add r7, sp, #0 8003496: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 8003498: 2300 movs r3, #0 800349a: 60fb str r3, [r7, #12] /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ /* enabling phase not yet completed: flag ADC ready not yet set). */ /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ /* causes: ADC clock not running, ...). */ if (ADC_IS_ENABLE(hadc) == RESET) 800349c: 687b ldr r3, [r7, #4] 800349e: 681b ldr r3, [r3, #0] 80034a0: 689b ldr r3, [r3, #8] 80034a2: f003 0303 and.w r3, r3, #3 80034a6: 2b01 cmp r3, #1 80034a8: d108 bne.n 80034bc 80034aa: 687b ldr r3, [r7, #4] 80034ac: 681b ldr r3, [r3, #0] 80034ae: 681b ldr r3, [r3, #0] 80034b0: f003 0301 and.w r3, r3, #1 80034b4: 2b01 cmp r3, #1 80034b6: d101 bne.n 80034bc 80034b8: 2301 movs r3, #1 80034ba: e000 b.n 80034be 80034bc: 2300 movs r3, #0 80034be: 2b00 cmp r3, #0 80034c0: d143 bne.n 800354a { /* Check if conditions to enable the ADC are fulfilled */ if (ADC_ENABLING_CONDITIONS(hadc) == RESET) 80034c2: 687b ldr r3, [r7, #4] 80034c4: 681b ldr r3, [r3, #0] 80034c6: 689a ldr r2, [r3, #8] 80034c8: 4b22 ldr r3, [pc, #136] @ (8003554 ) 80034ca: 4013 ands r3, r2 80034cc: 2b00 cmp r3, #0 80034ce: d00d beq.n 80034ec { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 80034d0: 687b ldr r3, [r7, #4] 80034d2: 6c1b ldr r3, [r3, #64] @ 0x40 80034d4: f043 0210 orr.w r2, r3, #16 80034d8: 687b ldr r3, [r7, #4] 80034da: 641a str r2, [r3, #64] @ 0x40 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 80034dc: 687b ldr r3, [r7, #4] 80034de: 6c5b ldr r3, [r3, #68] @ 0x44 80034e0: f043 0201 orr.w r2, r3, #1 80034e4: 687b ldr r3, [r7, #4] 80034e6: 645a str r2, [r3, #68] @ 0x44 return HAL_ERROR; 80034e8: 2301 movs r3, #1 80034ea: e02f b.n 800354c } /* Enable the ADC peripheral */ __HAL_ADC_ENABLE(hadc); 80034ec: 687b ldr r3, [r7, #4] 80034ee: 681b ldr r3, [r3, #0] 80034f0: 689a ldr r2, [r3, #8] 80034f2: 687b ldr r3, [r7, #4] 80034f4: 681b ldr r3, [r3, #0] 80034f6: f042 0201 orr.w r2, r2, #1 80034fa: 609a str r2, [r3, #8] /* Wait for ADC effectively enabled */ tickstart = HAL_GetTick(); 80034fc: f7fe ff02 bl 8002304 8003500: 60f8 str r0, [r7, #12] while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET) 8003502: e01b b.n 800353c { if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) 8003504: f7fe fefe bl 8002304 8003508: 4602 mov r2, r0 800350a: 68fb ldr r3, [r7, #12] 800350c: 1ad3 subs r3, r2, r3 800350e: 2b02 cmp r3, #2 8003510: d914 bls.n 800353c { /* New check to avoid false timeout detection in case of preemption */ if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET) 8003512: 687b ldr r3, [r7, #4] 8003514: 681b ldr r3, [r3, #0] 8003516: 681b ldr r3, [r3, #0] 8003518: f003 0301 and.w r3, r3, #1 800351c: 2b01 cmp r3, #1 800351e: d00d beq.n 800353c { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8003520: 687b ldr r3, [r7, #4] 8003522: 6c1b ldr r3, [r3, #64] @ 0x40 8003524: f043 0210 orr.w r2, r3, #16 8003528: 687b ldr r3, [r7, #4] 800352a: 641a str r2, [r3, #64] @ 0x40 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 800352c: 687b ldr r3, [r7, #4] 800352e: 6c5b ldr r3, [r3, #68] @ 0x44 8003530: f043 0201 orr.w r2, r3, #1 8003534: 687b ldr r3, [r7, #4] 8003536: 645a str r2, [r3, #68] @ 0x44 return HAL_ERROR; 8003538: 2301 movs r3, #1 800353a: e007 b.n 800354c while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET) 800353c: 687b ldr r3, [r7, #4] 800353e: 681b ldr r3, [r3, #0] 8003540: 681b ldr r3, [r3, #0] 8003542: f003 0301 and.w r3, r3, #1 8003546: 2b01 cmp r3, #1 8003548: d1dc bne.n 8003504 } } } /* Return HAL status */ return HAL_OK; 800354a: 2300 movs r3, #0 } 800354c: 4618 mov r0, r3 800354e: 3710 adds r7, #16 8003550: 46bd mov sp, r7 8003552: bd80 pop {r7, pc} 8003554: 8000003f .word 0x8000003f 08003558 : * stopped. * @param hadc ADC handle * @retval HAL status. */ static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc) { 8003558: b580 push {r7, lr} 800355a: b084 sub sp, #16 800355c: af00 add r7, sp, #0 800355e: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 8003560: 2300 movs r3, #0 8003562: 60fb str r3, [r7, #12] /* Verification if ADC is not already disabled: */ /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */ /* disabled. */ if (ADC_IS_ENABLE(hadc) != RESET ) 8003564: 687b ldr r3, [r7, #4] 8003566: 681b ldr r3, [r3, #0] 8003568: 689b ldr r3, [r3, #8] 800356a: f003 0303 and.w r3, r3, #3 800356e: 2b01 cmp r3, #1 8003570: d108 bne.n 8003584 8003572: 687b ldr r3, [r7, #4] 8003574: 681b ldr r3, [r3, #0] 8003576: 681b ldr r3, [r3, #0] 8003578: f003 0301 and.w r3, r3, #1 800357c: 2b01 cmp r3, #1 800357e: d101 bne.n 8003584 8003580: 2301 movs r3, #1 8003582: e000 b.n 8003586 8003584: 2300 movs r3, #0 8003586: 2b00 cmp r3, #0 8003588: d047 beq.n 800361a { /* Check if conditions to disable the ADC are fulfilled */ if (ADC_DISABLING_CONDITIONS(hadc) != RESET) 800358a: 687b ldr r3, [r7, #4] 800358c: 681b ldr r3, [r3, #0] 800358e: 689b ldr r3, [r3, #8] 8003590: f003 030d and.w r3, r3, #13 8003594: 2b01 cmp r3, #1 8003596: d10f bne.n 80035b8 { /* Disable the ADC peripheral */ __HAL_ADC_DISABLE(hadc); 8003598: 687b ldr r3, [r7, #4] 800359a: 681b ldr r3, [r3, #0] 800359c: 689a ldr r2, [r3, #8] 800359e: 687b ldr r3, [r7, #4] 80035a0: 681b ldr r3, [r3, #0] 80035a2: f042 0202 orr.w r2, r2, #2 80035a6: 609a str r2, [r3, #8] 80035a8: 687b ldr r3, [r7, #4] 80035aa: 681b ldr r3, [r3, #0] 80035ac: 2203 movs r2, #3 80035ae: 601a str r2, [r3, #0] return HAL_ERROR; } /* Wait for ADC effectively disabled */ tickstart = HAL_GetTick(); 80035b0: f7fe fea8 bl 8002304 80035b4: 60f8 str r0, [r7, #12] while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN)) 80035b6: e029 b.n 800360c SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 80035b8: 687b ldr r3, [r7, #4] 80035ba: 6c1b ldr r3, [r3, #64] @ 0x40 80035bc: f043 0210 orr.w r2, r3, #16 80035c0: 687b ldr r3, [r7, #4] 80035c2: 641a str r2, [r3, #64] @ 0x40 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 80035c4: 687b ldr r3, [r7, #4] 80035c6: 6c5b ldr r3, [r3, #68] @ 0x44 80035c8: f043 0201 orr.w r2, r3, #1 80035cc: 687b ldr r3, [r7, #4] 80035ce: 645a str r2, [r3, #68] @ 0x44 return HAL_ERROR; 80035d0: 2301 movs r3, #1 80035d2: e023 b.n 800361c { if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) 80035d4: f7fe fe96 bl 8002304 80035d8: 4602 mov r2, r0 80035da: 68fb ldr r3, [r7, #12] 80035dc: 1ad3 subs r3, r2, r3 80035de: 2b02 cmp r3, #2 80035e0: d914 bls.n 800360c { /* New check to avoid false timeout detection in case of preemption */ if(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN)) 80035e2: 687b ldr r3, [r7, #4] 80035e4: 681b ldr r3, [r3, #0] 80035e6: 689b ldr r3, [r3, #8] 80035e8: f003 0301 and.w r3, r3, #1 80035ec: 2b01 cmp r3, #1 80035ee: d10d bne.n 800360c { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 80035f0: 687b ldr r3, [r7, #4] 80035f2: 6c1b ldr r3, [r3, #64] @ 0x40 80035f4: f043 0210 orr.w r2, r3, #16 80035f8: 687b ldr r3, [r7, #4] 80035fa: 641a str r2, [r3, #64] @ 0x40 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 80035fc: 687b ldr r3, [r7, #4] 80035fe: 6c5b ldr r3, [r3, #68] @ 0x44 8003600: f043 0201 orr.w r2, r3, #1 8003604: 687b ldr r3, [r7, #4] 8003606: 645a str r2, [r3, #68] @ 0x44 return HAL_ERROR; 8003608: 2301 movs r3, #1 800360a: e007 b.n 800361c while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN)) 800360c: 687b ldr r3, [r7, #4] 800360e: 681b ldr r3, [r3, #0] 8003610: 689b ldr r3, [r3, #8] 8003612: f003 0301 and.w r3, r3, #1 8003616: 2b01 cmp r3, #1 8003618: d0dc beq.n 80035d4 } } } /* Return HAL status */ return HAL_OK; 800361a: 2300 movs r3, #0 } 800361c: 4618 mov r0, r3 800361e: 3710 adds r7, #16 8003620: 46bd mov sp, r7 8003622: bd80 pop {r7, pc} 08003624 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan) { 8003624: b580 push {r7, lr} 8003626: b084 sub sp, #16 8003628: af00 add r7, sp, #0 800362a: 6078 str r0, [r7, #4] uint32_t tickstart; /* Check CAN handle */ if (hcan == NULL) 800362c: 687b ldr r3, [r7, #4] 800362e: 2b00 cmp r3, #0 8003630: d101 bne.n 8003636 { return HAL_ERROR; 8003632: 2301 movs r3, #1 8003634: e0ed b.n 8003812 /* Init the low level hardware: CLOCK, NVIC */ hcan->MspInitCallback(hcan); } #else if (hcan->State == HAL_CAN_STATE_RESET) 8003636: 687b ldr r3, [r7, #4] 8003638: f893 3020 ldrb.w r3, [r3, #32] 800363c: b2db uxtb r3, r3 800363e: 2b00 cmp r3, #0 8003640: d102 bne.n 8003648 { /* Init the low level hardware: CLOCK, NVIC */ HAL_CAN_MspInit(hcan); 8003642: 6878 ldr r0, [r7, #4] 8003644: f7fe fc9a bl 8001f7c } #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ /* Request initialisation */ SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); 8003648: 687b ldr r3, [r7, #4] 800364a: 681b ldr r3, [r3, #0] 800364c: 681a ldr r2, [r3, #0] 800364e: 687b ldr r3, [r7, #4] 8003650: 681b ldr r3, [r3, #0] 8003652: f042 0201 orr.w r2, r2, #1 8003656: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 8003658: f7fe fe54 bl 8002304 800365c: 60f8 str r0, [r7, #12] /* Wait initialisation acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) 800365e: e012 b.n 8003686 { if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) 8003660: f7fe fe50 bl 8002304 8003664: 4602 mov r2, r0 8003666: 68fb ldr r3, [r7, #12] 8003668: 1ad3 subs r3, r2, r3 800366a: 2b0a cmp r3, #10 800366c: d90b bls.n 8003686 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; 800366e: 687b ldr r3, [r7, #4] 8003670: 6a5b ldr r3, [r3, #36] @ 0x24 8003672: f443 3200 orr.w r2, r3, #131072 @ 0x20000 8003676: 687b ldr r3, [r7, #4] 8003678: 625a str r2, [r3, #36] @ 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; 800367a: 687b ldr r3, [r7, #4] 800367c: 2205 movs r2, #5 800367e: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 8003682: 2301 movs r3, #1 8003684: e0c5 b.n 8003812 while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) 8003686: 687b ldr r3, [r7, #4] 8003688: 681b ldr r3, [r3, #0] 800368a: 685b ldr r3, [r3, #4] 800368c: f003 0301 and.w r3, r3, #1 8003690: 2b00 cmp r3, #0 8003692: d0e5 beq.n 8003660 } } /* Exit from sleep mode */ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); 8003694: 687b ldr r3, [r7, #4] 8003696: 681b ldr r3, [r3, #0] 8003698: 681a ldr r2, [r3, #0] 800369a: 687b ldr r3, [r7, #4] 800369c: 681b ldr r3, [r3, #0] 800369e: f022 0202 bic.w r2, r2, #2 80036a2: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 80036a4: f7fe fe2e bl 8002304 80036a8: 60f8 str r0, [r7, #12] /* Check Sleep mode leave acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) 80036aa: e012 b.n 80036d2 { if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) 80036ac: f7fe fe2a bl 8002304 80036b0: 4602 mov r2, r0 80036b2: 68fb ldr r3, [r7, #12] 80036b4: 1ad3 subs r3, r2, r3 80036b6: 2b0a cmp r3, #10 80036b8: d90b bls.n 80036d2 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; 80036ba: 687b ldr r3, [r7, #4] 80036bc: 6a5b ldr r3, [r3, #36] @ 0x24 80036be: f443 3200 orr.w r2, r3, #131072 @ 0x20000 80036c2: 687b ldr r3, [r7, #4] 80036c4: 625a str r2, [r3, #36] @ 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; 80036c6: 687b ldr r3, [r7, #4] 80036c8: 2205 movs r2, #5 80036ca: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 80036ce: 2301 movs r3, #1 80036d0: e09f b.n 8003812 while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) 80036d2: 687b ldr r3, [r7, #4] 80036d4: 681b ldr r3, [r3, #0] 80036d6: 685b ldr r3, [r3, #4] 80036d8: f003 0302 and.w r3, r3, #2 80036dc: 2b00 cmp r3, #0 80036de: d1e5 bne.n 80036ac } } /* Set the time triggered communication mode */ if (hcan->Init.TimeTriggeredMode == ENABLE) 80036e0: 687b ldr r3, [r7, #4] 80036e2: 7e1b ldrb r3, [r3, #24] 80036e4: 2b01 cmp r3, #1 80036e6: d108 bne.n 80036fa { SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); 80036e8: 687b ldr r3, [r7, #4] 80036ea: 681b ldr r3, [r3, #0] 80036ec: 681a ldr r2, [r3, #0] 80036ee: 687b ldr r3, [r7, #4] 80036f0: 681b ldr r3, [r3, #0] 80036f2: f042 0280 orr.w r2, r2, #128 @ 0x80 80036f6: 601a str r2, [r3, #0] 80036f8: e007 b.n 800370a } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); 80036fa: 687b ldr r3, [r7, #4] 80036fc: 681b ldr r3, [r3, #0] 80036fe: 681a ldr r2, [r3, #0] 8003700: 687b ldr r3, [r7, #4] 8003702: 681b ldr r3, [r3, #0] 8003704: f022 0280 bic.w r2, r2, #128 @ 0x80 8003708: 601a str r2, [r3, #0] } /* Set the automatic bus-off management */ if (hcan->Init.AutoBusOff == ENABLE) 800370a: 687b ldr r3, [r7, #4] 800370c: 7e5b ldrb r3, [r3, #25] 800370e: 2b01 cmp r3, #1 8003710: d108 bne.n 8003724 { SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); 8003712: 687b ldr r3, [r7, #4] 8003714: 681b ldr r3, [r3, #0] 8003716: 681a ldr r2, [r3, #0] 8003718: 687b ldr r3, [r7, #4] 800371a: 681b ldr r3, [r3, #0] 800371c: f042 0240 orr.w r2, r2, #64 @ 0x40 8003720: 601a str r2, [r3, #0] 8003722: e007 b.n 8003734 } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); 8003724: 687b ldr r3, [r7, #4] 8003726: 681b ldr r3, [r3, #0] 8003728: 681a ldr r2, [r3, #0] 800372a: 687b ldr r3, [r7, #4] 800372c: 681b ldr r3, [r3, #0] 800372e: f022 0240 bic.w r2, r2, #64 @ 0x40 8003732: 601a str r2, [r3, #0] } /* Set the automatic wake-up mode */ if (hcan->Init.AutoWakeUp == ENABLE) 8003734: 687b ldr r3, [r7, #4] 8003736: 7e9b ldrb r3, [r3, #26] 8003738: 2b01 cmp r3, #1 800373a: d108 bne.n 800374e { SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); 800373c: 687b ldr r3, [r7, #4] 800373e: 681b ldr r3, [r3, #0] 8003740: 681a ldr r2, [r3, #0] 8003742: 687b ldr r3, [r7, #4] 8003744: 681b ldr r3, [r3, #0] 8003746: f042 0220 orr.w r2, r2, #32 800374a: 601a str r2, [r3, #0] 800374c: e007 b.n 800375e } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); 800374e: 687b ldr r3, [r7, #4] 8003750: 681b ldr r3, [r3, #0] 8003752: 681a ldr r2, [r3, #0] 8003754: 687b ldr r3, [r7, #4] 8003756: 681b ldr r3, [r3, #0] 8003758: f022 0220 bic.w r2, r2, #32 800375c: 601a str r2, [r3, #0] } /* Set the automatic retransmission */ if (hcan->Init.AutoRetransmission == ENABLE) 800375e: 687b ldr r3, [r7, #4] 8003760: 7edb ldrb r3, [r3, #27] 8003762: 2b01 cmp r3, #1 8003764: d108 bne.n 8003778 { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART); 8003766: 687b ldr r3, [r7, #4] 8003768: 681b ldr r3, [r3, #0] 800376a: 681a ldr r2, [r3, #0] 800376c: 687b ldr r3, [r7, #4] 800376e: 681b ldr r3, [r3, #0] 8003770: f022 0210 bic.w r2, r2, #16 8003774: 601a str r2, [r3, #0] 8003776: e007 b.n 8003788 } else { SET_BIT(hcan->Instance->MCR, CAN_MCR_NART); 8003778: 687b ldr r3, [r7, #4] 800377a: 681b ldr r3, [r3, #0] 800377c: 681a ldr r2, [r3, #0] 800377e: 687b ldr r3, [r7, #4] 8003780: 681b ldr r3, [r3, #0] 8003782: f042 0210 orr.w r2, r2, #16 8003786: 601a str r2, [r3, #0] } /* Set the receive FIFO locked mode */ if (hcan->Init.ReceiveFifoLocked == ENABLE) 8003788: 687b ldr r3, [r7, #4] 800378a: 7f1b ldrb r3, [r3, #28] 800378c: 2b01 cmp r3, #1 800378e: d108 bne.n 80037a2 { SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); 8003790: 687b ldr r3, [r7, #4] 8003792: 681b ldr r3, [r3, #0] 8003794: 681a ldr r2, [r3, #0] 8003796: 687b ldr r3, [r7, #4] 8003798: 681b ldr r3, [r3, #0] 800379a: f042 0208 orr.w r2, r2, #8 800379e: 601a str r2, [r3, #0] 80037a0: e007 b.n 80037b2 } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); 80037a2: 687b ldr r3, [r7, #4] 80037a4: 681b ldr r3, [r3, #0] 80037a6: 681a ldr r2, [r3, #0] 80037a8: 687b ldr r3, [r7, #4] 80037aa: 681b ldr r3, [r3, #0] 80037ac: f022 0208 bic.w r2, r2, #8 80037b0: 601a str r2, [r3, #0] } /* Set the transmit FIFO priority */ if (hcan->Init.TransmitFifoPriority == ENABLE) 80037b2: 687b ldr r3, [r7, #4] 80037b4: 7f5b ldrb r3, [r3, #29] 80037b6: 2b01 cmp r3, #1 80037b8: d108 bne.n 80037cc { SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); 80037ba: 687b ldr r3, [r7, #4] 80037bc: 681b ldr r3, [r3, #0] 80037be: 681a ldr r2, [r3, #0] 80037c0: 687b ldr r3, [r7, #4] 80037c2: 681b ldr r3, [r3, #0] 80037c4: f042 0204 orr.w r2, r2, #4 80037c8: 601a str r2, [r3, #0] 80037ca: e007 b.n 80037dc } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); 80037cc: 687b ldr r3, [r7, #4] 80037ce: 681b ldr r3, [r3, #0] 80037d0: 681a ldr r2, [r3, #0] 80037d2: 687b ldr r3, [r7, #4] 80037d4: 681b ldr r3, [r3, #0] 80037d6: f022 0204 bic.w r2, r2, #4 80037da: 601a str r2, [r3, #0] } /* Set the bit timing register */ WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode | 80037dc: 687b ldr r3, [r7, #4] 80037de: 689a ldr r2, [r3, #8] 80037e0: 687b ldr r3, [r7, #4] 80037e2: 68db ldr r3, [r3, #12] 80037e4: 431a orrs r2, r3 80037e6: 687b ldr r3, [r7, #4] 80037e8: 691b ldr r3, [r3, #16] 80037ea: 431a orrs r2, r3 80037ec: 687b ldr r3, [r7, #4] 80037ee: 695b ldr r3, [r3, #20] 80037f0: ea42 0103 orr.w r1, r2, r3 80037f4: 687b ldr r3, [r7, #4] 80037f6: 685b ldr r3, [r3, #4] 80037f8: 1e5a subs r2, r3, #1 80037fa: 687b ldr r3, [r7, #4] 80037fc: 681b ldr r3, [r3, #0] 80037fe: 430a orrs r2, r1 8003800: 61da str r2, [r3, #28] hcan->Init.TimeSeg1 | hcan->Init.TimeSeg2 | (hcan->Init.Prescaler - 1U))); /* Initialize the error code */ hcan->ErrorCode = HAL_CAN_ERROR_NONE; 8003802: 687b ldr r3, [r7, #4] 8003804: 2200 movs r2, #0 8003806: 625a str r2, [r3, #36] @ 0x24 /* Initialize the CAN state */ hcan->State = HAL_CAN_STATE_READY; 8003808: 687b ldr r3, [r7, #4] 800380a: 2201 movs r2, #1 800380c: f883 2020 strb.w r2, [r3, #32] /* Return function status */ return HAL_OK; 8003810: 2300 movs r3, #0 } 8003812: 4618 mov r0, r3 8003814: 3710 adds r7, #16 8003816: 46bd mov sp, r7 8003818: bd80 pop {r7, pc} 0800381a : * @param sFilterConfig pointer to a CAN_FilterTypeDef structure that * contains the filter configuration information. * @retval None */ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_FilterTypeDef *sFilterConfig) { 800381a: b480 push {r7} 800381c: b087 sub sp, #28 800381e: af00 add r7, sp, #0 8003820: 6078 str r0, [r7, #4] 8003822: 6039 str r1, [r7, #0] uint32_t filternbrbitpos; CAN_TypeDef *can_ip = hcan->Instance; 8003824: 687b ldr r3, [r7, #4] 8003826: 681b ldr r3, [r3, #0] 8003828: 617b str r3, [r7, #20] HAL_CAN_StateTypeDef state = hcan->State; 800382a: 687b ldr r3, [r7, #4] 800382c: f893 3020 ldrb.w r3, [r3, #32] 8003830: 74fb strb r3, [r7, #19] if ((state == HAL_CAN_STATE_READY) || 8003832: 7cfb ldrb r3, [r7, #19] 8003834: 2b01 cmp r3, #1 8003836: d003 beq.n 8003840 8003838: 7cfb ldrb r3, [r7, #19] 800383a: 2b02 cmp r3, #2 800383c: f040 80aa bne.w 8003994 /* Check the parameters */ assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank)); /* Initialisation mode for the filter */ SET_BIT(can_ip->FMR, CAN_FMR_FINIT); 8003840: 697b ldr r3, [r7, #20] 8003842: f8d3 3200 ldr.w r3, [r3, #512] @ 0x200 8003846: f043 0201 orr.w r2, r3, #1 800384a: 697b ldr r3, [r7, #20] 800384c: f8c3 2200 str.w r2, [r3, #512] @ 0x200 /* Convert filter number into bit position */ filternbrbitpos = (uint32_t)1 << (sFilterConfig->FilterBank & 0x1FU); 8003850: 683b ldr r3, [r7, #0] 8003852: 695b ldr r3, [r3, #20] 8003854: f003 031f and.w r3, r3, #31 8003858: 2201 movs r2, #1 800385a: fa02 f303 lsl.w r3, r2, r3 800385e: 60fb str r3, [r7, #12] /* Filter Deactivation */ CLEAR_BIT(can_ip->FA1R, filternbrbitpos); 8003860: 697b ldr r3, [r7, #20] 8003862: f8d3 221c ldr.w r2, [r3, #540] @ 0x21c 8003866: 68fb ldr r3, [r7, #12] 8003868: 43db mvns r3, r3 800386a: 401a ands r2, r3 800386c: 697b ldr r3, [r7, #20] 800386e: f8c3 221c str.w r2, [r3, #540] @ 0x21c /* Filter Scale */ if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT) 8003872: 683b ldr r3, [r7, #0] 8003874: 69db ldr r3, [r3, #28] 8003876: 2b00 cmp r3, #0 8003878: d123 bne.n 80038c2 { /* 16-bit scale for the filter */ CLEAR_BIT(can_ip->FS1R, filternbrbitpos); 800387a: 697b ldr r3, [r7, #20] 800387c: f8d3 220c ldr.w r2, [r3, #524] @ 0x20c 8003880: 68fb ldr r3, [r7, #12] 8003882: 43db mvns r3, r3 8003884: 401a ands r2, r3 8003886: 697b ldr r3, [r7, #20] 8003888: f8c3 220c str.w r2, [r3, #524] @ 0x20c /* First 16-bit identifier and First 16-bit mask */ /* Or First 16-bit identifier and Second 16-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | 800388c: 683b ldr r3, [r7, #0] 800388e: 68db ldr r3, [r3, #12] 8003890: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); 8003892: 683b ldr r3, [r7, #0] 8003894: 685b ldr r3, [r3, #4] 8003896: b29b uxth r3, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = 8003898: 683a ldr r2, [r7, #0] 800389a: 6952 ldr r2, [r2, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | 800389c: 4319 orrs r1, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = 800389e: 697b ldr r3, [r7, #20] 80038a0: 3248 adds r2, #72 @ 0x48 80038a2: f843 1032 str.w r1, [r3, r2, lsl #3] /* Second 16-bit identifier and Second 16-bit mask */ /* Or Third 16-bit identifier and Fourth 16-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | 80038a6: 683b ldr r3, [r7, #0] 80038a8: 689b ldr r3, [r3, #8] 80038aa: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh); 80038ac: 683b ldr r3, [r7, #0] 80038ae: 681b ldr r3, [r3, #0] 80038b0: b29a uxth r2, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = 80038b2: 683b ldr r3, [r7, #0] 80038b4: 695b ldr r3, [r3, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | 80038b6: 430a orrs r2, r1 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = 80038b8: 6979 ldr r1, [r7, #20] 80038ba: 3348 adds r3, #72 @ 0x48 80038bc: 00db lsls r3, r3, #3 80038be: 440b add r3, r1 80038c0: 605a str r2, [r3, #4] } if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT) 80038c2: 683b ldr r3, [r7, #0] 80038c4: 69db ldr r3, [r3, #28] 80038c6: 2b01 cmp r3, #1 80038c8: d122 bne.n 8003910 { /* 32-bit scale for the filter */ SET_BIT(can_ip->FS1R, filternbrbitpos); 80038ca: 697b ldr r3, [r7, #20] 80038cc: f8d3 220c ldr.w r2, [r3, #524] @ 0x20c 80038d0: 68fb ldr r3, [r7, #12] 80038d2: 431a orrs r2, r3 80038d4: 697b ldr r3, [r7, #20] 80038d6: f8c3 220c str.w r2, [r3, #524] @ 0x20c /* 32-bit identifier or First 32-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | 80038da: 683b ldr r3, [r7, #0] 80038dc: 681b ldr r3, [r3, #0] 80038de: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); 80038e0: 683b ldr r3, [r7, #0] 80038e2: 685b ldr r3, [r3, #4] 80038e4: b29b uxth r3, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = 80038e6: 683a ldr r2, [r7, #0] 80038e8: 6952 ldr r2, [r2, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | 80038ea: 4319 orrs r1, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = 80038ec: 697b ldr r3, [r7, #20] 80038ee: 3248 adds r2, #72 @ 0x48 80038f0: f843 1032 str.w r1, [r3, r2, lsl #3] /* 32-bit mask or Second 32-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | 80038f4: 683b ldr r3, [r7, #0] 80038f6: 689b ldr r3, [r3, #8] 80038f8: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow); 80038fa: 683b ldr r3, [r7, #0] 80038fc: 68db ldr r3, [r3, #12] 80038fe: b29a uxth r2, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = 8003900: 683b ldr r3, [r7, #0] 8003902: 695b ldr r3, [r3, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | 8003904: 430a orrs r2, r1 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = 8003906: 6979 ldr r1, [r7, #20] 8003908: 3348 adds r3, #72 @ 0x48 800390a: 00db lsls r3, r3, #3 800390c: 440b add r3, r1 800390e: 605a str r2, [r3, #4] } /* Filter Mode */ if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK) 8003910: 683b ldr r3, [r7, #0] 8003912: 699b ldr r3, [r3, #24] 8003914: 2b00 cmp r3, #0 8003916: d109 bne.n 800392c { /* Id/Mask mode for the filter*/ CLEAR_BIT(can_ip->FM1R, filternbrbitpos); 8003918: 697b ldr r3, [r7, #20] 800391a: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204 800391e: 68fb ldr r3, [r7, #12] 8003920: 43db mvns r3, r3 8003922: 401a ands r2, r3 8003924: 697b ldr r3, [r7, #20] 8003926: f8c3 2204 str.w r2, [r3, #516] @ 0x204 800392a: e007 b.n 800393c } else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ { /* Identifier list mode for the filter*/ SET_BIT(can_ip->FM1R, filternbrbitpos); 800392c: 697b ldr r3, [r7, #20] 800392e: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204 8003932: 68fb ldr r3, [r7, #12] 8003934: 431a orrs r2, r3 8003936: 697b ldr r3, [r7, #20] 8003938: f8c3 2204 str.w r2, [r3, #516] @ 0x204 } /* Filter FIFO assignment */ if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0) 800393c: 683b ldr r3, [r7, #0] 800393e: 691b ldr r3, [r3, #16] 8003940: 2b00 cmp r3, #0 8003942: d109 bne.n 8003958 { /* FIFO 0 assignation for the filter */ CLEAR_BIT(can_ip->FFA1R, filternbrbitpos); 8003944: 697b ldr r3, [r7, #20] 8003946: f8d3 2214 ldr.w r2, [r3, #532] @ 0x214 800394a: 68fb ldr r3, [r7, #12] 800394c: 43db mvns r3, r3 800394e: 401a ands r2, r3 8003950: 697b ldr r3, [r7, #20] 8003952: f8c3 2214 str.w r2, [r3, #532] @ 0x214 8003956: e007 b.n 8003968 } else { /* FIFO 1 assignation for the filter */ SET_BIT(can_ip->FFA1R, filternbrbitpos); 8003958: 697b ldr r3, [r7, #20] 800395a: f8d3 2214 ldr.w r2, [r3, #532] @ 0x214 800395e: 68fb ldr r3, [r7, #12] 8003960: 431a orrs r2, r3 8003962: 697b ldr r3, [r7, #20] 8003964: f8c3 2214 str.w r2, [r3, #532] @ 0x214 } /* Filter activation */ if (sFilterConfig->FilterActivation == CAN_FILTER_ENABLE) 8003968: 683b ldr r3, [r7, #0] 800396a: 6a1b ldr r3, [r3, #32] 800396c: 2b01 cmp r3, #1 800396e: d107 bne.n 8003980 { SET_BIT(can_ip->FA1R, filternbrbitpos); 8003970: 697b ldr r3, [r7, #20] 8003972: f8d3 221c ldr.w r2, [r3, #540] @ 0x21c 8003976: 68fb ldr r3, [r7, #12] 8003978: 431a orrs r2, r3 800397a: 697b ldr r3, [r7, #20] 800397c: f8c3 221c str.w r2, [r3, #540] @ 0x21c } /* Leave the initialisation mode for the filter */ CLEAR_BIT(can_ip->FMR, CAN_FMR_FINIT); 8003980: 697b ldr r3, [r7, #20] 8003982: f8d3 3200 ldr.w r3, [r3, #512] @ 0x200 8003986: f023 0201 bic.w r2, r3, #1 800398a: 697b ldr r3, [r7, #20] 800398c: f8c3 2200 str.w r2, [r3, #512] @ 0x200 /* Return function status */ return HAL_OK; 8003990: 2300 movs r3, #0 8003992: e006 b.n 80039a2 } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; 8003994: 687b ldr r3, [r7, #4] 8003996: 6a5b ldr r3, [r3, #36] @ 0x24 8003998: f443 2280 orr.w r2, r3, #262144 @ 0x40000 800399c: 687b ldr r3, [r7, #4] 800399e: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 80039a0: 2301 movs r3, #1 } } 80039a2: 4618 mov r0, r3 80039a4: 371c adds r7, #28 80039a6: 46bd mov sp, r7 80039a8: f85d 7b04 ldr.w r7, [sp], #4 80039ac: 4770 bx lr 080039ae : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan) { 80039ae: b580 push {r7, lr} 80039b0: b084 sub sp, #16 80039b2: af00 add r7, sp, #0 80039b4: 6078 str r0, [r7, #4] uint32_t tickstart; if (hcan->State == HAL_CAN_STATE_READY) 80039b6: 687b ldr r3, [r7, #4] 80039b8: f893 3020 ldrb.w r3, [r3, #32] 80039bc: b2db uxtb r3, r3 80039be: 2b01 cmp r3, #1 80039c0: d12e bne.n 8003a20 { /* Change CAN peripheral state */ hcan->State = HAL_CAN_STATE_LISTENING; 80039c2: 687b ldr r3, [r7, #4] 80039c4: 2202 movs r2, #2 80039c6: f883 2020 strb.w r2, [r3, #32] /* Request leave initialisation */ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); 80039ca: 687b ldr r3, [r7, #4] 80039cc: 681b ldr r3, [r3, #0] 80039ce: 681a ldr r2, [r3, #0] 80039d0: 687b ldr r3, [r7, #4] 80039d2: 681b ldr r3, [r3, #0] 80039d4: f022 0201 bic.w r2, r2, #1 80039d8: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 80039da: f7fe fc93 bl 8002304 80039de: 60f8 str r0, [r7, #12] /* Wait the acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U) 80039e0: e012 b.n 8003a08 { /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) 80039e2: f7fe fc8f bl 8002304 80039e6: 4602 mov r2, r0 80039e8: 68fb ldr r3, [r7, #12] 80039ea: 1ad3 subs r3, r2, r3 80039ec: 2b0a cmp r3, #10 80039ee: d90b bls.n 8003a08 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; 80039f0: 687b ldr r3, [r7, #4] 80039f2: 6a5b ldr r3, [r3, #36] @ 0x24 80039f4: f443 3200 orr.w r2, r3, #131072 @ 0x20000 80039f8: 687b ldr r3, [r7, #4] 80039fa: 625a str r2, [r3, #36] @ 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; 80039fc: 687b ldr r3, [r7, #4] 80039fe: 2205 movs r2, #5 8003a00: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 8003a04: 2301 movs r3, #1 8003a06: e012 b.n 8003a2e while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U) 8003a08: 687b ldr r3, [r7, #4] 8003a0a: 681b ldr r3, [r3, #0] 8003a0c: 685b ldr r3, [r3, #4] 8003a0e: f003 0301 and.w r3, r3, #1 8003a12: 2b00 cmp r3, #0 8003a14: d1e5 bne.n 80039e2 } } /* Reset the CAN ErrorCode */ hcan->ErrorCode = HAL_CAN_ERROR_NONE; 8003a16: 687b ldr r3, [r7, #4] 8003a18: 2200 movs r2, #0 8003a1a: 625a str r2, [r3, #36] @ 0x24 /* Return function status */ return HAL_OK; 8003a1c: 2300 movs r3, #0 8003a1e: e006 b.n 8003a2e } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_READY; 8003a20: 687b ldr r3, [r7, #4] 8003a22: 6a5b ldr r3, [r3, #36] @ 0x24 8003a24: f443 2200 orr.w r2, r3, #524288 @ 0x80000 8003a28: 687b ldr r3, [r7, #4] 8003a2a: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 8003a2c: 2301 movs r3, #1 } } 8003a2e: 4618 mov r0, r3 8003a30: 3710 adds r7, #16 8003a32: 46bd mov sp, r7 8003a34: bd80 pop {r7, pc} 08003a36 : * This parameter can be a value of @arg CAN_Tx_Mailboxes. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, const CAN_TxHeaderTypeDef *pHeader, const uint8_t aData[], uint32_t *pTxMailbox) { 8003a36: b480 push {r7} 8003a38: b089 sub sp, #36 @ 0x24 8003a3a: af00 add r7, sp, #0 8003a3c: 60f8 str r0, [r7, #12] 8003a3e: 60b9 str r1, [r7, #8] 8003a40: 607a str r2, [r7, #4] 8003a42: 603b str r3, [r7, #0] uint32_t transmitmailbox; HAL_CAN_StateTypeDef state = hcan->State; 8003a44: 68fb ldr r3, [r7, #12] 8003a46: f893 3020 ldrb.w r3, [r3, #32] 8003a4a: 77fb strb r3, [r7, #31] uint32_t tsr = READ_REG(hcan->Instance->TSR); 8003a4c: 68fb ldr r3, [r7, #12] 8003a4e: 681b ldr r3, [r3, #0] 8003a50: 689b ldr r3, [r3, #8] 8003a52: 61bb str r3, [r7, #24] { assert_param(IS_CAN_EXTID(pHeader->ExtId)); } assert_param(IS_FUNCTIONAL_STATE(pHeader->TransmitGlobalTime)); if ((state == HAL_CAN_STATE_READY) || 8003a54: 7ffb ldrb r3, [r7, #31] 8003a56: 2b01 cmp r3, #1 8003a58: d003 beq.n 8003a62 8003a5a: 7ffb ldrb r3, [r7, #31] 8003a5c: 2b02 cmp r3, #2 8003a5e: f040 80ad bne.w 8003bbc (state == HAL_CAN_STATE_LISTENING)) { /* Check that all the Tx mailboxes are not full */ if (((tsr & CAN_TSR_TME0) != 0U) || 8003a62: 69bb ldr r3, [r7, #24] 8003a64: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 8003a68: 2b00 cmp r3, #0 8003a6a: d10a bne.n 8003a82 ((tsr & CAN_TSR_TME1) != 0U) || 8003a6c: 69bb ldr r3, [r7, #24] 8003a6e: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 if (((tsr & CAN_TSR_TME0) != 0U) || 8003a72: 2b00 cmp r3, #0 8003a74: d105 bne.n 8003a82 ((tsr & CAN_TSR_TME2) != 0U)) 8003a76: 69bb ldr r3, [r7, #24] 8003a78: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 ((tsr & CAN_TSR_TME1) != 0U) || 8003a7c: 2b00 cmp r3, #0 8003a7e: f000 8095 beq.w 8003bac { /* Select an empty transmit mailbox */ transmitmailbox = (tsr & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos; 8003a82: 69bb ldr r3, [r7, #24] 8003a84: 0e1b lsrs r3, r3, #24 8003a86: f003 0303 and.w r3, r3, #3 8003a8a: 617b str r3, [r7, #20] /* Store the Tx mailbox */ *pTxMailbox = (uint32_t)1 << transmitmailbox; 8003a8c: 2201 movs r2, #1 8003a8e: 697b ldr r3, [r7, #20] 8003a90: 409a lsls r2, r3 8003a92: 683b ldr r3, [r7, #0] 8003a94: 601a str r2, [r3, #0] /* Set up the Id */ if (pHeader->IDE == CAN_ID_STD) 8003a96: 68bb ldr r3, [r7, #8] 8003a98: 689b ldr r3, [r3, #8] 8003a9a: 2b00 cmp r3, #0 8003a9c: d10d bne.n 8003aba { hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) | 8003a9e: 68bb ldr r3, [r7, #8] 8003aa0: 681b ldr r3, [r3, #0] 8003aa2: 055a lsls r2, r3, #21 pHeader->RTR); 8003aa4: 68bb ldr r3, [r7, #8] 8003aa6: 68db ldr r3, [r3, #12] hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) | 8003aa8: 68f9 ldr r1, [r7, #12] 8003aaa: 6809 ldr r1, [r1, #0] 8003aac: 431a orrs r2, r3 8003aae: 697b ldr r3, [r7, #20] 8003ab0: 3318 adds r3, #24 8003ab2: 011b lsls r3, r3, #4 8003ab4: 440b add r3, r1 8003ab6: 601a str r2, [r3, #0] 8003ab8: e00f b.n 8003ada } else { hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | 8003aba: 68bb ldr r3, [r7, #8] 8003abc: 685b ldr r3, [r3, #4] 8003abe: 00da lsls r2, r3, #3 pHeader->IDE | 8003ac0: 68bb ldr r3, [r7, #8] 8003ac2: 689b ldr r3, [r3, #8] hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | 8003ac4: 431a orrs r2, r3 pHeader->RTR); 8003ac6: 68bb ldr r3, [r7, #8] 8003ac8: 68db ldr r3, [r3, #12] hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | 8003aca: 68f9 ldr r1, [r7, #12] 8003acc: 6809 ldr r1, [r1, #0] pHeader->IDE | 8003ace: 431a orrs r2, r3 hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | 8003ad0: 697b ldr r3, [r7, #20] 8003ad2: 3318 adds r3, #24 8003ad4: 011b lsls r3, r3, #4 8003ad6: 440b add r3, r1 8003ad8: 601a str r2, [r3, #0] } /* Set up the DLC */ hcan->Instance->sTxMailBox[transmitmailbox].TDTR = (pHeader->DLC); 8003ada: 68fb ldr r3, [r7, #12] 8003adc: 6819 ldr r1, [r3, #0] 8003ade: 68bb ldr r3, [r7, #8] 8003ae0: 691a ldr r2, [r3, #16] 8003ae2: 697b ldr r3, [r7, #20] 8003ae4: 3318 adds r3, #24 8003ae6: 011b lsls r3, r3, #4 8003ae8: 440b add r3, r1 8003aea: 3304 adds r3, #4 8003aec: 601a str r2, [r3, #0] /* Set up the Transmit Global Time mode */ if (pHeader->TransmitGlobalTime == ENABLE) 8003aee: 68bb ldr r3, [r7, #8] 8003af0: 7d1b ldrb r3, [r3, #20] 8003af2: 2b01 cmp r3, #1 8003af4: d111 bne.n 8003b1a { SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TDTR, CAN_TDT0R_TGT); 8003af6: 68fb ldr r3, [r7, #12] 8003af8: 681a ldr r2, [r3, #0] 8003afa: 697b ldr r3, [r7, #20] 8003afc: 3318 adds r3, #24 8003afe: 011b lsls r3, r3, #4 8003b00: 4413 add r3, r2 8003b02: 3304 adds r3, #4 8003b04: 681b ldr r3, [r3, #0] 8003b06: 68fa ldr r2, [r7, #12] 8003b08: 6811 ldr r1, [r2, #0] 8003b0a: f443 7280 orr.w r2, r3, #256 @ 0x100 8003b0e: 697b ldr r3, [r7, #20] 8003b10: 3318 adds r3, #24 8003b12: 011b lsls r3, r3, #4 8003b14: 440b add r3, r1 8003b16: 3304 adds r3, #4 8003b18: 601a str r2, [r3, #0] } /* Set up the data field */ WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, 8003b1a: 687b ldr r3, [r7, #4] 8003b1c: 3307 adds r3, #7 8003b1e: 781b ldrb r3, [r3, #0] 8003b20: 061a lsls r2, r3, #24 8003b22: 687b ldr r3, [r7, #4] 8003b24: 3306 adds r3, #6 8003b26: 781b ldrb r3, [r3, #0] 8003b28: 041b lsls r3, r3, #16 8003b2a: 431a orrs r2, r3 8003b2c: 687b ldr r3, [r7, #4] 8003b2e: 3305 adds r3, #5 8003b30: 781b ldrb r3, [r3, #0] 8003b32: 021b lsls r3, r3, #8 8003b34: 4313 orrs r3, r2 8003b36: 687a ldr r2, [r7, #4] 8003b38: 3204 adds r2, #4 8003b3a: 7812 ldrb r2, [r2, #0] 8003b3c: 4610 mov r0, r2 8003b3e: 68fa ldr r2, [r7, #12] 8003b40: 6811 ldr r1, [r2, #0] 8003b42: ea43 0200 orr.w r2, r3, r0 8003b46: 697b ldr r3, [r7, #20] 8003b48: 011b lsls r3, r3, #4 8003b4a: 440b add r3, r1 8003b4c: f503 73c6 add.w r3, r3, #396 @ 0x18c 8003b50: 601a str r2, [r3, #0] ((uint32_t)aData[7] << CAN_TDH0R_DATA7_Pos) | ((uint32_t)aData[6] << CAN_TDH0R_DATA6_Pos) | ((uint32_t)aData[5] << CAN_TDH0R_DATA5_Pos) | ((uint32_t)aData[4] << CAN_TDH0R_DATA4_Pos)); WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, 8003b52: 687b ldr r3, [r7, #4] 8003b54: 3303 adds r3, #3 8003b56: 781b ldrb r3, [r3, #0] 8003b58: 061a lsls r2, r3, #24 8003b5a: 687b ldr r3, [r7, #4] 8003b5c: 3302 adds r3, #2 8003b5e: 781b ldrb r3, [r3, #0] 8003b60: 041b lsls r3, r3, #16 8003b62: 431a orrs r2, r3 8003b64: 687b ldr r3, [r7, #4] 8003b66: 3301 adds r3, #1 8003b68: 781b ldrb r3, [r3, #0] 8003b6a: 021b lsls r3, r3, #8 8003b6c: 4313 orrs r3, r2 8003b6e: 687a ldr r2, [r7, #4] 8003b70: 7812 ldrb r2, [r2, #0] 8003b72: 4610 mov r0, r2 8003b74: 68fa ldr r2, [r7, #12] 8003b76: 6811 ldr r1, [r2, #0] 8003b78: ea43 0200 orr.w r2, r3, r0 8003b7c: 697b ldr r3, [r7, #20] 8003b7e: 011b lsls r3, r3, #4 8003b80: 440b add r3, r1 8003b82: f503 73c4 add.w r3, r3, #392 @ 0x188 8003b86: 601a str r2, [r3, #0] ((uint32_t)aData[2] << CAN_TDL0R_DATA2_Pos) | ((uint32_t)aData[1] << CAN_TDL0R_DATA1_Pos) | ((uint32_t)aData[0] << CAN_TDL0R_DATA0_Pos)); /* Request transmission */ SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ); 8003b88: 68fb ldr r3, [r7, #12] 8003b8a: 681a ldr r2, [r3, #0] 8003b8c: 697b ldr r3, [r7, #20] 8003b8e: 3318 adds r3, #24 8003b90: 011b lsls r3, r3, #4 8003b92: 4413 add r3, r2 8003b94: 681b ldr r3, [r3, #0] 8003b96: 68fa ldr r2, [r7, #12] 8003b98: 6811 ldr r1, [r2, #0] 8003b9a: f043 0201 orr.w r2, r3, #1 8003b9e: 697b ldr r3, [r7, #20] 8003ba0: 3318 adds r3, #24 8003ba2: 011b lsls r3, r3, #4 8003ba4: 440b add r3, r1 8003ba6: 601a str r2, [r3, #0] /* Return function status */ return HAL_OK; 8003ba8: 2300 movs r3, #0 8003baa: e00e b.n 8003bca } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; 8003bac: 68fb ldr r3, [r7, #12] 8003bae: 6a5b ldr r3, [r3, #36] @ 0x24 8003bb0: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 8003bb4: 68fb ldr r3, [r7, #12] 8003bb6: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 8003bb8: 2301 movs r3, #1 8003bba: e006 b.n 8003bca } } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; 8003bbc: 68fb ldr r3, [r7, #12] 8003bbe: 6a5b ldr r3, [r3, #36] @ 0x24 8003bc0: f443 2280 orr.w r2, r3, #262144 @ 0x40000 8003bc4: 68fb ldr r3, [r7, #12] 8003bc6: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 8003bc8: 2301 movs r3, #1 } } 8003bca: 4618 mov r0, r3 8003bcc: 3724 adds r7, #36 @ 0x24 8003bce: 46bd mov sp, r7 8003bd0: f85d 7b04 ldr.w r7, [sp], #4 8003bd4: 4770 bx lr 08003bd6 : * @param aData array where the payload of the Rx frame will be stored. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]) { 8003bd6: b480 push {r7} 8003bd8: b087 sub sp, #28 8003bda: af00 add r7, sp, #0 8003bdc: 60f8 str r0, [r7, #12] 8003bde: 60b9 str r1, [r7, #8] 8003be0: 607a str r2, [r7, #4] 8003be2: 603b str r3, [r7, #0] HAL_CAN_StateTypeDef state = hcan->State; 8003be4: 68fb ldr r3, [r7, #12] 8003be6: f893 3020 ldrb.w r3, [r3, #32] 8003bea: 75fb strb r3, [r7, #23] assert_param(IS_CAN_RX_FIFO(RxFifo)); if ((state == HAL_CAN_STATE_READY) || 8003bec: 7dfb ldrb r3, [r7, #23] 8003bee: 2b01 cmp r3, #1 8003bf0: d003 beq.n 8003bfa 8003bf2: 7dfb ldrb r3, [r7, #23] 8003bf4: 2b02 cmp r3, #2 8003bf6: f040 8103 bne.w 8003e00 (state == HAL_CAN_STATE_LISTENING)) { /* Check the Rx FIFO */ if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ 8003bfa: 68bb ldr r3, [r7, #8] 8003bfc: 2b00 cmp r3, #0 8003bfe: d10e bne.n 8003c1e { /* Check that the Rx FIFO 0 is not empty */ if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == 0U) 8003c00: 68fb ldr r3, [r7, #12] 8003c02: 681b ldr r3, [r3, #0] 8003c04: 68db ldr r3, [r3, #12] 8003c06: f003 0303 and.w r3, r3, #3 8003c0a: 2b00 cmp r3, #0 8003c0c: d116 bne.n 8003c3c { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; 8003c0e: 68fb ldr r3, [r7, #12] 8003c10: 6a5b ldr r3, [r3, #36] @ 0x24 8003c12: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 8003c16: 68fb ldr r3, [r7, #12] 8003c18: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 8003c1a: 2301 movs r3, #1 8003c1c: e0f7 b.n 8003e0e } } else /* Rx element is assigned to Rx FIFO 1 */ { /* Check that the Rx FIFO 1 is not empty */ if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == 0U) 8003c1e: 68fb ldr r3, [r7, #12] 8003c20: 681b ldr r3, [r3, #0] 8003c22: 691b ldr r3, [r3, #16] 8003c24: f003 0303 and.w r3, r3, #3 8003c28: 2b00 cmp r3, #0 8003c2a: d107 bne.n 8003c3c { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; 8003c2c: 68fb ldr r3, [r7, #12] 8003c2e: 6a5b ldr r3, [r3, #36] @ 0x24 8003c30: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 8003c34: 68fb ldr r3, [r7, #12] 8003c36: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 8003c38: 2301 movs r3, #1 8003c3a: e0e8 b.n 8003e0e } } /* Get the header */ pHeader->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[RxFifo].RIR; 8003c3c: 68fb ldr r3, [r7, #12] 8003c3e: 681a ldr r2, [r3, #0] 8003c40: 68bb ldr r3, [r7, #8] 8003c42: 331b adds r3, #27 8003c44: 011b lsls r3, r3, #4 8003c46: 4413 add r3, r2 8003c48: 681b ldr r3, [r3, #0] 8003c4a: f003 0204 and.w r2, r3, #4 8003c4e: 687b ldr r3, [r7, #4] 8003c50: 609a str r2, [r3, #8] if (pHeader->IDE == CAN_ID_STD) 8003c52: 687b ldr r3, [r7, #4] 8003c54: 689b ldr r3, [r3, #8] 8003c56: 2b00 cmp r3, #0 8003c58: d10c bne.n 8003c74 { pHeader->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_TI0R_STID_Pos; 8003c5a: 68fb ldr r3, [r7, #12] 8003c5c: 681a ldr r2, [r3, #0] 8003c5e: 68bb ldr r3, [r7, #8] 8003c60: 331b adds r3, #27 8003c62: 011b lsls r3, r3, #4 8003c64: 4413 add r3, r2 8003c66: 681b ldr r3, [r3, #0] 8003c68: 0d5b lsrs r3, r3, #21 8003c6a: f3c3 020a ubfx r2, r3, #0, #11 8003c6e: 687b ldr r3, [r7, #4] 8003c70: 601a str r2, [r3, #0] 8003c72: e00b b.n 8003c8c } else { pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos; 8003c74: 68fb ldr r3, [r7, #12] 8003c76: 681a ldr r2, [r3, #0] 8003c78: 68bb ldr r3, [r7, #8] 8003c7a: 331b adds r3, #27 8003c7c: 011b lsls r3, r3, #4 8003c7e: 4413 add r3, r2 8003c80: 681b ldr r3, [r3, #0] 8003c82: 08db lsrs r3, r3, #3 8003c84: f023 4260 bic.w r2, r3, #3758096384 @ 0xe0000000 pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & 8003c88: 687b ldr r3, [r7, #4] 8003c8a: 605a str r2, [r3, #4] } pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR); 8003c8c: 68fb ldr r3, [r7, #12] 8003c8e: 681a ldr r2, [r3, #0] 8003c90: 68bb ldr r3, [r7, #8] 8003c92: 331b adds r3, #27 8003c94: 011b lsls r3, r3, #4 8003c96: 4413 add r3, r2 8003c98: 681b ldr r3, [r3, #0] 8003c9a: f003 0202 and.w r2, r3, #2 8003c9e: 687b ldr r3, [r7, #4] 8003ca0: 60da str r2, [r3, #12] if (((CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos) >= 8U) 8003ca2: 68fb ldr r3, [r7, #12] 8003ca4: 681a ldr r2, [r3, #0] 8003ca6: 68bb ldr r3, [r7, #8] 8003ca8: 331b adds r3, #27 8003caa: 011b lsls r3, r3, #4 8003cac: 4413 add r3, r2 8003cae: 3304 adds r3, #4 8003cb0: 681b ldr r3, [r3, #0] 8003cb2: f003 0308 and.w r3, r3, #8 8003cb6: 2b00 cmp r3, #0 8003cb8: d003 beq.n 8003cc2 { /* Truncate DLC to 8 if received field is over range */ pHeader->DLC = 8U; 8003cba: 687b ldr r3, [r7, #4] 8003cbc: 2208 movs r2, #8 8003cbe: 611a str r2, [r3, #16] 8003cc0: e00b b.n 8003cda } else { pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos; 8003cc2: 68fb ldr r3, [r7, #12] 8003cc4: 681a ldr r2, [r3, #0] 8003cc6: 68bb ldr r3, [r7, #8] 8003cc8: 331b adds r3, #27 8003cca: 011b lsls r3, r3, #4 8003ccc: 4413 add r3, r2 8003cce: 3304 adds r3, #4 8003cd0: 681b ldr r3, [r3, #0] 8003cd2: f003 020f and.w r2, r3, #15 8003cd6: 687b ldr r3, [r7, #4] 8003cd8: 611a str r2, [r3, #16] } pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos; 8003cda: 68fb ldr r3, [r7, #12] 8003cdc: 681a ldr r2, [r3, #0] 8003cde: 68bb ldr r3, [r7, #8] 8003ce0: 331b adds r3, #27 8003ce2: 011b lsls r3, r3, #4 8003ce4: 4413 add r3, r2 8003ce6: 3304 adds r3, #4 8003ce8: 681b ldr r3, [r3, #0] 8003cea: 0a1b lsrs r3, r3, #8 8003cec: b2da uxtb r2, r3 8003cee: 687b ldr r3, [r7, #4] 8003cf0: 619a str r2, [r3, #24] pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos; 8003cf2: 68fb ldr r3, [r7, #12] 8003cf4: 681a ldr r2, [r3, #0] 8003cf6: 68bb ldr r3, [r7, #8] 8003cf8: 331b adds r3, #27 8003cfa: 011b lsls r3, r3, #4 8003cfc: 4413 add r3, r2 8003cfe: 3304 adds r3, #4 8003d00: 681b ldr r3, [r3, #0] 8003d02: 0c1b lsrs r3, r3, #16 8003d04: b29a uxth r2, r3 8003d06: 687b ldr r3, [r7, #4] 8003d08: 615a str r2, [r3, #20] /* Get the data */ aData[0] = (uint8_t)((CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos); 8003d0a: 68fb ldr r3, [r7, #12] 8003d0c: 681a ldr r2, [r3, #0] 8003d0e: 68bb ldr r3, [r7, #8] 8003d10: 011b lsls r3, r3, #4 8003d12: 4413 add r3, r2 8003d14: f503 73dc add.w r3, r3, #440 @ 0x1b8 8003d18: 681b ldr r3, [r3, #0] 8003d1a: b2da uxtb r2, r3 8003d1c: 683b ldr r3, [r7, #0] 8003d1e: 701a strb r2, [r3, #0] aData[1] = (uint8_t)((CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos); 8003d20: 68fb ldr r3, [r7, #12] 8003d22: 681a ldr r2, [r3, #0] 8003d24: 68bb ldr r3, [r7, #8] 8003d26: 011b lsls r3, r3, #4 8003d28: 4413 add r3, r2 8003d2a: f503 73dc add.w r3, r3, #440 @ 0x1b8 8003d2e: 681b ldr r3, [r3, #0] 8003d30: 0a1a lsrs r2, r3, #8 8003d32: 683b ldr r3, [r7, #0] 8003d34: 3301 adds r3, #1 8003d36: b2d2 uxtb r2, r2 8003d38: 701a strb r2, [r3, #0] aData[2] = (uint8_t)((CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos); 8003d3a: 68fb ldr r3, [r7, #12] 8003d3c: 681a ldr r2, [r3, #0] 8003d3e: 68bb ldr r3, [r7, #8] 8003d40: 011b lsls r3, r3, #4 8003d42: 4413 add r3, r2 8003d44: f503 73dc add.w r3, r3, #440 @ 0x1b8 8003d48: 681b ldr r3, [r3, #0] 8003d4a: 0c1a lsrs r2, r3, #16 8003d4c: 683b ldr r3, [r7, #0] 8003d4e: 3302 adds r3, #2 8003d50: b2d2 uxtb r2, r2 8003d52: 701a strb r2, [r3, #0] aData[3] = (uint8_t)((CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos); 8003d54: 68fb ldr r3, [r7, #12] 8003d56: 681a ldr r2, [r3, #0] 8003d58: 68bb ldr r3, [r7, #8] 8003d5a: 011b lsls r3, r3, #4 8003d5c: 4413 add r3, r2 8003d5e: f503 73dc add.w r3, r3, #440 @ 0x1b8 8003d62: 681b ldr r3, [r3, #0] 8003d64: 0e1a lsrs r2, r3, #24 8003d66: 683b ldr r3, [r7, #0] 8003d68: 3303 adds r3, #3 8003d6a: b2d2 uxtb r2, r2 8003d6c: 701a strb r2, [r3, #0] aData[4] = (uint8_t)((CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos); 8003d6e: 68fb ldr r3, [r7, #12] 8003d70: 681a ldr r2, [r3, #0] 8003d72: 68bb ldr r3, [r7, #8] 8003d74: 011b lsls r3, r3, #4 8003d76: 4413 add r3, r2 8003d78: f503 73de add.w r3, r3, #444 @ 0x1bc 8003d7c: 681a ldr r2, [r3, #0] 8003d7e: 683b ldr r3, [r7, #0] 8003d80: 3304 adds r3, #4 8003d82: b2d2 uxtb r2, r2 8003d84: 701a strb r2, [r3, #0] aData[5] = (uint8_t)((CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos); 8003d86: 68fb ldr r3, [r7, #12] 8003d88: 681a ldr r2, [r3, #0] 8003d8a: 68bb ldr r3, [r7, #8] 8003d8c: 011b lsls r3, r3, #4 8003d8e: 4413 add r3, r2 8003d90: f503 73de add.w r3, r3, #444 @ 0x1bc 8003d94: 681b ldr r3, [r3, #0] 8003d96: 0a1a lsrs r2, r3, #8 8003d98: 683b ldr r3, [r7, #0] 8003d9a: 3305 adds r3, #5 8003d9c: b2d2 uxtb r2, r2 8003d9e: 701a strb r2, [r3, #0] aData[6] = (uint8_t)((CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos); 8003da0: 68fb ldr r3, [r7, #12] 8003da2: 681a ldr r2, [r3, #0] 8003da4: 68bb ldr r3, [r7, #8] 8003da6: 011b lsls r3, r3, #4 8003da8: 4413 add r3, r2 8003daa: f503 73de add.w r3, r3, #444 @ 0x1bc 8003dae: 681b ldr r3, [r3, #0] 8003db0: 0c1a lsrs r2, r3, #16 8003db2: 683b ldr r3, [r7, #0] 8003db4: 3306 adds r3, #6 8003db6: b2d2 uxtb r2, r2 8003db8: 701a strb r2, [r3, #0] aData[7] = (uint8_t)((CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos); 8003dba: 68fb ldr r3, [r7, #12] 8003dbc: 681a ldr r2, [r3, #0] 8003dbe: 68bb ldr r3, [r7, #8] 8003dc0: 011b lsls r3, r3, #4 8003dc2: 4413 add r3, r2 8003dc4: f503 73de add.w r3, r3, #444 @ 0x1bc 8003dc8: 681b ldr r3, [r3, #0] 8003dca: 0e1a lsrs r2, r3, #24 8003dcc: 683b ldr r3, [r7, #0] 8003dce: 3307 adds r3, #7 8003dd0: b2d2 uxtb r2, r2 8003dd2: 701a strb r2, [r3, #0] /* Release the FIFO */ if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ 8003dd4: 68bb ldr r3, [r7, #8] 8003dd6: 2b00 cmp r3, #0 8003dd8: d108 bne.n 8003dec { /* Release RX FIFO 0 */ SET_BIT(hcan->Instance->RF0R, CAN_RF0R_RFOM0); 8003dda: 68fb ldr r3, [r7, #12] 8003ddc: 681b ldr r3, [r3, #0] 8003dde: 68da ldr r2, [r3, #12] 8003de0: 68fb ldr r3, [r7, #12] 8003de2: 681b ldr r3, [r3, #0] 8003de4: f042 0220 orr.w r2, r2, #32 8003de8: 60da str r2, [r3, #12] 8003dea: e007 b.n 8003dfc } else /* Rx element is assigned to Rx FIFO 1 */ { /* Release RX FIFO 1 */ SET_BIT(hcan->Instance->RF1R, CAN_RF1R_RFOM1); 8003dec: 68fb ldr r3, [r7, #12] 8003dee: 681b ldr r3, [r3, #0] 8003df0: 691a ldr r2, [r3, #16] 8003df2: 68fb ldr r3, [r7, #12] 8003df4: 681b ldr r3, [r3, #0] 8003df6: f042 0220 orr.w r2, r2, #32 8003dfa: 611a str r2, [r3, #16] } /* Return function status */ return HAL_OK; 8003dfc: 2300 movs r3, #0 8003dfe: e006 b.n 8003e0e } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; 8003e00: 68fb ldr r3, [r7, #12] 8003e02: 6a5b ldr r3, [r3, #36] @ 0x24 8003e04: f443 2280 orr.w r2, r3, #262144 @ 0x40000 8003e08: 68fb ldr r3, [r7, #12] 8003e0a: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 8003e0c: 2301 movs r3, #1 } } 8003e0e: 4618 mov r0, r3 8003e10: 371c adds r7, #28 8003e12: 46bd mov sp, r7 8003e14: f85d 7b04 ldr.w r7, [sp], #4 8003e18: 4770 bx lr 08003e1a : * @param ActiveITs indicates which interrupts will be enabled. * This parameter can be any combination of @arg CAN_Interrupts. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs) { 8003e1a: b480 push {r7} 8003e1c: b085 sub sp, #20 8003e1e: af00 add r7, sp, #0 8003e20: 6078 str r0, [r7, #4] 8003e22: 6039 str r1, [r7, #0] HAL_CAN_StateTypeDef state = hcan->State; 8003e24: 687b ldr r3, [r7, #4] 8003e26: f893 3020 ldrb.w r3, [r3, #32] 8003e2a: 73fb strb r3, [r7, #15] /* Check function parameters */ assert_param(IS_CAN_IT(ActiveITs)); if ((state == HAL_CAN_STATE_READY) || 8003e2c: 7bfb ldrb r3, [r7, #15] 8003e2e: 2b01 cmp r3, #1 8003e30: d002 beq.n 8003e38 8003e32: 7bfb ldrb r3, [r7, #15] 8003e34: 2b02 cmp r3, #2 8003e36: d109 bne.n 8003e4c (state == HAL_CAN_STATE_LISTENING)) { /* Enable the selected interrupts */ __HAL_CAN_ENABLE_IT(hcan, ActiveITs); 8003e38: 687b ldr r3, [r7, #4] 8003e3a: 681b ldr r3, [r3, #0] 8003e3c: 6959 ldr r1, [r3, #20] 8003e3e: 687b ldr r3, [r7, #4] 8003e40: 681b ldr r3, [r3, #0] 8003e42: 683a ldr r2, [r7, #0] 8003e44: 430a orrs r2, r1 8003e46: 615a str r2, [r3, #20] /* Return function status */ return HAL_OK; 8003e48: 2300 movs r3, #0 8003e4a: e006 b.n 8003e5a } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; 8003e4c: 687b ldr r3, [r7, #4] 8003e4e: 6a5b ldr r3, [r3, #36] @ 0x24 8003e50: f443 2280 orr.w r2, r3, #262144 @ 0x40000 8003e54: 687b ldr r3, [r7, #4] 8003e56: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 8003e58: 2301 movs r3, #1 } } 8003e5a: 4618 mov r0, r3 8003e5c: 3714 adds r7, #20 8003e5e: 46bd mov sp, r7 8003e60: f85d 7b04 ldr.w r7, [sp], #4 8003e64: 4770 bx lr 08003e66 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan) { 8003e66: b580 push {r7, lr} 8003e68: b08a sub sp, #40 @ 0x28 8003e6a: af00 add r7, sp, #0 8003e6c: 6078 str r0, [r7, #4] uint32_t errorcode = HAL_CAN_ERROR_NONE; 8003e6e: 2300 movs r3, #0 8003e70: 627b str r3, [r7, #36] @ 0x24 uint32_t interrupts = READ_REG(hcan->Instance->IER); 8003e72: 687b ldr r3, [r7, #4] 8003e74: 681b ldr r3, [r3, #0] 8003e76: 695b ldr r3, [r3, #20] 8003e78: 623b str r3, [r7, #32] uint32_t msrflags = READ_REG(hcan->Instance->MSR); 8003e7a: 687b ldr r3, [r7, #4] 8003e7c: 681b ldr r3, [r3, #0] 8003e7e: 685b ldr r3, [r3, #4] 8003e80: 61fb str r3, [r7, #28] uint32_t tsrflags = READ_REG(hcan->Instance->TSR); 8003e82: 687b ldr r3, [r7, #4] 8003e84: 681b ldr r3, [r3, #0] 8003e86: 689b ldr r3, [r3, #8] 8003e88: 61bb str r3, [r7, #24] uint32_t rf0rflags = READ_REG(hcan->Instance->RF0R); 8003e8a: 687b ldr r3, [r7, #4] 8003e8c: 681b ldr r3, [r3, #0] 8003e8e: 68db ldr r3, [r3, #12] 8003e90: 617b str r3, [r7, #20] uint32_t rf1rflags = READ_REG(hcan->Instance->RF1R); 8003e92: 687b ldr r3, [r7, #4] 8003e94: 681b ldr r3, [r3, #0] 8003e96: 691b ldr r3, [r3, #16] 8003e98: 613b str r3, [r7, #16] uint32_t esrflags = READ_REG(hcan->Instance->ESR); 8003e9a: 687b ldr r3, [r7, #4] 8003e9c: 681b ldr r3, [r3, #0] 8003e9e: 699b ldr r3, [r3, #24] 8003ea0: 60fb str r3, [r7, #12] /* Transmit Mailbox empty interrupt management *****************************/ if ((interrupts & CAN_IT_TX_MAILBOX_EMPTY) != 0U) 8003ea2: 6a3b ldr r3, [r7, #32] 8003ea4: f003 0301 and.w r3, r3, #1 8003ea8: 2b00 cmp r3, #0 8003eaa: d07c beq.n 8003fa6 { /* Transmit Mailbox 0 management *****************************************/ if ((tsrflags & CAN_TSR_RQCP0) != 0U) 8003eac: 69bb ldr r3, [r7, #24] 8003eae: f003 0301 and.w r3, r3, #1 8003eb2: 2b00 cmp r3, #0 8003eb4: d023 beq.n 8003efe { /* Clear the Transmission Complete flag (and TXOK0,ALST0,TERR0 bits) */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP0); 8003eb6: 687b ldr r3, [r7, #4] 8003eb8: 681b ldr r3, [r3, #0] 8003eba: 2201 movs r2, #1 8003ebc: 609a str r2, [r3, #8] if ((tsrflags & CAN_TSR_TXOK0) != 0U) 8003ebe: 69bb ldr r3, [r7, #24] 8003ec0: f003 0302 and.w r3, r3, #2 8003ec4: 2b00 cmp r3, #0 8003ec6: d003 beq.n 8003ed0 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox0CompleteCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox0CompleteCallback(hcan); 8003ec8: 6878 ldr r0, [r7, #4] 8003eca: f000 f983 bl 80041d4 8003ece: e016 b.n 8003efe #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } else { if ((tsrflags & CAN_TSR_ALST0) != 0U) 8003ed0: 69bb ldr r3, [r7, #24] 8003ed2: f003 0304 and.w r3, r3, #4 8003ed6: 2b00 cmp r3, #0 8003ed8: d004 beq.n 8003ee4 { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_ALST0; 8003eda: 6a7b ldr r3, [r7, #36] @ 0x24 8003edc: f443 6300 orr.w r3, r3, #2048 @ 0x800 8003ee0: 627b str r3, [r7, #36] @ 0x24 8003ee2: e00c b.n 8003efe } else if ((tsrflags & CAN_TSR_TERR0) != 0U) 8003ee4: 69bb ldr r3, [r7, #24] 8003ee6: f003 0308 and.w r3, r3, #8 8003eea: 2b00 cmp r3, #0 8003eec: d004 beq.n 8003ef8 { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_TERR0; 8003eee: 6a7b ldr r3, [r7, #36] @ 0x24 8003ef0: f443 5380 orr.w r3, r3, #4096 @ 0x1000 8003ef4: 627b str r3, [r7, #36] @ 0x24 8003ef6: e002 b.n 8003efe #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox0AbortCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox0AbortCallback(hcan); 8003ef8: 6878 ldr r0, [r7, #4] 8003efa: f000 f989 bl 8004210 } } } /* Transmit Mailbox 1 management *****************************************/ if ((tsrflags & CAN_TSR_RQCP1) != 0U) 8003efe: 69bb ldr r3, [r7, #24] 8003f00: f403 7380 and.w r3, r3, #256 @ 0x100 8003f04: 2b00 cmp r3, #0 8003f06: d024 beq.n 8003f52 { /* Clear the Transmission Complete flag (and TXOK1,ALST1,TERR1 bits) */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP1); 8003f08: 687b ldr r3, [r7, #4] 8003f0a: 681b ldr r3, [r3, #0] 8003f0c: f44f 7280 mov.w r2, #256 @ 0x100 8003f10: 609a str r2, [r3, #8] if ((tsrflags & CAN_TSR_TXOK1) != 0U) 8003f12: 69bb ldr r3, [r7, #24] 8003f14: f403 7300 and.w r3, r3, #512 @ 0x200 8003f18: 2b00 cmp r3, #0 8003f1a: d003 beq.n 8003f24 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox1CompleteCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox1CompleteCallback(hcan); 8003f1c: 6878 ldr r0, [r7, #4] 8003f1e: f000 f963 bl 80041e8 8003f22: e016 b.n 8003f52 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } else { if ((tsrflags & CAN_TSR_ALST1) != 0U) 8003f24: 69bb ldr r3, [r7, #24] 8003f26: f403 6380 and.w r3, r3, #1024 @ 0x400 8003f2a: 2b00 cmp r3, #0 8003f2c: d004 beq.n 8003f38 { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_ALST1; 8003f2e: 6a7b ldr r3, [r7, #36] @ 0x24 8003f30: f443 5300 orr.w r3, r3, #8192 @ 0x2000 8003f34: 627b str r3, [r7, #36] @ 0x24 8003f36: e00c b.n 8003f52 } else if ((tsrflags & CAN_TSR_TERR1) != 0U) 8003f38: 69bb ldr r3, [r7, #24] 8003f3a: f403 6300 and.w r3, r3, #2048 @ 0x800 8003f3e: 2b00 cmp r3, #0 8003f40: d004 beq.n 8003f4c { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_TERR1; 8003f42: 6a7b ldr r3, [r7, #36] @ 0x24 8003f44: f443 4380 orr.w r3, r3, #16384 @ 0x4000 8003f48: 627b str r3, [r7, #36] @ 0x24 8003f4a: e002 b.n 8003f52 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox1AbortCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox1AbortCallback(hcan); 8003f4c: 6878 ldr r0, [r7, #4] 8003f4e: f000 f969 bl 8004224 } } } /* Transmit Mailbox 2 management *****************************************/ if ((tsrflags & CAN_TSR_RQCP2) != 0U) 8003f52: 69bb ldr r3, [r7, #24] 8003f54: f403 3380 and.w r3, r3, #65536 @ 0x10000 8003f58: 2b00 cmp r3, #0 8003f5a: d024 beq.n 8003fa6 { /* Clear the Transmission Complete flag (and TXOK2,ALST2,TERR2 bits) */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP2); 8003f5c: 687b ldr r3, [r7, #4] 8003f5e: 681b ldr r3, [r3, #0] 8003f60: f44f 3280 mov.w r2, #65536 @ 0x10000 8003f64: 609a str r2, [r3, #8] if ((tsrflags & CAN_TSR_TXOK2) != 0U) 8003f66: 69bb ldr r3, [r7, #24] 8003f68: f403 3300 and.w r3, r3, #131072 @ 0x20000 8003f6c: 2b00 cmp r3, #0 8003f6e: d003 beq.n 8003f78 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox2CompleteCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox2CompleteCallback(hcan); 8003f70: 6878 ldr r0, [r7, #4] 8003f72: f000 f943 bl 80041fc 8003f76: e016 b.n 8003fa6 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } else { if ((tsrflags & CAN_TSR_ALST2) != 0U) 8003f78: 69bb ldr r3, [r7, #24] 8003f7a: f403 2380 and.w r3, r3, #262144 @ 0x40000 8003f7e: 2b00 cmp r3, #0 8003f80: d004 beq.n 8003f8c { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_ALST2; 8003f82: 6a7b ldr r3, [r7, #36] @ 0x24 8003f84: f443 4300 orr.w r3, r3, #32768 @ 0x8000 8003f88: 627b str r3, [r7, #36] @ 0x24 8003f8a: e00c b.n 8003fa6 } else if ((tsrflags & CAN_TSR_TERR2) != 0U) 8003f8c: 69bb ldr r3, [r7, #24] 8003f8e: f403 2300 and.w r3, r3, #524288 @ 0x80000 8003f92: 2b00 cmp r3, #0 8003f94: d004 beq.n 8003fa0 { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_TERR2; 8003f96: 6a7b ldr r3, [r7, #36] @ 0x24 8003f98: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8003f9c: 627b str r3, [r7, #36] @ 0x24 8003f9e: e002 b.n 8003fa6 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox2AbortCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox2AbortCallback(hcan); 8003fa0: 6878 ldr r0, [r7, #4] 8003fa2: f000 f949 bl 8004238 } } } /* Receive FIFO 0 overrun interrupt management *****************************/ if ((interrupts & CAN_IT_RX_FIFO0_OVERRUN) != 0U) 8003fa6: 6a3b ldr r3, [r7, #32] 8003fa8: f003 0308 and.w r3, r3, #8 8003fac: 2b00 cmp r3, #0 8003fae: d00c beq.n 8003fca { if ((rf0rflags & CAN_RF0R_FOVR0) != 0U) 8003fb0: 697b ldr r3, [r7, #20] 8003fb2: f003 0310 and.w r3, r3, #16 8003fb6: 2b00 cmp r3, #0 8003fb8: d007 beq.n 8003fca { /* Set CAN error code to Rx Fifo 0 overrun error */ errorcode |= HAL_CAN_ERROR_RX_FOV0; 8003fba: 6a7b ldr r3, [r7, #36] @ 0x24 8003fbc: f443 7300 orr.w r3, r3, #512 @ 0x200 8003fc0: 627b str r3, [r7, #36] @ 0x24 /* Clear FIFO0 Overrun Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0); 8003fc2: 687b ldr r3, [r7, #4] 8003fc4: 681b ldr r3, [r3, #0] 8003fc6: 2210 movs r2, #16 8003fc8: 60da str r2, [r3, #12] } } /* Receive FIFO 0 full interrupt management ********************************/ if ((interrupts & CAN_IT_RX_FIFO0_FULL) != 0U) 8003fca: 6a3b ldr r3, [r7, #32] 8003fcc: f003 0304 and.w r3, r3, #4 8003fd0: 2b00 cmp r3, #0 8003fd2: d00b beq.n 8003fec { if ((rf0rflags & CAN_RF0R_FULL0) != 0U) 8003fd4: 697b ldr r3, [r7, #20] 8003fd6: f003 0308 and.w r3, r3, #8 8003fda: 2b00 cmp r3, #0 8003fdc: d006 beq.n 8003fec { /* Clear FIFO 0 full Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0); 8003fde: 687b ldr r3, [r7, #4] 8003fe0: 681b ldr r3, [r3, #0] 8003fe2: 2208 movs r2, #8 8003fe4: 60da str r2, [r3, #12] #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo0FullCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo0FullCallback(hcan); 8003fe6: 6878 ldr r0, [r7, #4] 8003fe8: f000 f930 bl 800424c #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Receive FIFO 0 message pending interrupt management *********************/ if ((interrupts & CAN_IT_RX_FIFO0_MSG_PENDING) != 0U) 8003fec: 6a3b ldr r3, [r7, #32] 8003fee: f003 0302 and.w r3, r3, #2 8003ff2: 2b00 cmp r3, #0 8003ff4: d009 beq.n 800400a { /* Check if message is still pending */ if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != 0U) 8003ff6: 687b ldr r3, [r7, #4] 8003ff8: 681b ldr r3, [r3, #0] 8003ffa: 68db ldr r3, [r3, #12] 8003ffc: f003 0303 and.w r3, r3, #3 8004000: 2b00 cmp r3, #0 8004002: d002 beq.n 800400a #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo0MsgPendingCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo0MsgPendingCallback(hcan); 8004004: 6878 ldr r0, [r7, #4] 8004006: f7fc fddf bl 8000bc8 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Receive FIFO 1 overrun interrupt management *****************************/ if ((interrupts & CAN_IT_RX_FIFO1_OVERRUN) != 0U) 800400a: 6a3b ldr r3, [r7, #32] 800400c: f003 0340 and.w r3, r3, #64 @ 0x40 8004010: 2b00 cmp r3, #0 8004012: d00c beq.n 800402e { if ((rf1rflags & CAN_RF1R_FOVR1) != 0U) 8004014: 693b ldr r3, [r7, #16] 8004016: f003 0310 and.w r3, r3, #16 800401a: 2b00 cmp r3, #0 800401c: d007 beq.n 800402e { /* Set CAN error code to Rx Fifo 1 overrun error */ errorcode |= HAL_CAN_ERROR_RX_FOV1; 800401e: 6a7b ldr r3, [r7, #36] @ 0x24 8004020: f443 6380 orr.w r3, r3, #1024 @ 0x400 8004024: 627b str r3, [r7, #36] @ 0x24 /* Clear FIFO1 Overrun Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1); 8004026: 687b ldr r3, [r7, #4] 8004028: 681b ldr r3, [r3, #0] 800402a: 2210 movs r2, #16 800402c: 611a str r2, [r3, #16] } } /* Receive FIFO 1 full interrupt management ********************************/ if ((interrupts & CAN_IT_RX_FIFO1_FULL) != 0U) 800402e: 6a3b ldr r3, [r7, #32] 8004030: f003 0320 and.w r3, r3, #32 8004034: 2b00 cmp r3, #0 8004036: d00b beq.n 8004050 { if ((rf1rflags & CAN_RF1R_FULL1) != 0U) 8004038: 693b ldr r3, [r7, #16] 800403a: f003 0308 and.w r3, r3, #8 800403e: 2b00 cmp r3, #0 8004040: d006 beq.n 8004050 { /* Clear FIFO 1 full Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1); 8004042: 687b ldr r3, [r7, #4] 8004044: 681b ldr r3, [r3, #0] 8004046: 2208 movs r2, #8 8004048: 611a str r2, [r3, #16] #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo1FullCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo1FullCallback(hcan); 800404a: 6878 ldr r0, [r7, #4] 800404c: f000 f912 bl 8004274 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Receive FIFO 1 message pending interrupt management *********************/ if ((interrupts & CAN_IT_RX_FIFO1_MSG_PENDING) != 0U) 8004050: 6a3b ldr r3, [r7, #32] 8004052: f003 0310 and.w r3, r3, #16 8004056: 2b00 cmp r3, #0 8004058: d009 beq.n 800406e { /* Check if message is still pending */ if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != 0U) 800405a: 687b ldr r3, [r7, #4] 800405c: 681b ldr r3, [r3, #0] 800405e: 691b ldr r3, [r3, #16] 8004060: f003 0303 and.w r3, r3, #3 8004064: 2b00 cmp r3, #0 8004066: d002 beq.n 800406e #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo1MsgPendingCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo1MsgPendingCallback(hcan); 8004068: 6878 ldr r0, [r7, #4] 800406a: f000 f8f9 bl 8004260 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Sleep interrupt management *********************************************/ if ((interrupts & CAN_IT_SLEEP_ACK) != 0U) 800406e: 6a3b ldr r3, [r7, #32] 8004070: f403 3300 and.w r3, r3, #131072 @ 0x20000 8004074: 2b00 cmp r3, #0 8004076: d00b beq.n 8004090 { if ((msrflags & CAN_MSR_SLAKI) != 0U) 8004078: 69fb ldr r3, [r7, #28] 800407a: f003 0310 and.w r3, r3, #16 800407e: 2b00 cmp r3, #0 8004080: d006 beq.n 8004090 { /* Clear Sleep interrupt Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_SLAKI); 8004082: 687b ldr r3, [r7, #4] 8004084: 681b ldr r3, [r3, #0] 8004086: 2210 movs r2, #16 8004088: 605a str r2, [r3, #4] #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->SleepCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_SleepCallback(hcan); 800408a: 6878 ldr r0, [r7, #4] 800408c: f000 f8fc bl 8004288 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* WakeUp interrupt management *********************************************/ if ((interrupts & CAN_IT_WAKEUP) != 0U) 8004090: 6a3b ldr r3, [r7, #32] 8004092: f403 3380 and.w r3, r3, #65536 @ 0x10000 8004096: 2b00 cmp r3, #0 8004098: d00b beq.n 80040b2 { if ((msrflags & CAN_MSR_WKUI) != 0U) 800409a: 69fb ldr r3, [r7, #28] 800409c: f003 0308 and.w r3, r3, #8 80040a0: 2b00 cmp r3, #0 80040a2: d006 beq.n 80040b2 { /* Clear WakeUp Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_WKU); 80040a4: 687b ldr r3, [r7, #4] 80040a6: 681b ldr r3, [r3, #0] 80040a8: 2208 movs r2, #8 80040aa: 605a str r2, [r3, #4] #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->WakeUpFromRxMsgCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_WakeUpFromRxMsgCallback(hcan); 80040ac: 6878 ldr r0, [r7, #4] 80040ae: f000 f8f5 bl 800429c #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Error interrupts management *********************************************/ if ((interrupts & CAN_IT_ERROR) != 0U) 80040b2: 6a3b ldr r3, [r7, #32] 80040b4: f403 4300 and.w r3, r3, #32768 @ 0x8000 80040b8: 2b00 cmp r3, #0 80040ba: d07b beq.n 80041b4 { if ((msrflags & CAN_MSR_ERRI) != 0U) 80040bc: 69fb ldr r3, [r7, #28] 80040be: f003 0304 and.w r3, r3, #4 80040c2: 2b00 cmp r3, #0 80040c4: d072 beq.n 80041ac { /* Check Error Warning Flag */ if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) && 80040c6: 6a3b ldr r3, [r7, #32] 80040c8: f403 7380 and.w r3, r3, #256 @ 0x100 80040cc: 2b00 cmp r3, #0 80040ce: d008 beq.n 80040e2 ((esrflags & CAN_ESR_EWGF) != 0U)) 80040d0: 68fb ldr r3, [r7, #12] 80040d2: f003 0301 and.w r3, r3, #1 if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) && 80040d6: 2b00 cmp r3, #0 80040d8: d003 beq.n 80040e2 { /* Set CAN error code to Error Warning */ errorcode |= HAL_CAN_ERROR_EWG; 80040da: 6a7b ldr r3, [r7, #36] @ 0x24 80040dc: f043 0301 orr.w r3, r3, #1 80040e0: 627b str r3, [r7, #36] @ 0x24 /* No need for clear of Error Warning Flag as read-only */ } /* Check Error Passive Flag */ if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) && 80040e2: 6a3b ldr r3, [r7, #32] 80040e4: f403 7300 and.w r3, r3, #512 @ 0x200 80040e8: 2b00 cmp r3, #0 80040ea: d008 beq.n 80040fe ((esrflags & CAN_ESR_EPVF) != 0U)) 80040ec: 68fb ldr r3, [r7, #12] 80040ee: f003 0302 and.w r3, r3, #2 if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) && 80040f2: 2b00 cmp r3, #0 80040f4: d003 beq.n 80040fe { /* Set CAN error code to Error Passive */ errorcode |= HAL_CAN_ERROR_EPV; 80040f6: 6a7b ldr r3, [r7, #36] @ 0x24 80040f8: f043 0302 orr.w r3, r3, #2 80040fc: 627b str r3, [r7, #36] @ 0x24 /* No need for clear of Error Passive Flag as read-only */ } /* Check Bus-off Flag */ if (((interrupts & CAN_IT_BUSOFF) != 0U) && 80040fe: 6a3b ldr r3, [r7, #32] 8004100: f403 6380 and.w r3, r3, #1024 @ 0x400 8004104: 2b00 cmp r3, #0 8004106: d008 beq.n 800411a ((esrflags & CAN_ESR_BOFF) != 0U)) 8004108: 68fb ldr r3, [r7, #12] 800410a: f003 0304 and.w r3, r3, #4 if (((interrupts & CAN_IT_BUSOFF) != 0U) && 800410e: 2b00 cmp r3, #0 8004110: d003 beq.n 800411a { /* Set CAN error code to Bus-Off */ errorcode |= HAL_CAN_ERROR_BOF; 8004112: 6a7b ldr r3, [r7, #36] @ 0x24 8004114: f043 0304 orr.w r3, r3, #4 8004118: 627b str r3, [r7, #36] @ 0x24 /* No need for clear of Error Bus-Off as read-only */ } /* Check Last Error Code Flag */ if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) && 800411a: 6a3b ldr r3, [r7, #32] 800411c: f403 6300 and.w r3, r3, #2048 @ 0x800 8004120: 2b00 cmp r3, #0 8004122: d043 beq.n 80041ac ((esrflags & CAN_ESR_LEC) != 0U)) 8004124: 68fb ldr r3, [r7, #12] 8004126: f003 0370 and.w r3, r3, #112 @ 0x70 if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) && 800412a: 2b00 cmp r3, #0 800412c: d03e beq.n 80041ac { switch (esrflags & CAN_ESR_LEC) 800412e: 68fb ldr r3, [r7, #12] 8004130: f003 0370 and.w r3, r3, #112 @ 0x70 8004134: 2b60 cmp r3, #96 @ 0x60 8004136: d02b beq.n 8004190 8004138: 2b60 cmp r3, #96 @ 0x60 800413a: d82e bhi.n 800419a 800413c: 2b50 cmp r3, #80 @ 0x50 800413e: d022 beq.n 8004186 8004140: 2b50 cmp r3, #80 @ 0x50 8004142: d82a bhi.n 800419a 8004144: 2b40 cmp r3, #64 @ 0x40 8004146: d019 beq.n 800417c 8004148: 2b40 cmp r3, #64 @ 0x40 800414a: d826 bhi.n 800419a 800414c: 2b30 cmp r3, #48 @ 0x30 800414e: d010 beq.n 8004172 8004150: 2b30 cmp r3, #48 @ 0x30 8004152: d822 bhi.n 800419a 8004154: 2b10 cmp r3, #16 8004156: d002 beq.n 800415e 8004158: 2b20 cmp r3, #32 800415a: d005 beq.n 8004168 case (CAN_ESR_LEC_2 | CAN_ESR_LEC_1): /* Set CAN error code to CRC error */ errorcode |= HAL_CAN_ERROR_CRC; break; default: break; 800415c: e01d b.n 800419a errorcode |= HAL_CAN_ERROR_STF; 800415e: 6a7b ldr r3, [r7, #36] @ 0x24 8004160: f043 0308 orr.w r3, r3, #8 8004164: 627b str r3, [r7, #36] @ 0x24 break; 8004166: e019 b.n 800419c errorcode |= HAL_CAN_ERROR_FOR; 8004168: 6a7b ldr r3, [r7, #36] @ 0x24 800416a: f043 0310 orr.w r3, r3, #16 800416e: 627b str r3, [r7, #36] @ 0x24 break; 8004170: e014 b.n 800419c errorcode |= HAL_CAN_ERROR_ACK; 8004172: 6a7b ldr r3, [r7, #36] @ 0x24 8004174: f043 0320 orr.w r3, r3, #32 8004178: 627b str r3, [r7, #36] @ 0x24 break; 800417a: e00f b.n 800419c errorcode |= HAL_CAN_ERROR_BR; 800417c: 6a7b ldr r3, [r7, #36] @ 0x24 800417e: f043 0340 orr.w r3, r3, #64 @ 0x40 8004182: 627b str r3, [r7, #36] @ 0x24 break; 8004184: e00a b.n 800419c errorcode |= HAL_CAN_ERROR_BD; 8004186: 6a7b ldr r3, [r7, #36] @ 0x24 8004188: f043 0380 orr.w r3, r3, #128 @ 0x80 800418c: 627b str r3, [r7, #36] @ 0x24 break; 800418e: e005 b.n 800419c errorcode |= HAL_CAN_ERROR_CRC; 8004190: 6a7b ldr r3, [r7, #36] @ 0x24 8004192: f443 7380 orr.w r3, r3, #256 @ 0x100 8004196: 627b str r3, [r7, #36] @ 0x24 break; 8004198: e000 b.n 800419c break; 800419a: bf00 nop } /* Clear Last error code Flag */ CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC); 800419c: 687b ldr r3, [r7, #4] 800419e: 681b ldr r3, [r3, #0] 80041a0: 699a ldr r2, [r3, #24] 80041a2: 687b ldr r3, [r7, #4] 80041a4: 681b ldr r3, [r3, #0] 80041a6: f022 0270 bic.w r2, r2, #112 @ 0x70 80041aa: 619a str r2, [r3, #24] } } /* Clear ERRI Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_ERRI); 80041ac: 687b ldr r3, [r7, #4] 80041ae: 681b ldr r3, [r3, #0] 80041b0: 2204 movs r2, #4 80041b2: 605a str r2, [r3, #4] } /* Call the Error call Back in case of Errors */ if (errorcode != HAL_CAN_ERROR_NONE) 80041b4: 6a7b ldr r3, [r7, #36] @ 0x24 80041b6: 2b00 cmp r3, #0 80041b8: d008 beq.n 80041cc { /* Update error code in handle */ hcan->ErrorCode |= errorcode; 80041ba: 687b ldr r3, [r7, #4] 80041bc: 6a5a ldr r2, [r3, #36] @ 0x24 80041be: 6a7b ldr r3, [r7, #36] @ 0x24 80041c0: 431a orrs r2, r3 80041c2: 687b ldr r3, [r7, #4] 80041c4: 625a str r2, [r3, #36] @ 0x24 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->ErrorCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_ErrorCallback(hcan); 80041c6: 6878 ldr r0, [r7, #4] 80041c8: f000 f872 bl 80042b0 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } 80041cc: bf00 nop 80041ce: 3728 adds r7, #40 @ 0x28 80041d0: 46bd mov sp, r7 80041d2: bd80 pop {r7, pc} 080041d4 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan) { 80041d4: b480 push {r7} 80041d6: b083 sub sp, #12 80041d8: af00 add r7, sp, #0 80041da: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox0CompleteCallback could be implemented in the user file */ } 80041dc: bf00 nop 80041de: 370c adds r7, #12 80041e0: 46bd mov sp, r7 80041e2: f85d 7b04 ldr.w r7, [sp], #4 80041e6: 4770 bx lr 080041e8 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan) { 80041e8: b480 push {r7} 80041ea: b083 sub sp, #12 80041ec: af00 add r7, sp, #0 80041ee: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox1CompleteCallback could be implemented in the user file */ } 80041f0: bf00 nop 80041f2: 370c adds r7, #12 80041f4: 46bd mov sp, r7 80041f6: f85d 7b04 ldr.w r7, [sp], #4 80041fa: 4770 bx lr 080041fc : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan) { 80041fc: b480 push {r7} 80041fe: b083 sub sp, #12 8004200: af00 add r7, sp, #0 8004202: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox2CompleteCallback could be implemented in the user file */ } 8004204: bf00 nop 8004206: 370c adds r7, #12 8004208: 46bd mov sp, r7 800420a: f85d 7b04 ldr.w r7, [sp], #4 800420e: 4770 bx lr 08004210 : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan) { 8004210: b480 push {r7} 8004212: b083 sub sp, #12 8004214: af00 add r7, sp, #0 8004216: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox0AbortCallback could be implemented in the user file */ } 8004218: bf00 nop 800421a: 370c adds r7, #12 800421c: 46bd mov sp, r7 800421e: f85d 7b04 ldr.w r7, [sp], #4 8004222: 4770 bx lr 08004224 : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan) { 8004224: b480 push {r7} 8004226: b083 sub sp, #12 8004228: af00 add r7, sp, #0 800422a: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox1AbortCallback could be implemented in the user file */ } 800422c: bf00 nop 800422e: 370c adds r7, #12 8004230: 46bd mov sp, r7 8004232: f85d 7b04 ldr.w r7, [sp], #4 8004236: 4770 bx lr 08004238 : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan) { 8004238: b480 push {r7} 800423a: b083 sub sp, #12 800423c: af00 add r7, sp, #0 800423e: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox2AbortCallback could be implemented in the user file */ } 8004240: bf00 nop 8004242: 370c adds r7, #12 8004244: 46bd mov sp, r7 8004246: f85d 7b04 ldr.w r7, [sp], #4 800424a: 4770 bx lr 0800424c : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan) { 800424c: b480 push {r7} 800424e: b083 sub sp, #12 8004250: af00 add r7, sp, #0 8004252: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_RxFifo0FullCallback could be implemented in the user file */ } 8004254: bf00 nop 8004256: 370c adds r7, #12 8004258: 46bd mov sp, r7 800425a: f85d 7b04 ldr.w r7, [sp], #4 800425e: 4770 bx lr 08004260 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan) { 8004260: b480 push {r7} 8004262: b083 sub sp, #12 8004264: af00 add r7, sp, #0 8004266: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_RxFifo1MsgPendingCallback could be implemented in the user file */ } 8004268: bf00 nop 800426a: 370c adds r7, #12 800426c: 46bd mov sp, r7 800426e: f85d 7b04 ldr.w r7, [sp], #4 8004272: 4770 bx lr 08004274 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan) { 8004274: b480 push {r7} 8004276: b083 sub sp, #12 8004278: af00 add r7, sp, #0 800427a: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_RxFifo1FullCallback could be implemented in the user file */ } 800427c: bf00 nop 800427e: 370c adds r7, #12 8004280: 46bd mov sp, r7 8004282: f85d 7b04 ldr.w r7, [sp], #4 8004286: 4770 bx lr 08004288 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan) { 8004288: b480 push {r7} 800428a: b083 sub sp, #12 800428c: af00 add r7, sp, #0 800428e: 6078 str r0, [r7, #4] UNUSED(hcan); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_SleepCallback could be implemented in the user file */ } 8004290: bf00 nop 8004292: 370c adds r7, #12 8004294: 46bd mov sp, r7 8004296: f85d 7b04 ldr.w r7, [sp], #4 800429a: 4770 bx lr 0800429c : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan) { 800429c: b480 push {r7} 800429e: b083 sub sp, #12 80042a0: af00 add r7, sp, #0 80042a2: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_WakeUpFromRxMsgCallback could be implemented in the user file */ } 80042a4: bf00 nop 80042a6: 370c adds r7, #12 80042a8: 46bd mov sp, r7 80042aa: f85d 7b04 ldr.w r7, [sp], #4 80042ae: 4770 bx lr 080042b0 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) { 80042b0: b480 push {r7} 80042b2: b083 sub sp, #12 80042b4: af00 add r7, sp, #0 80042b6: 6078 str r0, [r7, #4] UNUSED(hcan); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_ErrorCallback could be implemented in the user file */ } 80042b8: bf00 nop 80042ba: 370c adds r7, #12 80042bc: 46bd mov sp, r7 80042be: f85d 7b04 ldr.w r7, [sp], #4 80042c2: 4770 bx lr 080042c4 <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 80042c4: b480 push {r7} 80042c6: b085 sub sp, #20 80042c8: af00 add r7, sp, #0 80042ca: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 80042cc: 687b ldr r3, [r7, #4] 80042ce: f003 0307 and.w r3, r3, #7 80042d2: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 80042d4: 4b0c ldr r3, [pc, #48] @ (8004308 <__NVIC_SetPriorityGrouping+0x44>) 80042d6: 68db ldr r3, [r3, #12] 80042d8: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 80042da: 68ba ldr r2, [r7, #8] 80042dc: f64f 03ff movw r3, #63743 @ 0xf8ff 80042e0: 4013 ands r3, r2 80042e2: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 80042e4: 68fb ldr r3, [r7, #12] 80042e6: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 80042e8: 68bb ldr r3, [r7, #8] 80042ea: 4313 orrs r3, r2 reg_value = (reg_value | 80042ec: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 80042f0: f443 3300 orr.w r3, r3, #131072 @ 0x20000 80042f4: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 80042f6: 4a04 ldr r2, [pc, #16] @ (8004308 <__NVIC_SetPriorityGrouping+0x44>) 80042f8: 68bb ldr r3, [r7, #8] 80042fa: 60d3 str r3, [r2, #12] } 80042fc: bf00 nop 80042fe: 3714 adds r7, #20 8004300: 46bd mov sp, r7 8004302: f85d 7b04 ldr.w r7, [sp], #4 8004306: 4770 bx lr 8004308: e000ed00 .word 0xe000ed00 0800430c <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { 800430c: b480 push {r7} 800430e: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 8004310: 4b04 ldr r3, [pc, #16] @ (8004324 <__NVIC_GetPriorityGrouping+0x18>) 8004312: 68db ldr r3, [r3, #12] 8004314: 0a1b lsrs r3, r3, #8 8004316: f003 0307 and.w r3, r3, #7 } 800431a: 4618 mov r0, r3 800431c: 46bd mov sp, r7 800431e: f85d 7b04 ldr.w r7, [sp], #4 8004322: 4770 bx lr 8004324: e000ed00 .word 0xe000ed00 08004328 <__NVIC_EnableIRQ>: \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { 8004328: b480 push {r7} 800432a: b083 sub sp, #12 800432c: af00 add r7, sp, #0 800432e: 4603 mov r3, r0 8004330: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8004332: f997 3007 ldrsb.w r3, [r7, #7] 8004336: 2b00 cmp r3, #0 8004338: db0b blt.n 8004352 <__NVIC_EnableIRQ+0x2a> { NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 800433a: 79fb ldrb r3, [r7, #7] 800433c: f003 021f and.w r2, r3, #31 8004340: 4907 ldr r1, [pc, #28] @ (8004360 <__NVIC_EnableIRQ+0x38>) 8004342: f997 3007 ldrsb.w r3, [r7, #7] 8004346: 095b lsrs r3, r3, #5 8004348: 2001 movs r0, #1 800434a: fa00 f202 lsl.w r2, r0, r2 800434e: f841 2023 str.w r2, [r1, r3, lsl #2] } } 8004352: bf00 nop 8004354: 370c adds r7, #12 8004356: 46bd mov sp, r7 8004358: f85d 7b04 ldr.w r7, [sp], #4 800435c: 4770 bx lr 800435e: bf00 nop 8004360: e000e100 .word 0xe000e100 08004364 <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 8004364: b480 push {r7} 8004366: b083 sub sp, #12 8004368: af00 add r7, sp, #0 800436a: 4603 mov r3, r0 800436c: 6039 str r1, [r7, #0] 800436e: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8004370: f997 3007 ldrsb.w r3, [r7, #7] 8004374: 2b00 cmp r3, #0 8004376: db0a blt.n 800438e <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8004378: 683b ldr r3, [r7, #0] 800437a: b2da uxtb r2, r3 800437c: 490c ldr r1, [pc, #48] @ (80043b0 <__NVIC_SetPriority+0x4c>) 800437e: f997 3007 ldrsb.w r3, [r7, #7] 8004382: 0112 lsls r2, r2, #4 8004384: b2d2 uxtb r2, r2 8004386: 440b add r3, r1 8004388: f883 2300 strb.w r2, [r3, #768] @ 0x300 } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } 800438c: e00a b.n 80043a4 <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 800438e: 683b ldr r3, [r7, #0] 8004390: b2da uxtb r2, r3 8004392: 4908 ldr r1, [pc, #32] @ (80043b4 <__NVIC_SetPriority+0x50>) 8004394: 79fb ldrb r3, [r7, #7] 8004396: f003 030f and.w r3, r3, #15 800439a: 3b04 subs r3, #4 800439c: 0112 lsls r2, r2, #4 800439e: b2d2 uxtb r2, r2 80043a0: 440b add r3, r1 80043a2: 761a strb r2, [r3, #24] } 80043a4: bf00 nop 80043a6: 370c adds r7, #12 80043a8: 46bd mov sp, r7 80043aa: f85d 7b04 ldr.w r7, [sp], #4 80043ae: 4770 bx lr 80043b0: e000e100 .word 0xe000e100 80043b4: e000ed00 .word 0xe000ed00 080043b8 : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { 80043b8: b480 push {r7} 80043ba: b089 sub sp, #36 @ 0x24 80043bc: af00 add r7, sp, #0 80043be: 60f8 str r0, [r7, #12] 80043c0: 60b9 str r1, [r7, #8] 80043c2: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 80043c4: 68fb ldr r3, [r7, #12] 80043c6: f003 0307 and.w r3, r3, #7 80043ca: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 80043cc: 69fb ldr r3, [r7, #28] 80043ce: f1c3 0307 rsb r3, r3, #7 80043d2: 2b04 cmp r3, #4 80043d4: bf28 it cs 80043d6: 2304 movcs r3, #4 80043d8: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 80043da: 69fb ldr r3, [r7, #28] 80043dc: 3304 adds r3, #4 80043de: 2b06 cmp r3, #6 80043e0: d902 bls.n 80043e8 80043e2: 69fb ldr r3, [r7, #28] 80043e4: 3b03 subs r3, #3 80043e6: e000 b.n 80043ea 80043e8: 2300 movs r3, #0 80043ea: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 80043ec: f04f 32ff mov.w r2, #4294967295 80043f0: 69bb ldr r3, [r7, #24] 80043f2: fa02 f303 lsl.w r3, r2, r3 80043f6: 43da mvns r2, r3 80043f8: 68bb ldr r3, [r7, #8] 80043fa: 401a ands r2, r3 80043fc: 697b ldr r3, [r7, #20] 80043fe: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 8004400: f04f 31ff mov.w r1, #4294967295 8004404: 697b ldr r3, [r7, #20] 8004406: fa01 f303 lsl.w r3, r1, r3 800440a: 43d9 mvns r1, r3 800440c: 687b ldr r3, [r7, #4] 800440e: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8004410: 4313 orrs r3, r2 ); } 8004412: 4618 mov r0, r3 8004414: 3724 adds r7, #36 @ 0x24 8004416: 46bd mov sp, r7 8004418: f85d 7b04 ldr.w r7, [sp], #4 800441c: 4770 bx lr ... 08004420 : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 8004420: b580 push {r7, lr} 8004422: b082 sub sp, #8 8004424: af00 add r7, sp, #0 8004426: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 8004428: 687b ldr r3, [r7, #4] 800442a: 3b01 subs r3, #1 800442c: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 8004430: d301 bcc.n 8004436 { return (1UL); /* Reload value impossible */ 8004432: 2301 movs r3, #1 8004434: e00f b.n 8004456 } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 8004436: 4a0a ldr r2, [pc, #40] @ (8004460 ) 8004438: 687b ldr r3, [r7, #4] 800443a: 3b01 subs r3, #1 800443c: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 800443e: 210f movs r1, #15 8004440: f04f 30ff mov.w r0, #4294967295 8004444: f7ff ff8e bl 8004364 <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 8004448: 4b05 ldr r3, [pc, #20] @ (8004460 ) 800444a: 2200 movs r2, #0 800444c: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 800444e: 4b04 ldr r3, [pc, #16] @ (8004460 ) 8004450: 2207 movs r2, #7 8004452: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 8004454: 2300 movs r3, #0 } 8004456: 4618 mov r0, r3 8004458: 3708 adds r7, #8 800445a: 46bd mov sp, r7 800445c: bd80 pop {r7, pc} 800445e: bf00 nop 8004460: e000e010 .word 0xe000e010 08004464 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8004464: b580 push {r7, lr} 8004466: b082 sub sp, #8 8004468: af00 add r7, sp, #0 800446a: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 800446c: 6878 ldr r0, [r7, #4] 800446e: f7ff ff29 bl 80042c4 <__NVIC_SetPriorityGrouping> } 8004472: bf00 nop 8004474: 3708 adds r7, #8 8004476: 46bd mov sp, r7 8004478: bd80 pop {r7, pc} 0800447a : * This parameter can be a value between 0 and 15 as described in the table CORTEX_NVIC_Priority_Table * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 800447a: b580 push {r7, lr} 800447c: b086 sub sp, #24 800447e: af00 add r7, sp, #0 8004480: 4603 mov r3, r0 8004482: 60b9 str r1, [r7, #8] 8004484: 607a str r2, [r7, #4] 8004486: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00U; 8004488: 2300 movs r3, #0 800448a: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 800448c: f7ff ff3e bl 800430c <__NVIC_GetPriorityGrouping> 8004490: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 8004492: 687a ldr r2, [r7, #4] 8004494: 68b9 ldr r1, [r7, #8] 8004496: 6978 ldr r0, [r7, #20] 8004498: f7ff ff8e bl 80043b8 800449c: 4602 mov r2, r0 800449e: f997 300f ldrsb.w r3, [r7, #15] 80044a2: 4611 mov r1, r2 80044a4: 4618 mov r0, r3 80044a6: f7ff ff5d bl 8004364 <__NVIC_SetPriority> } 80044aa: bf00 nop 80044ac: 3718 adds r7, #24 80044ae: 46bd mov sp, r7 80044b0: bd80 pop {r7, pc} 080044b2 : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 80044b2: b580 push {r7, lr} 80044b4: b082 sub sp, #8 80044b6: af00 add r7, sp, #0 80044b8: 4603 mov r3, r0 80044ba: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 80044bc: f997 3007 ldrsb.w r3, [r7, #7] 80044c0: 4618 mov r0, r3 80044c2: f7ff ff31 bl 8004328 <__NVIC_EnableIRQ> } 80044c6: bf00 nop 80044c8: 3708 adds r7, #8 80044ca: 46bd mov sp, r7 80044cc: bd80 pop {r7, pc} 080044ce : * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 80044ce: b580 push {r7, lr} 80044d0: b082 sub sp, #8 80044d2: af00 add r7, sp, #0 80044d4: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 80044d6: 6878 ldr r0, [r7, #4] 80044d8: f7ff ffa2 bl 8004420 80044dc: 4603 mov r3, r0 } 80044de: 4618 mov r0, r3 80044e0: 3708 adds r7, #8 80044e2: 46bd mov sp, r7 80044e4: bd80 pop {r7, pc} 080044e6 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) { 80044e6: b580 push {r7, lr} 80044e8: b084 sub sp, #16 80044ea: af00 add r7, sp, #0 80044ec: 6078 str r0, [r7, #4] uint32_t tmp = 0U; 80044ee: 2300 movs r3, #0 80044f0: 60fb str r3, [r7, #12] /* Check the DMA handle allocation */ if(NULL == hdma) 80044f2: 687b ldr r3, [r7, #4] 80044f4: 2b00 cmp r3, #0 80044f6: d101 bne.n 80044fc { return HAL_ERROR; 80044f8: 2301 movs r3, #1 80044fa: e037 b.n 800456c assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); assert_param(IS_DMA_MODE(hdma->Init.Mode)); assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 80044fc: 687b ldr r3, [r7, #4] 80044fe: 2202 movs r2, #2 8004500: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Get the CR register value */ tmp = hdma->Instance->CCR; 8004504: 687b ldr r3, [r7, #4] 8004506: 681b ldr r3, [r3, #0] 8004508: 681b ldr r3, [r3, #0] 800450a: 60fb str r3, [r7, #12] /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR bits */ tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \ 800450c: 68fb ldr r3, [r7, #12] 800450e: f423 537f bic.w r3, r3, #16320 @ 0x3fc0 8004512: f023 0330 bic.w r3, r3, #48 @ 0x30 8004516: 60fb str r3, [r7, #12] DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \ DMA_CCR_DIR)); /* Prepare the DMA Channel configuration */ tmp |= hdma->Init.Direction | 8004518: 687b ldr r3, [r7, #4] 800451a: 685a ldr r2, [r3, #4] hdma->Init.PeriphInc | hdma->Init.MemInc | 800451c: 687b ldr r3, [r7, #4] 800451e: 689b ldr r3, [r3, #8] tmp |= hdma->Init.Direction | 8004520: 431a orrs r2, r3 hdma->Init.PeriphInc | hdma->Init.MemInc | 8004522: 687b ldr r3, [r7, #4] 8004524: 68db ldr r3, [r3, #12] 8004526: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 8004528: 687b ldr r3, [r7, #4] 800452a: 691b ldr r3, [r3, #16] hdma->Init.PeriphInc | hdma->Init.MemInc | 800452c: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 800452e: 687b ldr r3, [r7, #4] 8004530: 695b ldr r3, [r3, #20] 8004532: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 8004534: 687b ldr r3, [r7, #4] 8004536: 699b ldr r3, [r3, #24] hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 8004538: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 800453a: 687b ldr r3, [r7, #4] 800453c: 69db ldr r3, [r3, #28] 800453e: 4313 orrs r3, r2 tmp |= hdma->Init.Direction | 8004540: 68fa ldr r2, [r7, #12] 8004542: 4313 orrs r3, r2 8004544: 60fb str r3, [r7, #12] /* Write to DMA Channel CR register */ hdma->Instance->CCR = tmp; 8004546: 687b ldr r3, [r7, #4] 8004548: 681b ldr r3, [r3, #0] 800454a: 68fa ldr r2, [r7, #12] 800454c: 601a str r2, [r3, #0] /* Initialize DmaBaseAddress and ChannelIndex parameters used by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ DMA_CalcBaseAndBitshift(hdma); 800454e: 6878 ldr r0, [r7, #4] 8004550: f000 f940 bl 80047d4 /* Initialise the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; 8004554: 687b ldr r3, [r7, #4] 8004556: 2200 movs r2, #0 8004558: 639a str r2, [r3, #56] @ 0x38 /* Initialize the DMA state*/ hdma->State = HAL_DMA_STATE_READY; 800455a: 687b ldr r3, [r7, #4] 800455c: 2201 movs r2, #1 800455e: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Allocate lock resource and initialize it */ hdma->Lock = HAL_UNLOCKED; 8004562: 687b ldr r3, [r7, #4] 8004564: 2200 movs r2, #0 8004566: f883 2020 strb.w r2, [r3, #32] return HAL_OK; 800456a: 2300 movs r3, #0 } 800456c: 4618 mov r0, r3 800456e: 3710 adds r7, #16 8004570: 46bd mov sp, r7 8004572: bd80 pop {r7, pc} 08004574 : * @param DstAddress The destination memory Buffer address * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 8004574: b580 push {r7, lr} 8004576: b086 sub sp, #24 8004578: af00 add r7, sp, #0 800457a: 60f8 str r0, [r7, #12] 800457c: 60b9 str r1, [r7, #8] 800457e: 607a str r2, [r7, #4] 8004580: 603b str r3, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 8004582: 2300 movs r3, #0 8004584: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); /* Process locked */ __HAL_LOCK(hdma); 8004586: 68fb ldr r3, [r7, #12] 8004588: f893 3020 ldrb.w r3, [r3, #32] 800458c: 2b01 cmp r3, #1 800458e: d101 bne.n 8004594 8004590: 2302 movs r3, #2 8004592: e04a b.n 800462a 8004594: 68fb ldr r3, [r7, #12] 8004596: 2201 movs r2, #1 8004598: f883 2020 strb.w r2, [r3, #32] if(HAL_DMA_STATE_READY == hdma->State) 800459c: 68fb ldr r3, [r7, #12] 800459e: f893 3021 ldrb.w r3, [r3, #33] @ 0x21 80045a2: 2b01 cmp r3, #1 80045a4: d13a bne.n 800461c { /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 80045a6: 68fb ldr r3, [r7, #12] 80045a8: 2202 movs r2, #2 80045aa: f883 2021 strb.w r2, [r3, #33] @ 0x21 hdma->ErrorCode = HAL_DMA_ERROR_NONE; 80045ae: 68fb ldr r3, [r7, #12] 80045b0: 2200 movs r2, #0 80045b2: 639a str r2, [r3, #56] @ 0x38 /* Disable the peripheral */ hdma->Instance->CCR &= ~DMA_CCR_EN; 80045b4: 68fb ldr r3, [r7, #12] 80045b6: 681b ldr r3, [r3, #0] 80045b8: 681a ldr r2, [r3, #0] 80045ba: 68fb ldr r3, [r7, #12] 80045bc: 681b ldr r3, [r3, #0] 80045be: f022 0201 bic.w r2, r2, #1 80045c2: 601a str r2, [r3, #0] /* Configure the source, destination address and the data length */ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); 80045c4: 683b ldr r3, [r7, #0] 80045c6: 687a ldr r2, [r7, #4] 80045c8: 68b9 ldr r1, [r7, #8] 80045ca: 68f8 ldr r0, [r7, #12] 80045cc: f000 f8d4 bl 8004778 /* Enable the transfer complete, & transfer error interrupts */ /* Half transfer interrupt is optional: enable it only if associated callback is available */ if(NULL != hdma->XferHalfCpltCallback ) 80045d0: 68fb ldr r3, [r7, #12] 80045d2: 6adb ldr r3, [r3, #44] @ 0x2c 80045d4: 2b00 cmp r3, #0 80045d6: d008 beq.n 80045ea { hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE); 80045d8: 68fb ldr r3, [r7, #12] 80045da: 681b ldr r3, [r3, #0] 80045dc: 681a ldr r2, [r3, #0] 80045de: 68fb ldr r3, [r7, #12] 80045e0: 681b ldr r3, [r3, #0] 80045e2: f042 020e orr.w r2, r2, #14 80045e6: 601a str r2, [r3, #0] 80045e8: e00f b.n 800460a } else { hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_TE); 80045ea: 68fb ldr r3, [r7, #12] 80045ec: 681b ldr r3, [r3, #0] 80045ee: 681a ldr r2, [r3, #0] 80045f0: 68fb ldr r3, [r7, #12] 80045f2: 681b ldr r3, [r3, #0] 80045f4: f042 020a orr.w r2, r2, #10 80045f8: 601a str r2, [r3, #0] hdma->Instance->CCR &= ~DMA_IT_HT; 80045fa: 68fb ldr r3, [r7, #12] 80045fc: 681b ldr r3, [r3, #0] 80045fe: 681a ldr r2, [r3, #0] 8004600: 68fb ldr r3, [r7, #12] 8004602: 681b ldr r3, [r3, #0] 8004604: f022 0204 bic.w r2, r2, #4 8004608: 601a str r2, [r3, #0] } /* Enable the Peripheral */ hdma->Instance->CCR |= DMA_CCR_EN; 800460a: 68fb ldr r3, [r7, #12] 800460c: 681b ldr r3, [r3, #0] 800460e: 681a ldr r2, [r3, #0] 8004610: 68fb ldr r3, [r7, #12] 8004612: 681b ldr r3, [r3, #0] 8004614: f042 0201 orr.w r2, r2, #1 8004618: 601a str r2, [r3, #0] 800461a: e005 b.n 8004628 } else { /* Process Unlocked */ __HAL_UNLOCK(hdma); 800461c: 68fb ldr r3, [r7, #12] 800461e: 2200 movs r2, #0 8004620: f883 2020 strb.w r2, [r3, #32] /* Remain BUSY */ status = HAL_BUSY; 8004624: 2302 movs r3, #2 8004626: 75fb strb r3, [r7, #23] } return status; 8004628: 7dfb ldrb r3, [r7, #23] } 800462a: 4618 mov r0, r3 800462c: 3718 adds r7, #24 800462e: 46bd mov sp, r7 8004630: bd80 pop {r7, pc} 08004632 : * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval None */ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) { 8004632: b580 push {r7, lr} 8004634: b084 sub sp, #16 8004636: af00 add r7, sp, #0 8004638: 6078 str r0, [r7, #4] uint32_t flag_it = hdma->DmaBaseAddress->ISR; 800463a: 687b ldr r3, [r7, #4] 800463c: 6bdb ldr r3, [r3, #60] @ 0x3c 800463e: 681b ldr r3, [r3, #0] 8004640: 60fb str r3, [r7, #12] uint32_t source_it = hdma->Instance->CCR; 8004642: 687b ldr r3, [r7, #4] 8004644: 681b ldr r3, [r3, #0] 8004646: 681b ldr r3, [r3, #0] 8004648: 60bb str r3, [r7, #8] /* Half Transfer Complete Interrupt management ******************************/ if ((RESET != (flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_HT))) 800464a: 687b ldr r3, [r7, #4] 800464c: 6c1b ldr r3, [r3, #64] @ 0x40 800464e: 2204 movs r2, #4 8004650: 409a lsls r2, r3 8004652: 68fb ldr r3, [r7, #12] 8004654: 4013 ands r3, r2 8004656: 2b00 cmp r3, #0 8004658: d024 beq.n 80046a4 800465a: 68bb ldr r3, [r7, #8] 800465c: f003 0304 and.w r3, r3, #4 8004660: 2b00 cmp r3, #0 8004662: d01f beq.n 80046a4 { /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) 8004664: 687b ldr r3, [r7, #4] 8004666: 681b ldr r3, [r3, #0] 8004668: 681b ldr r3, [r3, #0] 800466a: f003 0320 and.w r3, r3, #32 800466e: 2b00 cmp r3, #0 8004670: d107 bne.n 8004682 { /* Disable the half transfer interrupt */ hdma->Instance->CCR &= ~DMA_IT_HT; 8004672: 687b ldr r3, [r7, #4] 8004674: 681b ldr r3, [r3, #0] 8004676: 681a ldr r2, [r3, #0] 8004678: 687b ldr r3, [r7, #4] 800467a: 681b ldr r3, [r3, #0] 800467c: f022 0204 bic.w r2, r2, #4 8004680: 601a str r2, [r3, #0] } /* Clear the half transfer complete flag */ hdma->DmaBaseAddress->IFCR = DMA_FLAG_HT1 << hdma->ChannelIndex; 8004682: 687b ldr r3, [r7, #4] 8004684: 6c1a ldr r2, [r3, #64] @ 0x40 8004686: 687b ldr r3, [r7, #4] 8004688: 6bdb ldr r3, [r3, #60] @ 0x3c 800468a: 2104 movs r1, #4 800468c: fa01 f202 lsl.w r2, r1, r2 8004690: 605a str r2, [r3, #4] /* DMA peripheral state is not updated in Half Transfer */ /* State is updated only in Transfer Complete case */ if(hdma->XferHalfCpltCallback != NULL) 8004692: 687b ldr r3, [r7, #4] 8004694: 6adb ldr r3, [r3, #44] @ 0x2c 8004696: 2b00 cmp r3, #0 8004698: d06a beq.n 8004770 { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 800469a: 687b ldr r3, [r7, #4] 800469c: 6adb ldr r3, [r3, #44] @ 0x2c 800469e: 6878 ldr r0, [r7, #4] 80046a0: 4798 blx r3 if(hdma->XferHalfCpltCallback != NULL) 80046a2: e065 b.n 8004770 } } /* Transfer Complete Interrupt management ***********************************/ else if ((RESET != (flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TC))) 80046a4: 687b ldr r3, [r7, #4] 80046a6: 6c1b ldr r3, [r3, #64] @ 0x40 80046a8: 2202 movs r2, #2 80046aa: 409a lsls r2, r3 80046ac: 68fb ldr r3, [r7, #12] 80046ae: 4013 ands r3, r2 80046b0: 2b00 cmp r3, #0 80046b2: d02c beq.n 800470e 80046b4: 68bb ldr r3, [r7, #8] 80046b6: f003 0302 and.w r3, r3, #2 80046ba: 2b00 cmp r3, #0 80046bc: d027 beq.n 800470e { if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) 80046be: 687b ldr r3, [r7, #4] 80046c0: 681b ldr r3, [r3, #0] 80046c2: 681b ldr r3, [r3, #0] 80046c4: f003 0320 and.w r3, r3, #32 80046c8: 2b00 cmp r3, #0 80046ca: d10b bne.n 80046e4 { /* Disable the transfer complete & transfer error interrupts */ /* if the DMA mode is not CIRCULAR */ hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_TE); 80046cc: 687b ldr r3, [r7, #4] 80046ce: 681b ldr r3, [r3, #0] 80046d0: 681a ldr r2, [r3, #0] 80046d2: 687b ldr r3, [r7, #4] 80046d4: 681b ldr r3, [r3, #0] 80046d6: f022 020a bic.w r2, r2, #10 80046da: 601a str r2, [r3, #0] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 80046dc: 687b ldr r3, [r7, #4] 80046de: 2201 movs r2, #1 80046e0: f883 2021 strb.w r2, [r3, #33] @ 0x21 } /* Clear the transfer complete flag */ hdma->DmaBaseAddress->IFCR = DMA_FLAG_TC1 << hdma->ChannelIndex; 80046e4: 687b ldr r3, [r7, #4] 80046e6: 6c1a ldr r2, [r3, #64] @ 0x40 80046e8: 687b ldr r3, [r7, #4] 80046ea: 6bdb ldr r3, [r3, #60] @ 0x3c 80046ec: 2102 movs r1, #2 80046ee: fa01 f202 lsl.w r2, r1, r2 80046f2: 605a str r2, [r3, #4] /* Process Unlocked */ __HAL_UNLOCK(hdma); 80046f4: 687b ldr r3, [r7, #4] 80046f6: 2200 movs r2, #0 80046f8: f883 2020 strb.w r2, [r3, #32] if(hdma->XferCpltCallback != NULL) 80046fc: 687b ldr r3, [r7, #4] 80046fe: 6a9b ldr r3, [r3, #40] @ 0x28 8004700: 2b00 cmp r3, #0 8004702: d035 beq.n 8004770 { /* Transfer complete callback */ hdma->XferCpltCallback(hdma); 8004704: 687b ldr r3, [r7, #4] 8004706: 6a9b ldr r3, [r3, #40] @ 0x28 8004708: 6878 ldr r0, [r7, #4] 800470a: 4798 blx r3 if(hdma->XferCpltCallback != NULL) 800470c: e030 b.n 8004770 } } /* Transfer Error Interrupt management ***************************************/ else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE))) 800470e: 687b ldr r3, [r7, #4] 8004710: 6c1b ldr r3, [r3, #64] @ 0x40 8004712: 2208 movs r2, #8 8004714: 409a lsls r2, r3 8004716: 68fb ldr r3, [r7, #12] 8004718: 4013 ands r3, r2 800471a: 2b00 cmp r3, #0 800471c: d028 beq.n 8004770 800471e: 68bb ldr r3, [r7, #8] 8004720: f003 0308 and.w r3, r3, #8 8004724: 2b00 cmp r3, #0 8004726: d023 beq.n 8004770 { /* When a DMA transfer error occurs */ /* A hardware clear of its EN bits is performed */ /* Then, disable all DMA interrupts */ hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE); 8004728: 687b ldr r3, [r7, #4] 800472a: 681b ldr r3, [r3, #0] 800472c: 681a ldr r2, [r3, #0] 800472e: 687b ldr r3, [r7, #4] 8004730: 681b ldr r3, [r3, #0] 8004732: f022 020e bic.w r2, r2, #14 8004736: 601a str r2, [r3, #0] /* Clear all flags */ hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex; 8004738: 687b ldr r3, [r7, #4] 800473a: 6c1a ldr r2, [r3, #64] @ 0x40 800473c: 687b ldr r3, [r7, #4] 800473e: 6bdb ldr r3, [r3, #60] @ 0x3c 8004740: 2101 movs r1, #1 8004742: fa01 f202 lsl.w r2, r1, r2 8004746: 605a str r2, [r3, #4] /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TE; 8004748: 687b ldr r3, [r7, #4] 800474a: 2201 movs r2, #1 800474c: 639a str r2, [r3, #56] @ 0x38 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 800474e: 687b ldr r3, [r7, #4] 8004750: 2201 movs r2, #1 8004752: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8004756: 687b ldr r3, [r7, #4] 8004758: 2200 movs r2, #0 800475a: f883 2020 strb.w r2, [r3, #32] if(hdma->XferErrorCallback != NULL) 800475e: 687b ldr r3, [r7, #4] 8004760: 6b1b ldr r3, [r3, #48] @ 0x30 8004762: 2b00 cmp r3, #0 8004764: d004 beq.n 8004770 { /* Transfer error callback */ hdma->XferErrorCallback(hdma); 8004766: 687b ldr r3, [r7, #4] 8004768: 6b1b ldr r3, [r3, #48] @ 0x30 800476a: 6878 ldr r0, [r7, #4] 800476c: 4798 blx r3 } } } 800476e: e7ff b.n 8004770 8004770: bf00 nop 8004772: 3710 adds r7, #16 8004774: 46bd mov sp, r7 8004776: bd80 pop {r7, pc} 08004778 : * @param DstAddress The destination memory Buffer address * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 8004778: b480 push {r7} 800477a: b085 sub sp, #20 800477c: af00 add r7, sp, #0 800477e: 60f8 str r0, [r7, #12] 8004780: 60b9 str r1, [r7, #8] 8004782: 607a str r2, [r7, #4] 8004784: 603b str r3, [r7, #0] /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_FLAG_GL1 << hdma->ChannelIndex); 8004786: 68fb ldr r3, [r7, #12] 8004788: 6c1a ldr r2, [r3, #64] @ 0x40 800478a: 68fb ldr r3, [r7, #12] 800478c: 6bdb ldr r3, [r3, #60] @ 0x3c 800478e: 2101 movs r1, #1 8004790: fa01 f202 lsl.w r2, r1, r2 8004794: 605a str r2, [r3, #4] /* Configure DMA Channel data length */ hdma->Instance->CNDTR = DataLength; 8004796: 68fb ldr r3, [r7, #12] 8004798: 681b ldr r3, [r3, #0] 800479a: 683a ldr r2, [r7, #0] 800479c: 605a str r2, [r3, #4] /* Peripheral to Memory */ if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) 800479e: 68fb ldr r3, [r7, #12] 80047a0: 685b ldr r3, [r3, #4] 80047a2: 2b10 cmp r3, #16 80047a4: d108 bne.n 80047b8 { /* Configure DMA Channel destination address */ hdma->Instance->CPAR = DstAddress; 80047a6: 68fb ldr r3, [r7, #12] 80047a8: 681b ldr r3, [r3, #0] 80047aa: 687a ldr r2, [r7, #4] 80047ac: 609a str r2, [r3, #8] /* Configure DMA Channel source address */ hdma->Instance->CMAR = SrcAddress; 80047ae: 68fb ldr r3, [r7, #12] 80047b0: 681b ldr r3, [r3, #0] 80047b2: 68ba ldr r2, [r7, #8] 80047b4: 60da str r2, [r3, #12] hdma->Instance->CPAR = SrcAddress; /* Configure DMA Channel destination address */ hdma->Instance->CMAR = DstAddress; } } 80047b6: e007 b.n 80047c8 hdma->Instance->CPAR = SrcAddress; 80047b8: 68fb ldr r3, [r7, #12] 80047ba: 681b ldr r3, [r3, #0] 80047bc: 68ba ldr r2, [r7, #8] 80047be: 609a str r2, [r3, #8] hdma->Instance->CMAR = DstAddress; 80047c0: 68fb ldr r3, [r7, #12] 80047c2: 681b ldr r3, [r3, #0] 80047c4: 687a ldr r2, [r7, #4] 80047c6: 60da str r2, [r3, #12] } 80047c8: bf00 nop 80047ca: 3714 adds r7, #20 80047cc: 46bd mov sp, r7 80047ce: f85d 7b04 ldr.w r7, [sp], #4 80047d2: 4770 bx lr 080047d4 : * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval None */ static void DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) { 80047d4: b480 push {r7} 80047d6: b083 sub sp, #12 80047d8: af00 add r7, sp, #0 80047da: 6078 str r0, [r7, #4] #if defined (DMA2) /* calculation of the channel index */ if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) 80047dc: 687b ldr r3, [r7, #4] 80047de: 681b ldr r3, [r3, #0] 80047e0: 461a mov r2, r3 80047e2: 4b14 ldr r3, [pc, #80] @ (8004834 ) 80047e4: 429a cmp r2, r3 80047e6: d80f bhi.n 8004808 { /* DMA1 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; 80047e8: 687b ldr r3, [r7, #4] 80047ea: 681b ldr r3, [r3, #0] 80047ec: 461a mov r2, r3 80047ee: 4b12 ldr r3, [pc, #72] @ (8004838 ) 80047f0: 4413 add r3, r2 80047f2: 4a12 ldr r2, [pc, #72] @ (800483c ) 80047f4: fba2 2303 umull r2, r3, r2, r3 80047f8: 091b lsrs r3, r3, #4 80047fa: 009a lsls r2, r3, #2 80047fc: 687b ldr r3, [r7, #4] 80047fe: 641a str r2, [r3, #64] @ 0x40 hdma->DmaBaseAddress = DMA1; 8004800: 687b ldr r3, [r7, #4] 8004802: 4a0f ldr r2, [pc, #60] @ (8004840 ) 8004804: 63da str r2, [r3, #60] @ 0x3c /* calculation of the channel index */ /* DMA1 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; hdma->DmaBaseAddress = DMA1; #endif } 8004806: e00e b.n 8004826 hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U; 8004808: 687b ldr r3, [r7, #4] 800480a: 681b ldr r3, [r3, #0] 800480c: 461a mov r2, r3 800480e: 4b0d ldr r3, [pc, #52] @ (8004844 ) 8004810: 4413 add r3, r2 8004812: 4a0a ldr r2, [pc, #40] @ (800483c ) 8004814: fba2 2303 umull r2, r3, r2, r3 8004818: 091b lsrs r3, r3, #4 800481a: 009a lsls r2, r3, #2 800481c: 687b ldr r3, [r7, #4] 800481e: 641a str r2, [r3, #64] @ 0x40 hdma->DmaBaseAddress = DMA2; 8004820: 687b ldr r3, [r7, #4] 8004822: 4a09 ldr r2, [pc, #36] @ (8004848 ) 8004824: 63da str r2, [r3, #60] @ 0x3c } 8004826: bf00 nop 8004828: 370c adds r7, #12 800482a: 46bd mov sp, r7 800482c: f85d 7b04 ldr.w r7, [sp], #4 8004830: 4770 bx lr 8004832: bf00 nop 8004834: 40020407 .word 0x40020407 8004838: bffdfff8 .word 0xbffdfff8 800483c: cccccccd .word 0xcccccccd 8004840: 40020000 .word 0x40020000 8004844: bffdfbf8 .word 0xbffdfbf8 8004848: 40020400 .word 0x40020400 0800484c : * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 800484c: b480 push {r7} 800484e: b087 sub sp, #28 8004850: af00 add r7, sp, #0 8004852: 6078 str r0, [r7, #4] 8004854: 6039 str r1, [r7, #0] uint32_t position = 0x00u; 8004856: 2300 movs r3, #0 8004858: 617b str r3, [r7, #20] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00u) 800485a: e154 b.n 8004b06 { /* Get current io position */ iocurrent = (GPIO_Init->Pin) & (1uL << position); 800485c: 683b ldr r3, [r7, #0] 800485e: 681a ldr r2, [r3, #0] 8004860: 2101 movs r1, #1 8004862: 697b ldr r3, [r7, #20] 8004864: fa01 f303 lsl.w r3, r1, r3 8004868: 4013 ands r3, r2 800486a: 60fb str r3, [r7, #12] if (iocurrent != 0x00u) 800486c: 68fb ldr r3, [r7, #12] 800486e: 2b00 cmp r3, #0 8004870: f000 8146 beq.w 8004b00 { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) 8004874: 683b ldr r3, [r7, #0] 8004876: 685b ldr r3, [r3, #4] 8004878: f003 0303 and.w r3, r3, #3 800487c: 2b01 cmp r3, #1 800487e: d005 beq.n 800488c 8004880: 683b ldr r3, [r7, #0] 8004882: 685b ldr r3, [r3, #4] 8004884: f003 0303 and.w r3, r3, #3 8004888: 2b02 cmp r3, #2 800488a: d130 bne.n 80048ee { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; 800488c: 687b ldr r3, [r7, #4] 800488e: 689b ldr r3, [r3, #8] 8004890: 613b str r3, [r7, #16] temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2u)); 8004892: 697b ldr r3, [r7, #20] 8004894: 005b lsls r3, r3, #1 8004896: 2203 movs r2, #3 8004898: fa02 f303 lsl.w r3, r2, r3 800489c: 43db mvns r3, r3 800489e: 693a ldr r2, [r7, #16] 80048a0: 4013 ands r3, r2 80048a2: 613b str r3, [r7, #16] temp |= (GPIO_Init->Speed << (position * 2u)); 80048a4: 683b ldr r3, [r7, #0] 80048a6: 68da ldr r2, [r3, #12] 80048a8: 697b ldr r3, [r7, #20] 80048aa: 005b lsls r3, r3, #1 80048ac: fa02 f303 lsl.w r3, r2, r3 80048b0: 693a ldr r2, [r7, #16] 80048b2: 4313 orrs r3, r2 80048b4: 613b str r3, [r7, #16] GPIOx->OSPEEDR = temp; 80048b6: 687b ldr r3, [r7, #4] 80048b8: 693a ldr r2, [r7, #16] 80048ba: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; 80048bc: 687b ldr r3, [r7, #4] 80048be: 685b ldr r3, [r3, #4] 80048c0: 613b str r3, [r7, #16] temp &= ~(GPIO_OTYPER_OT_0 << position) ; 80048c2: 2201 movs r2, #1 80048c4: 697b ldr r3, [r7, #20] 80048c6: fa02 f303 lsl.w r3, r2, r3 80048ca: 43db mvns r3, r3 80048cc: 693a ldr r2, [r7, #16] 80048ce: 4013 ands r3, r2 80048d0: 613b str r3, [r7, #16] temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); 80048d2: 683b ldr r3, [r7, #0] 80048d4: 685b ldr r3, [r3, #4] 80048d6: 091b lsrs r3, r3, #4 80048d8: f003 0201 and.w r2, r3, #1 80048dc: 697b ldr r3, [r7, #20] 80048de: fa02 f303 lsl.w r3, r2, r3 80048e2: 693a ldr r2, [r7, #16] 80048e4: 4313 orrs r3, r2 80048e6: 613b str r3, [r7, #16] GPIOx->OTYPER = temp; 80048e8: 687b ldr r3, [r7, #4] 80048ea: 693a ldr r2, [r7, #16] 80048ec: 605a str r2, [r3, #4] } if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) 80048ee: 683b ldr r3, [r7, #0] 80048f0: 685b ldr r3, [r3, #4] 80048f2: f003 0303 and.w r3, r3, #3 80048f6: 2b03 cmp r3, #3 80048f8: d017 beq.n 800492a { /* Check the Pull parameter */ assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; 80048fa: 687b ldr r3, [r7, #4] 80048fc: 68db ldr r3, [r3, #12] 80048fe: 613b str r3, [r7, #16] temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2u)); 8004900: 697b ldr r3, [r7, #20] 8004902: 005b lsls r3, r3, #1 8004904: 2203 movs r2, #3 8004906: fa02 f303 lsl.w r3, r2, r3 800490a: 43db mvns r3, r3 800490c: 693a ldr r2, [r7, #16] 800490e: 4013 ands r3, r2 8004910: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Pull) << (position * 2u)); 8004912: 683b ldr r3, [r7, #0] 8004914: 689a ldr r2, [r3, #8] 8004916: 697b ldr r3, [r7, #20] 8004918: 005b lsls r3, r3, #1 800491a: fa02 f303 lsl.w r3, r2, r3 800491e: 693a ldr r2, [r7, #16] 8004920: 4313 orrs r3, r2 8004922: 613b str r3, [r7, #16] GPIOx->PUPDR = temp; 8004924: 687b ldr r3, [r7, #4] 8004926: 693a ldr r2, [r7, #16] 8004928: 60da str r2, [r3, #12] } /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Alternate function mode selection */ if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 800492a: 683b ldr r3, [r7, #0] 800492c: 685b ldr r3, [r3, #4] 800492e: f003 0303 and.w r3, r3, #3 8004932: 2b02 cmp r3, #2 8004934: d123 bne.n 800497e /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3u]; 8004936: 697b ldr r3, [r7, #20] 8004938: 08da lsrs r2, r3, #3 800493a: 687b ldr r3, [r7, #4] 800493c: 3208 adds r2, #8 800493e: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8004942: 613b str r3, [r7, #16] temp &= ~(0xFu << ((position & 0x07u) * 4u)); 8004944: 697b ldr r3, [r7, #20] 8004946: f003 0307 and.w r3, r3, #7 800494a: 009b lsls r3, r3, #2 800494c: 220f movs r2, #15 800494e: fa02 f303 lsl.w r3, r2, r3 8004952: 43db mvns r3, r3 8004954: 693a ldr r2, [r7, #16] 8004956: 4013 ands r3, r2 8004958: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u)); 800495a: 683b ldr r3, [r7, #0] 800495c: 691a ldr r2, [r3, #16] 800495e: 697b ldr r3, [r7, #20] 8004960: f003 0307 and.w r3, r3, #7 8004964: 009b lsls r3, r3, #2 8004966: fa02 f303 lsl.w r3, r2, r3 800496a: 693a ldr r2, [r7, #16] 800496c: 4313 orrs r3, r2 800496e: 613b str r3, [r7, #16] GPIOx->AFR[position >> 3u] = temp; 8004970: 697b ldr r3, [r7, #20] 8004972: 08da lsrs r2, r3, #3 8004974: 687b ldr r3, [r7, #4] 8004976: 3208 adds r2, #8 8004978: 6939 ldr r1, [r7, #16] 800497a: f843 1022 str.w r1, [r3, r2, lsl #2] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; 800497e: 687b ldr r3, [r7, #4] 8004980: 681b ldr r3, [r3, #0] 8004982: 613b str r3, [r7, #16] temp &= ~(GPIO_MODER_MODER0 << (position * 2u)); 8004984: 697b ldr r3, [r7, #20] 8004986: 005b lsls r3, r3, #1 8004988: 2203 movs r2, #3 800498a: fa02 f303 lsl.w r3, r2, r3 800498e: 43db mvns r3, r3 8004990: 693a ldr r2, [r7, #16] 8004992: 4013 ands r3, r2 8004994: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u)); 8004996: 683b ldr r3, [r7, #0] 8004998: 685b ldr r3, [r3, #4] 800499a: f003 0203 and.w r2, r3, #3 800499e: 697b ldr r3, [r7, #20] 80049a0: 005b lsls r3, r3, #1 80049a2: fa02 f303 lsl.w r3, r2, r3 80049a6: 693a ldr r2, [r7, #16] 80049a8: 4313 orrs r3, r2 80049aa: 613b str r3, [r7, #16] GPIOx->MODER = temp; 80049ac: 687b ldr r3, [r7, #4] 80049ae: 693a ldr r2, [r7, #16] 80049b0: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if((GPIO_Init->Mode & EXTI_MODE) != 0x00u) 80049b2: 683b ldr r3, [r7, #0] 80049b4: 685b ldr r3, [r3, #4] 80049b6: f403 3340 and.w r3, r3, #196608 @ 0x30000 80049ba: 2b00 cmp r3, #0 80049bc: f000 80a0 beq.w 8004b00 { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 80049c0: 4b58 ldr r3, [pc, #352] @ (8004b24 ) 80049c2: 699b ldr r3, [r3, #24] 80049c4: 4a57 ldr r2, [pc, #348] @ (8004b24 ) 80049c6: f043 0301 orr.w r3, r3, #1 80049ca: 6193 str r3, [r2, #24] 80049cc: 4b55 ldr r3, [pc, #340] @ (8004b24 ) 80049ce: 699b ldr r3, [r3, #24] 80049d0: f003 0301 and.w r3, r3, #1 80049d4: 60bb str r3, [r7, #8] 80049d6: 68bb ldr r3, [r7, #8] temp = SYSCFG->EXTICR[position >> 2u]; 80049d8: 4a53 ldr r2, [pc, #332] @ (8004b28 ) 80049da: 697b ldr r3, [r7, #20] 80049dc: 089b lsrs r3, r3, #2 80049de: 3302 adds r3, #2 80049e0: f852 3023 ldr.w r3, [r2, r3, lsl #2] 80049e4: 613b str r3, [r7, #16] temp &= ~(0x0FuL << (4u * (position & 0x03u))); 80049e6: 697b ldr r3, [r7, #20] 80049e8: f003 0303 and.w r3, r3, #3 80049ec: 009b lsls r3, r3, #2 80049ee: 220f movs r2, #15 80049f0: fa02 f303 lsl.w r3, r2, r3 80049f4: 43db mvns r3, r3 80049f6: 693a ldr r2, [r7, #16] 80049f8: 4013 ands r3, r2 80049fa: 613b str r3, [r7, #16] temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u))); 80049fc: 687b ldr r3, [r7, #4] 80049fe: f1b3 4f90 cmp.w r3, #1207959552 @ 0x48000000 8004a02: d019 beq.n 8004a38 8004a04: 687b ldr r3, [r7, #4] 8004a06: 4a49 ldr r2, [pc, #292] @ (8004b2c ) 8004a08: 4293 cmp r3, r2 8004a0a: d013 beq.n 8004a34 8004a0c: 687b ldr r3, [r7, #4] 8004a0e: 4a48 ldr r2, [pc, #288] @ (8004b30 ) 8004a10: 4293 cmp r3, r2 8004a12: d00d beq.n 8004a30 8004a14: 687b ldr r3, [r7, #4] 8004a16: 4a47 ldr r2, [pc, #284] @ (8004b34 ) 8004a18: 4293 cmp r3, r2 8004a1a: d007 beq.n 8004a2c 8004a1c: 687b ldr r3, [r7, #4] 8004a1e: 4a46 ldr r2, [pc, #280] @ (8004b38 ) 8004a20: 4293 cmp r3, r2 8004a22: d101 bne.n 8004a28 8004a24: 2304 movs r3, #4 8004a26: e008 b.n 8004a3a 8004a28: 2305 movs r3, #5 8004a2a: e006 b.n 8004a3a 8004a2c: 2303 movs r3, #3 8004a2e: e004 b.n 8004a3a 8004a30: 2302 movs r3, #2 8004a32: e002 b.n 8004a3a 8004a34: 2301 movs r3, #1 8004a36: e000 b.n 8004a3a 8004a38: 2300 movs r3, #0 8004a3a: 697a ldr r2, [r7, #20] 8004a3c: f002 0203 and.w r2, r2, #3 8004a40: 0092 lsls r2, r2, #2 8004a42: 4093 lsls r3, r2 8004a44: 693a ldr r2, [r7, #16] 8004a46: 4313 orrs r3, r2 8004a48: 613b str r3, [r7, #16] SYSCFG->EXTICR[position >> 2u] = temp; 8004a4a: 4937 ldr r1, [pc, #220] @ (8004b28 ) 8004a4c: 697b ldr r3, [r7, #20] 8004a4e: 089b lsrs r3, r3, #2 8004a50: 3302 adds r3, #2 8004a52: 693a ldr r2, [r7, #16] 8004a54: f841 2023 str.w r2, [r1, r3, lsl #2] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR; 8004a58: 4b38 ldr r3, [pc, #224] @ (8004b3c ) 8004a5a: 689b ldr r3, [r3, #8] 8004a5c: 613b str r3, [r7, #16] temp &= ~(iocurrent); 8004a5e: 68fb ldr r3, [r7, #12] 8004a60: 43db mvns r3, r3 8004a62: 693a ldr r2, [r7, #16] 8004a64: 4013 ands r3, r2 8004a66: 613b str r3, [r7, #16] if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u) 8004a68: 683b ldr r3, [r7, #0] 8004a6a: 685b ldr r3, [r3, #4] 8004a6c: f403 1380 and.w r3, r3, #1048576 @ 0x100000 8004a70: 2b00 cmp r3, #0 8004a72: d003 beq.n 8004a7c { temp |= iocurrent; 8004a74: 693a ldr r2, [r7, #16] 8004a76: 68fb ldr r3, [r7, #12] 8004a78: 4313 orrs r3, r2 8004a7a: 613b str r3, [r7, #16] } EXTI->RTSR = temp; 8004a7c: 4a2f ldr r2, [pc, #188] @ (8004b3c ) 8004a7e: 693b ldr r3, [r7, #16] 8004a80: 6093 str r3, [r2, #8] temp = EXTI->FTSR; 8004a82: 4b2e ldr r3, [pc, #184] @ (8004b3c ) 8004a84: 68db ldr r3, [r3, #12] 8004a86: 613b str r3, [r7, #16] temp &= ~(iocurrent); 8004a88: 68fb ldr r3, [r7, #12] 8004a8a: 43db mvns r3, r3 8004a8c: 693a ldr r2, [r7, #16] 8004a8e: 4013 ands r3, r2 8004a90: 613b str r3, [r7, #16] if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u) 8004a92: 683b ldr r3, [r7, #0] 8004a94: 685b ldr r3, [r3, #4] 8004a96: f403 1300 and.w r3, r3, #2097152 @ 0x200000 8004a9a: 2b00 cmp r3, #0 8004a9c: d003 beq.n 8004aa6 { temp |= iocurrent; 8004a9e: 693a ldr r2, [r7, #16] 8004aa0: 68fb ldr r3, [r7, #12] 8004aa2: 4313 orrs r3, r2 8004aa4: 613b str r3, [r7, #16] } EXTI->FTSR = temp; 8004aa6: 4a25 ldr r2, [pc, #148] @ (8004b3c ) 8004aa8: 693b ldr r3, [r7, #16] 8004aaa: 60d3 str r3, [r2, #12] temp = EXTI->EMR; 8004aac: 4b23 ldr r3, [pc, #140] @ (8004b3c ) 8004aae: 685b ldr r3, [r3, #4] 8004ab0: 613b str r3, [r7, #16] temp &= ~(iocurrent); 8004ab2: 68fb ldr r3, [r7, #12] 8004ab4: 43db mvns r3, r3 8004ab6: 693a ldr r2, [r7, #16] 8004ab8: 4013 ands r3, r2 8004aba: 613b str r3, [r7, #16] if((GPIO_Init->Mode & EXTI_EVT) != 0x00u) 8004abc: 683b ldr r3, [r7, #0] 8004abe: 685b ldr r3, [r3, #4] 8004ac0: f403 3300 and.w r3, r3, #131072 @ 0x20000 8004ac4: 2b00 cmp r3, #0 8004ac6: d003 beq.n 8004ad0 { temp |= iocurrent; 8004ac8: 693a ldr r2, [r7, #16] 8004aca: 68fb ldr r3, [r7, #12] 8004acc: 4313 orrs r3, r2 8004ace: 613b str r3, [r7, #16] } EXTI->EMR = temp; 8004ad0: 4a1a ldr r2, [pc, #104] @ (8004b3c ) 8004ad2: 693b ldr r3, [r7, #16] 8004ad4: 6053 str r3, [r2, #4] /* Clear EXTI line configuration */ temp = EXTI->IMR; 8004ad6: 4b19 ldr r3, [pc, #100] @ (8004b3c ) 8004ad8: 681b ldr r3, [r3, #0] 8004ada: 613b str r3, [r7, #16] temp &= ~(iocurrent); 8004adc: 68fb ldr r3, [r7, #12] 8004ade: 43db mvns r3, r3 8004ae0: 693a ldr r2, [r7, #16] 8004ae2: 4013 ands r3, r2 8004ae4: 613b str r3, [r7, #16] if((GPIO_Init->Mode & EXTI_IT) != 0x00u) 8004ae6: 683b ldr r3, [r7, #0] 8004ae8: 685b ldr r3, [r3, #4] 8004aea: f403 3380 and.w r3, r3, #65536 @ 0x10000 8004aee: 2b00 cmp r3, #0 8004af0: d003 beq.n 8004afa { temp |= iocurrent; 8004af2: 693a ldr r2, [r7, #16] 8004af4: 68fb ldr r3, [r7, #12] 8004af6: 4313 orrs r3, r2 8004af8: 613b str r3, [r7, #16] } EXTI->IMR = temp; 8004afa: 4a10 ldr r2, [pc, #64] @ (8004b3c ) 8004afc: 693b ldr r3, [r7, #16] 8004afe: 6013 str r3, [r2, #0] } } position++; 8004b00: 697b ldr r3, [r7, #20] 8004b02: 3301 adds r3, #1 8004b04: 617b str r3, [r7, #20] while (((GPIO_Init->Pin) >> position) != 0x00u) 8004b06: 683b ldr r3, [r7, #0] 8004b08: 681a ldr r2, [r3, #0] 8004b0a: 697b ldr r3, [r7, #20] 8004b0c: fa22 f303 lsr.w r3, r2, r3 8004b10: 2b00 cmp r3, #0 8004b12: f47f aea3 bne.w 800485c } } 8004b16: bf00 nop 8004b18: bf00 nop 8004b1a: 371c adds r7, #28 8004b1c: 46bd mov sp, r7 8004b1e: f85d 7b04 ldr.w r7, [sp], #4 8004b22: 4770 bx lr 8004b24: 40021000 .word 0x40021000 8004b28: 40010000 .word 0x40010000 8004b2c: 48000400 .word 0x48000400 8004b30: 48000800 .word 0x48000800 8004b34: 48000c00 .word 0x48000c00 8004b38: 48001000 .word 0x48001000 8004b3c: 40010400 .word 0x40010400 08004b40 : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 8004b40: b480 push {r7} 8004b42: b083 sub sp, #12 8004b44: af00 add r7, sp, #0 8004b46: 6078 str r0, [r7, #4] 8004b48: 460b mov r3, r1 8004b4a: 807b strh r3, [r7, #2] 8004b4c: 4613 mov r3, r2 8004b4e: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if(PinState != GPIO_PIN_RESET) 8004b50: 787b ldrb r3, [r7, #1] 8004b52: 2b00 cmp r3, #0 8004b54: d003 beq.n 8004b5e { GPIOx->BSRR = (uint32_t)GPIO_Pin; 8004b56: 887a ldrh r2, [r7, #2] 8004b58: 687b ldr r3, [r7, #4] 8004b5a: 619a str r2, [r3, #24] } else { GPIOx->BRR = (uint32_t)GPIO_Pin; } } 8004b5c: e002 b.n 8004b64 GPIOx->BRR = (uint32_t)GPIO_Pin; 8004b5e: 887a ldrh r2, [r7, #2] 8004b60: 687b ldr r3, [r7, #4] 8004b62: 629a str r2, [r3, #40] @ 0x28 } 8004b64: bf00 nop 8004b66: 370c adds r7, #12 8004b68: 46bd mov sp, r7 8004b6a: f85d 7b04 ldr.w r7, [sp], #4 8004b6e: 4770 bx lr 08004b70 : * supported by this macro. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 8004b70: b580 push {r7, lr} 8004b72: f5ad 7d00 sub.w sp, sp, #512 @ 0x200 8004b76: af00 add r7, sp, #0 8004b78: f507 7300 add.w r3, r7, #512 @ 0x200 8004b7c: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc 8004b80: 6018 str r0, [r3, #0] #if defined(RCC_CFGR_PLLSRC_HSI_PREDIV) uint32_t pll_config2; #endif /* RCC_CFGR_PLLSRC_HSI_PREDIV */ /* Check Null pointer */ if(RCC_OscInitStruct == NULL) 8004b82: f507 7300 add.w r3, r7, #512 @ 0x200 8004b86: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc 8004b8a: 681b ldr r3, [r3, #0] 8004b8c: 2b00 cmp r3, #0 8004b8e: d102 bne.n 8004b96 { return HAL_ERROR; 8004b90: 2301 movs r3, #1 8004b92: f001 b823 b.w 8005bdc /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 8004b96: f507 7300 add.w r3, r7, #512 @ 0x200 8004b9a: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc 8004b9e: 681b ldr r3, [r3, #0] 8004ba0: 681b ldr r3, [r3, #0] 8004ba2: f003 0301 and.w r3, r3, #1 8004ba6: 2b00 cmp r3, #0 8004ba8: f000 817d beq.w 8004ea6 { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) 8004bac: 4bbc ldr r3, [pc, #752] @ (8004ea0 ) 8004bae: 685b ldr r3, [r3, #4] 8004bb0: f003 030c and.w r3, r3, #12 8004bb4: 2b04 cmp r3, #4 8004bb6: d00c beq.n 8004bd2 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) 8004bb8: 4bb9 ldr r3, [pc, #740] @ (8004ea0 ) 8004bba: 685b ldr r3, [r3, #4] 8004bbc: f003 030c and.w r3, r3, #12 8004bc0: 2b08 cmp r3, #8 8004bc2: d15c bne.n 8004c7e 8004bc4: 4bb6 ldr r3, [pc, #728] @ (8004ea0 ) 8004bc6: 685b ldr r3, [r3, #4] 8004bc8: f403 3380 and.w r3, r3, #65536 @ 0x10000 8004bcc: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8004bd0: d155 bne.n 8004c7e 8004bd2: f44f 3300 mov.w r3, #131072 @ 0x20000 8004bd6: f8c7 31f0 str.w r3, [r7, #496] @ 0x1f0 uint32_t result; #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8004bda: f8d7 31f0 ldr.w r3, [r7, #496] @ 0x1f0 8004bde: fa93 f3a3 rbit r3, r3 8004be2: f8c7 31ec str.w r3, [r7, #492] @ 0x1ec result |= value & 1U; s--; } result <<= s; /* shift when v's highest bits are zero */ #endif return result; 8004be6: f8d7 31ec ldr.w r3, [r7, #492] @ 0x1ec { if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8004bea: fab3 f383 clz r3, r3 8004bee: b2db uxtb r3, r3 8004bf0: 095b lsrs r3, r3, #5 8004bf2: b2db uxtb r3, r3 8004bf4: f043 0301 orr.w r3, r3, #1 8004bf8: b2db uxtb r3, r3 8004bfa: 2b01 cmp r3, #1 8004bfc: d102 bne.n 8004c04 8004bfe: 4ba8 ldr r3, [pc, #672] @ (8004ea0 ) 8004c00: 681b ldr r3, [r3, #0] 8004c02: e015 b.n 8004c30 8004c04: f44f 3300 mov.w r3, #131072 @ 0x20000 8004c08: f8c7 31e8 str.w r3, [r7, #488] @ 0x1e8 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8004c0c: f8d7 31e8 ldr.w r3, [r7, #488] @ 0x1e8 8004c10: fa93 f3a3 rbit r3, r3 8004c14: f8c7 31e4 str.w r3, [r7, #484] @ 0x1e4 8004c18: f44f 3300 mov.w r3, #131072 @ 0x20000 8004c1c: f8c7 31e0 str.w r3, [r7, #480] @ 0x1e0 8004c20: f8d7 31e0 ldr.w r3, [r7, #480] @ 0x1e0 8004c24: fa93 f3a3 rbit r3, r3 8004c28: f8c7 31dc str.w r3, [r7, #476] @ 0x1dc 8004c2c: 4b9c ldr r3, [pc, #624] @ (8004ea0 ) 8004c2e: 6a5b ldr r3, [r3, #36] @ 0x24 8004c30: f44f 3200 mov.w r2, #131072 @ 0x20000 8004c34: f8c7 21d8 str.w r2, [r7, #472] @ 0x1d8 8004c38: f8d7 21d8 ldr.w r2, [r7, #472] @ 0x1d8 8004c3c: fa92 f2a2 rbit r2, r2 8004c40: f8c7 21d4 str.w r2, [r7, #468] @ 0x1d4 return result; 8004c44: f8d7 21d4 ldr.w r2, [r7, #468] @ 0x1d4 8004c48: fab2 f282 clz r2, r2 8004c4c: b2d2 uxtb r2, r2 8004c4e: f042 0220 orr.w r2, r2, #32 8004c52: b2d2 uxtb r2, r2 8004c54: f002 021f and.w r2, r2, #31 8004c58: 2101 movs r1, #1 8004c5a: fa01 f202 lsl.w r2, r1, r2 8004c5e: 4013 ands r3, r2 8004c60: 2b00 cmp r3, #0 8004c62: f000 811f beq.w 8004ea4 8004c66: f507 7300 add.w r3, r7, #512 @ 0x200 8004c6a: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc 8004c6e: 681b ldr r3, [r3, #0] 8004c70: 685b ldr r3, [r3, #4] 8004c72: 2b00 cmp r3, #0 8004c74: f040 8116 bne.w 8004ea4 { return HAL_ERROR; 8004c78: 2301 movs r3, #1 8004c7a: f000 bfaf b.w 8005bdc } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 8004c7e: f507 7300 add.w r3, r7, #512 @ 0x200 8004c82: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc 8004c86: 681b ldr r3, [r3, #0] 8004c88: 685b ldr r3, [r3, #4] 8004c8a: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8004c8e: d106 bne.n 8004c9e 8004c90: 4b83 ldr r3, [pc, #524] @ (8004ea0 ) 8004c92: 681b ldr r3, [r3, #0] 8004c94: 4a82 ldr r2, [pc, #520] @ (8004ea0 ) 8004c96: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8004c9a: 6013 str r3, [r2, #0] 8004c9c: e036 b.n 8004d0c 8004c9e: f507 7300 add.w r3, r7, #512 @ 0x200 8004ca2: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc 8004ca6: 681b ldr r3, [r3, #0] 8004ca8: 685b ldr r3, [r3, #4] 8004caa: 2b00 cmp r3, #0 8004cac: d10c bne.n 8004cc8 8004cae: 4b7c ldr r3, [pc, #496] @ (8004ea0 ) 8004cb0: 681b ldr r3, [r3, #0] 8004cb2: 4a7b ldr r2, [pc, #492] @ (8004ea0 ) 8004cb4: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8004cb8: 6013 str r3, [r2, #0] 8004cba: 4b79 ldr r3, [pc, #484] @ (8004ea0 ) 8004cbc: 681b ldr r3, [r3, #0] 8004cbe: 4a78 ldr r2, [pc, #480] @ (8004ea0 ) 8004cc0: f423 2380 bic.w r3, r3, #262144 @ 0x40000 8004cc4: 6013 str r3, [r2, #0] 8004cc6: e021 b.n 8004d0c 8004cc8: f507 7300 add.w r3, r7, #512 @ 0x200 8004ccc: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc 8004cd0: 681b ldr r3, [r3, #0] 8004cd2: 685b ldr r3, [r3, #4] 8004cd4: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 8004cd8: d10c bne.n 8004cf4 8004cda: 4b71 ldr r3, [pc, #452] @ (8004ea0 ) 8004cdc: 681b ldr r3, [r3, #0] 8004cde: 4a70 ldr r2, [pc, #448] @ (8004ea0 ) 8004ce0: f443 2380 orr.w r3, r3, #262144 @ 0x40000 8004ce4: 6013 str r3, [r2, #0] 8004ce6: 4b6e ldr r3, [pc, #440] @ (8004ea0 ) 8004ce8: 681b ldr r3, [r3, #0] 8004cea: 4a6d ldr r2, [pc, #436] @ (8004ea0 ) 8004cec: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8004cf0: 6013 str r3, [r2, #0] 8004cf2: e00b b.n 8004d0c 8004cf4: 4b6a ldr r3, [pc, #424] @ (8004ea0 ) 8004cf6: 681b ldr r3, [r3, #0] 8004cf8: 4a69 ldr r2, [pc, #420] @ (8004ea0 ) 8004cfa: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8004cfe: 6013 str r3, [r2, #0] 8004d00: 4b67 ldr r3, [pc, #412] @ (8004ea0 ) 8004d02: 681b ldr r3, [r3, #0] 8004d04: 4a66 ldr r2, [pc, #408] @ (8004ea0 ) 8004d06: f423 2380 bic.w r3, r3, #262144 @ 0x40000 8004d0a: 6013 str r3, [r2, #0] #if defined(RCC_CFGR_PLLSRC_HSI_DIV2) /* Configure the HSE predivision factor --------------------------------*/ __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue); 8004d0c: 4b64 ldr r3, [pc, #400] @ (8004ea0 ) 8004d0e: 6adb ldr r3, [r3, #44] @ 0x2c 8004d10: f023 020f bic.w r2, r3, #15 8004d14: f507 7300 add.w r3, r7, #512 @ 0x200 8004d18: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc 8004d1c: 681b ldr r3, [r3, #0] 8004d1e: 689b ldr r3, [r3, #8] 8004d20: 495f ldr r1, [pc, #380] @ (8004ea0 ) 8004d22: 4313 orrs r3, r2 8004d24: 62cb str r3, [r1, #44] @ 0x2c #endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */ /* Check the HSE State */ if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 8004d26: f507 7300 add.w r3, r7, #512 @ 0x200 8004d2a: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc 8004d2e: 681b ldr r3, [r3, #0] 8004d30: 685b ldr r3, [r3, #4] 8004d32: 2b00 cmp r3, #0 8004d34: d059 beq.n 8004dea { /* Get Start Tick */ tickstart = HAL_GetTick(); 8004d36: f7fd fae5 bl 8002304 8004d3a: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8 /* Wait till HSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8004d3e: e00a b.n 8004d56 { if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) 8004d40: f7fd fae0 bl 8002304 8004d44: 4602 mov r2, r0 8004d46: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8 8004d4a: 1ad3 subs r3, r2, r3 8004d4c: 2b64 cmp r3, #100 @ 0x64 8004d4e: d902 bls.n 8004d56 { return HAL_TIMEOUT; 8004d50: 2303 movs r3, #3 8004d52: f000 bf43 b.w 8005bdc 8004d56: f44f 3300 mov.w r3, #131072 @ 0x20000 8004d5a: f8c7 31d0 str.w r3, [r7, #464] @ 0x1d0 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8004d5e: f8d7 31d0 ldr.w r3, [r7, #464] @ 0x1d0 8004d62: fa93 f3a3 rbit r3, r3 8004d66: f8c7 31cc str.w r3, [r7, #460] @ 0x1cc return result; 8004d6a: f8d7 31cc ldr.w r3, [r7, #460] @ 0x1cc while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8004d6e: fab3 f383 clz r3, r3 8004d72: b2db uxtb r3, r3 8004d74: 095b lsrs r3, r3, #5 8004d76: b2db uxtb r3, r3 8004d78: f043 0301 orr.w r3, r3, #1 8004d7c: b2db uxtb r3, r3 8004d7e: 2b01 cmp r3, #1 8004d80: d102 bne.n 8004d88 8004d82: 4b47 ldr r3, [pc, #284] @ (8004ea0 ) 8004d84: 681b ldr r3, [r3, #0] 8004d86: e015 b.n 8004db4 8004d88: f44f 3300 mov.w r3, #131072 @ 0x20000 8004d8c: f8c7 31c8 str.w r3, [r7, #456] @ 0x1c8 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8004d90: f8d7 31c8 ldr.w r3, [r7, #456] @ 0x1c8 8004d94: fa93 f3a3 rbit r3, r3 8004d98: f8c7 31c4 str.w r3, [r7, #452] @ 0x1c4 8004d9c: f44f 3300 mov.w r3, #131072 @ 0x20000 8004da0: f8c7 31c0 str.w r3, [r7, #448] @ 0x1c0 8004da4: f8d7 31c0 ldr.w r3, [r7, #448] @ 0x1c0 8004da8: fa93 f3a3 rbit r3, r3 8004dac: f8c7 31bc str.w r3, [r7, #444] @ 0x1bc 8004db0: 4b3b ldr r3, [pc, #236] @ (8004ea0 ) 8004db2: 6a5b ldr r3, [r3, #36] @ 0x24 8004db4: f44f 3200 mov.w r2, #131072 @ 0x20000 8004db8: f8c7 21b8 str.w r2, [r7, #440] @ 0x1b8 8004dbc: f8d7 21b8 ldr.w r2, [r7, #440] @ 0x1b8 8004dc0: fa92 f2a2 rbit r2, r2 8004dc4: f8c7 21b4 str.w r2, [r7, #436] @ 0x1b4 return result; 8004dc8: f8d7 21b4 ldr.w r2, [r7, #436] @ 0x1b4 8004dcc: fab2 f282 clz r2, r2 8004dd0: b2d2 uxtb r2, r2 8004dd2: f042 0220 orr.w r2, r2, #32 8004dd6: b2d2 uxtb r2, r2 8004dd8: f002 021f and.w r2, r2, #31 8004ddc: 2101 movs r1, #1 8004dde: fa01 f202 lsl.w r2, r1, r2 8004de2: 4013 ands r3, r2 8004de4: 2b00 cmp r3, #0 8004de6: d0ab beq.n 8004d40 8004de8: e05d b.n 8004ea6 } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 8004dea: f7fd fa8b bl 8002304 8004dee: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8 /* Wait till HSE is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8004df2: e00a b.n 8004e0a { if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) 8004df4: f7fd fa86 bl 8002304 8004df8: 4602 mov r2, r0 8004dfa: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8 8004dfe: 1ad3 subs r3, r2, r3 8004e00: 2b64 cmp r3, #100 @ 0x64 8004e02: d902 bls.n 8004e0a { return HAL_TIMEOUT; 8004e04: 2303 movs r3, #3 8004e06: f000 bee9 b.w 8005bdc 8004e0a: f44f 3300 mov.w r3, #131072 @ 0x20000 8004e0e: f8c7 31b0 str.w r3, [r7, #432] @ 0x1b0 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8004e12: f8d7 31b0 ldr.w r3, [r7, #432] @ 0x1b0 8004e16: fa93 f3a3 rbit r3, r3 8004e1a: f8c7 31ac str.w r3, [r7, #428] @ 0x1ac return result; 8004e1e: f8d7 31ac ldr.w r3, [r7, #428] @ 0x1ac while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8004e22: fab3 f383 clz r3, r3 8004e26: b2db uxtb r3, r3 8004e28: 095b lsrs r3, r3, #5 8004e2a: b2db uxtb r3, r3 8004e2c: f043 0301 orr.w r3, r3, #1 8004e30: b2db uxtb r3, r3 8004e32: 2b01 cmp r3, #1 8004e34: d102 bne.n 8004e3c 8004e36: 4b1a ldr r3, [pc, #104] @ (8004ea0 ) 8004e38: 681b ldr r3, [r3, #0] 8004e3a: e015 b.n 8004e68 8004e3c: f44f 3300 mov.w r3, #131072 @ 0x20000 8004e40: f8c7 31a8 str.w r3, [r7, #424] @ 0x1a8 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8004e44: f8d7 31a8 ldr.w r3, [r7, #424] @ 0x1a8 8004e48: fa93 f3a3 rbit r3, r3 8004e4c: f8c7 31a4 str.w r3, [r7, #420] @ 0x1a4 8004e50: f44f 3300 mov.w r3, #131072 @ 0x20000 8004e54: f8c7 31a0 str.w r3, [r7, #416] @ 0x1a0 8004e58: f8d7 31a0 ldr.w r3, [r7, #416] @ 0x1a0 8004e5c: fa93 f3a3 rbit r3, r3 8004e60: f8c7 319c str.w r3, [r7, #412] @ 0x19c 8004e64: 4b0e ldr r3, [pc, #56] @ (8004ea0 ) 8004e66: 6a5b ldr r3, [r3, #36] @ 0x24 8004e68: f44f 3200 mov.w r2, #131072 @ 0x20000 8004e6c: f8c7 2198 str.w r2, [r7, #408] @ 0x198 8004e70: f8d7 2198 ldr.w r2, [r7, #408] @ 0x198 8004e74: fa92 f2a2 rbit r2, r2 8004e78: f8c7 2194 str.w r2, [r7, #404] @ 0x194 return result; 8004e7c: f8d7 2194 ldr.w r2, [r7, #404] @ 0x194 8004e80: fab2 f282 clz r2, r2 8004e84: b2d2 uxtb r2, r2 8004e86: f042 0220 orr.w r2, r2, #32 8004e8a: b2d2 uxtb r2, r2 8004e8c: f002 021f and.w r2, r2, #31 8004e90: 2101 movs r1, #1 8004e92: fa01 f202 lsl.w r2, r1, r2 8004e96: 4013 ands r3, r2 8004e98: 2b00 cmp r3, #0 8004e9a: d1ab bne.n 8004df4 8004e9c: e003 b.n 8004ea6 8004e9e: bf00 nop 8004ea0: 40021000 .word 0x40021000 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8004ea4: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 8004ea6: f507 7300 add.w r3, r7, #512 @ 0x200 8004eaa: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc 8004eae: 681b ldr r3, [r3, #0] 8004eb0: 681b ldr r3, [r3, #0] 8004eb2: f003 0302 and.w r3, r3, #2 8004eb6: 2b00 cmp r3, #0 8004eb8: f000 817d beq.w 80051b6 /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) 8004ebc: 4ba6 ldr r3, [pc, #664] @ (8005158 ) 8004ebe: 685b ldr r3, [r3, #4] 8004ec0: f003 030c and.w r3, r3, #12 8004ec4: 2b00 cmp r3, #0 8004ec6: d00b beq.n 8004ee0 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI))) 8004ec8: 4ba3 ldr r3, [pc, #652] @ (8005158 ) 8004eca: 685b ldr r3, [r3, #4] 8004ecc: f003 030c and.w r3, r3, #12 8004ed0: 2b08 cmp r3, #8 8004ed2: d172 bne.n 8004fba 8004ed4: 4ba0 ldr r3, [pc, #640] @ (8005158 ) 8004ed6: 685b ldr r3, [r3, #4] 8004ed8: f403 3380 and.w r3, r3, #65536 @ 0x10000 8004edc: 2b00 cmp r3, #0 8004ede: d16c bne.n 8004fba 8004ee0: 2302 movs r3, #2 8004ee2: f8c7 3190 str.w r3, [r7, #400] @ 0x190 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8004ee6: f8d7 3190 ldr.w r3, [r7, #400] @ 0x190 8004eea: fa93 f3a3 rbit r3, r3 8004eee: f8c7 318c str.w r3, [r7, #396] @ 0x18c return result; 8004ef2: f8d7 318c ldr.w r3, [r7, #396] @ 0x18c { /* When HSI is used as system clock it will not disabled */ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8004ef6: fab3 f383 clz r3, r3 8004efa: b2db uxtb r3, r3 8004efc: 095b lsrs r3, r3, #5 8004efe: b2db uxtb r3, r3 8004f00: f043 0301 orr.w r3, r3, #1 8004f04: b2db uxtb r3, r3 8004f06: 2b01 cmp r3, #1 8004f08: d102 bne.n 8004f10 8004f0a: 4b93 ldr r3, [pc, #588] @ (8005158 ) 8004f0c: 681b ldr r3, [r3, #0] 8004f0e: e013 b.n 8004f38 8004f10: 2302 movs r3, #2 8004f12: f8c7 3188 str.w r3, [r7, #392] @ 0x188 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8004f16: f8d7 3188 ldr.w r3, [r7, #392] @ 0x188 8004f1a: fa93 f3a3 rbit r3, r3 8004f1e: f8c7 3184 str.w r3, [r7, #388] @ 0x184 8004f22: 2302 movs r3, #2 8004f24: f8c7 3180 str.w r3, [r7, #384] @ 0x180 8004f28: f8d7 3180 ldr.w r3, [r7, #384] @ 0x180 8004f2c: fa93 f3a3 rbit r3, r3 8004f30: f8c7 317c str.w r3, [r7, #380] @ 0x17c 8004f34: 4b88 ldr r3, [pc, #544] @ (8005158 ) 8004f36: 6a5b ldr r3, [r3, #36] @ 0x24 8004f38: 2202 movs r2, #2 8004f3a: f8c7 2178 str.w r2, [r7, #376] @ 0x178 8004f3e: f8d7 2178 ldr.w r2, [r7, #376] @ 0x178 8004f42: fa92 f2a2 rbit r2, r2 8004f46: f8c7 2174 str.w r2, [r7, #372] @ 0x174 return result; 8004f4a: f8d7 2174 ldr.w r2, [r7, #372] @ 0x174 8004f4e: fab2 f282 clz r2, r2 8004f52: b2d2 uxtb r2, r2 8004f54: f042 0220 orr.w r2, r2, #32 8004f58: b2d2 uxtb r2, r2 8004f5a: f002 021f and.w r2, r2, #31 8004f5e: 2101 movs r1, #1 8004f60: fa01 f202 lsl.w r2, r1, r2 8004f64: 4013 ands r3, r2 8004f66: 2b00 cmp r3, #0 8004f68: d00a beq.n 8004f80 8004f6a: f507 7300 add.w r3, r7, #512 @ 0x200 8004f6e: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc 8004f72: 681b ldr r3, [r3, #0] 8004f74: 691b ldr r3, [r3, #16] 8004f76: 2b01 cmp r3, #1 8004f78: d002 beq.n 8004f80 { return HAL_ERROR; 8004f7a: 2301 movs r3, #1 8004f7c: f000 be2e b.w 8005bdc } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8004f80: 4b75 ldr r3, [pc, #468] @ (8005158 ) 8004f82: 681b ldr r3, [r3, #0] 8004f84: f023 02f8 bic.w r2, r3, #248 @ 0xf8 8004f88: f507 7300 add.w r3, r7, #512 @ 0x200 8004f8c: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc 8004f90: 681b ldr r3, [r3, #0] 8004f92: 695b ldr r3, [r3, #20] 8004f94: 21f8 movs r1, #248 @ 0xf8 8004f96: f8c7 1170 str.w r1, [r7, #368] @ 0x170 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8004f9a: f8d7 1170 ldr.w r1, [r7, #368] @ 0x170 8004f9e: fa91 f1a1 rbit r1, r1 8004fa2: f8c7 116c str.w r1, [r7, #364] @ 0x16c return result; 8004fa6: f8d7 116c ldr.w r1, [r7, #364] @ 0x16c 8004faa: fab1 f181 clz r1, r1 8004fae: b2c9 uxtb r1, r1 8004fb0: 408b lsls r3, r1 8004fb2: 4969 ldr r1, [pc, #420] @ (8005158 ) 8004fb4: 4313 orrs r3, r2 8004fb6: 600b str r3, [r1, #0] if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8004fb8: e0fd b.n 80051b6 } } else { /* Check the HSI State */ if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF) 8004fba: f507 7300 add.w r3, r7, #512 @ 0x200 8004fbe: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc 8004fc2: 681b ldr r3, [r3, #0] 8004fc4: 691b ldr r3, [r3, #16] 8004fc6: 2b00 cmp r3, #0 8004fc8: f000 8088 beq.w 80050dc 8004fcc: 2301 movs r3, #1 8004fce: f8c7 3168 str.w r3, [r7, #360] @ 0x168 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8004fd2: f8d7 3168 ldr.w r3, [r7, #360] @ 0x168 8004fd6: fa93 f3a3 rbit r3, r3 8004fda: f8c7 3164 str.w r3, [r7, #356] @ 0x164 return result; 8004fde: f8d7 3164 ldr.w r3, [r7, #356] @ 0x164 { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 8004fe2: fab3 f383 clz r3, r3 8004fe6: b2db uxtb r3, r3 8004fe8: f103 5384 add.w r3, r3, #276824064 @ 0x10800000 8004fec: f503 1384 add.w r3, r3, #1081344 @ 0x108000 8004ff0: 009b lsls r3, r3, #2 8004ff2: 461a mov r2, r3 8004ff4: 2301 movs r3, #1 8004ff6: 6013 str r3, [r2, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8004ff8: f7fd f984 bl 8002304 8004ffc: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8 /* Wait till HSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8005000: e00a b.n 8005018 { if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) 8005002: f7fd f97f bl 8002304 8005006: 4602 mov r2, r0 8005008: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8 800500c: 1ad3 subs r3, r2, r3 800500e: 2b02 cmp r3, #2 8005010: d902 bls.n 8005018 { return HAL_TIMEOUT; 8005012: 2303 movs r3, #3 8005014: f000 bde2 b.w 8005bdc 8005018: 2302 movs r3, #2 800501a: f8c7 3160 str.w r3, [r7, #352] @ 0x160 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 800501e: f8d7 3160 ldr.w r3, [r7, #352] @ 0x160 8005022: fa93 f3a3 rbit r3, r3 8005026: f8c7 315c str.w r3, [r7, #348] @ 0x15c return result; 800502a: f8d7 315c ldr.w r3, [r7, #348] @ 0x15c while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 800502e: fab3 f383 clz r3, r3 8005032: b2db uxtb r3, r3 8005034: 095b lsrs r3, r3, #5 8005036: b2db uxtb r3, r3 8005038: f043 0301 orr.w r3, r3, #1 800503c: b2db uxtb r3, r3 800503e: 2b01 cmp r3, #1 8005040: d102 bne.n 8005048 8005042: 4b45 ldr r3, [pc, #276] @ (8005158 ) 8005044: 681b ldr r3, [r3, #0] 8005046: e013 b.n 8005070 8005048: 2302 movs r3, #2 800504a: f8c7 3158 str.w r3, [r7, #344] @ 0x158 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 800504e: f8d7 3158 ldr.w r3, [r7, #344] @ 0x158 8005052: fa93 f3a3 rbit r3, r3 8005056: f8c7 3154 str.w r3, [r7, #340] @ 0x154 800505a: 2302 movs r3, #2 800505c: f8c7 3150 str.w r3, [r7, #336] @ 0x150 8005060: f8d7 3150 ldr.w r3, [r7, #336] @ 0x150 8005064: fa93 f3a3 rbit r3, r3 8005068: f8c7 314c str.w r3, [r7, #332] @ 0x14c 800506c: 4b3a ldr r3, [pc, #232] @ (8005158 ) 800506e: 6a5b ldr r3, [r3, #36] @ 0x24 8005070: 2202 movs r2, #2 8005072: f8c7 2148 str.w r2, [r7, #328] @ 0x148 8005076: f8d7 2148 ldr.w r2, [r7, #328] @ 0x148 800507a: fa92 f2a2 rbit r2, r2 800507e: f8c7 2144 str.w r2, [r7, #324] @ 0x144 return result; 8005082: f8d7 2144 ldr.w r2, [r7, #324] @ 0x144 8005086: fab2 f282 clz r2, r2 800508a: b2d2 uxtb r2, r2 800508c: f042 0220 orr.w r2, r2, #32 8005090: b2d2 uxtb r2, r2 8005092: f002 021f and.w r2, r2, #31 8005096: 2101 movs r1, #1 8005098: fa01 f202 lsl.w r2, r1, r2 800509c: 4013 ands r3, r2 800509e: 2b00 cmp r3, #0 80050a0: d0af beq.n 8005002 } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 80050a2: 4b2d ldr r3, [pc, #180] @ (8005158 ) 80050a4: 681b ldr r3, [r3, #0] 80050a6: f023 02f8 bic.w r2, r3, #248 @ 0xf8 80050aa: f507 7300 add.w r3, r7, #512 @ 0x200 80050ae: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc 80050b2: 681b ldr r3, [r3, #0] 80050b4: 695b ldr r3, [r3, #20] 80050b6: 21f8 movs r1, #248 @ 0xf8 80050b8: f8c7 1140 str.w r1, [r7, #320] @ 0x140 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 80050bc: f8d7 1140 ldr.w r1, [r7, #320] @ 0x140 80050c0: fa91 f1a1 rbit r1, r1 80050c4: f8c7 113c str.w r1, [r7, #316] @ 0x13c return result; 80050c8: f8d7 113c ldr.w r1, [r7, #316] @ 0x13c 80050cc: fab1 f181 clz r1, r1 80050d0: b2c9 uxtb r1, r1 80050d2: 408b lsls r3, r1 80050d4: 4920 ldr r1, [pc, #128] @ (8005158 ) 80050d6: 4313 orrs r3, r2 80050d8: 600b str r3, [r1, #0] 80050da: e06c b.n 80051b6 80050dc: 2301 movs r3, #1 80050de: f8c7 3138 str.w r3, [r7, #312] @ 0x138 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 80050e2: f8d7 3138 ldr.w r3, [r7, #312] @ 0x138 80050e6: fa93 f3a3 rbit r3, r3 80050ea: f8c7 3134 str.w r3, [r7, #308] @ 0x134 return result; 80050ee: f8d7 3134 ldr.w r3, [r7, #308] @ 0x134 } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 80050f2: fab3 f383 clz r3, r3 80050f6: b2db uxtb r3, r3 80050f8: f103 5384 add.w r3, r3, #276824064 @ 0x10800000 80050fc: f503 1384 add.w r3, r3, #1081344 @ 0x108000 8005100: 009b lsls r3, r3, #2 8005102: 461a mov r2, r3 8005104: 2300 movs r3, #0 8005106: 6013 str r3, [r2, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8005108: f7fd f8fc bl 8002304 800510c: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8 /* Wait till HSI is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8005110: e00a b.n 8005128 { if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) 8005112: f7fd f8f7 bl 8002304 8005116: 4602 mov r2, r0 8005118: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8 800511c: 1ad3 subs r3, r2, r3 800511e: 2b02 cmp r3, #2 8005120: d902 bls.n 8005128 { return HAL_TIMEOUT; 8005122: 2303 movs r3, #3 8005124: f000 bd5a b.w 8005bdc 8005128: 2302 movs r3, #2 800512a: f8c7 3130 str.w r3, [r7, #304] @ 0x130 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 800512e: f8d7 3130 ldr.w r3, [r7, #304] @ 0x130 8005132: fa93 f3a3 rbit r3, r3 8005136: f8c7 312c str.w r3, [r7, #300] @ 0x12c return result; 800513a: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 800513e: fab3 f383 clz r3, r3 8005142: b2db uxtb r3, r3 8005144: 095b lsrs r3, r3, #5 8005146: b2db uxtb r3, r3 8005148: f043 0301 orr.w r3, r3, #1 800514c: b2db uxtb r3, r3 800514e: 2b01 cmp r3, #1 8005150: d104 bne.n 800515c 8005152: 4b01 ldr r3, [pc, #4] @ (8005158 ) 8005154: 681b ldr r3, [r3, #0] 8005156: e015 b.n 8005184 8005158: 40021000 .word 0x40021000 800515c: 2302 movs r3, #2 800515e: f8c7 3128 str.w r3, [r7, #296] @ 0x128 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8005162: f8d7 3128 ldr.w r3, [r7, #296] @ 0x128 8005166: fa93 f3a3 rbit r3, r3 800516a: f8c7 3124 str.w r3, [r7, #292] @ 0x124 800516e: 2302 movs r3, #2 8005170: f8c7 3120 str.w r3, [r7, #288] @ 0x120 8005174: f8d7 3120 ldr.w r3, [r7, #288] @ 0x120 8005178: fa93 f3a3 rbit r3, r3 800517c: f8c7 311c str.w r3, [r7, #284] @ 0x11c 8005180: 4bc8 ldr r3, [pc, #800] @ (80054a4 ) 8005182: 6a5b ldr r3, [r3, #36] @ 0x24 8005184: 2202 movs r2, #2 8005186: f8c7 2118 str.w r2, [r7, #280] @ 0x118 800518a: f8d7 2118 ldr.w r2, [r7, #280] @ 0x118 800518e: fa92 f2a2 rbit r2, r2 8005192: f8c7 2114 str.w r2, [r7, #276] @ 0x114 return result; 8005196: f8d7 2114 ldr.w r2, [r7, #276] @ 0x114 800519a: fab2 f282 clz r2, r2 800519e: b2d2 uxtb r2, r2 80051a0: f042 0220 orr.w r2, r2, #32 80051a4: b2d2 uxtb r2, r2 80051a6: f002 021f and.w r2, r2, #31 80051aa: 2101 movs r1, #1 80051ac: fa01 f202 lsl.w r2, r1, r2 80051b0: 4013 ands r3, r2 80051b2: 2b00 cmp r3, #0 80051b4: d1ad bne.n 8005112 } } } } /*------------------------------ LSI Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 80051b6: f507 7300 add.w r3, r7, #512 @ 0x200 80051ba: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc 80051be: 681b ldr r3, [r3, #0] 80051c0: 681b ldr r3, [r3, #0] 80051c2: f003 0308 and.w r3, r3, #8 80051c6: 2b00 cmp r3, #0 80051c8: f000 8110 beq.w 80053ec { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) 80051cc: f507 7300 add.w r3, r7, #512 @ 0x200 80051d0: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc 80051d4: 681b ldr r3, [r3, #0] 80051d6: 699b ldr r3, [r3, #24] 80051d8: 2b00 cmp r3, #0 80051da: d079 beq.n 80052d0 80051dc: 2301 movs r3, #1 80051de: f8c7 3110 str.w r3, [r7, #272] @ 0x110 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 80051e2: f8d7 3110 ldr.w r3, [r7, #272] @ 0x110 80051e6: fa93 f3a3 rbit r3, r3 80051ea: f8c7 310c str.w r3, [r7, #268] @ 0x10c return result; 80051ee: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 80051f2: fab3 f383 clz r3, r3 80051f6: b2db uxtb r3, r3 80051f8: 461a mov r2, r3 80051fa: 4bab ldr r3, [pc, #684] @ (80054a8 ) 80051fc: 4413 add r3, r2 80051fe: 009b lsls r3, r3, #2 8005200: 461a mov r2, r3 8005202: 2301 movs r3, #1 8005204: 6013 str r3, [r2, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8005206: f7fd f87d bl 8002304 800520a: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8 /* Wait till LSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 800520e: e00a b.n 8005226 { if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) 8005210: f7fd f878 bl 8002304 8005214: 4602 mov r2, r0 8005216: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8 800521a: 1ad3 subs r3, r2, r3 800521c: 2b02 cmp r3, #2 800521e: d902 bls.n 8005226 { return HAL_TIMEOUT; 8005220: 2303 movs r3, #3 8005222: f000 bcdb b.w 8005bdc 8005226: 2302 movs r3, #2 8005228: f8c7 3108 str.w r3, [r7, #264] @ 0x108 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 800522c: f8d7 3108 ldr.w r3, [r7, #264] @ 0x108 8005230: fa93 f3a3 rbit r3, r3 8005234: f8c7 3104 str.w r3, [r7, #260] @ 0x104 8005238: f507 7300 add.w r3, r7, #512 @ 0x200 800523c: f5a3 7380 sub.w r3, r3, #256 @ 0x100 8005240: 2202 movs r2, #2 8005242: 601a str r2, [r3, #0] 8005244: f507 7300 add.w r3, r7, #512 @ 0x200 8005248: f5a3 7380 sub.w r3, r3, #256 @ 0x100 800524c: 681b ldr r3, [r3, #0] 800524e: fa93 f2a3 rbit r2, r3 8005252: f507 7300 add.w r3, r7, #512 @ 0x200 8005256: f5a3 7382 sub.w r3, r3, #260 @ 0x104 800525a: 601a str r2, [r3, #0] 800525c: f507 7300 add.w r3, r7, #512 @ 0x200 8005260: f5a3 7384 sub.w r3, r3, #264 @ 0x108 8005264: 2202 movs r2, #2 8005266: 601a str r2, [r3, #0] 8005268: f507 7300 add.w r3, r7, #512 @ 0x200 800526c: f5a3 7384 sub.w r3, r3, #264 @ 0x108 8005270: 681b ldr r3, [r3, #0] 8005272: fa93 f2a3 rbit r2, r3 8005276: f507 7300 add.w r3, r7, #512 @ 0x200 800527a: f5a3 7386 sub.w r3, r3, #268 @ 0x10c 800527e: 601a str r2, [r3, #0] while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8005280: 4b88 ldr r3, [pc, #544] @ (80054a4 ) 8005282: 6a5a ldr r2, [r3, #36] @ 0x24 8005284: f507 7300 add.w r3, r7, #512 @ 0x200 8005288: f5a3 7388 sub.w r3, r3, #272 @ 0x110 800528c: 2102 movs r1, #2 800528e: 6019 str r1, [r3, #0] 8005290: f507 7300 add.w r3, r7, #512 @ 0x200 8005294: f5a3 7388 sub.w r3, r3, #272 @ 0x110 8005298: 681b ldr r3, [r3, #0] 800529a: fa93 f1a3 rbit r1, r3 800529e: f507 7300 add.w r3, r7, #512 @ 0x200 80052a2: f5a3 738a sub.w r3, r3, #276 @ 0x114 80052a6: 6019 str r1, [r3, #0] return result; 80052a8: f507 7300 add.w r3, r7, #512 @ 0x200 80052ac: f5a3 738a sub.w r3, r3, #276 @ 0x114 80052b0: 681b ldr r3, [r3, #0] 80052b2: fab3 f383 clz r3, r3 80052b6: b2db uxtb r3, r3 80052b8: f043 0360 orr.w r3, r3, #96 @ 0x60 80052bc: b2db uxtb r3, r3 80052be: f003 031f and.w r3, r3, #31 80052c2: 2101 movs r1, #1 80052c4: fa01 f303 lsl.w r3, r1, r3 80052c8: 4013 ands r3, r2 80052ca: 2b00 cmp r3, #0 80052cc: d0a0 beq.n 8005210 80052ce: e08d b.n 80053ec 80052d0: f507 7300 add.w r3, r7, #512 @ 0x200 80052d4: f5a3 738c sub.w r3, r3, #280 @ 0x118 80052d8: 2201 movs r2, #1 80052da: 601a str r2, [r3, #0] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 80052dc: f507 7300 add.w r3, r7, #512 @ 0x200 80052e0: f5a3 738c sub.w r3, r3, #280 @ 0x118 80052e4: 681b ldr r3, [r3, #0] 80052e6: fa93 f2a3 rbit r2, r3 80052ea: f507 7300 add.w r3, r7, #512 @ 0x200 80052ee: f5a3 738e sub.w r3, r3, #284 @ 0x11c 80052f2: 601a str r2, [r3, #0] return result; 80052f4: f507 7300 add.w r3, r7, #512 @ 0x200 80052f8: f5a3 738e sub.w r3, r3, #284 @ 0x11c 80052fc: 681b ldr r3, [r3, #0] } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 80052fe: fab3 f383 clz r3, r3 8005302: b2db uxtb r3, r3 8005304: 461a mov r2, r3 8005306: 4b68 ldr r3, [pc, #416] @ (80054a8 ) 8005308: 4413 add r3, r2 800530a: 009b lsls r3, r3, #2 800530c: 461a mov r2, r3 800530e: 2300 movs r3, #0 8005310: 6013 str r3, [r2, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8005312: f7fc fff7 bl 8002304 8005316: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8 /* Wait till LSI is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 800531a: e00a b.n 8005332 { if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) 800531c: f7fc fff2 bl 8002304 8005320: 4602 mov r2, r0 8005322: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8 8005326: 1ad3 subs r3, r2, r3 8005328: 2b02 cmp r3, #2 800532a: d902 bls.n 8005332 { return HAL_TIMEOUT; 800532c: 2303 movs r3, #3 800532e: f000 bc55 b.w 8005bdc 8005332: f507 7300 add.w r3, r7, #512 @ 0x200 8005336: f5a3 7390 sub.w r3, r3, #288 @ 0x120 800533a: 2202 movs r2, #2 800533c: 601a str r2, [r3, #0] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 800533e: f507 7300 add.w r3, r7, #512 @ 0x200 8005342: f5a3 7390 sub.w r3, r3, #288 @ 0x120 8005346: 681b ldr r3, [r3, #0] 8005348: fa93 f2a3 rbit r2, r3 800534c: f507 7300 add.w r3, r7, #512 @ 0x200 8005350: f5a3 7392 sub.w r3, r3, #292 @ 0x124 8005354: 601a str r2, [r3, #0] 8005356: f507 7300 add.w r3, r7, #512 @ 0x200 800535a: f5a3 7394 sub.w r3, r3, #296 @ 0x128 800535e: 2202 movs r2, #2 8005360: 601a str r2, [r3, #0] 8005362: f507 7300 add.w r3, r7, #512 @ 0x200 8005366: f5a3 7394 sub.w r3, r3, #296 @ 0x128 800536a: 681b ldr r3, [r3, #0] 800536c: fa93 f2a3 rbit r2, r3 8005370: f507 7300 add.w r3, r7, #512 @ 0x200 8005374: f5a3 7396 sub.w r3, r3, #300 @ 0x12c 8005378: 601a str r2, [r3, #0] 800537a: f507 7300 add.w r3, r7, #512 @ 0x200 800537e: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8005382: 2202 movs r2, #2 8005384: 601a str r2, [r3, #0] 8005386: f507 7300 add.w r3, r7, #512 @ 0x200 800538a: f5a3 7398 sub.w r3, r3, #304 @ 0x130 800538e: 681b ldr r3, [r3, #0] 8005390: fa93 f2a3 rbit r2, r3 8005394: f507 7300 add.w r3, r7, #512 @ 0x200 8005398: f5a3 739a sub.w r3, r3, #308 @ 0x134 800539c: 601a str r2, [r3, #0] while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 800539e: 4b41 ldr r3, [pc, #260] @ (80054a4 ) 80053a0: 6a5a ldr r2, [r3, #36] @ 0x24 80053a2: f507 7300 add.w r3, r7, #512 @ 0x200 80053a6: f5a3 739c sub.w r3, r3, #312 @ 0x138 80053aa: 2102 movs r1, #2 80053ac: 6019 str r1, [r3, #0] 80053ae: f507 7300 add.w r3, r7, #512 @ 0x200 80053b2: f5a3 739c sub.w r3, r3, #312 @ 0x138 80053b6: 681b ldr r3, [r3, #0] 80053b8: fa93 f1a3 rbit r1, r3 80053bc: f507 7300 add.w r3, r7, #512 @ 0x200 80053c0: f5a3 739e sub.w r3, r3, #316 @ 0x13c 80053c4: 6019 str r1, [r3, #0] return result; 80053c6: f507 7300 add.w r3, r7, #512 @ 0x200 80053ca: f5a3 739e sub.w r3, r3, #316 @ 0x13c 80053ce: 681b ldr r3, [r3, #0] 80053d0: fab3 f383 clz r3, r3 80053d4: b2db uxtb r3, r3 80053d6: f043 0360 orr.w r3, r3, #96 @ 0x60 80053da: b2db uxtb r3, r3 80053dc: f003 031f and.w r3, r3, #31 80053e0: 2101 movs r1, #1 80053e2: fa01 f303 lsl.w r3, r1, r3 80053e6: 4013 ands r3, r2 80053e8: 2b00 cmp r3, #0 80053ea: d197 bne.n 800531c } } } } /*------------------------------ LSE Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 80053ec: f507 7300 add.w r3, r7, #512 @ 0x200 80053f0: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc 80053f4: 681b ldr r3, [r3, #0] 80053f6: 681b ldr r3, [r3, #0] 80053f8: f003 0304 and.w r3, r3, #4 80053fc: 2b00 cmp r3, #0 80053fe: f000 81a1 beq.w 8005744 { FlagStatus pwrclkchanged = RESET; 8005402: 2300 movs r3, #0 8005404: f887 31ff strb.w r3, [r7, #511] @ 0x1ff /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if(__HAL_RCC_PWR_IS_CLK_DISABLED()) 8005408: 4b26 ldr r3, [pc, #152] @ (80054a4 ) 800540a: 69db ldr r3, [r3, #28] 800540c: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8005410: 2b00 cmp r3, #0 8005412: d116 bne.n 8005442 { __HAL_RCC_PWR_CLK_ENABLE(); 8005414: 4b23 ldr r3, [pc, #140] @ (80054a4 ) 8005416: 69db ldr r3, [r3, #28] 8005418: 4a22 ldr r2, [pc, #136] @ (80054a4 ) 800541a: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 800541e: 61d3 str r3, [r2, #28] 8005420: 4b20 ldr r3, [pc, #128] @ (80054a4 ) 8005422: 69db ldr r3, [r3, #28] 8005424: f003 5280 and.w r2, r3, #268435456 @ 0x10000000 8005428: f507 7300 add.w r3, r7, #512 @ 0x200 800542c: f5a3 73fc sub.w r3, r3, #504 @ 0x1f8 8005430: 601a str r2, [r3, #0] 8005432: f507 7300 add.w r3, r7, #512 @ 0x200 8005436: f5a3 73fc sub.w r3, r3, #504 @ 0x1f8 800543a: 681b ldr r3, [r3, #0] pwrclkchanged = SET; 800543c: 2301 movs r3, #1 800543e: f887 31ff strb.w r3, [r7, #511] @ 0x1ff } if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8005442: 4b1a ldr r3, [pc, #104] @ (80054ac ) 8005444: 681b ldr r3, [r3, #0] 8005446: f403 7380 and.w r3, r3, #256 @ 0x100 800544a: 2b00 cmp r3, #0 800544c: d11a bne.n 8005484 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 800544e: 4b17 ldr r3, [pc, #92] @ (80054ac ) 8005450: 681b ldr r3, [r3, #0] 8005452: 4a16 ldr r2, [pc, #88] @ (80054ac ) 8005454: f443 7380 orr.w r3, r3, #256 @ 0x100 8005458: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 800545a: f7fc ff53 bl 8002304 800545e: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8 while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8005462: e009 b.n 8005478 { if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8005464: f7fc ff4e bl 8002304 8005468: 4602 mov r2, r0 800546a: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8 800546e: 1ad3 subs r3, r2, r3 8005470: 2b64 cmp r3, #100 @ 0x64 8005472: d901 bls.n 8005478 { return HAL_TIMEOUT; 8005474: 2303 movs r3, #3 8005476: e3b1 b.n 8005bdc while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8005478: 4b0c ldr r3, [pc, #48] @ (80054ac ) 800547a: 681b ldr r3, [r3, #0] 800547c: f403 7380 and.w r3, r3, #256 @ 0x100 8005480: 2b00 cmp r3, #0 8005482: d0ef beq.n 8005464 } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8005484: f507 7300 add.w r3, r7, #512 @ 0x200 8005488: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc 800548c: 681b ldr r3, [r3, #0] 800548e: 68db ldr r3, [r3, #12] 8005490: 2b01 cmp r3, #1 8005492: d10d bne.n 80054b0 8005494: 4b03 ldr r3, [pc, #12] @ (80054a4 ) 8005496: 6a1b ldr r3, [r3, #32] 8005498: 4a02 ldr r2, [pc, #8] @ (80054a4 ) 800549a: f043 0301 orr.w r3, r3, #1 800549e: 6213 str r3, [r2, #32] 80054a0: e03c b.n 800551c 80054a2: bf00 nop 80054a4: 40021000 .word 0x40021000 80054a8: 10908120 .word 0x10908120 80054ac: 40007000 .word 0x40007000 80054b0: f507 7300 add.w r3, r7, #512 @ 0x200 80054b4: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc 80054b8: 681b ldr r3, [r3, #0] 80054ba: 68db ldr r3, [r3, #12] 80054bc: 2b00 cmp r3, #0 80054be: d10c bne.n 80054da 80054c0: 4bc1 ldr r3, [pc, #772] @ (80057c8 ) 80054c2: 6a1b ldr r3, [r3, #32] 80054c4: 4ac0 ldr r2, [pc, #768] @ (80057c8 ) 80054c6: f023 0301 bic.w r3, r3, #1 80054ca: 6213 str r3, [r2, #32] 80054cc: 4bbe ldr r3, [pc, #760] @ (80057c8 ) 80054ce: 6a1b ldr r3, [r3, #32] 80054d0: 4abd ldr r2, [pc, #756] @ (80057c8 ) 80054d2: f023 0304 bic.w r3, r3, #4 80054d6: 6213 str r3, [r2, #32] 80054d8: e020 b.n 800551c 80054da: f507 7300 add.w r3, r7, #512 @ 0x200 80054de: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc 80054e2: 681b ldr r3, [r3, #0] 80054e4: 68db ldr r3, [r3, #12] 80054e6: 2b05 cmp r3, #5 80054e8: d10c bne.n 8005504 80054ea: 4bb7 ldr r3, [pc, #732] @ (80057c8 ) 80054ec: 6a1b ldr r3, [r3, #32] 80054ee: 4ab6 ldr r2, [pc, #728] @ (80057c8 ) 80054f0: f043 0304 orr.w r3, r3, #4 80054f4: 6213 str r3, [r2, #32] 80054f6: 4bb4 ldr r3, [pc, #720] @ (80057c8 ) 80054f8: 6a1b ldr r3, [r3, #32] 80054fa: 4ab3 ldr r2, [pc, #716] @ (80057c8 ) 80054fc: f043 0301 orr.w r3, r3, #1 8005500: 6213 str r3, [r2, #32] 8005502: e00b b.n 800551c 8005504: 4bb0 ldr r3, [pc, #704] @ (80057c8 ) 8005506: 6a1b ldr r3, [r3, #32] 8005508: 4aaf ldr r2, [pc, #700] @ (80057c8 ) 800550a: f023 0301 bic.w r3, r3, #1 800550e: 6213 str r3, [r2, #32] 8005510: 4bad ldr r3, [pc, #692] @ (80057c8 ) 8005512: 6a1b ldr r3, [r3, #32] 8005514: 4aac ldr r2, [pc, #688] @ (80057c8 ) 8005516: f023 0304 bic.w r3, r3, #4 800551a: 6213 str r3, [r2, #32] /* Check the LSE State */ if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF) 800551c: f507 7300 add.w r3, r7, #512 @ 0x200 8005520: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc 8005524: 681b ldr r3, [r3, #0] 8005526: 68db ldr r3, [r3, #12] 8005528: 2b00 cmp r3, #0 800552a: f000 8081 beq.w 8005630 { /* Get Start Tick */ tickstart = HAL_GetTick(); 800552e: f7fc fee9 bl 8002304 8005532: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8 /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8005536: e00b b.n 8005550 { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) 8005538: f7fc fee4 bl 8002304 800553c: 4602 mov r2, r0 800553e: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8 8005542: 1ad3 subs r3, r2, r3 8005544: f241 3288 movw r2, #5000 @ 0x1388 8005548: 4293 cmp r3, r2 800554a: d901 bls.n 8005550 { return HAL_TIMEOUT; 800554c: 2303 movs r3, #3 800554e: e345 b.n 8005bdc 8005550: f507 7300 add.w r3, r7, #512 @ 0x200 8005554: f5a3 73a0 sub.w r3, r3, #320 @ 0x140 8005558: 2202 movs r2, #2 800555a: 601a str r2, [r3, #0] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 800555c: f507 7300 add.w r3, r7, #512 @ 0x200 8005560: f5a3 73a0 sub.w r3, r3, #320 @ 0x140 8005564: 681b ldr r3, [r3, #0] 8005566: fa93 f2a3 rbit r2, r3 800556a: f507 7300 add.w r3, r7, #512 @ 0x200 800556e: f5a3 73a2 sub.w r3, r3, #324 @ 0x144 8005572: 601a str r2, [r3, #0] 8005574: f507 7300 add.w r3, r7, #512 @ 0x200 8005578: f5a3 73a4 sub.w r3, r3, #328 @ 0x148 800557c: 2202 movs r2, #2 800557e: 601a str r2, [r3, #0] 8005580: f507 7300 add.w r3, r7, #512 @ 0x200 8005584: f5a3 73a4 sub.w r3, r3, #328 @ 0x148 8005588: 681b ldr r3, [r3, #0] 800558a: fa93 f2a3 rbit r2, r3 800558e: f507 7300 add.w r3, r7, #512 @ 0x200 8005592: f5a3 73a6 sub.w r3, r3, #332 @ 0x14c 8005596: 601a str r2, [r3, #0] return result; 8005598: f507 7300 add.w r3, r7, #512 @ 0x200 800559c: f5a3 73a6 sub.w r3, r3, #332 @ 0x14c 80055a0: 681b ldr r3, [r3, #0] while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 80055a2: fab3 f383 clz r3, r3 80055a6: b2db uxtb r3, r3 80055a8: 095b lsrs r3, r3, #5 80055aa: b2db uxtb r3, r3 80055ac: f043 0302 orr.w r3, r3, #2 80055b0: b2db uxtb r3, r3 80055b2: 2b02 cmp r3, #2 80055b4: d102 bne.n 80055bc 80055b6: 4b84 ldr r3, [pc, #528] @ (80057c8 ) 80055b8: 6a1b ldr r3, [r3, #32] 80055ba: e013 b.n 80055e4 80055bc: f507 7300 add.w r3, r7, #512 @ 0x200 80055c0: f5a3 73a8 sub.w r3, r3, #336 @ 0x150 80055c4: 2202 movs r2, #2 80055c6: 601a str r2, [r3, #0] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 80055c8: f507 7300 add.w r3, r7, #512 @ 0x200 80055cc: f5a3 73a8 sub.w r3, r3, #336 @ 0x150 80055d0: 681b ldr r3, [r3, #0] 80055d2: fa93 f2a3 rbit r2, r3 80055d6: f507 7300 add.w r3, r7, #512 @ 0x200 80055da: f5a3 73aa sub.w r3, r3, #340 @ 0x154 80055de: 601a str r2, [r3, #0] 80055e0: 4b79 ldr r3, [pc, #484] @ (80057c8 ) 80055e2: 6a5b ldr r3, [r3, #36] @ 0x24 80055e4: f507 7200 add.w r2, r7, #512 @ 0x200 80055e8: f5a2 72ac sub.w r2, r2, #344 @ 0x158 80055ec: 2102 movs r1, #2 80055ee: 6011 str r1, [r2, #0] 80055f0: f507 7200 add.w r2, r7, #512 @ 0x200 80055f4: f5a2 72ac sub.w r2, r2, #344 @ 0x158 80055f8: 6812 ldr r2, [r2, #0] 80055fa: fa92 f1a2 rbit r1, r2 80055fe: f507 7200 add.w r2, r7, #512 @ 0x200 8005602: f5a2 72ae sub.w r2, r2, #348 @ 0x15c 8005606: 6011 str r1, [r2, #0] return result; 8005608: f507 7200 add.w r2, r7, #512 @ 0x200 800560c: f5a2 72ae sub.w r2, r2, #348 @ 0x15c 8005610: 6812 ldr r2, [r2, #0] 8005612: fab2 f282 clz r2, r2 8005616: b2d2 uxtb r2, r2 8005618: f042 0240 orr.w r2, r2, #64 @ 0x40 800561c: b2d2 uxtb r2, r2 800561e: f002 021f and.w r2, r2, #31 8005622: 2101 movs r1, #1 8005624: fa01 f202 lsl.w r2, r1, r2 8005628: 4013 ands r3, r2 800562a: 2b00 cmp r3, #0 800562c: d084 beq.n 8005538 800562e: e07f b.n 8005730 } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 8005630: f7fc fe68 bl 8002304 8005634: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8 /* Wait till LSE is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 8005638: e00b b.n 8005652 { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) 800563a: f7fc fe63 bl 8002304 800563e: 4602 mov r2, r0 8005640: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8 8005644: 1ad3 subs r3, r2, r3 8005646: f241 3288 movw r2, #5000 @ 0x1388 800564a: 4293 cmp r3, r2 800564c: d901 bls.n 8005652 { return HAL_TIMEOUT; 800564e: 2303 movs r3, #3 8005650: e2c4 b.n 8005bdc 8005652: f507 7300 add.w r3, r7, #512 @ 0x200 8005656: f5a3 73b0 sub.w r3, r3, #352 @ 0x160 800565a: 2202 movs r2, #2 800565c: 601a str r2, [r3, #0] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 800565e: f507 7300 add.w r3, r7, #512 @ 0x200 8005662: f5a3 73b0 sub.w r3, r3, #352 @ 0x160 8005666: 681b ldr r3, [r3, #0] 8005668: fa93 f2a3 rbit r2, r3 800566c: f507 7300 add.w r3, r7, #512 @ 0x200 8005670: f5a3 73b2 sub.w r3, r3, #356 @ 0x164 8005674: 601a str r2, [r3, #0] 8005676: f507 7300 add.w r3, r7, #512 @ 0x200 800567a: f5a3 73b4 sub.w r3, r3, #360 @ 0x168 800567e: 2202 movs r2, #2 8005680: 601a str r2, [r3, #0] 8005682: f507 7300 add.w r3, r7, #512 @ 0x200 8005686: f5a3 73b4 sub.w r3, r3, #360 @ 0x168 800568a: 681b ldr r3, [r3, #0] 800568c: fa93 f2a3 rbit r2, r3 8005690: f507 7300 add.w r3, r7, #512 @ 0x200 8005694: f5a3 73b6 sub.w r3, r3, #364 @ 0x16c 8005698: 601a str r2, [r3, #0] return result; 800569a: f507 7300 add.w r3, r7, #512 @ 0x200 800569e: f5a3 73b6 sub.w r3, r3, #364 @ 0x16c 80056a2: 681b ldr r3, [r3, #0] while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 80056a4: fab3 f383 clz r3, r3 80056a8: b2db uxtb r3, r3 80056aa: 095b lsrs r3, r3, #5 80056ac: b2db uxtb r3, r3 80056ae: f043 0302 orr.w r3, r3, #2 80056b2: b2db uxtb r3, r3 80056b4: 2b02 cmp r3, #2 80056b6: d102 bne.n 80056be 80056b8: 4b43 ldr r3, [pc, #268] @ (80057c8 ) 80056ba: 6a1b ldr r3, [r3, #32] 80056bc: e013 b.n 80056e6 80056be: f507 7300 add.w r3, r7, #512 @ 0x200 80056c2: f5a3 73b8 sub.w r3, r3, #368 @ 0x170 80056c6: 2202 movs r2, #2 80056c8: 601a str r2, [r3, #0] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 80056ca: f507 7300 add.w r3, r7, #512 @ 0x200 80056ce: f5a3 73b8 sub.w r3, r3, #368 @ 0x170 80056d2: 681b ldr r3, [r3, #0] 80056d4: fa93 f2a3 rbit r2, r3 80056d8: f507 7300 add.w r3, r7, #512 @ 0x200 80056dc: f5a3 73ba sub.w r3, r3, #372 @ 0x174 80056e0: 601a str r2, [r3, #0] 80056e2: 4b39 ldr r3, [pc, #228] @ (80057c8 ) 80056e4: 6a5b ldr r3, [r3, #36] @ 0x24 80056e6: f507 7200 add.w r2, r7, #512 @ 0x200 80056ea: f5a2 72bc sub.w r2, r2, #376 @ 0x178 80056ee: 2102 movs r1, #2 80056f0: 6011 str r1, [r2, #0] 80056f2: f507 7200 add.w r2, r7, #512 @ 0x200 80056f6: f5a2 72bc sub.w r2, r2, #376 @ 0x178 80056fa: 6812 ldr r2, [r2, #0] 80056fc: fa92 f1a2 rbit r1, r2 8005700: f507 7200 add.w r2, r7, #512 @ 0x200 8005704: f5a2 72be sub.w r2, r2, #380 @ 0x17c 8005708: 6011 str r1, [r2, #0] return result; 800570a: f507 7200 add.w r2, r7, #512 @ 0x200 800570e: f5a2 72be sub.w r2, r2, #380 @ 0x17c 8005712: 6812 ldr r2, [r2, #0] 8005714: fab2 f282 clz r2, r2 8005718: b2d2 uxtb r2, r2 800571a: f042 0240 orr.w r2, r2, #64 @ 0x40 800571e: b2d2 uxtb r2, r2 8005720: f002 021f and.w r2, r2, #31 8005724: 2101 movs r1, #1 8005726: fa01 f202 lsl.w r2, r1, r2 800572a: 4013 ands r3, r2 800572c: 2b00 cmp r3, #0 800572e: d184 bne.n 800563a } } } /* Require to disable power clock if necessary */ if(pwrclkchanged == SET) 8005730: f897 31ff ldrb.w r3, [r7, #511] @ 0x1ff 8005734: 2b01 cmp r3, #1 8005736: d105 bne.n 8005744 { __HAL_RCC_PWR_CLK_DISABLE(); 8005738: 4b23 ldr r3, [pc, #140] @ (80057c8 ) 800573a: 69db ldr r3, [r3, #28] 800573c: 4a22 ldr r2, [pc, #136] @ (80057c8 ) 800573e: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 8005742: 61d3 str r3, [r2, #28] } /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 8005744: f507 7300 add.w r3, r7, #512 @ 0x200 8005748: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc 800574c: 681b ldr r3, [r3, #0] 800574e: 69db ldr r3, [r3, #28] 8005750: 2b00 cmp r3, #0 8005752: f000 8242 beq.w 8005bda { /* Check if the PLL is used as system clock or not */ if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) 8005756: 4b1c ldr r3, [pc, #112] @ (80057c8 ) 8005758: 685b ldr r3, [r3, #4] 800575a: f003 030c and.w r3, r3, #12 800575e: 2b08 cmp r3, #8 8005760: f000 8213 beq.w 8005b8a { if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 8005764: f507 7300 add.w r3, r7, #512 @ 0x200 8005768: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc 800576c: 681b ldr r3, [r3, #0] 800576e: 69db ldr r3, [r3, #28] 8005770: 2b02 cmp r3, #2 8005772: f040 8162 bne.w 8005a3a 8005776: f507 7300 add.w r3, r7, #512 @ 0x200 800577a: f5a3 73c0 sub.w r3, r3, #384 @ 0x180 800577e: f04f 7280 mov.w r2, #16777216 @ 0x1000000 8005782: 601a str r2, [r3, #0] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8005784: f507 7300 add.w r3, r7, #512 @ 0x200 8005788: f5a3 73c0 sub.w r3, r3, #384 @ 0x180 800578c: 681b ldr r3, [r3, #0] 800578e: fa93 f2a3 rbit r2, r3 8005792: f507 7300 add.w r3, r7, #512 @ 0x200 8005796: f5a3 73c2 sub.w r3, r3, #388 @ 0x184 800579a: 601a str r2, [r3, #0] return result; 800579c: f507 7300 add.w r3, r7, #512 @ 0x200 80057a0: f5a3 73c2 sub.w r3, r3, #388 @ 0x184 80057a4: 681b ldr r3, [r3, #0] #if defined(RCC_CFGR_PLLSRC_HSI_PREDIV) assert_param(IS_RCC_PREDIV(RCC_OscInitStruct->PLL.PREDIV)); #endif /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 80057a6: fab3 f383 clz r3, r3 80057aa: b2db uxtb r3, r3 80057ac: f103 5384 add.w r3, r3, #276824064 @ 0x10800000 80057b0: f503 1384 add.w r3, r3, #1081344 @ 0x108000 80057b4: 009b lsls r3, r3, #2 80057b6: 461a mov r2, r3 80057b8: 2300 movs r3, #0 80057ba: 6013 str r3, [r2, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80057bc: f7fc fda2 bl 8002304 80057c0: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8 /* Wait till PLL is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 80057c4: e00c b.n 80057e0 80057c6: bf00 nop 80057c8: 40021000 .word 0x40021000 { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 80057cc: f7fc fd9a bl 8002304 80057d0: 4602 mov r2, r0 80057d2: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8 80057d6: 1ad3 subs r3, r2, r3 80057d8: 2b02 cmp r3, #2 80057da: d901 bls.n 80057e0 { return HAL_TIMEOUT; 80057dc: 2303 movs r3, #3 80057de: e1fd b.n 8005bdc 80057e0: f507 7300 add.w r3, r7, #512 @ 0x200 80057e4: f5a3 73c4 sub.w r3, r3, #392 @ 0x188 80057e8: f04f 7200 mov.w r2, #33554432 @ 0x2000000 80057ec: 601a str r2, [r3, #0] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 80057ee: f507 7300 add.w r3, r7, #512 @ 0x200 80057f2: f5a3 73c4 sub.w r3, r3, #392 @ 0x188 80057f6: 681b ldr r3, [r3, #0] 80057f8: fa93 f2a3 rbit r2, r3 80057fc: f507 7300 add.w r3, r7, #512 @ 0x200 8005800: f5a3 73c6 sub.w r3, r3, #396 @ 0x18c 8005804: 601a str r2, [r3, #0] return result; 8005806: f507 7300 add.w r3, r7, #512 @ 0x200 800580a: f5a3 73c6 sub.w r3, r3, #396 @ 0x18c 800580e: 681b ldr r3, [r3, #0] while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8005810: fab3 f383 clz r3, r3 8005814: b2db uxtb r3, r3 8005816: 095b lsrs r3, r3, #5 8005818: b2db uxtb r3, r3 800581a: f043 0301 orr.w r3, r3, #1 800581e: b2db uxtb r3, r3 8005820: 2b01 cmp r3, #1 8005822: d102 bne.n 800582a 8005824: 4bb0 ldr r3, [pc, #704] @ (8005ae8 ) 8005826: 681b ldr r3, [r3, #0] 8005828: e027 b.n 800587a 800582a: f507 7300 add.w r3, r7, #512 @ 0x200 800582e: f5a3 73c8 sub.w r3, r3, #400 @ 0x190 8005832: f04f 7200 mov.w r2, #33554432 @ 0x2000000 8005836: 601a str r2, [r3, #0] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8005838: f507 7300 add.w r3, r7, #512 @ 0x200 800583c: f5a3 73c8 sub.w r3, r3, #400 @ 0x190 8005840: 681b ldr r3, [r3, #0] 8005842: fa93 f2a3 rbit r2, r3 8005846: f507 7300 add.w r3, r7, #512 @ 0x200 800584a: f5a3 73ca sub.w r3, r3, #404 @ 0x194 800584e: 601a str r2, [r3, #0] 8005850: f507 7300 add.w r3, r7, #512 @ 0x200 8005854: f5a3 73cc sub.w r3, r3, #408 @ 0x198 8005858: f04f 7200 mov.w r2, #33554432 @ 0x2000000 800585c: 601a str r2, [r3, #0] 800585e: f507 7300 add.w r3, r7, #512 @ 0x200 8005862: f5a3 73cc sub.w r3, r3, #408 @ 0x198 8005866: 681b ldr r3, [r3, #0] 8005868: fa93 f2a3 rbit r2, r3 800586c: f507 7300 add.w r3, r7, #512 @ 0x200 8005870: f5a3 73ce sub.w r3, r3, #412 @ 0x19c 8005874: 601a str r2, [r3, #0] 8005876: 4b9c ldr r3, [pc, #624] @ (8005ae8 ) 8005878: 6a5b ldr r3, [r3, #36] @ 0x24 800587a: f507 7200 add.w r2, r7, #512 @ 0x200 800587e: f5a2 72d0 sub.w r2, r2, #416 @ 0x1a0 8005882: f04f 7100 mov.w r1, #33554432 @ 0x2000000 8005886: 6011 str r1, [r2, #0] 8005888: f507 7200 add.w r2, r7, #512 @ 0x200 800588c: f5a2 72d0 sub.w r2, r2, #416 @ 0x1a0 8005890: 6812 ldr r2, [r2, #0] 8005892: fa92 f1a2 rbit r1, r2 8005896: f507 7200 add.w r2, r7, #512 @ 0x200 800589a: f5a2 72d2 sub.w r2, r2, #420 @ 0x1a4 800589e: 6011 str r1, [r2, #0] return result; 80058a0: f507 7200 add.w r2, r7, #512 @ 0x200 80058a4: f5a2 72d2 sub.w r2, r2, #420 @ 0x1a4 80058a8: 6812 ldr r2, [r2, #0] 80058aa: fab2 f282 clz r2, r2 80058ae: b2d2 uxtb r2, r2 80058b0: f042 0220 orr.w r2, r2, #32 80058b4: b2d2 uxtb r2, r2 80058b6: f002 021f and.w r2, r2, #31 80058ba: 2101 movs r1, #1 80058bc: fa01 f202 lsl.w r2, r1, r2 80058c0: 4013 ands r3, r2 80058c2: 2b00 cmp r3, #0 80058c4: d182 bne.n 80057cc __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, RCC_OscInitStruct->PLL.PREDIV, RCC_OscInitStruct->PLL.PLLMUL); #else /* Configure the main PLL clock source and multiplication factor. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 80058c6: 4b88 ldr r3, [pc, #544] @ (8005ae8 ) 80058c8: 685b ldr r3, [r3, #4] 80058ca: f423 1274 bic.w r2, r3, #3997696 @ 0x3d0000 80058ce: f507 7300 add.w r3, r7, #512 @ 0x200 80058d2: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc 80058d6: 681b ldr r3, [r3, #0] 80058d8: 6a59 ldr r1, [r3, #36] @ 0x24 80058da: f507 7300 add.w r3, r7, #512 @ 0x200 80058de: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc 80058e2: 681b ldr r3, [r3, #0] 80058e4: 6a1b ldr r3, [r3, #32] 80058e6: 430b orrs r3, r1 80058e8: 497f ldr r1, [pc, #508] @ (8005ae8 ) 80058ea: 4313 orrs r3, r2 80058ec: 604b str r3, [r1, #4] 80058ee: f507 7300 add.w r3, r7, #512 @ 0x200 80058f2: f5a3 73d4 sub.w r3, r3, #424 @ 0x1a8 80058f6: f04f 7280 mov.w r2, #16777216 @ 0x1000000 80058fa: 601a str r2, [r3, #0] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 80058fc: f507 7300 add.w r3, r7, #512 @ 0x200 8005900: f5a3 73d4 sub.w r3, r3, #424 @ 0x1a8 8005904: 681b ldr r3, [r3, #0] 8005906: fa93 f2a3 rbit r2, r3 800590a: f507 7300 add.w r3, r7, #512 @ 0x200 800590e: f5a3 73d6 sub.w r3, r3, #428 @ 0x1ac 8005912: 601a str r2, [r3, #0] return result; 8005914: f507 7300 add.w r3, r7, #512 @ 0x200 8005918: f5a3 73d6 sub.w r3, r3, #428 @ 0x1ac 800591c: 681b ldr r3, [r3, #0] RCC_OscInitStruct->PLL.PLLMUL); #endif /* RCC_CFGR_PLLSRC_HSI_PREDIV */ /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 800591e: fab3 f383 clz r3, r3 8005922: b2db uxtb r3, r3 8005924: f103 5384 add.w r3, r3, #276824064 @ 0x10800000 8005928: f503 1384 add.w r3, r3, #1081344 @ 0x108000 800592c: 009b lsls r3, r3, #2 800592e: 461a mov r2, r3 8005930: 2301 movs r3, #1 8005932: 6013 str r3, [r2, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8005934: f7fc fce6 bl 8002304 8005938: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8 /* Wait till PLL is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 800593c: e009 b.n 8005952 { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 800593e: f7fc fce1 bl 8002304 8005942: 4602 mov r2, r0 8005944: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8 8005948: 1ad3 subs r3, r2, r3 800594a: 2b02 cmp r3, #2 800594c: d901 bls.n 8005952 { return HAL_TIMEOUT; 800594e: 2303 movs r3, #3 8005950: e144 b.n 8005bdc 8005952: f507 7300 add.w r3, r7, #512 @ 0x200 8005956: f5a3 73d8 sub.w r3, r3, #432 @ 0x1b0 800595a: f04f 7200 mov.w r2, #33554432 @ 0x2000000 800595e: 601a str r2, [r3, #0] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8005960: f507 7300 add.w r3, r7, #512 @ 0x200 8005964: f5a3 73d8 sub.w r3, r3, #432 @ 0x1b0 8005968: 681b ldr r3, [r3, #0] 800596a: fa93 f2a3 rbit r2, r3 800596e: f507 7300 add.w r3, r7, #512 @ 0x200 8005972: f5a3 73da sub.w r3, r3, #436 @ 0x1b4 8005976: 601a str r2, [r3, #0] return result; 8005978: f507 7300 add.w r3, r7, #512 @ 0x200 800597c: f5a3 73da sub.w r3, r3, #436 @ 0x1b4 8005980: 681b ldr r3, [r3, #0] while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8005982: fab3 f383 clz r3, r3 8005986: b2db uxtb r3, r3 8005988: 095b lsrs r3, r3, #5 800598a: b2db uxtb r3, r3 800598c: f043 0301 orr.w r3, r3, #1 8005990: b2db uxtb r3, r3 8005992: 2b01 cmp r3, #1 8005994: d102 bne.n 800599c 8005996: 4b54 ldr r3, [pc, #336] @ (8005ae8 ) 8005998: 681b ldr r3, [r3, #0] 800599a: e027 b.n 80059ec 800599c: f507 7300 add.w r3, r7, #512 @ 0x200 80059a0: f5a3 73dc sub.w r3, r3, #440 @ 0x1b8 80059a4: f04f 7200 mov.w r2, #33554432 @ 0x2000000 80059a8: 601a str r2, [r3, #0] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 80059aa: f507 7300 add.w r3, r7, #512 @ 0x200 80059ae: f5a3 73dc sub.w r3, r3, #440 @ 0x1b8 80059b2: 681b ldr r3, [r3, #0] 80059b4: fa93 f2a3 rbit r2, r3 80059b8: f507 7300 add.w r3, r7, #512 @ 0x200 80059bc: f5a3 73de sub.w r3, r3, #444 @ 0x1bc 80059c0: 601a str r2, [r3, #0] 80059c2: f507 7300 add.w r3, r7, #512 @ 0x200 80059c6: f5a3 73e0 sub.w r3, r3, #448 @ 0x1c0 80059ca: f04f 7200 mov.w r2, #33554432 @ 0x2000000 80059ce: 601a str r2, [r3, #0] 80059d0: f507 7300 add.w r3, r7, #512 @ 0x200 80059d4: f5a3 73e0 sub.w r3, r3, #448 @ 0x1c0 80059d8: 681b ldr r3, [r3, #0] 80059da: fa93 f2a3 rbit r2, r3 80059de: f507 7300 add.w r3, r7, #512 @ 0x200 80059e2: f5a3 73e2 sub.w r3, r3, #452 @ 0x1c4 80059e6: 601a str r2, [r3, #0] 80059e8: 4b3f ldr r3, [pc, #252] @ (8005ae8 ) 80059ea: 6a5b ldr r3, [r3, #36] @ 0x24 80059ec: f507 7200 add.w r2, r7, #512 @ 0x200 80059f0: f5a2 72e4 sub.w r2, r2, #456 @ 0x1c8 80059f4: f04f 7100 mov.w r1, #33554432 @ 0x2000000 80059f8: 6011 str r1, [r2, #0] 80059fa: f507 7200 add.w r2, r7, #512 @ 0x200 80059fe: f5a2 72e4 sub.w r2, r2, #456 @ 0x1c8 8005a02: 6812 ldr r2, [r2, #0] 8005a04: fa92 f1a2 rbit r1, r2 8005a08: f507 7200 add.w r2, r7, #512 @ 0x200 8005a0c: f5a2 72e6 sub.w r2, r2, #460 @ 0x1cc 8005a10: 6011 str r1, [r2, #0] return result; 8005a12: f507 7200 add.w r2, r7, #512 @ 0x200 8005a16: f5a2 72e6 sub.w r2, r2, #460 @ 0x1cc 8005a1a: 6812 ldr r2, [r2, #0] 8005a1c: fab2 f282 clz r2, r2 8005a20: b2d2 uxtb r2, r2 8005a22: f042 0220 orr.w r2, r2, #32 8005a26: b2d2 uxtb r2, r2 8005a28: f002 021f and.w r2, r2, #31 8005a2c: 2101 movs r1, #1 8005a2e: fa01 f202 lsl.w r2, r1, r2 8005a32: 4013 ands r3, r2 8005a34: 2b00 cmp r3, #0 8005a36: d082 beq.n 800593e 8005a38: e0cf b.n 8005bda 8005a3a: f507 7300 add.w r3, r7, #512 @ 0x200 8005a3e: f5a3 73e8 sub.w r3, r3, #464 @ 0x1d0 8005a42: f04f 7280 mov.w r2, #16777216 @ 0x1000000 8005a46: 601a str r2, [r3, #0] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8005a48: f507 7300 add.w r3, r7, #512 @ 0x200 8005a4c: f5a3 73e8 sub.w r3, r3, #464 @ 0x1d0 8005a50: 681b ldr r3, [r3, #0] 8005a52: fa93 f2a3 rbit r2, r3 8005a56: f507 7300 add.w r3, r7, #512 @ 0x200 8005a5a: f5a3 73ea sub.w r3, r3, #468 @ 0x1d4 8005a5e: 601a str r2, [r3, #0] return result; 8005a60: f507 7300 add.w r3, r7, #512 @ 0x200 8005a64: f5a3 73ea sub.w r3, r3, #468 @ 0x1d4 8005a68: 681b ldr r3, [r3, #0] } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8005a6a: fab3 f383 clz r3, r3 8005a6e: b2db uxtb r3, r3 8005a70: f103 5384 add.w r3, r3, #276824064 @ 0x10800000 8005a74: f503 1384 add.w r3, r3, #1081344 @ 0x108000 8005a78: 009b lsls r3, r3, #2 8005a7a: 461a mov r2, r3 8005a7c: 2300 movs r3, #0 8005a7e: 6013 str r3, [r2, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8005a80: f7fc fc40 bl 8002304 8005a84: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8 /* Wait till PLL is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8005a88: e009 b.n 8005a9e { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 8005a8a: f7fc fc3b bl 8002304 8005a8e: 4602 mov r2, r0 8005a90: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8 8005a94: 1ad3 subs r3, r2, r3 8005a96: 2b02 cmp r3, #2 8005a98: d901 bls.n 8005a9e { return HAL_TIMEOUT; 8005a9a: 2303 movs r3, #3 8005a9c: e09e b.n 8005bdc 8005a9e: f507 7300 add.w r3, r7, #512 @ 0x200 8005aa2: f5a3 73ec sub.w r3, r3, #472 @ 0x1d8 8005aa6: f04f 7200 mov.w r2, #33554432 @ 0x2000000 8005aaa: 601a str r2, [r3, #0] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8005aac: f507 7300 add.w r3, r7, #512 @ 0x200 8005ab0: f5a3 73ec sub.w r3, r3, #472 @ 0x1d8 8005ab4: 681b ldr r3, [r3, #0] 8005ab6: fa93 f2a3 rbit r2, r3 8005aba: f507 7300 add.w r3, r7, #512 @ 0x200 8005abe: f5a3 73ee sub.w r3, r3, #476 @ 0x1dc 8005ac2: 601a str r2, [r3, #0] return result; 8005ac4: f507 7300 add.w r3, r7, #512 @ 0x200 8005ac8: f5a3 73ee sub.w r3, r3, #476 @ 0x1dc 8005acc: 681b ldr r3, [r3, #0] while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8005ace: fab3 f383 clz r3, r3 8005ad2: b2db uxtb r3, r3 8005ad4: 095b lsrs r3, r3, #5 8005ad6: b2db uxtb r3, r3 8005ad8: f043 0301 orr.w r3, r3, #1 8005adc: b2db uxtb r3, r3 8005ade: 2b01 cmp r3, #1 8005ae0: d104 bne.n 8005aec 8005ae2: 4b01 ldr r3, [pc, #4] @ (8005ae8 ) 8005ae4: 681b ldr r3, [r3, #0] 8005ae6: e029 b.n 8005b3c 8005ae8: 40021000 .word 0x40021000 8005aec: f507 7300 add.w r3, r7, #512 @ 0x200 8005af0: f5a3 73f0 sub.w r3, r3, #480 @ 0x1e0 8005af4: f04f 7200 mov.w r2, #33554432 @ 0x2000000 8005af8: 601a str r2, [r3, #0] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8005afa: f507 7300 add.w r3, r7, #512 @ 0x200 8005afe: f5a3 73f0 sub.w r3, r3, #480 @ 0x1e0 8005b02: 681b ldr r3, [r3, #0] 8005b04: fa93 f2a3 rbit r2, r3 8005b08: f507 7300 add.w r3, r7, #512 @ 0x200 8005b0c: f5a3 73f2 sub.w r3, r3, #484 @ 0x1e4 8005b10: 601a str r2, [r3, #0] 8005b12: f507 7300 add.w r3, r7, #512 @ 0x200 8005b16: f5a3 73f4 sub.w r3, r3, #488 @ 0x1e8 8005b1a: f04f 7200 mov.w r2, #33554432 @ 0x2000000 8005b1e: 601a str r2, [r3, #0] 8005b20: f507 7300 add.w r3, r7, #512 @ 0x200 8005b24: f5a3 73f4 sub.w r3, r3, #488 @ 0x1e8 8005b28: 681b ldr r3, [r3, #0] 8005b2a: fa93 f2a3 rbit r2, r3 8005b2e: f507 7300 add.w r3, r7, #512 @ 0x200 8005b32: f5a3 73f6 sub.w r3, r3, #492 @ 0x1ec 8005b36: 601a str r2, [r3, #0] 8005b38: 4b2b ldr r3, [pc, #172] @ (8005be8 ) 8005b3a: 6a5b ldr r3, [r3, #36] @ 0x24 8005b3c: f507 7200 add.w r2, r7, #512 @ 0x200 8005b40: f5a2 72f8 sub.w r2, r2, #496 @ 0x1f0 8005b44: f04f 7100 mov.w r1, #33554432 @ 0x2000000 8005b48: 6011 str r1, [r2, #0] 8005b4a: f507 7200 add.w r2, r7, #512 @ 0x200 8005b4e: f5a2 72f8 sub.w r2, r2, #496 @ 0x1f0 8005b52: 6812 ldr r2, [r2, #0] 8005b54: fa92 f1a2 rbit r1, r2 8005b58: f507 7200 add.w r2, r7, #512 @ 0x200 8005b5c: f5a2 72fa sub.w r2, r2, #500 @ 0x1f4 8005b60: 6011 str r1, [r2, #0] return result; 8005b62: f507 7200 add.w r2, r7, #512 @ 0x200 8005b66: f5a2 72fa sub.w r2, r2, #500 @ 0x1f4 8005b6a: 6812 ldr r2, [r2, #0] 8005b6c: fab2 f282 clz r2, r2 8005b70: b2d2 uxtb r2, r2 8005b72: f042 0220 orr.w r2, r2, #32 8005b76: b2d2 uxtb r2, r2 8005b78: f002 021f and.w r2, r2, #31 8005b7c: 2101 movs r1, #1 8005b7e: fa01 f202 lsl.w r2, r1, r2 8005b82: 4013 ands r3, r2 8005b84: 2b00 cmp r3, #0 8005b86: d180 bne.n 8005a8a 8005b88: e027 b.n 8005bda } } else { /* Check if there is a request to disable the PLL used as System clock source */ if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) 8005b8a: f507 7300 add.w r3, r7, #512 @ 0x200 8005b8e: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc 8005b92: 681b ldr r3, [r3, #0] 8005b94: 69db ldr r3, [r3, #28] 8005b96: 2b01 cmp r3, #1 8005b98: d101 bne.n 8005b9e { return HAL_ERROR; 8005b9a: 2301 movs r3, #1 8005b9c: e01e b.n 8005bdc } else { /* Do not return HAL_ERROR if request repeats the current configuration */ pll_config = RCC->CFGR; 8005b9e: 4b12 ldr r3, [pc, #72] @ (8005be8 ) 8005ba0: 685b ldr r3, [r3, #4] 8005ba2: f8c7 31f4 str.w r3, [r7, #500] @ 0x1f4 pll_config2 = RCC->CFGR2; if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) || (READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV)) #else if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8005ba6: f8d7 31f4 ldr.w r3, [r7, #500] @ 0x1f4 8005baa: f403 3280 and.w r2, r3, #65536 @ 0x10000 8005bae: f507 7300 add.w r3, r7, #512 @ 0x200 8005bb2: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc 8005bb6: 681b ldr r3, [r3, #0] 8005bb8: 6a1b ldr r3, [r3, #32] 8005bba: 429a cmp r2, r3 8005bbc: d10b bne.n 8005bd6 (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL)) 8005bbe: f8d7 31f4 ldr.w r3, [r7, #500] @ 0x1f4 8005bc2: f403 1270 and.w r2, r3, #3932160 @ 0x3c0000 8005bc6: f507 7300 add.w r3, r7, #512 @ 0x200 8005bca: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc 8005bce: 681b ldr r3, [r3, #0] 8005bd0: 6a5b ldr r3, [r3, #36] @ 0x24 if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8005bd2: 429a cmp r2, r3 8005bd4: d001 beq.n 8005bda #endif { return HAL_ERROR; 8005bd6: 2301 movs r3, #1 8005bd8: e000 b.n 8005bdc } } } } return HAL_OK; 8005bda: 2300 movs r3, #0 } 8005bdc: 4618 mov r0, r3 8005bde: f507 7700 add.w r7, r7, #512 @ 0x200 8005be2: 46bd mov sp, r7 8005be4: bd80 pop {r7, pc} 8005be6: bf00 nop 8005be8: 40021000 .word 0x40021000 08005bec : * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is * currently used as system clock source. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 8005bec: b580 push {r7, lr} 8005bee: b09e sub sp, #120 @ 0x78 8005bf0: af00 add r7, sp, #0 8005bf2: 6078 str r0, [r7, #4] 8005bf4: 6039 str r1, [r7, #0] uint32_t tickstart = 0U; 8005bf6: 2300 movs r3, #0 8005bf8: 677b str r3, [r7, #116] @ 0x74 /* Check Null pointer */ if(RCC_ClkInitStruct == NULL) 8005bfa: 687b ldr r3, [r7, #4] 8005bfc: 2b00 cmp r3, #0 8005bfe: d101 bne.n 8005c04 { return HAL_ERROR; 8005c00: 2301 movs r3, #1 8005c02: e162 b.n 8005eca /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) of the device. */ /* Increasing the number of wait states because of higher CPU frequency */ if(FLatency > __HAL_FLASH_GET_LATENCY()) 8005c04: 4b90 ldr r3, [pc, #576] @ (8005e48 ) 8005c06: 681b ldr r3, [r3, #0] 8005c08: f003 0307 and.w r3, r3, #7 8005c0c: 683a ldr r2, [r7, #0] 8005c0e: 429a cmp r2, r3 8005c10: d910 bls.n 8005c34 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8005c12: 4b8d ldr r3, [pc, #564] @ (8005e48 ) 8005c14: 681b ldr r3, [r3, #0] 8005c16: f023 0207 bic.w r2, r3, #7 8005c1a: 498b ldr r1, [pc, #556] @ (8005e48 ) 8005c1c: 683b ldr r3, [r7, #0] 8005c1e: 4313 orrs r3, r2 8005c20: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if(__HAL_FLASH_GET_LATENCY() != FLatency) 8005c22: 4b89 ldr r3, [pc, #548] @ (8005e48 ) 8005c24: 681b ldr r3, [r3, #0] 8005c26: f003 0307 and.w r3, r3, #7 8005c2a: 683a ldr r2, [r7, #0] 8005c2c: 429a cmp r2, r3 8005c2e: d001 beq.n 8005c34 { return HAL_ERROR; 8005c30: 2301 movs r3, #1 8005c32: e14a b.n 8005eca } } /*-------------------------- HCLK Configuration --------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 8005c34: 687b ldr r3, [r7, #4] 8005c36: 681b ldr r3, [r3, #0] 8005c38: f003 0302 and.w r3, r3, #2 8005c3c: 2b00 cmp r3, #0 8005c3e: d008 beq.n 8005c52 { assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 8005c40: 4b82 ldr r3, [pc, #520] @ (8005e4c ) 8005c42: 685b ldr r3, [r3, #4] 8005c44: f023 02f0 bic.w r2, r3, #240 @ 0xf0 8005c48: 687b ldr r3, [r7, #4] 8005c4a: 689b ldr r3, [r3, #8] 8005c4c: 497f ldr r1, [pc, #508] @ (8005e4c ) 8005c4e: 4313 orrs r3, r2 8005c50: 604b str r3, [r1, #4] } /*------------------------- SYSCLK Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 8005c52: 687b ldr r3, [r7, #4] 8005c54: 681b ldr r3, [r3, #0] 8005c56: f003 0301 and.w r3, r3, #1 8005c5a: 2b00 cmp r3, #0 8005c5c: f000 80dc beq.w 8005e18 { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 8005c60: 687b ldr r3, [r7, #4] 8005c62: 685b ldr r3, [r3, #4] 8005c64: 2b01 cmp r3, #1 8005c66: d13c bne.n 8005ce2 8005c68: f44f 3300 mov.w r3, #131072 @ 0x20000 8005c6c: 673b str r3, [r7, #112] @ 0x70 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8005c6e: 6f3b ldr r3, [r7, #112] @ 0x70 8005c70: fa93 f3a3 rbit r3, r3 8005c74: 66fb str r3, [r7, #108] @ 0x6c return result; 8005c76: 6efb ldr r3, [r7, #108] @ 0x6c { /* Check the HSE ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8005c78: fab3 f383 clz r3, r3 8005c7c: b2db uxtb r3, r3 8005c7e: 095b lsrs r3, r3, #5 8005c80: b2db uxtb r3, r3 8005c82: f043 0301 orr.w r3, r3, #1 8005c86: b2db uxtb r3, r3 8005c88: 2b01 cmp r3, #1 8005c8a: d102 bne.n 8005c92 8005c8c: 4b6f ldr r3, [pc, #444] @ (8005e4c ) 8005c8e: 681b ldr r3, [r3, #0] 8005c90: e00f b.n 8005cb2 8005c92: f44f 3300 mov.w r3, #131072 @ 0x20000 8005c96: 66bb str r3, [r7, #104] @ 0x68 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8005c98: 6ebb ldr r3, [r7, #104] @ 0x68 8005c9a: fa93 f3a3 rbit r3, r3 8005c9e: 667b str r3, [r7, #100] @ 0x64 8005ca0: f44f 3300 mov.w r3, #131072 @ 0x20000 8005ca4: 663b str r3, [r7, #96] @ 0x60 8005ca6: 6e3b ldr r3, [r7, #96] @ 0x60 8005ca8: fa93 f3a3 rbit r3, r3 8005cac: 65fb str r3, [r7, #92] @ 0x5c 8005cae: 4b67 ldr r3, [pc, #412] @ (8005e4c ) 8005cb0: 6a5b ldr r3, [r3, #36] @ 0x24 8005cb2: f44f 3200 mov.w r2, #131072 @ 0x20000 8005cb6: 65ba str r2, [r7, #88] @ 0x58 8005cb8: 6dba ldr r2, [r7, #88] @ 0x58 8005cba: fa92 f2a2 rbit r2, r2 8005cbe: 657a str r2, [r7, #84] @ 0x54 return result; 8005cc0: 6d7a ldr r2, [r7, #84] @ 0x54 8005cc2: fab2 f282 clz r2, r2 8005cc6: b2d2 uxtb r2, r2 8005cc8: f042 0220 orr.w r2, r2, #32 8005ccc: b2d2 uxtb r2, r2 8005cce: f002 021f and.w r2, r2, #31 8005cd2: 2101 movs r1, #1 8005cd4: fa01 f202 lsl.w r2, r1, r2 8005cd8: 4013 ands r3, r2 8005cda: 2b00 cmp r3, #0 8005cdc: d17b bne.n 8005dd6 { return HAL_ERROR; 8005cde: 2301 movs r3, #1 8005ce0: e0f3 b.n 8005eca } } /* PLL is selected as System Clock Source */ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 8005ce2: 687b ldr r3, [r7, #4] 8005ce4: 685b ldr r3, [r3, #4] 8005ce6: 2b02 cmp r3, #2 8005ce8: d13c bne.n 8005d64 8005cea: f04f 7300 mov.w r3, #33554432 @ 0x2000000 8005cee: 653b str r3, [r7, #80] @ 0x50 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8005cf0: 6d3b ldr r3, [r7, #80] @ 0x50 8005cf2: fa93 f3a3 rbit r3, r3 8005cf6: 64fb str r3, [r7, #76] @ 0x4c return result; 8005cf8: 6cfb ldr r3, [r7, #76] @ 0x4c { /* Check the PLL ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8005cfa: fab3 f383 clz r3, r3 8005cfe: b2db uxtb r3, r3 8005d00: 095b lsrs r3, r3, #5 8005d02: b2db uxtb r3, r3 8005d04: f043 0301 orr.w r3, r3, #1 8005d08: b2db uxtb r3, r3 8005d0a: 2b01 cmp r3, #1 8005d0c: d102 bne.n 8005d14 8005d0e: 4b4f ldr r3, [pc, #316] @ (8005e4c ) 8005d10: 681b ldr r3, [r3, #0] 8005d12: e00f b.n 8005d34 8005d14: f04f 7300 mov.w r3, #33554432 @ 0x2000000 8005d18: 64bb str r3, [r7, #72] @ 0x48 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8005d1a: 6cbb ldr r3, [r7, #72] @ 0x48 8005d1c: fa93 f3a3 rbit r3, r3 8005d20: 647b str r3, [r7, #68] @ 0x44 8005d22: f04f 7300 mov.w r3, #33554432 @ 0x2000000 8005d26: 643b str r3, [r7, #64] @ 0x40 8005d28: 6c3b ldr r3, [r7, #64] @ 0x40 8005d2a: fa93 f3a3 rbit r3, r3 8005d2e: 63fb str r3, [r7, #60] @ 0x3c 8005d30: 4b46 ldr r3, [pc, #280] @ (8005e4c ) 8005d32: 6a5b ldr r3, [r3, #36] @ 0x24 8005d34: f04f 7200 mov.w r2, #33554432 @ 0x2000000 8005d38: 63ba str r2, [r7, #56] @ 0x38 8005d3a: 6bba ldr r2, [r7, #56] @ 0x38 8005d3c: fa92 f2a2 rbit r2, r2 8005d40: 637a str r2, [r7, #52] @ 0x34 return result; 8005d42: 6b7a ldr r2, [r7, #52] @ 0x34 8005d44: fab2 f282 clz r2, r2 8005d48: b2d2 uxtb r2, r2 8005d4a: f042 0220 orr.w r2, r2, #32 8005d4e: b2d2 uxtb r2, r2 8005d50: f002 021f and.w r2, r2, #31 8005d54: 2101 movs r1, #1 8005d56: fa01 f202 lsl.w r2, r1, r2 8005d5a: 4013 ands r3, r2 8005d5c: 2b00 cmp r3, #0 8005d5e: d13a bne.n 8005dd6 { return HAL_ERROR; 8005d60: 2301 movs r3, #1 8005d62: e0b2 b.n 8005eca 8005d64: 2302 movs r3, #2 8005d66: 633b str r3, [r7, #48] @ 0x30 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8005d68: 6b3b ldr r3, [r7, #48] @ 0x30 8005d6a: fa93 f3a3 rbit r3, r3 8005d6e: 62fb str r3, [r7, #44] @ 0x2c return result; 8005d70: 6afb ldr r3, [r7, #44] @ 0x2c } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8005d72: fab3 f383 clz r3, r3 8005d76: b2db uxtb r3, r3 8005d78: 095b lsrs r3, r3, #5 8005d7a: b2db uxtb r3, r3 8005d7c: f043 0301 orr.w r3, r3, #1 8005d80: b2db uxtb r3, r3 8005d82: 2b01 cmp r3, #1 8005d84: d102 bne.n 8005d8c 8005d86: 4b31 ldr r3, [pc, #196] @ (8005e4c ) 8005d88: 681b ldr r3, [r3, #0] 8005d8a: e00d b.n 8005da8 8005d8c: 2302 movs r3, #2 8005d8e: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8005d90: 6abb ldr r3, [r7, #40] @ 0x28 8005d92: fa93 f3a3 rbit r3, r3 8005d96: 627b str r3, [r7, #36] @ 0x24 8005d98: 2302 movs r3, #2 8005d9a: 623b str r3, [r7, #32] 8005d9c: 6a3b ldr r3, [r7, #32] 8005d9e: fa93 f3a3 rbit r3, r3 8005da2: 61fb str r3, [r7, #28] 8005da4: 4b29 ldr r3, [pc, #164] @ (8005e4c ) 8005da6: 6a5b ldr r3, [r3, #36] @ 0x24 8005da8: 2202 movs r2, #2 8005daa: 61ba str r2, [r7, #24] 8005dac: 69ba ldr r2, [r7, #24] 8005dae: fa92 f2a2 rbit r2, r2 8005db2: 617a str r2, [r7, #20] return result; 8005db4: 697a ldr r2, [r7, #20] 8005db6: fab2 f282 clz r2, r2 8005dba: b2d2 uxtb r2, r2 8005dbc: f042 0220 orr.w r2, r2, #32 8005dc0: b2d2 uxtb r2, r2 8005dc2: f002 021f and.w r2, r2, #31 8005dc6: 2101 movs r1, #1 8005dc8: fa01 f202 lsl.w r2, r1, r2 8005dcc: 4013 ands r3, r2 8005dce: 2b00 cmp r3, #0 8005dd0: d101 bne.n 8005dd6 { return HAL_ERROR; 8005dd2: 2301 movs r3, #1 8005dd4: e079 b.n 8005eca } } __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); 8005dd6: 4b1d ldr r3, [pc, #116] @ (8005e4c ) 8005dd8: 685b ldr r3, [r3, #4] 8005dda: f023 0203 bic.w r2, r3, #3 8005dde: 687b ldr r3, [r7, #4] 8005de0: 685b ldr r3, [r3, #4] 8005de2: 491a ldr r1, [pc, #104] @ (8005e4c ) 8005de4: 4313 orrs r3, r2 8005de6: 604b str r3, [r1, #4] /* Get Start Tick */ tickstart = HAL_GetTick(); 8005de8: f7fc fa8c bl 8002304 8005dec: 6778 str r0, [r7, #116] @ 0x74 while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8005dee: e00a b.n 8005e06 { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 8005df0: f7fc fa88 bl 8002304 8005df4: 4602 mov r2, r0 8005df6: 6f7b ldr r3, [r7, #116] @ 0x74 8005df8: 1ad3 subs r3, r2, r3 8005dfa: f241 3288 movw r2, #5000 @ 0x1388 8005dfe: 4293 cmp r3, r2 8005e00: d901 bls.n 8005e06 { return HAL_TIMEOUT; 8005e02: 2303 movs r3, #3 8005e04: e061 b.n 8005eca while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8005e06: 4b11 ldr r3, [pc, #68] @ (8005e4c ) 8005e08: 685b ldr r3, [r3, #4] 8005e0a: f003 020c and.w r2, r3, #12 8005e0e: 687b ldr r3, [r7, #4] 8005e10: 685b ldr r3, [r3, #4] 8005e12: 009b lsls r3, r3, #2 8005e14: 429a cmp r2, r3 8005e16: d1eb bne.n 8005df0 } } } /* Decreasing the number of wait states because of lower CPU frequency */ if(FLatency < __HAL_FLASH_GET_LATENCY()) 8005e18: 4b0b ldr r3, [pc, #44] @ (8005e48 ) 8005e1a: 681b ldr r3, [r3, #0] 8005e1c: f003 0307 and.w r3, r3, #7 8005e20: 683a ldr r2, [r7, #0] 8005e22: 429a cmp r2, r3 8005e24: d214 bcs.n 8005e50 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8005e26: 4b08 ldr r3, [pc, #32] @ (8005e48 ) 8005e28: 681b ldr r3, [r3, #0] 8005e2a: f023 0207 bic.w r2, r3, #7 8005e2e: 4906 ldr r1, [pc, #24] @ (8005e48 ) 8005e30: 683b ldr r3, [r7, #0] 8005e32: 4313 orrs r3, r2 8005e34: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if(__HAL_FLASH_GET_LATENCY() != FLatency) 8005e36: 4b04 ldr r3, [pc, #16] @ (8005e48 ) 8005e38: 681b ldr r3, [r3, #0] 8005e3a: f003 0307 and.w r3, r3, #7 8005e3e: 683a ldr r2, [r7, #0] 8005e40: 429a cmp r2, r3 8005e42: d005 beq.n 8005e50 { return HAL_ERROR; 8005e44: 2301 movs r3, #1 8005e46: e040 b.n 8005eca 8005e48: 40022000 .word 0x40022000 8005e4c: 40021000 .word 0x40021000 } } /*-------------------------- PCLK1 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8005e50: 687b ldr r3, [r7, #4] 8005e52: 681b ldr r3, [r3, #0] 8005e54: f003 0304 and.w r3, r3, #4 8005e58: 2b00 cmp r3, #0 8005e5a: d008 beq.n 8005e6e { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); 8005e5c: 4b1d ldr r3, [pc, #116] @ (8005ed4 ) 8005e5e: 685b ldr r3, [r3, #4] 8005e60: f423 62e0 bic.w r2, r3, #1792 @ 0x700 8005e64: 687b ldr r3, [r7, #4] 8005e66: 68db ldr r3, [r3, #12] 8005e68: 491a ldr r1, [pc, #104] @ (8005ed4 ) 8005e6a: 4313 orrs r3, r2 8005e6c: 604b str r3, [r1, #4] } /*-------------------------- PCLK2 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8005e6e: 687b ldr r3, [r7, #4] 8005e70: 681b ldr r3, [r3, #0] 8005e72: f003 0308 and.w r3, r3, #8 8005e76: 2b00 cmp r3, #0 8005e78: d009 beq.n 8005e8e { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); 8005e7a: 4b16 ldr r3, [pc, #88] @ (8005ed4 ) 8005e7c: 685b ldr r3, [r3, #4] 8005e7e: f423 5260 bic.w r2, r3, #14336 @ 0x3800 8005e82: 687b ldr r3, [r7, #4] 8005e84: 691b ldr r3, [r3, #16] 8005e86: 00db lsls r3, r3, #3 8005e88: 4912 ldr r1, [pc, #72] @ (8005ed4 ) 8005e8a: 4313 orrs r3, r2 8005e8c: 604b str r3, [r1, #4] } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER]; 8005e8e: f000 f829 bl 8005ee4 8005e92: 4601 mov r1, r0 8005e94: 4b0f ldr r3, [pc, #60] @ (8005ed4 ) 8005e96: 685b ldr r3, [r3, #4] 8005e98: f003 03f0 and.w r3, r3, #240 @ 0xf0 8005e9c: 22f0 movs r2, #240 @ 0xf0 8005e9e: 613a str r2, [r7, #16] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8005ea0: 693a ldr r2, [r7, #16] 8005ea2: fa92 f2a2 rbit r2, r2 8005ea6: 60fa str r2, [r7, #12] return result; 8005ea8: 68fa ldr r2, [r7, #12] 8005eaa: fab2 f282 clz r2, r2 8005eae: b2d2 uxtb r2, r2 8005eb0: 40d3 lsrs r3, r2 8005eb2: 4a09 ldr r2, [pc, #36] @ (8005ed8 ) 8005eb4: 5cd3 ldrb r3, [r2, r3] 8005eb6: fa21 f303 lsr.w r3, r1, r3 8005eba: 4a08 ldr r2, [pc, #32] @ (8005edc ) 8005ebc: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings*/ HAL_InitTick (uwTickPrio); 8005ebe: 4b08 ldr r3, [pc, #32] @ (8005ee0 ) 8005ec0: 681b ldr r3, [r3, #0] 8005ec2: 4618 mov r0, r3 8005ec4: f7fc f9da bl 800227c return HAL_OK; 8005ec8: 2300 movs r3, #0 } 8005eca: 4618 mov r0, r3 8005ecc: 3778 adds r7, #120 @ 0x78 8005ece: 46bd mov sp, r7 8005ed0: bd80 pop {r7, pc} 8005ed2: bf00 nop 8005ed4: 40021000 .word 0x40021000 8005ed8: 0800724c .word 0x0800724c 8005edc: 20000000 .word 0x20000000 8005ee0: 20000004 .word 0x20000004 08005ee4 : * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 8005ee4: b480 push {r7} 8005ee6: b087 sub sp, #28 8005ee8: af00 add r7, sp, #0 uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U; 8005eea: 2300 movs r3, #0 8005eec: 60fb str r3, [r7, #12] 8005eee: 2300 movs r3, #0 8005ef0: 60bb str r3, [r7, #8] 8005ef2: 2300 movs r3, #0 8005ef4: 617b str r3, [r7, #20] 8005ef6: 2300 movs r3, #0 8005ef8: 607b str r3, [r7, #4] uint32_t sysclockfreq = 0U; 8005efa: 2300 movs r3, #0 8005efc: 613b str r3, [r7, #16] tmpreg = RCC->CFGR; 8005efe: 4b1e ldr r3, [pc, #120] @ (8005f78 ) 8005f00: 685b ldr r3, [r3, #4] 8005f02: 60fb str r3, [r7, #12] /* Get SYSCLK source -------------------------------------------------------*/ switch (tmpreg & RCC_CFGR_SWS) 8005f04: 68fb ldr r3, [r7, #12] 8005f06: f003 030c and.w r3, r3, #12 8005f0a: 2b04 cmp r3, #4 8005f0c: d002 beq.n 8005f14 8005f0e: 2b08 cmp r3, #8 8005f10: d003 beq.n 8005f1a 8005f12: e026 b.n 8005f62 { case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ { sysclockfreq = HSE_VALUE; 8005f14: 4b19 ldr r3, [pc, #100] @ (8005f7c ) 8005f16: 613b str r3, [r7, #16] break; 8005f18: e026 b.n 8005f68 } case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ { pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_Pos]; 8005f1a: 68fb ldr r3, [r7, #12] 8005f1c: 0c9b lsrs r3, r3, #18 8005f1e: f003 030f and.w r3, r3, #15 8005f22: 4a17 ldr r2, [pc, #92] @ (8005f80 ) 8005f24: 5cd3 ldrb r3, [r2, r3] 8005f26: 607b str r3, [r7, #4] prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV) >> RCC_CFGR2_PREDIV_Pos]; 8005f28: 4b13 ldr r3, [pc, #76] @ (8005f78 ) 8005f2a: 6adb ldr r3, [r3, #44] @ 0x2c 8005f2c: f003 030f and.w r3, r3, #15 8005f30: 4a14 ldr r2, [pc, #80] @ (8005f84 ) 8005f32: 5cd3 ldrb r3, [r2, r3] 8005f34: 60bb str r3, [r7, #8] #if defined(RCC_CFGR_PLLSRC_HSI_DIV2) if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI) 8005f36: 68fb ldr r3, [r7, #12] 8005f38: f403 3380 and.w r3, r3, #65536 @ 0x10000 8005f3c: 2b00 cmp r3, #0 8005f3e: d008 beq.n 8005f52 { /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */ pllclk = (uint32_t)((uint64_t) HSE_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul); 8005f40: 4a0e ldr r2, [pc, #56] @ (8005f7c ) 8005f42: 68bb ldr r3, [r7, #8] 8005f44: fbb2 f2f3 udiv r2, r2, r3 8005f48: 687b ldr r3, [r7, #4] 8005f4a: fb02 f303 mul.w r3, r2, r3 8005f4e: 617b str r3, [r7, #20] 8005f50: e004 b.n 8005f5c } else { /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ pllclk = (uint32_t)((uint64_t) (HSI_VALUE >> 1U) * ((uint64_t) pllmul)); 8005f52: 687b ldr r3, [r7, #4] 8005f54: 4a0c ldr r2, [pc, #48] @ (8005f88 ) 8005f56: fb02 f303 mul.w r3, r2, r3 8005f5a: 617b str r3, [r7, #20] { /* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */ pllclk = (uint32_t)((uint64_t) HSI_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul); } #endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */ sysclockfreq = pllclk; 8005f5c: 697b ldr r3, [r7, #20] 8005f5e: 613b str r3, [r7, #16] break; 8005f60: e002 b.n 8005f68 } case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ default: /* HSI used as system clock */ { sysclockfreq = HSI_VALUE; 8005f62: 4b0a ldr r3, [pc, #40] @ (8005f8c ) 8005f64: 613b str r3, [r7, #16] break; 8005f66: bf00 nop } } return sysclockfreq; 8005f68: 693b ldr r3, [r7, #16] } 8005f6a: 4618 mov r0, r3 8005f6c: 371c adds r7, #28 8005f6e: 46bd mov sp, r7 8005f70: f85d 7b04 ldr.w r7, [sp], #4 8005f74: 4770 bx lr 8005f76: bf00 nop 8005f78: 40021000 .word 0x40021000 8005f7c: 00f42400 .word 0x00f42400 8005f80: 08007264 .word 0x08007264 8005f84: 08007274 .word 0x08007274 8005f88: 003d0900 .word 0x003d0900 8005f8c: 007a1200 .word 0x007a1200 08005f90 : * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency * and updated within this function * @retval HCLK frequency */ uint32_t HAL_RCC_GetHCLKFreq(void) { 8005f90: b480 push {r7} 8005f92: af00 add r7, sp, #0 return SystemCoreClock; 8005f94: 4b03 ldr r3, [pc, #12] @ (8005fa4 ) 8005f96: 681b ldr r3, [r3, #0] } 8005f98: 4618 mov r0, r3 8005f9a: 46bd mov sp, r7 8005f9c: f85d 7b04 ldr.w r7, [sp], #4 8005fa0: 4770 bx lr 8005fa2: bf00 nop 8005fa4: 20000000 .word 0x20000000 08005fa8 : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK1Freq(void) { 8005fa8: b580 push {r7, lr} 8005faa: b082 sub sp, #8 8005fac: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_BITNUMBER]); 8005fae: f7ff ffef bl 8005f90 8005fb2: 4601 mov r1, r0 8005fb4: 4b0b ldr r3, [pc, #44] @ (8005fe4 ) 8005fb6: 685b ldr r3, [r3, #4] 8005fb8: f403 63e0 and.w r3, r3, #1792 @ 0x700 8005fbc: f44f 62e0 mov.w r2, #1792 @ 0x700 8005fc0: 607a str r2, [r7, #4] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8005fc2: 687a ldr r2, [r7, #4] 8005fc4: fa92 f2a2 rbit r2, r2 8005fc8: 603a str r2, [r7, #0] return result; 8005fca: 683a ldr r2, [r7, #0] 8005fcc: fab2 f282 clz r2, r2 8005fd0: b2d2 uxtb r2, r2 8005fd2: 40d3 lsrs r3, r2 8005fd4: 4a04 ldr r2, [pc, #16] @ (8005fe8 ) 8005fd6: 5cd3 ldrb r3, [r2, r3] 8005fd8: fa21 f303 lsr.w r3, r1, r3 } 8005fdc: 4618 mov r0, r3 8005fde: 3708 adds r7, #8 8005fe0: 46bd mov sp, r7 8005fe2: bd80 pop {r7, pc} 8005fe4: 40021000 .word 0x40021000 8005fe8: 0800725c .word 0x0800725c 08005fec : * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK2 frequency */ uint32_t HAL_RCC_GetPCLK2Freq(void) { 8005fec: b580 push {r7, lr} 8005fee: b082 sub sp, #8 8005ff0: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_BITNUMBER]); 8005ff2: f7ff ffcd bl 8005f90 8005ff6: 4601 mov r1, r0 8005ff8: 4b0b ldr r3, [pc, #44] @ (8006028 ) 8005ffa: 685b ldr r3, [r3, #4] 8005ffc: f403 5360 and.w r3, r3, #14336 @ 0x3800 8006000: f44f 5260 mov.w r2, #14336 @ 0x3800 8006004: 607a str r2, [r7, #4] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8006006: 687a ldr r2, [r7, #4] 8006008: fa92 f2a2 rbit r2, r2 800600c: 603a str r2, [r7, #0] return result; 800600e: 683a ldr r2, [r7, #0] 8006010: fab2 f282 clz r2, r2 8006014: b2d2 uxtb r2, r2 8006016: 40d3 lsrs r3, r2 8006018: 4a04 ldr r2, [pc, #16] @ (800602c ) 800601a: 5cd3 ldrb r3, [r2, r3] 800601c: fa21 f303 lsr.w r3, r1, r3 } 8006020: 4618 mov r0, r3 8006022: 3708 adds r7, #8 8006024: 46bd mov sp, r7 8006026: bd80 pop {r7, pc} 8006028: 40021000 .word 0x40021000 800602c: 0800725c .word 0x0800725c 08006030 : * When the TIMx clock source is PLL clock, so the TIMx clock is PLL clock x 2. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 8006030: b580 push {r7, lr} 8006032: b092 sub sp, #72 @ 0x48 8006034: af00 add r7, sp, #0 8006036: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 8006038: 2300 movs r3, #0 800603a: 643b str r3, [r7, #64] @ 0x40 uint32_t temp_reg = 0U; 800603c: 2300 movs r3, #0 800603e: 63fb str r3, [r7, #60] @ 0x3c FlagStatus pwrclkchanged = RESET; 8006040: 2300 movs r3, #0 8006042: f887 3047 strb.w r3, [r7, #71] @ 0x47 /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); /*---------------------------- RTC configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) 8006046: 687b ldr r3, [r7, #4] 8006048: 681b ldr r3, [r3, #0] 800604a: f403 3380 and.w r3, r3, #65536 @ 0x10000 800604e: 2b00 cmp r3, #0 8006050: f000 80d4 beq.w 80061fc /* As soon as function is called to change RTC clock source, activation of the power domain is done. */ /* Requires to enable write access to Backup Domain of necessary */ if(__HAL_RCC_PWR_IS_CLK_DISABLED()) 8006054: 4b4e ldr r3, [pc, #312] @ (8006190 ) 8006056: 69db ldr r3, [r3, #28] 8006058: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 800605c: 2b00 cmp r3, #0 800605e: d10e bne.n 800607e { __HAL_RCC_PWR_CLK_ENABLE(); 8006060: 4b4b ldr r3, [pc, #300] @ (8006190 ) 8006062: 69db ldr r3, [r3, #28] 8006064: 4a4a ldr r2, [pc, #296] @ (8006190 ) 8006066: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 800606a: 61d3 str r3, [r2, #28] 800606c: 4b48 ldr r3, [pc, #288] @ (8006190 ) 800606e: 69db ldr r3, [r3, #28] 8006070: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8006074: 60bb str r3, [r7, #8] 8006076: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 8006078: 2301 movs r3, #1 800607a: f887 3047 strb.w r3, [r7, #71] @ 0x47 } if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 800607e: 4b45 ldr r3, [pc, #276] @ (8006194 ) 8006080: 681b ldr r3, [r3, #0] 8006082: f403 7380 and.w r3, r3, #256 @ 0x100 8006086: 2b00 cmp r3, #0 8006088: d118 bne.n 80060bc { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 800608a: 4b42 ldr r3, [pc, #264] @ (8006194 ) 800608c: 681b ldr r3, [r3, #0] 800608e: 4a41 ldr r2, [pc, #260] @ (8006194 ) 8006090: f443 7380 orr.w r3, r3, #256 @ 0x100 8006094: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8006096: f7fc f935 bl 8002304 800609a: 6438 str r0, [r7, #64] @ 0x40 while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 800609c: e008 b.n 80060b0 { if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 800609e: f7fc f931 bl 8002304 80060a2: 4602 mov r2, r0 80060a4: 6c3b ldr r3, [r7, #64] @ 0x40 80060a6: 1ad3 subs r3, r2, r3 80060a8: 2b64 cmp r3, #100 @ 0x64 80060aa: d901 bls.n 80060b0 { return HAL_TIMEOUT; 80060ac: 2303 movs r3, #3 80060ae: e14b b.n 8006348 while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 80060b0: 4b38 ldr r3, [pc, #224] @ (8006194 ) 80060b2: 681b ldr r3, [r3, #0] 80060b4: f403 7380 and.w r3, r3, #256 @ 0x100 80060b8: 2b00 cmp r3, #0 80060ba: d0f0 beq.n 800609e } } } /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL); 80060bc: 4b34 ldr r3, [pc, #208] @ (8006190 ) 80060be: 6a1b ldr r3, [r3, #32] 80060c0: f403 7340 and.w r3, r3, #768 @ 0x300 80060c4: 63fb str r3, [r7, #60] @ 0x3c if((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) 80060c6: 6bfb ldr r3, [r7, #60] @ 0x3c 80060c8: 2b00 cmp r3, #0 80060ca: f000 8084 beq.w 80061d6 80060ce: 687b ldr r3, [r7, #4] 80060d0: 685b ldr r3, [r3, #4] 80060d2: f403 7340 and.w r3, r3, #768 @ 0x300 80060d6: 6bfa ldr r2, [r7, #60] @ 0x3c 80060d8: 429a cmp r2, r3 80060da: d07c beq.n 80061d6 { /* Store the content of BDCR register before the reset of Backup Domain */ temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); 80060dc: 4b2c ldr r3, [pc, #176] @ (8006190 ) 80060de: 6a1b ldr r3, [r3, #32] 80060e0: f423 7340 bic.w r3, r3, #768 @ 0x300 80060e4: 63fb str r3, [r7, #60] @ 0x3c 80060e6: f44f 3380 mov.w r3, #65536 @ 0x10000 80060ea: 633b str r3, [r7, #48] @ 0x30 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 80060ec: 6b3b ldr r3, [r7, #48] @ 0x30 80060ee: fa93 f3a3 rbit r3, r3 80060f2: 62fb str r3, [r7, #44] @ 0x2c return result; 80060f4: 6afb ldr r3, [r7, #44] @ 0x2c /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); 80060f6: fab3 f383 clz r3, r3 80060fa: b2db uxtb r3, r3 80060fc: 461a mov r2, r3 80060fe: 4b26 ldr r3, [pc, #152] @ (8006198 ) 8006100: 4413 add r3, r2 8006102: 009b lsls r3, r3, #2 8006104: 461a mov r2, r3 8006106: 2301 movs r3, #1 8006108: 6013 str r3, [r2, #0] 800610a: f44f 3380 mov.w r3, #65536 @ 0x10000 800610e: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8006110: 6bbb ldr r3, [r7, #56] @ 0x38 8006112: fa93 f3a3 rbit r3, r3 8006116: 637b str r3, [r7, #52] @ 0x34 return result; 8006118: 6b7b ldr r3, [r7, #52] @ 0x34 __HAL_RCC_BACKUPRESET_RELEASE(); 800611a: fab3 f383 clz r3, r3 800611e: b2db uxtb r3, r3 8006120: 461a mov r2, r3 8006122: 4b1d ldr r3, [pc, #116] @ (8006198 ) 8006124: 4413 add r3, r2 8006126: 009b lsls r3, r3, #2 8006128: 461a mov r2, r3 800612a: 2300 movs r3, #0 800612c: 6013 str r3, [r2, #0] /* Restore the Content of BDCR register */ RCC->BDCR = temp_reg; 800612e: 4a18 ldr r2, [pc, #96] @ (8006190 ) 8006130: 6bfb ldr r3, [r7, #60] @ 0x3c 8006132: 6213 str r3, [r2, #32] /* Wait for LSERDY if LSE was enabled */ if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON)) 8006134: 6bfb ldr r3, [r7, #60] @ 0x3c 8006136: f003 0301 and.w r3, r3, #1 800613a: 2b00 cmp r3, #0 800613c: d04b beq.n 80061d6 { /* Get Start Tick */ tickstart = HAL_GetTick(); 800613e: f7fc f8e1 bl 8002304 8006142: 6438 str r0, [r7, #64] @ 0x40 /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8006144: e00a b.n 800615c { if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8006146: f7fc f8dd bl 8002304 800614a: 4602 mov r2, r0 800614c: 6c3b ldr r3, [r7, #64] @ 0x40 800614e: 1ad3 subs r3, r2, r3 8006150: f241 3288 movw r2, #5000 @ 0x1388 8006154: 4293 cmp r3, r2 8006156: d901 bls.n 800615c { return HAL_TIMEOUT; 8006158: 2303 movs r3, #3 800615a: e0f5 b.n 8006348 800615c: 2302 movs r3, #2 800615e: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8006160: 6abb ldr r3, [r7, #40] @ 0x28 8006162: fa93 f3a3 rbit r3, r3 8006166: 627b str r3, [r7, #36] @ 0x24 8006168: 2302 movs r3, #2 800616a: 623b str r3, [r7, #32] 800616c: 6a3b ldr r3, [r7, #32] 800616e: fa93 f3a3 rbit r3, r3 8006172: 61fb str r3, [r7, #28] return result; 8006174: 69fb ldr r3, [r7, #28] while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8006176: fab3 f383 clz r3, r3 800617a: b2db uxtb r3, r3 800617c: 095b lsrs r3, r3, #5 800617e: b2db uxtb r3, r3 8006180: f043 0302 orr.w r3, r3, #2 8006184: b2db uxtb r3, r3 8006186: 2b02 cmp r3, #2 8006188: d108 bne.n 800619c 800618a: 4b01 ldr r3, [pc, #4] @ (8006190 ) 800618c: 6a1b ldr r3, [r3, #32] 800618e: e00d b.n 80061ac 8006190: 40021000 .word 0x40021000 8006194: 40007000 .word 0x40007000 8006198: 10908100 .word 0x10908100 800619c: 2302 movs r3, #2 800619e: 61bb str r3, [r7, #24] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 80061a0: 69bb ldr r3, [r7, #24] 80061a2: fa93 f3a3 rbit r3, r3 80061a6: 617b str r3, [r7, #20] 80061a8: 4b69 ldr r3, [pc, #420] @ (8006350 ) 80061aa: 6a5b ldr r3, [r3, #36] @ 0x24 80061ac: 2202 movs r2, #2 80061ae: 613a str r2, [r7, #16] 80061b0: 693a ldr r2, [r7, #16] 80061b2: fa92 f2a2 rbit r2, r2 80061b6: 60fa str r2, [r7, #12] return result; 80061b8: 68fa ldr r2, [r7, #12] 80061ba: fab2 f282 clz r2, r2 80061be: b2d2 uxtb r2, r2 80061c0: f042 0240 orr.w r2, r2, #64 @ 0x40 80061c4: b2d2 uxtb r2, r2 80061c6: f002 021f and.w r2, r2, #31 80061ca: 2101 movs r1, #1 80061cc: fa01 f202 lsl.w r2, r1, r2 80061d0: 4013 ands r3, r2 80061d2: 2b00 cmp r3, #0 80061d4: d0b7 beq.n 8006146 } } } } __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 80061d6: 4b5e ldr r3, [pc, #376] @ (8006350 ) 80061d8: 6a1b ldr r3, [r3, #32] 80061da: f423 7240 bic.w r2, r3, #768 @ 0x300 80061de: 687b ldr r3, [r7, #4] 80061e0: 685b ldr r3, [r3, #4] 80061e2: 495b ldr r1, [pc, #364] @ (8006350 ) 80061e4: 4313 orrs r3, r2 80061e6: 620b str r3, [r1, #32] /* Require to disable power clock if necessary */ if(pwrclkchanged == SET) 80061e8: f897 3047 ldrb.w r3, [r7, #71] @ 0x47 80061ec: 2b01 cmp r3, #1 80061ee: d105 bne.n 80061fc { __HAL_RCC_PWR_CLK_DISABLE(); 80061f0: 4b57 ldr r3, [pc, #348] @ (8006350 ) 80061f2: 69db ldr r3, [r3, #28] 80061f4: 4a56 ldr r2, [pc, #344] @ (8006350 ) 80061f6: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 80061fa: 61d3 str r3, [r2, #28] } } /*------------------------------- USART1 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) 80061fc: 687b ldr r3, [r7, #4] 80061fe: 681b ldr r3, [r3, #0] 8006200: f003 0301 and.w r3, r3, #1 8006204: 2b00 cmp r3, #0 8006206: d008 beq.n 800621a { /* Check the parameters */ assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); /* Configure the USART1 clock source */ __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); 8006208: 4b51 ldr r3, [pc, #324] @ (8006350 ) 800620a: 6b1b ldr r3, [r3, #48] @ 0x30 800620c: f023 0203 bic.w r2, r3, #3 8006210: 687b ldr r3, [r7, #4] 8006212: 689b ldr r3, [r3, #8] 8006214: 494e ldr r1, [pc, #312] @ (8006350 ) 8006216: 4313 orrs r3, r2 8006218: 630b str r3, [r1, #48] @ 0x30 } #if defined(RCC_CFGR3_USART2SW) /*----------------------------- USART2 Configuration --------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) 800621a: 687b ldr r3, [r7, #4] 800621c: 681b ldr r3, [r3, #0] 800621e: f003 0302 and.w r3, r3, #2 8006222: 2b00 cmp r3, #0 8006224: d008 beq.n 8006238 { /* Check the parameters */ assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); /* Configure the USART2 clock source */ __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); 8006226: 4b4a ldr r3, [pc, #296] @ (8006350 ) 8006228: 6b1b ldr r3, [r3, #48] @ 0x30 800622a: f423 3240 bic.w r2, r3, #196608 @ 0x30000 800622e: 687b ldr r3, [r7, #4] 8006230: 68db ldr r3, [r3, #12] 8006232: 4947 ldr r1, [pc, #284] @ (8006350 ) 8006234: 4313 orrs r3, r2 8006236: 630b str r3, [r1, #48] @ 0x30 } #endif /* RCC_CFGR3_USART2SW */ #if defined(RCC_CFGR3_USART3SW) /*------------------------------ USART3 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) 8006238: 687b ldr r3, [r7, #4] 800623a: 681b ldr r3, [r3, #0] 800623c: f003 0304 and.w r3, r3, #4 8006240: 2b00 cmp r3, #0 8006242: d008 beq.n 8006256 { /* Check the parameters */ assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection)); /* Configure the USART3 clock source */ __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection); 8006244: 4b42 ldr r3, [pc, #264] @ (8006350 ) 8006246: 6b1b ldr r3, [r3, #48] @ 0x30 8006248: f423 2240 bic.w r2, r3, #786432 @ 0xc0000 800624c: 687b ldr r3, [r7, #4] 800624e: 691b ldr r3, [r3, #16] 8006250: 493f ldr r1, [pc, #252] @ (8006350 ) 8006252: 4313 orrs r3, r2 8006254: 630b str r3, [r1, #48] @ 0x30 } #endif /* RCC_CFGR3_USART3SW */ /*------------------------------ I2C1 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) 8006256: 687b ldr r3, [r7, #4] 8006258: 681b ldr r3, [r3, #0] 800625a: f003 0320 and.w r3, r3, #32 800625e: 2b00 cmp r3, #0 8006260: d008 beq.n 8006274 { /* Check the parameters */ assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); /* Configure the I2C1 clock source */ __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); 8006262: 4b3b ldr r3, [pc, #236] @ (8006350 ) 8006264: 6b1b ldr r3, [r3, #48] @ 0x30 8006266: f023 0210 bic.w r2, r3, #16 800626a: 687b ldr r3, [r7, #4] 800626c: 69db ldr r3, [r3, #28] 800626e: 4938 ldr r1, [pc, #224] @ (8006350 ) 8006270: 4313 orrs r3, r2 8006272: 630b str r3, [r1, #48] @ 0x30 #if defined(STM32F302xE) || defined(STM32F303xE)\ || defined(STM32F302xC) || defined(STM32F303xC)\ || defined(STM32F302x8) \ || defined(STM32F373xC) /*------------------------------ USB Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) 8006274: 687b ldr r3, [r7, #4] 8006276: 681b ldr r3, [r3, #0] 8006278: f403 3300 and.w r3, r3, #131072 @ 0x20000 800627c: 2b00 cmp r3, #0 800627e: d008 beq.n 8006292 { /* Check the parameters */ assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->USBClockSelection)); /* Configure the USB clock source */ __HAL_RCC_USB_CONFIG(PeriphClkInit->USBClockSelection); 8006280: 4b33 ldr r3, [pc, #204] @ (8006350 ) 8006282: 685b ldr r3, [r3, #4] 8006284: f423 0280 bic.w r2, r3, #4194304 @ 0x400000 8006288: 687b ldr r3, [r7, #4] 800628a: 6b1b ldr r3, [r3, #48] @ 0x30 800628c: 4930 ldr r1, [pc, #192] @ (8006350 ) 800628e: 4313 orrs r3, r2 8006290: 604b str r3, [r1, #4] || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\ || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)\ || defined(STM32F373xC) || defined(STM32F378xx) /*------------------------------ I2C2 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) 8006292: 687b ldr r3, [r7, #4] 8006294: 681b ldr r3, [r3, #0] 8006296: f003 0340 and.w r3, r3, #64 @ 0x40 800629a: 2b00 cmp r3, #0 800629c: d008 beq.n 80062b0 { /* Check the parameters */ assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection)); /* Configure the I2C2 clock source */ __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection); 800629e: 4b2c ldr r3, [pc, #176] @ (8006350 ) 80062a0: 6b1b ldr r3, [r3, #48] @ 0x30 80062a2: f023 0220 bic.w r2, r3, #32 80062a6: 687b ldr r3, [r7, #4] 80062a8: 6a1b ldr r3, [r3, #32] 80062aa: 4929 ldr r1, [pc, #164] @ (8006350 ) 80062ac: 4313 orrs r3, r2 80062ae: 630b str r3, [r1, #48] @ 0x30 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) /*------------------------------ UART4 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) 80062b0: 687b ldr r3, [r7, #4] 80062b2: 681b ldr r3, [r3, #0] 80062b4: f003 0308 and.w r3, r3, #8 80062b8: 2b00 cmp r3, #0 80062ba: d008 beq.n 80062ce { /* Check the parameters */ assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection)); /* Configure the UART4 clock source */ __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection); 80062bc: 4b24 ldr r3, [pc, #144] @ (8006350 ) 80062be: 6b1b ldr r3, [r3, #48] @ 0x30 80062c0: f423 1240 bic.w r2, r3, #3145728 @ 0x300000 80062c4: 687b ldr r3, [r7, #4] 80062c6: 695b ldr r3, [r3, #20] 80062c8: 4921 ldr r1, [pc, #132] @ (8006350 ) 80062ca: 4313 orrs r3, r2 80062cc: 630b str r3, [r1, #48] @ 0x30 } /*------------------------------ UART5 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) 80062ce: 687b ldr r3, [r7, #4] 80062d0: 681b ldr r3, [r3, #0] 80062d2: f003 0310 and.w r3, r3, #16 80062d6: 2b00 cmp r3, #0 80062d8: d008 beq.n 80062ec { /* Check the parameters */ assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection)); /* Configure the UART5 clock source */ __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection); 80062da: 4b1d ldr r3, [pc, #116] @ (8006350 ) 80062dc: 6b1b ldr r3, [r3, #48] @ 0x30 80062de: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000 80062e2: 687b ldr r3, [r7, #4] 80062e4: 699b ldr r3, [r3, #24] 80062e6: 491a ldr r1, [pc, #104] @ (8006350 ) 80062e8: 4313 orrs r3, r2 80062ea: 630b str r3, [r1, #48] @ 0x30 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\ || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) /*------------------------------ I2S Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) 80062ec: 687b ldr r3, [r7, #4] 80062ee: 681b ldr r3, [r3, #0] 80062f0: f403 7300 and.w r3, r3, #512 @ 0x200 80062f4: 2b00 cmp r3, #0 80062f6: d008 beq.n 800630a { /* Check the parameters */ assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection)); /* Configure the I2S clock source */ __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection); 80062f8: 4b15 ldr r3, [pc, #84] @ (8006350 ) 80062fa: 685b ldr r3, [r3, #4] 80062fc: f423 0200 bic.w r2, r3, #8388608 @ 0x800000 8006300: 687b ldr r3, [r7, #4] 8006302: 6a9b ldr r3, [r3, #40] @ 0x28 8006304: 4912 ldr r1, [pc, #72] @ (8006350 ) 8006306: 4313 orrs r3, r2 8006308: 604b str r3, [r1, #4] #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\ || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) /*------------------------------ ADC1 & ADC2 clock Configuration -------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) 800630a: 687b ldr r3, [r7, #4] 800630c: 681b ldr r3, [r3, #0] 800630e: f003 0380 and.w r3, r3, #128 @ 0x80 8006312: 2b00 cmp r3, #0 8006314: d008 beq.n 8006328 { /* Check the parameters */ assert_param(IS_RCC_ADC12PLLCLK_DIV(PeriphClkInit->Adc12ClockSelection)); /* Configure the ADC12 clock source */ __HAL_RCC_ADC12_CONFIG(PeriphClkInit->Adc12ClockSelection); 8006316: 4b0e ldr r3, [pc, #56] @ (8006350 ) 8006318: 6adb ldr r3, [r3, #44] @ 0x2c 800631a: f423 72f8 bic.w r2, r3, #496 @ 0x1f0 800631e: 687b ldr r3, [r7, #4] 8006320: 6a5b ldr r3, [r3, #36] @ 0x24 8006322: 490b ldr r1, [pc, #44] @ (8006350 ) 8006324: 4313 orrs r3, r2 8006326: 62cb str r3, [r1, #44] @ 0x2c || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\ || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\ || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) /*------------------------------ TIM1 clock Configuration ----------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1) 8006328: 687b ldr r3, [r7, #4] 800632a: 681b ldr r3, [r3, #0] 800632c: f403 5380 and.w r3, r3, #4096 @ 0x1000 8006330: 2b00 cmp r3, #0 8006332: d008 beq.n 8006346 { /* Check the parameters */ assert_param(IS_RCC_TIM1CLKSOURCE(PeriphClkInit->Tim1ClockSelection)); /* Configure the TIM1 clock source */ __HAL_RCC_TIM1_CONFIG(PeriphClkInit->Tim1ClockSelection); 8006334: 4b06 ldr r3, [pc, #24] @ (8006350 ) 8006336: 6b1b ldr r3, [r3, #48] @ 0x30 8006338: f423 7280 bic.w r2, r3, #256 @ 0x100 800633c: 687b ldr r3, [r7, #4] 800633e: 6adb ldr r3, [r3, #44] @ 0x2c 8006340: 4903 ldr r1, [pc, #12] @ (8006350 ) 8006342: 4313 orrs r3, r2 8006344: 630b str r3, [r1, #48] @ 0x30 __HAL_RCC_TIM20_CONFIG(PeriphClkInit->Tim20ClockSelection); } #endif /* STM32F303xE || STM32F398xx */ return HAL_OK; 8006346: 2300 movs r3, #0 } 8006348: 4618 mov r0, r3 800634a: 3748 adds r7, #72 @ 0x48 800634c: 46bd mov sp, r7 800634e: bd80 pop {r7, pc} 8006350: 40021000 .word 0x40021000 08006354 : * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { 8006354: b580 push {r7, lr} 8006356: b082 sub sp, #8 8006358: af00 add r7, sp, #0 800635a: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 800635c: 687b ldr r3, [r7, #4] 800635e: 2b00 cmp r3, #0 8006360: d101 bne.n 8006366 { return HAL_ERROR; 8006362: 2301 movs r3, #1 8006364: e049 b.n 80063fa assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 8006366: 687b ldr r3, [r7, #4] 8006368: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 800636c: b2db uxtb r3, r3 800636e: 2b00 cmp r3, #0 8006370: d106 bne.n 8006380 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 8006372: 687b ldr r3, [r7, #4] 8006374: 2200 movs r2, #0 8006376: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Base_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspInit(htim); 800637a: 6878 ldr r0, [r7, #4] 800637c: f7fb fe52 bl 8002024 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8006380: 687b ldr r3, [r7, #4] 8006382: 2202 movs r2, #2 8006384: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 8006388: 687b ldr r3, [r7, #4] 800638a: 681a ldr r2, [r3, #0] 800638c: 687b ldr r3, [r7, #4] 800638e: 3304 adds r3, #4 8006390: 4619 mov r1, r3 8006392: 4610 mov r0, r2 8006394: f000 f9c4 bl 8006720 /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 8006398: 687b ldr r3, [r7, #4] 800639a: 2201 movs r2, #1 800639c: f883 2048 strb.w r2, [r3, #72] @ 0x48 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 80063a0: 687b ldr r3, [r7, #4] 80063a2: 2201 movs r2, #1 80063a4: f883 203e strb.w r2, [r3, #62] @ 0x3e 80063a8: 687b ldr r3, [r7, #4] 80063aa: 2201 movs r2, #1 80063ac: f883 203f strb.w r2, [r3, #63] @ 0x3f 80063b0: 687b ldr r3, [r7, #4] 80063b2: 2201 movs r2, #1 80063b4: f883 2040 strb.w r2, [r3, #64] @ 0x40 80063b8: 687b ldr r3, [r7, #4] 80063ba: 2201 movs r2, #1 80063bc: f883 2041 strb.w r2, [r3, #65] @ 0x41 80063c0: 687b ldr r3, [r7, #4] 80063c2: 2201 movs r2, #1 80063c4: f883 2042 strb.w r2, [r3, #66] @ 0x42 80063c8: 687b ldr r3, [r7, #4] 80063ca: 2201 movs r2, #1 80063cc: f883 2043 strb.w r2, [r3, #67] @ 0x43 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 80063d0: 687b ldr r3, [r7, #4] 80063d2: 2201 movs r2, #1 80063d4: f883 2044 strb.w r2, [r3, #68] @ 0x44 80063d8: 687b ldr r3, [r7, #4] 80063da: 2201 movs r2, #1 80063dc: f883 2045 strb.w r2, [r3, #69] @ 0x45 80063e0: 687b ldr r3, [r7, #4] 80063e2: 2201 movs r2, #1 80063e4: f883 2046 strb.w r2, [r3, #70] @ 0x46 80063e8: 687b ldr r3, [r7, #4] 80063ea: 2201 movs r2, #1 80063ec: f883 2047 strb.w r2, [r3, #71] @ 0x47 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 80063f0: 687b ldr r3, [r7, #4] 80063f2: 2201 movs r2, #1 80063f4: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 80063f8: 2300 movs r3, #0 } 80063fa: 4618 mov r0, r3 80063fc: 3708 adds r7, #8 80063fe: 46bd mov sp, r7 8006400: bd80 pop {r7, pc} ... 08006404 : * @brief Starts the TIM Base generation. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) { 8006404: b480 push {r7} 8006406: b085 sub sp, #20 8006408: af00 add r7, sp, #0 800640a: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Check the TIM state */ if (htim->State != HAL_TIM_STATE_READY) 800640c: 687b ldr r3, [r7, #4] 800640e: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 8006412: b2db uxtb r3, r3 8006414: 2b01 cmp r3, #1 8006416: d001 beq.n 800641c { return HAL_ERROR; 8006418: 2301 movs r3, #1 800641a: e03d b.n 8006498 } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 800641c: 687b ldr r3, [r7, #4] 800641e: 2202 movs r2, #2 8006420: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8006424: 687b ldr r3, [r7, #4] 8006426: 681b ldr r3, [r3, #0] 8006428: 4a1e ldr r2, [pc, #120] @ (80064a4 ) 800642a: 4293 cmp r3, r2 800642c: d013 beq.n 8006456 800642e: 687b ldr r3, [r7, #4] 8006430: 681b ldr r3, [r3, #0] 8006432: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8006436: d00e beq.n 8006456 8006438: 687b ldr r3, [r7, #4] 800643a: 681b ldr r3, [r3, #0] 800643c: 4a1a ldr r2, [pc, #104] @ (80064a8 ) 800643e: 4293 cmp r3, r2 8006440: d009 beq.n 8006456 8006442: 687b ldr r3, [r7, #4] 8006444: 681b ldr r3, [r3, #0] 8006446: 4a19 ldr r2, [pc, #100] @ (80064ac ) 8006448: 4293 cmp r3, r2 800644a: d004 beq.n 8006456 800644c: 687b ldr r3, [r7, #4] 800644e: 681b ldr r3, [r3, #0] 8006450: 4a17 ldr r2, [pc, #92] @ (80064b0 ) 8006452: 4293 cmp r3, r2 8006454: d115 bne.n 8006482 { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 8006456: 687b ldr r3, [r7, #4] 8006458: 681b ldr r3, [r3, #0] 800645a: 689a ldr r2, [r3, #8] 800645c: 4b15 ldr r3, [pc, #84] @ (80064b4 ) 800645e: 4013 ands r3, r2 8006460: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 8006462: 68fb ldr r3, [r7, #12] 8006464: 2b06 cmp r3, #6 8006466: d015 beq.n 8006494 8006468: 68fb ldr r3, [r7, #12] 800646a: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800646e: d011 beq.n 8006494 { __HAL_TIM_ENABLE(htim); 8006470: 687b ldr r3, [r7, #4] 8006472: 681b ldr r3, [r3, #0] 8006474: 681a ldr r2, [r3, #0] 8006476: 687b ldr r3, [r7, #4] 8006478: 681b ldr r3, [r3, #0] 800647a: f042 0201 orr.w r2, r2, #1 800647e: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 8006480: e008 b.n 8006494 } } else { __HAL_TIM_ENABLE(htim); 8006482: 687b ldr r3, [r7, #4] 8006484: 681b ldr r3, [r3, #0] 8006486: 681a ldr r2, [r3, #0] 8006488: 687b ldr r3, [r7, #4] 800648a: 681b ldr r3, [r3, #0] 800648c: f042 0201 orr.w r2, r2, #1 8006490: 601a str r2, [r3, #0] 8006492: e000 b.n 8006496 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 8006494: bf00 nop } /* Return function status */ return HAL_OK; 8006496: 2300 movs r3, #0 } 8006498: 4618 mov r0, r3 800649a: 3714 adds r7, #20 800649c: 46bd mov sp, r7 800649e: f85d 7b04 ldr.w r7, [sp], #4 80064a2: 4770 bx lr 80064a4: 40012c00 .word 0x40012c00 80064a8: 40000400 .word 0x40000400 80064ac: 40000800 .word 0x40000800 80064b0: 40014000 .word 0x40014000 80064b4: 00010007 .word 0x00010007 080064b8 : * @brief This function handles TIM interrupts requests. * @param htim TIM handle * @retval None */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { 80064b8: b580 push {r7, lr} 80064ba: b084 sub sp, #16 80064bc: af00 add r7, sp, #0 80064be: 6078 str r0, [r7, #4] uint32_t itsource = htim->Instance->DIER; 80064c0: 687b ldr r3, [r7, #4] 80064c2: 681b ldr r3, [r3, #0] 80064c4: 68db ldr r3, [r3, #12] 80064c6: 60fb str r3, [r7, #12] uint32_t itflag = htim->Instance->SR; 80064c8: 687b ldr r3, [r7, #4] 80064ca: 681b ldr r3, [r3, #0] 80064cc: 691b ldr r3, [r3, #16] 80064ce: 60bb str r3, [r7, #8] /* Capture compare 1 event */ if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1)) 80064d0: 68bb ldr r3, [r7, #8] 80064d2: f003 0302 and.w r3, r3, #2 80064d6: 2b00 cmp r3, #0 80064d8: d020 beq.n 800651c { if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1)) 80064da: 68fb ldr r3, [r7, #12] 80064dc: f003 0302 and.w r3, r3, #2 80064e0: 2b00 cmp r3, #0 80064e2: d01b beq.n 800651c { { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1); 80064e4: 687b ldr r3, [r7, #4] 80064e6: 681b ldr r3, [r3, #0] 80064e8: f06f 0202 mvn.w r2, #2 80064ec: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; 80064ee: 687b ldr r3, [r7, #4] 80064f0: 2201 movs r2, #1 80064f2: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) 80064f4: 687b ldr r3, [r7, #4] 80064f6: 681b ldr r3, [r3, #0] 80064f8: 699b ldr r3, [r3, #24] 80064fa: f003 0303 and.w r3, r3, #3 80064fe: 2b00 cmp r3, #0 8006500: d003 beq.n 800650a { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 8006502: 6878 ldr r0, [r7, #4] 8006504: f000 f8ee bl 80066e4 8006508: e005 b.n 8006516 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 800650a: 6878 ldr r0, [r7, #4] 800650c: f000 f8e0 bl 80066d0 HAL_TIM_PWM_PulseFinishedCallback(htim); 8006510: 6878 ldr r0, [r7, #4] 8006512: f000 f8f1 bl 80066f8 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8006516: 687b ldr r3, [r7, #4] 8006518: 2200 movs r2, #0 800651a: 771a strb r2, [r3, #28] } } } /* Capture compare 2 event */ if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2)) 800651c: 68bb ldr r3, [r7, #8] 800651e: f003 0304 and.w r3, r3, #4 8006522: 2b00 cmp r3, #0 8006524: d020 beq.n 8006568 { if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2)) 8006526: 68fb ldr r3, [r7, #12] 8006528: f003 0304 and.w r3, r3, #4 800652c: 2b00 cmp r3, #0 800652e: d01b beq.n 8006568 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2); 8006530: 687b ldr r3, [r7, #4] 8006532: 681b ldr r3, [r3, #0] 8006534: f06f 0204 mvn.w r2, #4 8006538: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; 800653a: 687b ldr r3, [r7, #4] 800653c: 2202 movs r2, #2 800653e: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) 8006540: 687b ldr r3, [r7, #4] 8006542: 681b ldr r3, [r3, #0] 8006544: 699b ldr r3, [r3, #24] 8006546: f403 7340 and.w r3, r3, #768 @ 0x300 800654a: 2b00 cmp r3, #0 800654c: d003 beq.n 8006556 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 800654e: 6878 ldr r0, [r7, #4] 8006550: f000 f8c8 bl 80066e4 8006554: e005 b.n 8006562 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 8006556: 6878 ldr r0, [r7, #4] 8006558: f000 f8ba bl 80066d0 HAL_TIM_PWM_PulseFinishedCallback(htim); 800655c: 6878 ldr r0, [r7, #4] 800655e: f000 f8cb bl 80066f8 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8006562: 687b ldr r3, [r7, #4] 8006564: 2200 movs r2, #0 8006566: 771a strb r2, [r3, #28] } } /* Capture compare 3 event */ if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3)) 8006568: 68bb ldr r3, [r7, #8] 800656a: f003 0308 and.w r3, r3, #8 800656e: 2b00 cmp r3, #0 8006570: d020 beq.n 80065b4 { if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3)) 8006572: 68fb ldr r3, [r7, #12] 8006574: f003 0308 and.w r3, r3, #8 8006578: 2b00 cmp r3, #0 800657a: d01b beq.n 80065b4 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3); 800657c: 687b ldr r3, [r7, #4] 800657e: 681b ldr r3, [r3, #0] 8006580: f06f 0208 mvn.w r2, #8 8006584: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; 8006586: 687b ldr r3, [r7, #4] 8006588: 2204 movs r2, #4 800658a: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) 800658c: 687b ldr r3, [r7, #4] 800658e: 681b ldr r3, [r3, #0] 8006590: 69db ldr r3, [r3, #28] 8006592: f003 0303 and.w r3, r3, #3 8006596: 2b00 cmp r3, #0 8006598: d003 beq.n 80065a2 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 800659a: 6878 ldr r0, [r7, #4] 800659c: f000 f8a2 bl 80066e4 80065a0: e005 b.n 80065ae { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 80065a2: 6878 ldr r0, [r7, #4] 80065a4: f000 f894 bl 80066d0 HAL_TIM_PWM_PulseFinishedCallback(htim); 80065a8: 6878 ldr r0, [r7, #4] 80065aa: f000 f8a5 bl 80066f8 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 80065ae: 687b ldr r3, [r7, #4] 80065b0: 2200 movs r2, #0 80065b2: 771a strb r2, [r3, #28] } } /* Capture compare 4 event */ if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4)) 80065b4: 68bb ldr r3, [r7, #8] 80065b6: f003 0310 and.w r3, r3, #16 80065ba: 2b00 cmp r3, #0 80065bc: d020 beq.n 8006600 { if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4)) 80065be: 68fb ldr r3, [r7, #12] 80065c0: f003 0310 and.w r3, r3, #16 80065c4: 2b00 cmp r3, #0 80065c6: d01b beq.n 8006600 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4); 80065c8: 687b ldr r3, [r7, #4] 80065ca: 681b ldr r3, [r3, #0] 80065cc: f06f 0210 mvn.w r2, #16 80065d0: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; 80065d2: 687b ldr r3, [r7, #4] 80065d4: 2208 movs r2, #8 80065d6: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) 80065d8: 687b ldr r3, [r7, #4] 80065da: 681b ldr r3, [r3, #0] 80065dc: 69db ldr r3, [r3, #28] 80065de: f403 7340 and.w r3, r3, #768 @ 0x300 80065e2: 2b00 cmp r3, #0 80065e4: d003 beq.n 80065ee { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 80065e6: 6878 ldr r0, [r7, #4] 80065e8: f000 f87c bl 80066e4 80065ec: e005 b.n 80065fa { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 80065ee: 6878 ldr r0, [r7, #4] 80065f0: f000 f86e bl 80066d0 HAL_TIM_PWM_PulseFinishedCallback(htim); 80065f4: 6878 ldr r0, [r7, #4] 80065f6: f000 f87f bl 80066f8 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 80065fa: 687b ldr r3, [r7, #4] 80065fc: 2200 movs r2, #0 80065fe: 771a strb r2, [r3, #28] } } /* TIM Update event */ if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE)) 8006600: 68bb ldr r3, [r7, #8] 8006602: f003 0301 and.w r3, r3, #1 8006606: 2b00 cmp r3, #0 8006608: d00c beq.n 8006624 { if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE)) 800660a: 68fb ldr r3, [r7, #12] 800660c: f003 0301 and.w r3, r3, #1 8006610: 2b00 cmp r3, #0 8006612: d007 beq.n 8006624 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE); 8006614: 687b ldr r3, [r7, #4] 8006616: 681b ldr r3, [r3, #0] 8006618: f06f 0201 mvn.w r2, #1 800661c: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else HAL_TIM_PeriodElapsedCallback(htim); 800661e: 6878 ldr r0, [r7, #4] 8006620: f000 f84c bl 80066bc #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break input event */ if ((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) 8006624: 68bb ldr r3, [r7, #8] 8006626: f003 0380 and.w r3, r3, #128 @ 0x80 800662a: 2b00 cmp r3, #0 800662c: d00c beq.n 8006648 { if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) 800662e: 68fb ldr r3, [r7, #12] 8006630: f003 0380 and.w r3, r3, #128 @ 0x80 8006634: 2b00 cmp r3, #0 8006636: d007 beq.n 8006648 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK); 8006638: 687b ldr r3, [r7, #4] 800663a: 681b ldr r3, [r3, #0] 800663c: f06f 0280 mvn.w r2, #128 @ 0x80 8006640: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->BreakCallback(htim); #else HAL_TIMEx_BreakCallback(htim); 8006642: 6878 ldr r0, [r7, #4] 8006644: f000 f978 bl 8006938 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } #if defined(TIM_BDTR_BK2E) /* TIM Break2 input event */ if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2)) 8006648: 68bb ldr r3, [r7, #8] 800664a: f403 7380 and.w r3, r3, #256 @ 0x100 800664e: 2b00 cmp r3, #0 8006650: d00c beq.n 800666c { if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) 8006652: 68fb ldr r3, [r7, #12] 8006654: f003 0380 and.w r3, r3, #128 @ 0x80 8006658: 2b00 cmp r3, #0 800665a: d007 beq.n 800666c { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2); 800665c: 687b ldr r3, [r7, #4] 800665e: 681b ldr r3, [r3, #0] 8006660: f46f 7280 mvn.w r2, #256 @ 0x100 8006664: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->Break2Callback(htim); #else HAL_TIMEx_Break2Callback(htim); 8006666: 6878 ldr r0, [r7, #4] 8006668: f000 f970 bl 800694c #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } #endif /* TIM_BDTR_BK2E */ /* TIM Trigger detection event */ if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER)) 800666c: 68bb ldr r3, [r7, #8] 800666e: f003 0340 and.w r3, r3, #64 @ 0x40 8006672: 2b00 cmp r3, #0 8006674: d00c beq.n 8006690 { if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER)) 8006676: 68fb ldr r3, [r7, #12] 8006678: f003 0340 and.w r3, r3, #64 @ 0x40 800667c: 2b00 cmp r3, #0 800667e: d007 beq.n 8006690 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER); 8006680: 687b ldr r3, [r7, #4] 8006682: 681b ldr r3, [r3, #0] 8006684: f06f 0240 mvn.w r2, #64 @ 0x40 8006688: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else HAL_TIM_TriggerCallback(htim); 800668a: 6878 ldr r0, [r7, #4] 800668c: f000 f83e bl 800670c #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM commutation event */ if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM)) 8006690: 68bb ldr r3, [r7, #8] 8006692: f003 0320 and.w r3, r3, #32 8006696: 2b00 cmp r3, #0 8006698: d00c beq.n 80066b4 { if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM)) 800669a: 68fb ldr r3, [r7, #12] 800669c: f003 0320 and.w r3, r3, #32 80066a0: 2b00 cmp r3, #0 80066a2: d007 beq.n 80066b4 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM); 80066a4: 687b ldr r3, [r7, #4] 80066a6: 681b ldr r3, [r3, #0] 80066a8: f06f 0220 mvn.w r2, #32 80066ac: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationCallback(htim); #else HAL_TIMEx_CommutCallback(htim); 80066ae: 6878 ldr r0, [r7, #4] 80066b0: f000 f938 bl 8006924 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } } 80066b4: bf00 nop 80066b6: 3710 adds r7, #16 80066b8: 46bd mov sp, r7 80066ba: bd80 pop {r7, pc} 080066bc : * @brief Period elapsed callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { 80066bc: b480 push {r7} 80066be: b083 sub sp, #12 80066c0: af00 add r7, sp, #0 80066c2: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PeriodElapsedCallback could be implemented in the user file */ } 80066c4: bf00 nop 80066c6: 370c adds r7, #12 80066c8: 46bd mov sp, r7 80066ca: f85d 7b04 ldr.w r7, [sp], #4 80066ce: 4770 bx lr 080066d0 : * @brief Output Compare callback in non-blocking mode * @param htim TIM OC handle * @retval None */ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) { 80066d0: b480 push {r7} 80066d2: b083 sub sp, #12 80066d4: af00 add r7, sp, #0 80066d6: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file */ } 80066d8: bf00 nop 80066da: 370c adds r7, #12 80066dc: 46bd mov sp, r7 80066de: f85d 7b04 ldr.w r7, [sp], #4 80066e2: 4770 bx lr 080066e4 : * @brief Input Capture callback in non-blocking mode * @param htim TIM IC handle * @retval None */ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) { 80066e4: b480 push {r7} 80066e6: b083 sub sp, #12 80066e8: af00 add r7, sp, #0 80066ea: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_CaptureCallback could be implemented in the user file */ } 80066ec: bf00 nop 80066ee: 370c adds r7, #12 80066f0: 46bd mov sp, r7 80066f2: f85d 7b04 ldr.w r7, [sp], #4 80066f6: 4770 bx lr 080066f8 : * @brief PWM Pulse finished callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) { 80066f8: b480 push {r7} 80066fa: b083 sub sp, #12 80066fc: af00 add r7, sp, #0 80066fe: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file */ } 8006700: bf00 nop 8006702: 370c adds r7, #12 8006704: 46bd mov sp, r7 8006706: f85d 7b04 ldr.w r7, [sp], #4 800670a: 4770 bx lr 0800670c : * @brief Hall Trigger detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) { 800670c: b480 push {r7} 800670e: b083 sub sp, #12 8006710: af00 add r7, sp, #0 8006712: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_TriggerCallback could be implemented in the user file */ } 8006714: bf00 nop 8006716: 370c adds r7, #12 8006718: 46bd mov sp, r7 800671a: f85d 7b04 ldr.w r7, [sp], #4 800671e: 4770 bx lr 08006720 : * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) { 8006720: b480 push {r7} 8006722: b085 sub sp, #20 8006724: af00 add r7, sp, #0 8006726: 6078 str r0, [r7, #4] 8006728: 6039 str r1, [r7, #0] uint32_t tmpcr1; tmpcr1 = TIMx->CR1; 800672a: 687b ldr r3, [r7, #4] 800672c: 681b ldr r3, [r3, #0] 800672e: 60fb str r3, [r7, #12] /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 8006730: 687b ldr r3, [r7, #4] 8006732: 4a3c ldr r2, [pc, #240] @ (8006824 ) 8006734: 4293 cmp r3, r2 8006736: d00b beq.n 8006750 8006738: 687b ldr r3, [r7, #4] 800673a: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800673e: d007 beq.n 8006750 8006740: 687b ldr r3, [r7, #4] 8006742: 4a39 ldr r2, [pc, #228] @ (8006828 ) 8006744: 4293 cmp r3, r2 8006746: d003 beq.n 8006750 8006748: 687b ldr r3, [r7, #4] 800674a: 4a38 ldr r2, [pc, #224] @ (800682c ) 800674c: 4293 cmp r3, r2 800674e: d108 bne.n 8006762 { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 8006750: 68fb ldr r3, [r7, #12] 8006752: f023 0370 bic.w r3, r3, #112 @ 0x70 8006756: 60fb str r3, [r7, #12] tmpcr1 |= Structure->CounterMode; 8006758: 683b ldr r3, [r7, #0] 800675a: 685b ldr r3, [r3, #4] 800675c: 68fa ldr r2, [r7, #12] 800675e: 4313 orrs r3, r2 8006760: 60fb str r3, [r7, #12] } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 8006762: 687b ldr r3, [r7, #4] 8006764: 4a2f ldr r2, [pc, #188] @ (8006824 ) 8006766: 4293 cmp r3, r2 8006768: d017 beq.n 800679a 800676a: 687b ldr r3, [r7, #4] 800676c: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8006770: d013 beq.n 800679a 8006772: 687b ldr r3, [r7, #4] 8006774: 4a2c ldr r2, [pc, #176] @ (8006828 ) 8006776: 4293 cmp r3, r2 8006778: d00f beq.n 800679a 800677a: 687b ldr r3, [r7, #4] 800677c: 4a2b ldr r2, [pc, #172] @ (800682c ) 800677e: 4293 cmp r3, r2 8006780: d00b beq.n 800679a 8006782: 687b ldr r3, [r7, #4] 8006784: 4a2a ldr r2, [pc, #168] @ (8006830 ) 8006786: 4293 cmp r3, r2 8006788: d007 beq.n 800679a 800678a: 687b ldr r3, [r7, #4] 800678c: 4a29 ldr r2, [pc, #164] @ (8006834 ) 800678e: 4293 cmp r3, r2 8006790: d003 beq.n 800679a 8006792: 687b ldr r3, [r7, #4] 8006794: 4a28 ldr r2, [pc, #160] @ (8006838 ) 8006796: 4293 cmp r3, r2 8006798: d108 bne.n 80067ac { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; 800679a: 68fb ldr r3, [r7, #12] 800679c: f423 7340 bic.w r3, r3, #768 @ 0x300 80067a0: 60fb str r3, [r7, #12] tmpcr1 |= (uint32_t)Structure->ClockDivision; 80067a2: 683b ldr r3, [r7, #0] 80067a4: 68db ldr r3, [r3, #12] 80067a6: 68fa ldr r2, [r7, #12] 80067a8: 4313 orrs r3, r2 80067aa: 60fb str r3, [r7, #12] } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 80067ac: 68fb ldr r3, [r7, #12] 80067ae: f023 0280 bic.w r2, r3, #128 @ 0x80 80067b2: 683b ldr r3, [r7, #0] 80067b4: 695b ldr r3, [r3, #20] 80067b6: 4313 orrs r3, r2 80067b8: 60fb str r3, [r7, #12] TIMx->CR1 = tmpcr1; 80067ba: 687b ldr r3, [r7, #4] 80067bc: 68fa ldr r2, [r7, #12] 80067be: 601a str r2, [r3, #0] /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; 80067c0: 683b ldr r3, [r7, #0] 80067c2: 689a ldr r2, [r3, #8] 80067c4: 687b ldr r3, [r7, #4] 80067c6: 62da str r2, [r3, #44] @ 0x2c /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; 80067c8: 683b ldr r3, [r7, #0] 80067ca: 681a ldr r2, [r3, #0] 80067cc: 687b ldr r3, [r7, #4] 80067ce: 629a str r2, [r3, #40] @ 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 80067d0: 687b ldr r3, [r7, #4] 80067d2: 4a14 ldr r2, [pc, #80] @ (8006824 ) 80067d4: 4293 cmp r3, r2 80067d6: d00b beq.n 80067f0 80067d8: 687b ldr r3, [r7, #4] 80067da: 4a15 ldr r2, [pc, #84] @ (8006830 ) 80067dc: 4293 cmp r3, r2 80067de: d007 beq.n 80067f0 80067e0: 687b ldr r3, [r7, #4] 80067e2: 4a14 ldr r2, [pc, #80] @ (8006834 ) 80067e4: 4293 cmp r3, r2 80067e6: d003 beq.n 80067f0 80067e8: 687b ldr r3, [r7, #4] 80067ea: 4a13 ldr r2, [pc, #76] @ (8006838 ) 80067ec: 4293 cmp r3, r2 80067ee: d103 bne.n 80067f8 { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; 80067f0: 683b ldr r3, [r7, #0] 80067f2: 691a ldr r2, [r3, #16] 80067f4: 687b ldr r3, [r7, #4] 80067f6: 631a str r2, [r3, #48] @ 0x30 } /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; 80067f8: 687b ldr r3, [r7, #4] 80067fa: 2201 movs r2, #1 80067fc: 615a str r2, [r3, #20] /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */ if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE)) 80067fe: 687b ldr r3, [r7, #4] 8006800: 691b ldr r3, [r3, #16] 8006802: f003 0301 and.w r3, r3, #1 8006806: 2b01 cmp r3, #1 8006808: d105 bne.n 8006816 { /* Clear the update flag */ CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE); 800680a: 687b ldr r3, [r7, #4] 800680c: 691b ldr r3, [r3, #16] 800680e: f023 0201 bic.w r2, r3, #1 8006812: 687b ldr r3, [r7, #4] 8006814: 611a str r2, [r3, #16] } } 8006816: bf00 nop 8006818: 3714 adds r7, #20 800681a: 46bd mov sp, r7 800681c: f85d 7b04 ldr.w r7, [sp], #4 8006820: 4770 bx lr 8006822: bf00 nop 8006824: 40012c00 .word 0x40012c00 8006828: 40000400 .word 0x40000400 800682c: 40000800 .word 0x40000800 8006830: 40014000 .word 0x40014000 8006834: 40014400 .word 0x40014400 8006838: 40014800 .word 0x40014800 0800683c : * mode. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, const TIM_MasterConfigTypeDef *sMasterConfig) { 800683c: b480 push {r7} 800683e: b085 sub sp, #20 8006840: af00 add r7, sp, #0 8006842: 6078 str r0, [r7, #4] 8006844: 6039 str r1, [r7, #0] assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); /* Check input state */ __HAL_LOCK(htim); 8006846: 687b ldr r3, [r7, #4] 8006848: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 800684c: 2b01 cmp r3, #1 800684e: d101 bne.n 8006854 8006850: 2302 movs r3, #2 8006852: e059 b.n 8006908 8006854: 687b ldr r3, [r7, #4] 8006856: 2201 movs r2, #1 8006858: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Change the handler state */ htim->State = HAL_TIM_STATE_BUSY; 800685c: 687b ldr r3, [r7, #4] 800685e: 2202 movs r2, #2 8006860: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; 8006864: 687b ldr r3, [r7, #4] 8006866: 681b ldr r3, [r3, #0] 8006868: 685b ldr r3, [r3, #4] 800686a: 60fb str r3, [r7, #12] /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; 800686c: 687b ldr r3, [r7, #4] 800686e: 681b ldr r3, [r3, #0] 8006870: 689b ldr r3, [r3, #8] 8006872: 60bb str r3, [r7, #8] #if defined(TIM_CR2_MMS2) /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */ if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) 8006874: 687b ldr r3, [r7, #4] 8006876: 681b ldr r3, [r3, #0] 8006878: 4a26 ldr r2, [pc, #152] @ (8006914 ) 800687a: 4293 cmp r3, r2 800687c: d108 bne.n 8006890 { /* Check the parameters */ assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2)); /* Clear the MMS2 bits */ tmpcr2 &= ~TIM_CR2_MMS2; 800687e: 68fb ldr r3, [r7, #12] 8006880: f423 0370 bic.w r3, r3, #15728640 @ 0xf00000 8006884: 60fb str r3, [r7, #12] /* Select the TRGO2 source*/ tmpcr2 |= sMasterConfig->MasterOutputTrigger2; 8006886: 683b ldr r3, [r7, #0] 8006888: 685b ldr r3, [r3, #4] 800688a: 68fa ldr r2, [r7, #12] 800688c: 4313 orrs r3, r2 800688e: 60fb str r3, [r7, #12] } #endif /* TIM_CR2_MMS2 */ /* Reset the MMS Bits */ tmpcr2 &= ~TIM_CR2_MMS; 8006890: 68fb ldr r3, [r7, #12] 8006892: f023 0370 bic.w r3, r3, #112 @ 0x70 8006896: 60fb str r3, [r7, #12] /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; 8006898: 683b ldr r3, [r7, #0] 800689a: 681b ldr r3, [r3, #0] 800689c: 68fa ldr r2, [r7, #12] 800689e: 4313 orrs r3, r2 80068a0: 60fb str r3, [r7, #12] /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; 80068a2: 687b ldr r3, [r7, #4] 80068a4: 681b ldr r3, [r3, #0] 80068a6: 68fa ldr r2, [r7, #12] 80068a8: 605a str r2, [r3, #4] if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 80068aa: 687b ldr r3, [r7, #4] 80068ac: 681b ldr r3, [r3, #0] 80068ae: 4a19 ldr r2, [pc, #100] @ (8006914 ) 80068b0: 4293 cmp r3, r2 80068b2: d013 beq.n 80068dc 80068b4: 687b ldr r3, [r7, #4] 80068b6: 681b ldr r3, [r3, #0] 80068b8: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 80068bc: d00e beq.n 80068dc 80068be: 687b ldr r3, [r7, #4] 80068c0: 681b ldr r3, [r3, #0] 80068c2: 4a15 ldr r2, [pc, #84] @ (8006918 ) 80068c4: 4293 cmp r3, r2 80068c6: d009 beq.n 80068dc 80068c8: 687b ldr r3, [r7, #4] 80068ca: 681b ldr r3, [r3, #0] 80068cc: 4a13 ldr r2, [pc, #76] @ (800691c ) 80068ce: 4293 cmp r3, r2 80068d0: d004 beq.n 80068dc 80068d2: 687b ldr r3, [r7, #4] 80068d4: 681b ldr r3, [r3, #0] 80068d6: 4a12 ldr r2, [pc, #72] @ (8006920 ) 80068d8: 4293 cmp r3, r2 80068da: d10c bne.n 80068f6 { /* Reset the MSM Bit */ tmpsmcr &= ~TIM_SMCR_MSM; 80068dc: 68bb ldr r3, [r7, #8] 80068de: f023 0380 bic.w r3, r3, #128 @ 0x80 80068e2: 60bb str r3, [r7, #8] /* Set master mode */ tmpsmcr |= sMasterConfig->MasterSlaveMode; 80068e4: 683b ldr r3, [r7, #0] 80068e6: 689b ldr r3, [r3, #8] 80068e8: 68ba ldr r2, [r7, #8] 80068ea: 4313 orrs r3, r2 80068ec: 60bb str r3, [r7, #8] /* Update TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 80068ee: 687b ldr r3, [r7, #4] 80068f0: 681b ldr r3, [r3, #0] 80068f2: 68ba ldr r2, [r7, #8] 80068f4: 609a str r2, [r3, #8] } /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; 80068f6: 687b ldr r3, [r7, #4] 80068f8: 2201 movs r2, #1 80068fa: f883 203d strb.w r2, [r3, #61] @ 0x3d __HAL_UNLOCK(htim); 80068fe: 687b ldr r3, [r7, #4] 8006900: 2200 movs r2, #0 8006902: f883 203c strb.w r2, [r3, #60] @ 0x3c return HAL_OK; 8006906: 2300 movs r3, #0 } 8006908: 4618 mov r0, r3 800690a: 3714 adds r7, #20 800690c: 46bd mov sp, r7 800690e: f85d 7b04 ldr.w r7, [sp], #4 8006912: 4770 bx lr 8006914: 40012c00 .word 0x40012c00 8006918: 40000400 .word 0x40000400 800691c: 40000800 .word 0x40000800 8006920: 40014000 .word 0x40014000 08006924 : * @brief Commutation callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) { 8006924: b480 push {r7} 8006926: b083 sub sp, #12 8006928: af00 add r7, sp, #0 800692a: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_CommutCallback could be implemented in the user file */ } 800692c: bf00 nop 800692e: 370c adds r7, #12 8006930: 46bd mov sp, r7 8006932: f85d 7b04 ldr.w r7, [sp], #4 8006936: 4770 bx lr 08006938 : * @brief Break detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) { 8006938: b480 push {r7} 800693a: b083 sub sp, #12 800693c: af00 add r7, sp, #0 800693e: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_BreakCallback could be implemented in the user file */ } 8006940: bf00 nop 8006942: 370c adds r7, #12 8006944: 46bd mov sp, r7 8006946: f85d 7b04 ldr.w r7, [sp], #4 800694a: 4770 bx lr 0800694c : * @brief Break2 detection callback in non blocking mode * @param htim: TIM handle * @retval None */ __weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim) { 800694c: b480 push {r7} 800694e: b083 sub sp, #12 8006950: af00 add r7, sp, #0 8006952: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_TIMEx_Break2Callback could be implemented in the user file */ } 8006954: bf00 nop 8006956: 370c adds r7, #12 8006958: 46bd mov sp, r7 800695a: f85d 7b04 ldr.w r7, [sp], #4 800695e: 4770 bx lr 08006960 : * parameters in the UART_InitTypeDef and initialize the associated handle. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { 8006960: b580 push {r7, lr} 8006962: b082 sub sp, #8 8006964: af00 add r7, sp, #0 8006966: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) 8006968: 687b ldr r3, [r7, #4] 800696a: 2b00 cmp r3, #0 800696c: d101 bne.n 8006972 { return HAL_ERROR; 800696e: 2301 movs r3, #1 8006970: e040 b.n 80069f4 { /* Check the parameters */ assert_param(IS_UART_INSTANCE(huart->Instance)); } if (huart->gState == HAL_UART_STATE_RESET) 8006972: 687b ldr r3, [r7, #4] 8006974: 6fdb ldr r3, [r3, #124] @ 0x7c 8006976: 2b00 cmp r3, #0 8006978: d106 bne.n 8006988 { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; 800697a: 687b ldr r3, [r7, #4] 800697c: 2200 movs r2, #0 800697e: f883 2078 strb.w r2, [r3, #120] @ 0x78 /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); 8006982: 6878 ldr r0, [r7, #4] 8006984: f7fb fb74 bl 8002070 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; 8006988: 687b ldr r3, [r7, #4] 800698a: 2224 movs r2, #36 @ 0x24 800698c: 67da str r2, [r3, #124] @ 0x7c __HAL_UART_DISABLE(huart); 800698e: 687b ldr r3, [r7, #4] 8006990: 681b ldr r3, [r3, #0] 8006992: 681a ldr r2, [r3, #0] 8006994: 687b ldr r3, [r7, #4] 8006996: 681b ldr r3, [r3, #0] 8006998: f022 0201 bic.w r2, r2, #1 800699c: 601a str r2, [r3, #0] /* Perform advanced settings configuration */ /* For some items, configuration requires to be done prior TE and RE bits are set */ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) 800699e: 687b ldr r3, [r7, #4] 80069a0: 6a5b ldr r3, [r3, #36] @ 0x24 80069a2: 2b00 cmp r3, #0 80069a4: d002 beq.n 80069ac { UART_AdvFeatureConfig(huart); 80069a6: 6878 ldr r0, [r7, #4] 80069a8: f000 f9fc bl 8006da4 } /* Set the UART Communication parameters */ if (UART_SetConfig(huart) == HAL_ERROR) 80069ac: 6878 ldr r0, [r7, #4] 80069ae: f000 f825 bl 80069fc 80069b2: 4603 mov r3, r0 80069b4: 2b01 cmp r3, #1 80069b6: d101 bne.n 80069bc { return HAL_ERROR; 80069b8: 2301 movs r3, #1 80069ba: e01b b.n 80069f4 } /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 80069bc: 687b ldr r3, [r7, #4] 80069be: 681b ldr r3, [r3, #0] 80069c0: 685a ldr r2, [r3, #4] 80069c2: 687b ldr r3, [r7, #4] 80069c4: 681b ldr r3, [r3, #0] 80069c6: f422 4290 bic.w r2, r2, #18432 @ 0x4800 80069ca: 605a str r2, [r3, #4] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); 80069cc: 687b ldr r3, [r7, #4] 80069ce: 681b ldr r3, [r3, #0] 80069d0: 689a ldr r2, [r3, #8] 80069d2: 687b ldr r3, [r7, #4] 80069d4: 681b ldr r3, [r3, #0] 80069d6: f022 022a bic.w r2, r2, #42 @ 0x2a 80069da: 609a str r2, [r3, #8] __HAL_UART_ENABLE(huart); 80069dc: 687b ldr r3, [r7, #4] 80069de: 681b ldr r3, [r3, #0] 80069e0: 681a ldr r2, [r3, #0] 80069e2: 687b ldr r3, [r7, #4] 80069e4: 681b ldr r3, [r3, #0] 80069e6: f042 0201 orr.w r2, r2, #1 80069ea: 601a str r2, [r3, #0] /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); 80069ec: 6878 ldr r0, [r7, #4] 80069ee: f000 fa7b bl 8006ee8 80069f2: 4603 mov r3, r0 } 80069f4: 4618 mov r0, r3 80069f6: 3708 adds r7, #8 80069f8: 46bd mov sp, r7 80069fa: bd80 pop {r7, pc} 080069fc : * @brief Configure the UART peripheral. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) { 80069fc: b580 push {r7, lr} 80069fe: b088 sub sp, #32 8006a00: af00 add r7, sp, #0 8006a02: 6078 str r0, [r7, #4] uint32_t tmpreg; uint16_t brrtemp; UART_ClockSourceTypeDef clocksource; uint32_t usartdiv; HAL_StatusTypeDef ret = HAL_OK; 8006a04: 2300 movs r3, #0 8006a06: 77bb strb r3, [r7, #30] * the UART Word Length, Parity, Mode and oversampling: * set the M bits according to huart->Init.WordLength value * set PCE and PS bits according to huart->Init.Parity value * set TE and RE bits according to huart->Init.Mode value * set OVER8 bit according to huart->Init.OverSampling value */ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; 8006a08: 687b ldr r3, [r7, #4] 8006a0a: 689a ldr r2, [r3, #8] 8006a0c: 687b ldr r3, [r7, #4] 8006a0e: 691b ldr r3, [r3, #16] 8006a10: 431a orrs r2, r3 8006a12: 687b ldr r3, [r7, #4] 8006a14: 695b ldr r3, [r3, #20] 8006a16: 431a orrs r2, r3 8006a18: 687b ldr r3, [r7, #4] 8006a1a: 69db ldr r3, [r3, #28] 8006a1c: 4313 orrs r3, r2 8006a1e: 617b str r3, [r7, #20] MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); 8006a20: 687b ldr r3, [r7, #4] 8006a22: 681b ldr r3, [r3, #0] 8006a24: 681b ldr r3, [r3, #0] 8006a26: f423 4316 bic.w r3, r3, #38400 @ 0x9600 8006a2a: f023 030c bic.w r3, r3, #12 8006a2e: 687a ldr r2, [r7, #4] 8006a30: 6812 ldr r2, [r2, #0] 8006a32: 6979 ldr r1, [r7, #20] 8006a34: 430b orrs r3, r1 8006a36: 6013 str r3, [r2, #0] /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according * to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); 8006a38: 687b ldr r3, [r7, #4] 8006a3a: 681b ldr r3, [r3, #0] 8006a3c: 685b ldr r3, [r3, #4] 8006a3e: f423 5140 bic.w r1, r3, #12288 @ 0x3000 8006a42: 687b ldr r3, [r7, #4] 8006a44: 68da ldr r2, [r3, #12] 8006a46: 687b ldr r3, [r7, #4] 8006a48: 681b ldr r3, [r3, #0] 8006a4a: 430a orrs r2, r1 8006a4c: 605a str r2, [r3, #4] /* Configure * - UART HardWare Flow Control: set CTSE and RTSE bits according * to huart->Init.HwFlowCtl value * - one-bit sampling method versus three samples' majority rule according * to huart->Init.OneBitSampling (not applicable to LPUART) */ tmpreg = (uint32_t)huart->Init.HwFlowCtl; 8006a4e: 687b ldr r3, [r7, #4] 8006a50: 699b ldr r3, [r3, #24] 8006a52: 617b str r3, [r7, #20] tmpreg |= huart->Init.OneBitSampling; 8006a54: 687b ldr r3, [r7, #4] 8006a56: 6a1b ldr r3, [r3, #32] 8006a58: 697a ldr r2, [r7, #20] 8006a5a: 4313 orrs r3, r2 8006a5c: 617b str r3, [r7, #20] MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); 8006a5e: 687b ldr r3, [r7, #4] 8006a60: 681b ldr r3, [r3, #0] 8006a62: 689b ldr r3, [r3, #8] 8006a64: f423 6130 bic.w r1, r3, #2816 @ 0xb00 8006a68: 687b ldr r3, [r7, #4] 8006a6a: 681b ldr r3, [r3, #0] 8006a6c: 697a ldr r2, [r7, #20] 8006a6e: 430a orrs r2, r1 8006a70: 609a str r2, [r3, #8] /*-------------------------- USART BRR Configuration -----------------------*/ UART_GETCLOCKSOURCE(huart, clocksource); 8006a72: 687b ldr r3, [r7, #4] 8006a74: 681b ldr r3, [r3, #0] 8006a76: 4aa7 ldr r2, [pc, #668] @ (8006d14 ) 8006a78: 4293 cmp r3, r2 8006a7a: d120 bne.n 8006abe 8006a7c: 4ba6 ldr r3, [pc, #664] @ (8006d18 ) 8006a7e: 6b1b ldr r3, [r3, #48] @ 0x30 8006a80: f003 0303 and.w r3, r3, #3 8006a84: 2b03 cmp r3, #3 8006a86: d817 bhi.n 8006ab8 8006a88: a201 add r2, pc, #4 @ (adr r2, 8006a90 ) 8006a8a: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8006a8e: bf00 nop 8006a90: 08006aa1 .word 0x08006aa1 8006a94: 08006aad .word 0x08006aad 8006a98: 08006ab3 .word 0x08006ab3 8006a9c: 08006aa7 .word 0x08006aa7 8006aa0: 2301 movs r3, #1 8006aa2: 77fb strb r3, [r7, #31] 8006aa4: e0b5 b.n 8006c12 8006aa6: 2302 movs r3, #2 8006aa8: 77fb strb r3, [r7, #31] 8006aaa: e0b2 b.n 8006c12 8006aac: 2304 movs r3, #4 8006aae: 77fb strb r3, [r7, #31] 8006ab0: e0af b.n 8006c12 8006ab2: 2308 movs r3, #8 8006ab4: 77fb strb r3, [r7, #31] 8006ab6: e0ac b.n 8006c12 8006ab8: 2310 movs r3, #16 8006aba: 77fb strb r3, [r7, #31] 8006abc: e0a9 b.n 8006c12 8006abe: 687b ldr r3, [r7, #4] 8006ac0: 681b ldr r3, [r3, #0] 8006ac2: 4a96 ldr r2, [pc, #600] @ (8006d1c ) 8006ac4: 4293 cmp r3, r2 8006ac6: d124 bne.n 8006b12 8006ac8: 4b93 ldr r3, [pc, #588] @ (8006d18 ) 8006aca: 6b1b ldr r3, [r3, #48] @ 0x30 8006acc: f403 3340 and.w r3, r3, #196608 @ 0x30000 8006ad0: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 8006ad4: d011 beq.n 8006afa 8006ad6: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 8006ada: d817 bhi.n 8006b0c 8006adc: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 8006ae0: d011 beq.n 8006b06 8006ae2: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 8006ae6: d811 bhi.n 8006b0c 8006ae8: 2b00 cmp r3, #0 8006aea: d003 beq.n 8006af4 8006aec: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8006af0: d006 beq.n 8006b00 8006af2: e00b b.n 8006b0c 8006af4: 2300 movs r3, #0 8006af6: 77fb strb r3, [r7, #31] 8006af8: e08b b.n 8006c12 8006afa: 2302 movs r3, #2 8006afc: 77fb strb r3, [r7, #31] 8006afe: e088 b.n 8006c12 8006b00: 2304 movs r3, #4 8006b02: 77fb strb r3, [r7, #31] 8006b04: e085 b.n 8006c12 8006b06: 2308 movs r3, #8 8006b08: 77fb strb r3, [r7, #31] 8006b0a: e082 b.n 8006c12 8006b0c: 2310 movs r3, #16 8006b0e: 77fb strb r3, [r7, #31] 8006b10: e07f b.n 8006c12 8006b12: 687b ldr r3, [r7, #4] 8006b14: 681b ldr r3, [r3, #0] 8006b16: 4a82 ldr r2, [pc, #520] @ (8006d20 ) 8006b18: 4293 cmp r3, r2 8006b1a: d124 bne.n 8006b66 8006b1c: 4b7e ldr r3, [pc, #504] @ (8006d18 ) 8006b1e: 6b1b ldr r3, [r3, #48] @ 0x30 8006b20: f403 2340 and.w r3, r3, #786432 @ 0xc0000 8006b24: f5b3 2f40 cmp.w r3, #786432 @ 0xc0000 8006b28: d011 beq.n 8006b4e 8006b2a: f5b3 2f40 cmp.w r3, #786432 @ 0xc0000 8006b2e: d817 bhi.n 8006b60 8006b30: f5b3 2f00 cmp.w r3, #524288 @ 0x80000 8006b34: d011 beq.n 8006b5a 8006b36: f5b3 2f00 cmp.w r3, #524288 @ 0x80000 8006b3a: d811 bhi.n 8006b60 8006b3c: 2b00 cmp r3, #0 8006b3e: d003 beq.n 8006b48 8006b40: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 8006b44: d006 beq.n 8006b54 8006b46: e00b b.n 8006b60 8006b48: 2300 movs r3, #0 8006b4a: 77fb strb r3, [r7, #31] 8006b4c: e061 b.n 8006c12 8006b4e: 2302 movs r3, #2 8006b50: 77fb strb r3, [r7, #31] 8006b52: e05e b.n 8006c12 8006b54: 2304 movs r3, #4 8006b56: 77fb strb r3, [r7, #31] 8006b58: e05b b.n 8006c12 8006b5a: 2308 movs r3, #8 8006b5c: 77fb strb r3, [r7, #31] 8006b5e: e058 b.n 8006c12 8006b60: 2310 movs r3, #16 8006b62: 77fb strb r3, [r7, #31] 8006b64: e055 b.n 8006c12 8006b66: 687b ldr r3, [r7, #4] 8006b68: 681b ldr r3, [r3, #0] 8006b6a: 4a6e ldr r2, [pc, #440] @ (8006d24 ) 8006b6c: 4293 cmp r3, r2 8006b6e: d124 bne.n 8006bba 8006b70: 4b69 ldr r3, [pc, #420] @ (8006d18 ) 8006b72: 6b1b ldr r3, [r3, #48] @ 0x30 8006b74: f403 1340 and.w r3, r3, #3145728 @ 0x300000 8006b78: f5b3 1f40 cmp.w r3, #3145728 @ 0x300000 8006b7c: d011 beq.n 8006ba2 8006b7e: f5b3 1f40 cmp.w r3, #3145728 @ 0x300000 8006b82: d817 bhi.n 8006bb4 8006b84: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 8006b88: d011 beq.n 8006bae 8006b8a: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 8006b8e: d811 bhi.n 8006bb4 8006b90: 2b00 cmp r3, #0 8006b92: d003 beq.n 8006b9c 8006b94: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 8006b98: d006 beq.n 8006ba8 8006b9a: e00b b.n 8006bb4 8006b9c: 2300 movs r3, #0 8006b9e: 77fb strb r3, [r7, #31] 8006ba0: e037 b.n 8006c12 8006ba2: 2302 movs r3, #2 8006ba4: 77fb strb r3, [r7, #31] 8006ba6: e034 b.n 8006c12 8006ba8: 2304 movs r3, #4 8006baa: 77fb strb r3, [r7, #31] 8006bac: e031 b.n 8006c12 8006bae: 2308 movs r3, #8 8006bb0: 77fb strb r3, [r7, #31] 8006bb2: e02e b.n 8006c12 8006bb4: 2310 movs r3, #16 8006bb6: 77fb strb r3, [r7, #31] 8006bb8: e02b b.n 8006c12 8006bba: 687b ldr r3, [r7, #4] 8006bbc: 681b ldr r3, [r3, #0] 8006bbe: 4a5a ldr r2, [pc, #360] @ (8006d28 ) 8006bc0: 4293 cmp r3, r2 8006bc2: d124 bne.n 8006c0e 8006bc4: 4b54 ldr r3, [pc, #336] @ (8006d18 ) 8006bc6: 6b1b ldr r3, [r3, #48] @ 0x30 8006bc8: f403 0340 and.w r3, r3, #12582912 @ 0xc00000 8006bcc: f5b3 0f40 cmp.w r3, #12582912 @ 0xc00000 8006bd0: d011 beq.n 8006bf6 8006bd2: f5b3 0f40 cmp.w r3, #12582912 @ 0xc00000 8006bd6: d817 bhi.n 8006c08 8006bd8: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 8006bdc: d011 beq.n 8006c02 8006bde: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 8006be2: d811 bhi.n 8006c08 8006be4: 2b00 cmp r3, #0 8006be6: d003 beq.n 8006bf0 8006be8: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 8006bec: d006 beq.n 8006bfc 8006bee: e00b b.n 8006c08 8006bf0: 2300 movs r3, #0 8006bf2: 77fb strb r3, [r7, #31] 8006bf4: e00d b.n 8006c12 8006bf6: 2302 movs r3, #2 8006bf8: 77fb strb r3, [r7, #31] 8006bfa: e00a b.n 8006c12 8006bfc: 2304 movs r3, #4 8006bfe: 77fb strb r3, [r7, #31] 8006c00: e007 b.n 8006c12 8006c02: 2308 movs r3, #8 8006c04: 77fb strb r3, [r7, #31] 8006c06: e004 b.n 8006c12 8006c08: 2310 movs r3, #16 8006c0a: 77fb strb r3, [r7, #31] 8006c0c: e001 b.n 8006c12 8006c0e: 2310 movs r3, #16 8006c10: 77fb strb r3, [r7, #31] if (huart->Init.OverSampling == UART_OVERSAMPLING_8) 8006c12: 687b ldr r3, [r7, #4] 8006c14: 69db ldr r3, [r3, #28] 8006c16: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 8006c1a: d15b bne.n 8006cd4 { switch (clocksource) 8006c1c: 7ffb ldrb r3, [r7, #31] 8006c1e: 2b08 cmp r3, #8 8006c20: d827 bhi.n 8006c72 8006c22: a201 add r2, pc, #4 @ (adr r2, 8006c28 ) 8006c24: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8006c28: 08006c4d .word 0x08006c4d 8006c2c: 08006c55 .word 0x08006c55 8006c30: 08006c5d .word 0x08006c5d 8006c34: 08006c73 .word 0x08006c73 8006c38: 08006c63 .word 0x08006c63 8006c3c: 08006c73 .word 0x08006c73 8006c40: 08006c73 .word 0x08006c73 8006c44: 08006c73 .word 0x08006c73 8006c48: 08006c6b .word 0x08006c6b { case UART_CLOCKSOURCE_PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); 8006c4c: f7ff f9ac bl 8005fa8 8006c50: 61b8 str r0, [r7, #24] break; 8006c52: e013 b.n 8006c7c case UART_CLOCKSOURCE_PCLK2: pclk = HAL_RCC_GetPCLK2Freq(); 8006c54: f7ff f9ca bl 8005fec 8006c58: 61b8 str r0, [r7, #24] break; 8006c5a: e00f b.n 8006c7c case UART_CLOCKSOURCE_HSI: pclk = (uint32_t) HSI_VALUE; 8006c5c: 4b33 ldr r3, [pc, #204] @ (8006d2c ) 8006c5e: 61bb str r3, [r7, #24] break; 8006c60: e00c b.n 8006c7c case UART_CLOCKSOURCE_SYSCLK: pclk = HAL_RCC_GetSysClockFreq(); 8006c62: f7ff f93f bl 8005ee4 8006c66: 61b8 str r0, [r7, #24] break; 8006c68: e008 b.n 8006c7c case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; 8006c6a: f44f 4300 mov.w r3, #32768 @ 0x8000 8006c6e: 61bb str r3, [r7, #24] break; 8006c70: e004 b.n 8006c7c default: pclk = 0U; 8006c72: 2300 movs r3, #0 8006c74: 61bb str r3, [r7, #24] ret = HAL_ERROR; 8006c76: 2301 movs r3, #1 8006c78: 77bb strb r3, [r7, #30] break; 8006c7a: bf00 nop } /* USARTDIV must be greater than or equal to 0d16 */ if (pclk != 0U) 8006c7c: 69bb ldr r3, [r7, #24] 8006c7e: 2b00 cmp r3, #0 8006c80: f000 8082 beq.w 8006d88 { usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate)); 8006c84: 69bb ldr r3, [r7, #24] 8006c86: 005a lsls r2, r3, #1 8006c88: 687b ldr r3, [r7, #4] 8006c8a: 685b ldr r3, [r3, #4] 8006c8c: 085b lsrs r3, r3, #1 8006c8e: 441a add r2, r3 8006c90: 687b ldr r3, [r7, #4] 8006c92: 685b ldr r3, [r3, #4] 8006c94: fbb2 f3f3 udiv r3, r2, r3 8006c98: 613b str r3, [r7, #16] if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) 8006c9a: 693b ldr r3, [r7, #16] 8006c9c: 2b0f cmp r3, #15 8006c9e: d916 bls.n 8006cce 8006ca0: 693b ldr r3, [r7, #16] 8006ca2: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8006ca6: d212 bcs.n 8006cce { brrtemp = (uint16_t)(usartdiv & 0xFFF0U); 8006ca8: 693b ldr r3, [r7, #16] 8006caa: b29b uxth r3, r3 8006cac: f023 030f bic.w r3, r3, #15 8006cb0: 81fb strh r3, [r7, #14] brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); 8006cb2: 693b ldr r3, [r7, #16] 8006cb4: 085b lsrs r3, r3, #1 8006cb6: b29b uxth r3, r3 8006cb8: f003 0307 and.w r3, r3, #7 8006cbc: b29a uxth r2, r3 8006cbe: 89fb ldrh r3, [r7, #14] 8006cc0: 4313 orrs r3, r2 8006cc2: 81fb strh r3, [r7, #14] huart->Instance->BRR = brrtemp; 8006cc4: 687b ldr r3, [r7, #4] 8006cc6: 681b ldr r3, [r3, #0] 8006cc8: 89fa ldrh r2, [r7, #14] 8006cca: 60da str r2, [r3, #12] 8006ccc: e05c b.n 8006d88 } else { ret = HAL_ERROR; 8006cce: 2301 movs r3, #1 8006cd0: 77bb strb r3, [r7, #30] 8006cd2: e059 b.n 8006d88 } } } else { switch (clocksource) 8006cd4: 7ffb ldrb r3, [r7, #31] 8006cd6: 2b08 cmp r3, #8 8006cd8: d835 bhi.n 8006d46 8006cda: a201 add r2, pc, #4 @ (adr r2, 8006ce0 ) 8006cdc: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8006ce0: 08006d05 .word 0x08006d05 8006ce4: 08006d0d .word 0x08006d0d 8006ce8: 08006d31 .word 0x08006d31 8006cec: 08006d47 .word 0x08006d47 8006cf0: 08006d37 .word 0x08006d37 8006cf4: 08006d47 .word 0x08006d47 8006cf8: 08006d47 .word 0x08006d47 8006cfc: 08006d47 .word 0x08006d47 8006d00: 08006d3f .word 0x08006d3f { case UART_CLOCKSOURCE_PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); 8006d04: f7ff f950 bl 8005fa8 8006d08: 61b8 str r0, [r7, #24] break; 8006d0a: e021 b.n 8006d50 case UART_CLOCKSOURCE_PCLK2: pclk = HAL_RCC_GetPCLK2Freq(); 8006d0c: f7ff f96e bl 8005fec 8006d10: 61b8 str r0, [r7, #24] break; 8006d12: e01d b.n 8006d50 8006d14: 40013800 .word 0x40013800 8006d18: 40021000 .word 0x40021000 8006d1c: 40004400 .word 0x40004400 8006d20: 40004800 .word 0x40004800 8006d24: 40004c00 .word 0x40004c00 8006d28: 40005000 .word 0x40005000 8006d2c: 007a1200 .word 0x007a1200 case UART_CLOCKSOURCE_HSI: pclk = (uint32_t) HSI_VALUE; 8006d30: 4b1b ldr r3, [pc, #108] @ (8006da0 ) 8006d32: 61bb str r3, [r7, #24] break; 8006d34: e00c b.n 8006d50 case UART_CLOCKSOURCE_SYSCLK: pclk = HAL_RCC_GetSysClockFreq(); 8006d36: f7ff f8d5 bl 8005ee4 8006d3a: 61b8 str r0, [r7, #24] break; 8006d3c: e008 b.n 8006d50 case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; 8006d3e: f44f 4300 mov.w r3, #32768 @ 0x8000 8006d42: 61bb str r3, [r7, #24] break; 8006d44: e004 b.n 8006d50 default: pclk = 0U; 8006d46: 2300 movs r3, #0 8006d48: 61bb str r3, [r7, #24] ret = HAL_ERROR; 8006d4a: 2301 movs r3, #1 8006d4c: 77bb strb r3, [r7, #30] break; 8006d4e: bf00 nop } if (pclk != 0U) 8006d50: 69bb ldr r3, [r7, #24] 8006d52: 2b00 cmp r3, #0 8006d54: d018 beq.n 8006d88 { /* USARTDIV must be greater than or equal to 0d16 */ usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate)); 8006d56: 687b ldr r3, [r7, #4] 8006d58: 685b ldr r3, [r3, #4] 8006d5a: 085a lsrs r2, r3, #1 8006d5c: 69bb ldr r3, [r7, #24] 8006d5e: 441a add r2, r3 8006d60: 687b ldr r3, [r7, #4] 8006d62: 685b ldr r3, [r3, #4] 8006d64: fbb2 f3f3 udiv r3, r2, r3 8006d68: 613b str r3, [r7, #16] if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) 8006d6a: 693b ldr r3, [r7, #16] 8006d6c: 2b0f cmp r3, #15 8006d6e: d909 bls.n 8006d84 8006d70: 693b ldr r3, [r7, #16] 8006d72: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8006d76: d205 bcs.n 8006d84 { huart->Instance->BRR = (uint16_t)usartdiv; 8006d78: 693b ldr r3, [r7, #16] 8006d7a: b29a uxth r2, r3 8006d7c: 687b ldr r3, [r7, #4] 8006d7e: 681b ldr r3, [r3, #0] 8006d80: 60da str r2, [r3, #12] 8006d82: e001 b.n 8006d88 } else { ret = HAL_ERROR; 8006d84: 2301 movs r3, #1 8006d86: 77bb strb r3, [r7, #30] } } /* Clear ISR function pointers */ huart->RxISR = NULL; 8006d88: 687b ldr r3, [r7, #4] 8006d8a: 2200 movs r2, #0 8006d8c: 669a str r2, [r3, #104] @ 0x68 huart->TxISR = NULL; 8006d8e: 687b ldr r3, [r7, #4] 8006d90: 2200 movs r2, #0 8006d92: 66da str r2, [r3, #108] @ 0x6c return ret; 8006d94: 7fbb ldrb r3, [r7, #30] } 8006d96: 4618 mov r0, r3 8006d98: 3720 adds r7, #32 8006d9a: 46bd mov sp, r7 8006d9c: bd80 pop {r7, pc} 8006d9e: bf00 nop 8006da0: 007a1200 .word 0x007a1200 08006da4 : * @brief Configure the UART peripheral advanced features. * @param huart UART handle. * @retval None */ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) { 8006da4: b480 push {r7} 8006da6: b083 sub sp, #12 8006da8: af00 add r7, sp, #0 8006daa: 6078 str r0, [r7, #4] /* Check whether the set of advanced features to configure is properly set */ assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); /* if required, configure RX/TX pins swap */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) 8006dac: 687b ldr r3, [r7, #4] 8006dae: 6a5b ldr r3, [r3, #36] @ 0x24 8006db0: f003 0308 and.w r3, r3, #8 8006db4: 2b00 cmp r3, #0 8006db6: d00a beq.n 8006dce { assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); 8006db8: 687b ldr r3, [r7, #4] 8006dba: 681b ldr r3, [r3, #0] 8006dbc: 685b ldr r3, [r3, #4] 8006dbe: f423 4100 bic.w r1, r3, #32768 @ 0x8000 8006dc2: 687b ldr r3, [r7, #4] 8006dc4: 6b5a ldr r2, [r3, #52] @ 0x34 8006dc6: 687b ldr r3, [r7, #4] 8006dc8: 681b ldr r3, [r3, #0] 8006dca: 430a orrs r2, r1 8006dcc: 605a str r2, [r3, #4] } /* if required, configure TX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) 8006dce: 687b ldr r3, [r7, #4] 8006dd0: 6a5b ldr r3, [r3, #36] @ 0x24 8006dd2: f003 0301 and.w r3, r3, #1 8006dd6: 2b00 cmp r3, #0 8006dd8: d00a beq.n 8006df0 { assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); 8006dda: 687b ldr r3, [r7, #4] 8006ddc: 681b ldr r3, [r3, #0] 8006dde: 685b ldr r3, [r3, #4] 8006de0: f423 3100 bic.w r1, r3, #131072 @ 0x20000 8006de4: 687b ldr r3, [r7, #4] 8006de6: 6a9a ldr r2, [r3, #40] @ 0x28 8006de8: 687b ldr r3, [r7, #4] 8006dea: 681b ldr r3, [r3, #0] 8006dec: 430a orrs r2, r1 8006dee: 605a str r2, [r3, #4] } /* if required, configure RX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) 8006df0: 687b ldr r3, [r7, #4] 8006df2: 6a5b ldr r3, [r3, #36] @ 0x24 8006df4: f003 0302 and.w r3, r3, #2 8006df8: 2b00 cmp r3, #0 8006dfa: d00a beq.n 8006e12 { assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); 8006dfc: 687b ldr r3, [r7, #4] 8006dfe: 681b ldr r3, [r3, #0] 8006e00: 685b ldr r3, [r3, #4] 8006e02: f423 3180 bic.w r1, r3, #65536 @ 0x10000 8006e06: 687b ldr r3, [r7, #4] 8006e08: 6ada ldr r2, [r3, #44] @ 0x2c 8006e0a: 687b ldr r3, [r7, #4] 8006e0c: 681b ldr r3, [r3, #0] 8006e0e: 430a orrs r2, r1 8006e10: 605a str r2, [r3, #4] } /* if required, configure data inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) 8006e12: 687b ldr r3, [r7, #4] 8006e14: 6a5b ldr r3, [r3, #36] @ 0x24 8006e16: f003 0304 and.w r3, r3, #4 8006e1a: 2b00 cmp r3, #0 8006e1c: d00a beq.n 8006e34 { assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); 8006e1e: 687b ldr r3, [r7, #4] 8006e20: 681b ldr r3, [r3, #0] 8006e22: 685b ldr r3, [r3, #4] 8006e24: f423 2180 bic.w r1, r3, #262144 @ 0x40000 8006e28: 687b ldr r3, [r7, #4] 8006e2a: 6b1a ldr r2, [r3, #48] @ 0x30 8006e2c: 687b ldr r3, [r7, #4] 8006e2e: 681b ldr r3, [r3, #0] 8006e30: 430a orrs r2, r1 8006e32: 605a str r2, [r3, #4] } /* if required, configure RX overrun detection disabling */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) 8006e34: 687b ldr r3, [r7, #4] 8006e36: 6a5b ldr r3, [r3, #36] @ 0x24 8006e38: f003 0310 and.w r3, r3, #16 8006e3c: 2b00 cmp r3, #0 8006e3e: d00a beq.n 8006e56 { assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); 8006e40: 687b ldr r3, [r7, #4] 8006e42: 681b ldr r3, [r3, #0] 8006e44: 689b ldr r3, [r3, #8] 8006e46: f423 5180 bic.w r1, r3, #4096 @ 0x1000 8006e4a: 687b ldr r3, [r7, #4] 8006e4c: 6b9a ldr r2, [r3, #56] @ 0x38 8006e4e: 687b ldr r3, [r7, #4] 8006e50: 681b ldr r3, [r3, #0] 8006e52: 430a orrs r2, r1 8006e54: 609a str r2, [r3, #8] } /* if required, configure DMA disabling on reception error */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) 8006e56: 687b ldr r3, [r7, #4] 8006e58: 6a5b ldr r3, [r3, #36] @ 0x24 8006e5a: f003 0320 and.w r3, r3, #32 8006e5e: 2b00 cmp r3, #0 8006e60: d00a beq.n 8006e78 { assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); 8006e62: 687b ldr r3, [r7, #4] 8006e64: 681b ldr r3, [r3, #0] 8006e66: 689b ldr r3, [r3, #8] 8006e68: f423 5100 bic.w r1, r3, #8192 @ 0x2000 8006e6c: 687b ldr r3, [r7, #4] 8006e6e: 6bda ldr r2, [r3, #60] @ 0x3c 8006e70: 687b ldr r3, [r7, #4] 8006e72: 681b ldr r3, [r3, #0] 8006e74: 430a orrs r2, r1 8006e76: 609a str r2, [r3, #8] } /* if required, configure auto Baud rate detection scheme */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) 8006e78: 687b ldr r3, [r7, #4] 8006e7a: 6a5b ldr r3, [r3, #36] @ 0x24 8006e7c: f003 0340 and.w r3, r3, #64 @ 0x40 8006e80: 2b00 cmp r3, #0 8006e82: d01a beq.n 8006eba { assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance)); assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); 8006e84: 687b ldr r3, [r7, #4] 8006e86: 681b ldr r3, [r3, #0] 8006e88: 685b ldr r3, [r3, #4] 8006e8a: f423 1180 bic.w r1, r3, #1048576 @ 0x100000 8006e8e: 687b ldr r3, [r7, #4] 8006e90: 6c1a ldr r2, [r3, #64] @ 0x40 8006e92: 687b ldr r3, [r7, #4] 8006e94: 681b ldr r3, [r3, #0] 8006e96: 430a orrs r2, r1 8006e98: 605a str r2, [r3, #4] /* set auto Baudrate detection parameters if detection is enabled */ if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) 8006e9a: 687b ldr r3, [r7, #4] 8006e9c: 6c1b ldr r3, [r3, #64] @ 0x40 8006e9e: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 8006ea2: d10a bne.n 8006eba { assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); 8006ea4: 687b ldr r3, [r7, #4] 8006ea6: 681b ldr r3, [r3, #0] 8006ea8: 685b ldr r3, [r3, #4] 8006eaa: f423 01c0 bic.w r1, r3, #6291456 @ 0x600000 8006eae: 687b ldr r3, [r7, #4] 8006eb0: 6c5a ldr r2, [r3, #68] @ 0x44 8006eb2: 687b ldr r3, [r7, #4] 8006eb4: 681b ldr r3, [r3, #0] 8006eb6: 430a orrs r2, r1 8006eb8: 605a str r2, [r3, #4] } } /* if required, configure MSB first on communication line */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) 8006eba: 687b ldr r3, [r7, #4] 8006ebc: 6a5b ldr r3, [r3, #36] @ 0x24 8006ebe: f003 0380 and.w r3, r3, #128 @ 0x80 8006ec2: 2b00 cmp r3, #0 8006ec4: d00a beq.n 8006edc { assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); 8006ec6: 687b ldr r3, [r7, #4] 8006ec8: 681b ldr r3, [r3, #0] 8006eca: 685b ldr r3, [r3, #4] 8006ecc: f423 2100 bic.w r1, r3, #524288 @ 0x80000 8006ed0: 687b ldr r3, [r7, #4] 8006ed2: 6c9a ldr r2, [r3, #72] @ 0x48 8006ed4: 687b ldr r3, [r7, #4] 8006ed6: 681b ldr r3, [r3, #0] 8006ed8: 430a orrs r2, r1 8006eda: 605a str r2, [r3, #4] } } 8006edc: bf00 nop 8006ede: 370c adds r7, #12 8006ee0: 46bd mov sp, r7 8006ee2: f85d 7b04 ldr.w r7, [sp], #4 8006ee6: 4770 bx lr 08006ee8 : * @brief Check the UART Idle State. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) { 8006ee8: b580 push {r7, lr} 8006eea: b098 sub sp, #96 @ 0x60 8006eec: af02 add r7, sp, #8 8006eee: 6078 str r0, [r7, #4] uint32_t tickstart; /* Initialize the UART ErrorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8006ef0: 687b ldr r3, [r7, #4] 8006ef2: 2200 movs r2, #0 8006ef4: f8c3 2084 str.w r2, [r3, #132] @ 0x84 /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); 8006ef8: f7fb fa04 bl 8002304 8006efc: 6578 str r0, [r7, #84] @ 0x54 /* Check if the Transmitter is enabled */ if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) 8006efe: 687b ldr r3, [r7, #4] 8006f00: 681b ldr r3, [r3, #0] 8006f02: 681b ldr r3, [r3, #0] 8006f04: f003 0308 and.w r3, r3, #8 8006f08: 2b08 cmp r3, #8 8006f0a: d12e bne.n 8006f6a { /* Wait until TEACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) 8006f0c: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000 8006f10: 9300 str r3, [sp, #0] 8006f12: 6d7b ldr r3, [r7, #84] @ 0x54 8006f14: 2200 movs r2, #0 8006f16: f44f 1100 mov.w r1, #2097152 @ 0x200000 8006f1a: 6878 ldr r0, [r7, #4] 8006f1c: f000 f88c bl 8007038 8006f20: 4603 mov r3, r0 8006f22: 2b00 cmp r3, #0 8006f24: d021 beq.n 8006f6a { /* Disable TXE interrupt for the interrupt process */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE)); 8006f26: 687b ldr r3, [r7, #4] 8006f28: 681b ldr r3, [r3, #0] 8006f2a: 63bb str r3, [r7, #56] @ 0x38 */ __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) { uint32_t result; __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006f2c: 6bbb ldr r3, [r7, #56] @ 0x38 8006f2e: e853 3f00 ldrex r3, [r3] 8006f32: 637b str r3, [r7, #52] @ 0x34 return(result); 8006f34: 6b7b ldr r3, [r7, #52] @ 0x34 8006f36: f023 0380 bic.w r3, r3, #128 @ 0x80 8006f3a: 653b str r3, [r7, #80] @ 0x50 8006f3c: 687b ldr r3, [r7, #4] 8006f3e: 681b ldr r3, [r3, #0] 8006f40: 461a mov r2, r3 8006f42: 6d3b ldr r3, [r7, #80] @ 0x50 8006f44: 647b str r3, [r7, #68] @ 0x44 8006f46: 643a str r2, [r7, #64] @ 0x40 */ __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) { uint32_t result; __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006f48: 6c39 ldr r1, [r7, #64] @ 0x40 8006f4a: 6c7a ldr r2, [r7, #68] @ 0x44 8006f4c: e841 2300 strex r3, r2, [r1] 8006f50: 63fb str r3, [r7, #60] @ 0x3c return(result); 8006f52: 6bfb ldr r3, [r7, #60] @ 0x3c 8006f54: 2b00 cmp r3, #0 8006f56: d1e6 bne.n 8006f26 huart->gState = HAL_UART_STATE_READY; 8006f58: 687b ldr r3, [r7, #4] 8006f5a: 2220 movs r2, #32 8006f5c: 67da str r2, [r3, #124] @ 0x7c __HAL_UNLOCK(huart); 8006f5e: 687b ldr r3, [r7, #4] 8006f60: 2200 movs r2, #0 8006f62: f883 2078 strb.w r2, [r3, #120] @ 0x78 /* Timeout occurred */ return HAL_TIMEOUT; 8006f66: 2303 movs r3, #3 8006f68: e062 b.n 8007030 } } /* Check if the Receiver is enabled */ if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) 8006f6a: 687b ldr r3, [r7, #4] 8006f6c: 681b ldr r3, [r3, #0] 8006f6e: 681b ldr r3, [r3, #0] 8006f70: f003 0304 and.w r3, r3, #4 8006f74: 2b04 cmp r3, #4 8006f76: d149 bne.n 800700c { /* Wait until REACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) 8006f78: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000 8006f7c: 9300 str r3, [sp, #0] 8006f7e: 6d7b ldr r3, [r7, #84] @ 0x54 8006f80: 2200 movs r2, #0 8006f82: f44f 0180 mov.w r1, #4194304 @ 0x400000 8006f86: 6878 ldr r0, [r7, #4] 8006f88: f000 f856 bl 8007038 8006f8c: 4603 mov r3, r0 8006f8e: 2b00 cmp r3, #0 8006f90: d03c beq.n 800700c { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); 8006f92: 687b ldr r3, [r7, #4] 8006f94: 681b ldr r3, [r3, #0] 8006f96: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006f98: 6a7b ldr r3, [r7, #36] @ 0x24 8006f9a: e853 3f00 ldrex r3, [r3] 8006f9e: 623b str r3, [r7, #32] return(result); 8006fa0: 6a3b ldr r3, [r7, #32] 8006fa2: f423 7390 bic.w r3, r3, #288 @ 0x120 8006fa6: 64fb str r3, [r7, #76] @ 0x4c 8006fa8: 687b ldr r3, [r7, #4] 8006faa: 681b ldr r3, [r3, #0] 8006fac: 461a mov r2, r3 8006fae: 6cfb ldr r3, [r7, #76] @ 0x4c 8006fb0: 633b str r3, [r7, #48] @ 0x30 8006fb2: 62fa str r2, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006fb4: 6af9 ldr r1, [r7, #44] @ 0x2c 8006fb6: 6b3a ldr r2, [r7, #48] @ 0x30 8006fb8: e841 2300 strex r3, r2, [r1] 8006fbc: 62bb str r3, [r7, #40] @ 0x28 return(result); 8006fbe: 6abb ldr r3, [r7, #40] @ 0x28 8006fc0: 2b00 cmp r3, #0 8006fc2: d1e6 bne.n 8006f92 ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8006fc4: 687b ldr r3, [r7, #4] 8006fc6: 681b ldr r3, [r3, #0] 8006fc8: 3308 adds r3, #8 8006fca: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006fcc: 693b ldr r3, [r7, #16] 8006fce: e853 3f00 ldrex r3, [r3] 8006fd2: 60fb str r3, [r7, #12] return(result); 8006fd4: 68fb ldr r3, [r7, #12] 8006fd6: f023 0301 bic.w r3, r3, #1 8006fda: 64bb str r3, [r7, #72] @ 0x48 8006fdc: 687b ldr r3, [r7, #4] 8006fde: 681b ldr r3, [r3, #0] 8006fe0: 3308 adds r3, #8 8006fe2: 6cba ldr r2, [r7, #72] @ 0x48 8006fe4: 61fa str r2, [r7, #28] 8006fe6: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006fe8: 69b9 ldr r1, [r7, #24] 8006fea: 69fa ldr r2, [r7, #28] 8006fec: e841 2300 strex r3, r2, [r1] 8006ff0: 617b str r3, [r7, #20] return(result); 8006ff2: 697b ldr r3, [r7, #20] 8006ff4: 2b00 cmp r3, #0 8006ff6: d1e5 bne.n 8006fc4 huart->RxState = HAL_UART_STATE_READY; 8006ff8: 687b ldr r3, [r7, #4] 8006ffa: 2220 movs r2, #32 8006ffc: f8c3 2080 str.w r2, [r3, #128] @ 0x80 __HAL_UNLOCK(huart); 8007000: 687b ldr r3, [r7, #4] 8007002: 2200 movs r2, #0 8007004: f883 2078 strb.w r2, [r3, #120] @ 0x78 /* Timeout occurred */ return HAL_TIMEOUT; 8007008: 2303 movs r3, #3 800700a: e011 b.n 8007030 } } /* Initialize the UART State */ huart->gState = HAL_UART_STATE_READY; 800700c: 687b ldr r3, [r7, #4] 800700e: 2220 movs r2, #32 8007010: 67da str r2, [r3, #124] @ 0x7c huart->RxState = HAL_UART_STATE_READY; 8007012: 687b ldr r3, [r7, #4] 8007014: 2220 movs r2, #32 8007016: f8c3 2080 str.w r2, [r3, #128] @ 0x80 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 800701a: 687b ldr r3, [r7, #4] 800701c: 2200 movs r2, #0 800701e: 661a str r2, [r3, #96] @ 0x60 huart->RxEventType = HAL_UART_RXEVENT_TC; 8007020: 687b ldr r3, [r7, #4] 8007022: 2200 movs r2, #0 8007024: 665a str r2, [r3, #100] @ 0x64 __HAL_UNLOCK(huart); 8007026: 687b ldr r3, [r7, #4] 8007028: 2200 movs r2, #0 800702a: f883 2078 strb.w r2, [r3, #120] @ 0x78 return HAL_OK; 800702e: 2300 movs r3, #0 } 8007030: 4618 mov r0, r3 8007032: 3758 adds r7, #88 @ 0x58 8007034: 46bd mov sp, r7 8007036: bd80 pop {r7, pc} 08007038 : * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { 8007038: b580 push {r7, lr} 800703a: b084 sub sp, #16 800703c: af00 add r7, sp, #0 800703e: 60f8 str r0, [r7, #12] 8007040: 60b9 str r1, [r7, #8] 8007042: 603b str r3, [r7, #0] 8007044: 4613 mov r3, r2 8007046: 71fb strb r3, [r7, #7] /* Wait until flag is set */ while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 8007048: e04f b.n 80070ea { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) 800704a: 69bb ldr r3, [r7, #24] 800704c: f1b3 3fff cmp.w r3, #4294967295 8007050: d04b beq.n 80070ea { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 8007052: f7fb f957 bl 8002304 8007056: 4602 mov r2, r0 8007058: 683b ldr r3, [r7, #0] 800705a: 1ad3 subs r3, r2, r3 800705c: 69ba ldr r2, [r7, #24] 800705e: 429a cmp r2, r3 8007060: d302 bcc.n 8007068 8007062: 69bb ldr r3, [r7, #24] 8007064: 2b00 cmp r3, #0 8007066: d101 bne.n 800706c { return HAL_TIMEOUT; 8007068: 2303 movs r3, #3 800706a: e04e b.n 800710a } if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC)) 800706c: 68fb ldr r3, [r7, #12] 800706e: 681b ldr r3, [r3, #0] 8007070: 681b ldr r3, [r3, #0] 8007072: f003 0304 and.w r3, r3, #4 8007076: 2b00 cmp r3, #0 8007078: d037 beq.n 80070ea 800707a: 68bb ldr r3, [r7, #8] 800707c: 2b80 cmp r3, #128 @ 0x80 800707e: d034 beq.n 80070ea 8007080: 68bb ldr r3, [r7, #8] 8007082: 2b40 cmp r3, #64 @ 0x40 8007084: d031 beq.n 80070ea { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) 8007086: 68fb ldr r3, [r7, #12] 8007088: 681b ldr r3, [r3, #0] 800708a: 69db ldr r3, [r3, #28] 800708c: f003 0308 and.w r3, r3, #8 8007090: 2b08 cmp r3, #8 8007092: d110 bne.n 80070b6 { /* Clear Overrun Error flag*/ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); 8007094: 68fb ldr r3, [r7, #12] 8007096: 681b ldr r3, [r3, #0] 8007098: 2208 movs r2, #8 800709a: 621a str r2, [r3, #32] /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts if ongoing */ UART_EndRxTransfer(huart); 800709c: 68f8 ldr r0, [r7, #12] 800709e: f000 f838 bl 8007112 huart->ErrorCode = HAL_UART_ERROR_ORE; 80070a2: 68fb ldr r3, [r7, #12] 80070a4: 2208 movs r2, #8 80070a6: f8c3 2084 str.w r2, [r3, #132] @ 0x84 /* Process Unlocked */ __HAL_UNLOCK(huart); 80070aa: 68fb ldr r3, [r7, #12] 80070ac: 2200 movs r2, #0 80070ae: f883 2078 strb.w r2, [r3, #120] @ 0x78 return HAL_ERROR; 80070b2: 2301 movs r3, #1 80070b4: e029 b.n 800710a } if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) 80070b6: 68fb ldr r3, [r7, #12] 80070b8: 681b ldr r3, [r3, #0] 80070ba: 69db ldr r3, [r3, #28] 80070bc: f403 6300 and.w r3, r3, #2048 @ 0x800 80070c0: f5b3 6f00 cmp.w r3, #2048 @ 0x800 80070c4: d111 bne.n 80070ea { /* Clear Receiver Timeout flag*/ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); 80070c6: 68fb ldr r3, [r7, #12] 80070c8: 681b ldr r3, [r3, #0] 80070ca: f44f 6200 mov.w r2, #2048 @ 0x800 80070ce: 621a str r2, [r3, #32] /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts if ongoing */ UART_EndRxTransfer(huart); 80070d0: 68f8 ldr r0, [r7, #12] 80070d2: f000 f81e bl 8007112 huart->ErrorCode = HAL_UART_ERROR_RTO; 80070d6: 68fb ldr r3, [r7, #12] 80070d8: 2220 movs r2, #32 80070da: f8c3 2084 str.w r2, [r3, #132] @ 0x84 /* Process Unlocked */ __HAL_UNLOCK(huart); 80070de: 68fb ldr r3, [r7, #12] 80070e0: 2200 movs r2, #0 80070e2: f883 2078 strb.w r2, [r3, #120] @ 0x78 return HAL_TIMEOUT; 80070e6: 2303 movs r3, #3 80070e8: e00f b.n 800710a while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 80070ea: 68fb ldr r3, [r7, #12] 80070ec: 681b ldr r3, [r3, #0] 80070ee: 69da ldr r2, [r3, #28] 80070f0: 68bb ldr r3, [r7, #8] 80070f2: 4013 ands r3, r2 80070f4: 68ba ldr r2, [r7, #8] 80070f6: 429a cmp r2, r3 80070f8: bf0c ite eq 80070fa: 2301 moveq r3, #1 80070fc: 2300 movne r3, #0 80070fe: b2db uxtb r3, r3 8007100: 461a mov r2, r3 8007102: 79fb ldrb r3, [r7, #7] 8007104: 429a cmp r2, r3 8007106: d0a0 beq.n 800704a } } } } return HAL_OK; 8007108: 2300 movs r3, #0 } 800710a: 4618 mov r0, r3 800710c: 3710 adds r7, #16 800710e: 46bd mov sp, r7 8007110: bd80 pop {r7, pc} 08007112 : * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). * @param huart UART handle. * @retval None */ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) { 8007112: b480 push {r7} 8007114: b095 sub sp, #84 @ 0x54 8007116: af00 add r7, sp, #0 8007118: 6078 str r0, [r7, #4] /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); 800711a: 687b ldr r3, [r7, #4] 800711c: 681b ldr r3, [r3, #0] 800711e: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8007120: 6b7b ldr r3, [r7, #52] @ 0x34 8007122: e853 3f00 ldrex r3, [r3] 8007126: 633b str r3, [r7, #48] @ 0x30 return(result); 8007128: 6b3b ldr r3, [r7, #48] @ 0x30 800712a: f423 7390 bic.w r3, r3, #288 @ 0x120 800712e: 64fb str r3, [r7, #76] @ 0x4c 8007130: 687b ldr r3, [r7, #4] 8007132: 681b ldr r3, [r3, #0] 8007134: 461a mov r2, r3 8007136: 6cfb ldr r3, [r7, #76] @ 0x4c 8007138: 643b str r3, [r7, #64] @ 0x40 800713a: 63fa str r2, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800713c: 6bf9 ldr r1, [r7, #60] @ 0x3c 800713e: 6c3a ldr r2, [r7, #64] @ 0x40 8007140: e841 2300 strex r3, r2, [r1] 8007144: 63bb str r3, [r7, #56] @ 0x38 return(result); 8007146: 6bbb ldr r3, [r7, #56] @ 0x38 8007148: 2b00 cmp r3, #0 800714a: d1e6 bne.n 800711a ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 800714c: 687b ldr r3, [r7, #4] 800714e: 681b ldr r3, [r3, #0] 8007150: 3308 adds r3, #8 8007152: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8007154: 6a3b ldr r3, [r7, #32] 8007156: e853 3f00 ldrex r3, [r3] 800715a: 61fb str r3, [r7, #28] return(result); 800715c: 69fb ldr r3, [r7, #28] 800715e: f023 0301 bic.w r3, r3, #1 8007162: 64bb str r3, [r7, #72] @ 0x48 8007164: 687b ldr r3, [r7, #4] 8007166: 681b ldr r3, [r3, #0] 8007168: 3308 adds r3, #8 800716a: 6cba ldr r2, [r7, #72] @ 0x48 800716c: 62fa str r2, [r7, #44] @ 0x2c 800716e: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8007170: 6ab9 ldr r1, [r7, #40] @ 0x28 8007172: 6afa ldr r2, [r7, #44] @ 0x2c 8007174: e841 2300 strex r3, r2, [r1] 8007178: 627b str r3, [r7, #36] @ 0x24 return(result); 800717a: 6a7b ldr r3, [r7, #36] @ 0x24 800717c: 2b00 cmp r3, #0 800717e: d1e5 bne.n 800714c /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8007180: 687b ldr r3, [r7, #4] 8007182: 6e1b ldr r3, [r3, #96] @ 0x60 8007184: 2b01 cmp r3, #1 8007186: d118 bne.n 80071ba { ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8007188: 687b ldr r3, [r7, #4] 800718a: 681b ldr r3, [r3, #0] 800718c: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800718e: 68fb ldr r3, [r7, #12] 8007190: e853 3f00 ldrex r3, [r3] 8007194: 60bb str r3, [r7, #8] return(result); 8007196: 68bb ldr r3, [r7, #8] 8007198: f023 0310 bic.w r3, r3, #16 800719c: 647b str r3, [r7, #68] @ 0x44 800719e: 687b ldr r3, [r7, #4] 80071a0: 681b ldr r3, [r3, #0] 80071a2: 461a mov r2, r3 80071a4: 6c7b ldr r3, [r7, #68] @ 0x44 80071a6: 61bb str r3, [r7, #24] 80071a8: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80071aa: 6979 ldr r1, [r7, #20] 80071ac: 69ba ldr r2, [r7, #24] 80071ae: e841 2300 strex r3, r2, [r1] 80071b2: 613b str r3, [r7, #16] return(result); 80071b4: 693b ldr r3, [r7, #16] 80071b6: 2b00 cmp r3, #0 80071b8: d1e6 bne.n 8007188 } /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 80071ba: 687b ldr r3, [r7, #4] 80071bc: 2220 movs r2, #32 80071be: f8c3 2080 str.w r2, [r3, #128] @ 0x80 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 80071c2: 687b ldr r3, [r7, #4] 80071c4: 2200 movs r2, #0 80071c6: 661a str r2, [r3, #96] @ 0x60 /* Reset RxIsr function pointer */ huart->RxISR = NULL; 80071c8: 687b ldr r3, [r7, #4] 80071ca: 2200 movs r2, #0 80071cc: 669a str r2, [r3, #104] @ 0x68 } 80071ce: bf00 nop 80071d0: 3754 adds r7, #84 @ 0x54 80071d2: 46bd mov sp, r7 80071d4: f85d 7b04 ldr.w r7, [sp], #4 80071d8: 4770 bx lr 080071da : 80071da: 4402 add r2, r0 80071dc: 4603 mov r3, r0 80071de: 4293 cmp r3, r2 80071e0: d100 bne.n 80071e4 80071e2: 4770 bx lr 80071e4: f803 1b01 strb.w r1, [r3], #1 80071e8: e7f9 b.n 80071de ... 080071ec <__libc_init_array>: 80071ec: b570 push {r4, r5, r6, lr} 80071ee: 4d0d ldr r5, [pc, #52] @ (8007224 <__libc_init_array+0x38>) 80071f0: 4c0d ldr r4, [pc, #52] @ (8007228 <__libc_init_array+0x3c>) 80071f2: 1b64 subs r4, r4, r5 80071f4: 10a4 asrs r4, r4, #2 80071f6: 2600 movs r6, #0 80071f8: 42a6 cmp r6, r4 80071fa: d109 bne.n 8007210 <__libc_init_array+0x24> 80071fc: 4d0b ldr r5, [pc, #44] @ (800722c <__libc_init_array+0x40>) 80071fe: 4c0c ldr r4, [pc, #48] @ (8007230 <__libc_init_array+0x44>) 8007200: f000 f818 bl 8007234 <_init> 8007204: 1b64 subs r4, r4, r5 8007206: 10a4 asrs r4, r4, #2 8007208: 2600 movs r6, #0 800720a: 42a6 cmp r6, r4 800720c: d105 bne.n 800721a <__libc_init_array+0x2e> 800720e: bd70 pop {r4, r5, r6, pc} 8007210: f855 3b04 ldr.w r3, [r5], #4 8007214: 4798 blx r3 8007216: 3601 adds r6, #1 8007218: e7ee b.n 80071f8 <__libc_init_array+0xc> 800721a: f855 3b04 ldr.w r3, [r5], #4 800721e: 4798 blx r3 8007220: 3601 adds r6, #1 8007222: e7f2 b.n 800720a <__libc_init_array+0x1e> 8007224: 08007284 .word 0x08007284 8007228: 08007284 .word 0x08007284 800722c: 08007284 .word 0x08007284 8007230: 08007288 .word 0x08007288 08007234 <_init>: 8007234: b5f8 push {r3, r4, r5, r6, r7, lr} 8007236: bf00 nop 8007238: bcf8 pop {r3, r4, r5, r6, r7} 800723a: bc08 pop {r3} 800723c: 469e mov lr, r3 800723e: 4770 bx lr 08007240 <_fini>: 8007240: b5f8 push {r3, r4, r5, r6, r7, lr} 8007242: bf00 nop 8007244: bcf8 pop {r3, r4, r5, r6, r7} 8007246: bc08 pop {r3} 8007248: 469e mov lr, r3 800724a: 4770 bx lr