diff --git a/Documents/12V_pump_DCDC.pdf b/Documents/12V_pump_DCDC.pdf new file mode 100644 index 0000000..fec0ffb Binary files /dev/null and b/Documents/12V_pump_DCDC.pdf differ diff --git a/Documents/19V_ACU_DCDC.pdf b/Documents/19V_ACU_DCDC.pdf new file mode 100644 index 0000000..739a9ae Binary files /dev/null and b/Documents/19V_ACU_DCDC.pdf differ diff --git a/Documents/8V4_DRS_DCDC.pdf b/Documents/8V4_DRS_DCDC.pdf new file mode 100644 index 0000000..085403c Binary files /dev/null and b/Documents/8V4_DRS_DCDC.pdf differ diff --git a/Documents/ACU_DCDC.pdf b/Documents/ACU_DCDC.pdf deleted file mode 100644 index 53bb210..0000000 Binary files a/Documents/ACU_DCDC.pdf and /dev/null differ diff --git a/Documents/DRS_DCDC.pdf b/Documents/DRS_DCDC.pdf deleted file mode 100644 index 6072f2a..0000000 Binary files a/Documents/DRS_DCDC.pdf and /dev/null differ diff --git a/Documents/LM5148_calculation_table.xlsm b/Documents/LM5148_calculation_table.xlsm new file mode 100644 index 0000000..b73411a Binary files /dev/null and b/Documents/LM5148_calculation_table.xlsm differ diff --git a/Documents/PDU_Code.drawio b/Documents/PDU_Code.drawio deleted file mode 100644 index 59be7f7..0000000 --- a/Documents/PDU_Code.drawio +++ /dev/null @@ -1,145 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Documents/pump_DCDC.pdf b/Documents/pump_DCDC.pdf deleted file mode 100644 index 8ac0979..0000000 Binary files a/Documents/pump_DCDC.pdf and /dev/null differ diff --git a/Hardware/FT25_PDU.kicad_pcb b/Hardware/FT25_PDU.kicad_pcb index 5305f6c..ba74c0a 100644 --- a/Hardware/FT25_PDU.kicad_pcb +++ b/Hardware/FT25_PDU.kicad_pcb @@ -7414,7 +7414,7 @@ ) (fp_arc (start 0 2.2) - (mid 0.05 2.25) + (mid 0.050001 2.250001) (end 0 2.300001) (stroke (width 0.1) @@ -82275,343 +82275,6 @@ ) ) ) - (footprint "brain:toasty" - (layer "F.Cu") - (uuid "9e661cac-bbf1-4e9c-960e-b242aa83d97e") - (at 266.25 151.95) - (property "Reference" "G***" - (at 0 0 0) - (layer "F.SilkS") - (hide yes) - (uuid "7e0bca53-630b-4887-b616-e4c2eb8beeea") - (effects - (font - (size 1.5 1.5) - (thickness 0.3) - ) - ) - ) - (property "Value" "LOGO" - (at 0.75 0 0) - (layer "F.SilkS") - (hide yes) - (uuid "eb755ed6-df00-4757-8567-7b5d6a6e2185") - (effects - (font - (size 1.5 1.5) - (thickness 0.3) - ) - ) - ) - (property "Footprint" "brain:toasty" - (at 0 0 0) - (layer "F.Fab") - (hide yes) - (uuid "10d06b02-cf3f-4c99-8e26-90feb7730081") - (effects - (font - (size 1.27 1.27) - (thickness 0.15) - ) - ) - ) - (property "Datasheet" "" - (at 0 0 0) - (layer "F.Fab") - (hide yes) - (uuid "703e8053-df44-453a-9e11-8d8d469d0ba2") - (effects - (font - (size 1.27 1.27) - (thickness 0.15) - ) - ) - ) - (property "Description" "" - (at 0 0 0) - (layer "F.Fab") - (hide yes) - (uuid "5b218782-95f3-4013-8a62-463f7a21c34b") - (effects - (font - (size 1.27 1.27) - (thickness 0.15) - ) - ) - ) - (attr board_only exclude_from_pos_files exclude_from_bom) - (fp_poly - (pts - (xy 0.531564 -1.226003) (xy 0.625716 -1.217934) (xy 0.734536 -1.204303) (xy 0.838914 -1.187893) - (xy 0.920967 -1.171586) (xy 0.97572 -1.154922) (xy 1.009053 -1.135908) (xy 1.017495 -1.127455) (xy 1.044009 -1.073651) - (xy 1.040853 -1.017975) (xy 1.008874 -0.969812) (xy 1.002795 -0.964712) (xy 0.96484 -0.941441) (xy 0.923201 -0.933412) - (xy 0.867013 -0.939536) (xy 0.830608 -0.947437) (xy 0.78938 -0.955192) (xy 0.725299 -0.964973) (xy 0.648551 -0.97529) - (xy 0.598038 -0.981424) (xy 0.499321 -0.994987) (xy 0.428925 -1.010369) (xy 0.381949 -1.029453) - (xy 0.35349 -1.054128) (xy 0.340301 -1.080573) (xy 0.338725 -1.129613) (xy 0.357931 -1.178731) (xy 0.391364 -1.214679) - (xy 0.410998 -1.223483) (xy 0.458013 -1.228018) - ) - (stroke - (width 0) - (type solid) - ) - (fill solid) - (layer "F.SilkS") - (uuid "e80a966c-20dc-4595-bd88-9a7b448ce97a") - ) - (fp_poly - (pts - (xy 0.134169 0.277157) (xy 0.173265 0.304692) (xy 0.175183 0.30657) (xy 0.194755 0.326913) (xy 0.208907 0.346004) - (xy 0.215974 0.366119) (xy 0.214295 0.389535) (xy 0.202206 0.418529) (xy 0.178044 0.455378) (xy 0.140146 0.502358) - (xy 0.08685 0.561746) (xy 0.016493 0.635819) (xy -0.072588 0.726855) (xy -0.182057 0.837129) (xy -0.294928 0.950243) - (xy -0.419642 1.074914) (xy -0.523279 1.177894) (xy -0.608043 1.26119) (xy -0.67614 1.326812) (xy -0.729777 1.376767) - (xy -0.77116 1.413065) (xy -0.802494 1.437714) (xy -0.825985 1.452722) (xy -0.843839 1.460097) (xy -0.856846 1.46187) - (xy -0.914368 1.446443) (xy -0.943998 1.423422) (xy -0.961014 1.404388) (xy -0.972909 1.386256) - (xy -0.977981 1.366778) (xy -0.974526 1.343707) (xy -0.960845 1.314795) (xy -0.935235 1.277792) - (xy -0.895994 1.230452) (xy -0.84142 1.170526) (xy -0.769811 1.095765) (xy -0.679466 1.003923) (xy -0.568682 0.89275) - (xy -0.460378 0.784572) (xy -0.323148 0.648156) (xy -0.20762 0.534581) (xy -0.112538 0.442675) (xy -0.036641 0.371266) - (xy 0.021328 0.319183) (xy 0.062629 0.285253) (xy 0.088521 0.268305) (xy 0.096885 0.265794) - ) - (stroke - (width 0) - (type solid) - ) - (fill solid) - (layer "F.SilkS") - (uuid "1585b0d2-4ffb-4f00-b352-59967b10326d") - ) - (fp_poly - (pts - (xy 0.921913 1.054988) (xy 0.949482 1.078862) (xy 0.965131 1.09921) (xy 0.975835 1.118446) (xy 0.979862 1.138865) - (xy 0.975481 1.162761) (xy 0.960961 1.192427) (xy 0.934571 1.230156) (xy 0.894579 1.278242) (xy 0.839254 1.338979) - (xy 0.766866 1.41466) (xy 0.675683 1.507579) (xy 0.563974 1.62003) (xy 0.469652 1.714586) (xy 0.345483 1.838794) - (xy 0.242385 1.941354) (xy 0.158121 2.024294) (xy 0.090454 2.089645) (xy 0.037149 2.139435) (xy -0.004031 2.175694) - (xy -0.035323 2.200451) (xy -0.058962 2.215736) (xy -0.077185 2.223577) (xy -0.092229 2.226006) - (xy -0.093956 2.22603) (xy -0.146978 2.213486) (xy -0.181528 2.182259) (xy -0.205721 2.141466) (xy -0.215956 2.104278) - (xy -0.215958 2.103901) (xy -0.204261 2.082436) (xy -0.169076 2.039073) (xy -0.110269 1.973667) - (xy -0.027702 1.886073) (xy 0.078761 1.776144) (xy 0.209256 1.643734) (xy 0.297413 1.555171) (xy 0.421808 1.430776) - (xy 0.52512 1.328014) (xy 0.609587 1.244854) (xy 0.67745 1.179266) (xy 0.730949 1.129222) (xy 0.772323 1.092692) - (xy 0.803812 1.067646) (xy 0.827656 1.052054) (xy 0.846096 1.043887) (xy 0.86137 1.041116) (xy 0.864816 1.041029) - ) - (stroke - (width 0) - (type solid) - ) - (fill solid) - (layer "F.SilkS") - (uuid "5d071925-a521-4eb0-8173-c04a4848b679") - ) - (fp_poly - (pts - (xy 0.744053 0.479333) (xy 0.779092 0.51897) (xy 0.7944 0.57038) (xy 0.791143 0.60339) (xy 0.777982 0.621385) - (xy 0.743294 0.660595) (xy 0.689164 0.718859) (xy 0.617677 0.794018) (xy 0.530916 0.88391) (xy 0.430966 0.986376) - (xy 0.319912 1.099255) (xy 0.199837 1.220388) (xy 0.079018 1.341432) (xy -0.068553 1.488649) (xy -0.194584 1.613993) - (xy -0.300929 1.719187) (xy -0.389441 1.805953) (xy -0.461972 1.876011) (xy -0.520375 1.931085) - (xy -0.566502 1.972895) (xy -0.602206 2.003165) (xy -0.629341 2.023614) (xy -0.649758 2.035967) - (xy -0.665311 2.041943) (xy -0.676195 2.043296) (xy -0.729131 2.030305) (xy -0.762954 1.999525) - (xy -0.78715 1.958699) (xy -0.797382 1.921442) (xy -0.797384 1.921072) (xy -0.785944 1.903496) (xy -0.753276 1.865149) - (xy -0.70186 1.808537) (xy -0.634176 1.736167) (xy -0.552705 1.650545) (xy -0.459926 1.554176) (xy -0.358319 1.449568) - (xy -0.250365 1.339225) (xy -0.138542 1.225655) (xy -0.025332 1.111363) (xy 0.086786 0.998856) (xy 0.195332 0.890639) - (xy 0.297826 0.789218) (xy 0.391789 0.697101) (xy 0.474739 0.616792) (xy 0.544197 0.550798) (xy 0.597683 0.501625) - (xy 0.632717 0.471779) (xy 0.644655 0.463834) (xy 0.696751 0.458582) - ) - (stroke - (width 0) - (type solid) - ) - (fill solid) - (layer "F.SilkS") - (uuid "4f98e730-28a7-4678-b03d-dd19d50d3be6") - ) - (fp_poly - (pts - (xy 0.486771 -3.93074) (xy 0.527893 -3.911223) (xy 0.549697 -3.890244) (xy 0.560901 -3.859854) (xy 0.564663 -3.809709) - (xy 0.564813 -3.790316) (xy 0.560846 -3.728601) (xy 0.546613 -3.669363) (xy 0.518622 -3.599756) - (xy 0.505207 -3.571147) (xy 0.465632 -3.477346) (xy 0.447577 -3.3987) (xy 0.451093 -3.325008) (xy 0.476233 -3.246069) - (xy 0.50721 -3.181297) (xy 0.536817 -3.122468) (xy 0.554379 -3.077694) (xy 0.562552 -3.034473) (xy 0.563992 -2.980305) - (xy 0.562161 -2.922678) (xy 0.557153 -2.844046) (xy 0.547412 -2.785322) (xy 0.529785 -2.733229) - (xy 0.504936 -2.681734) (xy 0.475258 -2.616076) (xy 0.451718 -2.547934) (xy 0.44166 -2.50454) (xy 0.420317 -2.438843) - (xy 0.382963 -2.394467) (xy 0.335899 -2.373917) (xy 0.285427 -2.379697) (xy 0.237848 -2.414313) - (xy 0.232076 -2.421223) (xy 0.206221 -2.480643) (xy 0.206853 -2.559845) (xy 0.233945 -2.658594) - (xy 0.273695 -2.749585) (xy 0.312613 -2.83901) (xy 0.3301 -2.913678) (xy 0.326049 -2.98431) (xy 0.300354 -3.061628) - (xy 0.269947 -3.124482) (xy 0.238114 -3.188388) (xy 0.219549 -3.237852) (xy 0.210825 -3.287072) - (xy 0.208515 -3.350245) (xy 0.20859 -3.37863) (xy 0.210687 -3.451702) (xy 0.218167 -3.506346) (xy 0.234635 -3.557311) - (xy 0.263696 -3.619345) (xy 0.270886 -3.633497) (xy 0.300134 -3.696554) (xy 0.321808 -3.754418) - (xy 0.331947 -3.796239) (xy 0.332243 -3.801531) (xy 0.345668 -3.86335) (xy 0.380921 -3.908307) (xy 0.430466 -3.932179) - ) - (stroke - (width 0) - (type solid) - ) - (fill solid) - (layer "F.SilkS") - (uuid "e7f4bbcf-3618-40d9-b334-658d13e603e5") - ) - (fp_poly - (pts - (xy -0.285746 -3.933069) (xy -0.238125 -3.898622) (xy -0.232077 -3.8914) (xy -0.206221 -3.83198) - (xy -0.206854 -3.752778) (xy -0.233945 -3.65403) (xy -0.273696 -3.563038) (xy -0.312614 -3.473611) - (xy -0.330102 -3.398945) (xy -0.326051 -3.328321) (xy -0.300356 -3.251021) (xy -0.269948 -3.188187) - (xy -0.23808 -3.124201) (xy -0.219485 -3.074581) (xy -0.210713 -3.0251) (xy -0.208315 -2.96153) - (xy -0.20834 -2.934039) (xy -0.210198 -2.861659) (xy -0.217253 -2.808102) (xy -0.233052 -2.75901) - (xy -0.26114 -2.700023) (xy -0.270636 -2.681785) (xy -0.30029 -2.618996) (xy -0.322127 -2.560757) - (xy -0.332039 -2.518275) (xy -0.332244 -2.513751) (xy -0.345437 -2.450851) (xy -0.380182 -2.405043) - (xy -0.429224 -2.380494) (xy -0.485308 -2.381369) (xy -0.527893 -2.4014) (xy -0.549697 -2.42238) - (xy -0.560901 -2.45277) (xy -0.564664 -2.502914) (xy -0.564814 -2.522307) (xy -0.560846 -2.584022) - (xy -0.546614 -2.64326) (xy -0.518623 -2.712868) (xy -0.505208 -2.741476) (xy -0.465634 -2.835255) - (xy -0.44757 -2.913858) (xy -0.451074 -2.987477) (xy -0.476202 -3.066306) (xy -0.507393 -3.131393) - (xy -0.53635 -3.188501) (xy -0.55387 -3.231914) (xy -0.562348 -3.273345) (xy -0.564181 -3.324507) - (xy -0.561761 -3.39711) (xy -0.561756 -3.397242) (xy -0.556962 -3.475131) (xy -0.548656 -3.531518) - (xy -0.534019 -3.578117) (xy -0.510238 -3.626644) (xy -0.50385 -3.638118) (xy -0.473376 -3.702127) - (xy -0.449801 -3.769547) (xy -0.441164 -3.808083) (xy -0.420229 -3.873702) (xy -0.383128 -3.918087) - (xy -0.33619 -3.938717) - ) - (stroke - (width 0) - (type solid) - ) - (fill solid) - (layer "F.SilkS") - (uuid "3b4f9182-d155-46f5-bae6-c67190cb17e5") - ) - (fp_poly - (pts - (xy -1.065685 -3.931384) (xy -1.016251 -3.898609) (xy -1.014113 -3.896373) (xy -0.985764 -3.842311) - (xy -0.981774 -3.767888) (xy -1.001921 -3.675103) (xy -1.045985 -3.565951) (xy -1.051815 -3.553978) - (xy -1.080695 -3.489554) (xy -1.102233 -3.430127) (xy -1.112609 -3.386557) (xy -1.113015 -3.37996) - (xy -1.105695 -3.341592) (xy -1.086286 -3.284879) (xy -1.058616 -3.220641) (xy -1.051356 -3.205679) - (xy -1.021179 -3.142231) (xy -1.002797 -3.092454) (xy -0.993265 -3.043413) (xy -0.98964 -2.982173) - (xy -0.989065 -2.932047) (xy -0.989644 -2.858273) (xy -0.993998 -2.805695) (xy -1.004931 -2.762298) - (xy -1.025249 -2.716068) (xy -1.050724 -2.667902) (xy -1.081738 -2.604004) (xy -1.10388 -2.545147) - (xy -1.112975 -2.502547) (xy -1.113015 -2.500523) (xy -1.127251 -2.445459) (xy -1.163872 -2.40118) - (xy -1.21375 -2.377303) (xy -1.231628 -2.37554) (xy -1.271999 -2.387333) (xy -1.311115 -2.415747) - (xy -1.311591 -2.41625) (xy -1.339939 -2.470313) (xy -1.34393 -2.544735) (xy -1.323783 -2.63752) - (xy -1.279718 -2.746672) (xy -1.273889 -2.758645) (xy -1.245009 -2.823069) (xy -1.223471 -2.882496) - (xy -1.213094 -2.926066) (xy -1.212688 -2.932663) (xy -1.220009 -2.971032) (xy -1.239418 -3.027744) - (xy -1.267088 -3.091982) (xy -1.274348 -3.106944) (xy -1.304525 -3.170394) (xy -1.322908 -3.220174) - (xy -1.33244 -3.269219) (xy -1.336067 -3.330466) (xy -1.336643 -3.380576) (xy -1.335994 -3.454892) - (xy -1.331663 -3.507241) (xy -1.321211 -3.548856) (xy -1.302198 -3.590969) (xy -1.28362 -3.624769) - (xy -1.252856 -3.687442) (xy -1.2289 -3.751406) (xy -1.219165 -3.79089) (xy -1.197845 -3.861397) - (xy -1.161688 -3.9101) (xy -1.115899 -3.934322) - ) - (stroke - (width 0) - (type solid) - ) - (fill solid) - (layer "F.SilkS") - (uuid "5b394159-9d6b-4e54-a485-0f9496d85ee2") - ) - (fp_poly - (pts - (xy 1.260018 -3.931384) (xy 1.309452 -3.898609) (xy 1.31159 -3.896373) (xy 1.339939 -3.842311) (xy 1.343929 -3.767888) - (xy 1.323783 -3.675103) (xy 1.279718 -3.565951) (xy 1.273888 -3.553978) (xy 1.245008 -3.489554) - (xy 1.22347 -3.430127) (xy 1.213094 -3.386557) (xy 1.212688 -3.37996) (xy 1.220008 -3.341592) (xy 1.239417 -3.284879) - (xy 1.267088 -3.220641) (xy 1.274347 -3.205679) (xy 1.304524 -3.142231) (xy 1.322906 -3.092454) - (xy 1.332438 -3.043413) (xy 1.336063 -2.982173) (xy 1.336638 -2.932047) (xy 1.336059 -2.858273) - (xy 1.331705 -2.805695) (xy 1.320772 -2.762298) (xy 1.300454 -2.716068) (xy 1.274979 -2.667902) - (xy 1.243965 -2.604004) (xy 1.221823 -2.545147) (xy 1.212728 -2.502547) (xy 1.212688 -2.500523) - (xy 1.198452 -2.445459) (xy 1.161831 -2.40118) (xy 1.111953 -2.377303) (xy 1.094075 -2.37554) (xy 1.053704 -2.387333) - (xy 1.014589 -2.415747) (xy 1.014112 -2.41625) (xy 0.985764 -2.470313) (xy 0.981773 -2.544735) (xy 1.00192 -2.63752) - (xy 1.045985 -2.746672) (xy 1.051814 -2.758645) (xy 1.080695 -2.823069) (xy 1.102232 -2.882496) - (xy 1.112609 -2.926066) (xy 1.113015 -2.932663) (xy 1.105694 -2.971032) (xy 1.086285 -3.027744) - (xy 1.058615 -3.091982) (xy 1.051355 -3.106944) (xy 1.021178 -3.170394) (xy 1.002795 -3.220174) - (xy 0.993263 -3.269219) (xy 0.989636 -3.330466) (xy 0.98906 -3.380576) (xy 0.989709 -3.454892) (xy 0.99404 -3.507241) - (xy 1.004492 -3.548856) (xy 1.023505 -3.590969) (xy 1.042083 -3.624769) (xy 1.072847 -3.687442) - (xy 1.096803 -3.751406) (xy 1.106538 -3.79089) (xy 1.127858 -3.861397) (xy 1.164016 -3.9101) (xy 1.209804 -3.934322) - ) - (stroke - (width 0) - (type solid) - ) - (fill solid) - (layer "F.SilkS") - (uuid "3c371b7d-331f-487a-8166-4950056e7a1b") - ) - (fp_poly - (pts - (xy 0.122847 -2.04702) (xy 0.248034 -2.044361) (xy 0.36707 -2.040298) (xy 0.471467 -2.03513) (xy 0.552738 -2.02916) - (xy 0.564813 -2.027964) (xy 0.91212 -1.98183) (xy 1.232503 -1.919063) (xy 1.5256 -1.839801) (xy 1.791047 -1.744183) - (xy 2.028482 -1.632349) (xy 2.237541 -1.504437) (xy 2.417861 -1.360585) (xy 2.486698 -1.293629) - (xy 2.600508 -1.154546) (xy 2.684165 -1.005317) (xy 2.737062 -0.848463) (xy 2.75859 -0.686505) (xy 2.748142 -0.521966) - (xy 2.709422 -0.369483) (xy 2.647875 -0.224984) (xy 2.565218 -0.088312) (xy 2.457227 0.046919) (xy 2.379692 0.128841) - (xy 2.242642 0.266269) (xy 2.242642 2.065556) (xy 2.242642 3.864843) (xy 2.204194 3.900963) (xy 2.165746 3.937083) - (xy -0.002328 3.937083) (xy -2.170402 3.937083) (xy -2.206522 3.898635) (xy -2.242643 3.860187) - (xy -2.242643 2.062222) (xy -2.242643 0.264257) (xy -2.373549 0.136282) (xy -2.513549 -0.018327) - (xy -2.622363 -0.177298) (xy -2.699706 -0.339402) (xy -2.745295 -0.503407) (xy -2.757503 -0.651759) - (xy -2.524697 -0.651759) (xy -2.508898 -0.516082) (xy -2.461125 -0.378973) (xy -2.381144 -0.239797) - (xy -2.268716 -0.097917) (xy -2.123606 0.047301) (xy -2.08898 0.078262) (xy -2.010072 0.147568) - (xy -2.010072 1.92604) (xy -2.010072 3.704512) (xy 0 3.704512) (xy 2.010072 3.704512) (xy 2.010072 1.924745) - (xy 2.010072 0.144977) (xy 2.088979 0.076741) (xy 2.229085 -0.054234) (xy 2.33944 -0.17988) (xy 2.422407 -0.303385) - (xy 2.48035 -0.427935) (xy 2.494513 -0.47024) (xy 2.520879 -0.609973) (xy 2.515132 -0.74685) (xy 2.478331 -0.879877) - (xy 2.411537 -1.008056) (xy 2.315809 -1.130391) (xy 2.192207 -1.245887) (xy 2.041789 -1.353546) - (xy 1.865616 -1.452373) (xy 1.664747 -1.541372) (xy 1.440242 -1.619546) (xy 1.204382 -1.683268) - (xy 1.063124 -1.715253) (xy 0.934055 -1.741094) (xy 0.81099 -1.761393) (xy 0.687746 -1.776757) (xy 0.558139 -1.787789) - (xy 0.415987 -1.795096) (xy 0.255104 -1.79928) (xy 0.069309 -1.800947) (xy 0 -1.801048) (xy -0.155616 -1.800819) - (xy -0.283242 -1.799968) (xy -0.388115 -1.798243) (xy -0.475468 -1.795394) (xy -0.550534 -1.791171) - (xy -0.618548 -1.785324) (xy -0.684744 -1.777603) (xy -0.754356 -1.767757) (xy -0.780772 -1.763719) - (xy -1.099692 -1.705161) (xy -1.388553 -1.632955) (xy -1.647628 -1.547008) (xy -1.877192 -1.447228) - (xy -2.07752 -1.333521) (xy -2.109745 -1.312079) (xy -2.209212 -1.234167) (xy -2.304131 -1.141371) - (xy -2.386645 -1.042423) (xy -2.448895 -0.946057) (xy -2.461326 -0.921362) (xy -2.508761 -0.786641) - (xy -2.524697 -0.651759) (xy -2.757503 -0.651759) (xy -2.758846 -0.668082) (xy -2.740073 -0.832197) - (xy -2.688694 -0.994521) (xy -2.652343 -1.071485) (xy -2.605402 -1.144462) (xy -2.53732 -1.228681) - (xy -2.454825 -1.317296) (xy -2.364645 -1.403462) (xy -2.273509 -1.480335) (xy -2.195127 -1.536629) - (xy -1.974687 -1.661297) (xy -1.725922 -1.769851) (xy -1.449707 -1.862027) (xy -1.146914 -1.937561) - (xy -0.81842 -1.996191) (xy -0.564814 -2.027964) (xy -0.488873 -2.034053) (xy -0.388199 -2.039396) - (xy -0.271281 -2.043691) (xy -0.146607 -2.046638) (xy -0.022666 -2.047937) (xy 0 -2.047973) - ) - (stroke - (width 0) - (type solid) - ) - (fill solid) - (layer "F.SilkS") - (uuid "397348ab-5c52-413c-8813-ef3d186d043e") - ) - (fp_poly - (pts - (xy 0.080758 -1.649632) (xy 0.307529 -1.640957) (xy 0.53075 -1.625074) (xy 0.741495 -1.60227) (xy 0.863832 -1.584482) - (xy 1.088874 -1.540985) (xy 1.305381 -1.485705) (xy 1.509836 -1.42017) (xy 1.698725 -1.345909) (xy 1.868531 -1.264451) - (xy 2.015739 -1.177324) (xy 2.136832 -1.086059) (xy 2.228295 -0.992183) (xy 2.229618 -0.990518) - (xy 2.288833 -0.907563) (xy 2.32576 -0.83202) (xy 2.344768 -0.751476) (xy 2.350228 -0.653513) (xy 2.350223 -0.647875) - (xy 2.348386 -0.571565) (xy 2.341773 -0.516249) (xy 2.32796 -0.469779) (xy 2.304942 -0.420803) (xy 2.233217 -0.30759) - (xy 2.137505 -0.192589) (xy 2.025376 -0.084414) (xy 1.968332 -0.037742) (xy 1.844136 0.058142) (xy 1.844043 1.762146) - (xy 1.84395 3.466151) (xy 1.805502 3.502271) (xy 1.767054 3.538391) (xy -0.002328 3.538391) (xy -1.77171 3.538391) - (xy -1.807831 3.499943) (xy -1.843951 3.461495) (xy -1.844044 1.759818) (xy -1.844137 0.058142) - (xy -1.968332 -0.037742) (xy -2.08353 -0.137567) (xy -2.185949 -0.247521) (xy -2.26837 -0.359359) - (xy -2.303644 -0.420803) (xy -2.340313 -0.5218) (xy -2.356728 -0.633245) (xy -2.353996 -0.693492) - (xy -2.120606 -0.693492) (xy -2.117673 -0.611573) (xy -2.085042 -0.521437) (xy -2.024418 -0.425713) - (xy -1.937507 -0.327029) (xy -1.826016 -0.228014) (xy -1.810711 -0.215958) (xy -1.749703 -0.167997) - (xy -1.695943 -0.124799) (xy -1.656557 -0.092142) (xy -1.641626 -0.078908) (xy -1.636699 -0.073017) - (xy -1.632337 -0.06409) (xy -1.628506 -0.05019) (xy -1.625172 -0.029379) (xy -1.622299 0.00028) - (xy -1.619854 0.040724) (xy -1.617803 0.09389) (xy -1.616111 0.161714) (xy -1.614744 0.246136) (xy -1.613668 0.34909) - (xy -1.612847 0.472515) (xy -1.612249 0.618348) (xy -1.611838 0.788526) (xy -1.61158 0.984985) (xy -1.611441 1.209664) - (xy -1.611387 1.464499) (xy -1.61138 1.627992) (xy -1.61138 3.30582) (xy 0 3.30582) (xy 1.61138 3.30582) - (xy 1.61138 1.627992) (xy 1.611401 1.354655) (xy 1.611486 1.112606) (xy 1.61167 0.899907) (xy 1.611987 0.71462) - (xy 1.612472 0.55481) (xy 1.613159 0.418538) (xy 1.614082 0.303867) (xy 1.615275 0.208861) (xy 1.616773 0.131582) - (xy 1.618611 0.070094) (xy 1.620821 0.022458) (xy 1.62344 -0.013262) (xy 1.626501 -0.039004) (xy 1.630038 -0.056703) - (xy 1.634085 -0.068299) (xy 1.638678 -0.075727) (xy 1.641626 -0.078908) (xy 1.667173 -0.101103) - (xy 1.711938 -0.137765) (xy 1.768795 -0.183117) (xy 1.81071 -0.215958) (xy 1.925103 -0.314832) (xy 2.015124 -0.413698) - (xy 2.079068 -0.509928) (xy 2.11523 -0.600892) (xy 2.121903 -0.683962) (xy 2.120605 -0.693492) (xy 2.091129 -0.775931) - (xy 2.030913 -0.858552) (xy 1.942404 -0.939995) (xy 1.82805 -1.018901) (xy 1.690299 -1.093911) (xy 1.531599 -1.163665) - (xy 1.354399 -1.226803) (xy 1.161145 -1.281965) (xy 0.991746 -1.32043) (xy 0.674569 -1.371829) (xy 0.340058 -1.402595) - (xy -0.003081 -1.412728) (xy -0.346142 -1.402226) (xy -0.680419 -1.371091) (xy -0.991746 -1.32043) - (xy -1.195564 -1.273022) (xy -1.385605 -1.216486) (xy -1.559397 -1.152196) (xy -1.714463 -1.081526) - (xy -1.848328 -1.00585) (xy -1.958518 -0.926545) (xy -2.042558 -0.844983) (xy -2.097972 -0.76254) - (xy -2.120606 -0.693492) (xy -2.353996 -0.693492) (xy -2.351786 -0.742226) (xy -2.336505 -0.805909) - (xy -2.280302 -0.920976) (xy -2.192867 -1.030719) (xy -2.075878 -1.13437) (xy -1.931012 -1.231166) - (xy -1.759948 -1.32034) (xy -1.564363 -1.401127) (xy -1.345935 -1.47276) (xy -1.106342 -1.534475) - (xy -0.847262 -1.585506) (xy -0.570373 -1.625087) (xy -0.53159 -1.629526) (xy -0.347727 -1.644205) - (xy -0.140636 -1.650811) - ) - (stroke - (width 0) - (type solid) - ) - (fill solid) - (layer "F.SilkS") - (uuid "90cc2537-0acd-482e-a478-174d613215f0") - ) - ) (footprint "824501241:DIOM5127X250N" (layer "F.Cu") (uuid "9eab8db0-4919-4e0c-b7ba-c34c2e8c2084") @@ -146921,19 +146584,6 @@ (justify left bottom) ) ) - (gr_text "might get toasty" - (at 256.06 158.74 0) - (layer "F.SilkS" knockout) - (uuid "b5d190fe-882b-4a4c-bec8-951082c287ec") - (effects - (font - (size 1.5 1.5) - (thickness 0.3) - (bold yes) - ) - (justify left bottom) - ) - ) (gr_text "8" (at 260.6 135 0) (layer "F.SilkS") diff --git a/Software/Code/Core/Inc/can_communication.h b/Software/Code/Core/Inc/can_communication.h index 6703acc..d35635d 100644 --- a/Software/Code/Core/Inc/can_communication.h +++ b/Software/Code/Core/Inc/can_communication.h @@ -29,5 +29,6 @@ typedef struct { void can_init(CAN_HandleTypeDef* hcan); void can_rxupdateFrame(); void can_sendloop(); +void can_error_report(); #endif /* INC_CAN_COMMUNICATION_H_ */ diff --git a/Software/Code/Core/Inc/current_monitoring.h b/Software/Code/Core/Inc/current_monitoring.h index f041c36..f2fa187 100644 --- a/Software/Code/Core/Inc/current_monitoring.h +++ b/Software/Code/Core/Inc/current_monitoring.h @@ -11,7 +11,7 @@ #include "stm32f3xx_hal.h" // convert ADC quants to V -#define ADC_V_FACTOR (3.3f / 4095) // 3.3V / 12bit +#define ADC_V_FACTOR ((3.3f / 4095) * (3.3f / 3.14f)) // 3.3V / 12bit // scale to LV by divider to mV #define LV_SENSE_FACTOR (1e3 * (ADC_V_FACTOR * ((12.f + 1.8f) / 1.8f))) // scaled with voltage divider diff --git a/Software/Code/Core/Inc/plausibility_check.h b/Software/Code/Core/Inc/plausibility_check.h index b124b37..ccbf33b 100644 --- a/Software/Code/Core/Inc/plausibility_check.h +++ b/Software/Code/Core/Inc/plausibility_check.h @@ -12,6 +12,42 @@ #include "channel_control.h" #include "can_communication.h" +typedef union { + struct { + uint8_t sdc_open : 1; + uint8_t noload_acc_cooling : 1; + uint8_t noload_ts_cooling : 1; + uint8_t noload_drs : 1; + uint8_t noload_acu : 1; + uint8_t noload_epsc : 1; + uint8_t noload_inverter : 1; + uint8_t noload_lidar : 1; + }; + uint8_t group1; +} err_group1; + +typedef union { + struct { + uint8_t noload_misc : 1; + uint8_t noload_alwayson : 1; + uint8_t noload_sdc : 1; + uint8_t noload_ebs1 : 1; + uint8_t noload_ebs2 : 1; + uint8_t noload_ebs3 : 1; + uint8_t power_critcal : 1; + uint8_t power_limit : 1; + }; + uint8_t group2; +} err_group2; + +typedef union { + struct { + err_group1 group1; + err_group2 group2; + }; + uint16_t err_bitmask; +} err_states; + void check_plausibility(); #endif /* INC_PLAUSIBILITY_CHECK_H_ */ diff --git a/Software/Code/Core/Src/can_communication.c b/Software/Code/Core/Src/can_communication.c index 5a46454..982f8ea 100644 --- a/Software/Code/Core/Src/can_communication.c +++ b/Software/Code/Core/Src/can_communication.c @@ -14,7 +14,7 @@ rx_status_frame rxstate = {}; volatile uint8_t canmsg_received = 0; extern enable_gpios update_ports; extern current_measurements current_measurements_adc_val; -extern uint8_t error_data[16]; +extern err_states error; extern uint32_t lastheartbeat; @@ -93,39 +93,10 @@ void can_sendloop(){ } void can_error_report(){ - - static int error_loop = 0; - uint8_t data[8]; - - switch (error_loop){ - case 0: // 1 = error 0 = no error - data[0] = error_data[0]; // SDC-Status - data[1] = error_data[1]; // power draw critical (550W) - data[2] = error_data[2]; // power limit (> 600W) - data[3] = error_data[3]; // acc-cooling false OFF - data[4] = error_data[4]; // ts-cooling false OFF - data[5] = error_data[5]; // drs false OFF - data[6] = error_data[6]; // acu false OFF - data[7] = error_data[7]; // epsc false OFF - ftcan_transmit(ERROR_ID, data, 8); - break; - - case 1: // 3 = error 2 = no error - data[8] = error_data[8]; // inverter false OFF - data[9] = error_data[9]; // lidar false OFF - data[10] = error_data[10]; // misc false OFF - data[11] = error_data[11]; // always on false OFF - data[12] = error_data[12]; // sdc false OFF - data[13] = error_data[13]; // ebs1 false OFF - data[14] = error_data[14]; // ebs2 false OFF - data[15] = error_data[15]; // ebs3 false OFF - ftcan_transmit(ERROR_ID, data, 8); - break; - - default: - break; - } - error_loop = (error_loop + 1) % 2; + uint8_t error_data[2]; + error_data[0] = error.group1.group1; + error_data[1] = error.group2.group2; + ftcan_transmit(ERROR_ID, error_data, 2); } void ftcan_msg_received_cb(uint16_t id, size_t datalen, const uint8_t* data){ diff --git a/Software/Code/Core/Src/channel_control.c b/Software/Code/Core/Src/channel_control.c index a869a9d..329c63b 100644 --- a/Software/Code/Core/Src/channel_control.c +++ b/Software/Code/Core/Src/channel_control.c @@ -25,7 +25,7 @@ void ChannelControl_init(){ void ChannelControl_UpdateGPIOs(enable_gpios UpdatePorts){ - UpdatePorts.portb.alwayson = 1; + UpdatePorts.portb.alwayson = 1; // ensure always on stays always on if (inhibit_SDC == 1){ UpdatePorts.portb.sdc = 0; HAL_GPIO_WritePin(LED1_GPIO_Port, LED1_Pin, 1); @@ -37,11 +37,9 @@ void ChannelControl_UpdateGPIOs(enable_gpios UpdatePorts){ if (prev_epsc_state == 0 && UpdatePorts.porta.epsc == 1){ HAL_GPIO_WritePin(PC_EN_GPIO_Port, PC_EN_Pin, 1); // enable precharge - HAL_GPIO_WritePin(LED3_GPIO_Port, LED3_Pin, 1); - if (current_measurements_adc_val.epsc_precharge >= (0.95f * current_measurements_adc_val.asms_v)) { // precharge complete - HAL_GPIO_WritePin(IN5_GPIO_Port, IN5_Pin, (GPIO_PinState)UpdatePorts.porta.epsc); // switch PROFET + if (current_measurements_adc_val.epsc_precharge >= (0.95f * current_measurements_adc_val.asms_v)) { // check if precharge is complete (no while loop needed, this function is called by the main while-loop) + HAL_GPIO_WritePin(IN5_GPIO_Port, IN5_Pin, (GPIO_PinState)UpdatePorts.porta.epsc); // switch on PROFET HAL_GPIO_WritePin(PC_EN_GPIO_Port, PC_EN_Pin, 0); // disengage precharge - HAL_GPIO_WritePin(LED3_GPIO_Port, LED3_Pin, 0); prev_epsc_state = UpdatePorts.porta.epsc; } } @@ -54,8 +52,8 @@ void ChannelControl_UpdateGPIOs(enable_gpios UpdatePorts){ HAL_GPIO_WritePin(IN6_GPIO_Port, IN6_Pin, (GPIO_PinState)UpdatePorts.porta.inverter); // inverter HAL_GPIO_WritePin(IN7_GPIO_Port, IN7_Pin, (GPIO_PinState)UpdatePorts.porta.lidar); // lidar HAL_GPIO_WritePin(IN8_GPIO_Port, IN8_Pin, (GPIO_PinState)UpdatePorts.porta.misc); // MISC - HAL_GPIO_WritePin(IN9_GPIO_Port, IN9_Pin, (GPIO_PinState)UpdatePorts.portb.alwayson); // always on -> standardmäßig auf HIGH forcen - HAL_GPIO_WritePin(IN10_GPIO_Port, IN10_Pin, (GPIO_PinState)UpdatePorts.portb.sdc); // SDC -> muss anders controlled werden + HAL_GPIO_WritePin(IN9_GPIO_Port, IN9_Pin, (GPIO_PinState)UpdatePorts.portb.alwayson); // always on + HAL_GPIO_WritePin(IN10_GPIO_Port, IN10_Pin, (GPIO_PinState)UpdatePorts.portb.sdc); // SDC HAL_GPIO_WritePin(IN11_GPIO_Port, IN11_Pin, (GPIO_PinState)UpdatePorts.portb.ebs1); // EBS 1 HAL_GPIO_WritePin(IN12_GPIO_Port, IN12_Pin, (GPIO_PinState)UpdatePorts.portb.ebs2); // EBS 2 HAL_GPIO_WritePin(IN13_GPIO_Port, IN13_Pin, (GPIO_PinState)UpdatePorts.portb.ebs3); // EBS 3 diff --git a/Software/Code/Core/Src/main.c b/Software/Code/Core/Src/main.c index 610636b..451c0b8 100644 --- a/Software/Code/Core/Src/main.c +++ b/Software/Code/Core/Src/main.c @@ -23,7 +23,7 @@ /* USER CODE BEGIN Includes */ #include "can_communication.h" #include "channel_control.h" -//#include "plausibility_check.h" +#include "plausibility_check.h" /* USER CODE END Includes */ /* Private typedef -----------------------------------------------------------*/ @@ -119,6 +119,7 @@ int main(void) MX_UART4_Init(); MX_TIM6_Init(); /* USER CODE BEGIN 2 */ + // begin start-up animation HAL_GPIO_WritePin(LED1_GPIO_Port, LED1_Pin, GPIO_PIN_SET); HAL_Delay(100); @@ -142,6 +143,7 @@ int main(void) HAL_GPIO_WritePin(LED3_GPIO_Port, LED3_Pin, GPIO_PIN_RESET); HAL_GPIO_WritePin(LED4_GPIO_Port, LED4_Pin, GPIO_PIN_RESET); // end start-up animation + HAL_GPIO_WritePin(LED4_GPIO_Port, LED4_Pin, GPIO_PIN_SET); // indicates running STM ChannelControl_init(); @@ -167,8 +169,9 @@ int main(void) } if ((HAL_GetTick() - lasttick) > 100u){ lasttick = HAL_GetTick(); + check_plausibility(); can_sendloop(); - //can_error_report(); + can_error_report(); } if (((HAL_GetTick() - lastheartbeat) > 200U) && (HAL_GetTick() > 1000U)) { inhibit_SDC = 1; @@ -176,12 +179,10 @@ int main(void) HAL_GPIO_WritePin(LED1_GPIO_Port, LED1_Pin, (GPIO_PinState)!update_ports.portb.sdc); // indicates open SDC HAL_GPIO_WritePin(LED2_GPIO_Port, LED2_Pin, (GPIO_PinState)inhibit_SDC); // indicates watchdog-status - // overcurrent check (wenn funktioniert, LED schalten) + ChannelControl_UpdateGPIOs(update_ports); current_monitor_checklimits(); // currently not implemented - - //check_plausibility(); } /* USER CODE END 3 */ } diff --git a/Software/Code/Core/Src/plausibility_check.c b/Software/Code/Core/Src/plausibility_check.c index 6d9c0d7..cb64357 100644 --- a/Software/Code/Core/Src/plausibility_check.c +++ b/Software/Code/Core/Src/plausibility_check.c @@ -8,102 +8,103 @@ extern enable_gpios update_ports; extern current_measurements current_measurements_adc_val; -volatile uint8_t error_data[16]; +volatile err_states error; +extern int inhibit_SDC; void check_plausibility() { - if (!update_ports.portb.sdc) {error_data[0] = 1;} - else {error_data[0] = 0;} + if (!update_ports.portb.sdc || inhibit_SDC == 1) {error.group1.sdc_open = 1;} + else {error.group1.sdc_open = 0;} if (update_ports.porta.acc_cooling == 1 && current_measurements_adc_val.acc_cooling == 0) { - error_data[3] = 1; + error.group1.noload_acc_cooling = 1; } else { - error_data[3] = 0; + error.group1.noload_acc_cooling = 0; } if (update_ports.porta.ts_cooling == 1 && current_measurements_adc_val.ts_cooling == 0) { - error_data[4] = 1; - } - else { - error_data[4] = 0; - } + error.group1.noload_ts_cooling = 1; + } + else { + error.group1.noload_ts_cooling = 0; + } if (update_ports.porta.drs == 1 && current_measurements_adc_val.drs == 0) { - error_data[5] = 1; - } - else { - error_data[5] = 0; - } + error.group1.noload_drs = 1; + } + else { + error.group1.noload_drs = 0; + } if (update_ports.porta.acu == 1 && current_measurements_adc_val.acu == 0) { - error_data[6] = 1; - } - else { - error_data[6] = 0; - } + error.group1.noload_acu = 1; + } + else { + error.group1.noload_acu = 0; + } if (update_ports.porta.epsc == 1 && current_measurements_adc_val.epsc == 0) { - error_data[7] = 1; - } - else { - error_data[7] = 0; - } + error.group1.noload_epsc = 1; + } + else { + error.group1.noload_epsc = 0; + } if (update_ports.porta.inverter == 1 && current_measurements_adc_val.inverter == 0) { - error_data[8] = 3; - } - else { - error_data[8] = 2; - } + error.group1.noload_inverter = 1; + } + else { + error.group1.noload_inverter = 0; + } if (update_ports.porta.lidar == 1 && current_measurements_adc_val.lidar == 0) { - error_data[9] = 3; - } - else { - error_data[9] = 2; - } + error.group1.noload_lidar = 1; + } + else { + error.group1.noload_lidar = 0; + } if (update_ports.porta.misc == 1 && current_measurements_adc_val.misc == 0) { - error_data[10] = 3; - } - else { - error_data[10] = 2; - } + error.group2.noload_misc = 1; + } + else { + error.group2.noload_misc = 0; + } if (update_ports.portb.alwayson == 1 && current_measurements_adc_val.alwayson == 0) { - error_data[11] = 3; - } - else { - error_data[11] = 2; - } + error.group2.noload_alwayson = 1; + } + else { + error.group2.noload_alwayson = 0; + } if (update_ports.portb.sdc == 1 && current_measurements_adc_val.sdc == 0) { - error_data[12] = 3; - } - else { - error_data[12] = 2; - } + error.group2.noload_sdc = 1; + } + else { + error.group2.noload_sdc = 0; + } if (update_ports.portb.ebs1 == 1 && current_measurements_adc_val.ebs1 == 0) { - error_data[13] = 3; - } - else { - error_data[13] = 2; - } + error.group2.noload_ebs1 = 1; + } + else { + error.group2.noload_ebs1 = 0; + } if (update_ports.portb.ebs2 == 1 && current_measurements_adc_val.ebs2 == 0) { - error_data[14] = 3; - } - else { - error_data[14] = 2; - } + error.group2.noload_ebs2 = 1; + } + else { + error.group2.noload_ebs2 = 0; + } if (update_ports.portb.ebs3 == 1 && current_measurements_adc_val.ebs3 == 0) { - error_data[15] = 3; - } - else { - error_data[15] = 2; - } + error.group2.noload_ebs3 = 1; + } + else { + error.group2.noload_ebs3 = 0; + } } diff --git a/Software/Code/Debug/Core/Src/can_communication.cyclo b/Software/Code/Debug/Core/Src/can_communication.cyclo index 867b266..677efe4 100644 --- a/Software/Code/Debug/Core/Src/can_communication.cyclo +++ b/Software/Code/Debug/Core/Src/can_communication.cyclo @@ -1,4 +1,4 @@ ../Core/Src/can_communication.c:23:6:can_init 1 ../Core/Src/can_communication.c:28:6:can_sendloop 5 -../Core/Src/can_communication.c:95:6:can_error_report 3 -../Core/Src/can_communication.c:131:6:ftcan_msg_received_cb 4 +../Core/Src/can_communication.c:95:6:can_error_report 1 +../Core/Src/can_communication.c:102:6:ftcan_msg_received_cb 4 diff --git a/Software/Code/Debug/Core/Src/can_communication.o b/Software/Code/Debug/Core/Src/can_communication.o index dd4b9c8..f1e880d 100644 Binary files a/Software/Code/Debug/Core/Src/can_communication.o and b/Software/Code/Debug/Core/Src/can_communication.o differ diff --git a/Software/Code/Debug/Core/Src/can_communication.su b/Software/Code/Debug/Core/Src/can_communication.su index b10d7e8..8ce1dd1 100644 --- a/Software/Code/Debug/Core/Src/can_communication.su +++ b/Software/Code/Debug/Core/Src/can_communication.su @@ -1,4 +1,4 @@ ../Core/Src/can_communication.c:23:6:can_init 16 static ../Core/Src/can_communication.c:28:6:can_sendloop 24 static ../Core/Src/can_communication.c:95:6:can_error_report 16 static -../Core/Src/can_communication.c:131:6:ftcan_msg_received_cb 24 static +../Core/Src/can_communication.c:102:6:ftcan_msg_received_cb 24 static diff --git a/Software/Code/Debug/Core/Src/channel_control.o b/Software/Code/Debug/Core/Src/channel_control.o index 1a6563c..a21307e 100644 Binary files a/Software/Code/Debug/Core/Src/channel_control.o and b/Software/Code/Debug/Core/Src/channel_control.o differ diff --git a/Software/Code/Debug/Core/Src/current_monitoring.o b/Software/Code/Debug/Core/Src/current_monitoring.o index 3b0a27e..8df7e93 100644 Binary files a/Software/Code/Debug/Core/Src/current_monitoring.o and b/Software/Code/Debug/Core/Src/current_monitoring.o differ diff --git a/Software/Code/Debug/Core/Src/main.cyclo b/Software/Code/Debug/Core/Src/main.cyclo index 4ca8531..45c21af 100644 --- a/Software/Code/Debug/Core/Src/main.cyclo +++ b/Software/Code/Debug/Core/Src/main.cyclo @@ -1,10 +1,10 @@ ../Core/Src/main.c:90:5:main 5 -../Core/Src/main.c:193:6:SystemClock_Config 4 -../Core/Src/main.c:241:13:MX_ADC1_Init 11 -../Core/Src/main.c:370:13:MX_ADC2_Init 8 -../Core/Src/main.c:472:13:MX_CAN_Init 2 -../Core/Src/main.c:509:13:MX_TIM6_Init 3 -../Core/Src/main.c:547:13:MX_UART4_Init 2 -../Core/Src/main.c:580:13:MX_DMA_Init 1 -../Core/Src/main.c:602:13:MX_GPIO_Init 1 -../Core/Src/main.c:665:6:Error_Handler 1 +../Core/Src/main.c:194:6:SystemClock_Config 4 +../Core/Src/main.c:242:13:MX_ADC1_Init 11 +../Core/Src/main.c:371:13:MX_ADC2_Init 8 +../Core/Src/main.c:473:13:MX_CAN_Init 2 +../Core/Src/main.c:510:13:MX_TIM6_Init 3 +../Core/Src/main.c:548:13:MX_UART4_Init 2 +../Core/Src/main.c:581:13:MX_DMA_Init 1 +../Core/Src/main.c:603:13:MX_GPIO_Init 1 +../Core/Src/main.c:666:6:Error_Handler 1 diff --git a/Software/Code/Debug/Core/Src/main.d b/Software/Code/Debug/Core/Src/main.d index 42c0e9c..64691b8 100644 --- a/Software/Code/Debug/Core/Src/main.d +++ b/Software/Code/Debug/Core/Src/main.d @@ -34,7 +34,8 @@ Core/Src/main.o: ../Core/Src/main.c ../Core/Inc/main.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_uart_ex.h \ ../Core/Inc/can_communication.h ../Core/Inc/channel_control.h \ ../Core/Inc/can_halal.h ../Core/Inc/current_monitoring.h \ - ../Core/Inc/channel_control.h + ../Core/Inc/channel_control.h ../Core/Inc/plausibility_check.h \ + ../Core/Inc/can_communication.h ../Core/Inc/main.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: ../Core/Inc/stm32f3xx_hal_conf.h: @@ -74,3 +75,5 @@ Core/Src/main.o: ../Core/Src/main.c ../Core/Inc/main.h \ ../Core/Inc/can_halal.h: ../Core/Inc/current_monitoring.h: ../Core/Inc/channel_control.h: +../Core/Inc/plausibility_check.h: +../Core/Inc/can_communication.h: diff --git a/Software/Code/Debug/Core/Src/main.o b/Software/Code/Debug/Core/Src/main.o index 3160faf..a6eebc2 100644 Binary files a/Software/Code/Debug/Core/Src/main.o and b/Software/Code/Debug/Core/Src/main.o differ diff --git a/Software/Code/Debug/Core/Src/main.su b/Software/Code/Debug/Core/Src/main.su index 5a9135b..f3ea4f6 100644 --- a/Software/Code/Debug/Core/Src/main.su +++ b/Software/Code/Debug/Core/Src/main.su @@ -1,10 +1,10 @@ ../Core/Src/main.c:90:5:main 16 static -../Core/Src/main.c:193:6:SystemClock_Config 120 static -../Core/Src/main.c:241:13:MX_ADC1_Init 48 static -../Core/Src/main.c:370:13:MX_ADC2_Init 32 static -../Core/Src/main.c:472:13:MX_CAN_Init 8 static -../Core/Src/main.c:509:13:MX_TIM6_Init 24 static -../Core/Src/main.c:547:13:MX_UART4_Init 8 static -../Core/Src/main.c:580:13:MX_DMA_Init 16 static -../Core/Src/main.c:602:13:MX_GPIO_Init 48 static -../Core/Src/main.c:665:6:Error_Handler 4 static,ignoring_inline_asm +../Core/Src/main.c:194:6:SystemClock_Config 120 static +../Core/Src/main.c:242:13:MX_ADC1_Init 48 static +../Core/Src/main.c:371:13:MX_ADC2_Init 32 static +../Core/Src/main.c:473:13:MX_CAN_Init 8 static +../Core/Src/main.c:510:13:MX_TIM6_Init 24 static +../Core/Src/main.c:548:13:MX_UART4_Init 8 static +../Core/Src/main.c:581:13:MX_DMA_Init 16 static +../Core/Src/main.c:603:13:MX_GPIO_Init 48 static +../Core/Src/main.c:666:6:Error_Handler 4 static,ignoring_inline_asm diff --git a/Software/Code/Debug/Core/Src/plausibility_check.cyclo b/Software/Code/Debug/Core/Src/plausibility_check.cyclo index bf4db99..45e45c1 100644 --- a/Software/Code/Debug/Core/Src/plausibility_check.cyclo +++ b/Software/Code/Debug/Core/Src/plausibility_check.cyclo @@ -1 +1 @@ -../Core/Src/plausibility_check.c:13:6:check_plausibility 28 +../Core/Src/plausibility_check.c:14:6:check_plausibility 29 diff --git a/Software/Code/Debug/Core/Src/plausibility_check.o b/Software/Code/Debug/Core/Src/plausibility_check.o index 7a2b364..72b9fff 100644 Binary files a/Software/Code/Debug/Core/Src/plausibility_check.o and b/Software/Code/Debug/Core/Src/plausibility_check.o differ diff --git a/Software/Code/Debug/Core/Src/plausibility_check.su b/Software/Code/Debug/Core/Src/plausibility_check.su index 6252965..8cf63cb 100644 --- a/Software/Code/Debug/Core/Src/plausibility_check.su +++ b/Software/Code/Debug/Core/Src/plausibility_check.su @@ -1 +1 @@ -../Core/Src/plausibility_check.c:13:6:check_plausibility 4 static +../Core/Src/plausibility_check.c:14:6:check_plausibility 4 static diff --git a/Software/Code/Debug/PDU_FT25.elf b/Software/Code/Debug/PDU_FT25.elf index 40d33a7..a5bf6c2 100644 Binary files a/Software/Code/Debug/PDU_FT25.elf and b/Software/Code/Debug/PDU_FT25.elf differ diff --git a/Software/Code/Debug/PDU_FT25.list b/Software/Code/Debug/PDU_FT25.list index 40d0530..354c02a 100644 --- a/Software/Code/Debug/PDU_FT25.list +++ b/Software/Code/Debug/PDU_FT25.list @@ -5,47 +5,47 @@ Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 00000188 08000000 08000000 00001000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA - 1 .text 00007028 08000188 08000188 00001188 2**3 + 1 .text 000070c4 08000188 08000188 00001188 2**3 CONTENTS, ALLOC, LOAD, READONLY, CODE - 2 .rodata 00000038 080071b0 080071b0 000081b0 2**2 + 2 .rodata 00000038 0800724c 0800724c 0000824c 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA - 3 .ARM.extab 00000000 080071e8 080071e8 0000900c 2**0 + 3 .ARM.extab 00000000 08007284 08007284 0000900c 2**0 CONTENTS - 4 .ARM 00000000 080071e8 080071e8 0000900c 2**0 + 4 .ARM 00000000 08007284 08007284 0000900c 2**0 CONTENTS - 5 .preinit_array 00000000 080071e8 080071e8 0000900c 2**0 + 5 .preinit_array 00000000 08007284 08007284 0000900c 2**0 CONTENTS, ALLOC, LOAD, DATA - 6 .init_array 00000004 080071e8 080071e8 000081e8 2**2 + 6 .init_array 00000004 08007284 08007284 00008284 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA - 7 .fini_array 00000004 080071ec 080071ec 000081ec 2**2 + 7 .fini_array 00000004 08007288 08007288 00008288 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA - 8 .data 0000000c 20000000 080071f0 00009000 2**2 + 8 .data 0000000c 20000000 0800728c 00009000 2**2 CONTENTS, ALLOC, LOAD, DATA - 9 .bss 00000300 2000000c 080071fc 0000900c 2**2 + 9 .bss 000002f4 2000000c 08007298 0000900c 2**2 ALLOC - 10 ._user_heap_stack 00000604 2000030c 080071fc 0000930c 2**0 + 10 ._user_heap_stack 00000600 20000300 08007298 00009300 2**0 ALLOC 11 .ARM.attributes 00000030 00000000 00000000 0000900c 2**0 CONTENTS, READONLY - 12 .debug_info 00015769 00000000 00000000 0000903c 2**0 + 12 .debug_info 00015a5c 00000000 00000000 0000903c 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS - 13 .debug_abbrev 00002f63 00000000 00000000 0001e7a5 2**0 + 13 .debug_abbrev 00002f4b 00000000 00000000 0001ea98 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS - 14 .debug_aranges 00001148 00000000 00000000 00021708 2**3 + 14 .debug_aranges 00001148 00000000 00000000 000219e8 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS - 15 .debug_rnglists 00000d75 00000000 00000000 00022850 2**0 + 15 .debug_rnglists 00000d74 00000000 00000000 00022b30 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS - 16 .debug_macro 0001ea20 00000000 00000000 000235c5 2**0 + 16 .debug_macro 0001ea2e 00000000 00000000 000238a4 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS - 17 .debug_line 000170ef 00000000 00000000 00041fe5 2**0 + 17 .debug_line 000170a9 00000000 00000000 000422d2 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS - 18 .debug_str 000b7d41 00000000 00000000 000590d4 2**0 + 18 .debug_str 000b7e00 00000000 00000000 0005937b 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS - 19 .comment 00000043 00000000 00000000 00110e15 2**0 + 19 .comment 00000043 00000000 00000000 0011117b 2**0 CONTENTS, READONLY - 20 .debug_frame 00004948 00000000 00000000 00110e58 2**2 + 20 .debug_frame 0000494c 00000000 00000000 001111c0 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS - 21 .debug_line_str 00000071 00000000 00000000 001157a0 2**0 + 21 .debug_line_str 00000071 00000000 00000000 00115b0c 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: @@ -64,7 +64,7 @@ Disassembly of section .text: 800019e: bd10 pop {r4, pc} 80001a0: 2000000c .word 0x2000000c 80001a4: 00000000 .word 0x00000000 - 80001a8: 08007198 .word 0x08007198 + 80001a8: 08007234 .word 0x08007234 080001ac : 80001ac: b508 push {r3, lr} @@ -76,7 +76,7 @@ Disassembly of section .text: 80001ba: bd08 pop {r3, pc} 80001bc: 00000000 .word 0x00000000 80001c0: 20000010 .word 0x20000010 - 80001c4: 08007198 .word 0x08007198 + 80001c4: 08007234 .word 0x08007234 080001c8 <__aeabi_dmul>: 80001c8: b570 push {r4, r5, r6, lr} @@ -598,11 +598,11 @@ void can_init(CAN_HandleTypeDef* hcan){ 80007da: 6078 str r0, [r7, #4] ftcan_init(hcan); 80007dc: 6878 ldr r0, [r7, #4] - 80007de: f000 f93d bl 8000a5c + 80007de: f000 f953 bl 8000a88 ftcan_add_filter(0x00, 0x00); // no filter 80007e2: 2100 movs r1, #0 80007e4: 2000 movs r0, #0 - 80007e6: f000 f97d bl 8000ae4 + 80007e6: f000 f993 bl 8000b10 } 80007ea: bf00 nop 80007ec: 3708 adds r7, #8 @@ -641,7 +641,7 @@ void can_sendloop(){ 800081a: 2203 movs r2, #3 800081c: 4619 mov r1, r3 800081e: 20c9 movs r0, #201 @ 0xc9 - 8000820: f000 f93c bl 8000a9c + 8000820: f000 f952 bl 8000ac8 uint8_t data[8]; @@ -710,7 +710,7 @@ void can_sendloop(){ 8000896: 2208 movs r2, #8 8000898: 4619 mov r1, r3 800089a: 20ca movs r0, #202 @ 0xca - 800089c: f000 f8fe bl 8000a9c + 800089c: f000 f914 bl 8000ac8 break; 80008a0: e08d b.n 80009be @@ -768,7 +768,7 @@ void can_sendloop(){ 80008f4: 2208 movs r2, #8 80008f6: 4619 mov r1, r3 80008f8: 20cb movs r0, #203 @ 0xcb - 80008fa: f000 f8cf bl 8000a9c + 80008fa: f000 f8e5 bl 8000ac8 break; 80008fe: e05e b.n 80009be @@ -826,7 +826,7 @@ void can_sendloop(){ 8000952: 2208 movs r2, #8 8000954: 4619 mov r1, r3 8000956: 20cc movs r0, #204 @ 0xcc - 8000958: f000 f8a0 bl 8000a9c + 8000958: f000 f8b6 bl 8000ac8 break; 800095c: e02f b.n 80009be @@ -884,7 +884,7 @@ void can_sendloop(){ 80009b0: 2208 movs r2, #8 80009b2: 4619 mov r1, r3 80009b4: 20cd movs r0, #205 @ 0xcd - 80009b6: f000 f871 bl 8000a9c + 80009b6: f000 f887 bl 8000ac8 break; 80009ba: e000 b.n 80009be @@ -915,17179 +915,17232 @@ void can_sendloop(){ 80009e8: 2000002d .word 0x2000002d 80009ec: 20000098 .word 0x20000098 -080009f0 : - break; - } - error_loop = (error_loop + 1) % 2; +080009f0 : + +void can_error_report(){ + 80009f0: b580 push {r7, lr} + 80009f2: b082 sub sp, #8 + 80009f4: af00 add r7, sp, #0 + uint8_t error_data[2]; + error_data[0] = error.group1.group1; + 80009f6: 4b08 ldr r3, [pc, #32] @ (8000a18 ) + 80009f8: 781b ldrb r3, [r3, #0] + 80009fa: 713b strb r3, [r7, #4] + error_data[1] = error.group2.group2; + 80009fc: 4b06 ldr r3, [pc, #24] @ (8000a18 ) + 80009fe: 785b ldrb r3, [r3, #1] + 8000a00: 717b strb r3, [r7, #5] + ftcan_transmit(ERROR_ID, error_data, 2); + 8000a02: 1d3b adds r3, r7, #4 + 8000a04: 2202 movs r2, #2 + 8000a06: 4619 mov r1, r3 + 8000a08: 20ce movs r0, #206 @ 0xce + 8000a0a: f000 f85d bl 8000ac8 } + 8000a0e: bf00 nop + 8000a10: 3708 adds r7, #8 + 8000a12: 46bd mov sp, r7 + 8000a14: bd80 pop {r7, pc} + 8000a16: bf00 nop + 8000a18: 200002f4 .word 0x200002f4 + +08000a1c : void ftcan_msg_received_cb(uint16_t id, size_t datalen, const uint8_t* data){ - 80009f0: b580 push {r7, lr} - 80009f2: b084 sub sp, #16 - 80009f4: af00 add r7, sp, #0 - 80009f6: 4603 mov r3, r0 - 80009f8: 60b9 str r1, [r7, #8] - 80009fa: 607a str r2, [r7, #4] - 80009fc: 81fb strh r3, [r7, #14] + 8000a1c: b580 push {r7, lr} + 8000a1e: b084 sub sp, #16 + 8000a20: af00 add r7, sp, #0 + 8000a22: 4603 mov r3, r0 + 8000a24: 60b9 str r1, [r7, #8] + 8000a26: 607a str r2, [r7, #4] + 8000a28: 81fb strh r3, [r7, #14] canmsg_received = 1; - 80009fe: 4b13 ldr r3, [pc, #76] @ (8000a4c ) - 8000a00: 2201 movs r2, #1 - 8000a02: 701a strb r2, [r3, #0] + 8000a2a: 4b13 ldr r3, [pc, #76] @ (8000a78 ) + 8000a2c: 2201 movs r2, #1 + 8000a2e: 701a strb r2, [r3, #0] if((id == RX_STATUS_MSG_ID) && (datalen == 3)){ - 8000a04: 89fb ldrh r3, [r7, #14] - 8000a06: 2bc8 cmp r3, #200 @ 0xc8 - 8000a08: d110 bne.n 8000a2c - 8000a0a: 68bb ldr r3, [r7, #8] - 8000a0c: 2b03 cmp r3, #3 - 8000a0e: d10d bne.n 8000a2c + 8000a30: 89fb ldrh r3, [r7, #14] + 8000a32: 2bc8 cmp r3, #200 @ 0xc8 + 8000a34: d110 bne.n 8000a58 + 8000a36: 68bb ldr r3, [r7, #8] + 8000a38: 2b03 cmp r3, #3 + 8000a3a: d10d bne.n 8000a58 rxstate.iostatus.porta.porta = data[0]; - 8000a10: 687b ldr r3, [r7, #4] - 8000a12: 781a ldrb r2, [r3, #0] - 8000a14: 4b0e ldr r3, [pc, #56] @ (8000a50 ) - 8000a16: 701a strb r2, [r3, #0] + 8000a3c: 687b ldr r3, [r7, #4] + 8000a3e: 781a ldrb r2, [r3, #0] + 8000a40: 4b0e ldr r3, [pc, #56] @ (8000a7c ) + 8000a42: 701a strb r2, [r3, #0] rxstate.iostatus.portb.portb = data[1]; - 8000a18: 687b ldr r3, [r7, #4] - 8000a1a: 3301 adds r3, #1 - 8000a1c: 781a ldrb r2, [r3, #0] - 8000a1e: 4b0c ldr r3, [pc, #48] @ (8000a50 ) - 8000a20: 705a strb r2, [r3, #1] + 8000a44: 687b ldr r3, [r7, #4] + 8000a46: 3301 adds r3, #1 + 8000a48: 781a ldrb r2, [r3, #0] + 8000a4a: 4b0c ldr r3, [pc, #48] @ (8000a7c ) + 8000a4c: 705a strb r2, [r3, #1] rxstate.checksum = data[2]; - 8000a22: 687b ldr r3, [r7, #4] - 8000a24: 3302 adds r3, #2 - 8000a26: 781a ldrb r2, [r3, #0] - 8000a28: 4b09 ldr r3, [pc, #36] @ (8000a50 ) - 8000a2a: 709a strb r2, [r3, #2] + 8000a4e: 687b ldr r3, [r7, #4] + 8000a50: 3302 adds r3, #2 + 8000a52: 781a ldrb r2, [r3, #0] + 8000a54: 4b09 ldr r3, [pc, #36] @ (8000a7c ) + 8000a56: 709a strb r2, [r3, #2] } if (id == RX_STATUS_HEARTBEAT){ - 8000a2c: 89fb ldrh r3, [r7, #14] - 8000a2e: 2bc7 cmp r3, #199 @ 0xc7 - 8000a30: d107 bne.n 8000a42 + 8000a58: 89fb ldrh r3, [r7, #14] + 8000a5a: 2bc7 cmp r3, #199 @ 0xc7 + 8000a5c: d107 bne.n 8000a6e lastheartbeat = HAL_GetTick(); - 8000a32: f001 fc19 bl 8002268 - 8000a36: 4603 mov r3, r0 - 8000a38: 4a06 ldr r2, [pc, #24] @ (8000a54 ) - 8000a3a: 6013 str r3, [r2, #0] + 8000a5e: f001 fc51 bl 8002304 + 8000a62: 4603 mov r3, r0 + 8000a64: 4a06 ldr r2, [pc, #24] @ (8000a80 ) + 8000a66: 6013 str r3, [r2, #0] inhibit_SDC = 0; - 8000a3c: 4b06 ldr r3, [pc, #24] @ (8000a58 ) - 8000a3e: 2200 movs r2, #0 - 8000a40: 601a str r2, [r3, #0] + 8000a68: 4b06 ldr r3, [pc, #24] @ (8000a84 ) + 8000a6a: 2200 movs r2, #0 + 8000a6c: 601a str r2, [r3, #0] } } - 8000a42: bf00 nop - 8000a44: 3710 adds r7, #16 - 8000a46: 46bd mov sp, r7 - 8000a48: bd80 pop {r7, pc} - 8000a4a: bf00 nop - 8000a4c: 2000002c .word 0x2000002c - 8000a50: 20000028 .word 0x20000028 - 8000a54: 200002ec .word 0x200002ec - 8000a58: 200002f0 .word 0x200002f0 + 8000a6e: bf00 nop + 8000a70: 3710 adds r7, #16 + 8000a72: 46bd mov sp, r7 + 8000a74: bd80 pop {r7, pc} + 8000a76: bf00 nop + 8000a78: 2000002c .word 0x2000002c + 8000a7c: 20000028 .word 0x20000028 + 8000a80: 200002ec .word 0x200002ec + 8000a84: 200002f0 .word 0x200002f0 -08000a5c : +08000a88 : #include #if defined(FTCAN_IS_BXCAN) static CAN_HandleTypeDef *hcan; HAL_StatusTypeDef ftcan_init(CAN_HandleTypeDef *handle) { - 8000a5c: b580 push {r7, lr} - 8000a5e: b084 sub sp, #16 - 8000a60: af00 add r7, sp, #0 - 8000a62: 6078 str r0, [r7, #4] + 8000a88: b580 push {r7, lr} + 8000a8a: b084 sub sp, #16 + 8000a8c: af00 add r7, sp, #0 + 8000a8e: 6078 str r0, [r7, #4] hcan = handle; - 8000a64: 4a0c ldr r2, [pc, #48] @ (8000a98 ) - 8000a66: 687b ldr r3, [r7, #4] - 8000a68: 6013 str r3, [r2, #0] + 8000a90: 4a0c ldr r2, [pc, #48] @ (8000ac4 ) + 8000a92: 687b ldr r3, [r7, #4] + 8000a94: 6013 str r3, [r2, #0] HAL_StatusTypeDef status = HAL_CAN_ActivateNotification(hcan, CAN_IT_RX_FIFO0_MSG_PENDING); - 8000a6a: 4b0b ldr r3, [pc, #44] @ (8000a98 ) - 8000a6c: 681b ldr r3, [r3, #0] - 8000a6e: 2102 movs r1, #2 - 8000a70: 4618 mov r0, r3 - 8000a72: f003 f984 bl 8003d7e - 8000a76: 4603 mov r3, r0 - 8000a78: 73fb strb r3, [r7, #15] + 8000a96: 4b0b ldr r3, [pc, #44] @ (8000ac4 ) + 8000a98: 681b ldr r3, [r3, #0] + 8000a9a: 2102 movs r1, #2 + 8000a9c: 4618 mov r0, r3 + 8000a9e: f003 f9bc bl 8003e1a + 8000aa2: 4603 mov r3, r0 + 8000aa4: 73fb strb r3, [r7, #15] if (status != HAL_OK) { - 8000a7a: 7bfb ldrb r3, [r7, #15] - 8000a7c: 2b00 cmp r3, #0 - 8000a7e: d001 beq.n 8000a84 + 8000aa6: 7bfb ldrb r3, [r7, #15] + 8000aa8: 2b00 cmp r3, #0 + 8000aaa: d001 beq.n 8000ab0 return status; - 8000a80: 7bfb ldrb r3, [r7, #15] - 8000a82: e005 b.n 8000a90 + 8000aac: 7bfb ldrb r3, [r7, #15] + 8000aae: e005 b.n 8000abc } return HAL_CAN_Start(hcan); - 8000a84: 4b04 ldr r3, [pc, #16] @ (8000a98 ) - 8000a86: 681b ldr r3, [r3, #0] - 8000a88: 4618 mov r0, r3 - 8000a8a: f002 ff42 bl 8003912 - 8000a8e: 4603 mov r3, r0 + 8000ab0: 4b04 ldr r3, [pc, #16] @ (8000ac4 ) + 8000ab2: 681b ldr r3, [r3, #0] + 8000ab4: 4618 mov r0, r3 + 8000ab6: f002 ff7a bl 80039ae + 8000aba: 4603 mov r3, r0 } - 8000a90: 4618 mov r0, r3 - 8000a92: 3710 adds r7, #16 - 8000a94: 46bd mov sp, r7 - 8000a96: bd80 pop {r7, pc} - 8000a98: 20000030 .word 0x20000030 + 8000abc: 4618 mov r0, r3 + 8000abe: 3710 adds r7, #16 + 8000ac0: 46bd mov sp, r7 + 8000ac2: bd80 pop {r7, pc} + 8000ac4: 20000030 .word 0x20000030 -08000a9c : +08000ac8 : HAL_StatusTypeDef ftcan_transmit(uint16_t id, const uint8_t *data, size_t datalen) { - 8000a9c: b580 push {r7, lr} - 8000a9e: b086 sub sp, #24 - 8000aa0: af00 add r7, sp, #0 - 8000aa2: 4603 mov r3, r0 - 8000aa4: 60b9 str r1, [r7, #8] - 8000aa6: 607a str r2, [r7, #4] - 8000aa8: 81fb strh r3, [r7, #14] + 8000ac8: b580 push {r7, lr} + 8000aca: b086 sub sp, #24 + 8000acc: af00 add r7, sp, #0 + 8000ace: 4603 mov r3, r0 + 8000ad0: 60b9 str r1, [r7, #8] + 8000ad2: 607a str r2, [r7, #4] + 8000ad4: 81fb strh r3, [r7, #14] static CAN_TxHeaderTypeDef header; header.StdId = id; - 8000aaa: 89fb ldrh r3, [r7, #14] - 8000aac: 4a0b ldr r2, [pc, #44] @ (8000adc ) - 8000aae: 6013 str r3, [r2, #0] + 8000ad6: 89fb ldrh r3, [r7, #14] + 8000ad8: 4a0b ldr r2, [pc, #44] @ (8000b08 ) + 8000ada: 6013 str r3, [r2, #0] header.IDE = CAN_ID_STD; - 8000ab0: 4b0a ldr r3, [pc, #40] @ (8000adc ) - 8000ab2: 2200 movs r2, #0 - 8000ab4: 609a str r2, [r3, #8] + 8000adc: 4b0a ldr r3, [pc, #40] @ (8000b08 ) + 8000ade: 2200 movs r2, #0 + 8000ae0: 609a str r2, [r3, #8] header.RTR = CAN_RTR_DATA; - 8000ab6: 4b09 ldr r3, [pc, #36] @ (8000adc ) - 8000ab8: 2200 movs r2, #0 - 8000aba: 60da str r2, [r3, #12] + 8000ae2: 4b09 ldr r3, [pc, #36] @ (8000b08 ) + 8000ae4: 2200 movs r2, #0 + 8000ae6: 60da str r2, [r3, #12] header.DLC = datalen; - 8000abc: 4a07 ldr r2, [pc, #28] @ (8000adc ) - 8000abe: 687b ldr r3, [r7, #4] - 8000ac0: 6113 str r3, [r2, #16] + 8000ae8: 4a07 ldr r2, [pc, #28] @ (8000b08 ) + 8000aea: 687b ldr r3, [r7, #4] + 8000aec: 6113 str r3, [r2, #16] uint32_t mailbox; return HAL_CAN_AddTxMessage(hcan, &header, data, &mailbox); - 8000ac2: 4b07 ldr r3, [pc, #28] @ (8000ae0 ) - 8000ac4: 6818 ldr r0, [r3, #0] - 8000ac6: f107 0314 add.w r3, r7, #20 - 8000aca: 68ba ldr r2, [r7, #8] - 8000acc: 4903 ldr r1, [pc, #12] @ (8000adc ) - 8000ace: f002 ff64 bl 800399a - 8000ad2: 4603 mov r3, r0 + 8000aee: 4b07 ldr r3, [pc, #28] @ (8000b0c ) + 8000af0: 6818 ldr r0, [r3, #0] + 8000af2: f107 0314 add.w r3, r7, #20 + 8000af6: 68ba ldr r2, [r7, #8] + 8000af8: 4903 ldr r1, [pc, #12] @ (8000b08 ) + 8000afa: f002 ff9c bl 8003a36 + 8000afe: 4603 mov r3, r0 } - 8000ad4: 4618 mov r0, r3 - 8000ad6: 3718 adds r7, #24 - 8000ad8: 46bd mov sp, r7 - 8000ada: bd80 pop {r7, pc} - 8000adc: 20000034 .word 0x20000034 - 8000ae0: 20000030 .word 0x20000030 + 8000b00: 4618 mov r0, r3 + 8000b02: 3718 adds r7, #24 + 8000b04: 46bd mov sp, r7 + 8000b06: bd80 pop {r7, pc} + 8000b08: 20000034 .word 0x20000034 + 8000b0c: 20000030 .word 0x20000030 -08000ae4 : +08000b10 : HAL_StatusTypeDef ftcan_add_filter(uint16_t id, uint16_t mask) { - 8000ae4: b580 push {r7, lr} - 8000ae6: b084 sub sp, #16 - 8000ae8: af00 add r7, sp, #0 - 8000aea: 4603 mov r3, r0 - 8000aec: 460a mov r2, r1 - 8000aee: 80fb strh r3, [r7, #6] - 8000af0: 4613 mov r3, r2 - 8000af2: 80bb strh r3, [r7, #4] + 8000b10: b580 push {r7, lr} + 8000b12: b084 sub sp, #16 + 8000b14: af00 add r7, sp, #0 + 8000b16: 4603 mov r3, r0 + 8000b18: 460a mov r2, r1 + 8000b1a: 80fb strh r3, [r7, #6] + 8000b1c: 4613 mov r3, r2 + 8000b1e: 80bb strh r3, [r7, #4] static uint32_t next_filter_no = 0; static CAN_FilterTypeDef filter; if (next_filter_no % 2 == 0) { - 8000af4: 4b26 ldr r3, [pc, #152] @ (8000b90 ) - 8000af6: 681b ldr r3, [r3, #0] - 8000af8: f003 0301 and.w r3, r3, #1 - 8000afc: 2b00 cmp r3, #0 - 8000afe: d110 bne.n 8000b22 + 8000b20: 4b26 ldr r3, [pc, #152] @ (8000bbc ) + 8000b22: 681b ldr r3, [r3, #0] + 8000b24: f003 0301 and.w r3, r3, #1 + 8000b28: 2b00 cmp r3, #0 + 8000b2a: d110 bne.n 8000b4e filter.FilterIdHigh = id << 5; - 8000b00: 88fb ldrh r3, [r7, #6] - 8000b02: 015b lsls r3, r3, #5 - 8000b04: 4a23 ldr r2, [pc, #140] @ (8000b94 ) - 8000b06: 6013 str r3, [r2, #0] + 8000b2c: 88fb ldrh r3, [r7, #6] + 8000b2e: 015b lsls r3, r3, #5 + 8000b30: 4a23 ldr r2, [pc, #140] @ (8000bc0 ) + 8000b32: 6013 str r3, [r2, #0] filter.FilterMaskIdHigh = mask << 5; - 8000b08: 88bb ldrh r3, [r7, #4] - 8000b0a: 015b lsls r3, r3, #5 - 8000b0c: 4a21 ldr r2, [pc, #132] @ (8000b94 ) - 8000b0e: 6093 str r3, [r2, #8] + 8000b34: 88bb ldrh r3, [r7, #4] + 8000b36: 015b lsls r3, r3, #5 + 8000b38: 4a21 ldr r2, [pc, #132] @ (8000bc0 ) + 8000b3a: 6093 str r3, [r2, #8] filter.FilterIdLow = id << 5; - 8000b10: 88fb ldrh r3, [r7, #6] - 8000b12: 015b lsls r3, r3, #5 - 8000b14: 4a1f ldr r2, [pc, #124] @ (8000b94 ) - 8000b16: 6053 str r3, [r2, #4] + 8000b3c: 88fb ldrh r3, [r7, #6] + 8000b3e: 015b lsls r3, r3, #5 + 8000b40: 4a1f ldr r2, [pc, #124] @ (8000bc0 ) + 8000b42: 6053 str r3, [r2, #4] filter.FilterMaskIdLow = mask << 5; - 8000b18: 88bb ldrh r3, [r7, #4] - 8000b1a: 015b lsls r3, r3, #5 - 8000b1c: 4a1d ldr r2, [pc, #116] @ (8000b94 ) - 8000b1e: 60d3 str r3, [r2, #12] - 8000b20: e007 b.n 8000b32 + 8000b44: 88bb ldrh r3, [r7, #4] + 8000b46: 015b lsls r3, r3, #5 + 8000b48: 4a1d ldr r2, [pc, #116] @ (8000bc0 ) + 8000b4a: 60d3 str r3, [r2, #12] + 8000b4c: e007 b.n 8000b5e } else { // Leave high filter untouched from the last configuration filter.FilterIdLow = id << 5; - 8000b22: 88fb ldrh r3, [r7, #6] - 8000b24: 015b lsls r3, r3, #5 - 8000b26: 4a1b ldr r2, [pc, #108] @ (8000b94 ) - 8000b28: 6053 str r3, [r2, #4] + 8000b4e: 88fb ldrh r3, [r7, #6] + 8000b50: 015b lsls r3, r3, #5 + 8000b52: 4a1b ldr r2, [pc, #108] @ (8000bc0 ) + 8000b54: 6053 str r3, [r2, #4] filter.FilterMaskIdLow = mask << 5; - 8000b2a: 88bb ldrh r3, [r7, #4] - 8000b2c: 015b lsls r3, r3, #5 - 8000b2e: 4a19 ldr r2, [pc, #100] @ (8000b94 ) - 8000b30: 60d3 str r3, [r2, #12] + 8000b56: 88bb ldrh r3, [r7, #4] + 8000b58: 015b lsls r3, r3, #5 + 8000b5a: 4a19 ldr r2, [pc, #100] @ (8000bc0 ) + 8000b5c: 60d3 str r3, [r2, #12] } filter.FilterFIFOAssignment = CAN_FILTER_FIFO0; - 8000b32: 4b18 ldr r3, [pc, #96] @ (8000b94 ) - 8000b34: 2200 movs r2, #0 - 8000b36: 611a str r2, [r3, #16] + 8000b5e: 4b18 ldr r3, [pc, #96] @ (8000bc0 ) + 8000b60: 2200 movs r2, #0 + 8000b62: 611a str r2, [r3, #16] filter.FilterBank = next_filter_no / 2; - 8000b38: 4b15 ldr r3, [pc, #84] @ (8000b90 ) - 8000b3a: 681b ldr r3, [r3, #0] - 8000b3c: 085b lsrs r3, r3, #1 - 8000b3e: 4a15 ldr r2, [pc, #84] @ (8000b94 ) - 8000b40: 6153 str r3, [r2, #20] + 8000b64: 4b15 ldr r3, [pc, #84] @ (8000bbc ) + 8000b66: 681b ldr r3, [r3, #0] + 8000b68: 085b lsrs r3, r3, #1 + 8000b6a: 4a15 ldr r2, [pc, #84] @ (8000bc0 ) + 8000b6c: 6153 str r3, [r2, #20] if (filter.FilterBank > FTCAN_NUM_FILTERS + 1) { - 8000b42: 4b14 ldr r3, [pc, #80] @ (8000b94 ) - 8000b44: 695b ldr r3, [r3, #20] - 8000b46: 2b0e cmp r3, #14 - 8000b48: d901 bls.n 8000b4e + 8000b6e: 4b14 ldr r3, [pc, #80] @ (8000bc0 ) + 8000b70: 695b ldr r3, [r3, #20] + 8000b72: 2b0e cmp r3, #14 + 8000b74: d901 bls.n 8000b7a return HAL_ERROR; - 8000b4a: 2301 movs r3, #1 - 8000b4c: e01c b.n 8000b88 + 8000b76: 2301 movs r3, #1 + 8000b78: e01c b.n 8000bb4 } filter.FilterMode = CAN_FILTERMODE_IDMASK; - 8000b4e: 4b11 ldr r3, [pc, #68] @ (8000b94 ) - 8000b50: 2200 movs r2, #0 - 8000b52: 619a str r2, [r3, #24] + 8000b7a: 4b11 ldr r3, [pc, #68] @ (8000bc0 ) + 8000b7c: 2200 movs r2, #0 + 8000b7e: 619a str r2, [r3, #24] filter.FilterScale = CAN_FILTERSCALE_16BIT; - 8000b54: 4b0f ldr r3, [pc, #60] @ (8000b94 ) - 8000b56: 2200 movs r2, #0 - 8000b58: 61da str r2, [r3, #28] + 8000b80: 4b0f ldr r3, [pc, #60] @ (8000bc0 ) + 8000b82: 2200 movs r2, #0 + 8000b84: 61da str r2, [r3, #28] filter.FilterActivation = CAN_FILTER_ENABLE; - 8000b5a: 4b0e ldr r3, [pc, #56] @ (8000b94 ) - 8000b5c: 2201 movs r2, #1 - 8000b5e: 621a str r2, [r3, #32] + 8000b86: 4b0e ldr r3, [pc, #56] @ (8000bc0 ) + 8000b88: 2201 movs r2, #1 + 8000b8a: 621a str r2, [r3, #32] // Disable slave filters // TODO: Some STM32 have multiple CAN peripherals, and one uses the slave // filter bank filter.SlaveStartFilterBank = FTCAN_NUM_FILTERS; - 8000b60: 4b0c ldr r3, [pc, #48] @ (8000b94 ) - 8000b62: 220d movs r2, #13 - 8000b64: 625a str r2, [r3, #36] @ 0x24 + 8000b8c: 4b0c ldr r3, [pc, #48] @ (8000bc0 ) + 8000b8e: 220d movs r2, #13 + 8000b90: 625a str r2, [r3, #36] @ 0x24 HAL_StatusTypeDef status = HAL_CAN_ConfigFilter(hcan, &filter); - 8000b66: 4b0c ldr r3, [pc, #48] @ (8000b98 ) - 8000b68: 681b ldr r3, [r3, #0] - 8000b6a: 490a ldr r1, [pc, #40] @ (8000b94 ) - 8000b6c: 4618 mov r0, r3 - 8000b6e: f002 fe06 bl 800377e - 8000b72: 4603 mov r3, r0 - 8000b74: 73fb strb r3, [r7, #15] + 8000b92: 4b0c ldr r3, [pc, #48] @ (8000bc4 ) + 8000b94: 681b ldr r3, [r3, #0] + 8000b96: 490a ldr r1, [pc, #40] @ (8000bc0 ) + 8000b98: 4618 mov r0, r3 + 8000b9a: f002 fe3e bl 800381a + 8000b9e: 4603 mov r3, r0 + 8000ba0: 73fb strb r3, [r7, #15] if (status == HAL_OK) { - 8000b76: 7bfb ldrb r3, [r7, #15] - 8000b78: 2b00 cmp r3, #0 - 8000b7a: d104 bne.n 8000b86 + 8000ba2: 7bfb ldrb r3, [r7, #15] + 8000ba4: 2b00 cmp r3, #0 + 8000ba6: d104 bne.n 8000bb2 next_filter_no++; - 8000b7c: 4b04 ldr r3, [pc, #16] @ (8000b90 ) - 8000b7e: 681b ldr r3, [r3, #0] - 8000b80: 3301 adds r3, #1 - 8000b82: 4a03 ldr r2, [pc, #12] @ (8000b90 ) - 8000b84: 6013 str r3, [r2, #0] + 8000ba8: 4b04 ldr r3, [pc, #16] @ (8000bbc ) + 8000baa: 681b ldr r3, [r3, #0] + 8000bac: 3301 adds r3, #1 + 8000bae: 4a03 ldr r2, [pc, #12] @ (8000bbc ) + 8000bb0: 6013 str r3, [r2, #0] } return status; - 8000b86: 7bfb ldrb r3, [r7, #15] + 8000bb2: 7bfb ldrb r3, [r7, #15] } - 8000b88: 4618 mov r0, r3 - 8000b8a: 3710 adds r7, #16 - 8000b8c: 46bd mov sp, r7 - 8000b8e: bd80 pop {r7, pc} - 8000b90: 2000004c .word 0x2000004c - 8000b94: 20000050 .word 0x20000050 - 8000b98: 20000030 .word 0x20000030 + 8000bb4: 4618 mov r0, r3 + 8000bb6: 3710 adds r7, #16 + 8000bb8: 46bd mov sp, r7 + 8000bba: bd80 pop {r7, pc} + 8000bbc: 2000004c .word 0x2000004c + 8000bc0: 20000050 .word 0x20000050 + 8000bc4: 20000030 .word 0x20000030 -08000b9c : +08000bc8 : void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *handle) { - 8000b9c: b580 push {r7, lr} - 8000b9e: b08c sub sp, #48 @ 0x30 - 8000ba0: af00 add r7, sp, #0 - 8000ba2: 6078 str r0, [r7, #4] + 8000bc8: b580 push {r7, lr} + 8000bca: b08c sub sp, #48 @ 0x30 + 8000bcc: af00 add r7, sp, #0 + 8000bce: 6078 str r0, [r7, #4] if (handle != hcan) { - 8000ba4: 4b12 ldr r3, [pc, #72] @ (8000bf0 ) - 8000ba6: 681b ldr r3, [r3, #0] - 8000ba8: 687a ldr r2, [r7, #4] - 8000baa: 429a cmp r2, r3 - 8000bac: d117 bne.n 8000bde + 8000bd0: 4b12 ldr r3, [pc, #72] @ (8000c1c ) + 8000bd2: 681b ldr r3, [r3, #0] + 8000bd4: 687a ldr r2, [r7, #4] + 8000bd6: 429a cmp r2, r3 + 8000bd8: d117 bne.n 8000c0a return; } CAN_RxHeaderTypeDef header; uint8_t data[8]; if (HAL_CAN_GetRxMessage(hcan, CAN_RX_FIFO0, &header, data) != HAL_OK) { - 8000bae: 4b10 ldr r3, [pc, #64] @ (8000bf0 ) - 8000bb0: 6818 ldr r0, [r3, #0] - 8000bb2: f107 030c add.w r3, r7, #12 - 8000bb6: f107 0214 add.w r2, r7, #20 - 8000bba: 2100 movs r1, #0 - 8000bbc: f002 ffbd bl 8003b3a - 8000bc0: 4603 mov r3, r0 - 8000bc2: 2b00 cmp r3, #0 - 8000bc4: d10d bne.n 8000be2 + 8000bda: 4b10 ldr r3, [pc, #64] @ (8000c1c ) + 8000bdc: 6818 ldr r0, [r3, #0] + 8000bde: f107 030c add.w r3, r7, #12 + 8000be2: f107 0214 add.w r2, r7, #20 + 8000be6: 2100 movs r1, #0 + 8000be8: f002 fff5 bl 8003bd6 + 8000bec: 4603 mov r3, r0 + 8000bee: 2b00 cmp r3, #0 + 8000bf0: d10d bne.n 8000c0e return; } if (header.IDE != CAN_ID_STD) { - 8000bc6: 69fb ldr r3, [r7, #28] - 8000bc8: 2b00 cmp r3, #0 - 8000bca: d10c bne.n 8000be6 + 8000bf2: 69fb ldr r3, [r7, #28] + 8000bf4: 2b00 cmp r3, #0 + 8000bf6: d10c bne.n 8000c12 return; } ftcan_msg_received_cb(header.StdId, header.DLC, data); - 8000bcc: 697b ldr r3, [r7, #20] - 8000bce: b29b uxth r3, r3 - 8000bd0: 6a79 ldr r1, [r7, #36] @ 0x24 - 8000bd2: f107 020c add.w r2, r7, #12 - 8000bd6: 4618 mov r0, r3 - 8000bd8: f7ff ff0a bl 80009f0 - 8000bdc: e004 b.n 8000be8 + 8000bf8: 697b ldr r3, [r7, #20] + 8000bfa: b29b uxth r3, r3 + 8000bfc: 6a79 ldr r1, [r7, #36] @ 0x24 + 8000bfe: f107 020c add.w r2, r7, #12 + 8000c02: 4618 mov r0, r3 + 8000c04: f7ff ff0a bl 8000a1c + 8000c08: e004 b.n 8000c14 return; - 8000bde: bf00 nop - 8000be0: e002 b.n 8000be8 + 8000c0a: bf00 nop + 8000c0c: e002 b.n 8000c14 return; - 8000be2: bf00 nop - 8000be4: e000 b.n 8000be8 + 8000c0e: bf00 nop + 8000c10: e000 b.n 8000c14 return; - 8000be6: bf00 nop + 8000c12: bf00 nop } - 8000be8: 3730 adds r7, #48 @ 0x30 - 8000bea: 46bd mov sp, r7 - 8000bec: bd80 pop {r7, pc} - 8000bee: bf00 nop - 8000bf0: 20000030 .word 0x20000030 + 8000c14: 3730 adds r7, #48 @ 0x30 + 8000c16: 46bd mov sp, r7 + 8000c18: bd80 pop {r7, pc} + 8000c1a: bf00 nop + 8000c1c: 20000030 .word 0x20000030 -08000bf4 : +08000c20 : extern current_measurements current_measurements_adc_val; extern int inhibit_SDC; volatile int prev_epsc_state; void ChannelControl_init(){ - 8000bf4: b580 push {r7, lr} - 8000bf6: af00 add r7, sp, #0 + 8000c20: b580 push {r7, lr} + 8000c22: af00 add r7, sp, #0 update_ports.porta.porta = 0; - 8000bf8: 4b09 ldr r3, [pc, #36] @ (8000c20 ) - 8000bfa: 2200 movs r2, #0 - 8000bfc: 701a strb r2, [r3, #0] + 8000c24: 4b09 ldr r3, [pc, #36] @ (8000c4c ) + 8000c26: 2200 movs r2, #0 + 8000c28: 701a strb r2, [r3, #0] update_ports.portb.portb = 0; - 8000bfe: 4b08 ldr r3, [pc, #32] @ (8000c20 ) - 8000c00: 2200 movs r2, #0 - 8000c02: 705a strb r2, [r3, #1] + 8000c2a: 4b08 ldr r3, [pc, #32] @ (8000c4c ) + 8000c2c: 2200 movs r2, #0 + 8000c2e: 705a strb r2, [r3, #1] update_ports.portb.alwayson = 1; - 8000c04: 4a06 ldr r2, [pc, #24] @ (8000c20 ) - 8000c06: 7853 ldrb r3, [r2, #1] - 8000c08: f043 0301 orr.w r3, r3, #1 - 8000c0c: 7053 strb r3, [r2, #1] + 8000c30: 4a06 ldr r2, [pc, #24] @ (8000c4c ) + 8000c32: 7853 ldrb r3, [r2, #1] + 8000c34: f043 0301 orr.w r3, r3, #1 + 8000c38: 7053 strb r3, [r2, #1] ChannelControl_UpdateGPIOs(update_ports); - 8000c0e: 4b04 ldr r3, [pc, #16] @ (8000c20 ) - 8000c10: 8818 ldrh r0, [r3, #0] - 8000c12: f000 f809 bl 8000c28 + 8000c3a: 4b04 ldr r3, [pc, #16] @ (8000c4c ) + 8000c3c: 8818 ldrh r0, [r3, #0] + 8000c3e: f000 f809 bl 8000c54 prev_epsc_state = 0; - 8000c16: 4b03 ldr r3, [pc, #12] @ (8000c24 ) - 8000c18: 2200 movs r2, #0 - 8000c1a: 601a str r2, [r3, #0] + 8000c42: 4b03 ldr r3, [pc, #12] @ (8000c50 ) + 8000c44: 2200 movs r2, #0 + 8000c46: 601a str r2, [r3, #0] } - 8000c1c: bf00 nop - 8000c1e: bd80 pop {r7, pc} - 8000c20: 200002e8 .word 0x200002e8 - 8000c24: 20000078 .word 0x20000078 + 8000c48: bf00 nop + 8000c4a: bd80 pop {r7, pc} + 8000c4c: 200002e8 .word 0x200002e8 + 8000c50: 20000078 .word 0x20000078 -08000c28 : +08000c54 : void ChannelControl_UpdateGPIOs(enable_gpios UpdatePorts){ - 8000c28: b580 push {r7, lr} - 8000c2a: b082 sub sp, #8 - 8000c2c: af00 add r7, sp, #0 - 8000c2e: 80b8 strh r0, [r7, #4] - UpdatePorts.portb.alwayson = 1; - 8000c30: 797b ldrb r3, [r7, #5] - 8000c32: f043 0301 orr.w r3, r3, #1 - 8000c36: 717b strb r3, [r7, #5] + 8000c54: b580 push {r7, lr} + 8000c56: b082 sub sp, #8 + 8000c58: af00 add r7, sp, #0 + 8000c5a: 80b8 strh r0, [r7, #4] + UpdatePorts.portb.alwayson = 1; // ensure always on stays always on + 8000c5c: 797b ldrb r3, [r7, #5] + 8000c5e: f043 0301 orr.w r3, r3, #1 + 8000c62: 717b strb r3, [r7, #5] if (inhibit_SDC == 1){ - 8000c38: 4b7b ldr r3, [pc, #492] @ (8000e28 ) - 8000c3a: 681b ldr r3, [r3, #0] - 8000c3c: 2b01 cmp r3, #1 - 8000c3e: d109 bne.n 8000c54 + 8000c64: 4b76 ldr r3, [pc, #472] @ (8000e40 ) + 8000c66: 681b ldr r3, [r3, #0] + 8000c68: 2b01 cmp r3, #1 + 8000c6a: d109 bne.n 8000c80 UpdatePorts.portb.sdc = 0; - 8000c40: 797b ldrb r3, [r7, #5] - 8000c42: f36f 0341 bfc r3, #1, #1 - 8000c46: 717b strb r3, [r7, #5] + 8000c6c: 797b ldrb r3, [r7, #5] + 8000c6e: f36f 0341 bfc r3, #1, #1 + 8000c72: 717b strb r3, [r7, #5] HAL_GPIO_WritePin(LED1_GPIO_Port, LED1_Pin, 1); - 8000c48: 2201 movs r2, #1 - 8000c4a: f44f 7100 mov.w r1, #512 @ 0x200 - 8000c4e: 4877 ldr r0, [pc, #476] @ (8000e2c ) - 8000c50: f003 ff28 bl 8004aa4 + 8000c74: 2201 movs r2, #1 + 8000c76: f44f 7100 mov.w r1, #512 @ 0x200 + 8000c7a: 4872 ldr r0, [pc, #456] @ (8000e44 ) + 8000c7c: f003 ff60 bl 8004b40 } HAL_GPIO_WritePin(IN1_GPIO_Port, IN1_Pin, (GPIO_PinState)UpdatePorts.porta.acc_cooling); // Acc-Cooling - 8000c54: 793b ldrb r3, [r7, #4] - 8000c56: f3c3 0300 ubfx r3, r3, #0, #1 - 8000c5a: b2db uxtb r3, r3 - 8000c5c: 461a mov r2, r3 - 8000c5e: f44f 7100 mov.w r1, #512 @ 0x200 - 8000c62: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 - 8000c66: f003 ff1d bl 8004aa4 - HAL_GPIO_WritePin(IN2_GPIO_Port, IN2_Pin, (GPIO_PinState)UpdatePorts.porta.ts_cooling); // TS-Cooling - 8000c6a: 793b ldrb r3, [r7, #4] - 8000c6c: f3c3 0340 ubfx r3, r3, #1, #1 - 8000c70: b2db uxtb r3, r3 - 8000c72: 461a mov r2, r3 - 8000c74: f44f 7180 mov.w r1, #256 @ 0x100 - 8000c78: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 - 8000c7c: f003 ff12 bl 8004aa4 - HAL_GPIO_WritePin(IN3_GPIO_Port, IN3_Pin, (GPIO_PinState)UpdatePorts.porta.drs); // DRS 8000c80: 793b ldrb r3, [r7, #4] - 8000c82: f3c3 0380 ubfx r3, r3, #2, #1 + 8000c82: f3c3 0300 ubfx r3, r3, #0, #1 8000c86: b2db uxtb r3, r3 8000c88: 461a mov r2, r3 - 8000c8a: f44f 5180 mov.w r1, #4096 @ 0x1000 - 8000c8e: 4868 ldr r0, [pc, #416] @ (8000e30 ) - 8000c90: f003 ff08 bl 8004aa4 + 8000c8a: f44f 7100 mov.w r1, #512 @ 0x200 + 8000c8e: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 + 8000c92: f003 ff55 bl 8004b40 + HAL_GPIO_WritePin(IN2_GPIO_Port, IN2_Pin, (GPIO_PinState)UpdatePorts.porta.ts_cooling); // TS-Cooling + 8000c96: 793b ldrb r3, [r7, #4] + 8000c98: f3c3 0340 ubfx r3, r3, #1, #1 + 8000c9c: b2db uxtb r3, r3 + 8000c9e: 461a mov r2, r3 + 8000ca0: f44f 7180 mov.w r1, #256 @ 0x100 + 8000ca4: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 + 8000ca8: f003 ff4a bl 8004b40 + HAL_GPIO_WritePin(IN3_GPIO_Port, IN3_Pin, (GPIO_PinState)UpdatePorts.porta.drs); // DRS + 8000cac: 793b ldrb r3, [r7, #4] + 8000cae: f3c3 0380 ubfx r3, r3, #2, #1 + 8000cb2: b2db uxtb r3, r3 + 8000cb4: 461a mov r2, r3 + 8000cb6: f44f 5180 mov.w r1, #4096 @ 0x1000 + 8000cba: 4863 ldr r0, [pc, #396] @ (8000e48 ) + 8000cbc: f003 ff40 bl 8004b40 HAL_GPIO_WritePin(IN4_GPIO_Port, IN4_Pin, (GPIO_PinState)UpdatePorts.porta.acu); // ACU - 8000c94: 793b ldrb r3, [r7, #4] - 8000c96: f3c3 03c0 ubfx r3, r3, #3, #1 - 8000c9a: b2db uxtb r3, r3 - 8000c9c: 461a mov r2, r3 - 8000c9e: f44f 4100 mov.w r1, #32768 @ 0x8000 - 8000ca2: 4863 ldr r0, [pc, #396] @ (8000e30 ) - 8000ca4: f003 fefe bl 8004aa4 + 8000cc0: 793b ldrb r3, [r7, #4] + 8000cc2: f3c3 03c0 ubfx r3, r3, #3, #1 + 8000cc6: b2db uxtb r3, r3 + 8000cc8: 461a mov r2, r3 + 8000cca: f44f 4100 mov.w r1, #32768 @ 0x8000 + 8000cce: 485e ldr r0, [pc, #376] @ (8000e48 ) + 8000cd0: f003 ff36 bl 8004b40 if (prev_epsc_state == 0 && UpdatePorts.porta.epsc == 1){ - 8000ca8: 4b62 ldr r3, [pc, #392] @ (8000e34 ) - 8000caa: 681b ldr r3, [r3, #0] - 8000cac: 2b00 cmp r3, #0 - 8000cae: d13f bne.n 8000d30 - 8000cb0: 793b ldrb r3, [r7, #4] - 8000cb2: f003 0310 and.w r3, r3, #16 - 8000cb6: b2db uxtb r3, r3 - 8000cb8: 2b00 cmp r3, #0 - 8000cba: d039 beq.n 8000d30 + 8000cd4: 4b5d ldr r3, [pc, #372] @ (8000e4c ) + 8000cd6: 681b ldr r3, [r3, #0] + 8000cd8: 2b00 cmp r3, #0 + 8000cda: d135 bne.n 8000d48 + 8000cdc: 793b ldrb r3, [r7, #4] + 8000cde: f003 0310 and.w r3, r3, #16 + 8000ce2: b2db uxtb r3, r3 + 8000ce4: 2b00 cmp r3, #0 + 8000ce6: d02f beq.n 8000d48 HAL_GPIO_WritePin(PC_EN_GPIO_Port, PC_EN_Pin, 1); // enable precharge - 8000cbc: 2201 movs r2, #1 - 8000cbe: 2140 movs r1, #64 @ 0x40 - 8000cc0: 485b ldr r0, [pc, #364] @ (8000e30 ) - 8000cc2: f003 feef bl 8004aa4 - HAL_GPIO_WritePin(LED3_GPIO_Port, LED3_Pin, 1); - 8000cc6: 2201 movs r2, #1 - 8000cc8: 2180 movs r1, #128 @ 0x80 - 8000cca: 4858 ldr r0, [pc, #352] @ (8000e2c ) - 8000ccc: f003 feea bl 8004aa4 - if (current_measurements_adc_val.epsc_precharge >= (0.95f * current_measurements_adc_val.asms_v)) { // precharge complete - 8000cd0: 4b59 ldr r3, [pc, #356] @ (8000e38 ) - 8000cd2: 8b5b ldrh r3, [r3, #26] - 8000cd4: ee07 3a90 vmov s15, r3 - 8000cd8: eeb8 7ae7 vcvt.f32.s32 s14, s15 - 8000cdc: 4b56 ldr r3, [pc, #344] @ (8000e38 ) - 8000cde: 8bdb ldrh r3, [r3, #30] - 8000ce0: ee07 3a90 vmov s15, r3 - 8000ce4: eef8 7ae7 vcvt.f32.s32 s15, s15 - 8000ce8: eddf 6a54 vldr s13, [pc, #336] @ 8000e3c - 8000cec: ee67 7aa6 vmul.f32 s15, s15, s13 - 8000cf0: eeb4 7ae7 vcmpe.f32 s14, s15 - 8000cf4: eef1 fa10 vmrs APSR_nzcv, fpscr - 8000cf8: db1a blt.n 8000d30 - HAL_GPIO_WritePin(IN5_GPIO_Port, IN5_Pin, (GPIO_PinState)UpdatePorts.porta.epsc); // switch PROFET - 8000cfa: 793b ldrb r3, [r7, #4] - 8000cfc: f3c3 1300 ubfx r3, r3, #4, #1 - 8000d00: b2db uxtb r3, r3 - 8000d02: 461a mov r2, r3 - 8000d04: f44f 4180 mov.w r1, #16384 @ 0x4000 - 8000d08: 4849 ldr r0, [pc, #292] @ (8000e30 ) - 8000d0a: f003 fecb bl 8004aa4 + 8000ce8: 2201 movs r2, #1 + 8000cea: 2140 movs r1, #64 @ 0x40 + 8000cec: 4856 ldr r0, [pc, #344] @ (8000e48 ) + 8000cee: f003 ff27 bl 8004b40 + if (current_measurements_adc_val.epsc_precharge >= (0.95f * current_measurements_adc_val.asms_v)) { // check if precharge is complete (no while loop needed, this function is called by the main while-loop) + 8000cf2: 4b57 ldr r3, [pc, #348] @ (8000e50 ) + 8000cf4: 8b5b ldrh r3, [r3, #26] + 8000cf6: ee07 3a90 vmov s15, r3 + 8000cfa: eeb8 7ae7 vcvt.f32.s32 s14, s15 + 8000cfe: 4b54 ldr r3, [pc, #336] @ (8000e50 ) + 8000d00: 8bdb ldrh r3, [r3, #30] + 8000d02: ee07 3a90 vmov s15, r3 + 8000d06: eef8 7ae7 vcvt.f32.s32 s15, s15 + 8000d0a: eddf 6a52 vldr s13, [pc, #328] @ 8000e54 + 8000d0e: ee67 7aa6 vmul.f32 s15, s15, s13 + 8000d12: eeb4 7ae7 vcmpe.f32 s14, s15 + 8000d16: eef1 fa10 vmrs APSR_nzcv, fpscr + 8000d1a: db15 blt.n 8000d48 + HAL_GPIO_WritePin(IN5_GPIO_Port, IN5_Pin, (GPIO_PinState)UpdatePorts.porta.epsc); // switch on PROFET + 8000d1c: 793b ldrb r3, [r7, #4] + 8000d1e: f3c3 1300 ubfx r3, r3, #4, #1 + 8000d22: b2db uxtb r3, r3 + 8000d24: 461a mov r2, r3 + 8000d26: f44f 4180 mov.w r1, #16384 @ 0x4000 + 8000d2a: 4847 ldr r0, [pc, #284] @ (8000e48 ) + 8000d2c: f003 ff08 bl 8004b40 HAL_GPIO_WritePin(PC_EN_GPIO_Port, PC_EN_Pin, 0); // disengage precharge - 8000d0e: 2200 movs r2, #0 - 8000d10: 2140 movs r1, #64 @ 0x40 - 8000d12: 4847 ldr r0, [pc, #284] @ (8000e30 ) - 8000d14: f003 fec6 bl 8004aa4 - HAL_GPIO_WritePin(LED3_GPIO_Port, LED3_Pin, 0); - 8000d18: 2200 movs r2, #0 - 8000d1a: 2180 movs r1, #128 @ 0x80 - 8000d1c: 4843 ldr r0, [pc, #268] @ (8000e2c ) - 8000d1e: f003 fec1 bl 8004aa4 + 8000d30: 2200 movs r2, #0 + 8000d32: 2140 movs r1, #64 @ 0x40 + 8000d34: 4844 ldr r0, [pc, #272] @ (8000e48 ) + 8000d36: f003 ff03 bl 8004b40 prev_epsc_state = UpdatePorts.porta.epsc; - 8000d22: 793b ldrb r3, [r7, #4] - 8000d24: f3c3 1300 ubfx r3, r3, #4, #1 - 8000d28: b2db uxtb r3, r3 - 8000d2a: 461a mov r2, r3 - 8000d2c: 4b41 ldr r3, [pc, #260] @ (8000e34 ) - 8000d2e: 601a str r2, [r3, #0] + 8000d3a: 793b ldrb r3, [r7, #4] + 8000d3c: f3c3 1300 ubfx r3, r3, #4, #1 + 8000d40: b2db uxtb r3, r3 + 8000d42: 461a mov r2, r3 + 8000d44: 4b41 ldr r3, [pc, #260] @ (8000e4c ) + 8000d46: 601a str r2, [r3, #0] } } if ((prev_epsc_state == 1 && UpdatePorts.porta.epsc == 0) || (prev_epsc_state == UpdatePorts.porta.epsc)){ - 8000d30: 4b40 ldr r3, [pc, #256] @ (8000e34 ) - 8000d32: 681b ldr r3, [r3, #0] - 8000d34: 2b01 cmp r3, #1 - 8000d36: d105 bne.n 8000d44 - 8000d38: 793b ldrb r3, [r7, #4] - 8000d3a: f003 0310 and.w r3, r3, #16 - 8000d3e: b2db uxtb r3, r3 - 8000d40: 2b00 cmp r3, #0 - 8000d42: d008 beq.n 8000d56 - 8000d44: 793b ldrb r3, [r7, #4] - 8000d46: f3c3 1300 ubfx r3, r3, #4, #1 - 8000d4a: b2db uxtb r3, r3 - 8000d4c: 461a mov r2, r3 - 8000d4e: 4b39 ldr r3, [pc, #228] @ (8000e34 ) - 8000d50: 681b ldr r3, [r3, #0] - 8000d52: 429a cmp r2, r3 - 8000d54: d115 bne.n 8000d82 + 8000d48: 4b40 ldr r3, [pc, #256] @ (8000e4c ) + 8000d4a: 681b ldr r3, [r3, #0] + 8000d4c: 2b01 cmp r3, #1 + 8000d4e: d105 bne.n 8000d5c + 8000d50: 793b ldrb r3, [r7, #4] + 8000d52: f003 0310 and.w r3, r3, #16 + 8000d56: b2db uxtb r3, r3 + 8000d58: 2b00 cmp r3, #0 + 8000d5a: d008 beq.n 8000d6e + 8000d5c: 793b ldrb r3, [r7, #4] + 8000d5e: f3c3 1300 ubfx r3, r3, #4, #1 + 8000d62: b2db uxtb r3, r3 + 8000d64: 461a mov r2, r3 + 8000d66: 4b39 ldr r3, [pc, #228] @ (8000e4c ) + 8000d68: 681b ldr r3, [r3, #0] + 8000d6a: 429a cmp r2, r3 + 8000d6c: d115 bne.n 8000d9a HAL_GPIO_WritePin(PC_EN_GPIO_Port, PC_EN_Pin, 0); // ensure precharge is disabled, when not needed or stopped - 8000d56: 2200 movs r2, #0 - 8000d58: 2140 movs r1, #64 @ 0x40 - 8000d5a: 4835 ldr r0, [pc, #212] @ (8000e30 ) - 8000d5c: f003 fea2 bl 8004aa4 + 8000d6e: 2200 movs r2, #0 + 8000d70: 2140 movs r1, #64 @ 0x40 + 8000d72: 4835 ldr r0, [pc, #212] @ (8000e48 ) + 8000d74: f003 fee4 bl 8004b40 HAL_GPIO_WritePin(IN5_GPIO_Port, IN5_Pin, (GPIO_PinState)UpdatePorts.porta.epsc); - 8000d60: 793b ldrb r3, [r7, #4] - 8000d62: f3c3 1300 ubfx r3, r3, #4, #1 - 8000d66: b2db uxtb r3, r3 - 8000d68: 461a mov r2, r3 - 8000d6a: f44f 4180 mov.w r1, #16384 @ 0x4000 - 8000d6e: 4830 ldr r0, [pc, #192] @ (8000e30 ) - 8000d70: f003 fe98 bl 8004aa4 + 8000d78: 793b ldrb r3, [r7, #4] + 8000d7a: f3c3 1300 ubfx r3, r3, #4, #1 + 8000d7e: b2db uxtb r3, r3 + 8000d80: 461a mov r2, r3 + 8000d82: f44f 4180 mov.w r1, #16384 @ 0x4000 + 8000d86: 4830 ldr r0, [pc, #192] @ (8000e48 ) + 8000d88: f003 feda bl 8004b40 prev_epsc_state = UpdatePorts.porta.epsc; - 8000d74: 793b ldrb r3, [r7, #4] - 8000d76: f3c3 1300 ubfx r3, r3, #4, #1 - 8000d7a: b2db uxtb r3, r3 - 8000d7c: 461a mov r2, r3 - 8000d7e: 4b2d ldr r3, [pc, #180] @ (8000e34 ) - 8000d80: 601a str r2, [r3, #0] + 8000d8c: 793b ldrb r3, [r7, #4] + 8000d8e: f3c3 1300 ubfx r3, r3, #4, #1 + 8000d92: b2db uxtb r3, r3 + 8000d94: 461a mov r2, r3 + 8000d96: 4b2d ldr r3, [pc, #180] @ (8000e4c ) + 8000d98: 601a str r2, [r3, #0] } HAL_GPIO_WritePin(IN6_GPIO_Port, IN6_Pin, (GPIO_PinState)UpdatePorts.porta.inverter); // inverter - 8000d82: 793b ldrb r3, [r7, #4] - 8000d84: f3c3 1340 ubfx r3, r3, #5, #1 - 8000d88: b2db uxtb r3, r3 - 8000d8a: 461a mov r2, r3 - 8000d8c: f44f 6180 mov.w r1, #1024 @ 0x400 - 8000d90: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 - 8000d94: f003 fe86 bl 8004aa4 + 8000d9a: 793b ldrb r3, [r7, #4] + 8000d9c: f3c3 1340 ubfx r3, r3, #5, #1 + 8000da0: b2db uxtb r3, r3 + 8000da2: 461a mov r2, r3 + 8000da4: f44f 6180 mov.w r1, #1024 @ 0x400 + 8000da8: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 + 8000dac: f003 fec8 bl 8004b40 HAL_GPIO_WritePin(IN7_GPIO_Port, IN7_Pin, (GPIO_PinState)UpdatePorts.porta.lidar); // lidar - 8000d98: 793b ldrb r3, [r7, #4] - 8000d9a: f3c3 1380 ubfx r3, r3, #6, #1 - 8000d9e: b2db uxtb r3, r3 - 8000da0: 461a mov r2, r3 - 8000da2: f44f 7180 mov.w r1, #256 @ 0x100 - 8000da6: 4822 ldr r0, [pc, #136] @ (8000e30 ) - 8000da8: f003 fe7c bl 8004aa4 + 8000db0: 793b ldrb r3, [r7, #4] + 8000db2: f3c3 1380 ubfx r3, r3, #6, #1 + 8000db6: b2db uxtb r3, r3 + 8000db8: 461a mov r2, r3 + 8000dba: f44f 7180 mov.w r1, #256 @ 0x100 + 8000dbe: 4822 ldr r0, [pc, #136] @ (8000e48 ) + 8000dc0: f003 febe bl 8004b40 HAL_GPIO_WritePin(IN8_GPIO_Port, IN8_Pin, (GPIO_PinState)UpdatePorts.porta.misc); // MISC - 8000dac: 793b ldrb r3, [r7, #4] - 8000dae: f3c3 13c0 ubfx r3, r3, #7, #1 - 8000db2: b2db uxtb r3, r3 - 8000db4: 461a mov r2, r3 - 8000db6: f44f 5100 mov.w r1, #8192 @ 0x2000 - 8000dba: 481d ldr r0, [pc, #116] @ (8000e30 ) - 8000dbc: f003 fe72 bl 8004aa4 - HAL_GPIO_WritePin(IN9_GPIO_Port, IN9_Pin, (GPIO_PinState)UpdatePorts.portb.alwayson); // always on -> standardmäßig auf HIGH forcen - 8000dc0: 797b ldrb r3, [r7, #5] - 8000dc2: f3c3 0300 ubfx r3, r3, #0, #1 - 8000dc6: b2db uxtb r3, r3 - 8000dc8: 461a mov r2, r3 - 8000dca: f44f 6100 mov.w r1, #2048 @ 0x800 - 8000dce: 4818 ldr r0, [pc, #96] @ (8000e30 ) - 8000dd0: f003 fe68 bl 8004aa4 - HAL_GPIO_WritePin(IN10_GPIO_Port, IN10_Pin, (GPIO_PinState)UpdatePorts.portb.sdc); // SDC -> muss anders controlled werden - 8000dd4: 797b ldrb r3, [r7, #5] - 8000dd6: f3c3 0340 ubfx r3, r3, #1, #1 - 8000dda: b2db uxtb r3, r3 - 8000ddc: 461a mov r2, r3 - 8000dde: f44f 7100 mov.w r1, #512 @ 0x200 - 8000de2: 4813 ldr r0, [pc, #76] @ (8000e30 ) - 8000de4: f003 fe5e bl 8004aa4 + 8000dc4: 793b ldrb r3, [r7, #4] + 8000dc6: f3c3 13c0 ubfx r3, r3, #7, #1 + 8000dca: b2db uxtb r3, r3 + 8000dcc: 461a mov r2, r3 + 8000dce: f44f 5100 mov.w r1, #8192 @ 0x2000 + 8000dd2: 481d ldr r0, [pc, #116] @ (8000e48 ) + 8000dd4: f003 feb4 bl 8004b40 + HAL_GPIO_WritePin(IN9_GPIO_Port, IN9_Pin, (GPIO_PinState)UpdatePorts.portb.alwayson); // always on + 8000dd8: 797b ldrb r3, [r7, #5] + 8000dda: f3c3 0300 ubfx r3, r3, #0, #1 + 8000dde: b2db uxtb r3, r3 + 8000de0: 461a mov r2, r3 + 8000de2: f44f 6100 mov.w r1, #2048 @ 0x800 + 8000de6: 4818 ldr r0, [pc, #96] @ (8000e48 ) + 8000de8: f003 feaa bl 8004b40 + HAL_GPIO_WritePin(IN10_GPIO_Port, IN10_Pin, (GPIO_PinState)UpdatePorts.portb.sdc); // SDC + 8000dec: 797b ldrb r3, [r7, #5] + 8000dee: f3c3 0340 ubfx r3, r3, #1, #1 + 8000df2: b2db uxtb r3, r3 + 8000df4: 461a mov r2, r3 + 8000df6: f44f 7100 mov.w r1, #512 @ 0x200 + 8000dfa: 4813 ldr r0, [pc, #76] @ (8000e48 ) + 8000dfc: f003 fea0 bl 8004b40 HAL_GPIO_WritePin(IN11_GPIO_Port, IN11_Pin, (GPIO_PinState)UpdatePorts.portb.ebs1); // EBS 1 - 8000de8: 797b ldrb r3, [r7, #5] - 8000dea: f3c3 0380 ubfx r3, r3, #2, #1 - 8000dee: b2db uxtb r3, r3 - 8000df0: 461a mov r2, r3 - 8000df2: 2104 movs r1, #4 - 8000df4: 480e ldr r0, [pc, #56] @ (8000e30 ) - 8000df6: f003 fe55 bl 8004aa4 + 8000e00: 797b ldrb r3, [r7, #5] + 8000e02: f3c3 0380 ubfx r3, r3, #2, #1 + 8000e06: b2db uxtb r3, r3 + 8000e08: 461a mov r2, r3 + 8000e0a: 2104 movs r1, #4 + 8000e0c: 480e ldr r0, [pc, #56] @ (8000e48 ) + 8000e0e: f003 fe97 bl 8004b40 HAL_GPIO_WritePin(IN12_GPIO_Port, IN12_Pin, (GPIO_PinState)UpdatePorts.portb.ebs2); // EBS 2 - 8000dfa: 797b ldrb r3, [r7, #5] - 8000dfc: f3c3 03c0 ubfx r3, r3, #3, #1 - 8000e00: b2db uxtb r3, r3 - 8000e02: 461a mov r2, r3 - 8000e04: 2102 movs r1, #2 - 8000e06: 480a ldr r0, [pc, #40] @ (8000e30 ) - 8000e08: f003 fe4c bl 8004aa4 + 8000e12: 797b ldrb r3, [r7, #5] + 8000e14: f3c3 03c0 ubfx r3, r3, #3, #1 + 8000e18: b2db uxtb r3, r3 + 8000e1a: 461a mov r2, r3 + 8000e1c: 2102 movs r1, #2 + 8000e1e: 480a ldr r0, [pc, #40] @ (8000e48 ) + 8000e20: f003 fe8e bl 8004b40 HAL_GPIO_WritePin(IN13_GPIO_Port, IN13_Pin, (GPIO_PinState)UpdatePorts.portb.ebs3); // EBS 3 - 8000e0c: 797b ldrb r3, [r7, #5] - 8000e0e: f3c3 1300 ubfx r3, r3, #4, #1 - 8000e12: b2db uxtb r3, r3 - 8000e14: 461a mov r2, r3 - 8000e16: f44f 6180 mov.w r1, #1024 @ 0x400 - 8000e1a: 4805 ldr r0, [pc, #20] @ (8000e30 ) - 8000e1c: f003 fe42 bl 8004aa4 + 8000e24: 797b ldrb r3, [r7, #5] + 8000e26: f3c3 1300 ubfx r3, r3, #4, #1 + 8000e2a: b2db uxtb r3, r3 + 8000e2c: 461a mov r2, r3 + 8000e2e: f44f 6180 mov.w r1, #1024 @ 0x400 + 8000e32: 4805 ldr r0, [pc, #20] @ (8000e48 ) + 8000e34: f003 fe84 bl 8004b40 } - 8000e20: bf00 nop - 8000e22: 3708 adds r7, #8 - 8000e24: 46bd mov sp, r7 - 8000e26: bd80 pop {r7, pc} - 8000e28: 200002f0 .word 0x200002f0 - 8000e2c: 48000800 .word 0x48000800 - 8000e30: 48000400 .word 0x48000400 - 8000e34: 20000078 .word 0x20000078 - 8000e38: 20000098 .word 0x20000098 - 8000e3c: 3f733333 .word 0x3f733333 + 8000e38: bf00 nop + 8000e3a: 3708 adds r7, #8 + 8000e3c: 46bd mov sp, r7 + 8000e3e: bd80 pop {r7, pc} + 8000e40: 200002f0 .word 0x200002f0 + 8000e44: 48000800 .word 0x48000800 + 8000e48: 48000400 .word 0x48000400 + 8000e4c: 20000078 .word 0x20000078 + 8000e50: 20000098 .word 0x20000098 + 8000e54: 3f733333 .word 0x3f733333 -08000e40 : +08000e58 : GPIO_PinState valve3 = GPIO_PIN_RESET; ADC_HandleTypeDef* adc1; ADC_HandleTypeDef* adc2; void current_monitor_init(ADC_HandleTypeDef* hadc1, ADC_HandleTypeDef* hadc2, TIM_HandleTypeDef* trigtim) { - 8000e40: b580 push {r7, lr} - 8000e42: b084 sub sp, #16 - 8000e44: af00 add r7, sp, #0 - 8000e46: 60f8 str r0, [r7, #12] - 8000e48: 60b9 str r1, [r7, #8] - 8000e4a: 607a str r2, [r7, #4] + 8000e58: b580 push {r7, lr} + 8000e5a: b084 sub sp, #16 + 8000e5c: af00 add r7, sp, #0 + 8000e5e: 60f8 str r0, [r7, #12] + 8000e60: 60b9 str r1, [r7, #8] + 8000e62: 607a str r2, [r7, #4] HAL_GPIO_WritePin(DSEL0_GPIO_Port, DSEL0_Pin, valve3); - 8000e4c: 4b12 ldr r3, [pc, #72] @ (8000e98 ) - 8000e4e: 781b ldrb r3, [r3, #0] - 8000e50: 461a mov r2, r3 - 8000e52: 2110 movs r1, #16 - 8000e54: 4811 ldr r0, [pc, #68] @ (8000e9c ) - 8000e56: f003 fe25 bl 8004aa4 + 8000e64: 4b12 ldr r3, [pc, #72] @ (8000eb0 ) + 8000e66: 781b ldrb r3, [r3, #0] + 8000e68: 461a mov r2, r3 + 8000e6a: 2110 movs r1, #16 + 8000e6c: 4811 ldr r0, [pc, #68] @ (8000eb4 ) + 8000e6e: f003 fe67 bl 8004b40 HAL_GPIO_WritePin(DSEL1_GPIO_Port, DSEL1_Pin, valve2); - 8000e5a: 4b11 ldr r3, [pc, #68] @ (8000ea0 ) - 8000e5c: 781b ldrb r3, [r3, #0] - 8000e5e: 461a mov r2, r3 - 8000e60: 2120 movs r1, #32 - 8000e62: 480e ldr r0, [pc, #56] @ (8000e9c ) - 8000e64: f003 fe1e bl 8004aa4 + 8000e72: 4b11 ldr r3, [pc, #68] @ (8000eb8 ) + 8000e74: 781b ldrb r3, [r3, #0] + 8000e76: 461a mov r2, r3 + 8000e78: 2120 movs r1, #32 + 8000e7a: 480e ldr r0, [pc, #56] @ (8000eb4 ) + 8000e7c: f003 fe60 bl 8004b40 adc1 = hadc1; - 8000e68: 4a0e ldr r2, [pc, #56] @ (8000ea4 ) - 8000e6a: 68fb ldr r3, [r7, #12] - 8000e6c: 6013 str r3, [r2, #0] + 8000e80: 4a0e ldr r2, [pc, #56] @ (8000ebc ) + 8000e82: 68fb ldr r3, [r7, #12] + 8000e84: 6013 str r3, [r2, #0] adc2 = hadc2; - 8000e6e: 4a0e ldr r2, [pc, #56] @ (8000ea8 ) - 8000e70: 68bb ldr r3, [r7, #8] - 8000e72: 6013 str r3, [r2, #0] + 8000e86: 4a0e ldr r2, [pc, #56] @ (8000ec0 ) + 8000e88: 68bb ldr r3, [r7, #8] + 8000e8a: 6013 str r3, [r2, #0] HAL_TIM_Base_Start(trigtim); - 8000e74: 6878 ldr r0, [r7, #4] - 8000e76: f005 fa77 bl 8006368 + 8000e8c: 6878 ldr r0, [r7, #4] + 8000e8e: f005 fab9 bl 8006404 HAL_ADC_Start_DMA(hadc1, (uint32_t*)adc_channels1.adcbuffer, 8); - 8000e7a: 2208 movs r2, #8 - 8000e7c: 490b ldr r1, [pc, #44] @ (8000eac ) - 8000e7e: 68f8 ldr r0, [r7, #12] - 8000e80: f001 fbd2 bl 8002628 + 8000e92: 2208 movs r2, #8 + 8000e94: 490b ldr r1, [pc, #44] @ (8000ec4 ) + 8000e96: 68f8 ldr r0, [r7, #12] + 8000e98: f001 fc14 bl 80026c4 HAL_ADC_Start_DMA(hadc2, (uint32_t*)adc_channels2.adcbuffer, 6); - 8000e84: 2206 movs r2, #6 - 8000e86: 490a ldr r1, [pc, #40] @ (8000eb0 ) - 8000e88: 68b8 ldr r0, [r7, #8] - 8000e8a: f001 fbcd bl 8002628 + 8000e9c: 2206 movs r2, #6 + 8000e9e: 490a ldr r1, [pc, #40] @ (8000ec8 ) + 8000ea0: 68b8 ldr r0, [r7, #8] + 8000ea2: f001 fc0f bl 80026c4 } - 8000e8e: bf00 nop - 8000e90: 3710 adds r7, #16 - 8000e92: 46bd mov sp, r7 - 8000e94: bd80 pop {r7, pc} - 8000e96: bf00 nop - 8000e98: 200000b9 .word 0x200000b9 - 8000e9c: 48000400 .word 0x48000400 - 8000ea0: 200000b8 .word 0x200000b8 - 8000ea4: 200000bc .word 0x200000bc - 8000ea8: 200000c0 .word 0x200000c0 - 8000eac: 2000007c .word 0x2000007c - 8000eb0: 2000008c .word 0x2000008c + 8000ea6: bf00 nop + 8000ea8: 3710 adds r7, #16 + 8000eaa: 46bd mov sp, r7 + 8000eac: bd80 pop {r7, pc} + 8000eae: bf00 nop + 8000eb0: 200000b9 .word 0x200000b9 + 8000eb4: 48000400 .word 0x48000400 + 8000eb8: 200000b8 .word 0x200000b8 + 8000ebc: 200000bc .word 0x200000bc + 8000ec0: 200000c0 .word 0x200000c0 + 8000ec4: 2000007c .word 0x2000007c + 8000ec8: 2000008c .word 0x2000008c -08000eb4 : +08000ecc : uint8_t current_monitor_checklimits() {return 0;} // TODO: implement properly - 8000eb4: b480 push {r7} - 8000eb6: af00 add r7, sp, #0 - 8000eb8: 2300 movs r3, #0 - 8000eba: 4618 mov r0, r3 - 8000ebc: 46bd mov sp, r7 - 8000ebe: f85d 7b04 ldr.w r7, [sp], #4 - 8000ec2: 4770 bx lr - 8000ec4: 0000 movs r0, r0 + 8000ecc: b480 push {r7} + 8000ece: af00 add r7, sp, #0 + 8000ed0: 2300 movs r3, #0 + 8000ed2: 4618 mov r0, r3 + 8000ed4: 46bd mov sp, r7 + 8000ed6: f85d 7b04 ldr.w r7, [sp], #4 + 8000eda: 4770 bx lr + 8000edc: 0000 movs r0, r0 ... -08000ec8 : +08000ee0 : void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) { - 8000ec8: b580 push {r7, lr} - 8000eca: b082 sub sp, #8 - 8000ecc: af00 add r7, sp, #0 - 8000ece: 6078 str r0, [r7, #4] + 8000ee0: b580 push {r7, lr} + 8000ee2: b082 sub sp, #8 + 8000ee4: af00 add r7, sp, #0 + 8000ee6: 6078 str r0, [r7, #4] if (hadc == adc1){ - 8000ed0: 4b30 ldr r3, [pc, #192] @ (8000f94 ) - 8000ed2: 681b ldr r3, [r3, #0] - 8000ed4: 687a ldr r2, [r7, #4] - 8000ed6: 429a cmp r2, r3 - 8000ed8: d168 bne.n 8000fac + 8000ee8: 4b30 ldr r3, [pc, #192] @ (8000fac ) + 8000eea: 681b ldr r3, [r3, #0] + 8000eec: 687a ldr r2, [r7, #4] + 8000eee: 429a cmp r2, r3 + 8000ef0: d168 bne.n 8000fc4 if (valve2 == GPIO_PIN_RESET && valve3 == GPIO_PIN_RESET){ - 8000eda: 4b2f ldr r3, [pc, #188] @ (8000f98 ) - 8000edc: 781b ldrb r3, [r3, #0] - 8000ede: 2b00 cmp r3, #0 - 8000ee0: d118 bne.n 8000f14 - 8000ee2: 4b2e ldr r3, [pc, #184] @ (8000f9c ) - 8000ee4: 781b ldrb r3, [r3, #0] - 8000ee6: 2b00 cmp r3, #0 - 8000ee8: d114 bne.n 8000f14 + 8000ef2: 4b2f ldr r3, [pc, #188] @ (8000fb0 ) + 8000ef4: 781b ldrb r3, [r3, #0] + 8000ef6: 2b00 cmp r3, #0 + 8000ef8: d118 bne.n 8000f2c + 8000efa: 4b2e ldr r3, [pc, #184] @ (8000fb4 ) + 8000efc: 781b ldrb r3, [r3, #0] + 8000efe: 2b00 cmp r3, #0 + 8000f00: d114 bne.n 8000f2c current_measurements_adc_val.ebs1 = adc_channels1.adcbank1.isense11 * CURR_SENSE_FACTOR_1A; - 8000eea: 4b2d ldr r3, [pc, #180] @ (8000fa0 ) - 8000eec: 881b ldrh r3, [r3, #0] - 8000eee: b29b uxth r3, r3 - 8000ef0: ee07 3a90 vmov s15, r3 - 8000ef4: eef8 7ae7 vcvt.f32.s32 s15, s15 - 8000ef8: ed9f 7a2a vldr s14, [pc, #168] @ 8000fa4 - 8000efc: ee67 7a87 vmul.f32 s15, s15, s14 - 8000f00: eefc 7ae7 vcvt.u32.f32 s15, s15 - 8000f04: ee17 3a90 vmov r3, s15 - 8000f08: b29a uxth r2, r3 - 8000f0a: 4b27 ldr r3, [pc, #156] @ (8000fa8 ) - 8000f0c: 829a strh r2, [r3, #20] + 8000f02: 4b2d ldr r3, [pc, #180] @ (8000fb8 ) + 8000f04: 881b ldrh r3, [r3, #0] + 8000f06: b29b uxth r3, r3 + 8000f08: ee07 3a90 vmov s15, r3 + 8000f0c: eef8 7ae7 vcvt.f32.s32 s15, s15 + 8000f10: ed9f 7a2a vldr s14, [pc, #168] @ 8000fbc + 8000f14: ee67 7a87 vmul.f32 s15, s15, s14 + 8000f18: eefc 7ae7 vcvt.u32.f32 s15, s15 + 8000f1c: ee17 3a90 vmov r3, s15 + 8000f20: b29a uxth r2, r3 + 8000f22: 4b27 ldr r3, [pc, #156] @ (8000fc0 ) + 8000f24: 829a strh r2, [r3, #20] valve2 = GPIO_PIN_SET; - 8000f0e: 4b22 ldr r3, [pc, #136] @ (8000f98 ) - 8000f10: 2201 movs r2, #1 - 8000f12: 701a strb r2, [r3, #0] + 8000f26: 4b22 ldr r3, [pc, #136] @ (8000fb0 ) + 8000f28: 2201 movs r2, #1 + 8000f2a: 701a strb r2, [r3, #0] } if (valve2 == GPIO_PIN_SET && valve3 == GPIO_PIN_RESET){ - 8000f14: 4b20 ldr r3, [pc, #128] @ (8000f98 ) - 8000f16: 781b ldrb r3, [r3, #0] - 8000f18: 2b01 cmp r3, #1 - 8000f1a: d11b bne.n 8000f54 - 8000f1c: 4b1f ldr r3, [pc, #124] @ (8000f9c ) - 8000f1e: 781b ldrb r3, [r3, #0] - 8000f20: 2b00 cmp r3, #0 - 8000f22: d117 bne.n 8000f54 + 8000f2c: 4b20 ldr r3, [pc, #128] @ (8000fb0 ) + 8000f2e: 781b ldrb r3, [r3, #0] + 8000f30: 2b01 cmp r3, #1 + 8000f32: d11b bne.n 8000f6c + 8000f34: 4b1f ldr r3, [pc, #124] @ (8000fb4 ) + 8000f36: 781b ldrb r3, [r3, #0] + 8000f38: 2b00 cmp r3, #0 + 8000f3a: d117 bne.n 8000f6c current_measurements_adc_val.ebs2 = adc_channels1.adcbank1.isense11 * CURR_SENSE_FACTOR_1A; - 8000f24: 4b1e ldr r3, [pc, #120] @ (8000fa0 ) - 8000f26: 881b ldrh r3, [r3, #0] - 8000f28: b29b uxth r3, r3 - 8000f2a: ee07 3a90 vmov s15, r3 - 8000f2e: eef8 7ae7 vcvt.f32.s32 s15, s15 - 8000f32: ed9f 7a1c vldr s14, [pc, #112] @ 8000fa4 - 8000f36: ee67 7a87 vmul.f32 s15, s15, s14 - 8000f3a: eefc 7ae7 vcvt.u32.f32 s15, s15 - 8000f3e: ee17 3a90 vmov r3, s15 - 8000f42: b29a uxth r2, r3 - 8000f44: 4b18 ldr r3, [pc, #96] @ (8000fa8 ) - 8000f46: 82da strh r2, [r3, #22] + 8000f3c: 4b1e ldr r3, [pc, #120] @ (8000fb8 ) + 8000f3e: 881b ldrh r3, [r3, #0] + 8000f40: b29b uxth r3, r3 + 8000f42: ee07 3a90 vmov s15, r3 + 8000f46: eef8 7ae7 vcvt.f32.s32 s15, s15 + 8000f4a: ed9f 7a1c vldr s14, [pc, #112] @ 8000fbc + 8000f4e: ee67 7a87 vmul.f32 s15, s15, s14 + 8000f52: eefc 7ae7 vcvt.u32.f32 s15, s15 + 8000f56: ee17 3a90 vmov r3, s15 + 8000f5a: b29a uxth r2, r3 + 8000f5c: 4b18 ldr r3, [pc, #96] @ (8000fc0 ) + 8000f5e: 82da strh r2, [r3, #22] valve2 = GPIO_PIN_RESET; - 8000f48: 4b13 ldr r3, [pc, #76] @ (8000f98 ) - 8000f4a: 2200 movs r2, #0 - 8000f4c: 701a strb r2, [r3, #0] + 8000f60: 4b13 ldr r3, [pc, #76] @ (8000fb0 ) + 8000f62: 2200 movs r2, #0 + 8000f64: 701a strb r2, [r3, #0] valve3 = GPIO_PIN_SET; - 8000f4e: 4b13 ldr r3, [pc, #76] @ (8000f9c ) - 8000f50: 2201 movs r2, #1 - 8000f52: 701a strb r2, [r3, #0] + 8000f66: 4b13 ldr r3, [pc, #76] @ (8000fb4 ) + 8000f68: 2201 movs r2, #1 + 8000f6a: 701a strb r2, [r3, #0] } if (valve2 == GPIO_PIN_RESET && valve3 == GPIO_PIN_SET){ - 8000f54: 4b10 ldr r3, [pc, #64] @ (8000f98 ) - 8000f56: 781b ldrb r3, [r3, #0] - 8000f58: 2b00 cmp r3, #0 - 8000f5a: f040 80b9 bne.w 80010d0 - 8000f5e: 4b0f ldr r3, [pc, #60] @ (8000f9c ) - 8000f60: 781b ldrb r3, [r3, #0] - 8000f62: 2b01 cmp r3, #1 - 8000f64: f040 80b4 bne.w 80010d0 + 8000f6c: 4b10 ldr r3, [pc, #64] @ (8000fb0 ) + 8000f6e: 781b ldrb r3, [r3, #0] + 8000f70: 2b00 cmp r3, #0 + 8000f72: f040 80b9 bne.w 80010e8 + 8000f76: 4b0f ldr r3, [pc, #60] @ (8000fb4 ) + 8000f78: 781b ldrb r3, [r3, #0] + 8000f7a: 2b01 cmp r3, #1 + 8000f7c: f040 80b4 bne.w 80010e8 current_measurements_adc_val.ebs3 = adc_channels1.adcbank1.isense11 * CURR_SENSE_FACTOR_1A; - 8000f68: 4b0d ldr r3, [pc, #52] @ (8000fa0 ) - 8000f6a: 881b ldrh r3, [r3, #0] - 8000f6c: b29b uxth r3, r3 - 8000f6e: ee07 3a90 vmov s15, r3 - 8000f72: eef8 7ae7 vcvt.f32.s32 s15, s15 - 8000f76: ed9f 7a0b vldr s14, [pc, #44] @ 8000fa4 - 8000f7a: ee67 7a87 vmul.f32 s15, s15, s14 - 8000f7e: eefc 7ae7 vcvt.u32.f32 s15, s15 - 8000f82: ee17 3a90 vmov r3, s15 - 8000f86: b29a uxth r2, r3 - 8000f88: 4b07 ldr r3, [pc, #28] @ (8000fa8 ) - 8000f8a: 831a strh r2, [r3, #24] + 8000f80: 4b0d ldr r3, [pc, #52] @ (8000fb8 ) + 8000f82: 881b ldrh r3, [r3, #0] + 8000f84: b29b uxth r3, r3 + 8000f86: ee07 3a90 vmov s15, r3 + 8000f8a: eef8 7ae7 vcvt.f32.s32 s15, s15 + 8000f8e: ed9f 7a0b vldr s14, [pc, #44] @ 8000fbc + 8000f92: ee67 7a87 vmul.f32 s15, s15, s14 + 8000f96: eefc 7ae7 vcvt.u32.f32 s15, s15 + 8000f9a: ee17 3a90 vmov r3, s15 + 8000f9e: b29a uxth r2, r3 + 8000fa0: 4b07 ldr r3, [pc, #28] @ (8000fc0 ) + 8000fa2: 831a strh r2, [r3, #24] valve3 = GPIO_PIN_RESET; - 8000f8c: 4b03 ldr r3, [pc, #12] @ (8000f9c ) - 8000f8e: 2200 movs r2, #0 - 8000f90: 701a strb r2, [r3, #0] - 8000f92: e09d b.n 80010d0 - 8000f94: 200000bc .word 0x200000bc - 8000f98: 200000b8 .word 0x200000b8 - 8000f9c: 200000b9 .word 0x200000b9 - 8000fa0: 2000007c .word 0x2000007c - 8000fa4: 3d778f79 .word 0x3d778f79 - 8000fa8: 20000098 .word 0x20000098 + 8000fa4: 4b03 ldr r3, [pc, #12] @ (8000fb4 ) + 8000fa6: 2200 movs r2, #0 + 8000fa8: 701a strb r2, [r3, #0] + 8000faa: e09d b.n 80010e8 + 8000fac: 200000bc .word 0x200000bc + 8000fb0: 200000b8 .word 0x200000b8 + 8000fb4: 200000b9 .word 0x200000b9 + 8000fb8: 2000007c .word 0x2000007c + 8000fbc: 3d821665 .word 0x3d821665 + 8000fc0: 20000098 .word 0x20000098 } } else { current_measurements_adc_val.lvms_v = adc_channels1.adcbank1.lvms_vsense * LV_SENSE_FACTOR; - 8000fac: 4b88 ldr r3, [pc, #544] @ (80011d0 ) - 8000fae: 885b ldrh r3, [r3, #2] - 8000fb0: b29b uxth r3, r3 - 8000fb2: 4618 mov r0, r3 - 8000fb4: f7ff fb84 bl 80006c0 <__aeabi_i2d> - 8000fb8: a383 add r3, pc, #524 @ (adr r3, 80011c8 ) - 8000fba: e9d3 2300 ldrd r2, r3, [r3] - 8000fbe: f7ff f903 bl 80001c8 <__aeabi_dmul> - 8000fc2: 4602 mov r2, r0 - 8000fc4: 460b mov r3, r1 - 8000fc6: 4610 mov r0, r2 - 8000fc8: 4619 mov r1, r3 - 8000fca: f7ff fbe3 bl 8000794 <__aeabi_d2uiz> - 8000fce: 4603 mov r3, r0 - 8000fd0: b29a uxth r2, r3 - 8000fd2: 4b80 ldr r3, [pc, #512] @ (80011d4 ) - 8000fd4: 839a strh r2, [r3, #28] + 8000fc4: 4b88 ldr r3, [pc, #544] @ (80011e8 ) + 8000fc6: 885b ldrh r3, [r3, #2] + 8000fc8: b29b uxth r3, r3 + 8000fca: 4618 mov r0, r3 + 8000fcc: f7ff fb78 bl 80006c0 <__aeabi_i2d> + 8000fd0: a383 add r3, pc, #524 @ (adr r3, 80011e0 ) + 8000fd2: e9d3 2300 ldrd r2, r3, [r3] + 8000fd6: f7ff f8f7 bl 80001c8 <__aeabi_dmul> + 8000fda: 4602 mov r2, r0 + 8000fdc: 460b mov r3, r1 + 8000fde: 4610 mov r0, r2 + 8000fe0: 4619 mov r1, r3 + 8000fe2: f7ff fbd7 bl 8000794 <__aeabi_d2uiz> + 8000fe6: 4603 mov r3, r0 + 8000fe8: b29a uxth r2, r3 + 8000fea: 4b80 ldr r3, [pc, #512] @ (80011ec ) + 8000fec: 839a strh r2, [r3, #28] current_measurements_adc_val.acc_cooling = adc_channels1.adcbank1.isense1 * CURR_SENSE_FACTOR_9A; - 8000fd6: 4b7e ldr r3, [pc, #504] @ (80011d0 ) - 8000fd8: 889b ldrh r3, [r3, #4] - 8000fda: b29b uxth r3, r3 - 8000fdc: ee07 3a90 vmov s15, r3 - 8000fe0: eef8 7ae7 vcvt.f32.s32 s15, s15 - 8000fe4: ed9f 7a7c vldr s14, [pc, #496] @ 80011d8 - 8000fe8: ee67 7a87 vmul.f32 s15, s15, s14 - 8000fec: eefc 7ae7 vcvt.u32.f32 s15, s15 - 8000ff0: ee17 3a90 vmov r3, s15 - 8000ff4: b29a uxth r2, r3 - 8000ff6: 4b77 ldr r3, [pc, #476] @ (80011d4 ) - 8000ff8: 801a strh r2, [r3, #0] + 8000fee: 4b7e ldr r3, [pc, #504] @ (80011e8 ) + 8000ff0: 889b ldrh r3, [r3, #4] + 8000ff2: b29b uxth r3, r3 + 8000ff4: ee07 3a90 vmov s15, r3 + 8000ff8: eef8 7ae7 vcvt.f32.s32 s15, s15 + 8000ffc: ed9f 7a7c vldr s14, [pc, #496] @ 80011f0 + 8001000: ee67 7a87 vmul.f32 s15, s15, s14 + 8001004: eefc 7ae7 vcvt.u32.f32 s15, s15 + 8001008: ee17 3a90 vmov r3, s15 + 800100c: b29a uxth r2, r3 + 800100e: 4b77 ldr r3, [pc, #476] @ (80011ec ) + 8001010: 801a strh r2, [r3, #0] current_measurements_adc_val.ts_cooling = adc_channels1.adcbank1.isense2 * CURR_SENSE_FACTOR_9A; - 8000ffa: 4b75 ldr r3, [pc, #468] @ (80011d0 ) - 8000ffc: 88db ldrh r3, [r3, #6] - 8000ffe: b29b uxth r3, r3 - 8001000: ee07 3a90 vmov s15, r3 - 8001004: eef8 7ae7 vcvt.f32.s32 s15, s15 - 8001008: ed9f 7a73 vldr s14, [pc, #460] @ 80011d8 - 800100c: ee67 7a87 vmul.f32 s15, s15, s14 - 8001010: eefc 7ae7 vcvt.u32.f32 s15, s15 - 8001014: ee17 3a90 vmov r3, s15 - 8001018: b29a uxth r2, r3 - 800101a: 4b6e ldr r3, [pc, #440] @ (80011d4 ) - 800101c: 805a strh r2, [r3, #2] + 8001012: 4b75 ldr r3, [pc, #468] @ (80011e8 ) + 8001014: 88db ldrh r3, [r3, #6] + 8001016: b29b uxth r3, r3 + 8001018: ee07 3a90 vmov s15, r3 + 800101c: eef8 7ae7 vcvt.f32.s32 s15, s15 + 8001020: ed9f 7a73 vldr s14, [pc, #460] @ 80011f0 + 8001024: ee67 7a87 vmul.f32 s15, s15, s14 + 8001028: eefc 7ae7 vcvt.u32.f32 s15, s15 + 800102c: ee17 3a90 vmov r3, s15 + 8001030: b29a uxth r2, r3 + 8001032: 4b6e ldr r3, [pc, #440] @ (80011ec ) + 8001034: 805a strh r2, [r3, #2] current_measurements_adc_val.alwayson = adc_channels1.adcbank1.isense9 * CURR_SENSE_FACTOR_9A; - 800101e: 4b6c ldr r3, [pc, #432] @ (80011d0 ) - 8001020: 891b ldrh r3, [r3, #8] - 8001022: b29b uxth r3, r3 - 8001024: ee07 3a90 vmov s15, r3 - 8001028: eef8 7ae7 vcvt.f32.s32 s15, s15 - 800102c: ed9f 7a6a vldr s14, [pc, #424] @ 80011d8 - 8001030: ee67 7a87 vmul.f32 s15, s15, s14 - 8001034: eefc 7ae7 vcvt.u32.f32 s15, s15 - 8001038: ee17 3a90 vmov r3, s15 - 800103c: b29a uxth r2, r3 - 800103e: 4b65 ldr r3, [pc, #404] @ (80011d4 ) - 8001040: 821a strh r2, [r3, #16] + 8001036: 4b6c ldr r3, [pc, #432] @ (80011e8 ) + 8001038: 891b ldrh r3, [r3, #8] + 800103a: b29b uxth r3, r3 + 800103c: ee07 3a90 vmov s15, r3 + 8001040: eef8 7ae7 vcvt.f32.s32 s15, s15 + 8001044: ed9f 7a6a vldr s14, [pc, #424] @ 80011f0 + 8001048: ee67 7a87 vmul.f32 s15, s15, s14 + 800104c: eefc 7ae7 vcvt.u32.f32 s15, s15 + 8001050: ee17 3a90 vmov r3, s15 + 8001054: b29a uxth r2, r3 + 8001056: 4b65 ldr r3, [pc, #404] @ (80011ec ) + 8001058: 821a strh r2, [r3, #16] current_measurements_adc_val.asms_v = adc_channels1.adcbank1.asms_vsense * LV_SENSE_FACTOR; - 8001042: 4b63 ldr r3, [pc, #396] @ (80011d0 ) - 8001044: 895b ldrh r3, [r3, #10] - 8001046: b29b uxth r3, r3 - 8001048: 4618 mov r0, r3 - 800104a: f7ff fb39 bl 80006c0 <__aeabi_i2d> - 800104e: a35e add r3, pc, #376 @ (adr r3, 80011c8 ) - 8001050: e9d3 2300 ldrd r2, r3, [r3] - 8001054: f7ff f8b8 bl 80001c8 <__aeabi_dmul> - 8001058: 4602 mov r2, r0 - 800105a: 460b mov r3, r1 - 800105c: 4610 mov r0, r2 - 800105e: 4619 mov r1, r3 - 8001060: f7ff fb98 bl 8000794 <__aeabi_d2uiz> - 8001064: 4603 mov r3, r0 - 8001066: b29a uxth r2, r3 - 8001068: 4b5a ldr r3, [pc, #360] @ (80011d4 ) - 800106a: 83da strh r2, [r3, #30] + 800105a: 4b63 ldr r3, [pc, #396] @ (80011e8 ) + 800105c: 895b ldrh r3, [r3, #10] + 800105e: b29b uxth r3, r3 + 8001060: 4618 mov r0, r3 + 8001062: f7ff fb2d bl 80006c0 <__aeabi_i2d> + 8001066: a35e add r3, pc, #376 @ (adr r3, 80011e0 ) + 8001068: e9d3 2300 ldrd r2, r3, [r3] + 800106c: f7ff f8ac bl 80001c8 <__aeabi_dmul> + 8001070: 4602 mov r2, r0 + 8001072: 460b mov r3, r1 + 8001074: 4610 mov r0, r2 + 8001076: 4619 mov r1, r3 + 8001078: f7ff fb8c bl 8000794 <__aeabi_d2uiz> + 800107c: 4603 mov r3, r0 + 800107e: b29a uxth r2, r3 + 8001080: 4b5a ldr r3, [pc, #360] @ (80011ec ) + 8001082: 83da strh r2, [r3, #30] current_measurements_adc_val.sdc = adc_channels1.adcbank1.isense10 * CURR_SENSE_FACTOR_4_5A; - 800106c: 4b58 ldr r3, [pc, #352] @ (80011d0 ) - 800106e: 899b ldrh r3, [r3, #12] - 8001070: b29b uxth r3, r3 - 8001072: ee07 3a90 vmov s15, r3 - 8001076: eef8 7ae7 vcvt.f32.s32 s15, s15 - 800107a: ed9f 7a58 vldr s14, [pc, #352] @ 80011dc - 800107e: ee67 7a87 vmul.f32 s15, s15, s14 - 8001082: eefc 7ae7 vcvt.u32.f32 s15, s15 - 8001086: ee17 3a90 vmov r3, s15 - 800108a: b29a uxth r2, r3 - 800108c: 4b51 ldr r3, [pc, #324] @ (80011d4 ) - 800108e: 825a strh r2, [r3, #18] + 8001084: 4b58 ldr r3, [pc, #352] @ (80011e8 ) + 8001086: 899b ldrh r3, [r3, #12] + 8001088: b29b uxth r3, r3 + 800108a: ee07 3a90 vmov s15, r3 + 800108e: eef8 7ae7 vcvt.f32.s32 s15, s15 + 8001092: ed9f 7a58 vldr s14, [pc, #352] @ 80011f4 + 8001096: ee67 7a87 vmul.f32 s15, s15, s14 + 800109a: eefc 7ae7 vcvt.u32.f32 s15, s15 + 800109e: ee17 3a90 vmov r3, s15 + 80010a2: b29a uxth r2, r3 + 80010a4: 4b51 ldr r3, [pc, #324] @ (80011ec ) + 80010a6: 825a strh r2, [r3, #18] current_measurements_adc_val.inverter = adc_channels1.adcbank1.isense6 * CURR_SENSE_FACTOR_9A; - 8001090: 4b4f ldr r3, [pc, #316] @ (80011d0 ) - 8001092: 89db ldrh r3, [r3, #14] - 8001094: b29b uxth r3, r3 - 8001096: ee07 3a90 vmov s15, r3 - 800109a: eef8 7ae7 vcvt.f32.s32 s15, s15 - 800109e: ed9f 7a4e vldr s14, [pc, #312] @ 80011d8 - 80010a2: ee67 7a87 vmul.f32 s15, s15, s14 - 80010a6: eefc 7ae7 vcvt.u32.f32 s15, s15 - 80010aa: ee17 3a90 vmov r3, s15 - 80010ae: b29a uxth r2, r3 - 80010b0: 4b48 ldr r3, [pc, #288] @ (80011d4 ) - 80010b2: 815a strh r2, [r3, #10] + 80010a8: 4b4f ldr r3, [pc, #316] @ (80011e8 ) + 80010aa: 89db ldrh r3, [r3, #14] + 80010ac: b29b uxth r3, r3 + 80010ae: ee07 3a90 vmov s15, r3 + 80010b2: eef8 7ae7 vcvt.f32.s32 s15, s15 + 80010b6: ed9f 7a4e vldr s14, [pc, #312] @ 80011f0 + 80010ba: ee67 7a87 vmul.f32 s15, s15, s14 + 80010be: eefc 7ae7 vcvt.u32.f32 s15, s15 + 80010c2: ee17 3a90 vmov r3, s15 + 80010c6: b29a uxth r2, r3 + 80010c8: 4b48 ldr r3, [pc, #288] @ (80011ec ) + 80010ca: 815a strh r2, [r3, #10] HAL_GPIO_WritePin(DSEL0_GPIO_Port, DSEL0_Pin, valve3); - 80010b4: 4b4a ldr r3, [pc, #296] @ (80011e0 ) - 80010b6: 781b ldrb r3, [r3, #0] - 80010b8: 461a mov r2, r3 - 80010ba: 2110 movs r1, #16 - 80010bc: 4849 ldr r0, [pc, #292] @ (80011e4 ) - 80010be: f003 fcf1 bl 8004aa4 + 80010cc: 4b4a ldr r3, [pc, #296] @ (80011f8 ) + 80010ce: 781b ldrb r3, [r3, #0] + 80010d0: 461a mov r2, r3 + 80010d2: 2110 movs r1, #16 + 80010d4: 4849 ldr r0, [pc, #292] @ (80011fc ) + 80010d6: f003 fd33 bl 8004b40 HAL_GPIO_WritePin(DSEL1_GPIO_Port, DSEL1_Pin, valve2); - 80010c2: 4b49 ldr r3, [pc, #292] @ (80011e8 ) - 80010c4: 781b ldrb r3, [r3, #0] - 80010c6: 461a mov r2, r3 - 80010c8: 2120 movs r1, #32 - 80010ca: 4846 ldr r0, [pc, #280] @ (80011e4 ) - 80010cc: f003 fcea bl 8004aa4 + 80010da: 4b49 ldr r3, [pc, #292] @ (8001200 ) + 80010dc: 781b ldrb r3, [r3, #0] + 80010de: 461a mov r2, r3 + 80010e0: 2120 movs r1, #32 + 80010e2: 4846 ldr r0, [pc, #280] @ (80011fc ) + 80010e4: f003 fd2c bl 8004b40 } if (hadc == adc2){ - 80010d0: 4b46 ldr r3, [pc, #280] @ (80011ec ) - 80010d2: 681b ldr r3, [r3, #0] - 80010d4: 687a ldr r2, [r7, #4] - 80010d6: 429a cmp r2, r3 - 80010d8: d16e bne.n 80011b8 + 80010e8: 4b46 ldr r3, [pc, #280] @ (8001204 ) + 80010ea: 681b ldr r3, [r3, #0] + 80010ec: 687a ldr r2, [r7, #4] + 80010ee: 429a cmp r2, r3 + 80010f0: d16e bne.n 80011d0 current_measurements_adc_val.drs = adc_channels2.adcbank2.isense3 * CURR_SENSE_FACTOR_4_5A; - 80010da: 4b45 ldr r3, [pc, #276] @ (80011f0 ) - 80010dc: 881b ldrh r3, [r3, #0] - 80010de: b29b uxth r3, r3 - 80010e0: ee07 3a90 vmov s15, r3 - 80010e4: eef8 7ae7 vcvt.f32.s32 s15, s15 - 80010e8: ed9f 7a3c vldr s14, [pc, #240] @ 80011dc - 80010ec: ee67 7a87 vmul.f32 s15, s15, s14 - 80010f0: eefc 7ae7 vcvt.u32.f32 s15, s15 - 80010f4: ee17 3a90 vmov r3, s15 - 80010f8: b29a uxth r2, r3 - 80010fa: 4b36 ldr r3, [pc, #216] @ (80011d4 ) - 80010fc: 809a strh r2, [r3, #4] + 80010f2: 4b45 ldr r3, [pc, #276] @ (8001208 ) + 80010f4: 881b ldrh r3, [r3, #0] + 80010f6: b29b uxth r3, r3 + 80010f8: ee07 3a90 vmov s15, r3 + 80010fc: eef8 7ae7 vcvt.f32.s32 s15, s15 + 8001100: ed9f 7a3c vldr s14, [pc, #240] @ 80011f4 + 8001104: ee67 7a87 vmul.f32 s15, s15, s14 + 8001108: eefc 7ae7 vcvt.u32.f32 s15, s15 + 800110c: ee17 3a90 vmov r3, s15 + 8001110: b29a uxth r2, r3 + 8001112: 4b36 ldr r3, [pc, #216] @ (80011ec ) + 8001114: 809a strh r2, [r3, #4] current_measurements_adc_val.misc = adc_channels2.adcbank2.isense8 * CURR_SENSE_FACTOR_4_5A; - 80010fe: 4b3c ldr r3, [pc, #240] @ (80011f0 ) - 8001100: 885b ldrh r3, [r3, #2] - 8001102: b29b uxth r3, r3 - 8001104: ee07 3a90 vmov s15, r3 - 8001108: eef8 7ae7 vcvt.f32.s32 s15, s15 - 800110c: ed9f 7a33 vldr s14, [pc, #204] @ 80011dc - 8001110: ee67 7a87 vmul.f32 s15, s15, s14 - 8001114: eefc 7ae7 vcvt.u32.f32 s15, s15 - 8001118: ee17 3a90 vmov r3, s15 - 800111c: b29a uxth r2, r3 - 800111e: 4b2d ldr r3, [pc, #180] @ (80011d4 ) - 8001120: 81da strh r2, [r3, #14] + 8001116: 4b3c ldr r3, [pc, #240] @ (8001208 ) + 8001118: 885b ldrh r3, [r3, #2] + 800111a: b29b uxth r3, r3 + 800111c: ee07 3a90 vmov s15, r3 + 8001120: eef8 7ae7 vcvt.f32.s32 s15, s15 + 8001124: ed9f 7a33 vldr s14, [pc, #204] @ 80011f4 + 8001128: ee67 7a87 vmul.f32 s15, s15, s14 + 800112c: eefc 7ae7 vcvt.u32.f32 s15, s15 + 8001130: ee17 3a90 vmov r3, s15 + 8001134: b29a uxth r2, r3 + 8001136: 4b2d ldr r3, [pc, #180] @ (80011ec ) + 8001138: 81da strh r2, [r3, #14] current_measurements_adc_val.acu = adc_channels2.adcbank2.isense4 * CURR_SENSE_FACTOR_9A; - 8001122: 4b33 ldr r3, [pc, #204] @ (80011f0 ) - 8001124: 889b ldrh r3, [r3, #4] - 8001126: b29b uxth r3, r3 - 8001128: ee07 3a90 vmov s15, r3 - 800112c: eef8 7ae7 vcvt.f32.s32 s15, s15 - 8001130: ed9f 7a29 vldr s14, [pc, #164] @ 80011d8 - 8001134: ee67 7a87 vmul.f32 s15, s15, s14 - 8001138: eefc 7ae7 vcvt.u32.f32 s15, s15 - 800113c: ee17 3a90 vmov r3, s15 - 8001140: b29a uxth r2, r3 - 8001142: 4b24 ldr r3, [pc, #144] @ (80011d4 ) - 8001144: 80da strh r2, [r3, #6] + 800113a: 4b33 ldr r3, [pc, #204] @ (8001208 ) + 800113c: 889b ldrh r3, [r3, #4] + 800113e: b29b uxth r3, r3 + 8001140: ee07 3a90 vmov s15, r3 + 8001144: eef8 7ae7 vcvt.f32.s32 s15, s15 + 8001148: ed9f 7a29 vldr s14, [pc, #164] @ 80011f0 + 800114c: ee67 7a87 vmul.f32 s15, s15, s14 + 8001150: eefc 7ae7 vcvt.u32.f32 s15, s15 + 8001154: ee17 3a90 vmov r3, s15 + 8001158: b29a uxth r2, r3 + 800115a: 4b24 ldr r3, [pc, #144] @ (80011ec ) + 800115c: 80da strh r2, [r3, #6] current_measurements_adc_val.epsc = adc_channels2.adcbank2.isense5 * CURR_SENSE_FACTOR_9A; - 8001146: 4b2a ldr r3, [pc, #168] @ (80011f0 ) - 8001148: 88db ldrh r3, [r3, #6] - 800114a: b29b uxth r3, r3 - 800114c: ee07 3a90 vmov s15, r3 - 8001150: eef8 7ae7 vcvt.f32.s32 s15, s15 - 8001154: ed9f 7a20 vldr s14, [pc, #128] @ 80011d8 - 8001158: ee67 7a87 vmul.f32 s15, s15, s14 - 800115c: eefc 7ae7 vcvt.u32.f32 s15, s15 - 8001160: ee17 3a90 vmov r3, s15 - 8001164: b29a uxth r2, r3 - 8001166: 4b1b ldr r3, [pc, #108] @ (80011d4 ) - 8001168: 811a strh r2, [r3, #8] + 800115e: 4b2a ldr r3, [pc, #168] @ (8001208 ) + 8001160: 88db ldrh r3, [r3, #6] + 8001162: b29b uxth r3, r3 + 8001164: ee07 3a90 vmov s15, r3 + 8001168: eef8 7ae7 vcvt.f32.s32 s15, s15 + 800116c: ed9f 7a20 vldr s14, [pc, #128] @ 80011f0 + 8001170: ee67 7a87 vmul.f32 s15, s15, s14 + 8001174: eefc 7ae7 vcvt.u32.f32 s15, s15 + 8001178: ee17 3a90 vmov r3, s15 + 800117c: b29a uxth r2, r3 + 800117e: 4b1b ldr r3, [pc, #108] @ (80011ec ) + 8001180: 811a strh r2, [r3, #8] current_measurements_adc_val.epsc_precharge = adc_channels2.adcbank2.pc_read * LV_SENSE_FACTOR; - 800116a: 4b21 ldr r3, [pc, #132] @ (80011f0 ) - 800116c: 891b ldrh r3, [r3, #8] - 800116e: b29b uxth r3, r3 - 8001170: 4618 mov r0, r3 - 8001172: f7ff faa5 bl 80006c0 <__aeabi_i2d> - 8001176: a314 add r3, pc, #80 @ (adr r3, 80011c8 ) - 8001178: e9d3 2300 ldrd r2, r3, [r3] - 800117c: f7ff f824 bl 80001c8 <__aeabi_dmul> - 8001180: 4602 mov r2, r0 - 8001182: 460b mov r3, r1 - 8001184: 4610 mov r0, r2 - 8001186: 4619 mov r1, r3 - 8001188: f7ff fb04 bl 8000794 <__aeabi_d2uiz> - 800118c: 4603 mov r3, r0 - 800118e: b29a uxth r2, r3 - 8001190: 4b10 ldr r3, [pc, #64] @ (80011d4 ) - 8001192: 835a strh r2, [r3, #26] + 8001182: 4b21 ldr r3, [pc, #132] @ (8001208 ) + 8001184: 891b ldrh r3, [r3, #8] + 8001186: b29b uxth r3, r3 + 8001188: 4618 mov r0, r3 + 800118a: f7ff fa99 bl 80006c0 <__aeabi_i2d> + 800118e: a314 add r3, pc, #80 @ (adr r3, 80011e0 ) + 8001190: e9d3 2300 ldrd r2, r3, [r3] + 8001194: f7ff f818 bl 80001c8 <__aeabi_dmul> + 8001198: 4602 mov r2, r0 + 800119a: 460b mov r3, r1 + 800119c: 4610 mov r0, r2 + 800119e: 4619 mov r1, r3 + 80011a0: f7ff faf8 bl 8000794 <__aeabi_d2uiz> + 80011a4: 4603 mov r3, r0 + 80011a6: b29a uxth r2, r3 + 80011a8: 4b10 ldr r3, [pc, #64] @ (80011ec ) + 80011aa: 835a strh r2, [r3, #26] current_measurements_adc_val.lidar = adc_channels2.adcbank2.isense7 * CURR_SENSE_FACTOR_4_5A; - 8001194: 4b16 ldr r3, [pc, #88] @ (80011f0 ) - 8001196: 895b ldrh r3, [r3, #10] - 8001198: b29b uxth r3, r3 - 800119a: ee07 3a90 vmov s15, r3 - 800119e: eef8 7ae7 vcvt.f32.s32 s15, s15 - 80011a2: ed9f 7a0e vldr s14, [pc, #56] @ 80011dc - 80011a6: ee67 7a87 vmul.f32 s15, s15, s14 - 80011aa: eefc 7ae7 vcvt.u32.f32 s15, s15 - 80011ae: ee17 3a90 vmov r3, s15 - 80011b2: b29a uxth r2, r3 - 80011b4: 4b07 ldr r3, [pc, #28] @ (80011d4 ) - 80011b6: 819a strh r2, [r3, #12] + 80011ac: 4b16 ldr r3, [pc, #88] @ (8001208 ) + 80011ae: 895b ldrh r3, [r3, #10] + 80011b0: b29b uxth r3, r3 + 80011b2: ee07 3a90 vmov s15, r3 + 80011b6: eef8 7ae7 vcvt.f32.s32 s15, s15 + 80011ba: ed9f 7a0e vldr s14, [pc, #56] @ 80011f4 + 80011be: ee67 7a87 vmul.f32 s15, s15, s14 + 80011c2: eefc 7ae7 vcvt.u32.f32 s15, s15 + 80011c6: ee17 3a90 vmov r3, s15 + 80011ca: b29a uxth r2, r3 + 80011cc: 4b07 ldr r3, [pc, #28] @ (80011ec ) + 80011ce: 819a strh r2, [r3, #12] } check_plausibility(); - 80011b8: f000 fc36 bl 8001a28 + 80011d0: f000 fc3a bl 8001a48 } - 80011bc: bf00 nop - 80011be: 3708 adds r7, #8 - 80011c0: 46bd mov sp, r7 - 80011c2: bd80 pop {r7, pc} - 80011c4: f3af 8000 nop.w - 80011c8: 75800000 .word 0x75800000 - 80011cc: 4018b68b .word 0x4018b68b - 80011d0: 2000007c .word 0x2000007c - 80011d4: 20000098 .word 0x20000098 - 80011d8: 40279e79 .word 0x40279e79 - 80011dc: 3f9ab9ab .word 0x3f9ab9ab - 80011e0: 200000b9 .word 0x200000b9 - 80011e4: 48000400 .word 0x48000400 - 80011e8: 200000b8 .word 0x200000b8 - 80011ec: 200000c0 .word 0x200000c0 - 80011f0: 2000008c .word 0x2000008c + 80011d4: bf00 nop + 80011d6: 3708 adds r7, #8 + 80011d8: 46bd mov sp, r7 + 80011da: bd80 pop {r7, pc} + 80011dc: f3af 8000 nop.w + 80011e0: 8f000000 .word 0x8f000000 + 80011e4: 4019f8ea .word 0x4019f8ea + 80011e8: 2000007c .word 0x2000007c + 80011ec: 20000098 .word 0x20000098 + 80011f0: 403028fe .word 0x403028fe + 80011f4: 3fa29bff .word 0x3fa29bff + 80011f8: 200000b9 .word 0x200000b9 + 80011fc: 48000400 .word 0x48000400 + 8001200: 200000b8 .word 0x200000b8 + 8001204: 200000c0 .word 0x200000c0 + 8001208: 2000008c .word 0x2000008c -080011f4
: +0800120c
: /** * @brief The application entry point. * @retval int */ int main(void) { - 80011f4: b580 push {r7, lr} - 80011f6: b082 sub sp, #8 - 80011f8: af00 add r7, sp, #0 + 800120c: b580 push {r7, lr} + 800120e: b082 sub sp, #8 + 8001210: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); - 80011fa: f000 ffdb bl 80021b4 + 8001212: f001 f81d bl 8002250 /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); - 80011fe: f000 f8e1 bl 80013c4 + 8001216: f000 f8e5 bl 80013e4 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); - 8001202: f000 fb85 bl 8001910 + 800121a: f000 fb89 bl 8001930 MX_DMA_Init(); - 8001206: f000 fb51 bl 80018ac + 800121e: f000 fb55 bl 80018cc MX_ADC1_Init(); - 800120a: f000 f937 bl 800147c + 8001222: f000 f93b bl 800149c MX_ADC2_Init(); - 800120e: f000 fa09 bl 8001624 + 8001226: f000 fa0d bl 8001644 MX_CAN_Init(); - 8001212: f000 faad bl 8001770 + 800122a: f000 fab1 bl 8001790 MX_UART4_Init(); - 8001216: f000 fb19 bl 800184c + 800122e: f000 fb1d bl 800186c MX_TIM6_Init(); - 800121a: f000 fadf bl 80017dc + 8001232: f000 fae3 bl 80017fc /* USER CODE BEGIN 2 */ + // begin start-up animation HAL_GPIO_WritePin(LED1_GPIO_Port, LED1_Pin, GPIO_PIN_SET); - 800121e: 2201 movs r2, #1 - 8001220: f44f 7100 mov.w r1, #512 @ 0x200 - 8001224: 485d ldr r0, [pc, #372] @ (800139c ) - 8001226: f003 fc3d bl 8004aa4 + 8001236: 2201 movs r2, #1 + 8001238: f44f 7100 mov.w r1, #512 @ 0x200 + 800123c: 485f ldr r0, [pc, #380] @ (80013bc ) + 800123e: f003 fc7f bl 8004b40 HAL_Delay(100); - 800122a: 2064 movs r0, #100 @ 0x64 - 800122c: f001 f828 bl 8002280 + 8001242: 2064 movs r0, #100 @ 0x64 + 8001244: f001 f86a bl 800231c HAL_GPIO_WritePin(LED1_GPIO_Port, LED1_Pin, GPIO_PIN_RESET); - 8001230: 2200 movs r2, #0 - 8001232: f44f 7100 mov.w r1, #512 @ 0x200 - 8001236: 4859 ldr r0, [pc, #356] @ (800139c ) - 8001238: f003 fc34 bl 8004aa4 + 8001248: 2200 movs r2, #0 + 800124a: f44f 7100 mov.w r1, #512 @ 0x200 + 800124e: 485b ldr r0, [pc, #364] @ (80013bc ) + 8001250: f003 fc76 bl 8004b40 HAL_GPIO_WritePin(LED2_GPIO_Port, LED2_Pin, GPIO_PIN_SET); - 800123c: 2201 movs r2, #1 - 800123e: f44f 7180 mov.w r1, #256 @ 0x100 - 8001242: 4856 ldr r0, [pc, #344] @ (800139c ) - 8001244: f003 fc2e bl 8004aa4 + 8001254: 2201 movs r2, #1 + 8001256: f44f 7180 mov.w r1, #256 @ 0x100 + 800125a: 4858 ldr r0, [pc, #352] @ (80013bc ) + 800125c: f003 fc70 bl 8004b40 HAL_Delay(100); - 8001248: 2064 movs r0, #100 @ 0x64 - 800124a: f001 f819 bl 8002280 + 8001260: 2064 movs r0, #100 @ 0x64 + 8001262: f001 f85b bl 800231c HAL_GPIO_WritePin(LED2_GPIO_Port, LED2_Pin, GPIO_PIN_RESET); - 800124e: 2200 movs r2, #0 - 8001250: f44f 7180 mov.w r1, #256 @ 0x100 - 8001254: 4851 ldr r0, [pc, #324] @ (800139c ) - 8001256: f003 fc25 bl 8004aa4 + 8001266: 2200 movs r2, #0 + 8001268: f44f 7180 mov.w r1, #256 @ 0x100 + 800126c: 4853 ldr r0, [pc, #332] @ (80013bc ) + 800126e: f003 fc67 bl 8004b40 HAL_GPIO_WritePin(LED3_GPIO_Port, LED3_Pin, GPIO_PIN_SET); - 800125a: 2201 movs r2, #1 - 800125c: 2180 movs r1, #128 @ 0x80 - 800125e: 484f ldr r0, [pc, #316] @ (800139c ) - 8001260: f003 fc20 bl 8004aa4 + 8001272: 2201 movs r2, #1 + 8001274: 2180 movs r1, #128 @ 0x80 + 8001276: 4851 ldr r0, [pc, #324] @ (80013bc ) + 8001278: f003 fc62 bl 8004b40 HAL_Delay(100); - 8001264: 2064 movs r0, #100 @ 0x64 - 8001266: f001 f80b bl 8002280 + 800127c: 2064 movs r0, #100 @ 0x64 + 800127e: f001 f84d bl 800231c HAL_GPIO_WritePin(LED3_GPIO_Port, LED3_Pin, GPIO_PIN_RESET); - 800126a: 2200 movs r2, #0 - 800126c: 2180 movs r1, #128 @ 0x80 - 800126e: 484b ldr r0, [pc, #300] @ (800139c ) - 8001270: f003 fc18 bl 8004aa4 + 8001282: 2200 movs r2, #0 + 8001284: 2180 movs r1, #128 @ 0x80 + 8001286: 484d ldr r0, [pc, #308] @ (80013bc ) + 8001288: f003 fc5a bl 8004b40 HAL_GPIO_WritePin(LED4_GPIO_Port, LED4_Pin, GPIO_PIN_SET); - 8001274: 2201 movs r2, #1 - 8001276: 2140 movs r1, #64 @ 0x40 - 8001278: 4848 ldr r0, [pc, #288] @ (800139c ) - 800127a: f003 fc13 bl 8004aa4 + 800128c: 2201 movs r2, #1 + 800128e: 2140 movs r1, #64 @ 0x40 + 8001290: 484a ldr r0, [pc, #296] @ (80013bc ) + 8001292: f003 fc55 bl 8004b40 HAL_Delay(100); - 800127e: 2064 movs r0, #100 @ 0x64 - 8001280: f000 fffe bl 8002280 + 8001296: 2064 movs r0, #100 @ 0x64 + 8001298: f001 f840 bl 800231c HAL_GPIO_WritePin(LED4_GPIO_Port, LED3_Pin, GPIO_PIN_SET); - 8001284: 2201 movs r2, #1 - 8001286: 2180 movs r1, #128 @ 0x80 - 8001288: 4844 ldr r0, [pc, #272] @ (800139c ) - 800128a: f003 fc0b bl 8004aa4 + 800129c: 2201 movs r2, #1 + 800129e: 2180 movs r1, #128 @ 0x80 + 80012a0: 4846 ldr r0, [pc, #280] @ (80013bc ) + 80012a2: f003 fc4d bl 8004b40 HAL_Delay(100); - 800128e: 2064 movs r0, #100 @ 0x64 - 8001290: f000 fff6 bl 8002280 + 80012a6: 2064 movs r0, #100 @ 0x64 + 80012a8: f001 f838 bl 800231c HAL_GPIO_WritePin(LED2_GPIO_Port, LED2_Pin, GPIO_PIN_SET); - 8001294: 2201 movs r2, #1 - 8001296: f44f 7180 mov.w r1, #256 @ 0x100 - 800129a: 4840 ldr r0, [pc, #256] @ (800139c ) - 800129c: f003 fc02 bl 8004aa4 + 80012ac: 2201 movs r2, #1 + 80012ae: f44f 7180 mov.w r1, #256 @ 0x100 + 80012b2: 4842 ldr r0, [pc, #264] @ (80013bc ) + 80012b4: f003 fc44 bl 8004b40 HAL_Delay(100); - 80012a0: 2064 movs r0, #100 @ 0x64 - 80012a2: f000 ffed bl 8002280 + 80012b8: 2064 movs r0, #100 @ 0x64 + 80012ba: f001 f82f bl 800231c HAL_GPIO_WritePin(LED1_GPIO_Port, LED1_Pin, GPIO_PIN_SET); - 80012a6: 2201 movs r2, #1 - 80012a8: f44f 7100 mov.w r1, #512 @ 0x200 - 80012ac: 483b ldr r0, [pc, #236] @ (800139c ) - 80012ae: f003 fbf9 bl 8004aa4 + 80012be: 2201 movs r2, #1 + 80012c0: f44f 7100 mov.w r1, #512 @ 0x200 + 80012c4: 483d ldr r0, [pc, #244] @ (80013bc ) + 80012c6: f003 fc3b bl 8004b40 HAL_Delay(100); - 80012b2: 2064 movs r0, #100 @ 0x64 - 80012b4: f000 ffe4 bl 8002280 + 80012ca: 2064 movs r0, #100 @ 0x64 + 80012cc: f001 f826 bl 800231c HAL_GPIO_WritePin(LED1_GPIO_Port, LED1_Pin, GPIO_PIN_RESET); - 80012b8: 2200 movs r2, #0 - 80012ba: f44f 7100 mov.w r1, #512 @ 0x200 - 80012be: 4837 ldr r0, [pc, #220] @ (800139c ) - 80012c0: f003 fbf0 bl 8004aa4 - HAL_GPIO_WritePin(LED2_GPIO_Port, LED2_Pin, GPIO_PIN_RESET); - 80012c4: 2200 movs r2, #0 - 80012c6: f44f 7180 mov.w r1, #256 @ 0x100 - 80012ca: 4834 ldr r0, [pc, #208] @ (800139c ) - 80012cc: f003 fbea bl 8004aa4 - HAL_GPIO_WritePin(LED3_GPIO_Port, LED3_Pin, GPIO_PIN_RESET); 80012d0: 2200 movs r2, #0 - 80012d2: 2180 movs r1, #128 @ 0x80 - 80012d4: 4831 ldr r0, [pc, #196] @ (800139c ) - 80012d6: f003 fbe5 bl 8004aa4 + 80012d2: f44f 7100 mov.w r1, #512 @ 0x200 + 80012d6: 4839 ldr r0, [pc, #228] @ (80013bc ) + 80012d8: f003 fc32 bl 8004b40 + HAL_GPIO_WritePin(LED2_GPIO_Port, LED2_Pin, GPIO_PIN_RESET); + 80012dc: 2200 movs r2, #0 + 80012de: f44f 7180 mov.w r1, #256 @ 0x100 + 80012e2: 4836 ldr r0, [pc, #216] @ (80013bc ) + 80012e4: f003 fc2c bl 8004b40 + HAL_GPIO_WritePin(LED3_GPIO_Port, LED3_Pin, GPIO_PIN_RESET); + 80012e8: 2200 movs r2, #0 + 80012ea: 2180 movs r1, #128 @ 0x80 + 80012ec: 4833 ldr r0, [pc, #204] @ (80013bc ) + 80012ee: f003 fc27 bl 8004b40 HAL_GPIO_WritePin(LED4_GPIO_Port, LED4_Pin, GPIO_PIN_RESET); - 80012da: 2200 movs r2, #0 - 80012dc: 2140 movs r1, #64 @ 0x40 - 80012de: 482f ldr r0, [pc, #188] @ (800139c ) - 80012e0: f003 fbe0 bl 8004aa4 + 80012f2: 2200 movs r2, #0 + 80012f4: 2140 movs r1, #64 @ 0x40 + 80012f6: 4831 ldr r0, [pc, #196] @ (80013bc ) + 80012f8: f003 fc22 bl 8004b40 // end start-up animation + HAL_GPIO_WritePin(LED4_GPIO_Port, LED4_Pin, GPIO_PIN_SET); // indicates running STM - 80012e4: 2201 movs r2, #1 - 80012e6: 2140 movs r1, #64 @ 0x40 - 80012e8: 482c ldr r0, [pc, #176] @ (800139c ) - 80012ea: f003 fbdb bl 8004aa4 + 80012fc: 2201 movs r2, #1 + 80012fe: 2140 movs r1, #64 @ 0x40 + 8001300: 482e ldr r0, [pc, #184] @ (80013bc ) + 8001302: f003 fc1d bl 8004b40 ChannelControl_init(); - 80012ee: f7ff fc81 bl 8000bf4 + 8001306: f7ff fc8b bl 8000c20 can_init(&hcan); - 80012f2: 482b ldr r0, [pc, #172] @ (80013a0 ) - 80012f4: f7ff fa6e bl 80007d4 + 800130a: 482d ldr r0, [pc, #180] @ (80013c0 ) + 800130c: f7ff fa62 bl 80007d4 current_monitor_init(&hadc1, &hadc2, &htim6); - 80012f8: 4a2a ldr r2, [pc, #168] @ (80013a4 ) - 80012fa: 492b ldr r1, [pc, #172] @ (80013a8 ) - 80012fc: 482b ldr r0, [pc, #172] @ (80013ac ) - 80012fe: f7ff fd9f bl 8000e40 + 8001310: 4a2c ldr r2, [pc, #176] @ (80013c4 ) + 8001312: 492d ldr r1, [pc, #180] @ (80013c8 ) + 8001314: 482d ldr r0, [pc, #180] @ (80013cc ) + 8001316: f7ff fd9f bl 8000e58 uint32_t lasttick = HAL_GetTick(); // Zeit in ms seit Start - 8001302: f000 ffb1 bl 8002268 - 8001306: 6078 str r0, [r7, #4] + 800131a: f000 fff3 bl 8002304 + 800131e: 6078 str r0, [r7, #4] inhibit_SDC = 0; - 8001308: 4b29 ldr r3, [pc, #164] @ (80013b0 ) - 800130a: 2200 movs r2, #0 - 800130c: 601a str r2, [r3, #0] + 8001320: 4b2b ldr r3, [pc, #172] @ (80013d0 ) + 8001322: 2200 movs r2, #0 + 8001324: 601a str r2, [r3, #0] while (1) { /* USER CODE END WHILE */ /* USER CODE BEGIN 3 */ if (canmsg_received){ - 800130e: 4b29 ldr r3, [pc, #164] @ (80013b4 ) - 8001310: 781b ldrb r3, [r3, #0] - 8001312: b2db uxtb r3, r3 - 8001314: 2b00 cmp r3, #0 - 8001316: d006 beq.n 8001326 + 8001326: 4b2b ldr r3, [pc, #172] @ (80013d4 ) + 8001328: 781b ldrb r3, [r3, #0] + 800132a: b2db uxtb r3, r3 + 800132c: 2b00 cmp r3, #0 + 800132e: d006 beq.n 800133e canmsg_received = 0; - 8001318: 4b26 ldr r3, [pc, #152] @ (80013b4 ) - 800131a: 2200 movs r2, #0 - 800131c: 701a strb r2, [r3, #0] + 8001330: 4b28 ldr r3, [pc, #160] @ (80013d4 ) + 8001332: 2200 movs r2, #0 + 8001334: 701a strb r2, [r3, #0] update_ports = rxstate.iostatus; - 800131e: 4a26 ldr r2, [pc, #152] @ (80013b8 ) - 8001320: 4b26 ldr r3, [pc, #152] @ (80013bc ) - 8001322: 881b ldrh r3, [r3, #0] - 8001324: 8013 strh r3, [r2, #0] + 8001336: 4a28 ldr r2, [pc, #160] @ (80013d8 ) + 8001338: 4b28 ldr r3, [pc, #160] @ (80013dc ) + 800133a: 881b ldrh r3, [r3, #0] + 800133c: 8013 strh r3, [r2, #0] } if ((HAL_GetTick() - lasttick) > 100u){ - 8001326: f000 ff9f bl 8002268 - 800132a: 4602 mov r2, r0 - 800132c: 687b ldr r3, [r7, #4] - 800132e: 1ad3 subs r3, r2, r3 - 8001330: 2b64 cmp r3, #100 @ 0x64 - 8001332: d904 bls.n 800133e + 800133e: f000 ffe1 bl 8002304 + 8001342: 4602 mov r2, r0 + 8001344: 687b ldr r3, [r7, #4] + 8001346: 1ad3 subs r3, r2, r3 + 8001348: 2b64 cmp r3, #100 @ 0x64 + 800134a: d908 bls.n 800135e lasttick = HAL_GetTick(); - 8001334: f000 ff98 bl 8002268 - 8001338: 6078 str r0, [r7, #4] + 800134c: f000 ffda bl 8002304 + 8001350: 6078 str r0, [r7, #4] + check_plausibility(); + 8001352: f000 fb79 bl 8001a48 can_sendloop(); - 800133a: f7ff fa5b bl 80007f4 - //can_error_report(); + 8001356: f7ff fa4d bl 80007f4 + can_error_report(); + 800135a: f7ff fb49 bl 80009f0 } if (((HAL_GetTick() - lastheartbeat) > 200U) && (HAL_GetTick() > 1000U)) { - 800133e: f000 ff93 bl 8002268 - 8001342: 4602 mov r2, r0 - 8001344: 4b1e ldr r3, [pc, #120] @ (80013c0 ) - 8001346: 681b ldr r3, [r3, #0] - 8001348: 1ad3 subs r3, r2, r3 - 800134a: 2bc8 cmp r3, #200 @ 0xc8 - 800134c: d908 bls.n 8001360 - 800134e: f000 ff8b bl 8002268 - 8001352: 4603 mov r3, r0 - 8001354: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 - 8001358: d902 bls.n 8001360 + 800135e: f000 ffd1 bl 8002304 + 8001362: 4602 mov r2, r0 + 8001364: 4b1e ldr r3, [pc, #120] @ (80013e0 ) + 8001366: 681b ldr r3, [r3, #0] + 8001368: 1ad3 subs r3, r2, r3 + 800136a: 2bc8 cmp r3, #200 @ 0xc8 + 800136c: d908 bls.n 8001380 + 800136e: f000 ffc9 bl 8002304 + 8001372: 4603 mov r3, r0 + 8001374: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 + 8001378: d902 bls.n 8001380 inhibit_SDC = 1; - 800135a: 4b15 ldr r3, [pc, #84] @ (80013b0 ) - 800135c: 2201 movs r2, #1 - 800135e: 601a str r2, [r3, #0] + 800137a: 4b15 ldr r3, [pc, #84] @ (80013d0 ) + 800137c: 2201 movs r2, #1 + 800137e: 601a str r2, [r3, #0] } HAL_GPIO_WritePin(LED1_GPIO_Port, LED1_Pin, (GPIO_PinState)!update_ports.portb.sdc); // indicates open SDC - 8001360: 4b15 ldr r3, [pc, #84] @ (80013b8 ) - 8001362: 785b ldrb r3, [r3, #1] - 8001364: f3c3 0340 ubfx r3, r3, #1, #1 - 8001368: b2db uxtb r3, r3 - 800136a: f083 0301 eor.w r3, r3, #1 - 800136e: b2db uxtb r3, r3 - 8001370: 461a mov r2, r3 - 8001372: f44f 7100 mov.w r1, #512 @ 0x200 - 8001376: 4809 ldr r0, [pc, #36] @ (800139c ) - 8001378: f003 fb94 bl 8004aa4 + 8001380: 4b15 ldr r3, [pc, #84] @ (80013d8 ) + 8001382: 785b ldrb r3, [r3, #1] + 8001384: f3c3 0340 ubfx r3, r3, #1, #1 + 8001388: b2db uxtb r3, r3 + 800138a: f083 0301 eor.w r3, r3, #1 + 800138e: b2db uxtb r3, r3 + 8001390: 461a mov r2, r3 + 8001392: f44f 7100 mov.w r1, #512 @ 0x200 + 8001396: 4809 ldr r0, [pc, #36] @ (80013bc ) + 8001398: f003 fbd2 bl 8004b40 HAL_GPIO_WritePin(LED2_GPIO_Port, LED2_Pin, (GPIO_PinState)inhibit_SDC); // indicates watchdog-status - 800137c: 4b0c ldr r3, [pc, #48] @ (80013b0 ) - 800137e: 681b ldr r3, [r3, #0] - 8001380: b2db uxtb r3, r3 - 8001382: 461a mov r2, r3 - 8001384: f44f 7180 mov.w r1, #256 @ 0x100 - 8001388: 4804 ldr r0, [pc, #16] @ (800139c ) - 800138a: f003 fb8b bl 8004aa4 - // overcurrent check (wenn funktioniert, LED schalten) + 800139c: 4b0c ldr r3, [pc, #48] @ (80013d0 ) + 800139e: 681b ldr r3, [r3, #0] + 80013a0: b2db uxtb r3, r3 + 80013a2: 461a mov r2, r3 + 80013a4: f44f 7180 mov.w r1, #256 @ 0x100 + 80013a8: 4804 ldr r0, [pc, #16] @ (80013bc ) + 80013aa: f003 fbc9 bl 8004b40 + ChannelControl_UpdateGPIOs(update_ports); - 800138e: 4b0a ldr r3, [pc, #40] @ (80013b8 ) - 8001390: 8818 ldrh r0, [r3, #0] - 8001392: f7ff fc49 bl 8000c28 + 80013ae: 4b0a ldr r3, [pc, #40] @ (80013d8 ) + 80013b0: 8818 ldrh r0, [r3, #0] + 80013b2: f7ff fc4f bl 8000c54 current_monitor_checklimits(); // currently not implemented - 8001396: f7ff fd8d bl 8000eb4 + 80013b6: f7ff fd89 bl 8000ecc if (canmsg_received){ - 800139a: e7b8 b.n 800130e - 800139c: 48000800 .word 0x48000800 - 80013a0: 200001ec .word 0x200001ec - 80013a4: 20000214 .word 0x20000214 - 80013a8: 20000114 .word 0x20000114 - 80013ac: 200000c4 .word 0x200000c4 - 80013b0: 200002f0 .word 0x200002f0 - 80013b4: 2000002c .word 0x2000002c - 80013b8: 200002e8 .word 0x200002e8 - 80013bc: 20000028 .word 0x20000028 - 80013c0: 200002ec .word 0x200002ec + 80013ba: e7b4 b.n 8001326 + 80013bc: 48000800 .word 0x48000800 + 80013c0: 200001ec .word 0x200001ec + 80013c4: 20000214 .word 0x20000214 + 80013c8: 20000114 .word 0x20000114 + 80013cc: 200000c4 .word 0x200000c4 + 80013d0: 200002f0 .word 0x200002f0 + 80013d4: 2000002c .word 0x2000002c + 80013d8: 200002e8 .word 0x200002e8 + 80013dc: 20000028 .word 0x20000028 + 80013e0: 200002ec .word 0x200002ec -080013c4 : +080013e4 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { - 80013c4: b580 push {r7, lr} - 80013c6: b09c sub sp, #112 @ 0x70 - 80013c8: af00 add r7, sp, #0 + 80013e4: b580 push {r7, lr} + 80013e6: b09c sub sp, #112 @ 0x70 + 80013e8: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; - 80013ca: f107 0348 add.w r3, r7, #72 @ 0x48 - 80013ce: 2228 movs r2, #40 @ 0x28 - 80013d0: 2100 movs r1, #0 - 80013d2: 4618 mov r0, r3 - 80013d4: f005 feb3 bl 800713e + 80013ea: f107 0348 add.w r3, r7, #72 @ 0x48 + 80013ee: 2228 movs r2, #40 @ 0x28 + 80013f0: 2100 movs r1, #0 + 80013f2: 4618 mov r0, r3 + 80013f4: f005 fef1 bl 80071da RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - 80013d8: f107 0334 add.w r3, r7, #52 @ 0x34 - 80013dc: 2200 movs r2, #0 - 80013de: 601a str r2, [r3, #0] - 80013e0: 605a str r2, [r3, #4] - 80013e2: 609a str r2, [r3, #8] - 80013e4: 60da str r2, [r3, #12] - 80013e6: 611a str r2, [r3, #16] + 80013f8: f107 0334 add.w r3, r7, #52 @ 0x34 + 80013fc: 2200 movs r2, #0 + 80013fe: 601a str r2, [r3, #0] + 8001400: 605a str r2, [r3, #4] + 8001402: 609a str r2, [r3, #8] + 8001404: 60da str r2, [r3, #12] + 8001406: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - 80013e8: 463b mov r3, r7 - 80013ea: 2234 movs r2, #52 @ 0x34 - 80013ec: 2100 movs r1, #0 - 80013ee: 4618 mov r0, r3 - 80013f0: f005 fea5 bl 800713e + 8001408: 463b mov r3, r7 + 800140a: 2234 movs r2, #52 @ 0x34 + 800140c: 2100 movs r1, #0 + 800140e: 4618 mov r0, r3 + 8001410: f005 fee3 bl 80071da /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; - 80013f4: 2301 movs r3, #1 - 80013f6: 64bb str r3, [r7, #72] @ 0x48 + 8001414: 2301 movs r3, #1 + 8001416: 64bb str r3, [r7, #72] @ 0x48 RCC_OscInitStruct.HSEState = RCC_HSE_ON; - 80013f8: f44f 3380 mov.w r3, #65536 @ 0x10000 - 80013fc: 64fb str r3, [r7, #76] @ 0x4c + 8001418: f44f 3380 mov.w r3, #65536 @ 0x10000 + 800141c: 64fb str r3, [r7, #76] @ 0x4c RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1; - 80013fe: 2300 movs r3, #0 - 8001400: 653b str r3, [r7, #80] @ 0x50 + 800141e: 2300 movs r3, #0 + 8001420: 653b str r3, [r7, #80] @ 0x50 RCC_OscInitStruct.HSIState = RCC_HSI_ON; - 8001402: 2301 movs r3, #1 - 8001404: 65bb str r3, [r7, #88] @ 0x58 + 8001422: 2301 movs r3, #1 + 8001424: 65bb str r3, [r7, #88] @ 0x58 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - 8001406: 2302 movs r3, #2 - 8001408: 667b str r3, [r7, #100] @ 0x64 + 8001426: 2302 movs r3, #2 + 8001428: 667b str r3, [r7, #100] @ 0x64 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - 800140a: f44f 3380 mov.w r3, #65536 @ 0x10000 - 800140e: 66bb str r3, [r7, #104] @ 0x68 + 800142a: f44f 3380 mov.w r3, #65536 @ 0x10000 + 800142e: 66bb str r3, [r7, #104] @ 0x68 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL4; - 8001410: f44f 2300 mov.w r3, #524288 @ 0x80000 - 8001414: 66fb str r3, [r7, #108] @ 0x6c + 8001430: f44f 2300 mov.w r3, #524288 @ 0x80000 + 8001434: 66fb str r3, [r7, #108] @ 0x6c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) - 8001416: f107 0348 add.w r3, r7, #72 @ 0x48 - 800141a: 4618 mov r0, r3 - 800141c: f003 fb5a bl 8004ad4 - 8001420: 4603 mov r3, r0 - 8001422: 2b00 cmp r3, #0 - 8001424: d001 beq.n 800142a + 8001436: f107 0348 add.w r3, r7, #72 @ 0x48 + 800143a: 4618 mov r0, r3 + 800143c: f003 fb98 bl 8004b70 + 8001440: 4603 mov r3, r0 + 8001442: 2b00 cmp r3, #0 + 8001444: d001 beq.n 800144a { Error_Handler(); - 8001426: f000 faf9 bl 8001a1c + 8001446: f000 faf9 bl 8001a3c } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK - 800142a: 230f movs r3, #15 - 800142c: 637b str r3, [r7, #52] @ 0x34 + 800144a: 230f movs r3, #15 + 800144c: 637b str r3, [r7, #52] @ 0x34 |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE; - 800142e: 2301 movs r3, #1 - 8001430: 63bb str r3, [r7, #56] @ 0x38 + 800144e: 2301 movs r3, #1 + 8001450: 63bb str r3, [r7, #56] @ 0x38 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - 8001432: 2300 movs r3, #0 - 8001434: 63fb str r3, [r7, #60] @ 0x3c + 8001452: 2300 movs r3, #0 + 8001454: 63fb str r3, [r7, #60] @ 0x3c RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; - 8001436: 2300 movs r3, #0 - 8001438: 643b str r3, [r7, #64] @ 0x40 + 8001456: 2300 movs r3, #0 + 8001458: 643b str r3, [r7, #64] @ 0x40 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; - 800143a: 2300 movs r3, #0 - 800143c: 647b str r3, [r7, #68] @ 0x44 + 800145a: 2300 movs r3, #0 + 800145c: 647b str r3, [r7, #68] @ 0x44 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) - 800143e: f107 0334 add.w r3, r7, #52 @ 0x34 - 8001442: 2100 movs r1, #0 - 8001444: 4618 mov r0, r3 - 8001446: f004 fb83 bl 8005b50 - 800144a: 4603 mov r3, r0 - 800144c: 2b00 cmp r3, #0 - 800144e: d001 beq.n 8001454 - { - Error_Handler(); - 8001450: f000 fae4 bl 8001a1c - } - PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_UART4|RCC_PERIPHCLK_ADC12; - 8001454: 2388 movs r3, #136 @ 0x88 - 8001456: 603b str r3, [r7, #0] - PeriphClkInit.Uart4ClockSelection = RCC_UART4CLKSOURCE_PCLK1; - 8001458: 2300 movs r3, #0 - 800145a: 617b str r3, [r7, #20] - PeriphClkInit.Adc12ClockSelection = RCC_ADC12PLLCLK_DIV1; - 800145c: f44f 7380 mov.w r3, #256 @ 0x100 - 8001460: 627b str r3, [r7, #36] @ 0x24 - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) - 8001462: 463b mov r3, r7 + 800145e: f107 0334 add.w r3, r7, #52 @ 0x34 + 8001462: 2100 movs r1, #0 8001464: 4618 mov r0, r3 - 8001466: f004 fd95 bl 8005f94 + 8001466: f004 fbc1 bl 8005bec 800146a: 4603 mov r3, r0 800146c: 2b00 cmp r3, #0 - 800146e: d001 beq.n 8001474 + 800146e: d001 beq.n 8001474 { Error_Handler(); - 8001470: f000 fad4 bl 8001a1c + 8001470: f000 fae4 bl 8001a3c + } + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_UART4|RCC_PERIPHCLK_ADC12; + 8001474: 2388 movs r3, #136 @ 0x88 + 8001476: 603b str r3, [r7, #0] + PeriphClkInit.Uart4ClockSelection = RCC_UART4CLKSOURCE_PCLK1; + 8001478: 2300 movs r3, #0 + 800147a: 617b str r3, [r7, #20] + PeriphClkInit.Adc12ClockSelection = RCC_ADC12PLLCLK_DIV1; + 800147c: f44f 7380 mov.w r3, #256 @ 0x100 + 8001480: 627b str r3, [r7, #36] @ 0x24 + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + 8001482: 463b mov r3, r7 + 8001484: 4618 mov r0, r3 + 8001486: f004 fdd3 bl 8006030 + 800148a: 4603 mov r3, r0 + 800148c: 2b00 cmp r3, #0 + 800148e: d001 beq.n 8001494 + { + Error_Handler(); + 8001490: f000 fad4 bl 8001a3c } } - 8001474: bf00 nop - 8001476: 3770 adds r7, #112 @ 0x70 - 8001478: 46bd mov sp, r7 - 800147a: bd80 pop {r7, pc} + 8001494: bf00 nop + 8001496: 3770 adds r7, #112 @ 0x70 + 8001498: 46bd mov sp, r7 + 800149a: bd80 pop {r7, pc} -0800147c : +0800149c : * @brief ADC1 Initialization Function * @param None * @retval None */ static void MX_ADC1_Init(void) { - 800147c: b580 push {r7, lr} - 800147e: b08a sub sp, #40 @ 0x28 - 8001480: af00 add r7, sp, #0 + 800149c: b580 push {r7, lr} + 800149e: b08a sub sp, #40 @ 0x28 + 80014a0: af00 add r7, sp, #0 /* USER CODE BEGIN ADC1_Init 0 */ /* USER CODE END ADC1_Init 0 */ ADC_MultiModeTypeDef multimode = {0}; - 8001482: f107 031c add.w r3, r7, #28 - 8001486: 2200 movs r2, #0 - 8001488: 601a str r2, [r3, #0] - 800148a: 605a str r2, [r3, #4] - 800148c: 609a str r2, [r3, #8] + 80014a2: f107 031c add.w r3, r7, #28 + 80014a6: 2200 movs r2, #0 + 80014a8: 601a str r2, [r3, #0] + 80014aa: 605a str r2, [r3, #4] + 80014ac: 609a str r2, [r3, #8] ADC_ChannelConfTypeDef sConfig = {0}; - 800148e: 1d3b adds r3, r7, #4 - 8001490: 2200 movs r2, #0 - 8001492: 601a str r2, [r3, #0] - 8001494: 605a str r2, [r3, #4] - 8001496: 609a str r2, [r3, #8] - 8001498: 60da str r2, [r3, #12] - 800149a: 611a str r2, [r3, #16] - 800149c: 615a str r2, [r3, #20] + 80014ae: 1d3b adds r3, r7, #4 + 80014b0: 2200 movs r2, #0 + 80014b2: 601a str r2, [r3, #0] + 80014b4: 605a str r2, [r3, #4] + 80014b6: 609a str r2, [r3, #8] + 80014b8: 60da str r2, [r3, #12] + 80014ba: 611a str r2, [r3, #16] + 80014bc: 615a str r2, [r3, #20] /* USER CODE END ADC1_Init 1 */ /** Common config */ hadc1.Instance = ADC1; - 800149e: 4b60 ldr r3, [pc, #384] @ (8001620 ) - 80014a0: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 - 80014a4: 601a str r2, [r3, #0] + 80014be: 4b60 ldr r3, [pc, #384] @ (8001640 ) + 80014c0: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 + 80014c4: 601a str r2, [r3, #0] hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1; - 80014a6: 4b5e ldr r3, [pc, #376] @ (8001620 ) - 80014a8: 2200 movs r2, #0 - 80014aa: 605a str r2, [r3, #4] + 80014c6: 4b5e ldr r3, [pc, #376] @ (8001640 ) + 80014c8: 2200 movs r2, #0 + 80014ca: 605a str r2, [r3, #4] hadc1.Init.Resolution = ADC_RESOLUTION_12B; - 80014ac: 4b5c ldr r3, [pc, #368] @ (8001620 ) - 80014ae: 2200 movs r2, #0 - 80014b0: 609a str r2, [r3, #8] + 80014cc: 4b5c ldr r3, [pc, #368] @ (8001640 ) + 80014ce: 2200 movs r2, #0 + 80014d0: 609a str r2, [r3, #8] hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE; - 80014b2: 4b5b ldr r3, [pc, #364] @ (8001620 ) - 80014b4: 2201 movs r2, #1 - 80014b6: 611a str r2, [r3, #16] + 80014d2: 4b5b ldr r3, [pc, #364] @ (8001640 ) + 80014d4: 2201 movs r2, #1 + 80014d6: 611a str r2, [r3, #16] hadc1.Init.ContinuousConvMode = DISABLE; - 80014b8: 4b59 ldr r3, [pc, #356] @ (8001620 ) - 80014ba: 2200 movs r2, #0 - 80014bc: 765a strb r2, [r3, #25] + 80014d8: 4b59 ldr r3, [pc, #356] @ (8001640 ) + 80014da: 2200 movs r2, #0 + 80014dc: 765a strb r2, [r3, #25] hadc1.Init.DiscontinuousConvMode = DISABLE; - 80014be: 4b58 ldr r3, [pc, #352] @ (8001620 ) - 80014c0: 2200 movs r2, #0 - 80014c2: f883 2020 strb.w r2, [r3, #32] + 80014de: 4b58 ldr r3, [pc, #352] @ (8001640 ) + 80014e0: 2200 movs r2, #0 + 80014e2: f883 2020 strb.w r2, [r3, #32] hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; - 80014c6: 4b56 ldr r3, [pc, #344] @ (8001620 ) - 80014c8: f44f 6280 mov.w r2, #1024 @ 0x400 - 80014cc: 62da str r2, [r3, #44] @ 0x2c + 80014e6: 4b56 ldr r3, [pc, #344] @ (8001640 ) + 80014e8: f44f 6280 mov.w r2, #1024 @ 0x400 + 80014ec: 62da str r2, [r3, #44] @ 0x2c hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_T6_TRGO; - 80014ce: 4b54 ldr r3, [pc, #336] @ (8001620 ) - 80014d0: f44f 7250 mov.w r2, #832 @ 0x340 - 80014d4: 629a str r2, [r3, #40] @ 0x28 + 80014ee: 4b54 ldr r3, [pc, #336] @ (8001640 ) + 80014f0: f44f 7250 mov.w r2, #832 @ 0x340 + 80014f4: 629a str r2, [r3, #40] @ 0x28 hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; - 80014d6: 4b52 ldr r3, [pc, #328] @ (8001620 ) - 80014d8: 2200 movs r2, #0 - 80014da: 60da str r2, [r3, #12] - hadc1.Init.NbrOfConversion = 8; - 80014dc: 4b50 ldr r3, [pc, #320] @ (8001620 ) - 80014de: 2208 movs r2, #8 - 80014e0: 61da str r2, [r3, #28] - hadc1.Init.DMAContinuousRequests = ENABLE; - 80014e2: 4b4f ldr r3, [pc, #316] @ (8001620 ) - 80014e4: 2201 movs r2, #1 - 80014e6: f883 2030 strb.w r2, [r3, #48] @ 0x30 - hadc1.Init.EOCSelection = ADC_EOC_SEQ_CONV; - 80014ea: 4b4d ldr r3, [pc, #308] @ (8001620 ) - 80014ec: 2208 movs r2, #8 - 80014ee: 615a str r2, [r3, #20] - hadc1.Init.LowPowerAutoWait = DISABLE; - 80014f0: 4b4b ldr r3, [pc, #300] @ (8001620 ) - 80014f2: 2200 movs r2, #0 - 80014f4: 761a strb r2, [r3, #24] - hadc1.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN; - 80014f6: 4b4a ldr r3, [pc, #296] @ (8001620 ) + 80014f6: 4b52 ldr r3, [pc, #328] @ (8001640 ) 80014f8: 2200 movs r2, #0 - 80014fa: 635a str r2, [r3, #52] @ 0x34 + 80014fa: 60da str r2, [r3, #12] + hadc1.Init.NbrOfConversion = 8; + 80014fc: 4b50 ldr r3, [pc, #320] @ (8001640 ) + 80014fe: 2208 movs r2, #8 + 8001500: 61da str r2, [r3, #28] + hadc1.Init.DMAContinuousRequests = ENABLE; + 8001502: 4b4f ldr r3, [pc, #316] @ (8001640 ) + 8001504: 2201 movs r2, #1 + 8001506: f883 2030 strb.w r2, [r3, #48] @ 0x30 + hadc1.Init.EOCSelection = ADC_EOC_SEQ_CONV; + 800150a: 4b4d ldr r3, [pc, #308] @ (8001640 ) + 800150c: 2208 movs r2, #8 + 800150e: 615a str r2, [r3, #20] + hadc1.Init.LowPowerAutoWait = DISABLE; + 8001510: 4b4b ldr r3, [pc, #300] @ (8001640 ) + 8001512: 2200 movs r2, #0 + 8001514: 761a strb r2, [r3, #24] + hadc1.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN; + 8001516: 4b4a ldr r3, [pc, #296] @ (8001640 ) + 8001518: 2200 movs r2, #0 + 800151a: 635a str r2, [r3, #52] @ 0x34 if (HAL_ADC_Init(&hadc1) != HAL_OK) - 80014fc: 4848 ldr r0, [pc, #288] @ (8001620 ) - 80014fe: f000 ff01 bl 8002304 - 8001502: 4603 mov r3, r0 - 8001504: 2b00 cmp r3, #0 - 8001506: d001 beq.n 800150c + 800151c: 4848 ldr r0, [pc, #288] @ (8001640 ) + 800151e: f000 ff3f bl 80023a0 + 8001522: 4603 mov r3, r0 + 8001524: 2b00 cmp r3, #0 + 8001526: d001 beq.n 800152c { Error_Handler(); - 8001508: f000 fa88 bl 8001a1c + 8001528: f000 fa88 bl 8001a3c } /** Configure the ADC multi-mode */ multimode.Mode = ADC_MODE_INDEPENDENT; - 800150c: 2300 movs r3, #0 - 800150e: 61fb str r3, [r7, #28] + 800152c: 2300 movs r3, #0 + 800152e: 61fb str r3, [r7, #28] if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK) - 8001510: f107 031c add.w r3, r7, #28 - 8001514: 4619 mov r1, r3 - 8001516: 4842 ldr r0, [pc, #264] @ (8001620 ) - 8001518: f001 fe40 bl 800319c - 800151c: 4603 mov r3, r0 - 800151e: 2b00 cmp r3, #0 - 8001520: d001 beq.n 8001526 + 8001530: f107 031c add.w r3, r7, #28 + 8001534: 4619 mov r1, r3 + 8001536: 4842 ldr r0, [pc, #264] @ (8001640 ) + 8001538: f001 fe7e bl 8003238 + 800153c: 4603 mov r3, r0 + 800153e: 2b00 cmp r3, #0 + 8001540: d001 beq.n 8001546 { Error_Handler(); - 8001522: f000 fa7b bl 8001a1c + 8001542: f000 fa7b bl 8001a3c } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_5; - 8001526: 2305 movs r3, #5 - 8001528: 607b str r3, [r7, #4] + 8001546: 2305 movs r3, #5 + 8001548: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_1; - 800152a: 2301 movs r3, #1 - 800152c: 60bb str r3, [r7, #8] + 800154a: 2301 movs r3, #1 + 800154c: 60bb str r3, [r7, #8] sConfig.SingleDiff = ADC_SINGLE_ENDED; - 800152e: 2300 movs r3, #0 - 8001530: 613b str r3, [r7, #16] + 800154e: 2300 movs r3, #0 + 8001550: 613b str r3, [r7, #16] sConfig.SamplingTime = ADC_SAMPLETIME_61CYCLES_5; - 8001532: 2305 movs r3, #5 - 8001534: 60fb str r3, [r7, #12] + 8001552: 2305 movs r3, #5 + 8001554: 60fb str r3, [r7, #12] sConfig.OffsetNumber = ADC_OFFSET_NONE; - 8001536: 2300 movs r3, #0 - 8001538: 617b str r3, [r7, #20] + 8001556: 2300 movs r3, #0 + 8001558: 617b str r3, [r7, #20] sConfig.Offset = 0; - 800153a: 2300 movs r3, #0 - 800153c: 61bb str r3, [r7, #24] + 800155a: 2300 movs r3, #0 + 800155c: 61bb str r3, [r7, #24] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) - 800153e: 1d3b adds r3, r7, #4 - 8001540: 4619 mov r1, r3 - 8001542: 4837 ldr r0, [pc, #220] @ (8001620 ) - 8001544: f001 fb6c bl 8002c20 - 8001548: 4603 mov r3, r0 - 800154a: 2b00 cmp r3, #0 - 800154c: d001 beq.n 8001552 + 800155e: 1d3b adds r3, r7, #4 + 8001560: 4619 mov r1, r3 + 8001562: 4837 ldr r0, [pc, #220] @ (8001640 ) + 8001564: f001 fbaa bl 8002cbc + 8001568: 4603 mov r3, r0 + 800156a: 2b00 cmp r3, #0 + 800156c: d001 beq.n 8001572 { Error_Handler(); - 800154e: f000 fa65 bl 8001a1c + 800156e: f000 fa65 bl 8001a3c } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_6; - 8001552: 2306 movs r3, #6 - 8001554: 607b str r3, [r7, #4] + 8001572: 2306 movs r3, #6 + 8001574: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_2; - 8001556: 2302 movs r3, #2 - 8001558: 60bb str r3, [r7, #8] + 8001576: 2302 movs r3, #2 + 8001578: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) - 800155a: 1d3b adds r3, r7, #4 - 800155c: 4619 mov r1, r3 - 800155e: 4830 ldr r0, [pc, #192] @ (8001620 ) - 8001560: f001 fb5e bl 8002c20 - 8001564: 4603 mov r3, r0 - 8001566: 2b00 cmp r3, #0 - 8001568: d001 beq.n 800156e + 800157a: 1d3b adds r3, r7, #4 + 800157c: 4619 mov r1, r3 + 800157e: 4830 ldr r0, [pc, #192] @ (8001640 ) + 8001580: f001 fb9c bl 8002cbc + 8001584: 4603 mov r3, r0 + 8001586: 2b00 cmp r3, #0 + 8001588: d001 beq.n 800158e { Error_Handler(); - 800156a: f000 fa57 bl 8001a1c + 800158a: f000 fa57 bl 8001a3c } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_2; - 800156e: 2302 movs r3, #2 - 8001570: 607b str r3, [r7, #4] + 800158e: 2302 movs r3, #2 + 8001590: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_3; - 8001572: 2303 movs r3, #3 - 8001574: 60bb str r3, [r7, #8] + 8001592: 2303 movs r3, #3 + 8001594: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) - 8001576: 1d3b adds r3, r7, #4 - 8001578: 4619 mov r1, r3 - 800157a: 4829 ldr r0, [pc, #164] @ (8001620 ) - 800157c: f001 fb50 bl 8002c20 - 8001580: 4603 mov r3, r0 - 8001582: 2b00 cmp r3, #0 - 8001584: d001 beq.n 800158a + 8001596: 1d3b adds r3, r7, #4 + 8001598: 4619 mov r1, r3 + 800159a: 4829 ldr r0, [pc, #164] @ (8001640 ) + 800159c: f001 fb8e bl 8002cbc + 80015a0: 4603 mov r3, r0 + 80015a2: 2b00 cmp r3, #0 + 80015a4: d001 beq.n 80015aa { Error_Handler(); - 8001586: f000 fa49 bl 8001a1c + 80015a6: f000 fa49 bl 8001a3c } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_3; - 800158a: 2303 movs r3, #3 - 800158c: 607b str r3, [r7, #4] + 80015aa: 2303 movs r3, #3 + 80015ac: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_4; - 800158e: 2304 movs r3, #4 - 8001590: 60bb str r3, [r7, #8] + 80015ae: 2304 movs r3, #4 + 80015b0: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) - 8001592: 1d3b adds r3, r7, #4 - 8001594: 4619 mov r1, r3 - 8001596: 4822 ldr r0, [pc, #136] @ (8001620 ) - 8001598: f001 fb42 bl 8002c20 - 800159c: 4603 mov r3, r0 - 800159e: 2b00 cmp r3, #0 - 80015a0: d001 beq.n 80015a6 + 80015b2: 1d3b adds r3, r7, #4 + 80015b4: 4619 mov r1, r3 + 80015b6: 4822 ldr r0, [pc, #136] @ (8001640 ) + 80015b8: f001 fb80 bl 8002cbc + 80015bc: 4603 mov r3, r0 + 80015be: 2b00 cmp r3, #0 + 80015c0: d001 beq.n 80015c6 { Error_Handler(); - 80015a2: f000 fa3b bl 8001a1c + 80015c2: f000 fa3b bl 8001a3c } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_4; - 80015a6: 2304 movs r3, #4 - 80015a8: 607b str r3, [r7, #4] + 80015c6: 2304 movs r3, #4 + 80015c8: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_5; - 80015aa: 2305 movs r3, #5 - 80015ac: 60bb str r3, [r7, #8] + 80015ca: 2305 movs r3, #5 + 80015cc: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) - 80015ae: 1d3b adds r3, r7, #4 - 80015b0: 4619 mov r1, r3 - 80015b2: 481b ldr r0, [pc, #108] @ (8001620 ) - 80015b4: f001 fb34 bl 8002c20 - 80015b8: 4603 mov r3, r0 - 80015ba: 2b00 cmp r3, #0 - 80015bc: d001 beq.n 80015c2 + 80015ce: 1d3b adds r3, r7, #4 + 80015d0: 4619 mov r1, r3 + 80015d2: 481b ldr r0, [pc, #108] @ (8001640 ) + 80015d4: f001 fb72 bl 8002cbc + 80015d8: 4603 mov r3, r0 + 80015da: 2b00 cmp r3, #0 + 80015dc: d001 beq.n 80015e2 { Error_Handler(); - 80015be: f000 fa2d bl 8001a1c + 80015de: f000 fa2d bl 8001a3c } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_1; - 80015c2: 2301 movs r3, #1 - 80015c4: 607b str r3, [r7, #4] + 80015e2: 2301 movs r3, #1 + 80015e4: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_6; - 80015c6: 2306 movs r3, #6 - 80015c8: 60bb str r3, [r7, #8] + 80015e6: 2306 movs r3, #6 + 80015e8: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) - 80015ca: 1d3b adds r3, r7, #4 - 80015cc: 4619 mov r1, r3 - 80015ce: 4814 ldr r0, [pc, #80] @ (8001620 ) - 80015d0: f001 fb26 bl 8002c20 - 80015d4: 4603 mov r3, r0 - 80015d6: 2b00 cmp r3, #0 - 80015d8: d001 beq.n 80015de + 80015ea: 1d3b adds r3, r7, #4 + 80015ec: 4619 mov r1, r3 + 80015ee: 4814 ldr r0, [pc, #80] @ (8001640 ) + 80015f0: f001 fb64 bl 8002cbc + 80015f4: 4603 mov r3, r0 + 80015f6: 2b00 cmp r3, #0 + 80015f8: d001 beq.n 80015fe { Error_Handler(); - 80015da: f000 fa1f bl 8001a1c + 80015fa: f000 fa1f bl 8001a3c } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_7; - 80015de: 2307 movs r3, #7 - 80015e0: 607b str r3, [r7, #4] + 80015fe: 2307 movs r3, #7 + 8001600: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_7; - 80015e2: 2307 movs r3, #7 - 80015e4: 60bb str r3, [r7, #8] + 8001602: 2307 movs r3, #7 + 8001604: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) - 80015e6: 1d3b adds r3, r7, #4 - 80015e8: 4619 mov r1, r3 - 80015ea: 480d ldr r0, [pc, #52] @ (8001620 ) - 80015ec: f001 fb18 bl 8002c20 - 80015f0: 4603 mov r3, r0 - 80015f2: 2b00 cmp r3, #0 - 80015f4: d001 beq.n 80015fa + 8001606: 1d3b adds r3, r7, #4 + 8001608: 4619 mov r1, r3 + 800160a: 480d ldr r0, [pc, #52] @ (8001640 ) + 800160c: f001 fb56 bl 8002cbc + 8001610: 4603 mov r3, r0 + 8001612: 2b00 cmp r3, #0 + 8001614: d001 beq.n 800161a { Error_Handler(); - 80015f6: f000 fa11 bl 8001a1c + 8001616: f000 fa11 bl 8001a3c } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_8; - 80015fa: 2308 movs r3, #8 - 80015fc: 607b str r3, [r7, #4] + 800161a: 2308 movs r3, #8 + 800161c: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_8; - 80015fe: 2308 movs r3, #8 - 8001600: 60bb str r3, [r7, #8] + 800161e: 2308 movs r3, #8 + 8001620: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) - 8001602: 1d3b adds r3, r7, #4 - 8001604: 4619 mov r1, r3 - 8001606: 4806 ldr r0, [pc, #24] @ (8001620 ) - 8001608: f001 fb0a bl 8002c20 - 800160c: 4603 mov r3, r0 - 800160e: 2b00 cmp r3, #0 - 8001610: d001 beq.n 8001616 + 8001622: 1d3b adds r3, r7, #4 + 8001624: 4619 mov r1, r3 + 8001626: 4806 ldr r0, [pc, #24] @ (8001640 ) + 8001628: f001 fb48 bl 8002cbc + 800162c: 4603 mov r3, r0 + 800162e: 2b00 cmp r3, #0 + 8001630: d001 beq.n 8001636 { Error_Handler(); - 8001612: f000 fa03 bl 8001a1c + 8001632: f000 fa03 bl 8001a3c } /* USER CODE BEGIN ADC1_Init 2 */ /* USER CODE END ADC1_Init 2 */ } - 8001616: bf00 nop - 8001618: 3728 adds r7, #40 @ 0x28 - 800161a: 46bd mov sp, r7 - 800161c: bd80 pop {r7, pc} - 800161e: bf00 nop - 8001620: 200000c4 .word 0x200000c4 + 8001636: bf00 nop + 8001638: 3728 adds r7, #40 @ 0x28 + 800163a: 46bd mov sp, r7 + 800163c: bd80 pop {r7, pc} + 800163e: bf00 nop + 8001640: 200000c4 .word 0x200000c4 -08001624 : +08001644 : * @brief ADC2 Initialization Function * @param None * @retval None */ static void MX_ADC2_Init(void) { - 8001624: b580 push {r7, lr} - 8001626: b086 sub sp, #24 - 8001628: af00 add r7, sp, #0 + 8001644: b580 push {r7, lr} + 8001646: b086 sub sp, #24 + 8001648: af00 add r7, sp, #0 /* USER CODE BEGIN ADC2_Init 0 */ /* USER CODE END ADC2_Init 0 */ ADC_ChannelConfTypeDef sConfig = {0}; - 800162a: 463b mov r3, r7 - 800162c: 2200 movs r2, #0 - 800162e: 601a str r2, [r3, #0] - 8001630: 605a str r2, [r3, #4] - 8001632: 609a str r2, [r3, #8] - 8001634: 60da str r2, [r3, #12] - 8001636: 611a str r2, [r3, #16] - 8001638: 615a str r2, [r3, #20] + 800164a: 463b mov r3, r7 + 800164c: 2200 movs r2, #0 + 800164e: 601a str r2, [r3, #0] + 8001650: 605a str r2, [r3, #4] + 8001652: 609a str r2, [r3, #8] + 8001654: 60da str r2, [r3, #12] + 8001656: 611a str r2, [r3, #16] + 8001658: 615a str r2, [r3, #20] /* USER CODE END ADC2_Init 1 */ /** Common config */ hadc2.Instance = ADC2; - 800163a: 4b4b ldr r3, [pc, #300] @ (8001768 ) - 800163c: 4a4b ldr r2, [pc, #300] @ (800176c ) - 800163e: 601a str r2, [r3, #0] + 800165a: 4b4b ldr r3, [pc, #300] @ (8001788 ) + 800165c: 4a4b ldr r2, [pc, #300] @ (800178c ) + 800165e: 601a str r2, [r3, #0] hadc2.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1; - 8001640: 4b49 ldr r3, [pc, #292] @ (8001768 ) - 8001642: 2200 movs r2, #0 - 8001644: 605a str r2, [r3, #4] + 8001660: 4b49 ldr r3, [pc, #292] @ (8001788 ) + 8001662: 2200 movs r2, #0 + 8001664: 605a str r2, [r3, #4] hadc2.Init.Resolution = ADC_RESOLUTION_12B; - 8001646: 4b48 ldr r3, [pc, #288] @ (8001768 ) - 8001648: 2200 movs r2, #0 - 800164a: 609a str r2, [r3, #8] + 8001666: 4b48 ldr r3, [pc, #288] @ (8001788 ) + 8001668: 2200 movs r2, #0 + 800166a: 609a str r2, [r3, #8] hadc2.Init.ScanConvMode = ADC_SCAN_ENABLE; - 800164c: 4b46 ldr r3, [pc, #280] @ (8001768 ) - 800164e: 2201 movs r2, #1 - 8001650: 611a str r2, [r3, #16] + 800166c: 4b46 ldr r3, [pc, #280] @ (8001788 ) + 800166e: 2201 movs r2, #1 + 8001670: 611a str r2, [r3, #16] hadc2.Init.ContinuousConvMode = DISABLE; - 8001652: 4b45 ldr r3, [pc, #276] @ (8001768 ) - 8001654: 2200 movs r2, #0 - 8001656: 765a strb r2, [r3, #25] + 8001672: 4b45 ldr r3, [pc, #276] @ (8001788 ) + 8001674: 2200 movs r2, #0 + 8001676: 765a strb r2, [r3, #25] hadc2.Init.DiscontinuousConvMode = DISABLE; - 8001658: 4b43 ldr r3, [pc, #268] @ (8001768 ) - 800165a: 2200 movs r2, #0 - 800165c: f883 2020 strb.w r2, [r3, #32] + 8001678: 4b43 ldr r3, [pc, #268] @ (8001788 ) + 800167a: 2200 movs r2, #0 + 800167c: f883 2020 strb.w r2, [r3, #32] hadc2.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; - 8001660: 4b41 ldr r3, [pc, #260] @ (8001768 ) - 8001662: f44f 6280 mov.w r2, #1024 @ 0x400 - 8001666: 62da str r2, [r3, #44] @ 0x2c + 8001680: 4b41 ldr r3, [pc, #260] @ (8001788 ) + 8001682: f44f 6280 mov.w r2, #1024 @ 0x400 + 8001686: 62da str r2, [r3, #44] @ 0x2c hadc2.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_T6_TRGO; - 8001668: 4b3f ldr r3, [pc, #252] @ (8001768 ) - 800166a: f44f 7250 mov.w r2, #832 @ 0x340 - 800166e: 629a str r2, [r3, #40] @ 0x28 + 8001688: 4b3f ldr r3, [pc, #252] @ (8001788 ) + 800168a: f44f 7250 mov.w r2, #832 @ 0x340 + 800168e: 629a str r2, [r3, #40] @ 0x28 hadc2.Init.DataAlign = ADC_DATAALIGN_RIGHT; - 8001670: 4b3d ldr r3, [pc, #244] @ (8001768 ) - 8001672: 2200 movs r2, #0 - 8001674: 60da str r2, [r3, #12] - hadc2.Init.NbrOfConversion = 6; - 8001676: 4b3c ldr r3, [pc, #240] @ (8001768 ) - 8001678: 2206 movs r2, #6 - 800167a: 61da str r2, [r3, #28] - hadc2.Init.DMAContinuousRequests = ENABLE; - 800167c: 4b3a ldr r3, [pc, #232] @ (8001768 ) - 800167e: 2201 movs r2, #1 - 8001680: f883 2030 strb.w r2, [r3, #48] @ 0x30 - hadc2.Init.EOCSelection = ADC_EOC_SEQ_CONV; - 8001684: 4b38 ldr r3, [pc, #224] @ (8001768 ) - 8001686: 2208 movs r2, #8 - 8001688: 615a str r2, [r3, #20] - hadc2.Init.LowPowerAutoWait = DISABLE; - 800168a: 4b37 ldr r3, [pc, #220] @ (8001768 ) - 800168c: 2200 movs r2, #0 - 800168e: 761a strb r2, [r3, #24] - hadc2.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN; - 8001690: 4b35 ldr r3, [pc, #212] @ (8001768 ) + 8001690: 4b3d ldr r3, [pc, #244] @ (8001788 ) 8001692: 2200 movs r2, #0 - 8001694: 635a str r2, [r3, #52] @ 0x34 + 8001694: 60da str r2, [r3, #12] + hadc2.Init.NbrOfConversion = 6; + 8001696: 4b3c ldr r3, [pc, #240] @ (8001788 ) + 8001698: 2206 movs r2, #6 + 800169a: 61da str r2, [r3, #28] + hadc2.Init.DMAContinuousRequests = ENABLE; + 800169c: 4b3a ldr r3, [pc, #232] @ (8001788 ) + 800169e: 2201 movs r2, #1 + 80016a0: f883 2030 strb.w r2, [r3, #48] @ 0x30 + hadc2.Init.EOCSelection = ADC_EOC_SEQ_CONV; + 80016a4: 4b38 ldr r3, [pc, #224] @ (8001788 ) + 80016a6: 2208 movs r2, #8 + 80016a8: 615a str r2, [r3, #20] + hadc2.Init.LowPowerAutoWait = DISABLE; + 80016aa: 4b37 ldr r3, [pc, #220] @ (8001788 ) + 80016ac: 2200 movs r2, #0 + 80016ae: 761a strb r2, [r3, #24] + hadc2.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN; + 80016b0: 4b35 ldr r3, [pc, #212] @ (8001788 ) + 80016b2: 2200 movs r2, #0 + 80016b4: 635a str r2, [r3, #52] @ 0x34 if (HAL_ADC_Init(&hadc2) != HAL_OK) - 8001696: 4834 ldr r0, [pc, #208] @ (8001768 ) - 8001698: f000 fe34 bl 8002304 - 800169c: 4603 mov r3, r0 - 800169e: 2b00 cmp r3, #0 - 80016a0: d001 beq.n 80016a6 + 80016b6: 4834 ldr r0, [pc, #208] @ (8001788 ) + 80016b8: f000 fe72 bl 80023a0 + 80016bc: 4603 mov r3, r0 + 80016be: 2b00 cmp r3, #0 + 80016c0: d001 beq.n 80016c6 { Error_Handler(); - 80016a2: f000 f9bb bl 8001a1c + 80016c2: f000 f9bb bl 8001a3c } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_1; - 80016a6: 2301 movs r3, #1 - 80016a8: 603b str r3, [r7, #0] + 80016c6: 2301 movs r3, #1 + 80016c8: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_1; - 80016aa: 2301 movs r3, #1 - 80016ac: 607b str r3, [r7, #4] + 80016ca: 2301 movs r3, #1 + 80016cc: 607b str r3, [r7, #4] sConfig.SingleDiff = ADC_SINGLE_ENDED; - 80016ae: 2300 movs r3, #0 - 80016b0: 60fb str r3, [r7, #12] + 80016ce: 2300 movs r3, #0 + 80016d0: 60fb str r3, [r7, #12] sConfig.SamplingTime = ADC_SAMPLETIME_61CYCLES_5; - 80016b2: 2305 movs r3, #5 - 80016b4: 60bb str r3, [r7, #8] + 80016d2: 2305 movs r3, #5 + 80016d4: 60bb str r3, [r7, #8] sConfig.OffsetNumber = ADC_OFFSET_NONE; - 80016b6: 2300 movs r3, #0 - 80016b8: 613b str r3, [r7, #16] + 80016d6: 2300 movs r3, #0 + 80016d8: 613b str r3, [r7, #16] sConfig.Offset = 0; - 80016ba: 2300 movs r3, #0 - 80016bc: 617b str r3, [r7, #20] + 80016da: 2300 movs r3, #0 + 80016dc: 617b str r3, [r7, #20] if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) - 80016be: 463b mov r3, r7 - 80016c0: 4619 mov r1, r3 - 80016c2: 4829 ldr r0, [pc, #164] @ (8001768 ) - 80016c4: f001 faac bl 8002c20 - 80016c8: 4603 mov r3, r0 - 80016ca: 2b00 cmp r3, #0 - 80016cc: d001 beq.n 80016d2 + 80016de: 463b mov r3, r7 + 80016e0: 4619 mov r1, r3 + 80016e2: 4829 ldr r0, [pc, #164] @ (8001788 ) + 80016e4: f001 faea bl 8002cbc + 80016e8: 4603 mov r3, r0 + 80016ea: 2b00 cmp r3, #0 + 80016ec: d001 beq.n 80016f2 { Error_Handler(); - 80016ce: f000 f9a5 bl 8001a1c + 80016ee: f000 f9a5 bl 8001a3c } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_2; - 80016d2: 2302 movs r3, #2 - 80016d4: 603b str r3, [r7, #0] + 80016f2: 2302 movs r3, #2 + 80016f4: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_2; - 80016d6: 2302 movs r3, #2 - 80016d8: 607b str r3, [r7, #4] + 80016f6: 2302 movs r3, #2 + 80016f8: 607b str r3, [r7, #4] if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) - 80016da: 463b mov r3, r7 - 80016dc: 4619 mov r1, r3 - 80016de: 4822 ldr r0, [pc, #136] @ (8001768 ) - 80016e0: f001 fa9e bl 8002c20 - 80016e4: 4603 mov r3, r0 - 80016e6: 2b00 cmp r3, #0 - 80016e8: d001 beq.n 80016ee + 80016fa: 463b mov r3, r7 + 80016fc: 4619 mov r1, r3 + 80016fe: 4822 ldr r0, [pc, #136] @ (8001788 ) + 8001700: f001 fadc bl 8002cbc + 8001704: 4603 mov r3, r0 + 8001706: 2b00 cmp r3, #0 + 8001708: d001 beq.n 800170e { Error_Handler(); - 80016ea: f000 f997 bl 8001a1c + 800170a: f000 f997 bl 8001a3c } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_3; - 80016ee: 2303 movs r3, #3 - 80016f0: 603b str r3, [r7, #0] + 800170e: 2303 movs r3, #3 + 8001710: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_3; - 80016f2: 2303 movs r3, #3 - 80016f4: 607b str r3, [r7, #4] + 8001712: 2303 movs r3, #3 + 8001714: 607b str r3, [r7, #4] if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) - 80016f6: 463b mov r3, r7 - 80016f8: 4619 mov r1, r3 - 80016fa: 481b ldr r0, [pc, #108] @ (8001768 ) - 80016fc: f001 fa90 bl 8002c20 - 8001700: 4603 mov r3, r0 - 8001702: 2b00 cmp r3, #0 - 8001704: d001 beq.n 800170a + 8001716: 463b mov r3, r7 + 8001718: 4619 mov r1, r3 + 800171a: 481b ldr r0, [pc, #108] @ (8001788 ) + 800171c: f001 face bl 8002cbc + 8001720: 4603 mov r3, r0 + 8001722: 2b00 cmp r3, #0 + 8001724: d001 beq.n 800172a { Error_Handler(); - 8001706: f000 f989 bl 8001a1c + 8001726: f000 f989 bl 8001a3c } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_4; - 800170a: 2304 movs r3, #4 - 800170c: 603b str r3, [r7, #0] + 800172a: 2304 movs r3, #4 + 800172c: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_4; - 800170e: 2304 movs r3, #4 - 8001710: 607b str r3, [r7, #4] + 800172e: 2304 movs r3, #4 + 8001730: 607b str r3, [r7, #4] if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) - 8001712: 463b mov r3, r7 - 8001714: 4619 mov r1, r3 - 8001716: 4814 ldr r0, [pc, #80] @ (8001768 ) - 8001718: f001 fa82 bl 8002c20 - 800171c: 4603 mov r3, r0 - 800171e: 2b00 cmp r3, #0 - 8001720: d001 beq.n 8001726 + 8001732: 463b mov r3, r7 + 8001734: 4619 mov r1, r3 + 8001736: 4814 ldr r0, [pc, #80] @ (8001788 ) + 8001738: f001 fac0 bl 8002cbc + 800173c: 4603 mov r3, r0 + 800173e: 2b00 cmp r3, #0 + 8001740: d001 beq.n 8001746 { Error_Handler(); - 8001722: f000 f97b bl 8001a1c + 8001742: f000 f97b bl 8001a3c } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_5; - 8001726: 2305 movs r3, #5 - 8001728: 603b str r3, [r7, #0] + 8001746: 2305 movs r3, #5 + 8001748: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_5; - 800172a: 2305 movs r3, #5 - 800172c: 607b str r3, [r7, #4] + 800174a: 2305 movs r3, #5 + 800174c: 607b str r3, [r7, #4] if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) - 800172e: 463b mov r3, r7 - 8001730: 4619 mov r1, r3 - 8001732: 480d ldr r0, [pc, #52] @ (8001768 ) - 8001734: f001 fa74 bl 8002c20 - 8001738: 4603 mov r3, r0 - 800173a: 2b00 cmp r3, #0 - 800173c: d001 beq.n 8001742 + 800174e: 463b mov r3, r7 + 8001750: 4619 mov r1, r3 + 8001752: 480d ldr r0, [pc, #52] @ (8001788 ) + 8001754: f001 fab2 bl 8002cbc + 8001758: 4603 mov r3, r0 + 800175a: 2b00 cmp r3, #0 + 800175c: d001 beq.n 8001762 { Error_Handler(); - 800173e: f000 f96d bl 8001a1c + 800175e: f000 f96d bl 8001a3c } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_9; - 8001742: 2309 movs r3, #9 - 8001744: 603b str r3, [r7, #0] + 8001762: 2309 movs r3, #9 + 8001764: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_6; - 8001746: 2306 movs r3, #6 - 8001748: 607b str r3, [r7, #4] + 8001766: 2306 movs r3, #6 + 8001768: 607b str r3, [r7, #4] if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) - 800174a: 463b mov r3, r7 - 800174c: 4619 mov r1, r3 - 800174e: 4806 ldr r0, [pc, #24] @ (8001768 ) - 8001750: f001 fa66 bl 8002c20 - 8001754: 4603 mov r3, r0 - 8001756: 2b00 cmp r3, #0 - 8001758: d001 beq.n 800175e + 800176a: 463b mov r3, r7 + 800176c: 4619 mov r1, r3 + 800176e: 4806 ldr r0, [pc, #24] @ (8001788 ) + 8001770: f001 faa4 bl 8002cbc + 8001774: 4603 mov r3, r0 + 8001776: 2b00 cmp r3, #0 + 8001778: d001 beq.n 800177e { Error_Handler(); - 800175a: f000 f95f bl 8001a1c + 800177a: f000 f95f bl 8001a3c } /* USER CODE BEGIN ADC2_Init 2 */ /* USER CODE END ADC2_Init 2 */ } - 800175e: bf00 nop - 8001760: 3718 adds r7, #24 - 8001762: 46bd mov sp, r7 - 8001764: bd80 pop {r7, pc} - 8001766: bf00 nop - 8001768: 20000114 .word 0x20000114 - 800176c: 50000100 .word 0x50000100 + 800177e: bf00 nop + 8001780: 3718 adds r7, #24 + 8001782: 46bd mov sp, r7 + 8001784: bd80 pop {r7, pc} + 8001786: bf00 nop + 8001788: 20000114 .word 0x20000114 + 800178c: 50000100 .word 0x50000100 -08001770 : +08001790 : * @brief CAN Initialization Function * @param None * @retval None */ static void MX_CAN_Init(void) { - 8001770: b580 push {r7, lr} - 8001772: af00 add r7, sp, #0 + 8001790: b580 push {r7, lr} + 8001792: af00 add r7, sp, #0 /* USER CODE END CAN_Init 0 */ /* USER CODE BEGIN CAN_Init 1 */ /* USER CODE END CAN_Init 1 */ hcan.Instance = CAN; - 8001774: 4b17 ldr r3, [pc, #92] @ (80017d4 ) - 8001776: 4a18 ldr r2, [pc, #96] @ (80017d8 ) - 8001778: 601a str r2, [r3, #0] + 8001794: 4b17 ldr r3, [pc, #92] @ (80017f4 ) + 8001796: 4a18 ldr r2, [pc, #96] @ (80017f8 ) + 8001798: 601a str r2, [r3, #0] hcan.Init.Prescaler = 2; - 800177a: 4b16 ldr r3, [pc, #88] @ (80017d4 ) - 800177c: 2202 movs r2, #2 - 800177e: 605a str r2, [r3, #4] + 800179a: 4b16 ldr r3, [pc, #88] @ (80017f4 ) + 800179c: 2202 movs r2, #2 + 800179e: 605a str r2, [r3, #4] hcan.Init.Mode = CAN_MODE_NORMAL; - 8001780: 4b14 ldr r3, [pc, #80] @ (80017d4 ) - 8001782: 2200 movs r2, #0 - 8001784: 609a str r2, [r3, #8] + 80017a0: 4b14 ldr r3, [pc, #80] @ (80017f4 ) + 80017a2: 2200 movs r2, #0 + 80017a4: 609a str r2, [r3, #8] hcan.Init.SyncJumpWidth = CAN_SJW_1TQ; - 8001786: 4b13 ldr r3, [pc, #76] @ (80017d4 ) - 8001788: 2200 movs r2, #0 - 800178a: 60da str r2, [r3, #12] + 80017a6: 4b13 ldr r3, [pc, #76] @ (80017f4 ) + 80017a8: 2200 movs r2, #0 + 80017aa: 60da str r2, [r3, #12] hcan.Init.TimeSeg1 = CAN_BS1_13TQ; - 800178c: 4b11 ldr r3, [pc, #68] @ (80017d4 ) - 800178e: f44f 2240 mov.w r2, #786432 @ 0xc0000 - 8001792: 611a str r2, [r3, #16] + 80017ac: 4b11 ldr r3, [pc, #68] @ (80017f4 ) + 80017ae: f44f 2240 mov.w r2, #786432 @ 0xc0000 + 80017b2: 611a str r2, [r3, #16] hcan.Init.TimeSeg2 = CAN_BS2_2TQ; - 8001794: 4b0f ldr r3, [pc, #60] @ (80017d4 ) - 8001796: f44f 1280 mov.w r2, #1048576 @ 0x100000 - 800179a: 615a str r2, [r3, #20] + 80017b4: 4b0f ldr r3, [pc, #60] @ (80017f4 ) + 80017b6: f44f 1280 mov.w r2, #1048576 @ 0x100000 + 80017ba: 615a str r2, [r3, #20] hcan.Init.TimeTriggeredMode = DISABLE; - 800179c: 4b0d ldr r3, [pc, #52] @ (80017d4 ) - 800179e: 2200 movs r2, #0 - 80017a0: 761a strb r2, [r3, #24] + 80017bc: 4b0d ldr r3, [pc, #52] @ (80017f4 ) + 80017be: 2200 movs r2, #0 + 80017c0: 761a strb r2, [r3, #24] hcan.Init.AutoBusOff = DISABLE; - 80017a2: 4b0c ldr r3, [pc, #48] @ (80017d4 ) - 80017a4: 2200 movs r2, #0 - 80017a6: 765a strb r2, [r3, #25] + 80017c2: 4b0c ldr r3, [pc, #48] @ (80017f4 ) + 80017c4: 2200 movs r2, #0 + 80017c6: 765a strb r2, [r3, #25] hcan.Init.AutoWakeUp = DISABLE; - 80017a8: 4b0a ldr r3, [pc, #40] @ (80017d4 ) - 80017aa: 2200 movs r2, #0 - 80017ac: 769a strb r2, [r3, #26] + 80017c8: 4b0a ldr r3, [pc, #40] @ (80017f4 ) + 80017ca: 2200 movs r2, #0 + 80017cc: 769a strb r2, [r3, #26] hcan.Init.AutoRetransmission = DISABLE; - 80017ae: 4b09 ldr r3, [pc, #36] @ (80017d4 ) - 80017b0: 2200 movs r2, #0 - 80017b2: 76da strb r2, [r3, #27] + 80017ce: 4b09 ldr r3, [pc, #36] @ (80017f4 ) + 80017d0: 2200 movs r2, #0 + 80017d2: 76da strb r2, [r3, #27] hcan.Init.ReceiveFifoLocked = DISABLE; - 80017b4: 4b07 ldr r3, [pc, #28] @ (80017d4 ) - 80017b6: 2200 movs r2, #0 - 80017b8: 771a strb r2, [r3, #28] + 80017d4: 4b07 ldr r3, [pc, #28] @ (80017f4 ) + 80017d6: 2200 movs r2, #0 + 80017d8: 771a strb r2, [r3, #28] hcan.Init.TransmitFifoPriority = DISABLE; - 80017ba: 4b06 ldr r3, [pc, #24] @ (80017d4 ) - 80017bc: 2200 movs r2, #0 - 80017be: 775a strb r2, [r3, #29] + 80017da: 4b06 ldr r3, [pc, #24] @ (80017f4 ) + 80017dc: 2200 movs r2, #0 + 80017de: 775a strb r2, [r3, #29] if (HAL_CAN_Init(&hcan) != HAL_OK) - 80017c0: 4804 ldr r0, [pc, #16] @ (80017d4 ) - 80017c2: f001 fee1 bl 8003588 - 80017c6: 4603 mov r3, r0 - 80017c8: 2b00 cmp r3, #0 - 80017ca: d001 beq.n 80017d0 + 80017e0: 4804 ldr r0, [pc, #16] @ (80017f4 ) + 80017e2: f001 ff1f bl 8003624 + 80017e6: 4603 mov r3, r0 + 80017e8: 2b00 cmp r3, #0 + 80017ea: d001 beq.n 80017f0 { Error_Handler(); - 80017cc: f000 f926 bl 8001a1c + 80017ec: f000 f926 bl 8001a3c } /* USER CODE BEGIN CAN_Init 2 */ /* USER CODE END CAN_Init 2 */ } - 80017d0: bf00 nop - 80017d2: bd80 pop {r7, pc} - 80017d4: 200001ec .word 0x200001ec - 80017d8: 40006400 .word 0x40006400 + 80017f0: bf00 nop + 80017f2: bd80 pop {r7, pc} + 80017f4: 200001ec .word 0x200001ec + 80017f8: 40006400 .word 0x40006400 -080017dc : +080017fc : * @brief TIM6 Initialization Function * @param None * @retval None */ static void MX_TIM6_Init(void) { - 80017dc: b580 push {r7, lr} - 80017de: b084 sub sp, #16 - 80017e0: af00 add r7, sp, #0 + 80017fc: b580 push {r7, lr} + 80017fe: b084 sub sp, #16 + 8001800: af00 add r7, sp, #0 /* USER CODE BEGIN TIM6_Init 0 */ /* USER CODE END TIM6_Init 0 */ TIM_MasterConfigTypeDef sMasterConfig = {0}; - 80017e2: 1d3b adds r3, r7, #4 - 80017e4: 2200 movs r2, #0 - 80017e6: 601a str r2, [r3, #0] - 80017e8: 605a str r2, [r3, #4] - 80017ea: 609a str r2, [r3, #8] + 8001802: 1d3b adds r3, r7, #4 + 8001804: 2200 movs r2, #0 + 8001806: 601a str r2, [r3, #0] + 8001808: 605a str r2, [r3, #4] + 800180a: 609a str r2, [r3, #8] /* USER CODE BEGIN TIM6_Init 1 */ /* USER CODE END TIM6_Init 1 */ htim6.Instance = TIM6; - 80017ec: 4b15 ldr r3, [pc, #84] @ (8001844 ) - 80017ee: 4a16 ldr r2, [pc, #88] @ (8001848 ) - 80017f0: 601a str r2, [r3, #0] + 800180c: 4b15 ldr r3, [pc, #84] @ (8001864 ) + 800180e: 4a16 ldr r2, [pc, #88] @ (8001868 ) + 8001810: 601a str r2, [r3, #0] htim6.Init.Prescaler = 400; - 80017f2: 4b14 ldr r3, [pc, #80] @ (8001844 ) - 80017f4: f44f 72c8 mov.w r2, #400 @ 0x190 - 80017f8: 605a str r2, [r3, #4] + 8001812: 4b14 ldr r3, [pc, #80] @ (8001864 ) + 8001814: f44f 72c8 mov.w r2, #400 @ 0x190 + 8001818: 605a str r2, [r3, #4] htim6.Init.CounterMode = TIM_COUNTERMODE_UP; - 80017fa: 4b12 ldr r3, [pc, #72] @ (8001844 ) - 80017fc: 2200 movs r2, #0 - 80017fe: 609a str r2, [r3, #8] + 800181a: 4b12 ldr r3, [pc, #72] @ (8001864 ) + 800181c: 2200 movs r2, #0 + 800181e: 609a str r2, [r3, #8] htim6.Init.Period = 8000-1; - 8001800: 4b10 ldr r3, [pc, #64] @ (8001844 ) - 8001802: f641 723f movw r2, #7999 @ 0x1f3f - 8001806: 60da str r2, [r3, #12] + 8001820: 4b10 ldr r3, [pc, #64] @ (8001864 ) + 8001822: f641 723f movw r2, #7999 @ 0x1f3f + 8001826: 60da str r2, [r3, #12] htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; - 8001808: 4b0e ldr r3, [pc, #56] @ (8001844 ) - 800180a: 2200 movs r2, #0 - 800180c: 619a str r2, [r3, #24] + 8001828: 4b0e ldr r3, [pc, #56] @ (8001864 ) + 800182a: 2200 movs r2, #0 + 800182c: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim6) != HAL_OK) - 800180e: 480d ldr r0, [pc, #52] @ (8001844 ) - 8001810: f004 fd52 bl 80062b8 - 8001814: 4603 mov r3, r0 - 8001816: 2b00 cmp r3, #0 - 8001818: d001 beq.n 800181e + 800182e: 480d ldr r0, [pc, #52] @ (8001864 ) + 8001830: f004 fd90 bl 8006354 + 8001834: 4603 mov r3, r0 + 8001836: 2b00 cmp r3, #0 + 8001838: d001 beq.n 800183e { Error_Handler(); - 800181a: f000 f8ff bl 8001a1c + 800183a: f000 f8ff bl 8001a3c } sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE; - 800181e: 2320 movs r3, #32 - 8001820: 607b str r3, [r7, #4] + 800183e: 2320 movs r3, #32 + 8001840: 607b str r3, [r7, #4] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; - 8001822: 2300 movs r3, #0 - 8001824: 60fb str r3, [r7, #12] + 8001842: 2300 movs r3, #0 + 8001844: 60fb str r3, [r7, #12] if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig) != HAL_OK) - 8001826: 1d3b adds r3, r7, #4 - 8001828: 4619 mov r1, r3 - 800182a: 4806 ldr r0, [pc, #24] @ (8001844 ) - 800182c: f004 ffb8 bl 80067a0 - 8001830: 4603 mov r3, r0 - 8001832: 2b00 cmp r3, #0 - 8001834: d001 beq.n 800183a + 8001846: 1d3b adds r3, r7, #4 + 8001848: 4619 mov r1, r3 + 800184a: 4806 ldr r0, [pc, #24] @ (8001864 ) + 800184c: f004 fff6 bl 800683c + 8001850: 4603 mov r3, r0 + 8001852: 2b00 cmp r3, #0 + 8001854: d001 beq.n 800185a { Error_Handler(); - 8001836: f000 f8f1 bl 8001a1c + 8001856: f000 f8f1 bl 8001a3c } /* USER CODE BEGIN TIM6_Init 2 */ /* USER CODE END TIM6_Init 2 */ } - 800183a: bf00 nop - 800183c: 3710 adds r7, #16 - 800183e: 46bd mov sp, r7 - 8001840: bd80 pop {r7, pc} - 8001842: bf00 nop - 8001844: 20000214 .word 0x20000214 - 8001848: 40001000 .word 0x40001000 + 800185a: bf00 nop + 800185c: 3710 adds r7, #16 + 800185e: 46bd mov sp, r7 + 8001860: bd80 pop {r7, pc} + 8001862: bf00 nop + 8001864: 20000214 .word 0x20000214 + 8001868: 40001000 .word 0x40001000 -0800184c : +0800186c : * @brief UART4 Initialization Function * @param None * @retval None */ static void MX_UART4_Init(void) { - 800184c: b580 push {r7, lr} - 800184e: af00 add r7, sp, #0 + 800186c: b580 push {r7, lr} + 800186e: af00 add r7, sp, #0 /* USER CODE END UART4_Init 0 */ /* USER CODE BEGIN UART4_Init 1 */ /* USER CODE END UART4_Init 1 */ huart4.Instance = UART4; - 8001850: 4b14 ldr r3, [pc, #80] @ (80018a4 ) - 8001852: 4a15 ldr r2, [pc, #84] @ (80018a8 ) - 8001854: 601a str r2, [r3, #0] + 8001870: 4b14 ldr r3, [pc, #80] @ (80018c4 ) + 8001872: 4a15 ldr r2, [pc, #84] @ (80018c8 ) + 8001874: 601a str r2, [r3, #0] huart4.Init.BaudRate = 115200; - 8001856: 4b13 ldr r3, [pc, #76] @ (80018a4 ) - 8001858: f44f 32e1 mov.w r2, #115200 @ 0x1c200 - 800185c: 605a str r2, [r3, #4] + 8001876: 4b13 ldr r3, [pc, #76] @ (80018c4 ) + 8001878: f44f 32e1 mov.w r2, #115200 @ 0x1c200 + 800187c: 605a str r2, [r3, #4] huart4.Init.WordLength = UART_WORDLENGTH_8B; - 800185e: 4b11 ldr r3, [pc, #68] @ (80018a4 ) - 8001860: 2200 movs r2, #0 - 8001862: 609a str r2, [r3, #8] + 800187e: 4b11 ldr r3, [pc, #68] @ (80018c4 ) + 8001880: 2200 movs r2, #0 + 8001882: 609a str r2, [r3, #8] huart4.Init.StopBits = UART_STOPBITS_1; - 8001864: 4b0f ldr r3, [pc, #60] @ (80018a4 ) - 8001866: 2200 movs r2, #0 - 8001868: 60da str r2, [r3, #12] + 8001884: 4b0f ldr r3, [pc, #60] @ (80018c4 ) + 8001886: 2200 movs r2, #0 + 8001888: 60da str r2, [r3, #12] huart4.Init.Parity = UART_PARITY_NONE; - 800186a: 4b0e ldr r3, [pc, #56] @ (80018a4 ) - 800186c: 2200 movs r2, #0 - 800186e: 611a str r2, [r3, #16] + 800188a: 4b0e ldr r3, [pc, #56] @ (80018c4 ) + 800188c: 2200 movs r2, #0 + 800188e: 611a str r2, [r3, #16] huart4.Init.Mode = UART_MODE_TX_RX; - 8001870: 4b0c ldr r3, [pc, #48] @ (80018a4 ) - 8001872: 220c movs r2, #12 - 8001874: 615a str r2, [r3, #20] + 8001890: 4b0c ldr r3, [pc, #48] @ (80018c4 ) + 8001892: 220c movs r2, #12 + 8001894: 615a str r2, [r3, #20] huart4.Init.HwFlowCtl = UART_HWCONTROL_NONE; - 8001876: 4b0b ldr r3, [pc, #44] @ (80018a4 ) - 8001878: 2200 movs r2, #0 - 800187a: 619a str r2, [r3, #24] + 8001896: 4b0b ldr r3, [pc, #44] @ (80018c4 ) + 8001898: 2200 movs r2, #0 + 800189a: 619a str r2, [r3, #24] huart4.Init.OverSampling = UART_OVERSAMPLING_16; - 800187c: 4b09 ldr r3, [pc, #36] @ (80018a4 ) - 800187e: 2200 movs r2, #0 - 8001880: 61da str r2, [r3, #28] + 800189c: 4b09 ldr r3, [pc, #36] @ (80018c4 ) + 800189e: 2200 movs r2, #0 + 80018a0: 61da str r2, [r3, #28] huart4.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; - 8001882: 4b08 ldr r3, [pc, #32] @ (80018a4 ) - 8001884: 2200 movs r2, #0 - 8001886: 621a str r2, [r3, #32] + 80018a2: 4b08 ldr r3, [pc, #32] @ (80018c4 ) + 80018a4: 2200 movs r2, #0 + 80018a6: 621a str r2, [r3, #32] huart4.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; - 8001888: 4b06 ldr r3, [pc, #24] @ (80018a4 ) - 800188a: 2200 movs r2, #0 - 800188c: 625a str r2, [r3, #36] @ 0x24 + 80018a8: 4b06 ldr r3, [pc, #24] @ (80018c4 ) + 80018aa: 2200 movs r2, #0 + 80018ac: 625a str r2, [r3, #36] @ 0x24 if (HAL_UART_Init(&huart4) != HAL_OK) - 800188e: 4805 ldr r0, [pc, #20] @ (80018a4 ) - 8001890: f005 f818 bl 80068c4 - 8001894: 4603 mov r3, r0 - 8001896: 2b00 cmp r3, #0 - 8001898: d001 beq.n 800189e + 80018ae: 4805 ldr r0, [pc, #20] @ (80018c4 ) + 80018b0: f005 f856 bl 8006960 + 80018b4: 4603 mov r3, r0 + 80018b6: 2b00 cmp r3, #0 + 80018b8: d001 beq.n 80018be { Error_Handler(); - 800189a: f000 f8bf bl 8001a1c + 80018ba: f000 f8bf bl 8001a3c } /* USER CODE BEGIN UART4_Init 2 */ /* USER CODE END UART4_Init 2 */ } - 800189e: bf00 nop - 80018a0: bd80 pop {r7, pc} - 80018a2: bf00 nop - 80018a4: 20000260 .word 0x20000260 - 80018a8: 40004c00 .word 0x40004c00 + 80018be: bf00 nop + 80018c0: bd80 pop {r7, pc} + 80018c2: bf00 nop + 80018c4: 20000260 .word 0x20000260 + 80018c8: 40004c00 .word 0x40004c00 -080018ac : +080018cc : /** * Enable DMA controller clock */ static void MX_DMA_Init(void) { - 80018ac: b580 push {r7, lr} - 80018ae: b082 sub sp, #8 - 80018b0: af00 add r7, sp, #0 + 80018cc: b580 push {r7, lr} + 80018ce: b082 sub sp, #8 + 80018d0: af00 add r7, sp, #0 /* DMA controller clock enable */ __HAL_RCC_DMA1_CLK_ENABLE(); - 80018b2: 4b16 ldr r3, [pc, #88] @ (800190c ) - 80018b4: 695b ldr r3, [r3, #20] - 80018b6: 4a15 ldr r2, [pc, #84] @ (800190c ) - 80018b8: f043 0301 orr.w r3, r3, #1 - 80018bc: 6153 str r3, [r2, #20] - 80018be: 4b13 ldr r3, [pc, #76] @ (800190c ) - 80018c0: 695b ldr r3, [r3, #20] - 80018c2: f003 0301 and.w r3, r3, #1 - 80018c6: 607b str r3, [r7, #4] - 80018c8: 687b ldr r3, [r7, #4] + 80018d2: 4b16 ldr r3, [pc, #88] @ (800192c ) + 80018d4: 695b ldr r3, [r3, #20] + 80018d6: 4a15 ldr r2, [pc, #84] @ (800192c ) + 80018d8: f043 0301 orr.w r3, r3, #1 + 80018dc: 6153 str r3, [r2, #20] + 80018de: 4b13 ldr r3, [pc, #76] @ (800192c ) + 80018e0: 695b ldr r3, [r3, #20] + 80018e2: f003 0301 and.w r3, r3, #1 + 80018e6: 607b str r3, [r7, #4] + 80018e8: 687b ldr r3, [r7, #4] __HAL_RCC_DMA2_CLK_ENABLE(); - 80018ca: 4b10 ldr r3, [pc, #64] @ (800190c ) - 80018cc: 695b ldr r3, [r3, #20] - 80018ce: 4a0f ldr r2, [pc, #60] @ (800190c ) - 80018d0: f043 0302 orr.w r3, r3, #2 - 80018d4: 6153 str r3, [r2, #20] - 80018d6: 4b0d ldr r3, [pc, #52] @ (800190c ) - 80018d8: 695b ldr r3, [r3, #20] - 80018da: f003 0302 and.w r3, r3, #2 - 80018de: 603b str r3, [r7, #0] - 80018e0: 683b ldr r3, [r7, #0] + 80018ea: 4b10 ldr r3, [pc, #64] @ (800192c ) + 80018ec: 695b ldr r3, [r3, #20] + 80018ee: 4a0f ldr r2, [pc, #60] @ (800192c ) + 80018f0: f043 0302 orr.w r3, r3, #2 + 80018f4: 6153 str r3, [r2, #20] + 80018f6: 4b0d ldr r3, [pc, #52] @ (800192c ) + 80018f8: 695b ldr r3, [r3, #20] + 80018fa: f003 0302 and.w r3, r3, #2 + 80018fe: 603b str r3, [r7, #0] + 8001900: 683b ldr r3, [r7, #0] /* DMA interrupt init */ /* DMA1_Channel1_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0); - 80018e2: 2200 movs r2, #0 - 80018e4: 2100 movs r1, #0 - 80018e6: 200b movs r0, #11 - 80018e8: f002 fd79 bl 80043de + 8001902: 2200 movs r2, #0 + 8001904: 2100 movs r1, #0 + 8001906: 200b movs r0, #11 + 8001908: f002 fdb7 bl 800447a HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn); - 80018ec: 200b movs r0, #11 - 80018ee: f002 fd92 bl 8004416 + 800190c: 200b movs r0, #11 + 800190e: f002 fdd0 bl 80044b2 /* DMA2_Channel1_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA2_Channel1_IRQn, 0, 0); - 80018f2: 2200 movs r2, #0 - 80018f4: 2100 movs r1, #0 - 80018f6: 2038 movs r0, #56 @ 0x38 - 80018f8: f002 fd71 bl 80043de + 8001912: 2200 movs r2, #0 + 8001914: 2100 movs r1, #0 + 8001916: 2038 movs r0, #56 @ 0x38 + 8001918: f002 fdaf bl 800447a HAL_NVIC_EnableIRQ(DMA2_Channel1_IRQn); - 80018fc: 2038 movs r0, #56 @ 0x38 - 80018fe: f002 fd8a bl 8004416 + 800191c: 2038 movs r0, #56 @ 0x38 + 800191e: f002 fdc8 bl 80044b2 } - 8001902: bf00 nop - 8001904: 3708 adds r7, #8 - 8001906: 46bd mov sp, r7 - 8001908: bd80 pop {r7, pc} - 800190a: bf00 nop - 800190c: 40021000 .word 0x40021000 + 8001922: bf00 nop + 8001924: 3708 adds r7, #8 + 8001926: 46bd mov sp, r7 + 8001928: bd80 pop {r7, pc} + 800192a: bf00 nop + 800192c: 40021000 .word 0x40021000 -08001910 : +08001930 : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { - 8001910: b580 push {r7, lr} - 8001912: b08a sub sp, #40 @ 0x28 - 8001914: af00 add r7, sp, #0 + 8001930: b580 push {r7, lr} + 8001932: b08a sub sp, #40 @ 0x28 + 8001934: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; - 8001916: f107 0314 add.w r3, r7, #20 - 800191a: 2200 movs r2, #0 - 800191c: 601a str r2, [r3, #0] - 800191e: 605a str r2, [r3, #4] - 8001920: 609a str r2, [r3, #8] - 8001922: 60da str r2, [r3, #12] - 8001924: 611a str r2, [r3, #16] + 8001936: f107 0314 add.w r3, r7, #20 + 800193a: 2200 movs r2, #0 + 800193c: 601a str r2, [r3, #0] + 800193e: 605a str r2, [r3, #4] + 8001940: 609a str r2, [r3, #8] + 8001942: 60da str r2, [r3, #12] + 8001944: 611a str r2, [r3, #16] /* USER CODE BEGIN MX_GPIO_Init_1 */ /* USER CODE END MX_GPIO_Init_1 */ /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOF_CLK_ENABLE(); - 8001926: 4b3a ldr r3, [pc, #232] @ (8001a10 ) - 8001928: 695b ldr r3, [r3, #20] - 800192a: 4a39 ldr r2, [pc, #228] @ (8001a10 ) - 800192c: f443 0380 orr.w r3, r3, #4194304 @ 0x400000 - 8001930: 6153 str r3, [r2, #20] - 8001932: 4b37 ldr r3, [pc, #220] @ (8001a10 ) - 8001934: 695b ldr r3, [r3, #20] - 8001936: f403 0380 and.w r3, r3, #4194304 @ 0x400000 - 800193a: 613b str r3, [r7, #16] - 800193c: 693b ldr r3, [r7, #16] + 8001946: 4b3a ldr r3, [pc, #232] @ (8001a30 ) + 8001948: 695b ldr r3, [r3, #20] + 800194a: 4a39 ldr r2, [pc, #228] @ (8001a30 ) + 800194c: f443 0380 orr.w r3, r3, #4194304 @ 0x400000 + 8001950: 6153 str r3, [r2, #20] + 8001952: 4b37 ldr r3, [pc, #220] @ (8001a30 ) + 8001954: 695b ldr r3, [r3, #20] + 8001956: f403 0380 and.w r3, r3, #4194304 @ 0x400000 + 800195a: 613b str r3, [r7, #16] + 800195c: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOC_CLK_ENABLE(); - 800193e: 4b34 ldr r3, [pc, #208] @ (8001a10 ) - 8001940: 695b ldr r3, [r3, #20] - 8001942: 4a33 ldr r2, [pc, #204] @ (8001a10 ) - 8001944: f443 2300 orr.w r3, r3, #524288 @ 0x80000 - 8001948: 6153 str r3, [r2, #20] - 800194a: 4b31 ldr r3, [pc, #196] @ (8001a10 ) - 800194c: 695b ldr r3, [r3, #20] - 800194e: f403 2300 and.w r3, r3, #524288 @ 0x80000 - 8001952: 60fb str r3, [r7, #12] - 8001954: 68fb ldr r3, [r7, #12] + 800195e: 4b34 ldr r3, [pc, #208] @ (8001a30 ) + 8001960: 695b ldr r3, [r3, #20] + 8001962: 4a33 ldr r2, [pc, #204] @ (8001a30 ) + 8001964: f443 2300 orr.w r3, r3, #524288 @ 0x80000 + 8001968: 6153 str r3, [r2, #20] + 800196a: 4b31 ldr r3, [pc, #196] @ (8001a30 ) + 800196c: 695b ldr r3, [r3, #20] + 800196e: f403 2300 and.w r3, r3, #524288 @ 0x80000 + 8001972: 60fb str r3, [r7, #12] + 8001974: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOA_CLK_ENABLE(); - 8001956: 4b2e ldr r3, [pc, #184] @ (8001a10 ) - 8001958: 695b ldr r3, [r3, #20] - 800195a: 4a2d ldr r2, [pc, #180] @ (8001a10 ) - 800195c: f443 3300 orr.w r3, r3, #131072 @ 0x20000 - 8001960: 6153 str r3, [r2, #20] - 8001962: 4b2b ldr r3, [pc, #172] @ (8001a10 ) - 8001964: 695b ldr r3, [r3, #20] - 8001966: f403 3300 and.w r3, r3, #131072 @ 0x20000 - 800196a: 60bb str r3, [r7, #8] - 800196c: 68bb ldr r3, [r7, #8] + 8001976: 4b2e ldr r3, [pc, #184] @ (8001a30 ) + 8001978: 695b ldr r3, [r3, #20] + 800197a: 4a2d ldr r2, [pc, #180] @ (8001a30 ) + 800197c: f443 3300 orr.w r3, r3, #131072 @ 0x20000 + 8001980: 6153 str r3, [r2, #20] + 8001982: 4b2b ldr r3, [pc, #172] @ (8001a30 ) + 8001984: 695b ldr r3, [r3, #20] + 8001986: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 800198a: 60bb str r3, [r7, #8] + 800198c: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOB_CLK_ENABLE(); - 800196e: 4b28 ldr r3, [pc, #160] @ (8001a10 ) - 8001970: 695b ldr r3, [r3, #20] - 8001972: 4a27 ldr r2, [pc, #156] @ (8001a10 ) - 8001974: f443 2380 orr.w r3, r3, #262144 @ 0x40000 - 8001978: 6153 str r3, [r2, #20] - 800197a: 4b25 ldr r3, [pc, #148] @ (8001a10 ) - 800197c: 695b ldr r3, [r3, #20] - 800197e: f403 2380 and.w r3, r3, #262144 @ 0x40000 - 8001982: 607b str r3, [r7, #4] - 8001984: 687b ldr r3, [r7, #4] + 800198e: 4b28 ldr r3, [pc, #160] @ (8001a30 ) + 8001990: 695b ldr r3, [r3, #20] + 8001992: 4a27 ldr r2, [pc, #156] @ (8001a30 ) + 8001994: f443 2380 orr.w r3, r3, #262144 @ 0x40000 + 8001998: 6153 str r3, [r2, #20] + 800199a: 4b25 ldr r3, [pc, #148] @ (8001a30 ) + 800199c: 695b ldr r3, [r3, #20] + 800199e: f403 2380 and.w r3, r3, #262144 @ 0x40000 + 80019a2: 607b str r3, [r7, #4] + 80019a4: 687b ldr r3, [r7, #4] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOB, IN12_Pin|IN11_Pin|IN13_Pin|IN9_Pin - 8001986: 2200 movs r2, #0 - 8001988: f64f 7176 movw r1, #65398 @ 0xff76 - 800198c: 4821 ldr r0, [pc, #132] @ (8001a14 ) - 800198e: f003 f889 bl 8004aa4 + 80019a6: 2200 movs r2, #0 + 80019a8: f64f 7176 movw r1, #65398 @ 0xff76 + 80019ac: 4821 ldr r0, [pc, #132] @ (8001a34 ) + 80019ae: f003 f8c7 bl 8004b40 |IN3_Pin|IN8_Pin|IN5_Pin|IN4_Pin |DSEL0_Pin|DSEL1_Pin|PC_EN_Pin|IN7_Pin |IN10_Pin, GPIO_PIN_RESET); /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOC, LED4_Pin|LED3_Pin|LED2_Pin|LED1_Pin, GPIO_PIN_RESET); - 8001992: 2200 movs r2, #0 - 8001994: f44f 7170 mov.w r1, #960 @ 0x3c0 - 8001998: 481f ldr r0, [pc, #124] @ (8001a18 ) - 800199a: f003 f883 bl 8004aa4 + 80019b2: 2200 movs r2, #0 + 80019b4: f44f 7170 mov.w r1, #960 @ 0x3c0 + 80019b8: 481f ldr r0, [pc, #124] @ (8001a38 ) + 80019ba: f003 f8c1 bl 8004b40 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOA, IN2_Pin|IN1_Pin|IN6_Pin, GPIO_PIN_RESET); - 800199e: 2200 movs r2, #0 - 80019a0: f44f 61e0 mov.w r1, #1792 @ 0x700 - 80019a4: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 - 80019a8: f003 f87c bl 8004aa4 + 80019be: 2200 movs r2, #0 + 80019c0: f44f 61e0 mov.w r1, #1792 @ 0x700 + 80019c4: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 + 80019c8: f003 f8ba bl 8004b40 /*Configure GPIO pins : IN12_Pin IN11_Pin IN13_Pin IN9_Pin IN3_Pin IN8_Pin IN5_Pin IN4_Pin DSEL0_Pin DSEL1_Pin PC_EN_Pin IN7_Pin IN10_Pin */ GPIO_InitStruct.Pin = IN12_Pin|IN11_Pin|IN13_Pin|IN9_Pin - 80019ac: f64f 7376 movw r3, #65398 @ 0xff76 - 80019b0: 617b str r3, [r7, #20] + 80019cc: f64f 7376 movw r3, #65398 @ 0xff76 + 80019d0: 617b str r3, [r7, #20] |IN3_Pin|IN8_Pin|IN5_Pin|IN4_Pin |DSEL0_Pin|DSEL1_Pin|PC_EN_Pin|IN7_Pin |IN10_Pin; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; - 80019b2: 2301 movs r3, #1 - 80019b4: 61bb str r3, [r7, #24] + 80019d2: 2301 movs r3, #1 + 80019d4: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; - 80019b6: 2300 movs r3, #0 - 80019b8: 61fb str r3, [r7, #28] + 80019d6: 2300 movs r3, #0 + 80019d8: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - 80019ba: 2300 movs r3, #0 - 80019bc: 623b str r3, [r7, #32] + 80019da: 2300 movs r3, #0 + 80019dc: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); - 80019be: f107 0314 add.w r3, r7, #20 - 80019c2: 4619 mov r1, r3 - 80019c4: 4813 ldr r0, [pc, #76] @ (8001a14 ) - 80019c6: f002 fef3 bl 80047b0 + 80019de: f107 0314 add.w r3, r7, #20 + 80019e2: 4619 mov r1, r3 + 80019e4: 4813 ldr r0, [pc, #76] @ (8001a34 ) + 80019e6: f002 ff31 bl 800484c /*Configure GPIO pins : LED4_Pin LED3_Pin LED2_Pin LED1_Pin */ GPIO_InitStruct.Pin = LED4_Pin|LED3_Pin|LED2_Pin|LED1_Pin; - 80019ca: f44f 7370 mov.w r3, #960 @ 0x3c0 - 80019ce: 617b str r3, [r7, #20] + 80019ea: f44f 7370 mov.w r3, #960 @ 0x3c0 + 80019ee: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; - 80019d0: 2301 movs r3, #1 - 80019d2: 61bb str r3, [r7, #24] + 80019f0: 2301 movs r3, #1 + 80019f2: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; - 80019d4: 2300 movs r3, #0 - 80019d6: 61fb str r3, [r7, #28] + 80019f4: 2300 movs r3, #0 + 80019f6: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - 80019d8: 2300 movs r3, #0 - 80019da: 623b str r3, [r7, #32] + 80019f8: 2300 movs r3, #0 + 80019fa: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); - 80019dc: f107 0314 add.w r3, r7, #20 - 80019e0: 4619 mov r1, r3 - 80019e2: 480d ldr r0, [pc, #52] @ (8001a18 ) - 80019e4: f002 fee4 bl 80047b0 + 80019fc: f107 0314 add.w r3, r7, #20 + 8001a00: 4619 mov r1, r3 + 8001a02: 480d ldr r0, [pc, #52] @ (8001a38 ) + 8001a04: f002 ff22 bl 800484c /*Configure GPIO pins : IN2_Pin IN1_Pin IN6_Pin */ GPIO_InitStruct.Pin = IN2_Pin|IN1_Pin|IN6_Pin; - 80019e8: f44f 63e0 mov.w r3, #1792 @ 0x700 - 80019ec: 617b str r3, [r7, #20] + 8001a08: f44f 63e0 mov.w r3, #1792 @ 0x700 + 8001a0c: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; - 80019ee: 2301 movs r3, #1 - 80019f0: 61bb str r3, [r7, #24] + 8001a0e: 2301 movs r3, #1 + 8001a10: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; - 80019f2: 2300 movs r3, #0 - 80019f4: 61fb str r3, [r7, #28] + 8001a12: 2300 movs r3, #0 + 8001a14: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - 80019f6: 2300 movs r3, #0 - 80019f8: 623b str r3, [r7, #32] + 8001a16: 2300 movs r3, #0 + 8001a18: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - 80019fa: f107 0314 add.w r3, r7, #20 - 80019fe: 4619 mov r1, r3 - 8001a00: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 - 8001a04: f002 fed4 bl 80047b0 + 8001a1a: f107 0314 add.w r3, r7, #20 + 8001a1e: 4619 mov r1, r3 + 8001a20: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 + 8001a24: f002 ff12 bl 800484c /* USER CODE BEGIN MX_GPIO_Init_2 */ /* USER CODE END MX_GPIO_Init_2 */ } - 8001a08: bf00 nop - 8001a0a: 3728 adds r7, #40 @ 0x28 - 8001a0c: 46bd mov sp, r7 - 8001a0e: bd80 pop {r7, pc} - 8001a10: 40021000 .word 0x40021000 - 8001a14: 48000400 .word 0x48000400 - 8001a18: 48000800 .word 0x48000800 + 8001a28: bf00 nop + 8001a2a: 3728 adds r7, #40 @ 0x28 + 8001a2c: 46bd mov sp, r7 + 8001a2e: bd80 pop {r7, pc} + 8001a30: 40021000 .word 0x40021000 + 8001a34: 48000400 .word 0x48000400 + 8001a38: 48000800 .word 0x48000800 -08001a1c : +08001a3c : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { - 8001a1c: b480 push {r7} - 8001a1e: af00 add r7, sp, #0 + 8001a3c: b480 push {r7} + 8001a3e: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); - 8001a20: b672 cpsid i + 8001a40: b672 cpsid i } - 8001a22: bf00 nop + 8001a42: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) - 8001a24: bf00 nop - 8001a26: e7fd b.n 8001a24 - -08001a28 : + 8001a44: bf00 nop + 8001a46: e7fd b.n 8001a44 +08001a48 : extern enable_gpios update_ports; extern current_measurements current_measurements_adc_val; -volatile uint8_t error_data[16]; +volatile err_states error; +extern int inhibit_SDC; void check_plausibility() { - 8001a28: b480 push {r7} - 8001a2a: af00 add r7, sp, #0 - if (!update_ports.portb.sdc) {error_data[0] = 1;} - 8001a2c: 4b7e ldr r3, [pc, #504] @ (8001c28 ) - 8001a2e: 785b ldrb r3, [r3, #1] - 8001a30: f003 0302 and.w r3, r3, #2 - 8001a34: b2db uxtb r3, r3 - 8001a36: 2b00 cmp r3, #0 - 8001a38: d103 bne.n 8001a42 - 8001a3a: 4b7c ldr r3, [pc, #496] @ (8001c2c ) - 8001a3c: 2201 movs r2, #1 - 8001a3e: 701a strb r2, [r3, #0] - 8001a40: e002 b.n 8001a48 - else {error_data[0] = 0;} - 8001a42: 4b7a ldr r3, [pc, #488] @ (8001c2c ) - 8001a44: 2200 movs r2, #0 - 8001a46: 701a strb r2, [r3, #0] + 8001a48: b480 push {r7} + 8001a4a: af00 add r7, sp, #0 + if (!update_ports.portb.sdc || inhibit_SDC == 1) {error.group1.sdc_open = 1;} + 8001a4c: 4b9c ldr r3, [pc, #624] @ (8001cc0 ) + 8001a4e: 785b ldrb r3, [r3, #1] + 8001a50: f003 0302 and.w r3, r3, #2 + 8001a54: b2db uxtb r3, r3 + 8001a56: 2b00 cmp r3, #0 + 8001a58: d003 beq.n 8001a62 + 8001a5a: 4b9a ldr r3, [pc, #616] @ (8001cc4 ) + 8001a5c: 681b ldr r3, [r3, #0] + 8001a5e: 2b01 cmp r3, #1 + 8001a60: d105 bne.n 8001a6e + 8001a62: 4a99 ldr r2, [pc, #612] @ (8001cc8 ) + 8001a64: 7813 ldrb r3, [r2, #0] + 8001a66: f043 0301 orr.w r3, r3, #1 + 8001a6a: 7013 strb r3, [r2, #0] + 8001a6c: e004 b.n 8001a78 + else {error.group1.sdc_open = 0;} + 8001a6e: 4a96 ldr r2, [pc, #600] @ (8001cc8 ) + 8001a70: 7813 ldrb r3, [r2, #0] + 8001a72: f36f 0300 bfc r3, #0, #1 + 8001a76: 7013 strb r3, [r2, #0] if (update_ports.porta.acc_cooling == 1 && current_measurements_adc_val.acc_cooling == 0) { - 8001a48: 4b77 ldr r3, [pc, #476] @ (8001c28 ) - 8001a4a: 781b ldrb r3, [r3, #0] - 8001a4c: f003 0301 and.w r3, r3, #1 - 8001a50: b2db uxtb r3, r3 - 8001a52: 2b00 cmp r3, #0 - 8001a54: d007 beq.n 8001a66 - 8001a56: 4b76 ldr r3, [pc, #472] @ (8001c30 ) - 8001a58: 881b ldrh r3, [r3, #0] - 8001a5a: 2b00 cmp r3, #0 - 8001a5c: d103 bne.n 8001a66 - error_data[3] = 1; - 8001a5e: 4b73 ldr r3, [pc, #460] @ (8001c2c ) - 8001a60: 2201 movs r2, #1 - 8001a62: 70da strb r2, [r3, #3] - 8001a64: e002 b.n 8001a6c + 8001a78: 4b91 ldr r3, [pc, #580] @ (8001cc0 ) + 8001a7a: 781b ldrb r3, [r3, #0] + 8001a7c: f003 0301 and.w r3, r3, #1 + 8001a80: b2db uxtb r3, r3 + 8001a82: 2b00 cmp r3, #0 + 8001a84: d009 beq.n 8001a9a + 8001a86: 4b91 ldr r3, [pc, #580] @ (8001ccc ) + 8001a88: 881b ldrh r3, [r3, #0] + 8001a8a: 2b00 cmp r3, #0 + 8001a8c: d105 bne.n 8001a9a + error.group1.noload_acc_cooling = 1; + 8001a8e: 4a8e ldr r2, [pc, #568] @ (8001cc8 ) + 8001a90: 7813 ldrb r3, [r2, #0] + 8001a92: f043 0302 orr.w r3, r3, #2 + 8001a96: 7013 strb r3, [r2, #0] + 8001a98: e004 b.n 8001aa4 } else { - error_data[3] = 0; - 8001a66: 4b71 ldr r3, [pc, #452] @ (8001c2c ) - 8001a68: 2200 movs r2, #0 - 8001a6a: 70da strb r2, [r3, #3] + error.group1.noload_acc_cooling = 0; + 8001a9a: 4a8b ldr r2, [pc, #556] @ (8001cc8 ) + 8001a9c: 7813 ldrb r3, [r2, #0] + 8001a9e: f36f 0341 bfc r3, #1, #1 + 8001aa2: 7013 strb r3, [r2, #0] } if (update_ports.porta.ts_cooling == 1 && current_measurements_adc_val.ts_cooling == 0) { - 8001a6c: 4b6e ldr r3, [pc, #440] @ (8001c28 ) - 8001a6e: 781b ldrb r3, [r3, #0] - 8001a70: f003 0302 and.w r3, r3, #2 - 8001a74: b2db uxtb r3, r3 - 8001a76: 2b00 cmp r3, #0 - 8001a78: d007 beq.n 8001a8a - 8001a7a: 4b6d ldr r3, [pc, #436] @ (8001c30 ) - 8001a7c: 885b ldrh r3, [r3, #2] - 8001a7e: 2b00 cmp r3, #0 - 8001a80: d103 bne.n 8001a8a - error_data[4] = 1; - 8001a82: 4b6a ldr r3, [pc, #424] @ (8001c2c ) - 8001a84: 2201 movs r2, #1 - 8001a86: 711a strb r2, [r3, #4] - 8001a88: e002 b.n 8001a90 - } - else { - error_data[4] = 0; - 8001a8a: 4b68 ldr r3, [pc, #416] @ (8001c2c ) - 8001a8c: 2200 movs r2, #0 - 8001a8e: 711a strb r2, [r3, #4] - } + 8001aa4: 4b86 ldr r3, [pc, #536] @ (8001cc0 ) + 8001aa6: 781b ldrb r3, [r3, #0] + 8001aa8: f003 0302 and.w r3, r3, #2 + 8001aac: b2db uxtb r3, r3 + 8001aae: 2b00 cmp r3, #0 + 8001ab0: d009 beq.n 8001ac6 + 8001ab2: 4b86 ldr r3, [pc, #536] @ (8001ccc ) + 8001ab4: 885b ldrh r3, [r3, #2] + 8001ab6: 2b00 cmp r3, #0 + 8001ab8: d105 bne.n 8001ac6 + error.group1.noload_ts_cooling = 1; + 8001aba: 4a83 ldr r2, [pc, #524] @ (8001cc8 ) + 8001abc: 7813 ldrb r3, [r2, #0] + 8001abe: f043 0304 orr.w r3, r3, #4 + 8001ac2: 7013 strb r3, [r2, #0] + 8001ac4: e004 b.n 8001ad0 + } + else { + error.group1.noload_ts_cooling = 0; + 8001ac6: 4a80 ldr r2, [pc, #512] @ (8001cc8 ) + 8001ac8: 7813 ldrb r3, [r2, #0] + 8001aca: f36f 0382 bfc r3, #2, #1 + 8001ace: 7013 strb r3, [r2, #0] + } if (update_ports.porta.drs == 1 && current_measurements_adc_val.drs == 0) { - 8001a90: 4b65 ldr r3, [pc, #404] @ (8001c28 ) - 8001a92: 781b ldrb r3, [r3, #0] - 8001a94: f003 0304 and.w r3, r3, #4 - 8001a98: b2db uxtb r3, r3 - 8001a9a: 2b00 cmp r3, #0 - 8001a9c: d007 beq.n 8001aae - 8001a9e: 4b64 ldr r3, [pc, #400] @ (8001c30 ) - 8001aa0: 889b ldrh r3, [r3, #4] - 8001aa2: 2b00 cmp r3, #0 - 8001aa4: d103 bne.n 8001aae - error_data[5] = 1; - 8001aa6: 4b61 ldr r3, [pc, #388] @ (8001c2c ) - 8001aa8: 2201 movs r2, #1 - 8001aaa: 715a strb r2, [r3, #5] - 8001aac: e002 b.n 8001ab4 - } - else { - error_data[5] = 0; - 8001aae: 4b5f ldr r3, [pc, #380] @ (8001c2c ) - 8001ab0: 2200 movs r2, #0 - 8001ab2: 715a strb r2, [r3, #5] - } + 8001ad0: 4b7b ldr r3, [pc, #492] @ (8001cc0 ) + 8001ad2: 781b ldrb r3, [r3, #0] + 8001ad4: f003 0304 and.w r3, r3, #4 + 8001ad8: b2db uxtb r3, r3 + 8001ada: 2b00 cmp r3, #0 + 8001adc: d009 beq.n 8001af2 + 8001ade: 4b7b ldr r3, [pc, #492] @ (8001ccc ) + 8001ae0: 889b ldrh r3, [r3, #4] + 8001ae2: 2b00 cmp r3, #0 + 8001ae4: d105 bne.n 8001af2 + error.group1.noload_drs = 1; + 8001ae6: 4a78 ldr r2, [pc, #480] @ (8001cc8 ) + 8001ae8: 7813 ldrb r3, [r2, #0] + 8001aea: f043 0308 orr.w r3, r3, #8 + 8001aee: 7013 strb r3, [r2, #0] + 8001af0: e004 b.n 8001afc + } + else { + error.group1.noload_drs = 0; + 8001af2: 4a75 ldr r2, [pc, #468] @ (8001cc8 ) + 8001af4: 7813 ldrb r3, [r2, #0] + 8001af6: f36f 03c3 bfc r3, #3, #1 + 8001afa: 7013 strb r3, [r2, #0] + } if (update_ports.porta.acu == 1 && current_measurements_adc_val.acu == 0) { - 8001ab4: 4b5c ldr r3, [pc, #368] @ (8001c28 ) - 8001ab6: 781b ldrb r3, [r3, #0] - 8001ab8: f003 0308 and.w r3, r3, #8 - 8001abc: b2db uxtb r3, r3 - 8001abe: 2b00 cmp r3, #0 - 8001ac0: d007 beq.n 8001ad2 - 8001ac2: 4b5b ldr r3, [pc, #364] @ (8001c30 ) - 8001ac4: 88db ldrh r3, [r3, #6] - 8001ac6: 2b00 cmp r3, #0 - 8001ac8: d103 bne.n 8001ad2 - error_data[6] = 1; - 8001aca: 4b58 ldr r3, [pc, #352] @ (8001c2c ) - 8001acc: 2201 movs r2, #1 - 8001ace: 719a strb r2, [r3, #6] - 8001ad0: e002 b.n 8001ad8 - } - else { - error_data[6] = 0; - 8001ad2: 4b56 ldr r3, [pc, #344] @ (8001c2c ) - 8001ad4: 2200 movs r2, #0 - 8001ad6: 719a strb r2, [r3, #6] - } - - if (update_ports.porta.epsc == 1 && current_measurements_adc_val.epsc == 0) { - 8001ad8: 4b53 ldr r3, [pc, #332] @ (8001c28 ) - 8001ada: 781b ldrb r3, [r3, #0] - 8001adc: f003 0310 and.w r3, r3, #16 - 8001ae0: b2db uxtb r3, r3 - 8001ae2: 2b00 cmp r3, #0 - 8001ae4: d007 beq.n 8001af6 - 8001ae6: 4b52 ldr r3, [pc, #328] @ (8001c30 ) - 8001ae8: 891b ldrh r3, [r3, #8] - 8001aea: 2b00 cmp r3, #0 - 8001aec: d103 bne.n 8001af6 - error_data[7] = 1; - 8001aee: 4b4f ldr r3, [pc, #316] @ (8001c2c ) - 8001af0: 2201 movs r2, #1 - 8001af2: 71da strb r2, [r3, #7] - 8001af4: e002 b.n 8001afc - } - else { - error_data[7] = 0; - 8001af6: 4b4d ldr r3, [pc, #308] @ (8001c2c ) - 8001af8: 2200 movs r2, #0 - 8001afa: 71da strb r2, [r3, #7] - } - - if (update_ports.porta.inverter == 1 && current_measurements_adc_val.inverter == 0) { - 8001afc: 4b4a ldr r3, [pc, #296] @ (8001c28 ) + 8001afc: 4b70 ldr r3, [pc, #448] @ (8001cc0 ) 8001afe: 781b ldrb r3, [r3, #0] - 8001b00: f003 0320 and.w r3, r3, #32 + 8001b00: f003 0308 and.w r3, r3, #8 8001b04: b2db uxtb r3, r3 8001b06: 2b00 cmp r3, #0 - 8001b08: d007 beq.n 8001b1a - 8001b0a: 4b49 ldr r3, [pc, #292] @ (8001c30 ) - 8001b0c: 895b ldrh r3, [r3, #10] + 8001b08: d009 beq.n 8001b1e + 8001b0a: 4b70 ldr r3, [pc, #448] @ (8001ccc ) + 8001b0c: 88db ldrh r3, [r3, #6] 8001b0e: 2b00 cmp r3, #0 - 8001b10: d103 bne.n 8001b1a - error_data[8] = 3; - 8001b12: 4b46 ldr r3, [pc, #280] @ (8001c2c ) - 8001b14: 2203 movs r2, #3 - 8001b16: 721a strb r2, [r3, #8] - 8001b18: e002 b.n 8001b20 - } - else { - error_data[8] = 2; - 8001b1a: 4b44 ldr r3, [pc, #272] @ (8001c2c ) - 8001b1c: 2202 movs r2, #2 - 8001b1e: 721a strb r2, [r3, #8] - } + 8001b10: d105 bne.n 8001b1e + error.group1.noload_acu = 1; + 8001b12: 4a6d ldr r2, [pc, #436] @ (8001cc8 ) + 8001b14: 7813 ldrb r3, [r2, #0] + 8001b16: f043 0310 orr.w r3, r3, #16 + 8001b1a: 7013 strb r3, [r2, #0] + 8001b1c: e004 b.n 8001b28 + } + else { + error.group1.noload_acu = 0; + 8001b1e: 4a6a ldr r2, [pc, #424] @ (8001cc8 ) + 8001b20: 7813 ldrb r3, [r2, #0] + 8001b22: f36f 1304 bfc r3, #4, #1 + 8001b26: 7013 strb r3, [r2, #0] + } + + if (update_ports.porta.epsc == 1 && current_measurements_adc_val.epsc == 0) { + 8001b28: 4b65 ldr r3, [pc, #404] @ (8001cc0 ) + 8001b2a: 781b ldrb r3, [r3, #0] + 8001b2c: f003 0310 and.w r3, r3, #16 + 8001b30: b2db uxtb r3, r3 + 8001b32: 2b00 cmp r3, #0 + 8001b34: d009 beq.n 8001b4a + 8001b36: 4b65 ldr r3, [pc, #404] @ (8001ccc ) + 8001b38: 891b ldrh r3, [r3, #8] + 8001b3a: 2b00 cmp r3, #0 + 8001b3c: d105 bne.n 8001b4a + error.group1.noload_epsc = 1; + 8001b3e: 4a62 ldr r2, [pc, #392] @ (8001cc8 ) + 8001b40: 7813 ldrb r3, [r2, #0] + 8001b42: f043 0320 orr.w r3, r3, #32 + 8001b46: 7013 strb r3, [r2, #0] + 8001b48: e004 b.n 8001b54 + } + else { + error.group1.noload_epsc = 0; + 8001b4a: 4a5f ldr r2, [pc, #380] @ (8001cc8 ) + 8001b4c: 7813 ldrb r3, [r2, #0] + 8001b4e: f36f 1345 bfc r3, #5, #1 + 8001b52: 7013 strb r3, [r2, #0] + } + + if (update_ports.porta.inverter == 1 && current_measurements_adc_val.inverter == 0) { + 8001b54: 4b5a ldr r3, [pc, #360] @ (8001cc0 ) + 8001b56: 781b ldrb r3, [r3, #0] + 8001b58: f003 0320 and.w r3, r3, #32 + 8001b5c: b2db uxtb r3, r3 + 8001b5e: 2b00 cmp r3, #0 + 8001b60: d009 beq.n 8001b76 + 8001b62: 4b5a ldr r3, [pc, #360] @ (8001ccc ) + 8001b64: 895b ldrh r3, [r3, #10] + 8001b66: 2b00 cmp r3, #0 + 8001b68: d105 bne.n 8001b76 + error.group1.noload_inverter = 1; + 8001b6a: 4a57 ldr r2, [pc, #348] @ (8001cc8 ) + 8001b6c: 7813 ldrb r3, [r2, #0] + 8001b6e: f043 0340 orr.w r3, r3, #64 @ 0x40 + 8001b72: 7013 strb r3, [r2, #0] + 8001b74: e004 b.n 8001b80 + } + else { + error.group1.noload_inverter = 0; + 8001b76: 4a54 ldr r2, [pc, #336] @ (8001cc8 ) + 8001b78: 7813 ldrb r3, [r2, #0] + 8001b7a: f36f 1386 bfc r3, #6, #1 + 8001b7e: 7013 strb r3, [r2, #0] + } if (update_ports.porta.lidar == 1 && current_measurements_adc_val.lidar == 0) { - 8001b20: 4b41 ldr r3, [pc, #260] @ (8001c28 ) - 8001b22: 781b ldrb r3, [r3, #0] - 8001b24: f003 0340 and.w r3, r3, #64 @ 0x40 - 8001b28: b2db uxtb r3, r3 - 8001b2a: 2b00 cmp r3, #0 - 8001b2c: d007 beq.n 8001b3e - 8001b2e: 4b40 ldr r3, [pc, #256] @ (8001c30 ) - 8001b30: 899b ldrh r3, [r3, #12] - 8001b32: 2b00 cmp r3, #0 - 8001b34: d103 bne.n 8001b3e - error_data[9] = 3; - 8001b36: 4b3d ldr r3, [pc, #244] @ (8001c2c ) - 8001b38: 2203 movs r2, #3 - 8001b3a: 725a strb r2, [r3, #9] - 8001b3c: e002 b.n 8001b44 - } - else { - error_data[9] = 2; - 8001b3e: 4b3b ldr r3, [pc, #236] @ (8001c2c ) - 8001b40: 2202 movs r2, #2 - 8001b42: 725a strb r2, [r3, #9] - } + 8001b80: 4b4f ldr r3, [pc, #316] @ (8001cc0 ) + 8001b82: 781b ldrb r3, [r3, #0] + 8001b84: f003 0340 and.w r3, r3, #64 @ 0x40 + 8001b88: b2db uxtb r3, r3 + 8001b8a: 2b00 cmp r3, #0 + 8001b8c: d009 beq.n 8001ba2 + 8001b8e: 4b4f ldr r3, [pc, #316] @ (8001ccc ) + 8001b90: 899b ldrh r3, [r3, #12] + 8001b92: 2b00 cmp r3, #0 + 8001b94: d105 bne.n 8001ba2 + error.group1.noload_lidar = 1; + 8001b96: 4a4c ldr r2, [pc, #304] @ (8001cc8 ) + 8001b98: 7813 ldrb r3, [r2, #0] + 8001b9a: f043 0380 orr.w r3, r3, #128 @ 0x80 + 8001b9e: 7013 strb r3, [r2, #0] + 8001ba0: e004 b.n 8001bac + } + else { + error.group1.noload_lidar = 0; + 8001ba2: 4a49 ldr r2, [pc, #292] @ (8001cc8 ) + 8001ba4: 7813 ldrb r3, [r2, #0] + 8001ba6: f36f 13c7 bfc r3, #7, #1 + 8001baa: 7013 strb r3, [r2, #0] + } if (update_ports.porta.misc == 1 && current_measurements_adc_val.misc == 0) { - 8001b44: 4b38 ldr r3, [pc, #224] @ (8001c28 ) - 8001b46: 781b ldrb r3, [r3, #0] - 8001b48: f023 037f bic.w r3, r3, #127 @ 0x7f - 8001b4c: b2db uxtb r3, r3 - 8001b4e: 2b00 cmp r3, #0 - 8001b50: d007 beq.n 8001b62 - 8001b52: 4b37 ldr r3, [pc, #220] @ (8001c30 ) - 8001b54: 89db ldrh r3, [r3, #14] - 8001b56: 2b00 cmp r3, #0 - 8001b58: d103 bne.n 8001b62 - error_data[10] = 3; - 8001b5a: 4b34 ldr r3, [pc, #208] @ (8001c2c ) - 8001b5c: 2203 movs r2, #3 - 8001b5e: 729a strb r2, [r3, #10] - 8001b60: e002 b.n 8001b68 - } - else { - error_data[10] = 2; - 8001b62: 4b32 ldr r3, [pc, #200] @ (8001c2c ) - 8001b64: 2202 movs r2, #2 - 8001b66: 729a strb r2, [r3, #10] - } + 8001bac: 4b44 ldr r3, [pc, #272] @ (8001cc0 ) + 8001bae: 781b ldrb r3, [r3, #0] + 8001bb0: f023 037f bic.w r3, r3, #127 @ 0x7f + 8001bb4: b2db uxtb r3, r3 + 8001bb6: 2b00 cmp r3, #0 + 8001bb8: d009 beq.n 8001bce + 8001bba: 4b44 ldr r3, [pc, #272] @ (8001ccc ) + 8001bbc: 89db ldrh r3, [r3, #14] + 8001bbe: 2b00 cmp r3, #0 + 8001bc0: d105 bne.n 8001bce + error.group2.noload_misc = 1; + 8001bc2: 4a41 ldr r2, [pc, #260] @ (8001cc8 ) + 8001bc4: 7853 ldrb r3, [r2, #1] + 8001bc6: f043 0301 orr.w r3, r3, #1 + 8001bca: 7053 strb r3, [r2, #1] + 8001bcc: e004 b.n 8001bd8 + } + else { + error.group2.noload_misc = 0; + 8001bce: 4a3e ldr r2, [pc, #248] @ (8001cc8 ) + 8001bd0: 7853 ldrb r3, [r2, #1] + 8001bd2: f36f 0300 bfc r3, #0, #1 + 8001bd6: 7053 strb r3, [r2, #1] + } if (update_ports.portb.alwayson == 1 && current_measurements_adc_val.alwayson == 0) { - 8001b68: 4b2f ldr r3, [pc, #188] @ (8001c28 ) - 8001b6a: 785b ldrb r3, [r3, #1] - 8001b6c: f003 0301 and.w r3, r3, #1 - 8001b70: b2db uxtb r3, r3 - 8001b72: 2b00 cmp r3, #0 - 8001b74: d007 beq.n 8001b86 - 8001b76: 4b2e ldr r3, [pc, #184] @ (8001c30 ) - 8001b78: 8a1b ldrh r3, [r3, #16] - 8001b7a: 2b00 cmp r3, #0 - 8001b7c: d103 bne.n 8001b86 - error_data[11] = 3; - 8001b7e: 4b2b ldr r3, [pc, #172] @ (8001c2c ) - 8001b80: 2203 movs r2, #3 - 8001b82: 72da strb r2, [r3, #11] - 8001b84: e002 b.n 8001b8c - } - else { - error_data[11] = 2; - 8001b86: 4b29 ldr r3, [pc, #164] @ (8001c2c ) - 8001b88: 2202 movs r2, #2 - 8001b8a: 72da strb r2, [r3, #11] - } + 8001bd8: 4b39 ldr r3, [pc, #228] @ (8001cc0 ) + 8001bda: 785b ldrb r3, [r3, #1] + 8001bdc: f003 0301 and.w r3, r3, #1 + 8001be0: b2db uxtb r3, r3 + 8001be2: 2b00 cmp r3, #0 + 8001be4: d009 beq.n 8001bfa + 8001be6: 4b39 ldr r3, [pc, #228] @ (8001ccc ) + 8001be8: 8a1b ldrh r3, [r3, #16] + 8001bea: 2b00 cmp r3, #0 + 8001bec: d105 bne.n 8001bfa + error.group2.noload_alwayson = 1; + 8001bee: 4a36 ldr r2, [pc, #216] @ (8001cc8 ) + 8001bf0: 7853 ldrb r3, [r2, #1] + 8001bf2: f043 0302 orr.w r3, r3, #2 + 8001bf6: 7053 strb r3, [r2, #1] + 8001bf8: e004 b.n 8001c04 + } + else { + error.group2.noload_alwayson = 0; + 8001bfa: 4a33 ldr r2, [pc, #204] @ (8001cc8 ) + 8001bfc: 7853 ldrb r3, [r2, #1] + 8001bfe: f36f 0341 bfc r3, #1, #1 + 8001c02: 7053 strb r3, [r2, #1] + } if (update_ports.portb.sdc == 1 && current_measurements_adc_val.sdc == 0) { - 8001b8c: 4b26 ldr r3, [pc, #152] @ (8001c28 ) - 8001b8e: 785b ldrb r3, [r3, #1] - 8001b90: f003 0302 and.w r3, r3, #2 - 8001b94: b2db uxtb r3, r3 - 8001b96: 2b00 cmp r3, #0 - 8001b98: d007 beq.n 8001baa - 8001b9a: 4b25 ldr r3, [pc, #148] @ (8001c30 ) - 8001b9c: 8a5b ldrh r3, [r3, #18] - 8001b9e: 2b00 cmp r3, #0 - 8001ba0: d103 bne.n 8001baa - error_data[12] = 3; - 8001ba2: 4b22 ldr r3, [pc, #136] @ (8001c2c ) - 8001ba4: 2203 movs r2, #3 - 8001ba6: 731a strb r2, [r3, #12] - 8001ba8: e002 b.n 8001bb0 - } - else { - error_data[12] = 2; - 8001baa: 4b20 ldr r3, [pc, #128] @ (8001c2c ) - 8001bac: 2202 movs r2, #2 - 8001bae: 731a strb r2, [r3, #12] - } + 8001c04: 4b2e ldr r3, [pc, #184] @ (8001cc0 ) + 8001c06: 785b ldrb r3, [r3, #1] + 8001c08: f003 0302 and.w r3, r3, #2 + 8001c0c: b2db uxtb r3, r3 + 8001c0e: 2b00 cmp r3, #0 + 8001c10: d009 beq.n 8001c26 + 8001c12: 4b2e ldr r3, [pc, #184] @ (8001ccc ) + 8001c14: 8a5b ldrh r3, [r3, #18] + 8001c16: 2b00 cmp r3, #0 + 8001c18: d105 bne.n 8001c26 + error.group2.noload_sdc = 1; + 8001c1a: 4a2b ldr r2, [pc, #172] @ (8001cc8 ) + 8001c1c: 7853 ldrb r3, [r2, #1] + 8001c1e: f043 0304 orr.w r3, r3, #4 + 8001c22: 7053 strb r3, [r2, #1] + 8001c24: e004 b.n 8001c30 + } + else { + error.group2.noload_sdc = 0; + 8001c26: 4a28 ldr r2, [pc, #160] @ (8001cc8 ) + 8001c28: 7853 ldrb r3, [r2, #1] + 8001c2a: f36f 0382 bfc r3, #2, #1 + 8001c2e: 7053 strb r3, [r2, #1] + } if (update_ports.portb.ebs1 == 1 && current_measurements_adc_val.ebs1 == 0) { - 8001bb0: 4b1d ldr r3, [pc, #116] @ (8001c28 ) - 8001bb2: 785b ldrb r3, [r3, #1] - 8001bb4: f003 0304 and.w r3, r3, #4 - 8001bb8: b2db uxtb r3, r3 - 8001bba: 2b00 cmp r3, #0 - 8001bbc: d007 beq.n 8001bce - 8001bbe: 4b1c ldr r3, [pc, #112] @ (8001c30 ) - 8001bc0: 8a9b ldrh r3, [r3, #20] - 8001bc2: 2b00 cmp r3, #0 - 8001bc4: d103 bne.n 8001bce - error_data[13] = 3; - 8001bc6: 4b19 ldr r3, [pc, #100] @ (8001c2c ) - 8001bc8: 2203 movs r2, #3 - 8001bca: 735a strb r2, [r3, #13] - 8001bcc: e002 b.n 8001bd4 - } - else { - error_data[13] = 2; - 8001bce: 4b17 ldr r3, [pc, #92] @ (8001c2c ) - 8001bd0: 2202 movs r2, #2 - 8001bd2: 735a strb r2, [r3, #13] - } + 8001c30: 4b23 ldr r3, [pc, #140] @ (8001cc0 ) + 8001c32: 785b ldrb r3, [r3, #1] + 8001c34: f003 0304 and.w r3, r3, #4 + 8001c38: b2db uxtb r3, r3 + 8001c3a: 2b00 cmp r3, #0 + 8001c3c: d009 beq.n 8001c52 + 8001c3e: 4b23 ldr r3, [pc, #140] @ (8001ccc ) + 8001c40: 8a9b ldrh r3, [r3, #20] + 8001c42: 2b00 cmp r3, #0 + 8001c44: d105 bne.n 8001c52 + error.group2.noload_ebs1 = 1; + 8001c46: 4a20 ldr r2, [pc, #128] @ (8001cc8 ) + 8001c48: 7853 ldrb r3, [r2, #1] + 8001c4a: f043 0308 orr.w r3, r3, #8 + 8001c4e: 7053 strb r3, [r2, #1] + 8001c50: e004 b.n 8001c5c + } + else { + error.group2.noload_ebs1 = 0; + 8001c52: 4a1d ldr r2, [pc, #116] @ (8001cc8 ) + 8001c54: 7853 ldrb r3, [r2, #1] + 8001c56: f36f 03c3 bfc r3, #3, #1 + 8001c5a: 7053 strb r3, [r2, #1] + } if (update_ports.portb.ebs2 == 1 && current_measurements_adc_val.ebs2 == 0) { - 8001bd4: 4b14 ldr r3, [pc, #80] @ (8001c28 ) - 8001bd6: 785b ldrb r3, [r3, #1] - 8001bd8: f003 0308 and.w r3, r3, #8 - 8001bdc: b2db uxtb r3, r3 - 8001bde: 2b00 cmp r3, #0 - 8001be0: d007 beq.n 8001bf2 - 8001be2: 4b13 ldr r3, [pc, #76] @ (8001c30 ) - 8001be4: 8adb ldrh r3, [r3, #22] - 8001be6: 2b00 cmp r3, #0 - 8001be8: d103 bne.n 8001bf2 - error_data[14] = 3; - 8001bea: 4b10 ldr r3, [pc, #64] @ (8001c2c ) - 8001bec: 2203 movs r2, #3 - 8001bee: 739a strb r2, [r3, #14] - 8001bf0: e002 b.n 8001bf8 - } - else { - error_data[14] = 2; - 8001bf2: 4b0e ldr r3, [pc, #56] @ (8001c2c ) - 8001bf4: 2202 movs r2, #2 - 8001bf6: 739a strb r2, [r3, #14] - } + 8001c5c: 4b18 ldr r3, [pc, #96] @ (8001cc0 ) + 8001c5e: 785b ldrb r3, [r3, #1] + 8001c60: f003 0308 and.w r3, r3, #8 + 8001c64: b2db uxtb r3, r3 + 8001c66: 2b00 cmp r3, #0 + 8001c68: d009 beq.n 8001c7e + 8001c6a: 4b18 ldr r3, [pc, #96] @ (8001ccc ) + 8001c6c: 8adb ldrh r3, [r3, #22] + 8001c6e: 2b00 cmp r3, #0 + 8001c70: d105 bne.n 8001c7e + error.group2.noload_ebs2 = 1; + 8001c72: 4a15 ldr r2, [pc, #84] @ (8001cc8 ) + 8001c74: 7853 ldrb r3, [r2, #1] + 8001c76: f043 0310 orr.w r3, r3, #16 + 8001c7a: 7053 strb r3, [r2, #1] + 8001c7c: e004 b.n 8001c88 + } + else { + error.group2.noload_ebs2 = 0; + 8001c7e: 4a12 ldr r2, [pc, #72] @ (8001cc8 ) + 8001c80: 7853 ldrb r3, [r2, #1] + 8001c82: f36f 1304 bfc r3, #4, #1 + 8001c86: 7053 strb r3, [r2, #1] + } if (update_ports.portb.ebs3 == 1 && current_measurements_adc_val.ebs3 == 0) { - 8001bf8: 4b0b ldr r3, [pc, #44] @ (8001c28 ) - 8001bfa: 785b ldrb r3, [r3, #1] - 8001bfc: f003 0310 and.w r3, r3, #16 - 8001c00: b2db uxtb r3, r3 - 8001c02: 2b00 cmp r3, #0 - 8001c04: d007 beq.n 8001c16 - 8001c06: 4b0a ldr r3, [pc, #40] @ (8001c30 ) - 8001c08: 8b1b ldrh r3, [r3, #24] - 8001c0a: 2b00 cmp r3, #0 - 8001c0c: d103 bne.n 8001c16 - error_data[15] = 3; - 8001c0e: 4b07 ldr r3, [pc, #28] @ (8001c2c ) - 8001c10: 2203 movs r2, #3 - 8001c12: 73da strb r2, [r3, #15] - 8001c14: e003 b.n 8001c1e - } - else { - error_data[15] = 2; - 8001c16: 4b05 ldr r3, [pc, #20] @ (8001c2c ) - 8001c18: 2202 movs r2, #2 - 8001c1a: 73da strb r2, [r3, #15] - } + 8001c88: 4b0d ldr r3, [pc, #52] @ (8001cc0 ) + 8001c8a: 785b ldrb r3, [r3, #1] + 8001c8c: f003 0310 and.w r3, r3, #16 + 8001c90: b2db uxtb r3, r3 + 8001c92: 2b00 cmp r3, #0 + 8001c94: d009 beq.n 8001caa + 8001c96: 4b0d ldr r3, [pc, #52] @ (8001ccc ) + 8001c98: 8b1b ldrh r3, [r3, #24] + 8001c9a: 2b00 cmp r3, #0 + 8001c9c: d105 bne.n 8001caa + error.group2.noload_ebs3 = 1; + 8001c9e: 4a0a ldr r2, [pc, #40] @ (8001cc8 ) + 8001ca0: 7853 ldrb r3, [r2, #1] + 8001ca2: f043 0320 orr.w r3, r3, #32 + 8001ca6: 7053 strb r3, [r2, #1] + 8001ca8: e005 b.n 8001cb6 + } + else { + error.group2.noload_ebs3 = 0; + 8001caa: 4a07 ldr r2, [pc, #28] @ (8001cc8 ) + 8001cac: 7853 ldrb r3, [r2, #1] + 8001cae: f36f 1345 bfc r3, #5, #1 + 8001cb2: 7053 strb r3, [r2, #1] + } } - 8001c1c: bf00 nop - 8001c1e: bf00 nop - 8001c20: 46bd mov sp, r7 - 8001c22: f85d 7b04 ldr.w r7, [sp], #4 - 8001c26: 4770 bx lr - 8001c28: 200002e8 .word 0x200002e8 - 8001c2c: 200002f4 .word 0x200002f4 - 8001c30: 20000098 .word 0x20000098 + 8001cb4: bf00 nop + 8001cb6: bf00 nop + 8001cb8: 46bd mov sp, r7 + 8001cba: f85d 7b04 ldr.w r7, [sp], #4 + 8001cbe: 4770 bx lr + 8001cc0: 200002e8 .word 0x200002e8 + 8001cc4: 200002f0 .word 0x200002f0 + 8001cc8: 200002f4 .word 0x200002f4 + 8001ccc: 20000098 .word 0x20000098 -08001c34 : +08001cd0 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { - 8001c34: b480 push {r7} - 8001c36: b083 sub sp, #12 - 8001c38: af00 add r7, sp, #0 + 8001cd0: b480 push {r7} + 8001cd2: b083 sub sp, #12 + 8001cd4: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_SYSCFG_CLK_ENABLE(); - 8001c3a: 4b0f ldr r3, [pc, #60] @ (8001c78 ) - 8001c3c: 699b ldr r3, [r3, #24] - 8001c3e: 4a0e ldr r2, [pc, #56] @ (8001c78 ) - 8001c40: f043 0301 orr.w r3, r3, #1 - 8001c44: 6193 str r3, [r2, #24] - 8001c46: 4b0c ldr r3, [pc, #48] @ (8001c78 ) - 8001c48: 699b ldr r3, [r3, #24] - 8001c4a: f003 0301 and.w r3, r3, #1 - 8001c4e: 607b str r3, [r7, #4] - 8001c50: 687b ldr r3, [r7, #4] + 8001cd6: 4b0f ldr r3, [pc, #60] @ (8001d14 ) + 8001cd8: 699b ldr r3, [r3, #24] + 8001cda: 4a0e ldr r2, [pc, #56] @ (8001d14 ) + 8001cdc: f043 0301 orr.w r3, r3, #1 + 8001ce0: 6193 str r3, [r2, #24] + 8001ce2: 4b0c ldr r3, [pc, #48] @ (8001d14 ) + 8001ce4: 699b ldr r3, [r3, #24] + 8001ce6: f003 0301 and.w r3, r3, #1 + 8001cea: 607b str r3, [r7, #4] + 8001cec: 687b ldr r3, [r7, #4] __HAL_RCC_PWR_CLK_ENABLE(); - 8001c52: 4b09 ldr r3, [pc, #36] @ (8001c78 ) - 8001c54: 69db ldr r3, [r3, #28] - 8001c56: 4a08 ldr r2, [pc, #32] @ (8001c78 ) - 8001c58: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 - 8001c5c: 61d3 str r3, [r2, #28] - 8001c5e: 4b06 ldr r3, [pc, #24] @ (8001c78 ) - 8001c60: 69db ldr r3, [r3, #28] - 8001c62: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 - 8001c66: 603b str r3, [r7, #0] - 8001c68: 683b ldr r3, [r7, #0] + 8001cee: 4b09 ldr r3, [pc, #36] @ (8001d14 ) + 8001cf0: 69db ldr r3, [r3, #28] + 8001cf2: 4a08 ldr r2, [pc, #32] @ (8001d14 ) + 8001cf4: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 8001cf8: 61d3 str r3, [r2, #28] + 8001cfa: 4b06 ldr r3, [pc, #24] @ (8001d14 ) + 8001cfc: 69db ldr r3, [r3, #28] + 8001cfe: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 8001d02: 603b str r3, [r7, #0] + 8001d04: 683b ldr r3, [r7, #0] /* System interrupt init*/ /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } - 8001c6a: bf00 nop - 8001c6c: 370c adds r7, #12 - 8001c6e: 46bd mov sp, r7 - 8001c70: f85d 7b04 ldr.w r7, [sp], #4 - 8001c74: 4770 bx lr - 8001c76: bf00 nop - 8001c78: 40021000 .word 0x40021000 + 8001d06: bf00 nop + 8001d08: 370c adds r7, #12 + 8001d0a: 46bd mov sp, r7 + 8001d0c: f85d 7b04 ldr.w r7, [sp], #4 + 8001d10: 4770 bx lr + 8001d12: bf00 nop + 8001d14: 40021000 .word 0x40021000 -08001c7c : +08001d18 : * This function configures the hardware resources used in this example * @param hadc: ADC handle pointer * @retval None */ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) { - 8001c7c: b580 push {r7, lr} - 8001c7e: b08e sub sp, #56 @ 0x38 - 8001c80: af00 add r7, sp, #0 - 8001c82: 6078 str r0, [r7, #4] + 8001d18: b580 push {r7, lr} + 8001d1a: b08e sub sp, #56 @ 0x38 + 8001d1c: af00 add r7, sp, #0 + 8001d1e: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; - 8001c84: f107 0324 add.w r3, r7, #36 @ 0x24 - 8001c88: 2200 movs r2, #0 - 8001c8a: 601a str r2, [r3, #0] - 8001c8c: 605a str r2, [r3, #4] - 8001c8e: 609a str r2, [r3, #8] - 8001c90: 60da str r2, [r3, #12] - 8001c92: 611a str r2, [r3, #16] + 8001d20: f107 0324 add.w r3, r7, #36 @ 0x24 + 8001d24: 2200 movs r2, #0 + 8001d26: 601a str r2, [r3, #0] + 8001d28: 605a str r2, [r3, #4] + 8001d2a: 609a str r2, [r3, #8] + 8001d2c: 60da str r2, [r3, #12] + 8001d2e: 611a str r2, [r3, #16] if(hadc->Instance==ADC1) - 8001c94: 687b ldr r3, [r7, #4] - 8001c96: 681b ldr r3, [r3, #0] - 8001c98: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 - 8001c9c: f040 808f bne.w 8001dbe + 8001d30: 687b ldr r3, [r7, #4] + 8001d32: 681b ldr r3, [r3, #0] + 8001d34: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 + 8001d38: f040 808f bne.w 8001e5a { /* USER CODE BEGIN ADC1_MspInit 0 */ /* USER CODE END ADC1_MspInit 0 */ /* Peripheral clock enable */ HAL_RCC_ADC12_CLK_ENABLED++; - 8001ca0: 4b86 ldr r3, [pc, #536] @ (8001ebc ) - 8001ca2: 681b ldr r3, [r3, #0] - 8001ca4: 3301 adds r3, #1 - 8001ca6: 4a85 ldr r2, [pc, #532] @ (8001ebc ) - 8001ca8: 6013 str r3, [r2, #0] + 8001d3c: 4b86 ldr r3, [pc, #536] @ (8001f58 ) + 8001d3e: 681b ldr r3, [r3, #0] + 8001d40: 3301 adds r3, #1 + 8001d42: 4a85 ldr r2, [pc, #532] @ (8001f58 ) + 8001d44: 6013 str r3, [r2, #0] if(HAL_RCC_ADC12_CLK_ENABLED==1){ - 8001caa: 4b84 ldr r3, [pc, #528] @ (8001ebc ) - 8001cac: 681b ldr r3, [r3, #0] - 8001cae: 2b01 cmp r3, #1 - 8001cb0: d10b bne.n 8001cca + 8001d46: 4b84 ldr r3, [pc, #528] @ (8001f58 ) + 8001d48: 681b ldr r3, [r3, #0] + 8001d4a: 2b01 cmp r3, #1 + 8001d4c: d10b bne.n 8001d66 __HAL_RCC_ADC12_CLK_ENABLE(); - 8001cb2: 4b83 ldr r3, [pc, #524] @ (8001ec0 ) - 8001cb4: 695b ldr r3, [r3, #20] - 8001cb6: 4a82 ldr r2, [pc, #520] @ (8001ec0 ) - 8001cb8: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 - 8001cbc: 6153 str r3, [r2, #20] - 8001cbe: 4b80 ldr r3, [pc, #512] @ (8001ec0 ) - 8001cc0: 695b ldr r3, [r3, #20] - 8001cc2: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 - 8001cc6: 623b str r3, [r7, #32] - 8001cc8: 6a3b ldr r3, [r7, #32] + 8001d4e: 4b83 ldr r3, [pc, #524] @ (8001f5c ) + 8001d50: 695b ldr r3, [r3, #20] + 8001d52: 4a82 ldr r2, [pc, #520] @ (8001f5c ) + 8001d54: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 8001d58: 6153 str r3, [r2, #20] + 8001d5a: 4b80 ldr r3, [pc, #512] @ (8001f5c ) + 8001d5c: 695b ldr r3, [r3, #20] + 8001d5e: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 8001d62: 623b str r3, [r7, #32] + 8001d64: 6a3b ldr r3, [r7, #32] } __HAL_RCC_GPIOC_CLK_ENABLE(); - 8001cca: 4b7d ldr r3, [pc, #500] @ (8001ec0 ) - 8001ccc: 695b ldr r3, [r3, #20] - 8001cce: 4a7c ldr r2, [pc, #496] @ (8001ec0 ) - 8001cd0: f443 2300 orr.w r3, r3, #524288 @ 0x80000 - 8001cd4: 6153 str r3, [r2, #20] - 8001cd6: 4b7a ldr r3, [pc, #488] @ (8001ec0 ) - 8001cd8: 695b ldr r3, [r3, #20] - 8001cda: f403 2300 and.w r3, r3, #524288 @ 0x80000 - 8001cde: 61fb str r3, [r7, #28] - 8001ce0: 69fb ldr r3, [r7, #28] + 8001d66: 4b7d ldr r3, [pc, #500] @ (8001f5c ) + 8001d68: 695b ldr r3, [r3, #20] + 8001d6a: 4a7c ldr r2, [pc, #496] @ (8001f5c ) + 8001d6c: f443 2300 orr.w r3, r3, #524288 @ 0x80000 + 8001d70: 6153 str r3, [r2, #20] + 8001d72: 4b7a ldr r3, [pc, #488] @ (8001f5c ) + 8001d74: 695b ldr r3, [r3, #20] + 8001d76: f403 2300 and.w r3, r3, #524288 @ 0x80000 + 8001d7a: 61fb str r3, [r7, #28] + 8001d7c: 69fb ldr r3, [r7, #28] __HAL_RCC_GPIOA_CLK_ENABLE(); - 8001ce2: 4b77 ldr r3, [pc, #476] @ (8001ec0 ) - 8001ce4: 695b ldr r3, [r3, #20] - 8001ce6: 4a76 ldr r2, [pc, #472] @ (8001ec0 ) - 8001ce8: f443 3300 orr.w r3, r3, #131072 @ 0x20000 - 8001cec: 6153 str r3, [r2, #20] - 8001cee: 4b74 ldr r3, [pc, #464] @ (8001ec0 ) - 8001cf0: 695b ldr r3, [r3, #20] - 8001cf2: f403 3300 and.w r3, r3, #131072 @ 0x20000 - 8001cf6: 61bb str r3, [r7, #24] - 8001cf8: 69bb ldr r3, [r7, #24] + 8001d7e: 4b77 ldr r3, [pc, #476] @ (8001f5c ) + 8001d80: 695b ldr r3, [r3, #20] + 8001d82: 4a76 ldr r2, [pc, #472] @ (8001f5c ) + 8001d84: f443 3300 orr.w r3, r3, #131072 @ 0x20000 + 8001d88: 6153 str r3, [r2, #20] + 8001d8a: 4b74 ldr r3, [pc, #464] @ (8001f5c ) + 8001d8c: 695b ldr r3, [r3, #20] + 8001d8e: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 8001d92: 61bb str r3, [r7, #24] + 8001d94: 69bb ldr r3, [r7, #24] __HAL_RCC_GPIOF_CLK_ENABLE(); - 8001cfa: 4b71 ldr r3, [pc, #452] @ (8001ec0 ) - 8001cfc: 695b ldr r3, [r3, #20] - 8001cfe: 4a70 ldr r2, [pc, #448] @ (8001ec0 ) - 8001d00: f443 0380 orr.w r3, r3, #4194304 @ 0x400000 - 8001d04: 6153 str r3, [r2, #20] - 8001d06: 4b6e ldr r3, [pc, #440] @ (8001ec0 ) - 8001d08: 695b ldr r3, [r3, #20] - 8001d0a: f403 0380 and.w r3, r3, #4194304 @ 0x400000 - 8001d0e: 617b str r3, [r7, #20] - 8001d10: 697b ldr r3, [r7, #20] + 8001d96: 4b71 ldr r3, [pc, #452] @ (8001f5c ) + 8001d98: 695b ldr r3, [r3, #20] + 8001d9a: 4a70 ldr r2, [pc, #448] @ (8001f5c ) + 8001d9c: f443 0380 orr.w r3, r3, #4194304 @ 0x400000 + 8001da0: 6153 str r3, [r2, #20] + 8001da2: 4b6e ldr r3, [pc, #440] @ (8001f5c ) + 8001da4: 695b ldr r3, [r3, #20] + 8001da6: f403 0380 and.w r3, r3, #4194304 @ 0x400000 + 8001daa: 617b str r3, [r7, #20] + 8001dac: 697b ldr r3, [r7, #20] PA1 ------> ADC1_IN2 PA2 ------> ADC1_IN3 PA3 ------> ADC1_IN4 PF4 ------> ADC1_IN5 */ GPIO_InitStruct.Pin = LVMS_Vsense_Pin|IS10_Pin|IS6_Pin; - 8001d12: 2307 movs r3, #7 - 8001d14: 627b str r3, [r7, #36] @ 0x24 + 8001dae: 2307 movs r3, #7 + 8001db0: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; - 8001d16: 2303 movs r3, #3 - 8001d18: 62bb str r3, [r7, #40] @ 0x28 + 8001db2: 2303 movs r3, #3 + 8001db4: 62bb str r3, [r7, #40] @ 0x28 GPIO_InitStruct.Pull = GPIO_NOPULL; - 8001d1a: 2300 movs r3, #0 - 8001d1c: 62fb str r3, [r7, #44] @ 0x2c + 8001db6: 2300 movs r3, #0 + 8001db8: 62fb str r3, [r7, #44] @ 0x2c HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); - 8001d1e: f107 0324 add.w r3, r7, #36 @ 0x24 - 8001d22: 4619 mov r1, r3 - 8001d24: 4867 ldr r0, [pc, #412] @ (8001ec4 ) - 8001d26: f002 fd43 bl 80047b0 + 8001dba: f107 0324 add.w r3, r7, #36 @ 0x24 + 8001dbe: 4619 mov r1, r3 + 8001dc0: 4867 ldr r0, [pc, #412] @ (8001f60 ) + 8001dc2: f002 fd43 bl 800484c GPIO_InitStruct.Pin = ASMS_Vsense_Pin|IS1_Pin|IS2_Pin|IS9_Pin; - 8001d2a: 230f movs r3, #15 - 8001d2c: 627b str r3, [r7, #36] @ 0x24 + 8001dc6: 230f movs r3, #15 + 8001dc8: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; - 8001d2e: 2303 movs r3, #3 - 8001d30: 62bb str r3, [r7, #40] @ 0x28 + 8001dca: 2303 movs r3, #3 + 8001dcc: 62bb str r3, [r7, #40] @ 0x28 GPIO_InitStruct.Pull = GPIO_NOPULL; - 8001d32: 2300 movs r3, #0 - 8001d34: 62fb str r3, [r7, #44] @ 0x2c + 8001dce: 2300 movs r3, #0 + 8001dd0: 62fb str r3, [r7, #44] @ 0x2c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - 8001d36: f107 0324 add.w r3, r7, #36 @ 0x24 - 8001d3a: 4619 mov r1, r3 - 8001d3c: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 - 8001d40: f002 fd36 bl 80047b0 + 8001dd2: f107 0324 add.w r3, r7, #36 @ 0x24 + 8001dd6: 4619 mov r1, r3 + 8001dd8: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 + 8001ddc: f002 fd36 bl 800484c GPIO_InitStruct.Pin = IS11_Pin; - 8001d44: 2310 movs r3, #16 - 8001d46: 627b str r3, [r7, #36] @ 0x24 + 8001de0: 2310 movs r3, #16 + 8001de2: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; - 8001d48: 2303 movs r3, #3 - 8001d4a: 62bb str r3, [r7, #40] @ 0x28 + 8001de4: 2303 movs r3, #3 + 8001de6: 62bb str r3, [r7, #40] @ 0x28 GPIO_InitStruct.Pull = GPIO_NOPULL; - 8001d4c: 2300 movs r3, #0 - 8001d4e: 62fb str r3, [r7, #44] @ 0x2c + 8001de8: 2300 movs r3, #0 + 8001dea: 62fb str r3, [r7, #44] @ 0x2c HAL_GPIO_Init(IS11_GPIO_Port, &GPIO_InitStruct); - 8001d50: f107 0324 add.w r3, r7, #36 @ 0x24 - 8001d54: 4619 mov r1, r3 - 8001d56: 485c ldr r0, [pc, #368] @ (8001ec8 ) - 8001d58: f002 fd2a bl 80047b0 + 8001dec: f107 0324 add.w r3, r7, #36 @ 0x24 + 8001df0: 4619 mov r1, r3 + 8001df2: 485c ldr r0, [pc, #368] @ (8001f64 ) + 8001df4: f002 fd2a bl 800484c /* ADC1 DMA Init */ /* ADC1 Init */ hdma_adc1.Instance = DMA1_Channel1; - 8001d5c: 4b5b ldr r3, [pc, #364] @ (8001ecc ) - 8001d5e: 4a5c ldr r2, [pc, #368] @ (8001ed0 ) - 8001d60: 601a str r2, [r3, #0] + 8001df8: 4b5b ldr r3, [pc, #364] @ (8001f68 ) + 8001dfa: 4a5c ldr r2, [pc, #368] @ (8001f6c ) + 8001dfc: 601a str r2, [r3, #0] hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY; - 8001d62: 4b5a ldr r3, [pc, #360] @ (8001ecc ) - 8001d64: 2200 movs r2, #0 - 8001d66: 605a str r2, [r3, #4] + 8001dfe: 4b5a ldr r3, [pc, #360] @ (8001f68 ) + 8001e00: 2200 movs r2, #0 + 8001e02: 605a str r2, [r3, #4] hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE; - 8001d68: 4b58 ldr r3, [pc, #352] @ (8001ecc ) - 8001d6a: 2200 movs r2, #0 - 8001d6c: 609a str r2, [r3, #8] + 8001e04: 4b58 ldr r3, [pc, #352] @ (8001f68 ) + 8001e06: 2200 movs r2, #0 + 8001e08: 609a str r2, [r3, #8] hdma_adc1.Init.MemInc = DMA_MINC_ENABLE; - 8001d6e: 4b57 ldr r3, [pc, #348] @ (8001ecc ) - 8001d70: 2280 movs r2, #128 @ 0x80 - 8001d72: 60da str r2, [r3, #12] + 8001e0a: 4b57 ldr r3, [pc, #348] @ (8001f68 ) + 8001e0c: 2280 movs r2, #128 @ 0x80 + 8001e0e: 60da str r2, [r3, #12] hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; - 8001d74: 4b55 ldr r3, [pc, #340] @ (8001ecc ) - 8001d76: f44f 7280 mov.w r2, #256 @ 0x100 - 8001d7a: 611a str r2, [r3, #16] + 8001e10: 4b55 ldr r3, [pc, #340] @ (8001f68 ) + 8001e12: f44f 7280 mov.w r2, #256 @ 0x100 + 8001e16: 611a str r2, [r3, #16] hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; - 8001d7c: 4b53 ldr r3, [pc, #332] @ (8001ecc ) - 8001d7e: f44f 6280 mov.w r2, #1024 @ 0x400 - 8001d82: 615a str r2, [r3, #20] + 8001e18: 4b53 ldr r3, [pc, #332] @ (8001f68 ) + 8001e1a: f44f 6280 mov.w r2, #1024 @ 0x400 + 8001e1e: 615a str r2, [r3, #20] hdma_adc1.Init.Mode = DMA_CIRCULAR; - 8001d84: 4b51 ldr r3, [pc, #324] @ (8001ecc ) - 8001d86: 2220 movs r2, #32 - 8001d88: 619a str r2, [r3, #24] + 8001e20: 4b51 ldr r3, [pc, #324] @ (8001f68 ) + 8001e22: 2220 movs r2, #32 + 8001e24: 619a str r2, [r3, #24] hdma_adc1.Init.Priority = DMA_PRIORITY_LOW; - 8001d8a: 4b50 ldr r3, [pc, #320] @ (8001ecc ) - 8001d8c: 2200 movs r2, #0 - 8001d8e: 61da str r2, [r3, #28] + 8001e26: 4b50 ldr r3, [pc, #320] @ (8001f68 ) + 8001e28: 2200 movs r2, #0 + 8001e2a: 61da str r2, [r3, #28] if (HAL_DMA_Init(&hdma_adc1) != HAL_OK) - 8001d90: 484e ldr r0, [pc, #312] @ (8001ecc ) - 8001d92: f002 fb5a bl 800444a - 8001d96: 4603 mov r3, r0 - 8001d98: 2b00 cmp r3, #0 - 8001d9a: d001 beq.n 8001da0 + 8001e2c: 484e ldr r0, [pc, #312] @ (8001f68 ) + 8001e2e: f002 fb5a bl 80044e6 + 8001e32: 4603 mov r3, r0 + 8001e34: 2b00 cmp r3, #0 + 8001e36: d001 beq.n 8001e3c { Error_Handler(); - 8001d9c: f7ff fe3e bl 8001a1c + 8001e38: f7ff fe00 bl 8001a3c } __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc1); - 8001da0: 687b ldr r3, [r7, #4] - 8001da2: 4a4a ldr r2, [pc, #296] @ (8001ecc ) - 8001da4: 639a str r2, [r3, #56] @ 0x38 - 8001da6: 4a49 ldr r2, [pc, #292] @ (8001ecc ) - 8001da8: 687b ldr r3, [r7, #4] - 8001daa: 6253 str r3, [r2, #36] @ 0x24 + 8001e3c: 687b ldr r3, [r7, #4] + 8001e3e: 4a4a ldr r2, [pc, #296] @ (8001f68 ) + 8001e40: 639a str r2, [r3, #56] @ 0x38 + 8001e42: 4a49 ldr r2, [pc, #292] @ (8001f68 ) + 8001e44: 687b ldr r3, [r7, #4] + 8001e46: 6253 str r3, [r2, #36] @ 0x24 /* ADC1 interrupt Init */ HAL_NVIC_SetPriority(ADC1_2_IRQn, 0, 0); - 8001dac: 2200 movs r2, #0 - 8001dae: 2100 movs r1, #0 - 8001db0: 2012 movs r0, #18 - 8001db2: f002 fb14 bl 80043de + 8001e48: 2200 movs r2, #0 + 8001e4a: 2100 movs r1, #0 + 8001e4c: 2012 movs r0, #18 + 8001e4e: f002 fb14 bl 800447a HAL_NVIC_EnableIRQ(ADC1_2_IRQn); - 8001db6: 2012 movs r0, #18 - 8001db8: f002 fb2d bl 8004416 + 8001e52: 2012 movs r0, #18 + 8001e54: f002 fb2d bl 80044b2 /* USER CODE BEGIN ADC2_MspInit 1 */ /* USER CODE END ADC2_MspInit 1 */ } } - 8001dbc: e07a b.n 8001eb4 + 8001e58: e07a b.n 8001f50 else if(hadc->Instance==ADC2) - 8001dbe: 687b ldr r3, [r7, #4] - 8001dc0: 681b ldr r3, [r3, #0] - 8001dc2: 4a44 ldr r2, [pc, #272] @ (8001ed4 ) - 8001dc4: 4293 cmp r3, r2 - 8001dc6: d175 bne.n 8001eb4 + 8001e5a: 687b ldr r3, [r7, #4] + 8001e5c: 681b ldr r3, [r3, #0] + 8001e5e: 4a44 ldr r2, [pc, #272] @ (8001f70 ) + 8001e60: 4293 cmp r3, r2 + 8001e62: d175 bne.n 8001f50 HAL_RCC_ADC12_CLK_ENABLED++; - 8001dc8: 4b3c ldr r3, [pc, #240] @ (8001ebc ) - 8001dca: 681b ldr r3, [r3, #0] - 8001dcc: 3301 adds r3, #1 - 8001dce: 4a3b ldr r2, [pc, #236] @ (8001ebc ) - 8001dd0: 6013 str r3, [r2, #0] + 8001e64: 4b3c ldr r3, [pc, #240] @ (8001f58 ) + 8001e66: 681b ldr r3, [r3, #0] + 8001e68: 3301 adds r3, #1 + 8001e6a: 4a3b ldr r2, [pc, #236] @ (8001f58 ) + 8001e6c: 6013 str r3, [r2, #0] if(HAL_RCC_ADC12_CLK_ENABLED==1){ - 8001dd2: 4b3a ldr r3, [pc, #232] @ (8001ebc ) - 8001dd4: 681b ldr r3, [r3, #0] - 8001dd6: 2b01 cmp r3, #1 - 8001dd8: d10b bne.n 8001df2 + 8001e6e: 4b3a ldr r3, [pc, #232] @ (8001f58 ) + 8001e70: 681b ldr r3, [r3, #0] + 8001e72: 2b01 cmp r3, #1 + 8001e74: d10b bne.n 8001e8e __HAL_RCC_ADC12_CLK_ENABLE(); - 8001dda: 4b39 ldr r3, [pc, #228] @ (8001ec0 ) - 8001ddc: 695b ldr r3, [r3, #20] - 8001dde: 4a38 ldr r2, [pc, #224] @ (8001ec0 ) - 8001de0: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 - 8001de4: 6153 str r3, [r2, #20] - 8001de6: 4b36 ldr r3, [pc, #216] @ (8001ec0 ) - 8001de8: 695b ldr r3, [r3, #20] - 8001dea: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 - 8001dee: 613b str r3, [r7, #16] - 8001df0: 693b ldr r3, [r7, #16] + 8001e76: 4b39 ldr r3, [pc, #228] @ (8001f5c ) + 8001e78: 695b ldr r3, [r3, #20] + 8001e7a: 4a38 ldr r2, [pc, #224] @ (8001f5c ) + 8001e7c: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 8001e80: 6153 str r3, [r2, #20] + 8001e82: 4b36 ldr r3, [pc, #216] @ (8001f5c ) + 8001e84: 695b ldr r3, [r3, #20] + 8001e86: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 8001e8a: 613b str r3, [r7, #16] + 8001e8c: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOC_CLK_ENABLE(); - 8001df2: 4b33 ldr r3, [pc, #204] @ (8001ec0 ) - 8001df4: 695b ldr r3, [r3, #20] - 8001df6: 4a32 ldr r2, [pc, #200] @ (8001ec0 ) - 8001df8: f443 2300 orr.w r3, r3, #524288 @ 0x80000 - 8001dfc: 6153 str r3, [r2, #20] - 8001dfe: 4b30 ldr r3, [pc, #192] @ (8001ec0 ) - 8001e00: 695b ldr r3, [r3, #20] - 8001e02: f403 2300 and.w r3, r3, #524288 @ 0x80000 - 8001e06: 60fb str r3, [r7, #12] - 8001e08: 68fb ldr r3, [r7, #12] + 8001e8e: 4b33 ldr r3, [pc, #204] @ (8001f5c ) + 8001e90: 695b ldr r3, [r3, #20] + 8001e92: 4a32 ldr r2, [pc, #200] @ (8001f5c ) + 8001e94: f443 2300 orr.w r3, r3, #524288 @ 0x80000 + 8001e98: 6153 str r3, [r2, #20] + 8001e9a: 4b30 ldr r3, [pc, #192] @ (8001f5c ) + 8001e9c: 695b ldr r3, [r3, #20] + 8001e9e: f403 2300 and.w r3, r3, #524288 @ 0x80000 + 8001ea2: 60fb str r3, [r7, #12] + 8001ea4: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOA_CLK_ENABLE(); - 8001e0a: 4b2d ldr r3, [pc, #180] @ (8001ec0 ) - 8001e0c: 695b ldr r3, [r3, #20] - 8001e0e: 4a2c ldr r2, [pc, #176] @ (8001ec0 ) - 8001e10: f443 3300 orr.w r3, r3, #131072 @ 0x20000 - 8001e14: 6153 str r3, [r2, #20] - 8001e16: 4b2a ldr r3, [pc, #168] @ (8001ec0 ) - 8001e18: 695b ldr r3, [r3, #20] - 8001e1a: f403 3300 and.w r3, r3, #131072 @ 0x20000 - 8001e1e: 60bb str r3, [r7, #8] - 8001e20: 68bb ldr r3, [r7, #8] + 8001ea6: 4b2d ldr r3, [pc, #180] @ (8001f5c ) + 8001ea8: 695b ldr r3, [r3, #20] + 8001eaa: 4a2c ldr r2, [pc, #176] @ (8001f5c ) + 8001eac: f443 3300 orr.w r3, r3, #131072 @ 0x20000 + 8001eb0: 6153 str r3, [r2, #20] + 8001eb2: 4b2a ldr r3, [pc, #168] @ (8001f5c ) + 8001eb4: 695b ldr r3, [r3, #20] + 8001eb6: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 8001eba: 60bb str r3, [r7, #8] + 8001ebc: 68bb ldr r3, [r7, #8] GPIO_InitStruct.Pin = IS7_Pin|PC_Read_Pin; - 8001e22: 2318 movs r3, #24 - 8001e24: 627b str r3, [r7, #36] @ 0x24 + 8001ebe: 2318 movs r3, #24 + 8001ec0: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; - 8001e26: 2303 movs r3, #3 - 8001e28: 62bb str r3, [r7, #40] @ 0x28 + 8001ec2: 2303 movs r3, #3 + 8001ec4: 62bb str r3, [r7, #40] @ 0x28 GPIO_InitStruct.Pull = GPIO_NOPULL; - 8001e2a: 2300 movs r3, #0 - 8001e2c: 62fb str r3, [r7, #44] @ 0x2c + 8001ec6: 2300 movs r3, #0 + 8001ec8: 62fb str r3, [r7, #44] @ 0x2c HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); - 8001e2e: f107 0324 add.w r3, r7, #36 @ 0x24 - 8001e32: 4619 mov r1, r3 - 8001e34: 4823 ldr r0, [pc, #140] @ (8001ec4 ) - 8001e36: f002 fcbb bl 80047b0 + 8001eca: f107 0324 add.w r3, r7, #36 @ 0x24 + 8001ece: 4619 mov r1, r3 + 8001ed0: 4823 ldr r0, [pc, #140] @ (8001f60 ) + 8001ed2: f002 fcbb bl 800484c GPIO_InitStruct.Pin = IS3_Pin|IS8_Pin|IS4_Pin|IS5_Pin; - 8001e3a: 23f0 movs r3, #240 @ 0xf0 - 8001e3c: 627b str r3, [r7, #36] @ 0x24 + 8001ed6: 23f0 movs r3, #240 @ 0xf0 + 8001ed8: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; - 8001e3e: 2303 movs r3, #3 - 8001e40: 62bb str r3, [r7, #40] @ 0x28 + 8001eda: 2303 movs r3, #3 + 8001edc: 62bb str r3, [r7, #40] @ 0x28 GPIO_InitStruct.Pull = GPIO_NOPULL; - 8001e42: 2300 movs r3, #0 - 8001e44: 62fb str r3, [r7, #44] @ 0x2c + 8001ede: 2300 movs r3, #0 + 8001ee0: 62fb str r3, [r7, #44] @ 0x2c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - 8001e46: f107 0324 add.w r3, r7, #36 @ 0x24 - 8001e4a: 4619 mov r1, r3 - 8001e4c: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 - 8001e50: f002 fcae bl 80047b0 + 8001ee2: f107 0324 add.w r3, r7, #36 @ 0x24 + 8001ee6: 4619 mov r1, r3 + 8001ee8: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 + 8001eec: f002 fcae bl 800484c hdma_adc2.Instance = DMA2_Channel1; - 8001e54: 4b20 ldr r3, [pc, #128] @ (8001ed8 ) - 8001e56: 4a21 ldr r2, [pc, #132] @ (8001edc ) - 8001e58: 601a str r2, [r3, #0] + 8001ef0: 4b20 ldr r3, [pc, #128] @ (8001f74 ) + 8001ef2: 4a21 ldr r2, [pc, #132] @ (8001f78 ) + 8001ef4: 601a str r2, [r3, #0] hdma_adc2.Init.Direction = DMA_PERIPH_TO_MEMORY; - 8001e5a: 4b1f ldr r3, [pc, #124] @ (8001ed8 ) - 8001e5c: 2200 movs r2, #0 - 8001e5e: 605a str r2, [r3, #4] + 8001ef6: 4b1f ldr r3, [pc, #124] @ (8001f74 ) + 8001ef8: 2200 movs r2, #0 + 8001efa: 605a str r2, [r3, #4] hdma_adc2.Init.PeriphInc = DMA_PINC_DISABLE; - 8001e60: 4b1d ldr r3, [pc, #116] @ (8001ed8 ) - 8001e62: 2200 movs r2, #0 - 8001e64: 609a str r2, [r3, #8] + 8001efc: 4b1d ldr r3, [pc, #116] @ (8001f74 ) + 8001efe: 2200 movs r2, #0 + 8001f00: 609a str r2, [r3, #8] hdma_adc2.Init.MemInc = DMA_MINC_ENABLE; - 8001e66: 4b1c ldr r3, [pc, #112] @ (8001ed8 ) - 8001e68: 2280 movs r2, #128 @ 0x80 - 8001e6a: 60da str r2, [r3, #12] + 8001f02: 4b1c ldr r3, [pc, #112] @ (8001f74 ) + 8001f04: 2280 movs r2, #128 @ 0x80 + 8001f06: 60da str r2, [r3, #12] hdma_adc2.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; - 8001e6c: 4b1a ldr r3, [pc, #104] @ (8001ed8 ) - 8001e6e: f44f 7280 mov.w r2, #256 @ 0x100 - 8001e72: 611a str r2, [r3, #16] + 8001f08: 4b1a ldr r3, [pc, #104] @ (8001f74 ) + 8001f0a: f44f 7280 mov.w r2, #256 @ 0x100 + 8001f0e: 611a str r2, [r3, #16] hdma_adc2.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; - 8001e74: 4b18 ldr r3, [pc, #96] @ (8001ed8 ) - 8001e76: f44f 6280 mov.w r2, #1024 @ 0x400 - 8001e7a: 615a str r2, [r3, #20] + 8001f10: 4b18 ldr r3, [pc, #96] @ (8001f74 ) + 8001f12: f44f 6280 mov.w r2, #1024 @ 0x400 + 8001f16: 615a str r2, [r3, #20] hdma_adc2.Init.Mode = DMA_CIRCULAR; - 8001e7c: 4b16 ldr r3, [pc, #88] @ (8001ed8 ) - 8001e7e: 2220 movs r2, #32 - 8001e80: 619a str r2, [r3, #24] + 8001f18: 4b16 ldr r3, [pc, #88] @ (8001f74 ) + 8001f1a: 2220 movs r2, #32 + 8001f1c: 619a str r2, [r3, #24] hdma_adc2.Init.Priority = DMA_PRIORITY_LOW; - 8001e82: 4b15 ldr r3, [pc, #84] @ (8001ed8 ) - 8001e84: 2200 movs r2, #0 - 8001e86: 61da str r2, [r3, #28] + 8001f1e: 4b15 ldr r3, [pc, #84] @ (8001f74 ) + 8001f20: 2200 movs r2, #0 + 8001f22: 61da str r2, [r3, #28] if (HAL_DMA_Init(&hdma_adc2) != HAL_OK) - 8001e88: 4813 ldr r0, [pc, #76] @ (8001ed8 ) - 8001e8a: f002 fade bl 800444a - 8001e8e: 4603 mov r3, r0 - 8001e90: 2b00 cmp r3, #0 - 8001e92: d001 beq.n 8001e98 + 8001f24: 4813 ldr r0, [pc, #76] @ (8001f74 ) + 8001f26: f002 fade bl 80044e6 + 8001f2a: 4603 mov r3, r0 + 8001f2c: 2b00 cmp r3, #0 + 8001f2e: d001 beq.n 8001f34 Error_Handler(); - 8001e94: f7ff fdc2 bl 8001a1c + 8001f30: f7ff fd84 bl 8001a3c __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc2); - 8001e98: 687b ldr r3, [r7, #4] - 8001e9a: 4a0f ldr r2, [pc, #60] @ (8001ed8 ) - 8001e9c: 639a str r2, [r3, #56] @ 0x38 - 8001e9e: 4a0e ldr r2, [pc, #56] @ (8001ed8 ) - 8001ea0: 687b ldr r3, [r7, #4] - 8001ea2: 6253 str r3, [r2, #36] @ 0x24 + 8001f34: 687b ldr r3, [r7, #4] + 8001f36: 4a0f ldr r2, [pc, #60] @ (8001f74 ) + 8001f38: 639a str r2, [r3, #56] @ 0x38 + 8001f3a: 4a0e ldr r2, [pc, #56] @ (8001f74 ) + 8001f3c: 687b ldr r3, [r7, #4] + 8001f3e: 6253 str r3, [r2, #36] @ 0x24 HAL_NVIC_SetPriority(ADC1_2_IRQn, 0, 0); - 8001ea4: 2200 movs r2, #0 - 8001ea6: 2100 movs r1, #0 - 8001ea8: 2012 movs r0, #18 - 8001eaa: f002 fa98 bl 80043de + 8001f40: 2200 movs r2, #0 + 8001f42: 2100 movs r1, #0 + 8001f44: 2012 movs r0, #18 + 8001f46: f002 fa98 bl 800447a HAL_NVIC_EnableIRQ(ADC1_2_IRQn); - 8001eae: 2012 movs r0, #18 - 8001eb0: f002 fab1 bl 8004416 + 8001f4a: 2012 movs r0, #18 + 8001f4c: f002 fab1 bl 80044b2 } - 8001eb4: bf00 nop - 8001eb6: 3738 adds r7, #56 @ 0x38 - 8001eb8: 46bd mov sp, r7 - 8001eba: bd80 pop {r7, pc} - 8001ebc: 20000304 .word 0x20000304 - 8001ec0: 40021000 .word 0x40021000 - 8001ec4: 48000800 .word 0x48000800 - 8001ec8: 48001400 .word 0x48001400 - 8001ecc: 20000164 .word 0x20000164 - 8001ed0: 40020008 .word 0x40020008 - 8001ed4: 50000100 .word 0x50000100 - 8001ed8: 200001a8 .word 0x200001a8 - 8001edc: 40020408 .word 0x40020408 + 8001f50: bf00 nop + 8001f52: 3738 adds r7, #56 @ 0x38 + 8001f54: 46bd mov sp, r7 + 8001f56: bd80 pop {r7, pc} + 8001f58: 200002f8 .word 0x200002f8 + 8001f5c: 40021000 .word 0x40021000 + 8001f60: 48000800 .word 0x48000800 + 8001f64: 48001400 .word 0x48001400 + 8001f68: 20000164 .word 0x20000164 + 8001f6c: 40020008 .word 0x40020008 + 8001f70: 50000100 .word 0x50000100 + 8001f74: 200001a8 .word 0x200001a8 + 8001f78: 40020408 .word 0x40020408 -08001ee0 : +08001f7c : * This function configures the hardware resources used in this example * @param hcan: CAN handle pointer * @retval None */ void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan) { - 8001ee0: b580 push {r7, lr} - 8001ee2: b08a sub sp, #40 @ 0x28 - 8001ee4: af00 add r7, sp, #0 - 8001ee6: 6078 str r0, [r7, #4] + 8001f7c: b580 push {r7, lr} + 8001f7e: b08a sub sp, #40 @ 0x28 + 8001f80: af00 add r7, sp, #0 + 8001f82: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; - 8001ee8: f107 0314 add.w r3, r7, #20 - 8001eec: 2200 movs r2, #0 - 8001eee: 601a str r2, [r3, #0] - 8001ef0: 605a str r2, [r3, #4] - 8001ef2: 609a str r2, [r3, #8] - 8001ef4: 60da str r2, [r3, #12] - 8001ef6: 611a str r2, [r3, #16] + 8001f84: f107 0314 add.w r3, r7, #20 + 8001f88: 2200 movs r2, #0 + 8001f8a: 601a str r2, [r3, #0] + 8001f8c: 605a str r2, [r3, #4] + 8001f8e: 609a str r2, [r3, #8] + 8001f90: 60da str r2, [r3, #12] + 8001f92: 611a str r2, [r3, #16] if(hcan->Instance==CAN) - 8001ef8: 687b ldr r3, [r7, #4] - 8001efa: 681b ldr r3, [r3, #0] - 8001efc: 4a20 ldr r2, [pc, #128] @ (8001f80 ) - 8001efe: 4293 cmp r3, r2 - 8001f00: d139 bne.n 8001f76 + 8001f94: 687b ldr r3, [r7, #4] + 8001f96: 681b ldr r3, [r3, #0] + 8001f98: 4a20 ldr r2, [pc, #128] @ (800201c ) + 8001f9a: 4293 cmp r3, r2 + 8001f9c: d139 bne.n 8002012 { /* USER CODE BEGIN CAN_MspInit 0 */ /* USER CODE END CAN_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_CAN1_CLK_ENABLE(); - 8001f02: 4b20 ldr r3, [pc, #128] @ (8001f84 ) - 8001f04: 69db ldr r3, [r3, #28] - 8001f06: 4a1f ldr r2, [pc, #124] @ (8001f84 ) - 8001f08: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 - 8001f0c: 61d3 str r3, [r2, #28] - 8001f0e: 4b1d ldr r3, [pc, #116] @ (8001f84 ) - 8001f10: 69db ldr r3, [r3, #28] - 8001f12: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 - 8001f16: 613b str r3, [r7, #16] - 8001f18: 693b ldr r3, [r7, #16] + 8001f9e: 4b20 ldr r3, [pc, #128] @ (8002020 ) + 8001fa0: 69db ldr r3, [r3, #28] + 8001fa2: 4a1f ldr r2, [pc, #124] @ (8002020 ) + 8001fa4: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 + 8001fa8: 61d3 str r3, [r2, #28] + 8001faa: 4b1d ldr r3, [pc, #116] @ (8002020 ) + 8001fac: 69db ldr r3, [r3, #28] + 8001fae: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 8001fb2: 613b str r3, [r7, #16] + 8001fb4: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); - 8001f1a: 4b1a ldr r3, [pc, #104] @ (8001f84 ) - 8001f1c: 695b ldr r3, [r3, #20] - 8001f1e: 4a19 ldr r2, [pc, #100] @ (8001f84 ) - 8001f20: f443 3300 orr.w r3, r3, #131072 @ 0x20000 - 8001f24: 6153 str r3, [r2, #20] - 8001f26: 4b17 ldr r3, [pc, #92] @ (8001f84 ) - 8001f28: 695b ldr r3, [r3, #20] - 8001f2a: f403 3300 and.w r3, r3, #131072 @ 0x20000 - 8001f2e: 60fb str r3, [r7, #12] - 8001f30: 68fb ldr r3, [r7, #12] + 8001fb6: 4b1a ldr r3, [pc, #104] @ (8002020 ) + 8001fb8: 695b ldr r3, [r3, #20] + 8001fba: 4a19 ldr r2, [pc, #100] @ (8002020 ) + 8001fbc: f443 3300 orr.w r3, r3, #131072 @ 0x20000 + 8001fc0: 6153 str r3, [r2, #20] + 8001fc2: 4b17 ldr r3, [pc, #92] @ (8002020 ) + 8001fc4: 695b ldr r3, [r3, #20] + 8001fc6: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 8001fca: 60fb str r3, [r7, #12] + 8001fcc: 68fb ldr r3, [r7, #12] /**CAN GPIO Configuration PA11 ------> CAN_RX PA12 ------> CAN_TX */ GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12; - 8001f32: f44f 53c0 mov.w r3, #6144 @ 0x1800 - 8001f36: 617b str r3, [r7, #20] + 8001fce: f44f 53c0 mov.w r3, #6144 @ 0x1800 + 8001fd2: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - 8001f38: 2302 movs r3, #2 - 8001f3a: 61bb str r3, [r7, #24] + 8001fd4: 2302 movs r3, #2 + 8001fd6: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; - 8001f3c: 2300 movs r3, #0 - 8001f3e: 61fb str r3, [r7, #28] + 8001fd8: 2300 movs r3, #0 + 8001fda: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; - 8001f40: 2303 movs r3, #3 - 8001f42: 623b str r3, [r7, #32] + 8001fdc: 2303 movs r3, #3 + 8001fde: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF9_CAN; - 8001f44: 2309 movs r3, #9 - 8001f46: 627b str r3, [r7, #36] @ 0x24 + 8001fe0: 2309 movs r3, #9 + 8001fe2: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - 8001f48: f107 0314 add.w r3, r7, #20 - 8001f4c: 4619 mov r1, r3 - 8001f4e: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 - 8001f52: f002 fc2d bl 80047b0 + 8001fe4: f107 0314 add.w r3, r7, #20 + 8001fe8: 4619 mov r1, r3 + 8001fea: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 + 8001fee: f002 fc2d bl 800484c /* CAN interrupt Init */ HAL_NVIC_SetPriority(USB_LP_CAN_RX0_IRQn, 0, 0); - 8001f56: 2200 movs r2, #0 - 8001f58: 2100 movs r1, #0 - 8001f5a: 2014 movs r0, #20 - 8001f5c: f002 fa3f bl 80043de + 8001ff2: 2200 movs r2, #0 + 8001ff4: 2100 movs r1, #0 + 8001ff6: 2014 movs r0, #20 + 8001ff8: f002 fa3f bl 800447a HAL_NVIC_EnableIRQ(USB_LP_CAN_RX0_IRQn); - 8001f60: 2014 movs r0, #20 - 8001f62: f002 fa58 bl 8004416 + 8001ffc: 2014 movs r0, #20 + 8001ffe: f002 fa58 bl 80044b2 HAL_NVIC_SetPriority(CAN_RX1_IRQn, 0, 0); - 8001f66: 2200 movs r2, #0 - 8001f68: 2100 movs r1, #0 - 8001f6a: 2015 movs r0, #21 - 8001f6c: f002 fa37 bl 80043de + 8002002: 2200 movs r2, #0 + 8002004: 2100 movs r1, #0 + 8002006: 2015 movs r0, #21 + 8002008: f002 fa37 bl 800447a HAL_NVIC_EnableIRQ(CAN_RX1_IRQn); - 8001f70: 2015 movs r0, #21 - 8001f72: f002 fa50 bl 8004416 + 800200c: 2015 movs r0, #21 + 800200e: f002 fa50 bl 80044b2 /* USER CODE END CAN_MspInit 1 */ } } - 8001f76: bf00 nop - 8001f78: 3728 adds r7, #40 @ 0x28 - 8001f7a: 46bd mov sp, r7 - 8001f7c: bd80 pop {r7, pc} - 8001f7e: bf00 nop - 8001f80: 40006400 .word 0x40006400 - 8001f84: 40021000 .word 0x40021000 + 8002012: bf00 nop + 8002014: 3728 adds r7, #40 @ 0x28 + 8002016: 46bd mov sp, r7 + 8002018: bd80 pop {r7, pc} + 800201a: bf00 nop + 800201c: 40006400 .word 0x40006400 + 8002020: 40021000 .word 0x40021000 -08001f88 : +08002024 : * This function configures the hardware resources used in this example * @param htim_base: TIM_Base handle pointer * @retval None */ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) { - 8001f88: b580 push {r7, lr} - 8001f8a: b084 sub sp, #16 - 8001f8c: af00 add r7, sp, #0 - 8001f8e: 6078 str r0, [r7, #4] + 8002024: b580 push {r7, lr} + 8002026: b084 sub sp, #16 + 8002028: af00 add r7, sp, #0 + 800202a: 6078 str r0, [r7, #4] if(htim_base->Instance==TIM6) - 8001f90: 687b ldr r3, [r7, #4] - 8001f92: 681b ldr r3, [r3, #0] - 8001f94: 4a0d ldr r2, [pc, #52] @ (8001fcc ) - 8001f96: 4293 cmp r3, r2 - 8001f98: d113 bne.n 8001fc2 + 800202c: 687b ldr r3, [r7, #4] + 800202e: 681b ldr r3, [r3, #0] + 8002030: 4a0d ldr r2, [pc, #52] @ (8002068 ) + 8002032: 4293 cmp r3, r2 + 8002034: d113 bne.n 800205e { /* USER CODE BEGIN TIM6_MspInit 0 */ /* USER CODE END TIM6_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_TIM6_CLK_ENABLE(); - 8001f9a: 4b0d ldr r3, [pc, #52] @ (8001fd0 ) - 8001f9c: 69db ldr r3, [r3, #28] - 8001f9e: 4a0c ldr r2, [pc, #48] @ (8001fd0 ) - 8001fa0: f043 0310 orr.w r3, r3, #16 - 8001fa4: 61d3 str r3, [r2, #28] - 8001fa6: 4b0a ldr r3, [pc, #40] @ (8001fd0 ) - 8001fa8: 69db ldr r3, [r3, #28] - 8001faa: f003 0310 and.w r3, r3, #16 - 8001fae: 60fb str r3, [r7, #12] - 8001fb0: 68fb ldr r3, [r7, #12] + 8002036: 4b0d ldr r3, [pc, #52] @ (800206c ) + 8002038: 69db ldr r3, [r3, #28] + 800203a: 4a0c ldr r2, [pc, #48] @ (800206c ) + 800203c: f043 0310 orr.w r3, r3, #16 + 8002040: 61d3 str r3, [r2, #28] + 8002042: 4b0a ldr r3, [pc, #40] @ (800206c ) + 8002044: 69db ldr r3, [r3, #28] + 8002046: f003 0310 and.w r3, r3, #16 + 800204a: 60fb str r3, [r7, #12] + 800204c: 68fb ldr r3, [r7, #12] /* TIM6 interrupt Init */ HAL_NVIC_SetPriority(TIM6_DAC_IRQn, 0, 0); - 8001fb2: 2200 movs r2, #0 - 8001fb4: 2100 movs r1, #0 - 8001fb6: 2036 movs r0, #54 @ 0x36 - 8001fb8: f002 fa11 bl 80043de + 800204e: 2200 movs r2, #0 + 8002050: 2100 movs r1, #0 + 8002052: 2036 movs r0, #54 @ 0x36 + 8002054: f002 fa11 bl 800447a HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn); - 8001fbc: 2036 movs r0, #54 @ 0x36 - 8001fbe: f002 fa2a bl 8004416 + 8002058: 2036 movs r0, #54 @ 0x36 + 800205a: f002 fa2a bl 80044b2 /* USER CODE END TIM6_MspInit 1 */ } } - 8001fc2: bf00 nop - 8001fc4: 3710 adds r7, #16 - 8001fc6: 46bd mov sp, r7 - 8001fc8: bd80 pop {r7, pc} - 8001fca: bf00 nop - 8001fcc: 40001000 .word 0x40001000 - 8001fd0: 40021000 .word 0x40021000 + 800205e: bf00 nop + 8002060: 3710 adds r7, #16 + 8002062: 46bd mov sp, r7 + 8002064: bd80 pop {r7, pc} + 8002066: bf00 nop + 8002068: 40001000 .word 0x40001000 + 800206c: 40021000 .word 0x40021000 -08001fd4 : +08002070 : * This function configures the hardware resources used in this example * @param huart: UART handle pointer * @retval None */ void HAL_UART_MspInit(UART_HandleTypeDef* huart) { - 8001fd4: b580 push {r7, lr} - 8001fd6: b08a sub sp, #40 @ 0x28 - 8001fd8: af00 add r7, sp, #0 - 8001fda: 6078 str r0, [r7, #4] + 8002070: b580 push {r7, lr} + 8002072: b08a sub sp, #40 @ 0x28 + 8002074: af00 add r7, sp, #0 + 8002076: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; - 8001fdc: f107 0314 add.w r3, r7, #20 - 8001fe0: 2200 movs r2, #0 - 8001fe2: 601a str r2, [r3, #0] - 8001fe4: 605a str r2, [r3, #4] - 8001fe6: 609a str r2, [r3, #8] - 8001fe8: 60da str r2, [r3, #12] - 8001fea: 611a str r2, [r3, #16] + 8002078: f107 0314 add.w r3, r7, #20 + 800207c: 2200 movs r2, #0 + 800207e: 601a str r2, [r3, #0] + 8002080: 605a str r2, [r3, #4] + 8002082: 609a str r2, [r3, #8] + 8002084: 60da str r2, [r3, #12] + 8002086: 611a str r2, [r3, #16] if(huart->Instance==UART4) - 8001fec: 687b ldr r3, [r7, #4] - 8001fee: 681b ldr r3, [r3, #0] - 8001ff0: 4a17 ldr r2, [pc, #92] @ (8002050 ) - 8001ff2: 4293 cmp r3, r2 - 8001ff4: d128 bne.n 8002048 + 8002088: 687b ldr r3, [r7, #4] + 800208a: 681b ldr r3, [r3, #0] + 800208c: 4a17 ldr r2, [pc, #92] @ (80020ec ) + 800208e: 4293 cmp r3, r2 + 8002090: d128 bne.n 80020e4 { /* USER CODE BEGIN UART4_MspInit 0 */ /* USER CODE END UART4_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_UART4_CLK_ENABLE(); - 8001ff6: 4b17 ldr r3, [pc, #92] @ (8002054 ) - 8001ff8: 69db ldr r3, [r3, #28] - 8001ffa: 4a16 ldr r2, [pc, #88] @ (8002054 ) - 8001ffc: f443 2300 orr.w r3, r3, #524288 @ 0x80000 - 8002000: 61d3 str r3, [r2, #28] - 8002002: 4b14 ldr r3, [pc, #80] @ (8002054 ) - 8002004: 69db ldr r3, [r3, #28] - 8002006: f403 2300 and.w r3, r3, #524288 @ 0x80000 - 800200a: 613b str r3, [r7, #16] - 800200c: 693b ldr r3, [r7, #16] + 8002092: 4b17 ldr r3, [pc, #92] @ (80020f0 ) + 8002094: 69db ldr r3, [r3, #28] + 8002096: 4a16 ldr r2, [pc, #88] @ (80020f0 ) + 8002098: f443 2300 orr.w r3, r3, #524288 @ 0x80000 + 800209c: 61d3 str r3, [r2, #28] + 800209e: 4b14 ldr r3, [pc, #80] @ (80020f0 ) + 80020a0: 69db ldr r3, [r3, #28] + 80020a2: f403 2300 and.w r3, r3, #524288 @ 0x80000 + 80020a6: 613b str r3, [r7, #16] + 80020a8: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOC_CLK_ENABLE(); - 800200e: 4b11 ldr r3, [pc, #68] @ (8002054 ) - 8002010: 695b ldr r3, [r3, #20] - 8002012: 4a10 ldr r2, [pc, #64] @ (8002054 ) - 8002014: f443 2300 orr.w r3, r3, #524288 @ 0x80000 - 8002018: 6153 str r3, [r2, #20] - 800201a: 4b0e ldr r3, [pc, #56] @ (8002054 ) - 800201c: 695b ldr r3, [r3, #20] - 800201e: f403 2300 and.w r3, r3, #524288 @ 0x80000 - 8002022: 60fb str r3, [r7, #12] - 8002024: 68fb ldr r3, [r7, #12] + 80020aa: 4b11 ldr r3, [pc, #68] @ (80020f0 ) + 80020ac: 695b ldr r3, [r3, #20] + 80020ae: 4a10 ldr r2, [pc, #64] @ (80020f0 ) + 80020b0: f443 2300 orr.w r3, r3, #524288 @ 0x80000 + 80020b4: 6153 str r3, [r2, #20] + 80020b6: 4b0e ldr r3, [pc, #56] @ (80020f0 ) + 80020b8: 695b ldr r3, [r3, #20] + 80020ba: f403 2300 and.w r3, r3, #524288 @ 0x80000 + 80020be: 60fb str r3, [r7, #12] + 80020c0: 68fb ldr r3, [r7, #12] /**UART4 GPIO Configuration PC10 ------> UART4_TX PC11 ------> UART4_RX */ GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11; - 8002026: f44f 6340 mov.w r3, #3072 @ 0xc00 - 800202a: 617b str r3, [r7, #20] + 80020c2: f44f 6340 mov.w r3, #3072 @ 0xc00 + 80020c6: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - 800202c: 2302 movs r3, #2 - 800202e: 61bb str r3, [r7, #24] + 80020c8: 2302 movs r3, #2 + 80020ca: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; - 8002030: 2300 movs r3, #0 - 8002032: 61fb str r3, [r7, #28] + 80020cc: 2300 movs r3, #0 + 80020ce: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; - 8002034: 2303 movs r3, #3 - 8002036: 623b str r3, [r7, #32] + 80020d0: 2303 movs r3, #3 + 80020d2: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF5_UART4; - 8002038: 2305 movs r3, #5 - 800203a: 627b str r3, [r7, #36] @ 0x24 + 80020d4: 2305 movs r3, #5 + 80020d6: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); - 800203c: f107 0314 add.w r3, r7, #20 - 8002040: 4619 mov r1, r3 - 8002042: 4805 ldr r0, [pc, #20] @ (8002058 ) - 8002044: f002 fbb4 bl 80047b0 + 80020d8: f107 0314 add.w r3, r7, #20 + 80020dc: 4619 mov r1, r3 + 80020de: 4805 ldr r0, [pc, #20] @ (80020f4 ) + 80020e0: f002 fbb4 bl 800484c /* USER CODE END UART4_MspInit 1 */ } } - 8002048: bf00 nop - 800204a: 3728 adds r7, #40 @ 0x28 - 800204c: 46bd mov sp, r7 - 800204e: bd80 pop {r7, pc} - 8002050: 40004c00 .word 0x40004c00 - 8002054: 40021000 .word 0x40021000 - 8002058: 48000800 .word 0x48000800 + 80020e4: bf00 nop + 80020e6: 3728 adds r7, #40 @ 0x28 + 80020e8: 46bd mov sp, r7 + 80020ea: bd80 pop {r7, pc} + 80020ec: 40004c00 .word 0x40004c00 + 80020f0: 40021000 .word 0x40021000 + 80020f4: 48000800 .word 0x48000800 -0800205c : +080020f8 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { - 800205c: b480 push {r7} - 800205e: af00 add r7, sp, #0 + 80020f8: b480 push {r7} + 80020fa: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) - 8002060: bf00 nop - 8002062: e7fd b.n 8002060 + 80020fc: bf00 nop + 80020fe: e7fd b.n 80020fc -08002064 : +08002100 : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { - 8002064: b480 push {r7} - 8002066: af00 add r7, sp, #0 + 8002100: b480 push {r7} + 8002102: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) - 8002068: bf00 nop - 800206a: e7fd b.n 8002068 + 8002104: bf00 nop + 8002106: e7fd b.n 8002104 -0800206c : +08002108 : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { - 800206c: b480 push {r7} - 800206e: af00 add r7, sp, #0 + 8002108: b480 push {r7} + 800210a: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) - 8002070: bf00 nop - 8002072: e7fd b.n 8002070 + 800210c: bf00 nop + 800210e: e7fd b.n 800210c -08002074 : +08002110 : /** * @brief This function handles Pre-fetch fault, memory access fault. */ void BusFault_Handler(void) { - 8002074: b480 push {r7} - 8002076: af00 add r7, sp, #0 + 8002110: b480 push {r7} + 8002112: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) - 8002078: bf00 nop - 800207a: e7fd b.n 8002078 + 8002114: bf00 nop + 8002116: e7fd b.n 8002114 -0800207c : +08002118 : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { - 800207c: b480 push {r7} - 800207e: af00 add r7, sp, #0 + 8002118: b480 push {r7} + 800211a: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) - 8002080: bf00 nop - 8002082: e7fd b.n 8002080 + 800211c: bf00 nop + 800211e: e7fd b.n 800211c -08002084 : +08002120 : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { - 8002084: b480 push {r7} - 8002086: af00 add r7, sp, #0 + 8002120: b480 push {r7} + 8002122: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } - 8002088: bf00 nop - 800208a: 46bd mov sp, r7 - 800208c: f85d 7b04 ldr.w r7, [sp], #4 - 8002090: 4770 bx lr + 8002124: bf00 nop + 8002126: 46bd mov sp, r7 + 8002128: f85d 7b04 ldr.w r7, [sp], #4 + 800212c: 4770 bx lr -08002092 : +0800212e : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { - 8002092: b480 push {r7} - 8002094: af00 add r7, sp, #0 + 800212e: b480 push {r7} + 8002130: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } - 8002096: bf00 nop - 8002098: 46bd mov sp, r7 - 800209a: f85d 7b04 ldr.w r7, [sp], #4 - 800209e: 4770 bx lr + 8002132: bf00 nop + 8002134: 46bd mov sp, r7 + 8002136: f85d 7b04 ldr.w r7, [sp], #4 + 800213a: 4770 bx lr -080020a0 : +0800213c : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { - 80020a0: b480 push {r7} - 80020a2: af00 add r7, sp, #0 + 800213c: b480 push {r7} + 800213e: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } - 80020a4: bf00 nop - 80020a6: 46bd mov sp, r7 - 80020a8: f85d 7b04 ldr.w r7, [sp], #4 - 80020ac: 4770 bx lr + 8002140: bf00 nop + 8002142: 46bd mov sp, r7 + 8002144: f85d 7b04 ldr.w r7, [sp], #4 + 8002148: 4770 bx lr -080020ae : +0800214a : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { - 80020ae: b580 push {r7, lr} - 80020b0: af00 add r7, sp, #0 + 800214a: b580 push {r7, lr} + 800214c: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); - 80020b2: f000 f8c5 bl 8002240 + 800214e: f000 f8c5 bl 80022dc /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } - 80020b6: bf00 nop - 80020b8: bd80 pop {r7, pc} + 8002152: bf00 nop + 8002154: bd80 pop {r7, pc} ... -080020bc : +08002158 : /** * @brief This function handles DMA1 channel1 global interrupt. */ void DMA1_Channel1_IRQHandler(void) { - 80020bc: b580 push {r7, lr} - 80020be: af00 add r7, sp, #0 + 8002158: b580 push {r7, lr} + 800215a: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Channel1_IRQn 0 */ /* USER CODE END DMA1_Channel1_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_adc1); - 80020c0: 4802 ldr r0, [pc, #8] @ (80020cc ) - 80020c2: f002 fa68 bl 8004596 + 800215c: 4802 ldr r0, [pc, #8] @ (8002168 ) + 800215e: f002 fa68 bl 8004632 /* USER CODE BEGIN DMA1_Channel1_IRQn 1 */ /* USER CODE END DMA1_Channel1_IRQn 1 */ } - 80020c6: bf00 nop - 80020c8: bd80 pop {r7, pc} - 80020ca: bf00 nop - 80020cc: 20000164 .word 0x20000164 + 8002162: bf00 nop + 8002164: bd80 pop {r7, pc} + 8002166: bf00 nop + 8002168: 20000164 .word 0x20000164 -080020d0 : +0800216c : /** * @brief This function handles ADC1 and ADC2 interrupts. */ void ADC1_2_IRQHandler(void) { - 80020d0: b580 push {r7, lr} - 80020d2: af00 add r7, sp, #0 + 800216c: b580 push {r7, lr} + 800216e: af00 add r7, sp, #0 /* USER CODE BEGIN ADC1_2_IRQn 0 */ /* USER CODE END ADC1_2_IRQn 0 */ HAL_ADC_IRQHandler(&hadc1); - 80020d4: 4803 ldr r0, [pc, #12] @ (80020e4 ) - 80020d6: f000 fb81 bl 80027dc + 8002170: 4803 ldr r0, [pc, #12] @ (8002180 ) + 8002172: f000 fb81 bl 8002878 HAL_ADC_IRQHandler(&hadc2); - 80020da: 4803 ldr r0, [pc, #12] @ (80020e8 ) - 80020dc: f000 fb7e bl 80027dc + 8002176: 4803 ldr r0, [pc, #12] @ (8002184 ) + 8002178: f000 fb7e bl 8002878 /* USER CODE BEGIN ADC1_2_IRQn 1 */ /* USER CODE END ADC1_2_IRQn 1 */ } - 80020e0: bf00 nop - 80020e2: bd80 pop {r7, pc} - 80020e4: 200000c4 .word 0x200000c4 - 80020e8: 20000114 .word 0x20000114 + 800217c: bf00 nop + 800217e: bd80 pop {r7, pc} + 8002180: 200000c4 .word 0x200000c4 + 8002184: 20000114 .word 0x20000114 -080020ec : +08002188 : /** * @brief This function handles USB low priority or CAN_RX0 interrupts. */ void USB_LP_CAN_RX0_IRQHandler(void) { - 80020ec: b580 push {r7, lr} - 80020ee: af00 add r7, sp, #0 + 8002188: b580 push {r7, lr} + 800218a: af00 add r7, sp, #0 /* USER CODE BEGIN USB_LP_CAN_RX0_IRQn 0 */ /* USER CODE END USB_LP_CAN_RX0_IRQn 0 */ HAL_CAN_IRQHandler(&hcan); - 80020f0: 4802 ldr r0, [pc, #8] @ (80020fc ) - 80020f2: f001 fe6a bl 8003dca + 800218c: 4802 ldr r0, [pc, #8] @ (8002198 ) + 800218e: f001 fe6a bl 8003e66 /* USER CODE BEGIN USB_LP_CAN_RX0_IRQn 1 */ /* USER CODE END USB_LP_CAN_RX0_IRQn 1 */ } - 80020f6: bf00 nop - 80020f8: bd80 pop {r7, pc} - 80020fa: bf00 nop - 80020fc: 200001ec .word 0x200001ec + 8002192: bf00 nop + 8002194: bd80 pop {r7, pc} + 8002196: bf00 nop + 8002198: 200001ec .word 0x200001ec -08002100 : +0800219c : /** * @brief This function handles CAN RX1 interrupt. */ void CAN_RX1_IRQHandler(void) { - 8002100: b580 push {r7, lr} - 8002102: af00 add r7, sp, #0 + 800219c: b580 push {r7, lr} + 800219e: af00 add r7, sp, #0 /* USER CODE BEGIN CAN_RX1_IRQn 0 */ /* USER CODE END CAN_RX1_IRQn 0 */ HAL_CAN_IRQHandler(&hcan); - 8002104: 4802 ldr r0, [pc, #8] @ (8002110 ) - 8002106: f001 fe60 bl 8003dca + 80021a0: 4802 ldr r0, [pc, #8] @ (80021ac ) + 80021a2: f001 fe60 bl 8003e66 /* USER CODE BEGIN CAN_RX1_IRQn 1 */ /* USER CODE END CAN_RX1_IRQn 1 */ } - 800210a: bf00 nop - 800210c: bd80 pop {r7, pc} - 800210e: bf00 nop - 8002110: 200001ec .word 0x200001ec + 80021a6: bf00 nop + 80021a8: bd80 pop {r7, pc} + 80021aa: bf00 nop + 80021ac: 200001ec .word 0x200001ec -08002114 : +080021b0 : /** * @brief This function handles Timer 6 interrupt and DAC underrun interrupts. */ void TIM6_DAC_IRQHandler(void) { - 8002114: b580 push {r7, lr} - 8002116: af00 add r7, sp, #0 + 80021b0: b580 push {r7, lr} + 80021b2: af00 add r7, sp, #0 /* USER CODE BEGIN TIM6_DAC_IRQn 0 */ /* USER CODE END TIM6_DAC_IRQn 0 */ HAL_TIM_IRQHandler(&htim6); - 8002118: 4802 ldr r0, [pc, #8] @ (8002124 ) - 800211a: f004 f97f bl 800641c + 80021b4: 4802 ldr r0, [pc, #8] @ (80021c0 ) + 80021b6: f004 f97f bl 80064b8 /* USER CODE BEGIN TIM6_DAC_IRQn 1 */ /* USER CODE END TIM6_DAC_IRQn 1 */ } - 800211e: bf00 nop - 8002120: bd80 pop {r7, pc} - 8002122: bf00 nop - 8002124: 20000214 .word 0x20000214 + 80021ba: bf00 nop + 80021bc: bd80 pop {r7, pc} + 80021be: bf00 nop + 80021c0: 20000214 .word 0x20000214 -08002128 : +080021c4 : /** * @brief This function handles DMA2 channel1 global interrupt. */ void DMA2_Channel1_IRQHandler(void) { - 8002128: b580 push {r7, lr} - 800212a: af00 add r7, sp, #0 + 80021c4: b580 push {r7, lr} + 80021c6: af00 add r7, sp, #0 /* USER CODE BEGIN DMA2_Channel1_IRQn 0 */ /* USER CODE END DMA2_Channel1_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_adc2); - 800212c: 4802 ldr r0, [pc, #8] @ (8002138 ) - 800212e: f002 fa32 bl 8004596 + 80021c8: 4802 ldr r0, [pc, #8] @ (80021d4 ) + 80021ca: f002 fa32 bl 8004632 /* USER CODE BEGIN DMA2_Channel1_IRQn 1 */ /* USER CODE END DMA2_Channel1_IRQn 1 */ } - 8002132: bf00 nop - 8002134: bd80 pop {r7, pc} - 8002136: bf00 nop - 8002138: 200001a8 .word 0x200001a8 + 80021ce: bf00 nop + 80021d0: bd80 pop {r7, pc} + 80021d2: bf00 nop + 80021d4: 200001a8 .word 0x200001a8 -0800213c : +080021d8 : * @brief Setup the microcontroller system * @param None * @retval None */ void SystemInit(void) { - 800213c: b480 push {r7} - 800213e: af00 add r7, sp, #0 + 80021d8: b480 push {r7} + 80021da: af00 add r7, sp, #0 /* FPU settings --------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ - 8002140: 4b06 ldr r3, [pc, #24] @ (800215c ) - 8002142: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 - 8002146: 4a05 ldr r2, [pc, #20] @ (800215c ) - 8002148: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000 - 800214c: f8c2 3088 str.w r3, [r2, #136] @ 0x88 + 80021dc: 4b06 ldr r3, [pc, #24] @ (80021f8 ) + 80021de: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 + 80021e2: 4a05 ldr r2, [pc, #20] @ (80021f8 ) + 80021e4: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000 + 80021e8: f8c2 3088 str.w r3, [r2, #136] @ 0x88 /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ #endif /* USER_VECT_TAB_ADDRESS */ } - 8002150: bf00 nop - 8002152: 46bd mov sp, r7 - 8002154: f85d 7b04 ldr.w r7, [sp], #4 - 8002158: 4770 bx lr - 800215a: bf00 nop - 800215c: e000ed00 .word 0xe000ed00 + 80021ec: bf00 nop + 80021ee: 46bd mov sp, r7 + 80021f0: f85d 7b04 ldr.w r7, [sp], #4 + 80021f4: 4770 bx lr + 80021f6: bf00 nop + 80021f8: e000ed00 .word 0xe000ed00 -08002160 : +080021fc : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr sp, =_estack /* Atollic update: set stack pointer */ - 8002160: f8df d034 ldr.w sp, [pc, #52] @ 8002198 + 80021fc: f8df d034 ldr.w sp, [pc, #52] @ 8002234 /* Call the clock system initialization function.*/ bl SystemInit - 8002164: f7ff ffea bl 800213c + 8002200: f7ff ffea bl 80021d8 /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata - 8002168: 480c ldr r0, [pc, #48] @ (800219c ) + 8002204: 480c ldr r0, [pc, #48] @ (8002238 ) ldr r1, =_edata - 800216a: 490d ldr r1, [pc, #52] @ (80021a0 ) + 8002206: 490d ldr r1, [pc, #52] @ (800223c ) ldr r2, =_sidata - 800216c: 4a0d ldr r2, [pc, #52] @ (80021a4 ) + 8002208: 4a0d ldr r2, [pc, #52] @ (8002240 ) movs r3, #0 - 800216e: 2300 movs r3, #0 + 800220a: 2300 movs r3, #0 b LoopCopyDataInit - 8002170: e002 b.n 8002178 + 800220c: e002 b.n 8002214 -08002172 : +0800220e : CopyDataInit: ldr r4, [r2, r3] - 8002172: 58d4 ldr r4, [r2, r3] + 800220e: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] - 8002174: 50c4 str r4, [r0, r3] + 8002210: 50c4 str r4, [r0, r3] adds r3, r3, #4 - 8002176: 3304 adds r3, #4 + 8002212: 3304 adds r3, #4 -08002178 : +08002214 : LoopCopyDataInit: adds r4, r0, r3 - 8002178: 18c4 adds r4, r0, r3 + 8002214: 18c4 adds r4, r0, r3 cmp r4, r1 - 800217a: 428c cmp r4, r1 + 8002216: 428c cmp r4, r1 bcc CopyDataInit - 800217c: d3f9 bcc.n 8002172 + 8002218: d3f9 bcc.n 800220e /* Zero fill the bss segment. */ ldr r2, =_sbss - 800217e: 4a0a ldr r2, [pc, #40] @ (80021a8 ) + 800221a: 4a0a ldr r2, [pc, #40] @ (8002244 ) ldr r4, =_ebss - 8002180: 4c0a ldr r4, [pc, #40] @ (80021ac ) + 800221c: 4c0a ldr r4, [pc, #40] @ (8002248 ) movs r3, #0 - 8002182: 2300 movs r3, #0 + 800221e: 2300 movs r3, #0 b LoopFillZerobss - 8002184: e001 b.n 800218a + 8002220: e001 b.n 8002226 -08002186 : +08002222 : FillZerobss: str r3, [r2] - 8002186: 6013 str r3, [r2, #0] + 8002222: 6013 str r3, [r2, #0] adds r2, r2, #4 - 8002188: 3204 adds r2, #4 + 8002224: 3204 adds r2, #4 -0800218a : +08002226 : LoopFillZerobss: cmp r2, r4 - 800218a: 42a2 cmp r2, r4 + 8002226: 42a2 cmp r2, r4 bcc FillZerobss - 800218c: d3fb bcc.n 8002186 + 8002228: d3fb bcc.n 8002222 /* Call static constructors */ bl __libc_init_array - 800218e: f004 ffdf bl 8007150 <__libc_init_array> + 800222a: f004 ffdf bl 80071ec <__libc_init_array> /* Call the application's entry point.*/ bl main - 8002192: f7ff f82f bl 80011f4
+ 800222e: f7fe ffed bl 800120c
-08002196 : +08002232 : LoopForever: b LoopForever - 8002196: e7fe b.n 8002196 + 8002232: e7fe b.n 8002232 ldr sp, =_estack /* Atollic update: set stack pointer */ - 8002198: 20008000 .word 0x20008000 + 8002234: 20008000 .word 0x20008000 ldr r0, =_sdata - 800219c: 20000000 .word 0x20000000 + 8002238: 20000000 .word 0x20000000 ldr r1, =_edata - 80021a0: 2000000c .word 0x2000000c + 800223c: 2000000c .word 0x2000000c ldr r2, =_sidata - 80021a4: 080071f0 .word 0x080071f0 + 8002240: 0800728c .word 0x0800728c ldr r2, =_sbss - 80021a8: 2000000c .word 0x2000000c + 8002244: 2000000c .word 0x2000000c ldr r4, =_ebss - 80021ac: 2000030c .word 0x2000030c + 8002248: 20000300 .word 0x20000300 -080021b0 : +0800224c : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop - 80021b0: e7fe b.n 80021b0 + 800224c: e7fe b.n 800224c ... -080021b4 : +08002250 : * In the default implementation,Systick is used as source of time base. * The tick variable is incremented each 1ms in its ISR. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { - 80021b4: b580 push {r7, lr} - 80021b6: af00 add r7, sp, #0 + 8002250: b580 push {r7, lr} + 8002252: af00 add r7, sp, #0 /* Configure Flash prefetch */ #if (PREFETCH_ENABLE != 0U) __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); - 80021b8: 4b08 ldr r3, [pc, #32] @ (80021dc ) - 80021ba: 681b ldr r3, [r3, #0] - 80021bc: 4a07 ldr r2, [pc, #28] @ (80021dc ) - 80021be: f043 0310 orr.w r3, r3, #16 - 80021c2: 6013 str r3, [r2, #0] + 8002254: 4b08 ldr r3, [pc, #32] @ (8002278 ) + 8002256: 681b ldr r3, [r3, #0] + 8002258: 4a07 ldr r2, [pc, #28] @ (8002278 ) + 800225a: f043 0310 orr.w r3, r3, #16 + 800225e: 6013 str r3, [r2, #0] #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); - 80021c4: 2003 movs r0, #3 - 80021c6: f002 f8ff bl 80043c8 + 8002260: 2003 movs r0, #3 + 8002262: f002 f8ff bl 8004464 /* Enable systick and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); - 80021ca: 200f movs r0, #15 - 80021cc: f000 f808 bl 80021e0 + 8002266: 200f movs r0, #15 + 8002268: f000 f808 bl 800227c /* Init the low level hardware */ HAL_MspInit(); - 80021d0: f7ff fd30 bl 8001c34 + 800226c: f7ff fd30 bl 8001cd0 /* Return function status */ return HAL_OK; - 80021d4: 2300 movs r3, #0 + 8002270: 2300 movs r3, #0 } - 80021d6: 4618 mov r0, r3 - 80021d8: bd80 pop {r7, pc} - 80021da: bf00 nop - 80021dc: 40022000 .word 0x40022000 + 8002272: 4618 mov r0, r3 + 8002274: bd80 pop {r7, pc} + 8002276: bf00 nop + 8002278: 40022000 .word 0x40022000 -080021e0 : +0800227c : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { - 80021e0: b580 push {r7, lr} - 80021e2: b082 sub sp, #8 - 80021e4: af00 add r7, sp, #0 - 80021e6: 6078 str r0, [r7, #4] + 800227c: b580 push {r7, lr} + 800227e: b082 sub sp, #8 + 8002280: af00 add r7, sp, #0 + 8002282: 6078 str r0, [r7, #4] /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) - 80021e8: 4b12 ldr r3, [pc, #72] @ (8002234 ) - 80021ea: 681a ldr r2, [r3, #0] - 80021ec: 4b12 ldr r3, [pc, #72] @ (8002238 ) - 80021ee: 781b ldrb r3, [r3, #0] - 80021f0: 4619 mov r1, r3 - 80021f2: f44f 737a mov.w r3, #1000 @ 0x3e8 - 80021f6: fbb3 f3f1 udiv r3, r3, r1 - 80021fa: fbb2 f3f3 udiv r3, r2, r3 - 80021fe: 4618 mov r0, r3 - 8002200: f002 f917 bl 8004432 - 8002204: 4603 mov r3, r0 - 8002206: 2b00 cmp r3, #0 - 8002208: d001 beq.n 800220e + 8002284: 4b12 ldr r3, [pc, #72] @ (80022d0 ) + 8002286: 681a ldr r2, [r3, #0] + 8002288: 4b12 ldr r3, [pc, #72] @ (80022d4 ) + 800228a: 781b ldrb r3, [r3, #0] + 800228c: 4619 mov r1, r3 + 800228e: f44f 737a mov.w r3, #1000 @ 0x3e8 + 8002292: fbb3 f3f1 udiv r3, r3, r1 + 8002296: fbb2 f3f3 udiv r3, r2, r3 + 800229a: 4618 mov r0, r3 + 800229c: f002 f917 bl 80044ce + 80022a0: 4603 mov r3, r0 + 80022a2: 2b00 cmp r3, #0 + 80022a4: d001 beq.n 80022aa { return HAL_ERROR; - 800220a: 2301 movs r3, #1 - 800220c: e00e b.n 800222c + 80022a6: 2301 movs r3, #1 + 80022a8: e00e b.n 80022c8 } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) - 800220e: 687b ldr r3, [r7, #4] - 8002210: 2b0f cmp r3, #15 - 8002212: d80a bhi.n 800222a + 80022aa: 687b ldr r3, [r7, #4] + 80022ac: 2b0f cmp r3, #15 + 80022ae: d80a bhi.n 80022c6 { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); - 8002214: 2200 movs r2, #0 - 8002216: 6879 ldr r1, [r7, #4] - 8002218: f04f 30ff mov.w r0, #4294967295 - 800221c: f002 f8df bl 80043de + 80022b0: 2200 movs r2, #0 + 80022b2: 6879 ldr r1, [r7, #4] + 80022b4: f04f 30ff mov.w r0, #4294967295 + 80022b8: f002 f8df bl 800447a uwTickPrio = TickPriority; - 8002220: 4a06 ldr r2, [pc, #24] @ (800223c ) - 8002222: 687b ldr r3, [r7, #4] - 8002224: 6013 str r3, [r2, #0] + 80022bc: 4a06 ldr r2, [pc, #24] @ (80022d8 ) + 80022be: 687b ldr r3, [r7, #4] + 80022c0: 6013 str r3, [r2, #0] else { return HAL_ERROR; } /* Return function status */ return HAL_OK; - 8002226: 2300 movs r3, #0 - 8002228: e000 b.n 800222c + 80022c2: 2300 movs r3, #0 + 80022c4: e000 b.n 80022c8 return HAL_ERROR; - 800222a: 2301 movs r3, #1 + 80022c6: 2301 movs r3, #1 } - 800222c: 4618 mov r0, r3 - 800222e: 3708 adds r7, #8 - 8002230: 46bd mov sp, r7 - 8002232: bd80 pop {r7, pc} - 8002234: 20000000 .word 0x20000000 - 8002238: 20000008 .word 0x20000008 - 800223c: 20000004 .word 0x20000004 + 80022c8: 4618 mov r0, r3 + 80022ca: 3708 adds r7, #8 + 80022cc: 46bd mov sp, r7 + 80022ce: bd80 pop {r7, pc} + 80022d0: 20000000 .word 0x20000000 + 80022d4: 20000008 .word 0x20000008 + 80022d8: 20000004 .word 0x20000004 -08002240 : +080022dc : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { - 8002240: b480 push {r7} - 8002242: af00 add r7, sp, #0 + 80022dc: b480 push {r7} + 80022de: af00 add r7, sp, #0 uwTick += uwTickFreq; - 8002244: 4b06 ldr r3, [pc, #24] @ (8002260 ) - 8002246: 781b ldrb r3, [r3, #0] - 8002248: 461a mov r2, r3 - 800224a: 4b06 ldr r3, [pc, #24] @ (8002264 ) - 800224c: 681b ldr r3, [r3, #0] - 800224e: 4413 add r3, r2 - 8002250: 4a04 ldr r2, [pc, #16] @ (8002264 ) - 8002252: 6013 str r3, [r2, #0] + 80022e0: 4b06 ldr r3, [pc, #24] @ (80022fc ) + 80022e2: 781b ldrb r3, [r3, #0] + 80022e4: 461a mov r2, r3 + 80022e6: 4b06 ldr r3, [pc, #24] @ (8002300 ) + 80022e8: 681b ldr r3, [r3, #0] + 80022ea: 4413 add r3, r2 + 80022ec: 4a04 ldr r2, [pc, #16] @ (8002300 ) + 80022ee: 6013 str r3, [r2, #0] } - 8002254: bf00 nop - 8002256: 46bd mov sp, r7 - 8002258: f85d 7b04 ldr.w r7, [sp], #4 - 800225c: 4770 bx lr - 800225e: bf00 nop - 8002260: 20000008 .word 0x20000008 - 8002264: 20000308 .word 0x20000308 + 80022f0: bf00 nop + 80022f2: 46bd mov sp, r7 + 80022f4: f85d 7b04 ldr.w r7, [sp], #4 + 80022f8: 4770 bx lr + 80022fa: bf00 nop + 80022fc: 20000008 .word 0x20000008 + 8002300: 200002fc .word 0x200002fc -08002268 : +08002304 : * @note The function is declared as __Weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { - 8002268: b480 push {r7} - 800226a: af00 add r7, sp, #0 + 8002304: b480 push {r7} + 8002306: af00 add r7, sp, #0 return uwTick; - 800226c: 4b03 ldr r3, [pc, #12] @ (800227c ) - 800226e: 681b ldr r3, [r3, #0] + 8002308: 4b03 ldr r3, [pc, #12] @ (8002318 ) + 800230a: 681b ldr r3, [r3, #0] } - 8002270: 4618 mov r0, r3 - 8002272: 46bd mov sp, r7 - 8002274: f85d 7b04 ldr.w r7, [sp], #4 - 8002278: 4770 bx lr - 800227a: bf00 nop - 800227c: 20000308 .word 0x20000308 + 800230c: 4618 mov r0, r3 + 800230e: 46bd mov sp, r7 + 8002310: f85d 7b04 ldr.w r7, [sp], #4 + 8002314: 4770 bx lr + 8002316: bf00 nop + 8002318: 200002fc .word 0x200002fc -08002280 : +0800231c : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { - 8002280: b580 push {r7, lr} - 8002282: b084 sub sp, #16 - 8002284: af00 add r7, sp, #0 - 8002286: 6078 str r0, [r7, #4] + 800231c: b580 push {r7, lr} + 800231e: b084 sub sp, #16 + 8002320: af00 add r7, sp, #0 + 8002322: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); - 8002288: f7ff ffee bl 8002268 - 800228c: 60b8 str r0, [r7, #8] + 8002324: f7ff ffee bl 8002304 + 8002328: 60b8 str r0, [r7, #8] uint32_t wait = Delay; - 800228e: 687b ldr r3, [r7, #4] - 8002290: 60fb str r3, [r7, #12] + 800232a: 687b ldr r3, [r7, #4] + 800232c: 60fb str r3, [r7, #12] /* Add freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) - 8002292: 68fb ldr r3, [r7, #12] - 8002294: f1b3 3fff cmp.w r3, #4294967295 - 8002298: d005 beq.n 80022a6 + 800232e: 68fb ldr r3, [r7, #12] + 8002330: f1b3 3fff cmp.w r3, #4294967295 + 8002334: d005 beq.n 8002342 { wait += (uint32_t)(uwTickFreq); - 800229a: 4b0a ldr r3, [pc, #40] @ (80022c4 ) - 800229c: 781b ldrb r3, [r3, #0] - 800229e: 461a mov r2, r3 - 80022a0: 68fb ldr r3, [r7, #12] - 80022a2: 4413 add r3, r2 - 80022a4: 60fb str r3, [r7, #12] + 8002336: 4b0a ldr r3, [pc, #40] @ (8002360 ) + 8002338: 781b ldrb r3, [r3, #0] + 800233a: 461a mov r2, r3 + 800233c: 68fb ldr r3, [r7, #12] + 800233e: 4413 add r3, r2 + 8002340: 60fb str r3, [r7, #12] } while((HAL_GetTick() - tickstart) < wait) - 80022a6: bf00 nop - 80022a8: f7ff ffde bl 8002268 - 80022ac: 4602 mov r2, r0 - 80022ae: 68bb ldr r3, [r7, #8] - 80022b0: 1ad3 subs r3, r2, r3 - 80022b2: 68fa ldr r2, [r7, #12] - 80022b4: 429a cmp r2, r3 - 80022b6: d8f7 bhi.n 80022a8 + 8002342: bf00 nop + 8002344: f7ff ffde bl 8002304 + 8002348: 4602 mov r2, r0 + 800234a: 68bb ldr r3, [r7, #8] + 800234c: 1ad3 subs r3, r2, r3 + 800234e: 68fa ldr r2, [r7, #12] + 8002350: 429a cmp r2, r3 + 8002352: d8f7 bhi.n 8002344 { } } - 80022b8: bf00 nop - 80022ba: bf00 nop - 80022bc: 3710 adds r7, #16 - 80022be: 46bd mov sp, r7 - 80022c0: bd80 pop {r7, pc} - 80022c2: bf00 nop - 80022c4: 20000008 .word 0x20000008 + 8002354: bf00 nop + 8002356: bf00 nop + 8002358: 3710 adds r7, #16 + 800235a: 46bd mov sp, r7 + 800235c: bd80 pop {r7, pc} + 800235e: bf00 nop + 8002360: 20000008 .word 0x20000008 -080022c8 : +08002364 : * @brief Conversion DMA half-transfer callback in non blocking mode * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) { - 80022c8: b480 push {r7} - 80022ca: b083 sub sp, #12 - 80022cc: af00 add r7, sp, #0 - 80022ce: 6078 str r0, [r7, #4] + 8002364: b480 push {r7} + 8002366: b083 sub sp, #12 + 8002368: af00 add r7, sp, #0 + 800236a: 6078 str r0, [r7, #4] UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file. */ } - 80022d0: bf00 nop - 80022d2: 370c adds r7, #12 - 80022d4: 46bd mov sp, r7 - 80022d6: f85d 7b04 ldr.w r7, [sp], #4 - 80022da: 4770 bx lr + 800236c: bf00 nop + 800236e: 370c adds r7, #12 + 8002370: 46bd mov sp, r7 + 8002372: f85d 7b04 ldr.w r7, [sp], #4 + 8002376: 4770 bx lr -080022dc : +08002378 : * @brief Analog watchdog callback in non blocking mode. * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) { - 80022dc: b480 push {r7} - 80022de: b083 sub sp, #12 - 80022e0: af00 add r7, sp, #0 - 80022e2: 6078 str r0, [r7, #4] + 8002378: b480 push {r7} + 800237a: b083 sub sp, #12 + 800237c: af00 add r7, sp, #0 + 800237e: 6078 str r0, [r7, #4] UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_LevelOoutOfWindowCallback must be implemented in the user file. */ } - 80022e4: bf00 nop - 80022e6: 370c adds r7, #12 - 80022e8: 46bd mov sp, r7 - 80022ea: f85d 7b04 ldr.w r7, [sp], #4 - 80022ee: 4770 bx lr + 8002380: bf00 nop + 8002382: 370c adds r7, #12 + 8002384: 46bd mov sp, r7 + 8002386: f85d 7b04 ldr.w r7, [sp], #4 + 800238a: 4770 bx lr -080022f0 : +0800238c : * (ADC conversion with interruption or transfer by DMA) * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) { - 80022f0: b480 push {r7} - 80022f2: b083 sub sp, #12 - 80022f4: af00 add r7, sp, #0 - 80022f6: 6078 str r0, [r7, #4] + 800238c: b480 push {r7} + 800238e: b083 sub sp, #12 + 8002390: af00 add r7, sp, #0 + 8002392: 6078 str r0, [r7, #4] UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ErrorCallback must be implemented in the user file. */ } - 80022f8: bf00 nop - 80022fa: 370c adds r7, #12 - 80022fc: 46bd mov sp, r7 - 80022fe: f85d 7b04 ldr.w r7, [sp], #4 - 8002302: 4770 bx lr + 8002394: bf00 nop + 8002396: 370c adds r7, #12 + 8002398: 46bd mov sp, r7 + 800239a: f85d 7b04 ldr.w r7, [sp], #4 + 800239e: 4770 bx lr -08002304 : +080023a0 : * without disabling the other ADCs sharing the same common group. * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) { - 8002304: b580 push {r7, lr} - 8002306: b09a sub sp, #104 @ 0x68 - 8002308: af00 add r7, sp, #0 - 800230a: 6078 str r0, [r7, #4] + 80023a0: b580 push {r7, lr} + 80023a2: b09a sub sp, #104 @ 0x68 + 80023a4: af00 add r7, sp, #0 + 80023a6: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; - 800230c: 2300 movs r3, #0 - 800230e: f887 3067 strb.w r3, [r7, #103] @ 0x67 + 80023a8: 2300 movs r3, #0 + 80023aa: f887 3067 strb.w r3, [r7, #103] @ 0x67 ADC_Common_TypeDef *tmpADC_Common; ADC_HandleTypeDef tmphadcSharingSameCommonRegister; uint32_t tmpCFGR = 0U; - 8002312: 2300 movs r3, #0 - 8002314: 663b str r3, [r7, #96] @ 0x60 + 80023ae: 2300 movs r3, #0 + 80023b0: 663b str r3, [r7, #96] @ 0x60 __IO uint32_t wait_loop_index = 0U; - 8002316: 2300 movs r3, #0 - 8002318: 60bb str r3, [r7, #8] + 80023b2: 2300 movs r3, #0 + 80023b4: 60bb str r3, [r7, #8] /* Check ADC handle */ if(hadc == NULL) - 800231a: 687b ldr r3, [r7, #4] - 800231c: 2b00 cmp r3, #0 - 800231e: d101 bne.n 8002324 + 80023b6: 687b ldr r3, [r7, #4] + 80023b8: 2b00 cmp r3, #0 + 80023ba: d101 bne.n 80023c0 { return HAL_ERROR; - 8002320: 2301 movs r3, #1 - 8002322: e172 b.n 800260a + 80023bc: 2301 movs r3, #1 + 80023be: e172 b.n 80026a6 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests)); assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait)); if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) - 8002324: 687b ldr r3, [r7, #4] - 8002326: 691b ldr r3, [r3, #16] - 8002328: 2b00 cmp r3, #0 + 80023c0: 687b ldr r3, [r7, #4] + 80023c2: 691b ldr r3, [r3, #16] + 80023c4: 2b00 cmp r3, #0 assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion)); } } /* Configuration of ADC core parameters and ADC MSP related parameters */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) - 800232a: 687b ldr r3, [r7, #4] - 800232c: 6c1b ldr r3, [r3, #64] @ 0x40 - 800232e: f003 0310 and.w r3, r3, #16 - 8002332: 2b00 cmp r3, #0 - 8002334: d176 bne.n 8002424 + 80023c6: 687b ldr r3, [r7, #4] + 80023c8: 6c1b ldr r3, [r3, #64] @ 0x40 + 80023ca: f003 0310 and.w r3, r3, #16 + 80023ce: 2b00 cmp r3, #0 + 80023d0: d176 bne.n 80024c0 /* procedure. */ /* Actions performed only if ADC is coming from state reset: */ /* - Initialization of ADC MSP */ /* - ADC voltage regulator enable */ if (hadc->State == HAL_ADC_STATE_RESET) - 8002336: 687b ldr r3, [r7, #4] - 8002338: 6c1b ldr r3, [r3, #64] @ 0x40 - 800233a: 2b00 cmp r3, #0 - 800233c: d152 bne.n 80023e4 + 80023d2: 687b ldr r3, [r7, #4] + 80023d4: 6c1b ldr r3, [r3, #64] @ 0x40 + 80023d6: 2b00 cmp r3, #0 + 80023d8: d152 bne.n 8002480 { /* Initialize ADC error code */ ADC_CLEAR_ERRORCODE(hadc); - 800233e: 687b ldr r3, [r7, #4] - 8002340: 2200 movs r2, #0 - 8002342: 645a str r2, [r3, #68] @ 0x44 + 80023da: 687b ldr r3, [r7, #4] + 80023dc: 2200 movs r2, #0 + 80023de: 645a str r2, [r3, #68] @ 0x44 /* Initialize HAL ADC API internal variables */ hadc->InjectionConfig.ChannelCount = 0U; - 8002344: 687b ldr r3, [r7, #4] - 8002346: 2200 movs r2, #0 - 8002348: 64da str r2, [r3, #76] @ 0x4c + 80023e0: 687b ldr r3, [r7, #4] + 80023e2: 2200 movs r2, #0 + 80023e4: 64da str r2, [r3, #76] @ 0x4c hadc->InjectionConfig.ContextQueue = 0U; - 800234a: 687b ldr r3, [r7, #4] - 800234c: 2200 movs r2, #0 - 800234e: 649a str r2, [r3, #72] @ 0x48 + 80023e6: 687b ldr r3, [r7, #4] + 80023e8: 2200 movs r2, #0 + 80023ea: 649a str r2, [r3, #72] @ 0x48 /* Allocate lock resource and initialize it */ hadc->Lock = HAL_UNLOCKED; - 8002350: 687b ldr r3, [r7, #4] - 8002352: 2200 movs r2, #0 - 8002354: f883 203c strb.w r2, [r3, #60] @ 0x3c + 80023ec: 687b ldr r3, [r7, #4] + 80023ee: 2200 movs r2, #0 + 80023f0: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Init the low level hardware */ hadc->MspInitCallback(hadc); #else /* Init the low level hardware */ HAL_ADC_MspInit(hadc); - 8002358: 6878 ldr r0, [r7, #4] - 800235a: f7ff fc8f bl 8001c7c + 80023f4: 6878 ldr r0, [r7, #4] + 80023f6: f7ff fc8f bl 8001d18 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Enable voltage regulator (if disabled at this step) */ if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN_0)) - 800235e: 687b ldr r3, [r7, #4] - 8002360: 681b ldr r3, [r3, #0] - 8002362: 689b ldr r3, [r3, #8] - 8002364: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 - 8002368: 2b00 cmp r3, #0 - 800236a: d13b bne.n 80023e4 + 80023fa: 687b ldr r3, [r7, #4] + 80023fc: 681b ldr r3, [r3, #0] + 80023fe: 689b ldr r3, [r3, #8] + 8002400: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 8002404: 2b00 cmp r3, #0 + 8002406: d13b bne.n 8002480 /* enabling the ADC. This temporization must be implemented by */ /* software and is equal to 10 us in the worst case */ /* process/temperature/power supply. */ /* Disable the ADC (if not already disabled) */ tmp_hal_status = ADC_Disable(hadc); - 800236c: 6878 ldr r0, [r7, #4] - 800236e: f001 f8a5 bl 80034bc - 8002372: 4603 mov r3, r0 - 8002374: f887 3067 strb.w r3, [r7, #103] @ 0x67 + 8002408: 6878 ldr r0, [r7, #4] + 800240a: f001 f8a5 bl 8003558 + 800240e: 4603 mov r3, r0 + 8002410: f887 3067 strb.w r3, [r7, #103] @ 0x67 /* Check if ADC is effectively disabled */ /* Configuration of ADC parameters if previous preliminary actions */ /* are correctly completed. */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && - 8002378: 687b ldr r3, [r7, #4] - 800237a: 6c1b ldr r3, [r3, #64] @ 0x40 - 800237c: f003 0310 and.w r3, r3, #16 - 8002380: 2b00 cmp r3, #0 - 8002382: d12f bne.n 80023e4 - 8002384: f897 3067 ldrb.w r3, [r7, #103] @ 0x67 - 8002388: 2b00 cmp r3, #0 - 800238a: d12b bne.n 80023e4 + 8002414: 687b ldr r3, [r7, #4] + 8002416: 6c1b ldr r3, [r3, #64] @ 0x40 + 8002418: f003 0310 and.w r3, r3, #16 + 800241c: 2b00 cmp r3, #0 + 800241e: d12f bne.n 8002480 + 8002420: f897 3067 ldrb.w r3, [r7, #103] @ 0x67 + 8002424: 2b00 cmp r3, #0 + 8002426: d12b bne.n 8002480 (tmp_hal_status == HAL_OK) ) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, - 800238c: 687b ldr r3, [r7, #4] - 800238e: 6c1b ldr r3, [r3, #64] @ 0x40 - 8002390: f423 5388 bic.w r3, r3, #4352 @ 0x1100 - 8002394: f023 0302 bic.w r3, r3, #2 - 8002398: f043 0202 orr.w r2, r3, #2 - 800239c: 687b ldr r3, [r7, #4] - 800239e: 641a str r2, [r3, #64] @ 0x40 + 8002428: 687b ldr r3, [r7, #4] + 800242a: 6c1b ldr r3, [r3, #64] @ 0x40 + 800242c: f423 5388 bic.w r3, r3, #4352 @ 0x1100 + 8002430: f023 0302 bic.w r3, r3, #2 + 8002434: f043 0202 orr.w r2, r3, #2 + 8002438: 687b ldr r3, [r7, #4] + 800243a: 641a str r2, [r3, #64] @ 0x40 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_BUSY_INTERNAL); /* Set the intermediate state before moving the ADC voltage */ /* regulator to state enable. */ CLEAR_BIT(hadc->Instance->CR, (ADC_CR_ADVREGEN_1 | ADC_CR_ADVREGEN_0)); - 80023a0: 687b ldr r3, [r7, #4] - 80023a2: 681b ldr r3, [r3, #0] - 80023a4: 689a ldr r2, [r3, #8] - 80023a6: 687b ldr r3, [r7, #4] - 80023a8: 681b ldr r3, [r3, #0] - 80023aa: f022 5240 bic.w r2, r2, #805306368 @ 0x30000000 - 80023ae: 609a str r2, [r3, #8] + 800243c: 687b ldr r3, [r7, #4] + 800243e: 681b ldr r3, [r3, #0] + 8002440: 689a ldr r2, [r3, #8] + 8002442: 687b ldr r3, [r7, #4] + 8002444: 681b ldr r3, [r3, #0] + 8002446: f022 5240 bic.w r2, r2, #805306368 @ 0x30000000 + 800244a: 609a str r2, [r3, #8] /* Set ADVREGEN bits to 0x01U */ SET_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN_0); - 80023b0: 687b ldr r3, [r7, #4] - 80023b2: 681b ldr r3, [r3, #0] - 80023b4: 689a ldr r2, [r3, #8] - 80023b6: 687b ldr r3, [r7, #4] - 80023b8: 681b ldr r3, [r3, #0] - 80023ba: f042 5280 orr.w r2, r2, #268435456 @ 0x10000000 - 80023be: 609a str r2, [r3, #8] + 800244c: 687b ldr r3, [r7, #4] + 800244e: 681b ldr r3, [r3, #0] + 8002450: 689a ldr r2, [r3, #8] + 8002452: 687b ldr r3, [r7, #4] + 8002454: 681b ldr r3, [r3, #0] + 8002456: f042 5280 orr.w r2, r2, #268435456 @ 0x10000000 + 800245a: 609a str r2, [r3, #8] /* Delay for ADC stabilization time. */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); - 80023c0: 4b94 ldr r3, [pc, #592] @ (8002614 ) - 80023c2: 681b ldr r3, [r3, #0] - 80023c4: 4a94 ldr r2, [pc, #592] @ (8002618 ) - 80023c6: fba2 2303 umull r2, r3, r2, r3 - 80023ca: 0c9a lsrs r2, r3, #18 - 80023cc: 4613 mov r3, r2 - 80023ce: 009b lsls r3, r3, #2 - 80023d0: 4413 add r3, r2 - 80023d2: 005b lsls r3, r3, #1 - 80023d4: 60bb str r3, [r7, #8] + 800245c: 4b94 ldr r3, [pc, #592] @ (80026b0 ) + 800245e: 681b ldr r3, [r3, #0] + 8002460: 4a94 ldr r2, [pc, #592] @ (80026b4 ) + 8002462: fba2 2303 umull r2, r3, r2, r3 + 8002466: 0c9a lsrs r2, r3, #18 + 8002468: 4613 mov r3, r2 + 800246a: 009b lsls r3, r3, #2 + 800246c: 4413 add r3, r2 + 800246e: 005b lsls r3, r3, #1 + 8002470: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) - 80023d6: e002 b.n 80023de + 8002472: e002 b.n 800247a { wait_loop_index--; - 80023d8: 68bb ldr r3, [r7, #8] - 80023da: 3b01 subs r3, #1 - 80023dc: 60bb str r3, [r7, #8] + 8002474: 68bb ldr r3, [r7, #8] + 8002476: 3b01 subs r3, #1 + 8002478: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) - 80023de: 68bb ldr r3, [r7, #8] - 80023e0: 2b00 cmp r3, #0 - 80023e2: d1f9 bne.n 80023d8 + 800247a: 68bb ldr r3, [r7, #8] + 800247c: 2b00 cmp r3, #0 + 800247e: d1f9 bne.n 8002474 } /* Verification that ADC voltage regulator is correctly enabled, whether */ /* or not ADC is coming from state reset (if any potential problem of */ /* clocking, voltage regulator would not be enabled). */ if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN_0) || - 80023e4: 687b ldr r3, [r7, #4] - 80023e6: 681b ldr r3, [r3, #0] - 80023e8: 689b ldr r3, [r3, #8] - 80023ea: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 - 80023ee: 2b00 cmp r3, #0 - 80023f0: d007 beq.n 8002402 + 8002480: 687b ldr r3, [r7, #4] + 8002482: 681b ldr r3, [r3, #0] + 8002484: 689b ldr r3, [r3, #8] + 8002486: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 800248a: 2b00 cmp r3, #0 + 800248c: d007 beq.n 800249e HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADVREGEN_1) ) - 80023f2: 687b ldr r3, [r7, #4] - 80023f4: 681b ldr r3, [r3, #0] - 80023f6: 689b ldr r3, [r3, #8] - 80023f8: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 + 800248e: 687b ldr r3, [r7, #4] + 8002490: 681b ldr r3, [r3, #0] + 8002492: 689b ldr r3, [r3, #8] + 8002494: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN_0) || - 80023fc: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 - 8002400: d110 bne.n 8002424 + 8002498: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 + 800249c: d110 bne.n 80024c0 { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, - 8002402: 687b ldr r3, [r7, #4] - 8002404: 6c1b ldr r3, [r3, #64] @ 0x40 - 8002406: f023 0312 bic.w r3, r3, #18 - 800240a: f043 0210 orr.w r2, r3, #16 - 800240e: 687b ldr r3, [r7, #4] - 8002410: 641a str r2, [r3, #64] @ 0x40 + 800249e: 687b ldr r3, [r7, #4] + 80024a0: 6c1b ldr r3, [r3, #64] @ 0x40 + 80024a2: f023 0312 bic.w r3, r3, #18 + 80024a6: f043 0210 orr.w r2, r3, #16 + 80024aa: 687b ldr r3, [r7, #4] + 80024ac: 641a str r2, [r3, #64] @ 0x40 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - 8002412: 687b ldr r3, [r7, #4] - 8002414: 6c5b ldr r3, [r3, #68] @ 0x44 - 8002416: f043 0201 orr.w r2, r3, #1 - 800241a: 687b ldr r3, [r7, #4] - 800241c: 645a str r2, [r3, #68] @ 0x44 + 80024ae: 687b ldr r3, [r7, #4] + 80024b0: 6c5b ldr r3, [r3, #68] @ 0x44 + 80024b2: f043 0201 orr.w r2, r3, #1 + 80024b6: 687b ldr r3, [r7, #4] + 80024b8: 645a str r2, [r3, #68] @ 0x44 tmp_hal_status = HAL_ERROR; - 800241e: 2301 movs r3, #1 - 8002420: f887 3067 strb.w r3, [r7, #103] @ 0x67 + 80024ba: 2301 movs r3, #1 + 80024bc: f887 3067 strb.w r3, [r7, #103] @ 0x67 /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed and if there is no conversion on going on regular */ /* group (ADC may already be enabled at this point if HAL_ADC_Init() is */ /* called to update a parameter on the fly). */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && - 8002424: 687b ldr r3, [r7, #4] - 8002426: 6c1b ldr r3, [r3, #64] @ 0x40 - 8002428: f003 0310 and.w r3, r3, #16 - 800242c: 2b00 cmp r3, #0 - 800242e: f040 80df bne.w 80025f0 - 8002432: f897 3067 ldrb.w r3, [r7, #103] @ 0x67 - 8002436: 2b00 cmp r3, #0 - 8002438: f040 80da bne.w 80025f0 + 80024c0: 687b ldr r3, [r7, #4] + 80024c2: 6c1b ldr r3, [r3, #64] @ 0x40 + 80024c4: f003 0310 and.w r3, r3, #16 + 80024c8: 2b00 cmp r3, #0 + 80024ca: f040 80df bne.w 800268c + 80024ce: f897 3067 ldrb.w r3, [r7, #103] @ 0x67 + 80024d2: 2b00 cmp r3, #0 + 80024d4: f040 80da bne.w 800268c (tmp_hal_status == HAL_OK) && (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) ) - 800243c: 687b ldr r3, [r7, #4] - 800243e: 681b ldr r3, [r3, #0] - 8002440: 689b ldr r3, [r3, #8] - 8002442: f003 0304 and.w r3, r3, #4 + 80024d8: 687b ldr r3, [r7, #4] + 80024da: 681b ldr r3, [r3, #0] + 80024dc: 689b ldr r3, [r3, #8] + 80024de: f003 0304 and.w r3, r3, #4 (tmp_hal_status == HAL_OK) && - 8002446: 2b00 cmp r3, #0 - 8002448: f040 80d2 bne.w 80025f0 + 80024e2: 2b00 cmp r3, #0 + 80024e4: f040 80d2 bne.w 800268c { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, - 800244c: 687b ldr r3, [r7, #4] - 800244e: 6c1b ldr r3, [r3, #64] @ 0x40 - 8002450: f423 7381 bic.w r3, r3, #258 @ 0x102 - 8002454: f043 0202 orr.w r2, r3, #2 - 8002458: 687b ldr r3, [r7, #4] - 800245a: 641a str r2, [r3, #64] @ 0x40 + 80024e8: 687b ldr r3, [r7, #4] + 80024ea: 6c1b ldr r3, [r3, #64] @ 0x40 + 80024ec: f423 7381 bic.w r3, r3, #258 @ 0x102 + 80024f0: f043 0202 orr.w r2, r3, #2 + 80024f4: 687b ldr r3, [r7, #4] + 80024f6: 641a str r2, [r3, #64] @ 0x40 /* Configuration of common ADC parameters */ /* Pointer to the common control register to which is belonging hadc */ /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */ /* control registers) */ tmpADC_Common = ADC_COMMON_REGISTER(hadc); - 800245c: 4b6f ldr r3, [pc, #444] @ (800261c ) - 800245e: 65fb str r3, [r7, #92] @ 0x5c + 80024f8: 4b6f ldr r3, [pc, #444] @ (80026b8 ) + 80024fa: 65fb str r3, [r7, #92] @ 0x5c /* Set handle of the other ADC sharing the same common register */ ADC_COMMON_ADC_OTHER(hadc, &tmphadcSharingSameCommonRegister); - 8002460: 687b ldr r3, [r7, #4] - 8002462: 681b ldr r3, [r3, #0] - 8002464: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 - 8002468: d102 bne.n 8002470 - 800246a: 4b6d ldr r3, [pc, #436] @ (8002620 ) - 800246c: 60fb str r3, [r7, #12] - 800246e: e002 b.n 8002476 - 8002470: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 - 8002474: 60fb str r3, [r7, #12] + 80024fc: 687b ldr r3, [r7, #4] + 80024fe: 681b ldr r3, [r3, #0] + 8002500: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 + 8002504: d102 bne.n 800250c + 8002506: 4b6d ldr r3, [pc, #436] @ (80026bc ) + 8002508: 60fb str r3, [r7, #12] + 800250a: e002 b.n 8002512 + 800250c: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 + 8002510: 60fb str r3, [r7, #12] /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - Multimode clock configuration */ if ((ADC_IS_ENABLE(hadc) == RESET) && - 8002476: 687b ldr r3, [r7, #4] - 8002478: 681b ldr r3, [r3, #0] - 800247a: 689b ldr r3, [r3, #8] - 800247c: f003 0303 and.w r3, r3, #3 - 8002480: 2b01 cmp r3, #1 - 8002482: d108 bne.n 8002496 - 8002484: 687b ldr r3, [r7, #4] - 8002486: 681b ldr r3, [r3, #0] - 8002488: 681b ldr r3, [r3, #0] - 800248a: f003 0301 and.w r3, r3, #1 - 800248e: 2b01 cmp r3, #1 - 8002490: d101 bne.n 8002496 - 8002492: 2301 movs r3, #1 - 8002494: e000 b.n 8002498 - 8002496: 2300 movs r3, #0 - 8002498: 2b00 cmp r3, #0 - 800249a: d11c bne.n 80024d6 + 8002512: 687b ldr r3, [r7, #4] + 8002514: 681b ldr r3, [r3, #0] + 8002516: 689b ldr r3, [r3, #8] + 8002518: f003 0303 and.w r3, r3, #3 + 800251c: 2b01 cmp r3, #1 + 800251e: d108 bne.n 8002532 + 8002520: 687b ldr r3, [r7, #4] + 8002522: 681b ldr r3, [r3, #0] + 8002524: 681b ldr r3, [r3, #0] + 8002526: f003 0301 and.w r3, r3, #1 + 800252a: 2b01 cmp r3, #1 + 800252c: d101 bne.n 8002532 + 800252e: 2301 movs r3, #1 + 8002530: e000 b.n 8002534 + 8002532: 2300 movs r3, #0 + 8002534: 2b00 cmp r3, #0 + 8002536: d11c bne.n 8002572 ((tmphadcSharingSameCommonRegister.Instance == NULL) || - 800249c: 68fb ldr r3, [r7, #12] + 8002538: 68fb ldr r3, [r7, #12] if ((ADC_IS_ENABLE(hadc) == RESET) && - 800249e: 2b00 cmp r3, #0 - 80024a0: d010 beq.n 80024c4 + 800253a: 2b00 cmp r3, #0 + 800253c: d010 beq.n 8002560 (ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) ) ) - 80024a2: 68fb ldr r3, [r7, #12] - 80024a4: 689b ldr r3, [r3, #8] - 80024a6: f003 0303 and.w r3, r3, #3 - 80024aa: 2b01 cmp r3, #1 - 80024ac: d107 bne.n 80024be - 80024ae: 68fb ldr r3, [r7, #12] - 80024b0: 681b ldr r3, [r3, #0] - 80024b2: f003 0301 and.w r3, r3, #1 - 80024b6: 2b01 cmp r3, #1 - 80024b8: d101 bne.n 80024be - 80024ba: 2301 movs r3, #1 - 80024bc: e000 b.n 80024c0 - 80024be: 2300 movs r3, #0 + 800253e: 68fb ldr r3, [r7, #12] + 8002540: 689b ldr r3, [r3, #8] + 8002542: f003 0303 and.w r3, r3, #3 + 8002546: 2b01 cmp r3, #1 + 8002548: d107 bne.n 800255a + 800254a: 68fb ldr r3, [r7, #12] + 800254c: 681b ldr r3, [r3, #0] + 800254e: f003 0301 and.w r3, r3, #1 + 8002552: 2b01 cmp r3, #1 + 8002554: d101 bne.n 800255a + 8002556: 2301 movs r3, #1 + 8002558: e000 b.n 800255c + 800255a: 2300 movs r3, #0 ((tmphadcSharingSameCommonRegister.Instance == NULL) || - 80024c0: 2b00 cmp r3, #0 - 80024c2: d108 bne.n 80024d6 + 800255c: 2b00 cmp r3, #0 + 800255e: d108 bne.n 8002572 /* into HAL_ADCEx_MultiModeConfigChannel() ) */ /* - internal measurement paths: Vbat, temperature sensor, Vref */ /* (set into HAL_ADC_ConfigChannel() or */ /* HAL_ADCEx_InjectedConfigChannel() ) */ MODIFY_REG(tmpADC_Common->CCR , - 80024c4: 6dfb ldr r3, [r7, #92] @ 0x5c - 80024c6: 689b ldr r3, [r3, #8] - 80024c8: f423 3240 bic.w r2, r3, #196608 @ 0x30000 - 80024cc: 687b ldr r3, [r7, #4] - 80024ce: 685b ldr r3, [r3, #4] - 80024d0: 431a orrs r2, r3 - 80024d2: 6dfb ldr r3, [r7, #92] @ 0x5c - 80024d4: 609a str r2, [r3, #8] + 8002560: 6dfb ldr r3, [r7, #92] @ 0x5c + 8002562: 689b ldr r3, [r3, #8] + 8002564: f423 3240 bic.w r2, r3, #196608 @ 0x30000 + 8002568: 687b ldr r3, [r7, #4] + 800256a: 685b ldr r3, [r3, #4] + 800256c: 431a orrs r2, r3 + 800256e: 6dfb ldr r3, [r7, #92] @ 0x5c + 8002570: 609a str r2, [r3, #8] /* - external trigger to start conversion */ /* - external trigger polarity */ /* - continuous conversion mode */ /* - overrun */ /* - discontinuous mode */ SET_BIT(tmpCFGR, ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | - 80024d6: 687b ldr r3, [r7, #4] - 80024d8: 7e5b ldrb r3, [r3, #25] - 80024da: 035b lsls r3, r3, #13 - 80024dc: 687a ldr r2, [r7, #4] - 80024de: 6b52 ldr r2, [r2, #52] @ 0x34 - 80024e0: 2a01 cmp r2, #1 - 80024e2: d002 beq.n 80024ea - 80024e4: f44f 5280 mov.w r2, #4096 @ 0x1000 - 80024e8: e000 b.n 80024ec - 80024ea: 2200 movs r2, #0 - 80024ec: 431a orrs r2, r3 - 80024ee: 687b ldr r3, [r7, #4] - 80024f0: 68db ldr r3, [r3, #12] - 80024f2: 431a orrs r2, r3 - 80024f4: 687b ldr r3, [r7, #4] - 80024f6: 689b ldr r3, [r3, #8] - 80024f8: 4313 orrs r3, r2 - 80024fa: 6e3a ldr r2, [r7, #96] @ 0x60 - 80024fc: 4313 orrs r3, r2 - 80024fe: 663b str r3, [r7, #96] @ 0x60 + 8002572: 687b ldr r3, [r7, #4] + 8002574: 7e5b ldrb r3, [r3, #25] + 8002576: 035b lsls r3, r3, #13 + 8002578: 687a ldr r2, [r7, #4] + 800257a: 6b52 ldr r2, [r2, #52] @ 0x34 + 800257c: 2a01 cmp r2, #1 + 800257e: d002 beq.n 8002586 + 8002580: f44f 5280 mov.w r2, #4096 @ 0x1000 + 8002584: e000 b.n 8002588 + 8002586: 2200 movs r2, #0 + 8002588: 431a orrs r2, r3 + 800258a: 687b ldr r3, [r7, #4] + 800258c: 68db ldr r3, [r3, #12] + 800258e: 431a orrs r2, r3 + 8002590: 687b ldr r3, [r7, #4] + 8002592: 689b ldr r3, [r3, #8] + 8002594: 4313 orrs r3, r2 + 8002596: 6e3a ldr r2, [r7, #96] @ 0x60 + 8002598: 4313 orrs r3, r2 + 800259a: 663b str r3, [r7, #96] @ 0x60 ADC_CFGR_OVERRUN(hadc->Init.Overrun) | hadc->Init.DataAlign | hadc->Init.Resolution ); /* Enable discontinuous mode only if continuous mode is disabled */ if (hadc->Init.DiscontinuousConvMode == ENABLE) - 8002500: 687b ldr r3, [r7, #4] - 8002502: f893 3020 ldrb.w r3, [r3, #32] - 8002506: 2b01 cmp r3, #1 - 8002508: d11b bne.n 8002542 + 800259c: 687b ldr r3, [r7, #4] + 800259e: f893 3020 ldrb.w r3, [r3, #32] + 80025a2: 2b01 cmp r3, #1 + 80025a4: d11b bne.n 80025de { if (hadc->Init.ContinuousConvMode == DISABLE) - 800250a: 687b ldr r3, [r7, #4] - 800250c: 7e5b ldrb r3, [r3, #25] - 800250e: 2b00 cmp r3, #0 - 8002510: d109 bne.n 8002526 + 80025a6: 687b ldr r3, [r7, #4] + 80025a8: 7e5b ldrb r3, [r3, #25] + 80025aa: 2b00 cmp r3, #0 + 80025ac: d109 bne.n 80025c2 { /* Enable the selected ADC regular discontinuous mode */ /* Set the number of channels to be converted in discontinuous mode */ SET_BIT(tmpCFGR, ADC_CFGR_DISCEN | - 8002512: 687b ldr r3, [r7, #4] - 8002514: 6a5b ldr r3, [r3, #36] @ 0x24 - 8002516: 3b01 subs r3, #1 - 8002518: 045a lsls r2, r3, #17 - 800251a: 6e3b ldr r3, [r7, #96] @ 0x60 - 800251c: 4313 orrs r3, r2 - 800251e: f443 3380 orr.w r3, r3, #65536 @ 0x10000 - 8002522: 663b str r3, [r7, #96] @ 0x60 - 8002524: e00d b.n 8002542 + 80025ae: 687b ldr r3, [r7, #4] + 80025b0: 6a5b ldr r3, [r3, #36] @ 0x24 + 80025b2: 3b01 subs r3, #1 + 80025b4: 045a lsls r2, r3, #17 + 80025b6: 6e3b ldr r3, [r7, #96] @ 0x60 + 80025b8: 4313 orrs r3, r2 + 80025ba: f443 3380 orr.w r3, r3, #65536 @ 0x10000 + 80025be: 663b str r3, [r7, #96] @ 0x60 + 80025c0: e00d b.n 80025de /* ADC regular group discontinuous was intended to be enabled, */ /* but ADC regular group modes continuous and sequencer discontinuous */ /* cannot be enabled simultaneously. */ /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, - 8002526: 687b ldr r3, [r7, #4] - 8002528: 6c1b ldr r3, [r3, #64] @ 0x40 - 800252a: f023 0322 bic.w r3, r3, #34 @ 0x22 - 800252e: f043 0220 orr.w r2, r3, #32 - 8002532: 687b ldr r3, [r7, #4] - 8002534: 641a str r2, [r3, #64] @ 0x40 + 80025c2: 687b ldr r3, [r7, #4] + 80025c4: 6c1b ldr r3, [r3, #64] @ 0x40 + 80025c6: f023 0322 bic.w r3, r3, #34 @ 0x22 + 80025ca: f043 0220 orr.w r2, r3, #32 + 80025ce: 687b ldr r3, [r7, #4] + 80025d0: 641a str r2, [r3, #64] @ 0x40 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_CONFIG); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - 8002536: 687b ldr r3, [r7, #4] - 8002538: 6c5b ldr r3, [r3, #68] @ 0x44 - 800253a: f043 0201 orr.w r2, r3, #1 - 800253e: 687b ldr r3, [r7, #4] - 8002540: 645a str r2, [r3, #68] @ 0x44 + 80025d2: 687b ldr r3, [r7, #4] + 80025d4: 6c5b ldr r3, [r3, #68] @ 0x44 + 80025d6: f043 0201 orr.w r2, r3, #1 + 80025da: 687b ldr r3, [r7, #4] + 80025dc: 645a str r2, [r3, #68] @ 0x44 /* Enable external trigger if trigger selection is different of software */ /* start. */ /* Note: This configuration keeps the hardware feature of parameter */ /* ExternalTrigConvEdge "trigger edge none" equivalent to */ /* software start. */ if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) - 8002542: 687b ldr r3, [r7, #4] - 8002544: 6a9b ldr r3, [r3, #40] @ 0x28 - 8002546: 2b01 cmp r3, #1 - 8002548: d007 beq.n 800255a + 80025de: 687b ldr r3, [r7, #4] + 80025e0: 6a9b ldr r3, [r3, #40] @ 0x28 + 80025e2: 2b01 cmp r3, #1 + 80025e4: d007 beq.n 80025f6 { SET_BIT(tmpCFGR, ADC_CFGR_EXTSEL_SET(hadc, hadc->Init.ExternalTrigConv) | - 800254a: 687b ldr r3, [r7, #4] - 800254c: 6a9a ldr r2, [r3, #40] @ 0x28 - 800254e: 687b ldr r3, [r7, #4] - 8002550: 6adb ldr r3, [r3, #44] @ 0x2c - 8002552: 4313 orrs r3, r2 - 8002554: 6e3a ldr r2, [r7, #96] @ 0x60 - 8002556: 4313 orrs r3, r2 - 8002558: 663b str r3, [r7, #96] @ 0x60 + 80025e6: 687b ldr r3, [r7, #4] + 80025e8: 6a9a ldr r2, [r3, #40] @ 0x28 + 80025ea: 687b ldr r3, [r7, #4] + 80025ec: 6adb ldr r3, [r3, #44] @ 0x2c + 80025ee: 4313 orrs r3, r2 + 80025f0: 6e3a ldr r2, [r7, #96] @ 0x60 + 80025f2: 4313 orrs r3, r2 + 80025f4: 663b str r3, [r7, #96] @ 0x60 /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular and injected groups: */ /* - DMA continuous request */ /* - LowPowerAutoWait feature */ if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) - 800255a: 687b ldr r3, [r7, #4] - 800255c: 681b ldr r3, [r3, #0] - 800255e: 689b ldr r3, [r3, #8] - 8002560: f003 030c and.w r3, r3, #12 - 8002564: 2b00 cmp r3, #0 - 8002566: d114 bne.n 8002592 + 80025f6: 687b ldr r3, [r7, #4] + 80025f8: 681b ldr r3, [r3, #0] + 80025fa: 689b ldr r3, [r3, #8] + 80025fc: f003 030c and.w r3, r3, #12 + 8002600: 2b00 cmp r3, #0 + 8002602: d114 bne.n 800262e { CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_AUTDLY | - 8002568: 687b ldr r3, [r7, #4] - 800256a: 681b ldr r3, [r3, #0] - 800256c: 68db ldr r3, [r3, #12] - 800256e: 687a ldr r2, [r7, #4] - 8002570: 6812 ldr r2, [r2, #0] - 8002572: f423 4380 bic.w r3, r3, #16384 @ 0x4000 - 8002576: f023 0302 bic.w r3, r3, #2 - 800257a: 60d3 str r3, [r2, #12] + 8002604: 687b ldr r3, [r7, #4] + 8002606: 681b ldr r3, [r3, #0] + 8002608: 68db ldr r3, [r3, #12] + 800260a: 687a ldr r2, [r7, #4] + 800260c: 6812 ldr r2, [r2, #0] + 800260e: f423 4380 bic.w r3, r3, #16384 @ 0x4000 + 8002612: f023 0302 bic.w r3, r3, #2 + 8002616: 60d3 str r3, [r2, #12] ADC_CFGR_DMACFG ); SET_BIT(tmpCFGR, ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | - 800257c: 687b ldr r3, [r7, #4] - 800257e: 7e1b ldrb r3, [r3, #24] - 8002580: 039a lsls r2, r3, #14 - 8002582: 687b ldr r3, [r7, #4] - 8002584: f893 3030 ldrb.w r3, [r3, #48] @ 0x30 - 8002588: 005b lsls r3, r3, #1 - 800258a: 4313 orrs r3, r2 - 800258c: 6e3a ldr r2, [r7, #96] @ 0x60 - 800258e: 4313 orrs r3, r2 - 8002590: 663b str r3, [r7, #96] @ 0x60 + 8002618: 687b ldr r3, [r7, #4] + 800261a: 7e1b ldrb r3, [r3, #24] + 800261c: 039a lsls r2, r3, #14 + 800261e: 687b ldr r3, [r7, #4] + 8002620: f893 3030 ldrb.w r3, [r3, #48] @ 0x30 + 8002624: 005b lsls r3, r3, #1 + 8002626: 4313 orrs r3, r2 + 8002628: 6e3a ldr r2, [r7, #96] @ 0x60 + 800262a: 4313 orrs r3, r2 + 800262c: 663b str r3, [r7, #96] @ 0x60 ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests) ); } /* Update ADC configuration register with previous settings */ MODIFY_REG(hadc->Instance->CFGR, - 8002592: 687b ldr r3, [r7, #4] - 8002594: 681b ldr r3, [r3, #0] - 8002596: 68da ldr r2, [r3, #12] - 8002598: 4b22 ldr r3, [pc, #136] @ (8002624 ) - 800259a: 4013 ands r3, r2 - 800259c: 687a ldr r2, [r7, #4] - 800259e: 6812 ldr r2, [r2, #0] - 80025a0: 6e39 ldr r1, [r7, #96] @ 0x60 - 80025a2: 430b orrs r3, r1 - 80025a4: 60d3 str r3, [r2, #12] + 800262e: 687b ldr r3, [r7, #4] + 8002630: 681b ldr r3, [r3, #0] + 8002632: 68da ldr r2, [r3, #12] + 8002634: 4b22 ldr r3, [pc, #136] @ (80026c0 ) + 8002636: 4013 ands r3, r2 + 8002638: 687a ldr r2, [r7, #4] + 800263a: 6812 ldr r2, [r2, #0] + 800263c: 6e39 ldr r1, [r7, #96] @ 0x60 + 800263e: 430b orrs r3, r1 + 8002640: 60d3 str r3, [r2, #12] /* Parameter "NbrOfConversion" is discarded. */ /* Note: Scan mode is not present by hardware on this device, but */ /* emulated by software for alignment over all STM32 devices. */ /* - if scan mode is enabled, regular channels sequence length is set to */ /* parameter "NbrOfConversion" */ if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE) - 80025a6: 687b ldr r3, [r7, #4] - 80025a8: 691b ldr r3, [r3, #16] - 80025aa: 2b01 cmp r3, #1 - 80025ac: d10c bne.n 80025c8 + 8002642: 687b ldr r3, [r7, #4] + 8002644: 691b ldr r3, [r3, #16] + 8002646: 2b01 cmp r3, #1 + 8002648: d10c bne.n 8002664 { /* Set number of ranks in regular group sequencer */ MODIFY_REG(hadc->Instance->SQR1 , - 80025ae: 687b ldr r3, [r7, #4] - 80025b0: 681b ldr r3, [r3, #0] - 80025b2: 6b1b ldr r3, [r3, #48] @ 0x30 - 80025b4: f023 010f bic.w r1, r3, #15 - 80025b8: 687b ldr r3, [r7, #4] - 80025ba: 69db ldr r3, [r3, #28] - 80025bc: 1e5a subs r2, r3, #1 - 80025be: 687b ldr r3, [r7, #4] - 80025c0: 681b ldr r3, [r3, #0] - 80025c2: 430a orrs r2, r1 - 80025c4: 631a str r2, [r3, #48] @ 0x30 - 80025c6: e007 b.n 80025d8 + 800264a: 687b ldr r3, [r7, #4] + 800264c: 681b ldr r3, [r3, #0] + 800264e: 6b1b ldr r3, [r3, #48] @ 0x30 + 8002650: f023 010f bic.w r1, r3, #15 + 8002654: 687b ldr r3, [r7, #4] + 8002656: 69db ldr r3, [r3, #28] + 8002658: 1e5a subs r2, r3, #1 + 800265a: 687b ldr r3, [r7, #4] + 800265c: 681b ldr r3, [r3, #0] + 800265e: 430a orrs r2, r1 + 8002660: 631a str r2, [r3, #48] @ 0x30 + 8002662: e007 b.n 8002674 ADC_SQR1_L , (hadc->Init.NbrOfConversion - (uint8_t)1U) ); } else { CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L); - 80025c8: 687b ldr r3, [r7, #4] - 80025ca: 681b ldr r3, [r3, #0] - 80025cc: 6b1a ldr r2, [r3, #48] @ 0x30 - 80025ce: 687b ldr r3, [r7, #4] - 80025d0: 681b ldr r3, [r3, #0] - 80025d2: f022 020f bic.w r2, r2, #15 - 80025d6: 631a str r2, [r3, #48] @ 0x30 + 8002664: 687b ldr r3, [r7, #4] + 8002666: 681b ldr r3, [r3, #0] + 8002668: 6b1a ldr r2, [r3, #48] @ 0x30 + 800266a: 687b ldr r3, [r7, #4] + 800266c: 681b ldr r3, [r3, #0] + 800266e: f022 020f bic.w r2, r2, #15 + 8002672: 631a str r2, [r3, #48] @ 0x30 } /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); - 80025d8: 687b ldr r3, [r7, #4] - 80025da: 2200 movs r2, #0 - 80025dc: 645a str r2, [r3, #68] @ 0x44 + 8002674: 687b ldr r3, [r7, #4] + 8002676: 2200 movs r2, #0 + 8002678: 645a str r2, [r3, #68] @ 0x44 /* Set the ADC state */ ADC_STATE_CLR_SET(hadc->State, - 80025de: 687b ldr r3, [r7, #4] - 80025e0: 6c1b ldr r3, [r3, #64] @ 0x40 - 80025e2: f023 0303 bic.w r3, r3, #3 - 80025e6: f043 0201 orr.w r2, r3, #1 - 80025ea: 687b ldr r3, [r7, #4] - 80025ec: 641a str r2, [r3, #64] @ 0x40 - 80025ee: e00a b.n 8002606 + 800267a: 687b ldr r3, [r7, #4] + 800267c: 6c1b ldr r3, [r3, #64] @ 0x40 + 800267e: f023 0303 bic.w r3, r3, #3 + 8002682: f043 0201 orr.w r2, r3, #1 + 8002686: 687b ldr r3, [r7, #4] + 8002688: 641a str r2, [r3, #64] @ 0x40 + 800268a: e00a b.n 80026a2 HAL_ADC_STATE_READY); } else { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, - 80025f0: 687b ldr r3, [r7, #4] - 80025f2: 6c1b ldr r3, [r3, #64] @ 0x40 - 80025f4: f023 0312 bic.w r3, r3, #18 - 80025f8: f043 0210 orr.w r2, r3, #16 - 80025fc: 687b ldr r3, [r7, #4] - 80025fe: 641a str r2, [r3, #64] @ 0x40 + 800268c: 687b ldr r3, [r7, #4] + 800268e: 6c1b ldr r3, [r3, #64] @ 0x40 + 8002690: f023 0312 bic.w r3, r3, #18 + 8002694: f043 0210 orr.w r2, r3, #16 + 8002698: 687b ldr r3, [r7, #4] + 800269a: 641a str r2, [r3, #64] @ 0x40 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); tmp_hal_status = HAL_ERROR; - 8002600: 2301 movs r3, #1 - 8002602: f887 3067 strb.w r3, [r7, #103] @ 0x67 + 800269c: 2301 movs r3, #1 + 800269e: f887 3067 strb.w r3, [r7, #103] @ 0x67 } /* Return function status */ return tmp_hal_status; - 8002606: f897 3067 ldrb.w r3, [r7, #103] @ 0x67 + 80026a2: f897 3067 ldrb.w r3, [r7, #103] @ 0x67 } - 800260a: 4618 mov r0, r3 - 800260c: 3768 adds r7, #104 @ 0x68 - 800260e: 46bd mov sp, r7 - 8002610: bd80 pop {r7, pc} - 8002612: bf00 nop - 8002614: 20000000 .word 0x20000000 - 8002618: 431bde83 .word 0x431bde83 - 800261c: 50000300 .word 0x50000300 - 8002620: 50000100 .word 0x50000100 - 8002624: fff0c007 .word 0xfff0c007 + 80026a6: 4618 mov r0, r3 + 80026a8: 3768 adds r7, #104 @ 0x68 + 80026aa: 46bd mov sp, r7 + 80026ac: bd80 pop {r7, pc} + 80026ae: bf00 nop + 80026b0: 20000000 .word 0x20000000 + 80026b4: 431bde83 .word 0x431bde83 + 80026b8: 50000300 .word 0x50000300 + 80026bc: 50000100 .word 0x50000100 + 80026c0: fff0c007 .word 0xfff0c007 -08002628 : +080026c4 : * @param pData The destination Buffer address. * @param Length The length of data to be transferred from ADC peripheral to memory. * @retval None */ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) { - 8002628: b580 push {r7, lr} - 800262a: b086 sub sp, #24 - 800262c: af00 add r7, sp, #0 - 800262e: 60f8 str r0, [r7, #12] - 8002630: 60b9 str r1, [r7, #8] - 8002632: 607a str r2, [r7, #4] + 80026c4: b580 push {r7, lr} + 80026c6: b086 sub sp, #24 + 80026c8: af00 add r7, sp, #0 + 80026ca: 60f8 str r0, [r7, #12] + 80026cc: 60b9 str r1, [r7, #8] + 80026ce: 607a str r2, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; - 8002634: 2300 movs r3, #0 - 8002636: 75fb strb r3, [r7, #23] + 80026d0: 2300 movs r3, #0 + 80026d2: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Perform ADC enable and conversion start if no conversion is on going */ if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) - 8002638: 68fb ldr r3, [r7, #12] - 800263a: 681b ldr r3, [r3, #0] - 800263c: 689b ldr r3, [r3, #8] - 800263e: f003 0304 and.w r3, r3, #4 - 8002642: 2b00 cmp r3, #0 - 8002644: f040 80b9 bne.w 80027ba + 80026d4: 68fb ldr r3, [r7, #12] + 80026d6: 681b ldr r3, [r3, #0] + 80026d8: 689b ldr r3, [r3, #8] + 80026da: f003 0304 and.w r3, r3, #4 + 80026de: 2b00 cmp r3, #0 + 80026e0: f040 80b9 bne.w 8002856 { /* Process locked */ __HAL_LOCK(hadc); - 8002648: 68fb ldr r3, [r7, #12] - 800264a: f893 303c ldrb.w r3, [r3, #60] @ 0x3c - 800264e: 2b01 cmp r3, #1 - 8002650: d101 bne.n 8002656 - 8002652: 2302 movs r3, #2 - 8002654: e0b4 b.n 80027c0 - 8002656: 68fb ldr r3, [r7, #12] - 8002658: 2201 movs r2, #1 - 800265a: f883 203c strb.w r2, [r3, #60] @ 0x3c + 80026e4: 68fb ldr r3, [r7, #12] + 80026e6: f893 303c ldrb.w r3, [r3, #60] @ 0x3c + 80026ea: 2b01 cmp r3, #1 + 80026ec: d101 bne.n 80026f2 + 80026ee: 2302 movs r3, #2 + 80026f0: e0b4 b.n 800285c + 80026f2: 68fb ldr r3, [r7, #12] + 80026f4: 2201 movs r2, #1 + 80026f6: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Verification if multimode is disabled (for devices with several ADC) */ /* If multimode is enabled, dedicated function multimode conversion */ /* start DMA must be used. */ if(ADC_COMMON_CCR_MULTI(hadc) == RESET) - 800265e: 4b5a ldr r3, [pc, #360] @ (80027c8 ) - 8002660: 689b ldr r3, [r3, #8] - 8002662: f003 031f and.w r3, r3, #31 - 8002666: 2b00 cmp r3, #0 - 8002668: f040 80a0 bne.w 80027ac + 80026fa: 4b5a ldr r3, [pc, #360] @ (8002864 ) + 80026fc: 689b ldr r3, [r3, #8] + 80026fe: f003 031f and.w r3, r3, #31 + 8002702: 2b00 cmp r3, #0 + 8002704: f040 80a0 bne.w 8002848 { /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); - 800266c: 68f8 ldr r0, [r7, #12] - 800266e: f000 fec1 bl 80033f4 - 8002672: 4603 mov r3, r0 - 8002674: 75fb strb r3, [r7, #23] + 8002708: 68f8 ldr r0, [r7, #12] + 800270a: f000 fec1 bl 8003490 + 800270e: 4603 mov r3, r0 + 8002710: 75fb strb r3, [r7, #23] /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) - 8002676: 7dfb ldrb r3, [r7, #23] - 8002678: 2b00 cmp r3, #0 - 800267a: f040 8092 bne.w 80027a2 + 8002712: 7dfb ldrb r3, [r7, #23] + 8002714: 2b00 cmp r3, #0 + 8002716: f040 8092 bne.w 800283e { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ /* - Set state bitfield related to regular operation */ ADC_STATE_CLR_SET(hadc->State, - 800267e: 68fb ldr r3, [r7, #12] - 8002680: 6c1b ldr r3, [r3, #64] @ 0x40 - 8002682: f423 6370 bic.w r3, r3, #3840 @ 0xf00 - 8002686: f023 0301 bic.w r3, r3, #1 - 800268a: f443 7280 orr.w r2, r3, #256 @ 0x100 - 800268e: 68fb ldr r3, [r7, #12] - 8002690: 641a str r2, [r3, #64] @ 0x40 + 800271a: 68fb ldr r3, [r7, #12] + 800271c: 6c1b ldr r3, [r3, #64] @ 0x40 + 800271e: f423 6370 bic.w r3, r3, #3840 @ 0xf00 + 8002722: f023 0301 bic.w r3, r3, #1 + 8002726: f443 7280 orr.w r2, r3, #256 @ 0x100 + 800272a: 68fb ldr r3, [r7, #12] + 800272c: 641a str r2, [r3, #64] @ 0x40 HAL_ADC_STATE_REG_BUSY); /* Set group injected state (from auto-injection) and multimode state */ /* for all cases of multimode: independent mode, multimode ADC master */ /* or multimode ADC slave (for devices with several ADCs): */ if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) - 8002692: 4b4d ldr r3, [pc, #308] @ (80027c8 ) - 8002694: 689b ldr r3, [r3, #8] - 8002696: f003 031f and.w r3, r3, #31 - 800269a: 2b00 cmp r3, #0 - 800269c: d004 beq.n 80026a8 - 800269e: 68fb ldr r3, [r7, #12] - 80026a0: 681b ldr r3, [r3, #0] - 80026a2: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 - 80026a6: d115 bne.n 80026d4 + 800272e: 4b4d ldr r3, [pc, #308] @ (8002864 ) + 8002730: 689b ldr r3, [r3, #8] + 8002732: f003 031f and.w r3, r3, #31 + 8002736: 2b00 cmp r3, #0 + 8002738: d004 beq.n 8002744 + 800273a: 68fb ldr r3, [r7, #12] + 800273c: 681b ldr r3, [r3, #0] + 800273e: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 + 8002742: d115 bne.n 8002770 { /* Set ADC state (ADC independent or master) */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); - 80026a8: 68fb ldr r3, [r7, #12] - 80026aa: 6c1b ldr r3, [r3, #64] @ 0x40 - 80026ac: f423 1280 bic.w r2, r3, #1048576 @ 0x100000 - 80026b0: 68fb ldr r3, [r7, #12] - 80026b2: 641a str r2, [r3, #64] @ 0x40 + 8002744: 68fb ldr r3, [r7, #12] + 8002746: 6c1b ldr r3, [r3, #64] @ 0x40 + 8002748: f423 1280 bic.w r2, r3, #1048576 @ 0x100000 + 800274c: 68fb ldr r3, [r7, #12] + 800274e: 641a str r2, [r3, #64] @ 0x40 /* If conversions on group regular are also triggering group injected,*/ /* update ADC state. */ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET) - 80026b4: 68fb ldr r3, [r7, #12] - 80026b6: 681b ldr r3, [r3, #0] - 80026b8: 68db ldr r3, [r3, #12] - 80026ba: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 - 80026be: 2b00 cmp r3, #0 - 80026c0: d027 beq.n 8002712 + 8002750: 68fb ldr r3, [r7, #12] + 8002752: 681b ldr r3, [r3, #0] + 8002754: 68db ldr r3, [r3, #12] + 8002756: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 800275a: 2b00 cmp r3, #0 + 800275c: d027 beq.n 80027ae { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); - 80026c2: 68fb ldr r3, [r7, #12] - 80026c4: 6c1b ldr r3, [r3, #64] @ 0x40 - 80026c6: f423 5340 bic.w r3, r3, #12288 @ 0x3000 - 80026ca: f443 5280 orr.w r2, r3, #4096 @ 0x1000 - 80026ce: 68fb ldr r3, [r7, #12] - 80026d0: 641a str r2, [r3, #64] @ 0x40 + 800275e: 68fb ldr r3, [r7, #12] + 8002760: 6c1b ldr r3, [r3, #64] @ 0x40 + 8002762: f423 5340 bic.w r3, r3, #12288 @ 0x3000 + 8002766: f443 5280 orr.w r2, r3, #4096 @ 0x1000 + 800276a: 68fb ldr r3, [r7, #12] + 800276c: 641a str r2, [r3, #64] @ 0x40 if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET) - 80026d2: e01e b.n 8002712 + 800276e: e01e b.n 80027ae } } else { /* Set ADC state (ADC slave) */ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); - 80026d4: 68fb ldr r3, [r7, #12] - 80026d6: 6c1b ldr r3, [r3, #64] @ 0x40 - 80026d8: f443 1280 orr.w r2, r3, #1048576 @ 0x100000 - 80026dc: 68fb ldr r3, [r7, #12] - 80026de: 641a str r2, [r3, #64] @ 0x40 + 8002770: 68fb ldr r3, [r7, #12] + 8002772: 6c1b ldr r3, [r3, #64] @ 0x40 + 8002774: f443 1280 orr.w r2, r3, #1048576 @ 0x100000 + 8002778: 68fb ldr r3, [r7, #12] + 800277a: 641a str r2, [r3, #64] @ 0x40 /* If conversions on group regular are also triggering group injected,*/ /* update ADC state. */ if (ADC_MULTIMODE_AUTO_INJECTED(hadc)) - 80026e0: 68fb ldr r3, [r7, #12] - 80026e2: 681b ldr r3, [r3, #0] - 80026e4: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 - 80026e8: d004 beq.n 80026f4 - 80026ea: 68fb ldr r3, [r7, #12] - 80026ec: 681b ldr r3, [r3, #0] - 80026ee: 4a37 ldr r2, [pc, #220] @ (80027cc ) - 80026f0: 4293 cmp r3, r2 - 80026f2: d10e bne.n 8002712 - 80026f4: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 - 80026f8: 68db ldr r3, [r3, #12] - 80026fa: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 - 80026fe: 2b00 cmp r3, #0 - 8002700: d007 beq.n 8002712 + 800277c: 68fb ldr r3, [r7, #12] + 800277e: 681b ldr r3, [r3, #0] + 8002780: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 + 8002784: d004 beq.n 8002790 + 8002786: 68fb ldr r3, [r7, #12] + 8002788: 681b ldr r3, [r3, #0] + 800278a: 4a37 ldr r2, [pc, #220] @ (8002868 ) + 800278c: 4293 cmp r3, r2 + 800278e: d10e bne.n 80027ae + 8002790: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 + 8002794: 68db ldr r3, [r3, #12] + 8002796: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 800279a: 2b00 cmp r3, #0 + 800279c: d007 beq.n 80027ae { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); - 8002702: 68fb ldr r3, [r7, #12] - 8002704: 6c1b ldr r3, [r3, #64] @ 0x40 - 8002706: f423 5340 bic.w r3, r3, #12288 @ 0x3000 - 800270a: f443 5280 orr.w r2, r3, #4096 @ 0x1000 - 800270e: 68fb ldr r3, [r7, #12] - 8002710: 641a str r2, [r3, #64] @ 0x40 + 800279e: 68fb ldr r3, [r7, #12] + 80027a0: 6c1b ldr r3, [r3, #64] @ 0x40 + 80027a2: f423 5340 bic.w r3, r3, #12288 @ 0x3000 + 80027a6: f443 5280 orr.w r2, r3, #4096 @ 0x1000 + 80027aa: 68fb ldr r3, [r7, #12] + 80027ac: 641a str r2, [r3, #64] @ 0x40 } } /* State machine update: Check if an injected conversion is ongoing */ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) - 8002712: 68fb ldr r3, [r7, #12] - 8002714: 6c1b ldr r3, [r3, #64] @ 0x40 - 8002716: f403 5380 and.w r3, r3, #4096 @ 0x1000 - 800271a: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 - 800271e: d106 bne.n 800272e + 80027ae: 68fb ldr r3, [r7, #12] + 80027b0: 6c1b ldr r3, [r3, #64] @ 0x40 + 80027b2: f403 5380 and.w r3, r3, #4096 @ 0x1000 + 80027b6: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 + 80027ba: d106 bne.n 80027ca { /* Reset ADC error code fields related to conversions on group regular*/ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); - 8002720: 68fb ldr r3, [r7, #12] - 8002722: 6c5b ldr r3, [r3, #68] @ 0x44 - 8002724: f023 0206 bic.w r2, r3, #6 - 8002728: 68fb ldr r3, [r7, #12] - 800272a: 645a str r2, [r3, #68] @ 0x44 - 800272c: e002 b.n 8002734 + 80027bc: 68fb ldr r3, [r7, #12] + 80027be: 6c5b ldr r3, [r3, #68] @ 0x44 + 80027c0: f023 0206 bic.w r2, r3, #6 + 80027c4: 68fb ldr r3, [r7, #12] + 80027c6: 645a str r2, [r3, #68] @ 0x44 + 80027c8: e002 b.n 80027d0 } else { /* Reset ADC all error code fields */ ADC_CLEAR_ERRORCODE(hadc); - 800272e: 68fb ldr r3, [r7, #12] - 8002730: 2200 movs r2, #0 - 8002732: 645a str r2, [r3, #68] @ 0x44 + 80027ca: 68fb ldr r3, [r7, #12] + 80027cc: 2200 movs r2, #0 + 80027ce: 645a str r2, [r3, #68] @ 0x44 } /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); - 8002734: 68fb ldr r3, [r7, #12] - 8002736: 2200 movs r2, #0 - 8002738: f883 203c strb.w r2, [r3, #60] @ 0x3c + 80027d0: 68fb ldr r3, [r7, #12] + 80027d2: 2200 movs r2, #0 + 80027d4: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Set the DMA transfer complete callback */ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; - 800273c: 68fb ldr r3, [r7, #12] - 800273e: 6b9b ldr r3, [r3, #56] @ 0x38 - 8002740: 4a23 ldr r2, [pc, #140] @ (80027d0 ) - 8002742: 629a str r2, [r3, #40] @ 0x28 + 80027d8: 68fb ldr r3, [r7, #12] + 80027da: 6b9b ldr r3, [r3, #56] @ 0x38 + 80027dc: 4a23 ldr r2, [pc, #140] @ (800286c ) + 80027de: 629a str r2, [r3, #40] @ 0x28 /* Set the DMA half transfer complete callback */ hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; - 8002744: 68fb ldr r3, [r7, #12] - 8002746: 6b9b ldr r3, [r3, #56] @ 0x38 - 8002748: 4a22 ldr r2, [pc, #136] @ (80027d4 ) - 800274a: 62da str r2, [r3, #44] @ 0x2c + 80027e0: 68fb ldr r3, [r7, #12] + 80027e2: 6b9b ldr r3, [r3, #56] @ 0x38 + 80027e4: 4a22 ldr r2, [pc, #136] @ (8002870 ) + 80027e6: 62da str r2, [r3, #44] @ 0x2c /* Set the DMA error callback */ hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; - 800274c: 68fb ldr r3, [r7, #12] - 800274e: 6b9b ldr r3, [r3, #56] @ 0x38 - 8002750: 4a21 ldr r2, [pc, #132] @ (80027d8 ) - 8002752: 631a str r2, [r3, #48] @ 0x30 + 80027e8: 68fb ldr r3, [r7, #12] + 80027ea: 6b9b ldr r3, [r3, #56] @ 0x38 + 80027ec: 4a21 ldr r2, [pc, #132] @ (8002874 ) + 80027ee: 631a str r2, [r3, #48] @ 0x30 /* start (in case of SW start): */ /* Clear regular group conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC */ /* operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); - 8002754: 68fb ldr r3, [r7, #12] - 8002756: 681b ldr r3, [r3, #0] - 8002758: 221c movs r2, #28 - 800275a: 601a str r2, [r3, #0] + 80027f0: 68fb ldr r3, [r7, #12] + 80027f2: 681b ldr r3, [r3, #0] + 80027f4: 221c movs r2, #28 + 80027f6: 601a str r2, [r3, #0] /* Enable ADC overrun interrupt */ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); - 800275c: 68fb ldr r3, [r7, #12] - 800275e: 681b ldr r3, [r3, #0] - 8002760: 685a ldr r2, [r3, #4] - 8002762: 68fb ldr r3, [r7, #12] - 8002764: 681b ldr r3, [r3, #0] - 8002766: f042 0210 orr.w r2, r2, #16 - 800276a: 605a str r2, [r3, #4] + 80027f8: 68fb ldr r3, [r7, #12] + 80027fa: 681b ldr r3, [r3, #0] + 80027fc: 685a ldr r2, [r3, #4] + 80027fe: 68fb ldr r3, [r7, #12] + 8002800: 681b ldr r3, [r3, #0] + 8002802: f042 0210 orr.w r2, r2, #16 + 8002806: 605a str r2, [r3, #4] /* Enable ADC DMA mode */ SET_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN); - 800276c: 68fb ldr r3, [r7, #12] - 800276e: 681b ldr r3, [r3, #0] - 8002770: 68da ldr r2, [r3, #12] - 8002772: 68fb ldr r3, [r7, #12] - 8002774: 681b ldr r3, [r3, #0] - 8002776: f042 0201 orr.w r2, r2, #1 - 800277a: 60da str r2, [r3, #12] + 8002808: 68fb ldr r3, [r7, #12] + 800280a: 681b ldr r3, [r3, #0] + 800280c: 68da ldr r2, [r3, #12] + 800280e: 68fb ldr r3, [r7, #12] + 8002810: 681b ldr r3, [r3, #0] + 8002812: f042 0201 orr.w r2, r2, #1 + 8002816: 60da str r2, [r3, #12] /* Start the DMA channel */ HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); - 800277c: 68fb ldr r3, [r7, #12] - 800277e: 6b98 ldr r0, [r3, #56] @ 0x38 - 8002780: 68fb ldr r3, [r7, #12] - 8002782: 681b ldr r3, [r3, #0] - 8002784: 3340 adds r3, #64 @ 0x40 - 8002786: 4619 mov r1, r3 - 8002788: 68ba ldr r2, [r7, #8] - 800278a: 687b ldr r3, [r7, #4] - 800278c: f001 fea4 bl 80044d8 + 8002818: 68fb ldr r3, [r7, #12] + 800281a: 6b98 ldr r0, [r3, #56] @ 0x38 + 800281c: 68fb ldr r3, [r7, #12] + 800281e: 681b ldr r3, [r3, #0] + 8002820: 3340 adds r3, #64 @ 0x40 + 8002822: 4619 mov r1, r3 + 8002824: 68ba ldr r2, [r7, #8] + 8002826: 687b ldr r3, [r7, #4] + 8002828: f001 fea4 bl 8004574 /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately.*/ /* If external trigger has been selected, conversion will start at */ /* next trigger event. */ SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART); - 8002790: 68fb ldr r3, [r7, #12] - 8002792: 681b ldr r3, [r3, #0] - 8002794: 689a ldr r2, [r3, #8] - 8002796: 68fb ldr r3, [r7, #12] - 8002798: 681b ldr r3, [r3, #0] - 800279a: f042 0204 orr.w r2, r2, #4 - 800279e: 609a str r2, [r3, #8] - 80027a0: e00d b.n 80027be + 800282c: 68fb ldr r3, [r7, #12] + 800282e: 681b ldr r3, [r3, #0] + 8002830: 689a ldr r2, [r3, #8] + 8002832: 68fb ldr r3, [r7, #12] + 8002834: 681b ldr r3, [r3, #0] + 8002836: f042 0204 orr.w r2, r2, #4 + 800283a: 609a str r2, [r3, #8] + 800283c: e00d b.n 800285a } else { /* Process unlocked */ __HAL_UNLOCK(hadc); - 80027a2: 68fb ldr r3, [r7, #12] - 80027a4: 2200 movs r2, #0 - 80027a6: f883 203c strb.w r2, [r3, #60] @ 0x3c - 80027aa: e008 b.n 80027be + 800283e: 68fb ldr r3, [r7, #12] + 8002840: 2200 movs r2, #0 + 8002842: f883 203c strb.w r2, [r3, #60] @ 0x3c + 8002846: e008 b.n 800285a } } else { tmp_hal_status = HAL_ERROR; - 80027ac: 2301 movs r3, #1 - 80027ae: 75fb strb r3, [r7, #23] + 8002848: 2301 movs r3, #1 + 800284a: 75fb strb r3, [r7, #23] /* Process unlocked */ __HAL_UNLOCK(hadc); - 80027b0: 68fb ldr r3, [r7, #12] - 80027b2: 2200 movs r2, #0 - 80027b4: f883 203c strb.w r2, [r3, #60] @ 0x3c - 80027b8: e001 b.n 80027be + 800284c: 68fb ldr r3, [r7, #12] + 800284e: 2200 movs r2, #0 + 8002850: f883 203c strb.w r2, [r3, #60] @ 0x3c + 8002854: e001 b.n 800285a } } else { tmp_hal_status = HAL_BUSY; - 80027ba: 2302 movs r3, #2 - 80027bc: 75fb strb r3, [r7, #23] + 8002856: 2302 movs r3, #2 + 8002858: 75fb strb r3, [r7, #23] } /* Return function status */ return tmp_hal_status; - 80027be: 7dfb ldrb r3, [r7, #23] + 800285a: 7dfb ldrb r3, [r7, #23] } - 80027c0: 4618 mov r0, r3 - 80027c2: 3718 adds r7, #24 - 80027c4: 46bd mov sp, r7 - 80027c6: bd80 pop {r7, pc} - 80027c8: 50000300 .word 0x50000300 - 80027cc: 50000100 .word 0x50000100 - 80027d0: 08003329 .word 0x08003329 - 80027d4: 080033a3 .word 0x080033a3 - 80027d8: 080033bf .word 0x080033bf + 800285c: 4618 mov r0, r3 + 800285e: 3718 adds r7, #24 + 8002860: 46bd mov sp, r7 + 8002862: bd80 pop {r7, pc} + 8002864: 50000300 .word 0x50000300 + 8002868: 50000100 .word 0x50000100 + 800286c: 080033c5 .word 0x080033c5 + 8002870: 0800343f .word 0x0800343f + 8002874: 0800345b .word 0x0800345b -080027dc : +08002878 : * @brief Handles ADC interrupt request. * @param hadc ADC handle * @retval None */ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) { - 80027dc: b580 push {r7, lr} - 80027de: b088 sub sp, #32 - 80027e0: af00 add r7, sp, #0 - 80027e2: 6078 str r0, [r7, #4] + 8002878: b580 push {r7, lr} + 800287a: b088 sub sp, #32 + 800287c: af00 add r7, sp, #0 + 800287e: 6078 str r0, [r7, #4] uint32_t overrun_error = 0U; /* flag set if overrun occurrence has to be considered as an error */ - 80027e4: 2300 movs r3, #0 - 80027e6: 61fb str r3, [r7, #28] + 8002880: 2300 movs r3, #0 + 8002882: 61fb str r3, [r7, #28] ADC_Common_TypeDef *tmpADC_Common; uint32_t tmp_cfgr = 0x0U; - 80027e8: 2300 movs r3, #0 - 80027ea: 61bb str r3, [r7, #24] + 8002884: 2300 movs r3, #0 + 8002886: 61bb str r3, [r7, #24] uint32_t tmp_cfgr_jqm = 0x0U; - 80027ec: 2300 movs r3, #0 - 80027ee: 617b str r3, [r7, #20] + 8002888: 2300 movs r3, #0 + 800288a: 617b str r3, [r7, #20] uint32_t tmp_isr = hadc->Instance->ISR; - 80027f0: 687b ldr r3, [r7, #4] - 80027f2: 681b ldr r3, [r3, #0] - 80027f4: 681b ldr r3, [r3, #0] - 80027f6: 613b str r3, [r7, #16] + 800288c: 687b ldr r3, [r7, #4] + 800288e: 681b ldr r3, [r3, #0] + 8002890: 681b ldr r3, [r3, #0] + 8002892: 613b str r3, [r7, #16] uint32_t tmp_ier = hadc->Instance->IER; - 80027f8: 687b ldr r3, [r7, #4] - 80027fa: 681b ldr r3, [r3, #0] - 80027fc: 685b ldr r3, [r3, #4] - 80027fe: 60fb str r3, [r7, #12] + 8002894: 687b ldr r3, [r7, #4] + 8002896: 681b ldr r3, [r3, #0] + 8002898: 685b ldr r3, [r3, #4] + 800289a: 60fb str r3, [r7, #12] assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); /* ========== Check End of Conversion flag for regular group ========== */ if( (((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) || - 8002800: 693b ldr r3, [r7, #16] - 8002802: f003 0304 and.w r3, r3, #4 - 8002806: 2b00 cmp r3, #0 - 8002808: d004 beq.n 8002814 - 800280a: 68fb ldr r3, [r7, #12] - 800280c: f003 0304 and.w r3, r3, #4 - 8002810: 2b00 cmp r3, #0 - 8002812: d109 bne.n 8002828 + 800289c: 693b ldr r3, [r7, #16] + 800289e: f003 0304 and.w r3, r3, #4 + 80028a2: 2b00 cmp r3, #0 + 80028a4: d004 beq.n 80028b0 + 80028a6: 68fb ldr r3, [r7, #12] + 80028a8: f003 0304 and.w r3, r3, #4 + 80028ac: 2b00 cmp r3, #0 + 80028ae: d109 bne.n 80028c4 (((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS)) ) - 8002814: 693b ldr r3, [r7, #16] - 8002816: f003 0308 and.w r3, r3, #8 + 80028b0: 693b ldr r3, [r7, #16] + 80028b2: f003 0308 and.w r3, r3, #8 if( (((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) || - 800281a: 2b00 cmp r3, #0 - 800281c: d076 beq.n 800290c + 80028b6: 2b00 cmp r3, #0 + 80028b8: d076 beq.n 80029a8 (((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS)) ) - 800281e: 68fb ldr r3, [r7, #12] - 8002820: f003 0308 and.w r3, r3, #8 - 8002824: 2b00 cmp r3, #0 - 8002826: d071 beq.n 800290c + 80028ba: 68fb ldr r3, [r7, #12] + 80028bc: f003 0308 and.w r3, r3, #8 + 80028c0: 2b00 cmp r3, #0 + 80028c2: d071 beq.n 80029a8 { /* Update state machine on conversion status if not in error state */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) - 8002828: 687b ldr r3, [r7, #4] - 800282a: 6c1b ldr r3, [r3, #64] @ 0x40 - 800282c: f003 0310 and.w r3, r3, #16 - 8002830: 2b00 cmp r3, #0 - 8002832: d105 bne.n 8002840 + 80028c4: 687b ldr r3, [r7, #4] + 80028c6: 6c1b ldr r3, [r3, #64] @ 0x40 + 80028c8: f003 0310 and.w r3, r3, #16 + 80028cc: 2b00 cmp r3, #0 + 80028ce: d105 bne.n 80028dc { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); - 8002834: 687b ldr r3, [r7, #4] - 8002836: 6c1b ldr r3, [r3, #64] @ 0x40 - 8002838: f443 7200 orr.w r2, r3, #512 @ 0x200 - 800283c: 687b ldr r3, [r7, #4] - 800283e: 641a str r2, [r3, #64] @ 0x40 + 80028d0: 687b ldr r3, [r7, #4] + 80028d2: 6c1b ldr r3, [r3, #64] @ 0x40 + 80028d4: f443 7200 orr.w r2, r3, #512 @ 0x200 + 80028d8: 687b ldr r3, [r7, #4] + 80028da: 641a str r2, [r3, #64] @ 0x40 } /* Get relevant register CFGR in ADC instance of ADC master or slave */ /* in function of multimode state (for devices with multimode */ /* available). */ if (ADC_NONMULTIMODE_REG_OR_MULTIMODEMASTER(hadc)) - 8002840: 4b82 ldr r3, [pc, #520] @ (8002a4c ) - 8002842: 689b ldr r3, [r3, #8] - 8002844: f003 031f and.w r3, r3, #31 - 8002848: 2b00 cmp r3, #0 - 800284a: d010 beq.n 800286e - 800284c: 4b7f ldr r3, [pc, #508] @ (8002a4c ) - 800284e: 689b ldr r3, [r3, #8] - 8002850: f003 031f and.w r3, r3, #31 - 8002854: 2b05 cmp r3, #5 - 8002856: d00a beq.n 800286e - 8002858: 4b7c ldr r3, [pc, #496] @ (8002a4c ) - 800285a: 689b ldr r3, [r3, #8] - 800285c: f003 031f and.w r3, r3, #31 - 8002860: 2b09 cmp r3, #9 - 8002862: d004 beq.n 800286e - 8002864: 687b ldr r3, [r7, #4] - 8002866: 681b ldr r3, [r3, #0] - 8002868: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 - 800286c: d104 bne.n 8002878 + 80028dc: 4b82 ldr r3, [pc, #520] @ (8002ae8 ) + 80028de: 689b ldr r3, [r3, #8] + 80028e0: f003 031f and.w r3, r3, #31 + 80028e4: 2b00 cmp r3, #0 + 80028e6: d010 beq.n 800290a + 80028e8: 4b7f ldr r3, [pc, #508] @ (8002ae8 ) + 80028ea: 689b ldr r3, [r3, #8] + 80028ec: f003 031f and.w r3, r3, #31 + 80028f0: 2b05 cmp r3, #5 + 80028f2: d00a beq.n 800290a + 80028f4: 4b7c ldr r3, [pc, #496] @ (8002ae8 ) + 80028f6: 689b ldr r3, [r3, #8] + 80028f8: f003 031f and.w r3, r3, #31 + 80028fc: 2b09 cmp r3, #9 + 80028fe: d004 beq.n 800290a + 8002900: 687b ldr r3, [r7, #4] + 8002902: 681b ldr r3, [r3, #0] + 8002904: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 + 8002908: d104 bne.n 8002914 { tmp_cfgr = READ_REG(hadc->Instance->CFGR); - 800286e: 687b ldr r3, [r7, #4] - 8002870: 681b ldr r3, [r3, #0] - 8002872: 68db ldr r3, [r3, #12] - 8002874: 61bb str r3, [r7, #24] - 8002876: e003 b.n 8002880 + 800290a: 687b ldr r3, [r7, #4] + 800290c: 681b ldr r3, [r3, #0] + 800290e: 68db ldr r3, [r3, #12] + 8002910: 61bb str r3, [r7, #24] + 8002912: e003 b.n 800291c } else { tmp_cfgr = READ_REG(ADC_MASTER_INSTANCE(hadc)->CFGR); - 8002878: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 - 800287c: 68db ldr r3, [r3, #12] - 800287e: 61bb str r3, [r7, #24] + 8002914: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 + 8002918: 68db ldr r3, [r3, #12] + 800291a: 61bb str r3, [r7, #24] } /* Disable interruption if no further conversion upcoming by regular */ /* external trigger or by continuous mode, */ /* and if scan sequence if completed. */ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && - 8002880: 687b ldr r3, [r7, #4] - 8002882: 681b ldr r3, [r3, #0] - 8002884: 68db ldr r3, [r3, #12] - 8002886: f403 6340 and.w r3, r3, #3072 @ 0xc00 - 800288a: 2b00 cmp r3, #0 - 800288c: d137 bne.n 80028fe + 800291c: 687b ldr r3, [r7, #4] + 800291e: 681b ldr r3, [r3, #0] + 8002920: 68db ldr r3, [r3, #12] + 8002922: f403 6340 and.w r3, r3, #3072 @ 0xc00 + 8002926: 2b00 cmp r3, #0 + 8002928: d137 bne.n 800299a (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == RESET) ) - 800288e: 69bb ldr r3, [r7, #24] - 8002890: f403 5300 and.w r3, r3, #8192 @ 0x2000 + 800292a: 69bb ldr r3, [r7, #24] + 800292c: f403 5300 and.w r3, r3, #8192 @ 0x2000 if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && - 8002894: 2b00 cmp r3, #0 - 8002896: d132 bne.n 80028fe + 8002930: 2b00 cmp r3, #0 + 8002932: d132 bne.n 800299a { /* If End of Sequence is reached, disable interrupts */ if((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) - 8002898: 693b ldr r3, [r7, #16] - 800289a: f003 0308 and.w r3, r3, #8 - 800289e: 2b00 cmp r3, #0 - 80028a0: d02d beq.n 80028fe + 8002934: 693b ldr r3, [r7, #16] + 8002936: f003 0308 and.w r3, r3, #8 + 800293a: 2b00 cmp r3, #0 + 800293c: d02d beq.n 800299a { /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */ /* ADSTART==0 (no conversion on going) */ if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) - 80028a2: 687b ldr r3, [r7, #4] - 80028a4: 681b ldr r3, [r3, #0] - 80028a6: 689b ldr r3, [r3, #8] - 80028a8: f003 0304 and.w r3, r3, #4 - 80028ac: 2b00 cmp r3, #0 - 80028ae: d11a bne.n 80028e6 + 800293e: 687b ldr r3, [r7, #4] + 8002940: 681b ldr r3, [r3, #0] + 8002942: 689b ldr r3, [r3, #8] + 8002944: f003 0304 and.w r3, r3, #4 + 8002948: 2b00 cmp r3, #0 + 800294a: d11a bne.n 8002982 { /* Disable ADC end of sequence conversion interrupt */ /* Note: Overrun interrupt was enabled with EOC interrupt in */ /* HAL_Start_IT(), but is not disabled here because can be used */ /* by overrun IRQ process below. */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS); - 80028b0: 687b ldr r3, [r7, #4] - 80028b2: 681b ldr r3, [r3, #0] - 80028b4: 685a ldr r2, [r3, #4] - 80028b6: 687b ldr r3, [r7, #4] - 80028b8: 681b ldr r3, [r3, #0] - 80028ba: f022 020c bic.w r2, r2, #12 - 80028be: 605a str r2, [r3, #4] + 800294c: 687b ldr r3, [r7, #4] + 800294e: 681b ldr r3, [r3, #0] + 8002950: 685a ldr r2, [r3, #4] + 8002952: 687b ldr r3, [r7, #4] + 8002954: 681b ldr r3, [r3, #0] + 8002956: f022 020c bic.w r2, r2, #12 + 800295a: 605a str r2, [r3, #4] /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); - 80028c0: 687b ldr r3, [r7, #4] - 80028c2: 6c1b ldr r3, [r3, #64] @ 0x40 - 80028c4: f423 7280 bic.w r2, r3, #256 @ 0x100 - 80028c8: 687b ldr r3, [r7, #4] - 80028ca: 641a str r2, [r3, #64] @ 0x40 + 800295c: 687b ldr r3, [r7, #4] + 800295e: 6c1b ldr r3, [r3, #64] @ 0x40 + 8002960: f423 7280 bic.w r2, r3, #256 @ 0x100 + 8002964: 687b ldr r3, [r7, #4] + 8002966: 641a str r2, [r3, #64] @ 0x40 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) - 80028cc: 687b ldr r3, [r7, #4] - 80028ce: 6c1b ldr r3, [r3, #64] @ 0x40 - 80028d0: f403 5380 and.w r3, r3, #4096 @ 0x1000 - 80028d4: 2b00 cmp r3, #0 - 80028d6: d112 bne.n 80028fe + 8002968: 687b ldr r3, [r7, #4] + 800296a: 6c1b ldr r3, [r3, #64] @ 0x40 + 800296c: f403 5380 and.w r3, r3, #4096 @ 0x1000 + 8002970: 2b00 cmp r3, #0 + 8002972: d112 bne.n 800299a { SET_BIT(hadc->State, HAL_ADC_STATE_READY); - 80028d8: 687b ldr r3, [r7, #4] - 80028da: 6c1b ldr r3, [r3, #64] @ 0x40 - 80028dc: f043 0201 orr.w r2, r3, #1 - 80028e0: 687b ldr r3, [r7, #4] - 80028e2: 641a str r2, [r3, #64] @ 0x40 - 80028e4: e00b b.n 80028fe + 8002974: 687b ldr r3, [r7, #4] + 8002976: 6c1b ldr r3, [r3, #64] @ 0x40 + 8002978: f043 0201 orr.w r2, r3, #1 + 800297c: 687b ldr r3, [r7, #4] + 800297e: 641a str r2, [r3, #64] @ 0x40 + 8002980: e00b b.n 800299a } } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - 80028e6: 687b ldr r3, [r7, #4] - 80028e8: 6c1b ldr r3, [r3, #64] @ 0x40 - 80028ea: f043 0210 orr.w r2, r3, #16 - 80028ee: 687b ldr r3, [r7, #4] - 80028f0: 641a str r2, [r3, #64] @ 0x40 + 8002982: 687b ldr r3, [r7, #4] + 8002984: 6c1b ldr r3, [r3, #64] @ 0x40 + 8002986: f043 0210 orr.w r2, r3, #16 + 800298a: 687b ldr r3, [r7, #4] + 800298c: 641a str r2, [r3, #64] @ 0x40 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - 80028f2: 687b ldr r3, [r7, #4] - 80028f4: 6c5b ldr r3, [r3, #68] @ 0x44 - 80028f6: f043 0201 orr.w r2, r3, #1 - 80028fa: 687b ldr r3, [r7, #4] - 80028fc: 645a str r2, [r3, #68] @ 0x44 + 800298e: 687b ldr r3, [r7, #4] + 8002990: 6c5b ldr r3, [r3, #68] @ 0x44 + 8002992: f043 0201 orr.w r2, r3, #1 + 8002996: 687b ldr r3, [r7, #4] + 8002998: 645a str r2, [r3, #68] @ 0x44 /* from EOC or EOS, possibility to use: */ /* " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvCpltCallback(hadc); #else HAL_ADC_ConvCpltCallback(hadc); - 80028fe: 6878 ldr r0, [r7, #4] - 8002900: f7fe fae2 bl 8000ec8 + 800299a: 6878 ldr r0, [r7, #4] + 800299c: f7fe faa0 bl 8000ee0 /* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of */ /* conversion flags clear induces the release of the preserved */ /* data. */ /* Therefore, if the preserved data value is needed, it must be */ /* read preliminarily into HAL_ADC_ConvCpltCallback(). */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS) ); - 8002904: 687b ldr r3, [r7, #4] - 8002906: 681b ldr r3, [r3, #0] - 8002908: 220c movs r2, #12 - 800290a: 601a str r2, [r3, #0] + 80029a0: 687b ldr r3, [r7, #4] + 80029a2: 681b ldr r3, [r3, #0] + 80029a4: 220c movs r2, #12 + 80029a6: 601a str r2, [r3, #0] } /* ========== Check End of Conversion flag for injected group ========== */ if( (((tmp_isr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) && ((tmp_ier & ADC_IT_JEOC) == ADC_IT_JEOC)) || - 800290c: 693b ldr r3, [r7, #16] - 800290e: f003 0320 and.w r3, r3, #32 - 8002912: 2b00 cmp r3, #0 - 8002914: d004 beq.n 8002920 - 8002916: 68fb ldr r3, [r7, #12] - 8002918: f003 0320 and.w r3, r3, #32 - 800291c: 2b00 cmp r3, #0 - 800291e: d10b bne.n 8002938 + 80029a8: 693b ldr r3, [r7, #16] + 80029aa: f003 0320 and.w r3, r3, #32 + 80029ae: 2b00 cmp r3, #0 + 80029b0: d004 beq.n 80029bc + 80029b2: 68fb ldr r3, [r7, #12] + 80029b4: f003 0320 and.w r3, r3, #32 + 80029b8: 2b00 cmp r3, #0 + 80029ba: d10b bne.n 80029d4 (((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) && ((tmp_ier & ADC_IT_JEOS) == ADC_IT_JEOS)) ) - 8002920: 693b ldr r3, [r7, #16] - 8002922: f003 0340 and.w r3, r3, #64 @ 0x40 + 80029bc: 693b ldr r3, [r7, #16] + 80029be: f003 0340 and.w r3, r3, #64 @ 0x40 if( (((tmp_isr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) && ((tmp_ier & ADC_IT_JEOC) == ADC_IT_JEOC)) || - 8002926: 2b00 cmp r3, #0 - 8002928: f000 80a5 beq.w 8002a76 + 80029c2: 2b00 cmp r3, #0 + 80029c4: f000 80a5 beq.w 8002b12 (((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) && ((tmp_ier & ADC_IT_JEOS) == ADC_IT_JEOS)) ) - 800292c: 68fb ldr r3, [r7, #12] - 800292e: f003 0340 and.w r3, r3, #64 @ 0x40 - 8002932: 2b00 cmp r3, #0 - 8002934: f000 809f beq.w 8002a76 + 80029c8: 68fb ldr r3, [r7, #12] + 80029ca: f003 0340 and.w r3, r3, #64 @ 0x40 + 80029ce: 2b00 cmp r3, #0 + 80029d0: f000 809f beq.w 8002b12 { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); - 8002938: 687b ldr r3, [r7, #4] - 800293a: 6c1b ldr r3, [r3, #64] @ 0x40 - 800293c: f443 5200 orr.w r2, r3, #8192 @ 0x2000 - 8002940: 687b ldr r3, [r7, #4] - 8002942: 641a str r2, [r3, #64] @ 0x40 + 80029d4: 687b ldr r3, [r7, #4] + 80029d6: 6c1b ldr r3, [r3, #64] @ 0x40 + 80029d8: f443 5200 orr.w r2, r3, #8192 @ 0x2000 + 80029dc: 687b ldr r3, [r7, #4] + 80029de: 641a str r2, [r3, #64] @ 0x40 /* Get relevant register CFGR in ADC instance of ADC master or slave */ /* in function of multimode state (for devices with multimode */ /* available). */ if (ADC_NONMULTIMODE_REG_OR_MULTIMODEMASTER(hadc)) - 8002944: 4b41 ldr r3, [pc, #260] @ (8002a4c ) - 8002946: 689b ldr r3, [r3, #8] - 8002948: f003 031f and.w r3, r3, #31 - 800294c: 2b00 cmp r3, #0 - 800294e: d010 beq.n 8002972 - 8002950: 4b3e ldr r3, [pc, #248] @ (8002a4c ) - 8002952: 689b ldr r3, [r3, #8] - 8002954: f003 031f and.w r3, r3, #31 - 8002958: 2b05 cmp r3, #5 - 800295a: d00a beq.n 8002972 - 800295c: 4b3b ldr r3, [pc, #236] @ (8002a4c ) - 800295e: 689b ldr r3, [r3, #8] - 8002960: f003 031f and.w r3, r3, #31 - 8002964: 2b09 cmp r3, #9 - 8002966: d004 beq.n 8002972 - 8002968: 687b ldr r3, [r7, #4] - 800296a: 681b ldr r3, [r3, #0] - 800296c: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 - 8002970: d104 bne.n 800297c + 80029e0: 4b41 ldr r3, [pc, #260] @ (8002ae8 ) + 80029e2: 689b ldr r3, [r3, #8] + 80029e4: f003 031f and.w r3, r3, #31 + 80029e8: 2b00 cmp r3, #0 + 80029ea: d010 beq.n 8002a0e + 80029ec: 4b3e ldr r3, [pc, #248] @ (8002ae8 ) + 80029ee: 689b ldr r3, [r3, #8] + 80029f0: f003 031f and.w r3, r3, #31 + 80029f4: 2b05 cmp r3, #5 + 80029f6: d00a beq.n 8002a0e + 80029f8: 4b3b ldr r3, [pc, #236] @ (8002ae8 ) + 80029fa: 689b ldr r3, [r3, #8] + 80029fc: f003 031f and.w r3, r3, #31 + 8002a00: 2b09 cmp r3, #9 + 8002a02: d004 beq.n 8002a0e + 8002a04: 687b ldr r3, [r7, #4] + 8002a06: 681b ldr r3, [r3, #0] + 8002a08: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 + 8002a0c: d104 bne.n 8002a18 { tmp_cfgr = READ_REG(hadc->Instance->CFGR); - 8002972: 687b ldr r3, [r7, #4] - 8002974: 681b ldr r3, [r3, #0] - 8002976: 68db ldr r3, [r3, #12] - 8002978: 61bb str r3, [r7, #24] - 800297a: e003 b.n 8002984 + 8002a0e: 687b ldr r3, [r7, #4] + 8002a10: 681b ldr r3, [r3, #0] + 8002a12: 68db ldr r3, [r3, #12] + 8002a14: 61bb str r3, [r7, #24] + 8002a16: e003 b.n 8002a20 } else { tmp_cfgr = READ_REG(ADC_MASTER_INSTANCE(hadc)->CFGR); - 800297c: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 - 8002980: 68db ldr r3, [r3, #12] - 8002982: 61bb str r3, [r7, #24] + 8002a18: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 + 8002a1c: 68db ldr r3, [r3, #12] + 8002a1e: 61bb str r3, [r7, #24] /* Disable interruption if no further conversion upcoming by injected */ /* external trigger or by automatic injected conversion with regular */ /* group having no further conversion upcoming (same conditions as */ /* regular group interruption disabling above), */ /* and if injected scan sequence is completed. */ if(ADC_IS_SOFTWARE_START_INJECTED(hadc)) - 8002984: 687b ldr r3, [r7, #4] - 8002986: 681b ldr r3, [r3, #0] - 8002988: 6cdb ldr r3, [r3, #76] @ 0x4c - 800298a: f003 03c0 and.w r3, r3, #192 @ 0xc0 - 800298e: 2b00 cmp r3, #0 - 8002990: d16a bne.n 8002a68 + 8002a20: 687b ldr r3, [r7, #4] + 8002a22: 681b ldr r3, [r3, #0] + 8002a24: 6cdb ldr r3, [r3, #76] @ 0x4c + 8002a26: f003 03c0 and.w r3, r3, #192 @ 0xc0 + 8002a2a: 2b00 cmp r3, #0 + 8002a2c: d16a bne.n 8002b04 { if((READ_BIT (tmp_cfgr, ADC_CFGR_JAUTO) == RESET) || - 8002992: 69bb ldr r3, [r7, #24] - 8002994: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 - 8002998: 2b00 cmp r3, #0 - 800299a: d00b beq.n 80029b4 + 8002a2e: 69bb ldr r3, [r7, #24] + 8002a30: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 8002a34: 2b00 cmp r3, #0 + 8002a36: d00b beq.n 8002a50 (ADC_IS_SOFTWARE_START_REGULAR(hadc) && - 800299c: 687b ldr r3, [r7, #4] - 800299e: 681b ldr r3, [r3, #0] - 80029a0: 68db ldr r3, [r3, #12] - 80029a2: f403 6340 and.w r3, r3, #3072 @ 0xc00 + 8002a38: 687b ldr r3, [r7, #4] + 8002a3a: 681b ldr r3, [r3, #0] + 8002a3c: 68db ldr r3, [r3, #12] + 8002a3e: f403 6340 and.w r3, r3, #3072 @ 0xc00 if((READ_BIT (tmp_cfgr, ADC_CFGR_JAUTO) == RESET) || - 80029a6: 2b00 cmp r3, #0 - 80029a8: d15e bne.n 8002a68 + 8002a42: 2b00 cmp r3, #0 + 8002a44: d15e bne.n 8002b04 (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) == RESET) ) ) - 80029aa: 69bb ldr r3, [r7, #24] - 80029ac: f403 5300 and.w r3, r3, #8192 @ 0x2000 + 8002a46: 69bb ldr r3, [r7, #24] + 8002a48: f403 5300 and.w r3, r3, #8192 @ 0x2000 (ADC_IS_SOFTWARE_START_REGULAR(hadc) && - 80029b0: 2b00 cmp r3, #0 - 80029b2: d159 bne.n 8002a68 + 8002a4c: 2b00 cmp r3, #0 + 8002a4e: d159 bne.n 8002b04 { /* If End of Sequence is reached, disable interrupts */ if((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) - 80029b4: 693b ldr r3, [r7, #16] - 80029b6: f003 0340 and.w r3, r3, #64 @ 0x40 - 80029ba: 2b00 cmp r3, #0 - 80029bc: d054 beq.n 8002a68 + 8002a50: 693b ldr r3, [r7, #16] + 8002a52: f003 0340 and.w r3, r3, #64 @ 0x40 + 8002a56: 2b00 cmp r3, #0 + 8002a58: d054 beq.n 8002b04 { /* Get relevant register CFGR in ADC instance of ADC master or slave */ /* in function of multimode state (for devices with multimode */ /* available). */ if (ADC_NONMULTIMODE_INJ_OR_MULTIMODEMASTER(hadc)) - 80029be: 4b23 ldr r3, [pc, #140] @ (8002a4c ) - 80029c0: 689b ldr r3, [r3, #8] - 80029c2: f003 031f and.w r3, r3, #31 - 80029c6: 2b00 cmp r3, #0 - 80029c8: d010 beq.n 80029ec - 80029ca: 4b20 ldr r3, [pc, #128] @ (8002a4c ) - 80029cc: 689b ldr r3, [r3, #8] - 80029ce: f003 031f and.w r3, r3, #31 - 80029d2: 2b06 cmp r3, #6 - 80029d4: d00a beq.n 80029ec - 80029d6: 4b1d ldr r3, [pc, #116] @ (8002a4c ) - 80029d8: 689b ldr r3, [r3, #8] - 80029da: f003 031f and.w r3, r3, #31 - 80029de: 2b07 cmp r3, #7 - 80029e0: d004 beq.n 80029ec - 80029e2: 687b ldr r3, [r7, #4] - 80029e4: 681b ldr r3, [r3, #0] - 80029e6: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 - 80029ea: d104 bne.n 80029f6 + 8002a5a: 4b23 ldr r3, [pc, #140] @ (8002ae8 ) + 8002a5c: 689b ldr r3, [r3, #8] + 8002a5e: f003 031f and.w r3, r3, #31 + 8002a62: 2b00 cmp r3, #0 + 8002a64: d010 beq.n 8002a88 + 8002a66: 4b20 ldr r3, [pc, #128] @ (8002ae8 ) + 8002a68: 689b ldr r3, [r3, #8] + 8002a6a: f003 031f and.w r3, r3, #31 + 8002a6e: 2b06 cmp r3, #6 + 8002a70: d00a beq.n 8002a88 + 8002a72: 4b1d ldr r3, [pc, #116] @ (8002ae8 ) + 8002a74: 689b ldr r3, [r3, #8] + 8002a76: f003 031f and.w r3, r3, #31 + 8002a7a: 2b07 cmp r3, #7 + 8002a7c: d004 beq.n 8002a88 + 8002a7e: 687b ldr r3, [r7, #4] + 8002a80: 681b ldr r3, [r3, #0] + 8002a82: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 + 8002a86: d104 bne.n 8002a92 { tmp_cfgr_jqm = READ_REG(hadc->Instance->CFGR); - 80029ec: 687b ldr r3, [r7, #4] - 80029ee: 681b ldr r3, [r3, #0] - 80029f0: 68db ldr r3, [r3, #12] - 80029f2: 617b str r3, [r7, #20] - 80029f4: e003 b.n 80029fe + 8002a88: 687b ldr r3, [r7, #4] + 8002a8a: 681b ldr r3, [r3, #0] + 8002a8c: 68db ldr r3, [r3, #12] + 8002a8e: 617b str r3, [r7, #20] + 8002a90: e003 b.n 8002a9a } else { tmp_cfgr_jqm = READ_REG(ADC_MASTER_INSTANCE(hadc)->CFGR); - 80029f6: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 - 80029fa: 68db ldr r3, [r3, #12] - 80029fc: 617b str r3, [r7, #20] + 8002a92: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 + 8002a96: 68db ldr r3, [r3, #12] + 8002a98: 617b str r3, [r7, #20] /* when the last context has been fully processed, JSQR is reset */ /* by the hardware. Even if no injected conversion is planned to come */ /* (queue empty, triggers are ignored), it can start again */ /* immediately after setting a new context (JADSTART is still set). */ /* Therefore, state of HAL ADC injected group is kept to busy. */ if(READ_BIT(tmp_cfgr_jqm, ADC_CFGR_JQM) == RESET) - 80029fe: 697b ldr r3, [r7, #20] - 8002a00: f403 1300 and.w r3, r3, #2097152 @ 0x200000 - 8002a04: 2b00 cmp r3, #0 - 8002a06: d12f bne.n 8002a68 + 8002a9a: 697b ldr r3, [r7, #20] + 8002a9c: f403 1300 and.w r3, r3, #2097152 @ 0x200000 + 8002aa0: 2b00 cmp r3, #0 + 8002aa2: d12f bne.n 8002b04 { /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */ /* JADSTART==0 (no conversion on going) */ if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET) - 8002a08: 687b ldr r3, [r7, #4] - 8002a0a: 681b ldr r3, [r3, #0] - 8002a0c: 689b ldr r3, [r3, #8] - 8002a0e: f003 0308 and.w r3, r3, #8 - 8002a12: 2b00 cmp r3, #0 - 8002a14: d11c bne.n 8002a50 + 8002aa4: 687b ldr r3, [r7, #4] + 8002aa6: 681b ldr r3, [r3, #0] + 8002aa8: 689b ldr r3, [r3, #8] + 8002aaa: f003 0308 and.w r3, r3, #8 + 8002aae: 2b00 cmp r3, #0 + 8002ab0: d11c bne.n 8002aec { /* Disable ADC end of sequence conversion interrupt */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS); - 8002a16: 687b ldr r3, [r7, #4] - 8002a18: 681b ldr r3, [r3, #0] - 8002a1a: 685a ldr r2, [r3, #4] - 8002a1c: 687b ldr r3, [r7, #4] - 8002a1e: 681b ldr r3, [r3, #0] - 8002a20: f022 0260 bic.w r2, r2, #96 @ 0x60 - 8002a24: 605a str r2, [r3, #4] + 8002ab2: 687b ldr r3, [r7, #4] + 8002ab4: 681b ldr r3, [r3, #0] + 8002ab6: 685a ldr r2, [r3, #4] + 8002ab8: 687b ldr r3, [r7, #4] + 8002aba: 681b ldr r3, [r3, #0] + 8002abc: f022 0260 bic.w r2, r2, #96 @ 0x60 + 8002ac0: 605a str r2, [r3, #4] /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); - 8002a26: 687b ldr r3, [r7, #4] - 8002a28: 6c1b ldr r3, [r3, #64] @ 0x40 - 8002a2a: f423 5280 bic.w r2, r3, #4096 @ 0x1000 - 8002a2e: 687b ldr r3, [r7, #4] - 8002a30: 641a str r2, [r3, #64] @ 0x40 + 8002ac2: 687b ldr r3, [r7, #4] + 8002ac4: 6c1b ldr r3, [r3, #64] @ 0x40 + 8002ac6: f423 5280 bic.w r2, r3, #4096 @ 0x1000 + 8002aca: 687b ldr r3, [r7, #4] + 8002acc: 641a str r2, [r3, #64] @ 0x40 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) - 8002a32: 687b ldr r3, [r7, #4] - 8002a34: 6c1b ldr r3, [r3, #64] @ 0x40 - 8002a36: f403 7380 and.w r3, r3, #256 @ 0x100 - 8002a3a: 2b00 cmp r3, #0 - 8002a3c: d114 bne.n 8002a68 + 8002ace: 687b ldr r3, [r7, #4] + 8002ad0: 6c1b ldr r3, [r3, #64] @ 0x40 + 8002ad2: f403 7380 and.w r3, r3, #256 @ 0x100 + 8002ad6: 2b00 cmp r3, #0 + 8002ad8: d114 bne.n 8002b04 { SET_BIT(hadc->State, HAL_ADC_STATE_READY); - 8002a3e: 687b ldr r3, [r7, #4] - 8002a40: 6c1b ldr r3, [r3, #64] @ 0x40 - 8002a42: f043 0201 orr.w r2, r3, #1 - 8002a46: 687b ldr r3, [r7, #4] - 8002a48: 641a str r2, [r3, #64] @ 0x40 - 8002a4a: e00d b.n 8002a68 - 8002a4c: 50000300 .word 0x50000300 + 8002ada: 687b ldr r3, [r7, #4] + 8002adc: 6c1b ldr r3, [r3, #64] @ 0x40 + 8002ade: f043 0201 orr.w r2, r3, #1 + 8002ae2: 687b ldr r3, [r7, #4] + 8002ae4: 641a str r2, [r3, #64] @ 0x40 + 8002ae6: e00d b.n 8002b04 + 8002ae8: 50000300 .word 0x50000300 } } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - 8002a50: 687b ldr r3, [r7, #4] - 8002a52: 6c1b ldr r3, [r3, #64] @ 0x40 - 8002a54: f043 0210 orr.w r2, r3, #16 - 8002a58: 687b ldr r3, [r7, #4] - 8002a5a: 641a str r2, [r3, #64] @ 0x40 + 8002aec: 687b ldr r3, [r7, #4] + 8002aee: 6c1b ldr r3, [r3, #64] @ 0x40 + 8002af0: f043 0210 orr.w r2, r3, #16 + 8002af4: 687b ldr r3, [r7, #4] + 8002af6: 641a str r2, [r3, #64] @ 0x40 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - 8002a5c: 687b ldr r3, [r7, #4] - 8002a5e: 6c5b ldr r3, [r3, #68] @ 0x44 - 8002a60: f043 0201 orr.w r2, r3, #1 - 8002a64: 687b ldr r3, [r7, #4] - 8002a66: 645a str r2, [r3, #68] @ 0x44 + 8002af8: 687b ldr r3, [r7, #4] + 8002afa: 6c5b ldr r3, [r3, #68] @ 0x44 + 8002afc: f043 0201 orr.w r2, r3, #1 + 8002b00: 687b ldr r3, [r7, #4] + 8002b02: 645a str r2, [r3, #68] @ 0x44 /* from JEOC or JEOS, possibility to use: */ /* " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOS)) " */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->InjectedConvCpltCallback(hadc); #else HAL_ADCEx_InjectedConvCpltCallback(hadc); - 8002a68: 6878 ldr r0, [r7, #4] - 8002a6a: f000 f8b1 bl 8002bd0 + 8002b04: 6878 ldr r0, [r7, #4] + 8002b06: f000 f8b1 bl 8002c6c #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear injected group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC | ADC_FLAG_JEOS); - 8002a6e: 687b ldr r3, [r7, #4] - 8002a70: 681b ldr r3, [r3, #0] - 8002a72: 2260 movs r2, #96 @ 0x60 - 8002a74: 601a str r2, [r3, #0] + 8002b0a: 687b ldr r3, [r7, #4] + 8002b0c: 681b ldr r3, [r3, #0] + 8002b0e: 2260 movs r2, #96 @ 0x60 + 8002b10: 601a str r2, [r3, #0] } /* ========== Check analog watchdog 1 flag ========== */ if(((tmp_isr & ADC_FLAG_AWD1) == ADC_FLAG_AWD1) && ((tmp_ier & ADC_IT_AWD1) == ADC_IT_AWD1)) - 8002a76: 693b ldr r3, [r7, #16] - 8002a78: f003 0380 and.w r3, r3, #128 @ 0x80 - 8002a7c: 2b00 cmp r3, #0 - 8002a7e: d011 beq.n 8002aa4 - 8002a80: 68fb ldr r3, [r7, #12] - 8002a82: f003 0380 and.w r3, r3, #128 @ 0x80 - 8002a86: 2b00 cmp r3, #0 - 8002a88: d00c beq.n 8002aa4 + 8002b12: 693b ldr r3, [r7, #16] + 8002b14: f003 0380 and.w r3, r3, #128 @ 0x80 + 8002b18: 2b00 cmp r3, #0 + 8002b1a: d011 beq.n 8002b40 + 8002b1c: 68fb ldr r3, [r7, #12] + 8002b1e: f003 0380 and.w r3, r3, #128 @ 0x80 + 8002b22: 2b00 cmp r3, #0 + 8002b24: d00c beq.n 8002b40 { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); - 8002a8a: 687b ldr r3, [r7, #4] - 8002a8c: 6c1b ldr r3, [r3, #64] @ 0x40 - 8002a8e: f443 3280 orr.w r2, r3, #65536 @ 0x10000 - 8002a92: 687b ldr r3, [r7, #4] - 8002a94: 641a str r2, [r3, #64] @ 0x40 + 8002b26: 687b ldr r3, [r7, #4] + 8002b28: 6c1b ldr r3, [r3, #64] @ 0x40 + 8002b2a: f443 3280 orr.w r2, r3, #65536 @ 0x10000 + 8002b2e: 687b ldr r3, [r7, #4] + 8002b30: 641a str r2, [r3, #64] @ 0x40 /* Level out of window 1 callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->LevelOutOfWindowCallback(hadc); #else HAL_ADC_LevelOutOfWindowCallback(hadc); - 8002a96: 6878 ldr r0, [r7, #4] - 8002a98: f7ff fc20 bl 80022dc + 8002b32: 6878 ldr r0, [r7, #4] + 8002b34: f7ff fc20 bl 8002378 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear ADC analog watchdog flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1); - 8002a9c: 687b ldr r3, [r7, #4] - 8002a9e: 681b ldr r3, [r3, #0] - 8002aa0: 2280 movs r2, #128 @ 0x80 - 8002aa2: 601a str r2, [r3, #0] + 8002b38: 687b ldr r3, [r7, #4] + 8002b3a: 681b ldr r3, [r3, #0] + 8002b3c: 2280 movs r2, #128 @ 0x80 + 8002b3e: 601a str r2, [r3, #0] } /* ========== Check analog watchdog 2 flag ========== */ if(((tmp_isr & ADC_FLAG_AWD2) == ADC_FLAG_AWD2) && ((tmp_ier & ADC_IT_AWD2) == ADC_IT_AWD2)) - 8002aa4: 693b ldr r3, [r7, #16] - 8002aa6: f403 7380 and.w r3, r3, #256 @ 0x100 - 8002aaa: 2b00 cmp r3, #0 - 8002aac: d012 beq.n 8002ad4 - 8002aae: 68fb ldr r3, [r7, #12] - 8002ab0: f403 7380 and.w r3, r3, #256 @ 0x100 - 8002ab4: 2b00 cmp r3, #0 - 8002ab6: d00d beq.n 8002ad4 + 8002b40: 693b ldr r3, [r7, #16] + 8002b42: f403 7380 and.w r3, r3, #256 @ 0x100 + 8002b46: 2b00 cmp r3, #0 + 8002b48: d012 beq.n 8002b70 + 8002b4a: 68fb ldr r3, [r7, #12] + 8002b4c: f403 7380 and.w r3, r3, #256 @ 0x100 + 8002b50: 2b00 cmp r3, #0 + 8002b52: d00d beq.n 8002b70 { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_AWD2); - 8002ab8: 687b ldr r3, [r7, #4] - 8002aba: 6c1b ldr r3, [r3, #64] @ 0x40 - 8002abc: f443 3200 orr.w r2, r3, #131072 @ 0x20000 - 8002ac0: 687b ldr r3, [r7, #4] - 8002ac2: 641a str r2, [r3, #64] @ 0x40 + 8002b54: 687b ldr r3, [r7, #4] + 8002b56: 6c1b ldr r3, [r3, #64] @ 0x40 + 8002b58: f443 3200 orr.w r2, r3, #131072 @ 0x20000 + 8002b5c: 687b ldr r3, [r7, #4] + 8002b5e: 641a str r2, [r3, #64] @ 0x40 /* Level out of window 2 callback */ HAL_ADCEx_LevelOutOfWindow2Callback(hadc); - 8002ac4: 6878 ldr r0, [r7, #4] - 8002ac6: f000 f897 bl 8002bf8 + 8002b60: 6878 ldr r0, [r7, #4] + 8002b62: f000 f897 bl 8002c94 /* Clear ADC analog watchdog flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2); - 8002aca: 687b ldr r3, [r7, #4] - 8002acc: 681b ldr r3, [r3, #0] - 8002ace: f44f 7280 mov.w r2, #256 @ 0x100 - 8002ad2: 601a str r2, [r3, #0] + 8002b66: 687b ldr r3, [r7, #4] + 8002b68: 681b ldr r3, [r3, #0] + 8002b6a: f44f 7280 mov.w r2, #256 @ 0x100 + 8002b6e: 601a str r2, [r3, #0] } /* ========== Check analog watchdog 3 flag ========== */ if(((tmp_isr & ADC_FLAG_AWD3) == ADC_FLAG_AWD3) && ((tmp_ier & ADC_IT_AWD3) == ADC_IT_AWD3)) - 8002ad4: 693b ldr r3, [r7, #16] - 8002ad6: f403 7300 and.w r3, r3, #512 @ 0x200 - 8002ada: 2b00 cmp r3, #0 - 8002adc: d012 beq.n 8002b04 - 8002ade: 68fb ldr r3, [r7, #12] - 8002ae0: f403 7300 and.w r3, r3, #512 @ 0x200 - 8002ae4: 2b00 cmp r3, #0 - 8002ae6: d00d beq.n 8002b04 + 8002b70: 693b ldr r3, [r7, #16] + 8002b72: f403 7300 and.w r3, r3, #512 @ 0x200 + 8002b76: 2b00 cmp r3, #0 + 8002b78: d012 beq.n 8002ba0 + 8002b7a: 68fb ldr r3, [r7, #12] + 8002b7c: f403 7300 and.w r3, r3, #512 @ 0x200 + 8002b80: 2b00 cmp r3, #0 + 8002b82: d00d beq.n 8002ba0 { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_AWD3); - 8002ae8: 687b ldr r3, [r7, #4] - 8002aea: 6c1b ldr r3, [r3, #64] @ 0x40 - 8002aec: f443 2280 orr.w r2, r3, #262144 @ 0x40000 - 8002af0: 687b ldr r3, [r7, #4] - 8002af2: 641a str r2, [r3, #64] @ 0x40 + 8002b84: 687b ldr r3, [r7, #4] + 8002b86: 6c1b ldr r3, [r3, #64] @ 0x40 + 8002b88: f443 2280 orr.w r2, r3, #262144 @ 0x40000 + 8002b8c: 687b ldr r3, [r7, #4] + 8002b8e: 641a str r2, [r3, #64] @ 0x40 /* Level out of window 3 callback */ HAL_ADCEx_LevelOutOfWindow3Callback(hadc); - 8002af4: 6878 ldr r0, [r7, #4] - 8002af6: f000 f889 bl 8002c0c + 8002b90: 6878 ldr r0, [r7, #4] + 8002b92: f000 f889 bl 8002ca8 /* Clear ADC analog watchdog flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3); - 8002afa: 687b ldr r3, [r7, #4] - 8002afc: 681b ldr r3, [r3, #0] - 8002afe: f44f 7200 mov.w r2, #512 @ 0x200 - 8002b02: 601a str r2, [r3, #0] + 8002b96: 687b ldr r3, [r7, #4] + 8002b98: 681b ldr r3, [r3, #0] + 8002b9a: f44f 7200 mov.w r2, #512 @ 0x200 + 8002b9e: 601a str r2, [r3, #0] } /* ========== Check Overrun flag ========== */ if(((tmp_isr & ADC_FLAG_OVR) == ADC_FLAG_OVR) && ((tmp_ier & ADC_IT_OVR) == ADC_IT_OVR)) - 8002b04: 693b ldr r3, [r7, #16] - 8002b06: f003 0310 and.w r3, r3, #16 - 8002b0a: 2b00 cmp r3, #0 - 8002b0c: d03b beq.n 8002b86 - 8002b0e: 68fb ldr r3, [r7, #12] - 8002b10: f003 0310 and.w r3, r3, #16 - 8002b14: 2b00 cmp r3, #0 - 8002b16: d036 beq.n 8002b86 + 8002ba0: 693b ldr r3, [r7, #16] + 8002ba2: f003 0310 and.w r3, r3, #16 + 8002ba6: 2b00 cmp r3, #0 + 8002ba8: d03b beq.n 8002c22 + 8002baa: 68fb ldr r3, [r7, #12] + 8002bac: f003 0310 and.w r3, r3, #16 + 8002bb0: 2b00 cmp r3, #0 + 8002bb2: d036 beq.n 8002c22 /* overrun event is not considered as an error. */ /* (cf ref manual "Managing conversions without using the DMA and */ /* without overrun ") */ /* Exception for usage with DMA overrun event always considered as an */ /* error. */ if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) - 8002b18: 687b ldr r3, [r7, #4] - 8002b1a: 6b5b ldr r3, [r3, #52] @ 0x34 - 8002b1c: 2b01 cmp r3, #1 - 8002b1e: d102 bne.n 8002b26 + 8002bb4: 687b ldr r3, [r7, #4] + 8002bb6: 6b5b ldr r3, [r3, #52] @ 0x34 + 8002bb8: 2b01 cmp r3, #1 + 8002bba: d102 bne.n 8002bc2 { overrun_error = 1U; - 8002b20: 2301 movs r3, #1 - 8002b22: 61fb str r3, [r7, #28] - 8002b24: e019 b.n 8002b5a + 8002bbc: 2301 movs r3, #1 + 8002bbe: 61fb str r3, [r7, #28] + 8002bc0: e019 b.n 8002bf6 else { /* Pointer to the common control register to which is belonging hadc */ /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */ /* control registers) */ tmpADC_Common = ADC_COMMON_REGISTER(hadc); - 8002b26: 4b29 ldr r3, [pc, #164] @ (8002bcc ) - 8002b28: 60bb str r3, [r7, #8] + 8002bc2: 4b29 ldr r3, [pc, #164] @ (8002c68 ) + 8002bc4: 60bb str r3, [r7, #8] /* Check DMA configuration, depending on MultiMode set or not */ if (READ_BIT(tmpADC_Common->CCR, ADC_CCR_MULTI) == ADC_MODE_INDEPENDENT) - 8002b2a: 68bb ldr r3, [r7, #8] - 8002b2c: 689b ldr r3, [r3, #8] - 8002b2e: f003 031f and.w r3, r3, #31 - 8002b32: 2b00 cmp r3, #0 - 8002b34: d109 bne.n 8002b4a + 8002bc6: 68bb ldr r3, [r7, #8] + 8002bc8: 689b ldr r3, [r3, #8] + 8002bca: f003 031f and.w r3, r3, #31 + 8002bce: 2b00 cmp r3, #0 + 8002bd0: d109 bne.n 8002be6 { if (HAL_IS_BIT_SET(hadc->Instance->CFGR, ADC_CFGR_DMAEN)) - 8002b36: 687b ldr r3, [r7, #4] - 8002b38: 681b ldr r3, [r3, #0] - 8002b3a: 68db ldr r3, [r3, #12] - 8002b3c: f003 0301 and.w r3, r3, #1 - 8002b40: 2b01 cmp r3, #1 - 8002b42: d10a bne.n 8002b5a + 8002bd2: 687b ldr r3, [r7, #4] + 8002bd4: 681b ldr r3, [r3, #0] + 8002bd6: 68db ldr r3, [r3, #12] + 8002bd8: f003 0301 and.w r3, r3, #1 + 8002bdc: 2b01 cmp r3, #1 + 8002bde: d10a bne.n 8002bf6 { overrun_error = 1U; - 8002b44: 2301 movs r3, #1 - 8002b46: 61fb str r3, [r7, #28] - 8002b48: e007 b.n 8002b5a + 8002be0: 2301 movs r3, #1 + 8002be2: 61fb str r3, [r7, #28] + 8002be4: e007 b.n 8002bf6 } } else { /* MultiMode is enabled, Common Control Register MDMA bits must be checked */ if (READ_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA) != RESET) - 8002b4a: 68bb ldr r3, [r7, #8] - 8002b4c: 689b ldr r3, [r3, #8] - 8002b4e: f403 4340 and.w r3, r3, #49152 @ 0xc000 - 8002b52: 2b00 cmp r3, #0 - 8002b54: d001 beq.n 8002b5a + 8002be6: 68bb ldr r3, [r7, #8] + 8002be8: 689b ldr r3, [r3, #8] + 8002bea: f403 4340 and.w r3, r3, #49152 @ 0xc000 + 8002bee: 2b00 cmp r3, #0 + 8002bf0: d001 beq.n 8002bf6 { overrun_error = 1U; - 8002b56: 2301 movs r3, #1 - 8002b58: 61fb str r3, [r7, #28] + 8002bf2: 2301 movs r3, #1 + 8002bf4: 61fb str r3, [r7, #28] } } } if (overrun_error == 1U) - 8002b5a: 69fb ldr r3, [r7, #28] - 8002b5c: 2b01 cmp r3, #1 - 8002b5e: d10e bne.n 8002b7e + 8002bf6: 69fb ldr r3, [r7, #28] + 8002bf8: 2b01 cmp r3, #1 + 8002bfa: d10e bne.n 8002c1a { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR); - 8002b60: 687b ldr r3, [r7, #4] - 8002b62: 6c1b ldr r3, [r3, #64] @ 0x40 - 8002b64: f443 6280 orr.w r2, r3, #1024 @ 0x400 - 8002b68: 687b ldr r3, [r7, #4] - 8002b6a: 641a str r2, [r3, #64] @ 0x40 + 8002bfc: 687b ldr r3, [r7, #4] + 8002bfe: 6c1b ldr r3, [r3, #64] @ 0x40 + 8002c00: f443 6280 orr.w r2, r3, #1024 @ 0x400 + 8002c04: 687b ldr r3, [r7, #4] + 8002c06: 641a str r2, [r3, #64] @ 0x40 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); - 8002b6c: 687b ldr r3, [r7, #4] - 8002b6e: 6c5b ldr r3, [r3, #68] @ 0x44 - 8002b70: f043 0202 orr.w r2, r3, #2 - 8002b74: 687b ldr r3, [r7, #4] - 8002b76: 645a str r2, [r3, #68] @ 0x44 + 8002c08: 687b ldr r3, [r7, #4] + 8002c0a: 6c5b ldr r3, [r3, #68] @ 0x44 + 8002c0c: f043 0202 orr.w r2, r3, #2 + 8002c10: 687b ldr r3, [r7, #4] + 8002c12: 645a str r2, [r3, #68] @ 0x44 /* Error callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ErrorCallback(hadc); #else HAL_ADC_ErrorCallback(hadc); - 8002b78: 6878 ldr r0, [r7, #4] - 8002b7a: f7ff fbb9 bl 80022f0 + 8002c14: 6878 ldr r0, [r7, #4] + 8002c16: f7ff fbb9 bl 800238c #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } /* Clear the Overrun flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); - 8002b7e: 687b ldr r3, [r7, #4] - 8002b80: 681b ldr r3, [r3, #0] - 8002b82: 2210 movs r2, #16 - 8002b84: 601a str r2, [r3, #0] + 8002c1a: 687b ldr r3, [r7, #4] + 8002c1c: 681b ldr r3, [r3, #0] + 8002c1e: 2210 movs r2, #16 + 8002c20: 601a str r2, [r3, #0] } /* ========== Check Injected context queue overflow flag ========== */ if(((tmp_isr & ADC_FLAG_JQOVF) == ADC_FLAG_JQOVF) && ((tmp_ier & ADC_IT_JQOVF) == ADC_IT_JQOVF)) - 8002b86: 693b ldr r3, [r7, #16] - 8002b88: f403 6380 and.w r3, r3, #1024 @ 0x400 - 8002b8c: 2b00 cmp r3, #0 - 8002b8e: d018 beq.n 8002bc2 - 8002b90: 68fb ldr r3, [r7, #12] - 8002b92: f403 6380 and.w r3, r3, #1024 @ 0x400 - 8002b96: 2b00 cmp r3, #0 - 8002b98: d013 beq.n 8002bc2 + 8002c22: 693b ldr r3, [r7, #16] + 8002c24: f403 6380 and.w r3, r3, #1024 @ 0x400 + 8002c28: 2b00 cmp r3, #0 + 8002c2a: d018 beq.n 8002c5e + 8002c2c: 68fb ldr r3, [r7, #12] + 8002c2e: f403 6380 and.w r3, r3, #1024 @ 0x400 + 8002c32: 2b00 cmp r3, #0 + 8002c34: d013 beq.n 8002c5e { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF); - 8002b9a: 687b ldr r3, [r7, #4] - 8002b9c: 6c1b ldr r3, [r3, #64] @ 0x40 - 8002b9e: f443 4280 orr.w r2, r3, #16384 @ 0x4000 - 8002ba2: 687b ldr r3, [r7, #4] - 8002ba4: 641a str r2, [r3, #64] @ 0x40 + 8002c36: 687b ldr r3, [r7, #4] + 8002c38: 6c1b ldr r3, [r3, #64] @ 0x40 + 8002c3a: f443 4280 orr.w r2, r3, #16384 @ 0x4000 + 8002c3e: 687b ldr r3, [r7, #4] + 8002c40: 641a str r2, [r3, #64] @ 0x40 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF); - 8002ba6: 687b ldr r3, [r7, #4] - 8002ba8: 6c5b ldr r3, [r3, #68] @ 0x44 - 8002baa: f043 0208 orr.w r2, r3, #8 - 8002bae: 687b ldr r3, [r7, #4] - 8002bb0: 645a str r2, [r3, #68] @ 0x44 + 8002c42: 687b ldr r3, [r7, #4] + 8002c44: 6c5b ldr r3, [r3, #68] @ 0x44 + 8002c46: f043 0208 orr.w r2, r3, #8 + 8002c4a: 687b ldr r3, [r7, #4] + 8002c4c: 645a str r2, [r3, #68] @ 0x44 /* Clear the Injected context queue overflow flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF); - 8002bb2: 687b ldr r3, [r7, #4] - 8002bb4: 681b ldr r3, [r3, #0] - 8002bb6: f44f 6280 mov.w r2, #1024 @ 0x400 - 8002bba: 601a str r2, [r3, #0] + 8002c4e: 687b ldr r3, [r7, #4] + 8002c50: 681b ldr r3, [r3, #0] + 8002c52: f44f 6280 mov.w r2, #1024 @ 0x400 + 8002c56: 601a str r2, [r3, #0] /* Error callback */ HAL_ADCEx_InjectedQueueOverflowCallback(hadc); - 8002bbc: 6878 ldr r0, [r7, #4] - 8002bbe: f000 f811 bl 8002be4 + 8002c58: 6878 ldr r0, [r7, #4] + 8002c5a: f000 f811 bl 8002c80 } } - 8002bc2: bf00 nop - 8002bc4: 3720 adds r7, #32 - 8002bc6: 46bd mov sp, r7 - 8002bc8: bd80 pop {r7, pc} - 8002bca: bf00 nop - 8002bcc: 50000300 .word 0x50000300 + 8002c5e: bf00 nop + 8002c60: 3720 adds r7, #32 + 8002c62: 46bd mov sp, r7 + 8002c64: bd80 pop {r7, pc} + 8002c66: bf00 nop + 8002c68: 50000300 .word 0x50000300 -08002bd0 : +08002c6c : * @brief Injected conversion complete callback in non blocking mode * @param hadc ADC handle * @retval None */ __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc) { - 8002bd0: b480 push {r7} - 8002bd2: b083 sub sp, #12 - 8002bd4: af00 add r7, sp, #0 - 8002bd6: 6078 str r0, [r7, #4] + 8002c6c: b480 push {r7} + 8002c6e: b083 sub sp, #12 + 8002c70: af00 add r7, sp, #0 + 8002c72: 6078 str r0, [r7, #4] UNUSED(hadc); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_ADCEx_InjectedConvCpltCallback could be implemented in the user file */ } - 8002bd8: bf00 nop - 8002bda: 370c adds r7, #12 - 8002bdc: 46bd mov sp, r7 - 8002bde: f85d 7b04 ldr.w r7, [sp], #4 - 8002be2: 4770 bx lr + 8002c74: bf00 nop + 8002c76: 370c adds r7, #12 + 8002c78: 46bd mov sp, r7 + 8002c7a: f85d 7b04 ldr.w r7, [sp], #4 + 8002c7e: 4770 bx lr -08002be4 : +08002c80 : contexts). * @param hadc ADC handle * @retval None */ __weak void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef* hadc) { - 8002be4: b480 push {r7} - 8002be6: b083 sub sp, #12 - 8002be8: af00 add r7, sp, #0 - 8002bea: 6078 str r0, [r7, #4] + 8002c80: b480 push {r7} + 8002c82: b083 sub sp, #12 + 8002c84: af00 add r7, sp, #0 + 8002c86: 6078 str r0, [r7, #4] /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADCEx_InjectedQueueOverflowCallback must be implemented in the user file. */ } - 8002bec: bf00 nop - 8002bee: 370c adds r7, #12 - 8002bf0: 46bd mov sp, r7 - 8002bf2: f85d 7b04 ldr.w r7, [sp], #4 - 8002bf6: 4770 bx lr + 8002c88: bf00 nop + 8002c8a: 370c adds r7, #12 + 8002c8c: 46bd mov sp, r7 + 8002c8e: f85d 7b04 ldr.w r7, [sp], #4 + 8002c92: 4770 bx lr -08002bf8 : +08002c94 : * @brief Analog watchdog 2 callback in non blocking mode. * @param hadc ADC handle * @retval None */ __weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef* hadc) { - 8002bf8: b480 push {r7} - 8002bfa: b083 sub sp, #12 - 8002bfc: af00 add r7, sp, #0 - 8002bfe: 6078 str r0, [r7, #4] + 8002c94: b480 push {r7} + 8002c96: b083 sub sp, #12 + 8002c98: af00 add r7, sp, #0 + 8002c9a: 6078 str r0, [r7, #4] UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_LevelOoutOfWindow2Callback must be implemented in the user file. */ } - 8002c00: bf00 nop - 8002c02: 370c adds r7, #12 - 8002c04: 46bd mov sp, r7 - 8002c06: f85d 7b04 ldr.w r7, [sp], #4 - 8002c0a: 4770 bx lr + 8002c9c: bf00 nop + 8002c9e: 370c adds r7, #12 + 8002ca0: 46bd mov sp, r7 + 8002ca2: f85d 7b04 ldr.w r7, [sp], #4 + 8002ca6: 4770 bx lr -08002c0c : +08002ca8 : * @brief Analog watchdog 3 callback in non blocking mode. * @param hadc ADC handle * @retval None */ __weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef* hadc) { - 8002c0c: b480 push {r7} - 8002c0e: b083 sub sp, #12 - 8002c10: af00 add r7, sp, #0 - 8002c12: 6078 str r0, [r7, #4] + 8002ca8: b480 push {r7} + 8002caa: b083 sub sp, #12 + 8002cac: af00 add r7, sp, #0 + 8002cae: 6078 str r0, [r7, #4] UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_LevelOoutOfWindow3Callback must be implemented in the user file. */ } - 8002c14: bf00 nop - 8002c16: 370c adds r7, #12 - 8002c18: 46bd mov sp, r7 - 8002c1a: f85d 7b04 ldr.w r7, [sp], #4 - 8002c1e: 4770 bx lr + 8002cb0: bf00 nop + 8002cb2: 370c adds r7, #12 + 8002cb4: 46bd mov sp, r7 + 8002cb6: f85d 7b04 ldr.w r7, [sp], #4 + 8002cba: 4770 bx lr -08002c20 : +08002cbc : * @param hadc ADC handle * @param sConfig Structure ADC channel for regular group. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) { - 8002c20: b480 push {r7} - 8002c22: b09b sub sp, #108 @ 0x6c - 8002c24: af00 add r7, sp, #0 - 8002c26: 6078 str r0, [r7, #4] - 8002c28: 6039 str r1, [r7, #0] + 8002cbc: b480 push {r7} + 8002cbe: b09b sub sp, #108 @ 0x6c + 8002cc0: af00 add r7, sp, #0 + 8002cc2: 6078 str r0, [r7, #4] + 8002cc4: 6039 str r1, [r7, #0] HAL_StatusTypeDef tmp_hal_status = HAL_OK; - 8002c2a: 2300 movs r3, #0 - 8002c2c: f887 3067 strb.w r3, [r7, #103] @ 0x67 + 8002cc6: 2300 movs r3, #0 + 8002cc8: f887 3067 strb.w r3, [r7, #103] @ 0x67 ADC_Common_TypeDef *tmpADC_Common; ADC_HandleTypeDef tmphadcSharingSameCommonRegister; uint32_t tmpOffsetShifted; __IO uint32_t wait_loop_index = 0U; - 8002c30: 2300 movs r3, #0 - 8002c32: 60bb str r3, [r7, #8] + 8002ccc: 2300 movs r3, #0 + 8002cce: 60bb str r3, [r7, #8] { assert_param(IS_ADC_DIFF_CHANNEL(sConfig->Channel)); } /* Process locked */ __HAL_LOCK(hadc); - 8002c34: 687b ldr r3, [r7, #4] - 8002c36: f893 303c ldrb.w r3, [r3, #60] @ 0x3c - 8002c3a: 2b01 cmp r3, #1 - 8002c3c: d101 bne.n 8002c42 - 8002c3e: 2302 movs r3, #2 - 8002c40: e2a1 b.n 8003186 - 8002c42: 687b ldr r3, [r7, #4] - 8002c44: 2201 movs r2, #1 - 8002c46: f883 203c strb.w r2, [r3, #60] @ 0x3c + 8002cd0: 687b ldr r3, [r7, #4] + 8002cd2: f893 303c ldrb.w r3, [r3, #60] @ 0x3c + 8002cd6: 2b01 cmp r3, #1 + 8002cd8: d101 bne.n 8002cde + 8002cda: 2302 movs r3, #2 + 8002cdc: e2a1 b.n 8003222 + 8002cde: 687b ldr r3, [r7, #4] + 8002ce0: 2201 movs r2, #1 + 8002ce2: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - Channel number */ /* - Channel rank */ if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) - 8002c4a: 687b ldr r3, [r7, #4] - 8002c4c: 681b ldr r3, [r3, #0] - 8002c4e: 689b ldr r3, [r3, #8] - 8002c50: f003 0304 and.w r3, r3, #4 - 8002c54: 2b00 cmp r3, #0 - 8002c56: f040 8285 bne.w 8003164 + 8002ce6: 687b ldr r3, [r7, #4] + 8002ce8: 681b ldr r3, [r3, #0] + 8002cea: 689b ldr r3, [r3, #8] + 8002cec: f003 0304 and.w r3, r3, #4 + 8002cf0: 2b00 cmp r3, #0 + 8002cf2: f040 8285 bne.w 8003200 { /* Regular sequence configuration */ /* For Rank 1 to 4U */ if (sConfig->Rank < 5U) - 8002c5a: 683b ldr r3, [r7, #0] - 8002c5c: 685b ldr r3, [r3, #4] - 8002c5e: 2b04 cmp r3, #4 - 8002c60: d81c bhi.n 8002c9c + 8002cf6: 683b ldr r3, [r7, #0] + 8002cf8: 685b ldr r3, [r3, #4] + 8002cfa: 2b04 cmp r3, #4 + 8002cfc: d81c bhi.n 8002d38 { MODIFY_REG(hadc->Instance->SQR1, - 8002c62: 687b ldr r3, [r7, #4] - 8002c64: 681b ldr r3, [r3, #0] - 8002c66: 6b19 ldr r1, [r3, #48] @ 0x30 - 8002c68: 683b ldr r3, [r7, #0] - 8002c6a: 685a ldr r2, [r3, #4] - 8002c6c: 4613 mov r3, r2 - 8002c6e: 005b lsls r3, r3, #1 - 8002c70: 4413 add r3, r2 - 8002c72: 005b lsls r3, r3, #1 - 8002c74: 461a mov r2, r3 - 8002c76: 231f movs r3, #31 - 8002c78: 4093 lsls r3, r2 - 8002c7a: 43db mvns r3, r3 - 8002c7c: 4019 ands r1, r3 - 8002c7e: 683b ldr r3, [r7, #0] - 8002c80: 6818 ldr r0, [r3, #0] - 8002c82: 683b ldr r3, [r7, #0] - 8002c84: 685a ldr r2, [r3, #4] - 8002c86: 4613 mov r3, r2 - 8002c88: 005b lsls r3, r3, #1 - 8002c8a: 4413 add r3, r2 - 8002c8c: 005b lsls r3, r3, #1 - 8002c8e: fa00 f203 lsl.w r2, r0, r3 - 8002c92: 687b ldr r3, [r7, #4] - 8002c94: 681b ldr r3, [r3, #0] - 8002c96: 430a orrs r2, r1 - 8002c98: 631a str r2, [r3, #48] @ 0x30 - 8002c9a: e063 b.n 8002d64 + 8002cfe: 687b ldr r3, [r7, #4] + 8002d00: 681b ldr r3, [r3, #0] + 8002d02: 6b19 ldr r1, [r3, #48] @ 0x30 + 8002d04: 683b ldr r3, [r7, #0] + 8002d06: 685a ldr r2, [r3, #4] + 8002d08: 4613 mov r3, r2 + 8002d0a: 005b lsls r3, r3, #1 + 8002d0c: 4413 add r3, r2 + 8002d0e: 005b lsls r3, r3, #1 + 8002d10: 461a mov r2, r3 + 8002d12: 231f movs r3, #31 + 8002d14: 4093 lsls r3, r2 + 8002d16: 43db mvns r3, r3 + 8002d18: 4019 ands r1, r3 + 8002d1a: 683b ldr r3, [r7, #0] + 8002d1c: 6818 ldr r0, [r3, #0] + 8002d1e: 683b ldr r3, [r7, #0] + 8002d20: 685a ldr r2, [r3, #4] + 8002d22: 4613 mov r3, r2 + 8002d24: 005b lsls r3, r3, #1 + 8002d26: 4413 add r3, r2 + 8002d28: 005b lsls r3, r3, #1 + 8002d2a: fa00 f203 lsl.w r2, r0, r3 + 8002d2e: 687b ldr r3, [r7, #4] + 8002d30: 681b ldr r3, [r3, #0] + 8002d32: 430a orrs r2, r1 + 8002d34: 631a str r2, [r3, #48] @ 0x30 + 8002d36: e063 b.n 8002e00 ADC_SQR1_RK(ADC_SQR2_SQ5, sConfig->Rank) , ADC_SQR1_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 5 to 9U */ else if (sConfig->Rank < 10U) - 8002c9c: 683b ldr r3, [r7, #0] - 8002c9e: 685b ldr r3, [r3, #4] - 8002ca0: 2b09 cmp r3, #9 - 8002ca2: d81e bhi.n 8002ce2 + 8002d38: 683b ldr r3, [r7, #0] + 8002d3a: 685b ldr r3, [r3, #4] + 8002d3c: 2b09 cmp r3, #9 + 8002d3e: d81e bhi.n 8002d7e { MODIFY_REG(hadc->Instance->SQR2, - 8002ca4: 687b ldr r3, [r7, #4] - 8002ca6: 681b ldr r3, [r3, #0] - 8002ca8: 6b59 ldr r1, [r3, #52] @ 0x34 - 8002caa: 683b ldr r3, [r7, #0] - 8002cac: 685a ldr r2, [r3, #4] - 8002cae: 4613 mov r3, r2 - 8002cb0: 005b lsls r3, r3, #1 - 8002cb2: 4413 add r3, r2 - 8002cb4: 005b lsls r3, r3, #1 - 8002cb6: 3b1e subs r3, #30 - 8002cb8: 221f movs r2, #31 - 8002cba: fa02 f303 lsl.w r3, r2, r3 - 8002cbe: 43db mvns r3, r3 - 8002cc0: 4019 ands r1, r3 - 8002cc2: 683b ldr r3, [r7, #0] - 8002cc4: 6818 ldr r0, [r3, #0] - 8002cc6: 683b ldr r3, [r7, #0] - 8002cc8: 685a ldr r2, [r3, #4] - 8002cca: 4613 mov r3, r2 - 8002ccc: 005b lsls r3, r3, #1 - 8002cce: 4413 add r3, r2 - 8002cd0: 005b lsls r3, r3, #1 - 8002cd2: 3b1e subs r3, #30 - 8002cd4: fa00 f203 lsl.w r2, r0, r3 - 8002cd8: 687b ldr r3, [r7, #4] - 8002cda: 681b ldr r3, [r3, #0] - 8002cdc: 430a orrs r2, r1 - 8002cde: 635a str r2, [r3, #52] @ 0x34 - 8002ce0: e040 b.n 8002d64 + 8002d40: 687b ldr r3, [r7, #4] + 8002d42: 681b ldr r3, [r3, #0] + 8002d44: 6b59 ldr r1, [r3, #52] @ 0x34 + 8002d46: 683b ldr r3, [r7, #0] + 8002d48: 685a ldr r2, [r3, #4] + 8002d4a: 4613 mov r3, r2 + 8002d4c: 005b lsls r3, r3, #1 + 8002d4e: 4413 add r3, r2 + 8002d50: 005b lsls r3, r3, #1 + 8002d52: 3b1e subs r3, #30 + 8002d54: 221f movs r2, #31 + 8002d56: fa02 f303 lsl.w r3, r2, r3 + 8002d5a: 43db mvns r3, r3 + 8002d5c: 4019 ands r1, r3 + 8002d5e: 683b ldr r3, [r7, #0] + 8002d60: 6818 ldr r0, [r3, #0] + 8002d62: 683b ldr r3, [r7, #0] + 8002d64: 685a ldr r2, [r3, #4] + 8002d66: 4613 mov r3, r2 + 8002d68: 005b lsls r3, r3, #1 + 8002d6a: 4413 add r3, r2 + 8002d6c: 005b lsls r3, r3, #1 + 8002d6e: 3b1e subs r3, #30 + 8002d70: fa00 f203 lsl.w r2, r0, r3 + 8002d74: 687b ldr r3, [r7, #4] + 8002d76: 681b ldr r3, [r3, #0] + 8002d78: 430a orrs r2, r1 + 8002d7a: 635a str r2, [r3, #52] @ 0x34 + 8002d7c: e040 b.n 8002e00 ADC_SQR2_RK(ADC_SQR2_SQ5, sConfig->Rank) , ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 10 to 14U */ else if (sConfig->Rank < 15U) - 8002ce2: 683b ldr r3, [r7, #0] - 8002ce4: 685b ldr r3, [r3, #4] - 8002ce6: 2b0e cmp r3, #14 - 8002ce8: d81e bhi.n 8002d28 + 8002d7e: 683b ldr r3, [r7, #0] + 8002d80: 685b ldr r3, [r3, #4] + 8002d82: 2b0e cmp r3, #14 + 8002d84: d81e bhi.n 8002dc4 { MODIFY_REG(hadc->Instance->SQR3 , - 8002cea: 687b ldr r3, [r7, #4] - 8002cec: 681b ldr r3, [r3, #0] - 8002cee: 6b99 ldr r1, [r3, #56] @ 0x38 - 8002cf0: 683b ldr r3, [r7, #0] - 8002cf2: 685a ldr r2, [r3, #4] - 8002cf4: 4613 mov r3, r2 - 8002cf6: 005b lsls r3, r3, #1 - 8002cf8: 4413 add r3, r2 - 8002cfa: 005b lsls r3, r3, #1 - 8002cfc: 3b3c subs r3, #60 @ 0x3c - 8002cfe: 221f movs r2, #31 - 8002d00: fa02 f303 lsl.w r3, r2, r3 - 8002d04: 43db mvns r3, r3 - 8002d06: 4019 ands r1, r3 - 8002d08: 683b ldr r3, [r7, #0] - 8002d0a: 6818 ldr r0, [r3, #0] - 8002d0c: 683b ldr r3, [r7, #0] - 8002d0e: 685a ldr r2, [r3, #4] - 8002d10: 4613 mov r3, r2 - 8002d12: 005b lsls r3, r3, #1 - 8002d14: 4413 add r3, r2 - 8002d16: 005b lsls r3, r3, #1 - 8002d18: 3b3c subs r3, #60 @ 0x3c - 8002d1a: fa00 f203 lsl.w r2, r0, r3 - 8002d1e: 687b ldr r3, [r7, #4] - 8002d20: 681b ldr r3, [r3, #0] - 8002d22: 430a orrs r2, r1 - 8002d24: 639a str r2, [r3, #56] @ 0x38 - 8002d26: e01d b.n 8002d64 + 8002d86: 687b ldr r3, [r7, #4] + 8002d88: 681b ldr r3, [r3, #0] + 8002d8a: 6b99 ldr r1, [r3, #56] @ 0x38 + 8002d8c: 683b ldr r3, [r7, #0] + 8002d8e: 685a ldr r2, [r3, #4] + 8002d90: 4613 mov r3, r2 + 8002d92: 005b lsls r3, r3, #1 + 8002d94: 4413 add r3, r2 + 8002d96: 005b lsls r3, r3, #1 + 8002d98: 3b3c subs r3, #60 @ 0x3c + 8002d9a: 221f movs r2, #31 + 8002d9c: fa02 f303 lsl.w r3, r2, r3 + 8002da0: 43db mvns r3, r3 + 8002da2: 4019 ands r1, r3 + 8002da4: 683b ldr r3, [r7, #0] + 8002da6: 6818 ldr r0, [r3, #0] + 8002da8: 683b ldr r3, [r7, #0] + 8002daa: 685a ldr r2, [r3, #4] + 8002dac: 4613 mov r3, r2 + 8002dae: 005b lsls r3, r3, #1 + 8002db0: 4413 add r3, r2 + 8002db2: 005b lsls r3, r3, #1 + 8002db4: 3b3c subs r3, #60 @ 0x3c + 8002db6: fa00 f203 lsl.w r2, r0, r3 + 8002dba: 687b ldr r3, [r7, #4] + 8002dbc: 681b ldr r3, [r3, #0] + 8002dbe: 430a orrs r2, r1 + 8002dc0: 639a str r2, [r3, #56] @ 0x38 + 8002dc2: e01d b.n 8002e00 ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 15 to 16U */ else { MODIFY_REG(hadc->Instance->SQR4 , - 8002d28: 687b ldr r3, [r7, #4] - 8002d2a: 681b ldr r3, [r3, #0] - 8002d2c: 6bd9 ldr r1, [r3, #60] @ 0x3c - 8002d2e: 683b ldr r3, [r7, #0] - 8002d30: 685a ldr r2, [r3, #4] - 8002d32: 4613 mov r3, r2 - 8002d34: 005b lsls r3, r3, #1 - 8002d36: 4413 add r3, r2 - 8002d38: 005b lsls r3, r3, #1 - 8002d3a: 3b5a subs r3, #90 @ 0x5a - 8002d3c: 221f movs r2, #31 - 8002d3e: fa02 f303 lsl.w r3, r2, r3 - 8002d42: 43db mvns r3, r3 - 8002d44: 4019 ands r1, r3 - 8002d46: 683b ldr r3, [r7, #0] - 8002d48: 6818 ldr r0, [r3, #0] - 8002d4a: 683b ldr r3, [r7, #0] - 8002d4c: 685a ldr r2, [r3, #4] - 8002d4e: 4613 mov r3, r2 - 8002d50: 005b lsls r3, r3, #1 - 8002d52: 4413 add r3, r2 - 8002d54: 005b lsls r3, r3, #1 - 8002d56: 3b5a subs r3, #90 @ 0x5a - 8002d58: fa00 f203 lsl.w r2, r0, r3 - 8002d5c: 687b ldr r3, [r7, #4] - 8002d5e: 681b ldr r3, [r3, #0] - 8002d60: 430a orrs r2, r1 - 8002d62: 63da str r2, [r3, #60] @ 0x3c + 8002dc4: 687b ldr r3, [r7, #4] + 8002dc6: 681b ldr r3, [r3, #0] + 8002dc8: 6bd9 ldr r1, [r3, #60] @ 0x3c + 8002dca: 683b ldr r3, [r7, #0] + 8002dcc: 685a ldr r2, [r3, #4] + 8002dce: 4613 mov r3, r2 + 8002dd0: 005b lsls r3, r3, #1 + 8002dd2: 4413 add r3, r2 + 8002dd4: 005b lsls r3, r3, #1 + 8002dd6: 3b5a subs r3, #90 @ 0x5a + 8002dd8: 221f movs r2, #31 + 8002dda: fa02 f303 lsl.w r3, r2, r3 + 8002dde: 43db mvns r3, r3 + 8002de0: 4019 ands r1, r3 + 8002de2: 683b ldr r3, [r7, #0] + 8002de4: 6818 ldr r0, [r3, #0] + 8002de6: 683b ldr r3, [r7, #0] + 8002de8: 685a ldr r2, [r3, #4] + 8002dea: 4613 mov r3, r2 + 8002dec: 005b lsls r3, r3, #1 + 8002dee: 4413 add r3, r2 + 8002df0: 005b lsls r3, r3, #1 + 8002df2: 3b5a subs r3, #90 @ 0x5a + 8002df4: fa00 f203 lsl.w r2, r0, r3 + 8002df8: 687b ldr r3, [r7, #4] + 8002dfa: 681b ldr r3, [r3, #0] + 8002dfc: 430a orrs r2, r1 + 8002dfe: 63da str r2, [r3, #60] @ 0x3c /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - Channel sampling time */ /* - Channel offset */ if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) - 8002d64: 687b ldr r3, [r7, #4] - 8002d66: 681b ldr r3, [r3, #0] - 8002d68: 689b ldr r3, [r3, #8] - 8002d6a: f003 030c and.w r3, r3, #12 - 8002d6e: 2b00 cmp r3, #0 - 8002d70: f040 80e5 bne.w 8002f3e + 8002e00: 687b ldr r3, [r7, #4] + 8002e02: 681b ldr r3, [r3, #0] + 8002e04: 689b ldr r3, [r3, #8] + 8002e06: f003 030c and.w r3, r3, #12 + 8002e0a: 2b00 cmp r3, #0 + 8002e0c: f040 80e5 bne.w 8002fda { /* Channel sampling time configuration */ /* For channels 10 to 18U */ if (sConfig->Channel >= ADC_CHANNEL_10) - 8002d74: 683b ldr r3, [r7, #0] - 8002d76: 681b ldr r3, [r3, #0] - 8002d78: 2b09 cmp r3, #9 - 8002d7a: d91c bls.n 8002db6 + 8002e10: 683b ldr r3, [r7, #0] + 8002e12: 681b ldr r3, [r3, #0] + 8002e14: 2b09 cmp r3, #9 + 8002e16: d91c bls.n 8002e52 { MODIFY_REG(hadc->Instance->SMPR2 , - 8002d7c: 687b ldr r3, [r7, #4] - 8002d7e: 681b ldr r3, [r3, #0] - 8002d80: 6999 ldr r1, [r3, #24] - 8002d82: 683b ldr r3, [r7, #0] - 8002d84: 681a ldr r2, [r3, #0] - 8002d86: 4613 mov r3, r2 - 8002d88: 005b lsls r3, r3, #1 - 8002d8a: 4413 add r3, r2 - 8002d8c: 3b1e subs r3, #30 - 8002d8e: 2207 movs r2, #7 - 8002d90: fa02 f303 lsl.w r3, r2, r3 - 8002d94: 43db mvns r3, r3 - 8002d96: 4019 ands r1, r3 - 8002d98: 683b ldr r3, [r7, #0] - 8002d9a: 6898 ldr r0, [r3, #8] - 8002d9c: 683b ldr r3, [r7, #0] - 8002d9e: 681a ldr r2, [r3, #0] - 8002da0: 4613 mov r3, r2 - 8002da2: 005b lsls r3, r3, #1 - 8002da4: 4413 add r3, r2 - 8002da6: 3b1e subs r3, #30 - 8002da8: fa00 f203 lsl.w r2, r0, r3 - 8002dac: 687b ldr r3, [r7, #4] - 8002dae: 681b ldr r3, [r3, #0] - 8002db0: 430a orrs r2, r1 - 8002db2: 619a str r2, [r3, #24] - 8002db4: e019 b.n 8002dea + 8002e18: 687b ldr r3, [r7, #4] + 8002e1a: 681b ldr r3, [r3, #0] + 8002e1c: 6999 ldr r1, [r3, #24] + 8002e1e: 683b ldr r3, [r7, #0] + 8002e20: 681a ldr r2, [r3, #0] + 8002e22: 4613 mov r3, r2 + 8002e24: 005b lsls r3, r3, #1 + 8002e26: 4413 add r3, r2 + 8002e28: 3b1e subs r3, #30 + 8002e2a: 2207 movs r2, #7 + 8002e2c: fa02 f303 lsl.w r3, r2, r3 + 8002e30: 43db mvns r3, r3 + 8002e32: 4019 ands r1, r3 + 8002e34: 683b ldr r3, [r7, #0] + 8002e36: 6898 ldr r0, [r3, #8] + 8002e38: 683b ldr r3, [r7, #0] + 8002e3a: 681a ldr r2, [r3, #0] + 8002e3c: 4613 mov r3, r2 + 8002e3e: 005b lsls r3, r3, #1 + 8002e40: 4413 add r3, r2 + 8002e42: 3b1e subs r3, #30 + 8002e44: fa00 f203 lsl.w r2, r0, r3 + 8002e48: 687b ldr r3, [r7, #4] + 8002e4a: 681b ldr r3, [r3, #0] + 8002e4c: 430a orrs r2, r1 + 8002e4e: 619a str r2, [r3, #24] + 8002e50: e019 b.n 8002e86 ADC_SMPR2(ADC_SMPR2_SMP10, sConfig->Channel) , ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) ); } else /* For channels 1 to 9U */ { MODIFY_REG(hadc->Instance->SMPR1 , - 8002db6: 687b ldr r3, [r7, #4] - 8002db8: 681b ldr r3, [r3, #0] - 8002dba: 6959 ldr r1, [r3, #20] - 8002dbc: 683b ldr r3, [r7, #0] - 8002dbe: 681a ldr r2, [r3, #0] - 8002dc0: 4613 mov r3, r2 - 8002dc2: 005b lsls r3, r3, #1 - 8002dc4: 4413 add r3, r2 - 8002dc6: 2207 movs r2, #7 - 8002dc8: fa02 f303 lsl.w r3, r2, r3 - 8002dcc: 43db mvns r3, r3 - 8002dce: 4019 ands r1, r3 - 8002dd0: 683b ldr r3, [r7, #0] - 8002dd2: 6898 ldr r0, [r3, #8] - 8002dd4: 683b ldr r3, [r7, #0] - 8002dd6: 681a ldr r2, [r3, #0] - 8002dd8: 4613 mov r3, r2 - 8002dda: 005b lsls r3, r3, #1 - 8002ddc: 4413 add r3, r2 - 8002dde: fa00 f203 lsl.w r2, r0, r3 - 8002de2: 687b ldr r3, [r7, #4] - 8002de4: 681b ldr r3, [r3, #0] - 8002de6: 430a orrs r2, r1 - 8002de8: 615a str r2, [r3, #20] + 8002e52: 687b ldr r3, [r7, #4] + 8002e54: 681b ldr r3, [r3, #0] + 8002e56: 6959 ldr r1, [r3, #20] + 8002e58: 683b ldr r3, [r7, #0] + 8002e5a: 681a ldr r2, [r3, #0] + 8002e5c: 4613 mov r3, r2 + 8002e5e: 005b lsls r3, r3, #1 + 8002e60: 4413 add r3, r2 + 8002e62: 2207 movs r2, #7 + 8002e64: fa02 f303 lsl.w r3, r2, r3 + 8002e68: 43db mvns r3, r3 + 8002e6a: 4019 ands r1, r3 + 8002e6c: 683b ldr r3, [r7, #0] + 8002e6e: 6898 ldr r0, [r3, #8] + 8002e70: 683b ldr r3, [r7, #0] + 8002e72: 681a ldr r2, [r3, #0] + 8002e74: 4613 mov r3, r2 + 8002e76: 005b lsls r3, r3, #1 + 8002e78: 4413 add r3, r2 + 8002e7a: fa00 f203 lsl.w r2, r0, r3 + 8002e7e: 687b ldr r3, [r7, #4] + 8002e80: 681b ldr r3, [r3, #0] + 8002e82: 430a orrs r2, r1 + 8002e84: 615a str r2, [r3, #20] /* Configure the offset: offset enable/disable, channel, offset value */ /* Shift the offset in function of the selected ADC resolution. */ /* Offset has to be left-aligned on bit 11U, the LSB (right bits) are set */ /* to 0. */ tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfig->Offset); - 8002dea: 683b ldr r3, [r7, #0] - 8002dec: 695a ldr r2, [r3, #20] - 8002dee: 687b ldr r3, [r7, #4] - 8002df0: 681b ldr r3, [r3, #0] - 8002df2: 68db ldr r3, [r3, #12] - 8002df4: 08db lsrs r3, r3, #3 - 8002df6: f003 0303 and.w r3, r3, #3 - 8002dfa: 005b lsls r3, r3, #1 - 8002dfc: fa02 f303 lsl.w r3, r2, r3 - 8002e00: 663b str r3, [r7, #96] @ 0x60 + 8002e86: 683b ldr r3, [r7, #0] + 8002e88: 695a ldr r2, [r3, #20] + 8002e8a: 687b ldr r3, [r7, #4] + 8002e8c: 681b ldr r3, [r3, #0] + 8002e8e: 68db ldr r3, [r3, #12] + 8002e90: 08db lsrs r3, r3, #3 + 8002e92: f003 0303 and.w r3, r3, #3 + 8002e96: 005b lsls r3, r3, #1 + 8002e98: fa02 f303 lsl.w r3, r2, r3 + 8002e9c: 663b str r3, [r7, #96] @ 0x60 /* Configure the selected offset register: */ /* - Enable offset */ /* - Set channel number */ /* - Set offset value */ switch (sConfig->OffsetNumber) - 8002e02: 683b ldr r3, [r7, #0] - 8002e04: 691b ldr r3, [r3, #16] - 8002e06: 3b01 subs r3, #1 - 8002e08: 2b03 cmp r3, #3 - 8002e0a: d84f bhi.n 8002eac - 8002e0c: a201 add r2, pc, #4 @ (adr r2, 8002e14 ) - 8002e0e: f852 f023 ldr.w pc, [r2, r3, lsl #2] - 8002e12: bf00 nop - 8002e14: 08002e25 .word 0x08002e25 - 8002e18: 08002e47 .word 0x08002e47 - 8002e1c: 08002e69 .word 0x08002e69 - 8002e20: 08002e8b .word 0x08002e8b + 8002e9e: 683b ldr r3, [r7, #0] + 8002ea0: 691b ldr r3, [r3, #16] + 8002ea2: 3b01 subs r3, #1 + 8002ea4: 2b03 cmp r3, #3 + 8002ea6: d84f bhi.n 8002f48 + 8002ea8: a201 add r2, pc, #4 @ (adr r2, 8002eb0 ) + 8002eaa: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8002eae: bf00 nop + 8002eb0: 08002ec1 .word 0x08002ec1 + 8002eb4: 08002ee3 .word 0x08002ee3 + 8002eb8: 08002f05 .word 0x08002f05 + 8002ebc: 08002f27 .word 0x08002f27 { case ADC_OFFSET_1: /* Configure offset register 1U */ MODIFY_REG(hadc->Instance->OFR1 , - 8002e24: 687b ldr r3, [r7, #4] - 8002e26: 681b ldr r3, [r3, #0] - 8002e28: 6e1a ldr r2, [r3, #96] @ 0x60 - 8002e2a: 4b9c ldr r3, [pc, #624] @ (800309c ) - 8002e2c: 4013 ands r3, r2 - 8002e2e: 683a ldr r2, [r7, #0] - 8002e30: 6812 ldr r2, [r2, #0] - 8002e32: 0691 lsls r1, r2, #26 - 8002e34: 6e3a ldr r2, [r7, #96] @ 0x60 - 8002e36: 430a orrs r2, r1 - 8002e38: 431a orrs r2, r3 - 8002e3a: 687b ldr r3, [r7, #4] - 8002e3c: 681b ldr r3, [r3, #0] - 8002e3e: f042 4200 orr.w r2, r2, #2147483648 @ 0x80000000 - 8002e42: 661a str r2, [r3, #96] @ 0x60 + 8002ec0: 687b ldr r3, [r7, #4] + 8002ec2: 681b ldr r3, [r3, #0] + 8002ec4: 6e1a ldr r2, [r3, #96] @ 0x60 + 8002ec6: 4b9c ldr r3, [pc, #624] @ (8003138 ) + 8002ec8: 4013 ands r3, r2 + 8002eca: 683a ldr r2, [r7, #0] + 8002ecc: 6812 ldr r2, [r2, #0] + 8002ece: 0691 lsls r1, r2, #26 + 8002ed0: 6e3a ldr r2, [r7, #96] @ 0x60 + 8002ed2: 430a orrs r2, r1 + 8002ed4: 431a orrs r2, r3 + 8002ed6: 687b ldr r3, [r7, #4] + 8002ed8: 681b ldr r3, [r3, #0] + 8002eda: f042 4200 orr.w r2, r2, #2147483648 @ 0x80000000 + 8002ede: 661a str r2, [r3, #96] @ 0x60 ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1 , ADC_OFR1_OFFSET1_EN | ADC_OFR_CHANNEL(sConfig->Channel) | tmpOffsetShifted ); break; - 8002e44: e07b b.n 8002f3e + 8002ee0: e07b b.n 8002fda case ADC_OFFSET_2: /* Configure offset register 2U */ MODIFY_REG(hadc->Instance->OFR2 , - 8002e46: 687b ldr r3, [r7, #4] - 8002e48: 681b ldr r3, [r3, #0] - 8002e4a: 6e5a ldr r2, [r3, #100] @ 0x64 - 8002e4c: 4b93 ldr r3, [pc, #588] @ (800309c ) - 8002e4e: 4013 ands r3, r2 - 8002e50: 683a ldr r2, [r7, #0] - 8002e52: 6812 ldr r2, [r2, #0] - 8002e54: 0691 lsls r1, r2, #26 - 8002e56: 6e3a ldr r2, [r7, #96] @ 0x60 - 8002e58: 430a orrs r2, r1 - 8002e5a: 431a orrs r2, r3 - 8002e5c: 687b ldr r3, [r7, #4] - 8002e5e: 681b ldr r3, [r3, #0] - 8002e60: f042 4200 orr.w r2, r2, #2147483648 @ 0x80000000 - 8002e64: 665a str r2, [r3, #100] @ 0x64 + 8002ee2: 687b ldr r3, [r7, #4] + 8002ee4: 681b ldr r3, [r3, #0] + 8002ee6: 6e5a ldr r2, [r3, #100] @ 0x64 + 8002ee8: 4b93 ldr r3, [pc, #588] @ (8003138 ) + 8002eea: 4013 ands r3, r2 + 8002eec: 683a ldr r2, [r7, #0] + 8002eee: 6812 ldr r2, [r2, #0] + 8002ef0: 0691 lsls r1, r2, #26 + 8002ef2: 6e3a ldr r2, [r7, #96] @ 0x60 + 8002ef4: 430a orrs r2, r1 + 8002ef6: 431a orrs r2, r3 + 8002ef8: 687b ldr r3, [r7, #4] + 8002efa: 681b ldr r3, [r3, #0] + 8002efc: f042 4200 orr.w r2, r2, #2147483648 @ 0x80000000 + 8002f00: 665a str r2, [r3, #100] @ 0x64 ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2 , ADC_OFR2_OFFSET2_EN | ADC_OFR_CHANNEL(sConfig->Channel) | tmpOffsetShifted ); break; - 8002e66: e06a b.n 8002f3e + 8002f02: e06a b.n 8002fda case ADC_OFFSET_3: /* Configure offset register 3U */ MODIFY_REG(hadc->Instance->OFR3 , - 8002e68: 687b ldr r3, [r7, #4] - 8002e6a: 681b ldr r3, [r3, #0] - 8002e6c: 6e9a ldr r2, [r3, #104] @ 0x68 - 8002e6e: 4b8b ldr r3, [pc, #556] @ (800309c ) - 8002e70: 4013 ands r3, r2 - 8002e72: 683a ldr r2, [r7, #0] - 8002e74: 6812 ldr r2, [r2, #0] - 8002e76: 0691 lsls r1, r2, #26 - 8002e78: 6e3a ldr r2, [r7, #96] @ 0x60 - 8002e7a: 430a orrs r2, r1 - 8002e7c: 431a orrs r2, r3 - 8002e7e: 687b ldr r3, [r7, #4] - 8002e80: 681b ldr r3, [r3, #0] - 8002e82: f042 4200 orr.w r2, r2, #2147483648 @ 0x80000000 - 8002e86: 669a str r2, [r3, #104] @ 0x68 + 8002f04: 687b ldr r3, [r7, #4] + 8002f06: 681b ldr r3, [r3, #0] + 8002f08: 6e9a ldr r2, [r3, #104] @ 0x68 + 8002f0a: 4b8b ldr r3, [pc, #556] @ (8003138 ) + 8002f0c: 4013 ands r3, r2 + 8002f0e: 683a ldr r2, [r7, #0] + 8002f10: 6812 ldr r2, [r2, #0] + 8002f12: 0691 lsls r1, r2, #26 + 8002f14: 6e3a ldr r2, [r7, #96] @ 0x60 + 8002f16: 430a orrs r2, r1 + 8002f18: 431a orrs r2, r3 + 8002f1a: 687b ldr r3, [r7, #4] + 8002f1c: 681b ldr r3, [r3, #0] + 8002f1e: f042 4200 orr.w r2, r2, #2147483648 @ 0x80000000 + 8002f22: 669a str r2, [r3, #104] @ 0x68 ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3 , ADC_OFR3_OFFSET3_EN | ADC_OFR_CHANNEL(sConfig->Channel) | tmpOffsetShifted ); break; - 8002e88: e059 b.n 8002f3e + 8002f24: e059 b.n 8002fda case ADC_OFFSET_4: /* Configure offset register 4U */ MODIFY_REG(hadc->Instance->OFR4 , - 8002e8a: 687b ldr r3, [r7, #4] - 8002e8c: 681b ldr r3, [r3, #0] - 8002e8e: 6eda ldr r2, [r3, #108] @ 0x6c - 8002e90: 4b82 ldr r3, [pc, #520] @ (800309c ) - 8002e92: 4013 ands r3, r2 - 8002e94: 683a ldr r2, [r7, #0] - 8002e96: 6812 ldr r2, [r2, #0] - 8002e98: 0691 lsls r1, r2, #26 - 8002e9a: 6e3a ldr r2, [r7, #96] @ 0x60 - 8002e9c: 430a orrs r2, r1 - 8002e9e: 431a orrs r2, r3 - 8002ea0: 687b ldr r3, [r7, #4] - 8002ea2: 681b ldr r3, [r3, #0] - 8002ea4: f042 4200 orr.w r2, r2, #2147483648 @ 0x80000000 - 8002ea8: 66da str r2, [r3, #108] @ 0x6c + 8002f26: 687b ldr r3, [r7, #4] + 8002f28: 681b ldr r3, [r3, #0] + 8002f2a: 6eda ldr r2, [r3, #108] @ 0x6c + 8002f2c: 4b82 ldr r3, [pc, #520] @ (8003138 ) + 8002f2e: 4013 ands r3, r2 + 8002f30: 683a ldr r2, [r7, #0] + 8002f32: 6812 ldr r2, [r2, #0] + 8002f34: 0691 lsls r1, r2, #26 + 8002f36: 6e3a ldr r2, [r7, #96] @ 0x60 + 8002f38: 430a orrs r2, r1 + 8002f3a: 431a orrs r2, r3 + 8002f3c: 687b ldr r3, [r7, #4] + 8002f3e: 681b ldr r3, [r3, #0] + 8002f40: f042 4200 orr.w r2, r2, #2147483648 @ 0x80000000 + 8002f44: 66da str r2, [r3, #108] @ 0x6c ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4 , ADC_OFR4_OFFSET4_EN | ADC_OFR_CHANNEL(sConfig->Channel) | tmpOffsetShifted ); break; - 8002eaa: e048 b.n 8002f3e + 8002f46: e048 b.n 8002fda /* Case ADC_OFFSET_NONE */ default : /* Scan OFR1, OFR2, OFR3, OFR4 to check if the selected channel is */ /* enabled. If this is the case, offset OFRx is disabled. */ if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) - 8002eac: 687b ldr r3, [r7, #4] - 8002eae: 681b ldr r3, [r3, #0] - 8002eb0: 6e1b ldr r3, [r3, #96] @ 0x60 - 8002eb2: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 - 8002eb6: 683b ldr r3, [r7, #0] - 8002eb8: 681b ldr r3, [r3, #0] - 8002eba: 069b lsls r3, r3, #26 - 8002ebc: 429a cmp r2, r3 - 8002ebe: d107 bne.n 8002ed0 + 8002f48: 687b ldr r3, [r7, #4] + 8002f4a: 681b ldr r3, [r3, #0] + 8002f4c: 6e1b ldr r3, [r3, #96] @ 0x60 + 8002f4e: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 + 8002f52: 683b ldr r3, [r7, #0] + 8002f54: 681b ldr r3, [r3, #0] + 8002f56: 069b lsls r3, r3, #26 + 8002f58: 429a cmp r2, r3 + 8002f5a: d107 bne.n 8002f6c { /* Disable offset OFR1*/ CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN); - 8002ec0: 687b ldr r3, [r7, #4] - 8002ec2: 681b ldr r3, [r3, #0] - 8002ec4: 6e1a ldr r2, [r3, #96] @ 0x60 - 8002ec6: 687b ldr r3, [r7, #4] - 8002ec8: 681b ldr r3, [r3, #0] - 8002eca: f022 4200 bic.w r2, r2, #2147483648 @ 0x80000000 - 8002ece: 661a str r2, [r3, #96] @ 0x60 + 8002f5c: 687b ldr r3, [r7, #4] + 8002f5e: 681b ldr r3, [r3, #0] + 8002f60: 6e1a ldr r2, [r3, #96] @ 0x60 + 8002f62: 687b ldr r3, [r7, #4] + 8002f64: 681b ldr r3, [r3, #0] + 8002f66: f022 4200 bic.w r2, r2, #2147483648 @ 0x80000000 + 8002f6a: 661a str r2, [r3, #96] @ 0x60 } if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) - 8002ed0: 687b ldr r3, [r7, #4] - 8002ed2: 681b ldr r3, [r3, #0] - 8002ed4: 6e5b ldr r3, [r3, #100] @ 0x64 - 8002ed6: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 - 8002eda: 683b ldr r3, [r7, #0] - 8002edc: 681b ldr r3, [r3, #0] - 8002ede: 069b lsls r3, r3, #26 - 8002ee0: 429a cmp r2, r3 - 8002ee2: d107 bne.n 8002ef4 + 8002f6c: 687b ldr r3, [r7, #4] + 8002f6e: 681b ldr r3, [r3, #0] + 8002f70: 6e5b ldr r3, [r3, #100] @ 0x64 + 8002f72: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 + 8002f76: 683b ldr r3, [r7, #0] + 8002f78: 681b ldr r3, [r3, #0] + 8002f7a: 069b lsls r3, r3, #26 + 8002f7c: 429a cmp r2, r3 + 8002f7e: d107 bne.n 8002f90 { /* Disable offset OFR2*/ CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN); - 8002ee4: 687b ldr r3, [r7, #4] - 8002ee6: 681b ldr r3, [r3, #0] - 8002ee8: 6e5a ldr r2, [r3, #100] @ 0x64 - 8002eea: 687b ldr r3, [r7, #4] - 8002eec: 681b ldr r3, [r3, #0] - 8002eee: f022 4200 bic.w r2, r2, #2147483648 @ 0x80000000 - 8002ef2: 665a str r2, [r3, #100] @ 0x64 + 8002f80: 687b ldr r3, [r7, #4] + 8002f82: 681b ldr r3, [r3, #0] + 8002f84: 6e5a ldr r2, [r3, #100] @ 0x64 + 8002f86: 687b ldr r3, [r7, #4] + 8002f88: 681b ldr r3, [r3, #0] + 8002f8a: f022 4200 bic.w r2, r2, #2147483648 @ 0x80000000 + 8002f8e: 665a str r2, [r3, #100] @ 0x64 } if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) - 8002ef4: 687b ldr r3, [r7, #4] - 8002ef6: 681b ldr r3, [r3, #0] - 8002ef8: 6e9b ldr r3, [r3, #104] @ 0x68 - 8002efa: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 - 8002efe: 683b ldr r3, [r7, #0] - 8002f00: 681b ldr r3, [r3, #0] - 8002f02: 069b lsls r3, r3, #26 - 8002f04: 429a cmp r2, r3 - 8002f06: d107 bne.n 8002f18 + 8002f90: 687b ldr r3, [r7, #4] + 8002f92: 681b ldr r3, [r3, #0] + 8002f94: 6e9b ldr r3, [r3, #104] @ 0x68 + 8002f96: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 + 8002f9a: 683b ldr r3, [r7, #0] + 8002f9c: 681b ldr r3, [r3, #0] + 8002f9e: 069b lsls r3, r3, #26 + 8002fa0: 429a cmp r2, r3 + 8002fa2: d107 bne.n 8002fb4 { /* Disable offset OFR3*/ CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN); - 8002f08: 687b ldr r3, [r7, #4] - 8002f0a: 681b ldr r3, [r3, #0] - 8002f0c: 6e9a ldr r2, [r3, #104] @ 0x68 - 8002f0e: 687b ldr r3, [r7, #4] - 8002f10: 681b ldr r3, [r3, #0] - 8002f12: f022 4200 bic.w r2, r2, #2147483648 @ 0x80000000 - 8002f16: 669a str r2, [r3, #104] @ 0x68 + 8002fa4: 687b ldr r3, [r7, #4] + 8002fa6: 681b ldr r3, [r3, #0] + 8002fa8: 6e9a ldr r2, [r3, #104] @ 0x68 + 8002faa: 687b ldr r3, [r7, #4] + 8002fac: 681b ldr r3, [r3, #0] + 8002fae: f022 4200 bic.w r2, r2, #2147483648 @ 0x80000000 + 8002fb2: 669a str r2, [r3, #104] @ 0x68 } if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) - 8002f18: 687b ldr r3, [r7, #4] - 8002f1a: 681b ldr r3, [r3, #0] - 8002f1c: 6edb ldr r3, [r3, #108] @ 0x6c - 8002f1e: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 - 8002f22: 683b ldr r3, [r7, #0] - 8002f24: 681b ldr r3, [r3, #0] - 8002f26: 069b lsls r3, r3, #26 - 8002f28: 429a cmp r2, r3 - 8002f2a: d107 bne.n 8002f3c + 8002fb4: 687b ldr r3, [r7, #4] + 8002fb6: 681b ldr r3, [r3, #0] + 8002fb8: 6edb ldr r3, [r3, #108] @ 0x6c + 8002fba: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 + 8002fbe: 683b ldr r3, [r7, #0] + 8002fc0: 681b ldr r3, [r3, #0] + 8002fc2: 069b lsls r3, r3, #26 + 8002fc4: 429a cmp r2, r3 + 8002fc6: d107 bne.n 8002fd8 { /* Disable offset OFR4*/ CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN); - 8002f2c: 687b ldr r3, [r7, #4] - 8002f2e: 681b ldr r3, [r3, #0] - 8002f30: 6eda ldr r2, [r3, #108] @ 0x6c - 8002f32: 687b ldr r3, [r7, #4] - 8002f34: 681b ldr r3, [r3, #0] - 8002f36: f022 4200 bic.w r2, r2, #2147483648 @ 0x80000000 - 8002f3a: 66da str r2, [r3, #108] @ 0x6c + 8002fc8: 687b ldr r3, [r7, #4] + 8002fca: 681b ldr r3, [r3, #0] + 8002fcc: 6eda ldr r2, [r3, #108] @ 0x6c + 8002fce: 687b ldr r3, [r7, #4] + 8002fd0: 681b ldr r3, [r3, #0] + 8002fd2: f022 4200 bic.w r2, r2, #2147483648 @ 0x80000000 + 8002fd6: 66da str r2, [r3, #108] @ 0x6c } break; - 8002f3c: bf00 nop + 8002fd8: bf00 nop /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - Single or differential mode */ /* - Internal measurement channels: Vbat/VrefInt/TempSensor */ if (ADC_IS_ENABLE(hadc) == RESET) - 8002f3e: 687b ldr r3, [r7, #4] - 8002f40: 681b ldr r3, [r3, #0] - 8002f42: 689b ldr r3, [r3, #8] - 8002f44: f003 0303 and.w r3, r3, #3 - 8002f48: 2b01 cmp r3, #1 - 8002f4a: d108 bne.n 8002f5e - 8002f4c: 687b ldr r3, [r7, #4] - 8002f4e: 681b ldr r3, [r3, #0] - 8002f50: 681b ldr r3, [r3, #0] - 8002f52: f003 0301 and.w r3, r3, #1 - 8002f56: 2b01 cmp r3, #1 - 8002f58: d101 bne.n 8002f5e - 8002f5a: 2301 movs r3, #1 - 8002f5c: e000 b.n 8002f60 - 8002f5e: 2300 movs r3, #0 - 8002f60: 2b00 cmp r3, #0 - 8002f62: f040 810a bne.w 800317a + 8002fda: 687b ldr r3, [r7, #4] + 8002fdc: 681b ldr r3, [r3, #0] + 8002fde: 689b ldr r3, [r3, #8] + 8002fe0: f003 0303 and.w r3, r3, #3 + 8002fe4: 2b01 cmp r3, #1 + 8002fe6: d108 bne.n 8002ffa + 8002fe8: 687b ldr r3, [r7, #4] + 8002fea: 681b ldr r3, [r3, #0] + 8002fec: 681b ldr r3, [r3, #0] + 8002fee: f003 0301 and.w r3, r3, #1 + 8002ff2: 2b01 cmp r3, #1 + 8002ff4: d101 bne.n 8002ffa + 8002ff6: 2301 movs r3, #1 + 8002ff8: e000 b.n 8002ffc + 8002ffa: 2300 movs r3, #0 + 8002ffc: 2b00 cmp r3, #0 + 8002ffe: f040 810a bne.w 8003216 { /* Configuration of differential mode */ if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED) - 8002f66: 683b ldr r3, [r7, #0] - 8002f68: 68db ldr r3, [r3, #12] - 8002f6a: 2b01 cmp r3, #1 - 8002f6c: d00f beq.n 8002f8e + 8003002: 683b ldr r3, [r7, #0] + 8003004: 68db ldr r3, [r3, #12] + 8003006: 2b01 cmp r3, #1 + 8003008: d00f beq.n 800302a { /* Disable differential mode (default mode: single-ended) */ CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfig->Channel)); - 8002f6e: 687b ldr r3, [r7, #4] - 8002f70: 681b ldr r3, [r3, #0] - 8002f72: f8d3 10b0 ldr.w r1, [r3, #176] @ 0xb0 - 8002f76: 683b ldr r3, [r7, #0] - 8002f78: 681b ldr r3, [r3, #0] - 8002f7a: 2201 movs r2, #1 - 8002f7c: fa02 f303 lsl.w r3, r2, r3 - 8002f80: 43da mvns r2, r3 - 8002f82: 687b ldr r3, [r7, #4] - 8002f84: 681b ldr r3, [r3, #0] - 8002f86: 400a ands r2, r1 - 8002f88: f8c3 20b0 str.w r2, [r3, #176] @ 0xb0 - 8002f8c: e049 b.n 8003022 + 800300a: 687b ldr r3, [r7, #4] + 800300c: 681b ldr r3, [r3, #0] + 800300e: f8d3 10b0 ldr.w r1, [r3, #176] @ 0xb0 + 8003012: 683b ldr r3, [r7, #0] + 8003014: 681b ldr r3, [r3, #0] + 8003016: 2201 movs r2, #1 + 8003018: fa02 f303 lsl.w r3, r2, r3 + 800301c: 43da mvns r2, r3 + 800301e: 687b ldr r3, [r7, #4] + 8003020: 681b ldr r3, [r3, #0] + 8003022: 400a ands r2, r1 + 8003024: f8c3 20b0 str.w r2, [r3, #176] @ 0xb0 + 8003028: e049 b.n 80030be } else { /* Enable differential mode */ SET_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfig->Channel)); - 8002f8e: 687b ldr r3, [r7, #4] - 8002f90: 681b ldr r3, [r3, #0] - 8002f92: f8d3 10b0 ldr.w r1, [r3, #176] @ 0xb0 - 8002f96: 683b ldr r3, [r7, #0] - 8002f98: 681b ldr r3, [r3, #0] - 8002f9a: 2201 movs r2, #1 - 8002f9c: 409a lsls r2, r3 - 8002f9e: 687b ldr r3, [r7, #4] - 8002fa0: 681b ldr r3, [r3, #0] - 8002fa2: 430a orrs r2, r1 - 8002fa4: f8c3 20b0 str.w r2, [r3, #176] @ 0xb0 + 800302a: 687b ldr r3, [r7, #4] + 800302c: 681b ldr r3, [r3, #0] + 800302e: f8d3 10b0 ldr.w r1, [r3, #176] @ 0xb0 + 8003032: 683b ldr r3, [r7, #0] + 8003034: 681b ldr r3, [r3, #0] + 8003036: 2201 movs r2, #1 + 8003038: 409a lsls r2, r3 + 800303a: 687b ldr r3, [r7, #4] + 800303c: 681b ldr r3, [r3, #0] + 800303e: 430a orrs r2, r1 + 8003040: f8c3 20b0 str.w r2, [r3, #176] @ 0xb0 /* Channel sampling time configuration (channel ADC_INx +1 */ /* corresponding to differential negative input). */ /* For channels 10 to 18U */ if (sConfig->Channel >= ADC_CHANNEL_10) - 8002fa8: 683b ldr r3, [r7, #0] - 8002faa: 681b ldr r3, [r3, #0] - 8002fac: 2b09 cmp r3, #9 - 8002fae: d91c bls.n 8002fea + 8003044: 683b ldr r3, [r7, #0] + 8003046: 681b ldr r3, [r3, #0] + 8003048: 2b09 cmp r3, #9 + 800304a: d91c bls.n 8003086 { MODIFY_REG(hadc->Instance->SMPR2, - 8002fb0: 687b ldr r3, [r7, #4] - 8002fb2: 681b ldr r3, [r3, #0] - 8002fb4: 6999 ldr r1, [r3, #24] - 8002fb6: 683b ldr r3, [r7, #0] - 8002fb8: 681a ldr r2, [r3, #0] - 8002fba: 4613 mov r3, r2 - 8002fbc: 005b lsls r3, r3, #1 - 8002fbe: 4413 add r3, r2 - 8002fc0: 3b1b subs r3, #27 - 8002fc2: 2207 movs r2, #7 - 8002fc4: fa02 f303 lsl.w r3, r2, r3 - 8002fc8: 43db mvns r3, r3 - 8002fca: 4019 ands r1, r3 - 8002fcc: 683b ldr r3, [r7, #0] - 8002fce: 6898 ldr r0, [r3, #8] - 8002fd0: 683b ldr r3, [r7, #0] - 8002fd2: 681a ldr r2, [r3, #0] - 8002fd4: 4613 mov r3, r2 - 8002fd6: 005b lsls r3, r3, #1 - 8002fd8: 4413 add r3, r2 - 8002fda: 3b1b subs r3, #27 - 8002fdc: fa00 f203 lsl.w r2, r0, r3 - 8002fe0: 687b ldr r3, [r7, #4] - 8002fe2: 681b ldr r3, [r3, #0] - 8002fe4: 430a orrs r2, r1 - 8002fe6: 619a str r2, [r3, #24] - 8002fe8: e01b b.n 8003022 + 800304c: 687b ldr r3, [r7, #4] + 800304e: 681b ldr r3, [r3, #0] + 8003050: 6999 ldr r1, [r3, #24] + 8003052: 683b ldr r3, [r7, #0] + 8003054: 681a ldr r2, [r3, #0] + 8003056: 4613 mov r3, r2 + 8003058: 005b lsls r3, r3, #1 + 800305a: 4413 add r3, r2 + 800305c: 3b1b subs r3, #27 + 800305e: 2207 movs r2, #7 + 8003060: fa02 f303 lsl.w r3, r2, r3 + 8003064: 43db mvns r3, r3 + 8003066: 4019 ands r1, r3 + 8003068: 683b ldr r3, [r7, #0] + 800306a: 6898 ldr r0, [r3, #8] + 800306c: 683b ldr r3, [r7, #0] + 800306e: 681a ldr r2, [r3, #0] + 8003070: 4613 mov r3, r2 + 8003072: 005b lsls r3, r3, #1 + 8003074: 4413 add r3, r2 + 8003076: 3b1b subs r3, #27 + 8003078: fa00 f203 lsl.w r2, r0, r3 + 800307c: 687b ldr r3, [r7, #4] + 800307e: 681b ldr r3, [r3, #0] + 8003080: 430a orrs r2, r1 + 8003082: 619a str r2, [r3, #24] + 8003084: e01b b.n 80030be ADC_SMPR2(ADC_SMPR2_SMP10, sConfig->Channel +1U) , ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel +1U) ); } else /* For channels 1 to 9U */ { MODIFY_REG(hadc->Instance->SMPR1, - 8002fea: 687b ldr r3, [r7, #4] - 8002fec: 681b ldr r3, [r3, #0] - 8002fee: 6959 ldr r1, [r3, #20] - 8002ff0: 683b ldr r3, [r7, #0] - 8002ff2: 681b ldr r3, [r3, #0] - 8002ff4: 1c5a adds r2, r3, #1 - 8002ff6: 4613 mov r3, r2 - 8002ff8: 005b lsls r3, r3, #1 - 8002ffa: 4413 add r3, r2 - 8002ffc: 2207 movs r2, #7 - 8002ffe: fa02 f303 lsl.w r3, r2, r3 - 8003002: 43db mvns r3, r3 - 8003004: 4019 ands r1, r3 - 8003006: 683b ldr r3, [r7, #0] - 8003008: 6898 ldr r0, [r3, #8] - 800300a: 683b ldr r3, [r7, #0] - 800300c: 681b ldr r3, [r3, #0] - 800300e: 1c5a adds r2, r3, #1 - 8003010: 4613 mov r3, r2 - 8003012: 005b lsls r3, r3, #1 - 8003014: 4413 add r3, r2 - 8003016: fa00 f203 lsl.w r2, r0, r3 - 800301a: 687b ldr r3, [r7, #4] - 800301c: 681b ldr r3, [r3, #0] - 800301e: 430a orrs r2, r1 - 8003020: 615a str r2, [r3, #20] + 8003086: 687b ldr r3, [r7, #4] + 8003088: 681b ldr r3, [r3, #0] + 800308a: 6959 ldr r1, [r3, #20] + 800308c: 683b ldr r3, [r7, #0] + 800308e: 681b ldr r3, [r3, #0] + 8003090: 1c5a adds r2, r3, #1 + 8003092: 4613 mov r3, r2 + 8003094: 005b lsls r3, r3, #1 + 8003096: 4413 add r3, r2 + 8003098: 2207 movs r2, #7 + 800309a: fa02 f303 lsl.w r3, r2, r3 + 800309e: 43db mvns r3, r3 + 80030a0: 4019 ands r1, r3 + 80030a2: 683b ldr r3, [r7, #0] + 80030a4: 6898 ldr r0, [r3, #8] + 80030a6: 683b ldr r3, [r7, #0] + 80030a8: 681b ldr r3, [r3, #0] + 80030aa: 1c5a adds r2, r3, #1 + 80030ac: 4613 mov r3, r2 + 80030ae: 005b lsls r3, r3, #1 + 80030b0: 4413 add r3, r2 + 80030b2: fa00 f203 lsl.w r2, r0, r3 + 80030b6: 687b ldr r3, [r7, #4] + 80030b8: 681b ldr r3, [r3, #0] + 80030ba: 430a orrs r2, r1 + 80030bc: 615a str r2, [r3, #20] /* Configuration of common ADC parameters */ /* Pointer to the common control register to which is belonging hadc */ /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */ /* control registers) */ tmpADC_Common = ADC_COMMON_REGISTER(hadc); - 8003022: 4b1f ldr r3, [pc, #124] @ (80030a0 ) - 8003024: 65fb str r3, [r7, #92] @ 0x5c + 80030be: 4b1f ldr r3, [pc, #124] @ (800313c ) + 80030c0: 65fb str r3, [r7, #92] @ 0x5c /* If the requested internal measurement path has already been enabled, */ /* bypass the configuration processing. */ if (( (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && - 8003026: 683b ldr r3, [r7, #0] - 8003028: 681b ldr r3, [r3, #0] - 800302a: 2b10 cmp r3, #16 - 800302c: d105 bne.n 800303a + 80030c2: 683b ldr r3, [r7, #0] + 80030c4: 681b ldr r3, [r3, #0] + 80030c6: 2b10 cmp r3, #16 + 80030c8: d105 bne.n 80030d6 (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_TSEN)) ) || - 800302e: 6dfb ldr r3, [r7, #92] @ 0x5c - 8003030: 689b ldr r3, [r3, #8] - 8003032: f403 0300 and.w r3, r3, #8388608 @ 0x800000 + 80030ca: 6dfb ldr r3, [r7, #92] @ 0x5c + 80030cc: 689b ldr r3, [r3, #8] + 80030ce: f403 0300 and.w r3, r3, #8388608 @ 0x800000 if (( (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && - 8003036: 2b00 cmp r3, #0 - 8003038: d015 beq.n 8003066 + 80030d2: 2b00 cmp r3, #0 + 80030d4: d015 beq.n 8003102 ( (sConfig->Channel == ADC_CHANNEL_VBAT) && - 800303a: 683b ldr r3, [r7, #0] - 800303c: 681b ldr r3, [r3, #0] + 80030d6: 683b ldr r3, [r7, #0] + 80030d8: 681b ldr r3, [r3, #0] (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_TSEN)) ) || - 800303e: 2b11 cmp r3, #17 - 8003040: d105 bne.n 800304e + 80030da: 2b11 cmp r3, #17 + 80030dc: d105 bne.n 80030ea (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VBATEN)) ) || - 8003042: 6dfb ldr r3, [r7, #92] @ 0x5c - 8003044: 689b ldr r3, [r3, #8] - 8003046: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 + 80030de: 6dfb ldr r3, [r7, #92] @ 0x5c + 80030e0: 689b ldr r3, [r3, #8] + 80030e2: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 ( (sConfig->Channel == ADC_CHANNEL_VBAT) && - 800304a: 2b00 cmp r3, #0 - 800304c: d00b beq.n 8003066 + 80030e6: 2b00 cmp r3, #0 + 80030e8: d00b beq.n 8003102 ( (sConfig->Channel == ADC_CHANNEL_VREFINT) && - 800304e: 683b ldr r3, [r7, #0] - 8003050: 681b ldr r3, [r3, #0] + 80030ea: 683b ldr r3, [r7, #0] + 80030ec: 681b ldr r3, [r3, #0] (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VBATEN)) ) || - 8003052: 2b12 cmp r3, #18 - 8003054: f040 8091 bne.w 800317a + 80030ee: 2b12 cmp r3, #18 + 80030f0: f040 8091 bne.w 8003216 (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VREFEN))) - 8003058: 6dfb ldr r3, [r7, #92] @ 0x5c - 800305a: 689b ldr r3, [r3, #8] - 800305c: f403 0380 and.w r3, r3, #4194304 @ 0x400000 + 80030f4: 6dfb ldr r3, [r7, #92] @ 0x5c + 80030f6: 689b ldr r3, [r3, #8] + 80030f8: f403 0380 and.w r3, r3, #4194304 @ 0x400000 ( (sConfig->Channel == ADC_CHANNEL_VREFINT) && - 8003060: 2b00 cmp r3, #0 - 8003062: f040 808a bne.w 800317a + 80030fc: 2b00 cmp r3, #0 + 80030fe: f040 808a bne.w 8003216 ) { /* Configuration of common ADC parameters (continuation) */ /* Set handle of the other ADC sharing the same common register */ ADC_COMMON_ADC_OTHER(hadc, &tmphadcSharingSameCommonRegister); - 8003066: 687b ldr r3, [r7, #4] - 8003068: 681b ldr r3, [r3, #0] - 800306a: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 - 800306e: d102 bne.n 8003076 - 8003070: 4b0c ldr r3, [pc, #48] @ (80030a4 ) - 8003072: 60fb str r3, [r7, #12] - 8003074: e002 b.n 800307c - 8003076: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 - 800307a: 60fb str r3, [r7, #12] + 8003102: 687b ldr r3, [r7, #4] + 8003104: 681b ldr r3, [r3, #0] + 8003106: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 + 800310a: d102 bne.n 8003112 + 800310c: 4b0c ldr r3, [pc, #48] @ (8003140 ) + 800310e: 60fb str r3, [r7, #12] + 8003110: e002 b.n 8003118 + 8003112: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 + 8003116: 60fb str r3, [r7, #12] /* Software is allowed to change common parameters only when all ADCs */ /* of the common group are disabled. */ if ((ADC_IS_ENABLE(hadc) == RESET) && - 800307c: 687b ldr r3, [r7, #4] - 800307e: 681b ldr r3, [r3, #0] - 8003080: 689b ldr r3, [r3, #8] - 8003082: f003 0303 and.w r3, r3, #3 - 8003086: 2b01 cmp r3, #1 - 8003088: d10e bne.n 80030a8 - 800308a: 687b ldr r3, [r7, #4] - 800308c: 681b ldr r3, [r3, #0] - 800308e: 681b ldr r3, [r3, #0] - 8003090: f003 0301 and.w r3, r3, #1 - 8003094: 2b01 cmp r3, #1 - 8003096: d107 bne.n 80030a8 - 8003098: 2301 movs r3, #1 - 800309a: e006 b.n 80030aa - 800309c: 83fff000 .word 0x83fff000 - 80030a0: 50000300 .word 0x50000300 - 80030a4: 50000100 .word 0x50000100 - 80030a8: 2300 movs r3, #0 - 80030aa: 2b00 cmp r3, #0 - 80030ac: d150 bne.n 8003150 + 8003118: 687b ldr r3, [r7, #4] + 800311a: 681b ldr r3, [r3, #0] + 800311c: 689b ldr r3, [r3, #8] + 800311e: f003 0303 and.w r3, r3, #3 + 8003122: 2b01 cmp r3, #1 + 8003124: d10e bne.n 8003144 + 8003126: 687b ldr r3, [r7, #4] + 8003128: 681b ldr r3, [r3, #0] + 800312a: 681b ldr r3, [r3, #0] + 800312c: f003 0301 and.w r3, r3, #1 + 8003130: 2b01 cmp r3, #1 + 8003132: d107 bne.n 8003144 + 8003134: 2301 movs r3, #1 + 8003136: e006 b.n 8003146 + 8003138: 83fff000 .word 0x83fff000 + 800313c: 50000300 .word 0x50000300 + 8003140: 50000100 .word 0x50000100 + 8003144: 2300 movs r3, #0 + 8003146: 2b00 cmp r3, #0 + 8003148: d150 bne.n 80031ec ( (tmphadcSharingSameCommonRegister.Instance == NULL) || - 80030ae: 68fb ldr r3, [r7, #12] + 800314a: 68fb ldr r3, [r7, #12] if ((ADC_IS_ENABLE(hadc) == RESET) && - 80030b0: 2b00 cmp r3, #0 - 80030b2: d010 beq.n 80030d6 + 800314c: 2b00 cmp r3, #0 + 800314e: d010 beq.n 8003172 (ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) ) ) - 80030b4: 68fb ldr r3, [r7, #12] - 80030b6: 689b ldr r3, [r3, #8] - 80030b8: f003 0303 and.w r3, r3, #3 - 80030bc: 2b01 cmp r3, #1 - 80030be: d107 bne.n 80030d0 - 80030c0: 68fb ldr r3, [r7, #12] - 80030c2: 681b ldr r3, [r3, #0] - 80030c4: f003 0301 and.w r3, r3, #1 - 80030c8: 2b01 cmp r3, #1 - 80030ca: d101 bne.n 80030d0 - 80030cc: 2301 movs r3, #1 - 80030ce: e000 b.n 80030d2 - 80030d0: 2300 movs r3, #0 + 8003150: 68fb ldr r3, [r7, #12] + 8003152: 689b ldr r3, [r3, #8] + 8003154: f003 0303 and.w r3, r3, #3 + 8003158: 2b01 cmp r3, #1 + 800315a: d107 bne.n 800316c + 800315c: 68fb ldr r3, [r7, #12] + 800315e: 681b ldr r3, [r3, #0] + 8003160: f003 0301 and.w r3, r3, #1 + 8003164: 2b01 cmp r3, #1 + 8003166: d101 bne.n 800316c + 8003168: 2301 movs r3, #1 + 800316a: e000 b.n 800316e + 800316c: 2300 movs r3, #0 ( (tmphadcSharingSameCommonRegister.Instance == NULL) || - 80030d2: 2b00 cmp r3, #0 - 80030d4: d13c bne.n 8003150 + 800316e: 2b00 cmp r3, #0 + 8003170: d13c bne.n 80031ec { /* If Channel_16 is selected, enable Temp. sensor measurement path */ /* Note: Temp. sensor internal channels available on ADC1 only */ if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && (hadc->Instance == ADC1)) - 80030d6: 683b ldr r3, [r7, #0] - 80030d8: 681b ldr r3, [r3, #0] - 80030da: 2b10 cmp r3, #16 - 80030dc: d11d bne.n 800311a - 80030de: 687b ldr r3, [r7, #4] - 80030e0: 681b ldr r3, [r3, #0] - 80030e2: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 - 80030e6: d118 bne.n 800311a + 8003172: 683b ldr r3, [r7, #0] + 8003174: 681b ldr r3, [r3, #0] + 8003176: 2b10 cmp r3, #16 + 8003178: d11d bne.n 80031b6 + 800317a: 687b ldr r3, [r7, #4] + 800317c: 681b ldr r3, [r3, #0] + 800317e: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 + 8003182: d118 bne.n 80031b6 { SET_BIT(tmpADC_Common->CCR, ADC_CCR_TSEN); - 80030e8: 6dfb ldr r3, [r7, #92] @ 0x5c - 80030ea: 689b ldr r3, [r3, #8] - 80030ec: f443 0200 orr.w r2, r3, #8388608 @ 0x800000 - 80030f0: 6dfb ldr r3, [r7, #92] @ 0x5c - 80030f2: 609a str r2, [r3, #8] + 8003184: 6dfb ldr r3, [r7, #92] @ 0x5c + 8003186: 689b ldr r3, [r3, #8] + 8003188: f443 0200 orr.w r2, r3, #8388608 @ 0x800000 + 800318c: 6dfb ldr r3, [r7, #92] @ 0x5c + 800318e: 609a str r2, [r3, #8] /* Delay for temperature sensor stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); - 80030f4: 4b27 ldr r3, [pc, #156] @ (8003194 ) - 80030f6: 681b ldr r3, [r3, #0] - 80030f8: 4a27 ldr r2, [pc, #156] @ (8003198 ) - 80030fa: fba2 2303 umull r2, r3, r2, r3 - 80030fe: 0c9a lsrs r2, r3, #18 - 8003100: 4613 mov r3, r2 - 8003102: 009b lsls r3, r3, #2 - 8003104: 4413 add r3, r2 - 8003106: 005b lsls r3, r3, #1 - 8003108: 60bb str r3, [r7, #8] + 8003190: 4b27 ldr r3, [pc, #156] @ (8003230 ) + 8003192: 681b ldr r3, [r3, #0] + 8003194: 4a27 ldr r2, [pc, #156] @ (8003234 ) + 8003196: fba2 2303 umull r2, r3, r2, r3 + 800319a: 0c9a lsrs r2, r3, #18 + 800319c: 4613 mov r3, r2 + 800319e: 009b lsls r3, r3, #2 + 80031a0: 4413 add r3, r2 + 80031a2: 005b lsls r3, r3, #1 + 80031a4: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) - 800310a: e002 b.n 8003112 + 80031a6: e002 b.n 80031ae { wait_loop_index--; - 800310c: 68bb ldr r3, [r7, #8] - 800310e: 3b01 subs r3, #1 - 8003110: 60bb str r3, [r7, #8] + 80031a8: 68bb ldr r3, [r7, #8] + 80031aa: 3b01 subs r3, #1 + 80031ac: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) - 8003112: 68bb ldr r3, [r7, #8] - 8003114: 2b00 cmp r3, #0 - 8003116: d1f9 bne.n 800310c + 80031ae: 68bb ldr r3, [r7, #8] + 80031b0: 2b00 cmp r3, #0 + 80031b2: d1f9 bne.n 80031a8 if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && (hadc->Instance == ADC1)) - 8003118: e02e b.n 8003178 + 80031b4: e02e b.n 8003214 } } /* If Channel_17 is selected, enable VBAT measurement path */ /* Note: VBAT internal channels available on ADC1 only */ else if ((sConfig->Channel == ADC_CHANNEL_VBAT) && (hadc->Instance == ADC1)) - 800311a: 683b ldr r3, [r7, #0] - 800311c: 681b ldr r3, [r3, #0] - 800311e: 2b11 cmp r3, #17 - 8003120: d10b bne.n 800313a - 8003122: 687b ldr r3, [r7, #4] - 8003124: 681b ldr r3, [r3, #0] - 8003126: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 - 800312a: d106 bne.n 800313a + 80031b6: 683b ldr r3, [r7, #0] + 80031b8: 681b ldr r3, [r3, #0] + 80031ba: 2b11 cmp r3, #17 + 80031bc: d10b bne.n 80031d6 + 80031be: 687b ldr r3, [r7, #4] + 80031c0: 681b ldr r3, [r3, #0] + 80031c2: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 + 80031c6: d106 bne.n 80031d6 { SET_BIT(tmpADC_Common->CCR, ADC_CCR_VBATEN); - 800312c: 6dfb ldr r3, [r7, #92] @ 0x5c - 800312e: 689b ldr r3, [r3, #8] - 8003130: f043 7280 orr.w r2, r3, #16777216 @ 0x1000000 - 8003134: 6dfb ldr r3, [r7, #92] @ 0x5c - 8003136: 609a str r2, [r3, #8] + 80031c8: 6dfb ldr r3, [r7, #92] @ 0x5c + 80031ca: 689b ldr r3, [r3, #8] + 80031cc: f043 7280 orr.w r2, r3, #16777216 @ 0x1000000 + 80031d0: 6dfb ldr r3, [r7, #92] @ 0x5c + 80031d2: 609a str r2, [r3, #8] if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && (hadc->Instance == ADC1)) - 8003138: e01e b.n 8003178 + 80031d4: e01e b.n 8003214 } /* If Channel_18 is selected, enable VREFINT measurement path */ /* Note: VrefInt internal channels available on all ADCs, but only */ /* one ADC is allowed to be connected to VrefInt at the same */ /* time. */ else if (sConfig->Channel == ADC_CHANNEL_VREFINT) - 800313a: 683b ldr r3, [r7, #0] - 800313c: 681b ldr r3, [r3, #0] - 800313e: 2b12 cmp r3, #18 - 8003140: d11a bne.n 8003178 + 80031d6: 683b ldr r3, [r7, #0] + 80031d8: 681b ldr r3, [r3, #0] + 80031da: 2b12 cmp r3, #18 + 80031dc: d11a bne.n 8003214 { SET_BIT(tmpADC_Common->CCR, ADC_CCR_VREFEN); - 8003142: 6dfb ldr r3, [r7, #92] @ 0x5c - 8003144: 689b ldr r3, [r3, #8] - 8003146: f443 0280 orr.w r2, r3, #4194304 @ 0x400000 - 800314a: 6dfb ldr r3, [r7, #92] @ 0x5c - 800314c: 609a str r2, [r3, #8] + 80031de: 6dfb ldr r3, [r7, #92] @ 0x5c + 80031e0: 689b ldr r3, [r3, #8] + 80031e2: f443 0280 orr.w r2, r3, #4194304 @ 0x400000 + 80031e6: 6dfb ldr r3, [r7, #92] @ 0x5c + 80031e8: 609a str r2, [r3, #8] if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && (hadc->Instance == ADC1)) - 800314e: e013 b.n 8003178 + 80031ea: e013 b.n 8003214 /* enabled and other ADC of the common group are enabled, internal */ /* measurement paths cannot be enabled. */ else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - 8003150: 687b ldr r3, [r7, #4] - 8003152: 6c1b ldr r3, [r3, #64] @ 0x40 - 8003154: f043 0220 orr.w r2, r3, #32 - 8003158: 687b ldr r3, [r7, #4] - 800315a: 641a str r2, [r3, #64] @ 0x40 + 80031ec: 687b ldr r3, [r7, #4] + 80031ee: 6c1b ldr r3, [r3, #64] @ 0x40 + 80031f0: f043 0220 orr.w r2, r3, #32 + 80031f4: 687b ldr r3, [r7, #4] + 80031f6: 641a str r2, [r3, #64] @ 0x40 tmp_hal_status = HAL_ERROR; - 800315c: 2301 movs r3, #1 - 800315e: f887 3067 strb.w r3, [r7, #103] @ 0x67 - 8003162: e00a b.n 800317a + 80031f8: 2301 movs r3, #1 + 80031fa: f887 3067 strb.w r3, [r7, #103] @ 0x67 + 80031fe: e00a b.n 8003216 /* channel could be done on neither of the channel configuration structure */ /* parameters. */ else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - 8003164: 687b ldr r3, [r7, #4] - 8003166: 6c1b ldr r3, [r3, #64] @ 0x40 - 8003168: f043 0220 orr.w r2, r3, #32 - 800316c: 687b ldr r3, [r7, #4] - 800316e: 641a str r2, [r3, #64] @ 0x40 + 8003200: 687b ldr r3, [r7, #4] + 8003202: 6c1b ldr r3, [r3, #64] @ 0x40 + 8003204: f043 0220 orr.w r2, r3, #32 + 8003208: 687b ldr r3, [r7, #4] + 800320a: 641a str r2, [r3, #64] @ 0x40 tmp_hal_status = HAL_ERROR; - 8003170: 2301 movs r3, #1 - 8003172: f887 3067 strb.w r3, [r7, #103] @ 0x67 - 8003176: e000 b.n 800317a + 800320c: 2301 movs r3, #1 + 800320e: f887 3067 strb.w r3, [r7, #103] @ 0x67 + 8003212: e000 b.n 8003216 if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && (hadc->Instance == ADC1)) - 8003178: bf00 nop + 8003214: bf00 nop } /* Process unlocked */ __HAL_UNLOCK(hadc); - 800317a: 687b ldr r3, [r7, #4] - 800317c: 2200 movs r2, #0 - 800317e: f883 203c strb.w r2, [r3, #60] @ 0x3c + 8003216: 687b ldr r3, [r7, #4] + 8003218: 2200 movs r2, #0 + 800321a: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Return function status */ return tmp_hal_status; - 8003182: f897 3067 ldrb.w r3, [r7, #103] @ 0x67 + 800321e: f897 3067 ldrb.w r3, [r7, #103] @ 0x67 } - 8003186: 4618 mov r0, r3 - 8003188: 376c adds r7, #108 @ 0x6c - 800318a: 46bd mov sp, r7 - 800318c: f85d 7b04 ldr.w r7, [sp], #4 - 8003190: 4770 bx lr - 8003192: bf00 nop - 8003194: 20000000 .word 0x20000000 - 8003198: 431bde83 .word 0x431bde83 + 8003222: 4618 mov r0, r3 + 8003224: 376c adds r7, #108 @ 0x6c + 8003226: 46bd mov sp, r7 + 8003228: f85d 7b04 ldr.w r7, [sp], #4 + 800322c: 4770 bx lr + 800322e: bf00 nop + 8003230: 20000000 .word 0x20000000 + 8003234: 431bde83 .word 0x431bde83 -0800319c : +08003238 : * @param hadc ADC handle * @param multimode Structure of ADC multimode configuration * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode) { - 800319c: b480 push {r7} - 800319e: b099 sub sp, #100 @ 0x64 - 80031a0: af00 add r7, sp, #0 - 80031a2: 6078 str r0, [r7, #4] - 80031a4: 6039 str r1, [r7, #0] + 8003238: b480 push {r7} + 800323a: b099 sub sp, #100 @ 0x64 + 800323c: af00 add r7, sp, #0 + 800323e: 6078 str r0, [r7, #4] + 8003240: 6039 str r1, [r7, #0] HAL_StatusTypeDef tmp_hal_status = HAL_OK; - 80031a6: 2300 movs r3, #0 - 80031a8: f887 305f strb.w r3, [r7, #95] @ 0x5f + 8003242: 2300 movs r3, #0 + 8003244: f887 305f strb.w r3, [r7, #95] @ 0x5f assert_param(IS_ADC_DMA_ACCESS_MODE(multimode->DMAAccessMode)); assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay)); } /* Set handle of the other ADC sharing the same common register */ ADC_COMMON_ADC_OTHER(hadc, &tmphadcSharingSameCommonRegister); - 80031ac: 687b ldr r3, [r7, #4] - 80031ae: 681b ldr r3, [r3, #0] - 80031b0: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 - 80031b4: d102 bne.n 80031bc - 80031b6: 4b5a ldr r3, [pc, #360] @ (8003320 ) - 80031b8: 60bb str r3, [r7, #8] - 80031ba: e002 b.n 80031c2 - 80031bc: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 - 80031c0: 60bb str r3, [r7, #8] + 8003248: 687b ldr r3, [r7, #4] + 800324a: 681b ldr r3, [r3, #0] + 800324c: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 + 8003250: d102 bne.n 8003258 + 8003252: 4b5a ldr r3, [pc, #360] @ (80033bc ) + 8003254: 60bb str r3, [r7, #8] + 8003256: e002 b.n 800325e + 8003258: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 + 800325c: 60bb str r3, [r7, #8] if (tmphadcSharingSameCommonRegister.Instance == NULL) - 80031c2: 68bb ldr r3, [r7, #8] - 80031c4: 2b00 cmp r3, #0 - 80031c6: d101 bne.n 80031cc + 800325e: 68bb ldr r3, [r7, #8] + 8003260: 2b00 cmp r3, #0 + 8003262: d101 bne.n 8003268 { /* Return function status */ return HAL_ERROR; - 80031c8: 2301 movs r3, #1 - 80031ca: e0a2 b.n 8003312 + 8003264: 2301 movs r3, #1 + 8003266: e0a2 b.n 80033ae } /* Process locked */ __HAL_LOCK(hadc); - 80031cc: 687b ldr r3, [r7, #4] - 80031ce: f893 303c ldrb.w r3, [r3, #60] @ 0x3c - 80031d2: 2b01 cmp r3, #1 - 80031d4: d101 bne.n 80031da - 80031d6: 2302 movs r3, #2 - 80031d8: e09b b.n 8003312 - 80031da: 687b ldr r3, [r7, #4] - 80031dc: 2201 movs r2, #1 - 80031de: f883 203c strb.w r2, [r3, #60] @ 0x3c + 8003268: 687b ldr r3, [r7, #4] + 800326a: f893 303c ldrb.w r3, [r3, #60] @ 0x3c + 800326e: 2b01 cmp r3, #1 + 8003270: d101 bne.n 8003276 + 8003272: 2302 movs r3, #2 + 8003274: e09b b.n 80033ae + 8003276: 687b ldr r3, [r7, #4] + 8003278: 2201 movs r2, #1 + 800327a: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - Multimode DMA configuration */ /* - Multimode DMA mode */ if ( (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) - 80031e2: 687b ldr r3, [r7, #4] - 80031e4: 681b ldr r3, [r3, #0] - 80031e6: 689b ldr r3, [r3, #8] - 80031e8: f003 0304 and.w r3, r3, #4 - 80031ec: 2b00 cmp r3, #0 - 80031ee: d17f bne.n 80032f0 + 800327e: 687b ldr r3, [r7, #4] + 8003280: 681b ldr r3, [r3, #0] + 8003282: 689b ldr r3, [r3, #8] + 8003284: f003 0304 and.w r3, r3, #4 + 8003288: 2b00 cmp r3, #0 + 800328a: d17f bne.n 800338c && (ADC_IS_CONVERSION_ONGOING_REGULAR(&tmphadcSharingSameCommonRegister) == RESET) ) - 80031f0: 68bb ldr r3, [r7, #8] - 80031f2: 689b ldr r3, [r3, #8] - 80031f4: f003 0304 and.w r3, r3, #4 - 80031f8: 2b00 cmp r3, #0 - 80031fa: d179 bne.n 80032f0 + 800328c: 68bb ldr r3, [r7, #8] + 800328e: 689b ldr r3, [r3, #8] + 8003290: f003 0304 and.w r3, r3, #4 + 8003294: 2b00 cmp r3, #0 + 8003296: d179 bne.n 800338c { /* Pointer to the common control register to which is belonging hadc */ /* (Depending on STM32F3 product, there may have up to 4 ADC and 2 common */ /* control registers) */ tmpADC_Common = ADC_COMMON_REGISTER(hadc); - 80031fc: 4b49 ldr r3, [pc, #292] @ (8003324 ) - 80031fe: 65bb str r3, [r7, #88] @ 0x58 + 8003298: 4b49 ldr r3, [pc, #292] @ (80033c0 ) + 800329a: 65bb str r3, [r7, #88] @ 0x58 /* If multimode is selected, configure all multimode parameters. */ /* Otherwise, reset multimode parameters (can be used in case of */ /* transition from multimode to independent mode). */ if(multimode->Mode != ADC_MODE_INDEPENDENT) - 8003200: 683b ldr r3, [r7, #0] - 8003202: 681b ldr r3, [r3, #0] - 8003204: 2b00 cmp r3, #0 - 8003206: d040 beq.n 800328a + 800329c: 683b ldr r3, [r7, #0] + 800329e: 681b ldr r3, [r3, #0] + 80032a0: 2b00 cmp r3, #0 + 80032a2: d040 beq.n 8003326 { /* Configuration of ADC common group ADC1&ADC2, ADC3&ADC4 if available */ /* (ADC2, ADC3, ADC4 availability depends on STM32 product) */ /* - DMA access mode */ MODIFY_REG(tmpADC_Common->CCR , - 8003208: 6dbb ldr r3, [r7, #88] @ 0x58 - 800320a: 689b ldr r3, [r3, #8] - 800320c: f423 4260 bic.w r2, r3, #57344 @ 0xe000 - 8003210: 683b ldr r3, [r7, #0] - 8003212: 6859 ldr r1, [r3, #4] - 8003214: 687b ldr r3, [r7, #4] - 8003216: f893 3030 ldrb.w r3, [r3, #48] @ 0x30 - 800321a: 035b lsls r3, r3, #13 - 800321c: 430b orrs r3, r1 - 800321e: 431a orrs r2, r3 - 8003220: 6dbb ldr r3, [r7, #88] @ 0x58 - 8003222: 609a str r2, [r3, #8] + 80032a4: 6dbb ldr r3, [r7, #88] @ 0x58 + 80032a6: 689b ldr r3, [r3, #8] + 80032a8: f423 4260 bic.w r2, r3, #57344 @ 0xe000 + 80032ac: 683b ldr r3, [r7, #0] + 80032ae: 6859 ldr r1, [r3, #4] + 80032b0: 687b ldr r3, [r7, #4] + 80032b2: f893 3030 ldrb.w r3, [r3, #48] @ 0x30 + 80032b6: 035b lsls r3, r3, #13 + 80032b8: 430b orrs r3, r1 + 80032ba: 431a orrs r2, r3 + 80032bc: 6dbb ldr r3, [r7, #88] @ 0x58 + 80032be: 609a str r2, [r3, #8] /* parameters, their setting is bypassed without error reporting */ /* (as it can be the expected behaviour in case of intended action */ /* to update parameter above (which fulfills the ADC state */ /* condition: no conversion on going on group regular) */ /* on the fly). */ if ((ADC_IS_ENABLE(hadc) == RESET) && - 8003224: 687b ldr r3, [r7, #4] - 8003226: 681b ldr r3, [r3, #0] - 8003228: 689b ldr r3, [r3, #8] - 800322a: f003 0303 and.w r3, r3, #3 - 800322e: 2b01 cmp r3, #1 - 8003230: d108 bne.n 8003244 - 8003232: 687b ldr r3, [r7, #4] - 8003234: 681b ldr r3, [r3, #0] - 8003236: 681b ldr r3, [r3, #0] - 8003238: f003 0301 and.w r3, r3, #1 - 800323c: 2b01 cmp r3, #1 - 800323e: d101 bne.n 8003244 - 8003240: 2301 movs r3, #1 - 8003242: e000 b.n 8003246 - 8003244: 2300 movs r3, #0 - 8003246: 2b00 cmp r3, #0 - 8003248: d15c bne.n 8003304 + 80032c0: 687b ldr r3, [r7, #4] + 80032c2: 681b ldr r3, [r3, #0] + 80032c4: 689b ldr r3, [r3, #8] + 80032c6: f003 0303 and.w r3, r3, #3 + 80032ca: 2b01 cmp r3, #1 + 80032cc: d108 bne.n 80032e0 + 80032ce: 687b ldr r3, [r7, #4] + 80032d0: 681b ldr r3, [r3, #0] + 80032d2: 681b ldr r3, [r3, #0] + 80032d4: f003 0301 and.w r3, r3, #1 + 80032d8: 2b01 cmp r3, #1 + 80032da: d101 bne.n 80032e0 + 80032dc: 2301 movs r3, #1 + 80032de: e000 b.n 80032e2 + 80032e0: 2300 movs r3, #0 + 80032e2: 2b00 cmp r3, #0 + 80032e4: d15c bne.n 80033a0 (ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) ) - 800324a: 68bb ldr r3, [r7, #8] - 800324c: 689b ldr r3, [r3, #8] - 800324e: f003 0303 and.w r3, r3, #3 - 8003252: 2b01 cmp r3, #1 - 8003254: d107 bne.n 8003266 - 8003256: 68bb ldr r3, [r7, #8] - 8003258: 681b ldr r3, [r3, #0] - 800325a: f003 0301 and.w r3, r3, #1 - 800325e: 2b01 cmp r3, #1 - 8003260: d101 bne.n 8003266 - 8003262: 2301 movs r3, #1 - 8003264: e000 b.n 8003268 - 8003266: 2300 movs r3, #0 + 80032e6: 68bb ldr r3, [r7, #8] + 80032e8: 689b ldr r3, [r3, #8] + 80032ea: f003 0303 and.w r3, r3, #3 + 80032ee: 2b01 cmp r3, #1 + 80032f0: d107 bne.n 8003302 + 80032f2: 68bb ldr r3, [r7, #8] + 80032f4: 681b ldr r3, [r3, #0] + 80032f6: f003 0301 and.w r3, r3, #1 + 80032fa: 2b01 cmp r3, #1 + 80032fc: d101 bne.n 8003302 + 80032fe: 2301 movs r3, #1 + 8003300: e000 b.n 8003304 + 8003302: 2300 movs r3, #0 if ((ADC_IS_ENABLE(hadc) == RESET) && - 8003268: 2b00 cmp r3, #0 - 800326a: d14b bne.n 8003304 + 8003304: 2b00 cmp r3, #0 + 8003306: d14b bne.n 80033a0 { MODIFY_REG(tmpADC_Common->CCR , - 800326c: 6dbb ldr r3, [r7, #88] @ 0x58 - 800326e: 689b ldr r3, [r3, #8] - 8003270: f423 6371 bic.w r3, r3, #3856 @ 0xf10 - 8003274: f023 030f bic.w r3, r3, #15 - 8003278: 683a ldr r2, [r7, #0] - 800327a: 6811 ldr r1, [r2, #0] - 800327c: 683a ldr r2, [r7, #0] - 800327e: 6892 ldr r2, [r2, #8] - 8003280: 430a orrs r2, r1 - 8003282: 431a orrs r2, r3 - 8003284: 6dbb ldr r3, [r7, #88] @ 0x58 - 8003286: 609a str r2, [r3, #8] + 8003308: 6dbb ldr r3, [r7, #88] @ 0x58 + 800330a: 689b ldr r3, [r3, #8] + 800330c: f423 6371 bic.w r3, r3, #3856 @ 0xf10 + 8003310: f023 030f bic.w r3, r3, #15 + 8003314: 683a ldr r2, [r7, #0] + 8003316: 6811 ldr r1, [r2, #0] + 8003318: 683a ldr r2, [r7, #0] + 800331a: 6892 ldr r2, [r2, #8] + 800331c: 430a orrs r2, r1 + 800331e: 431a orrs r2, r3 + 8003320: 6dbb ldr r3, [r7, #88] @ 0x58 + 8003322: 609a str r2, [r3, #8] if(multimode->Mode != ADC_MODE_INDEPENDENT) - 8003288: e03c b.n 8003304 + 8003324: e03c b.n 80033a0 multimode->TwoSamplingDelay ); } } else /* ADC_MODE_INDEPENDENT */ { CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG); - 800328a: 6dbb ldr r3, [r7, #88] @ 0x58 - 800328c: 689b ldr r3, [r3, #8] - 800328e: f423 4260 bic.w r2, r3, #57344 @ 0xe000 - 8003292: 6dbb ldr r3, [r7, #88] @ 0x58 - 8003294: 609a str r2, [r3, #8] + 8003326: 6dbb ldr r3, [r7, #88] @ 0x58 + 8003328: 689b ldr r3, [r3, #8] + 800332a: f423 4260 bic.w r2, r3, #57344 @ 0xe000 + 800332e: 6dbb ldr r3, [r7, #88] @ 0x58 + 8003330: 609a str r2, [r3, #8] /* Parameters that can be updated only when ADC is disabled: */ /* - Multimode mode selection */ /* - Multimode delay */ if ((ADC_IS_ENABLE(hadc) == RESET) && - 8003296: 687b ldr r3, [r7, #4] - 8003298: 681b ldr r3, [r3, #0] - 800329a: 689b ldr r3, [r3, #8] - 800329c: f003 0303 and.w r3, r3, #3 - 80032a0: 2b01 cmp r3, #1 - 80032a2: d108 bne.n 80032b6 - 80032a4: 687b ldr r3, [r7, #4] - 80032a6: 681b ldr r3, [r3, #0] - 80032a8: 681b ldr r3, [r3, #0] - 80032aa: f003 0301 and.w r3, r3, #1 - 80032ae: 2b01 cmp r3, #1 - 80032b0: d101 bne.n 80032b6 - 80032b2: 2301 movs r3, #1 - 80032b4: e000 b.n 80032b8 - 80032b6: 2300 movs r3, #0 - 80032b8: 2b00 cmp r3, #0 - 80032ba: d123 bne.n 8003304 + 8003332: 687b ldr r3, [r7, #4] + 8003334: 681b ldr r3, [r3, #0] + 8003336: 689b ldr r3, [r3, #8] + 8003338: f003 0303 and.w r3, r3, #3 + 800333c: 2b01 cmp r3, #1 + 800333e: d108 bne.n 8003352 + 8003340: 687b ldr r3, [r7, #4] + 8003342: 681b ldr r3, [r3, #0] + 8003344: 681b ldr r3, [r3, #0] + 8003346: f003 0301 and.w r3, r3, #1 + 800334a: 2b01 cmp r3, #1 + 800334c: d101 bne.n 8003352 + 800334e: 2301 movs r3, #1 + 8003350: e000 b.n 8003354 + 8003352: 2300 movs r3, #0 + 8003354: 2b00 cmp r3, #0 + 8003356: d123 bne.n 80033a0 (ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) ) - 80032bc: 68bb ldr r3, [r7, #8] - 80032be: 689b ldr r3, [r3, #8] - 80032c0: f003 0303 and.w r3, r3, #3 - 80032c4: 2b01 cmp r3, #1 - 80032c6: d107 bne.n 80032d8 - 80032c8: 68bb ldr r3, [r7, #8] - 80032ca: 681b ldr r3, [r3, #0] - 80032cc: f003 0301 and.w r3, r3, #1 - 80032d0: 2b01 cmp r3, #1 - 80032d2: d101 bne.n 80032d8 - 80032d4: 2301 movs r3, #1 - 80032d6: e000 b.n 80032da - 80032d8: 2300 movs r3, #0 + 8003358: 68bb ldr r3, [r7, #8] + 800335a: 689b ldr r3, [r3, #8] + 800335c: f003 0303 and.w r3, r3, #3 + 8003360: 2b01 cmp r3, #1 + 8003362: d107 bne.n 8003374 + 8003364: 68bb ldr r3, [r7, #8] + 8003366: 681b ldr r3, [r3, #0] + 8003368: f003 0301 and.w r3, r3, #1 + 800336c: 2b01 cmp r3, #1 + 800336e: d101 bne.n 8003374 + 8003370: 2301 movs r3, #1 + 8003372: e000 b.n 8003376 + 8003374: 2300 movs r3, #0 if ((ADC_IS_ENABLE(hadc) == RESET) && - 80032da: 2b00 cmp r3, #0 - 80032dc: d112 bne.n 8003304 + 8003376: 2b00 cmp r3, #0 + 8003378: d112 bne.n 80033a0 { CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_MULTI | ADC_CCR_DELAY); - 80032de: 6dbb ldr r3, [r7, #88] @ 0x58 - 80032e0: 689b ldr r3, [r3, #8] - 80032e2: f423 6371 bic.w r3, r3, #3856 @ 0xf10 - 80032e6: f023 030f bic.w r3, r3, #15 - 80032ea: 6dba ldr r2, [r7, #88] @ 0x58 - 80032ec: 6093 str r3, [r2, #8] + 800337a: 6dbb ldr r3, [r7, #88] @ 0x58 + 800337c: 689b ldr r3, [r3, #8] + 800337e: f423 6371 bic.w r3, r3, #3856 @ 0xf10 + 8003382: f023 030f bic.w r3, r3, #15 + 8003386: 6dba ldr r2, [r7, #88] @ 0x58 + 8003388: 6093 str r3, [r2, #8] if(multimode->Mode != ADC_MODE_INDEPENDENT) - 80032ee: e009 b.n 8003304 + 800338a: e009 b.n 80033a0 /* If one of the ADC sharing the same common group is enabled, no update */ /* could be done on neither of the multimode structure parameters. */ else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - 80032f0: 687b ldr r3, [r7, #4] - 80032f2: 6c1b ldr r3, [r3, #64] @ 0x40 - 80032f4: f043 0220 orr.w r2, r3, #32 - 80032f8: 687b ldr r3, [r7, #4] - 80032fa: 641a str r2, [r3, #64] @ 0x40 + 800338c: 687b ldr r3, [r7, #4] + 800338e: 6c1b ldr r3, [r3, #64] @ 0x40 + 8003390: f043 0220 orr.w r2, r3, #32 + 8003394: 687b ldr r3, [r7, #4] + 8003396: 641a str r2, [r3, #64] @ 0x40 tmp_hal_status = HAL_ERROR; - 80032fc: 2301 movs r3, #1 - 80032fe: f887 305f strb.w r3, [r7, #95] @ 0x5f - 8003302: e000 b.n 8003306 + 8003398: 2301 movs r3, #1 + 800339a: f887 305f strb.w r3, [r7, #95] @ 0x5f + 800339e: e000 b.n 80033a2 if(multimode->Mode != ADC_MODE_INDEPENDENT) - 8003304: bf00 nop + 80033a0: bf00 nop } /* Process unlocked */ __HAL_UNLOCK(hadc); - 8003306: 687b ldr r3, [r7, #4] - 8003308: 2200 movs r2, #0 - 800330a: f883 203c strb.w r2, [r3, #60] @ 0x3c + 80033a2: 687b ldr r3, [r7, #4] + 80033a4: 2200 movs r2, #0 + 80033a6: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Return function status */ return tmp_hal_status; - 800330e: f897 305f ldrb.w r3, [r7, #95] @ 0x5f + 80033aa: f897 305f ldrb.w r3, [r7, #95] @ 0x5f } - 8003312: 4618 mov r0, r3 - 8003314: 3764 adds r7, #100 @ 0x64 - 8003316: 46bd mov sp, r7 - 8003318: f85d 7b04 ldr.w r7, [sp], #4 - 800331c: 4770 bx lr - 800331e: bf00 nop - 8003320: 50000100 .word 0x50000100 - 8003324: 50000300 .word 0x50000300 + 80033ae: 4618 mov r0, r3 + 80033b0: 3764 adds r7, #100 @ 0x64 + 80033b2: 46bd mov sp, r7 + 80033b4: f85d 7b04 ldr.w r7, [sp], #4 + 80033b8: 4770 bx lr + 80033ba: bf00 nop + 80033bc: 50000100 .word 0x50000100 + 80033c0: 50000300 .word 0x50000300 -08003328 : +080033c4 : * @brief DMA transfer complete callback. * @param hdma pointer to DMA handle. * @retval None */ static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) { - 8003328: b580 push {r7, lr} - 800332a: b084 sub sp, #16 - 800332c: af00 add r7, sp, #0 - 800332e: 6078 str r0, [r7, #4] + 80033c4: b580 push {r7, lr} + 80033c6: b084 sub sp, #16 + 80033c8: af00 add r7, sp, #0 + 80033ca: 6078 str r0, [r7, #4] /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - 8003330: 687b ldr r3, [r7, #4] - 8003332: 6a5b ldr r3, [r3, #36] @ 0x24 - 8003334: 60fb str r3, [r7, #12] + 80033cc: 687b ldr r3, [r7, #4] + 80033ce: 6a5b ldr r3, [r3, #36] @ 0x24 + 80033d0: 60fb str r3, [r7, #12] /* Update state machine on conversion status if not in error state */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) - 8003336: 68fb ldr r3, [r7, #12] - 8003338: 6c1b ldr r3, [r3, #64] @ 0x40 - 800333a: f003 0350 and.w r3, r3, #80 @ 0x50 - 800333e: 2b00 cmp r3, #0 - 8003340: d126 bne.n 8003390 + 80033d2: 68fb ldr r3, [r7, #12] + 80033d4: 6c1b ldr r3, [r3, #64] @ 0x40 + 80033d6: f003 0350 and.w r3, r3, #80 @ 0x50 + 80033da: 2b00 cmp r3, #0 + 80033dc: d126 bne.n 800342c { /* Update ADC state machine */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); - 8003342: 68fb ldr r3, [r7, #12] - 8003344: 6c1b ldr r3, [r3, #64] @ 0x40 - 8003346: f443 7200 orr.w r2, r3, #512 @ 0x200 - 800334a: 68fb ldr r3, [r7, #12] - 800334c: 641a str r2, [r3, #64] @ 0x40 + 80033de: 68fb ldr r3, [r7, #12] + 80033e0: 6c1b ldr r3, [r3, #64] @ 0x40 + 80033e2: f443 7200 orr.w r2, r3, #512 @ 0x200 + 80033e6: 68fb ldr r3, [r7, #12] + 80033e8: 641a str r2, [r3, #64] @ 0x40 /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going. */ /* Note: On STM32F3 devices, in case of sequencer enabled */ /* (several ranks selected), end of conversion flag is raised */ /* at the end of the sequence. */ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && - 800334e: 68fb ldr r3, [r7, #12] - 8003350: 681b ldr r3, [r3, #0] - 8003352: 68db ldr r3, [r3, #12] - 8003354: f403 6340 and.w r3, r3, #3072 @ 0xc00 - 8003358: 2b00 cmp r3, #0 - 800335a: d115 bne.n 8003388 + 80033ea: 68fb ldr r3, [r7, #12] + 80033ec: 681b ldr r3, [r3, #0] + 80033ee: 68db ldr r3, [r3, #12] + 80033f0: f403 6340 and.w r3, r3, #3072 @ 0xc00 + 80033f4: 2b00 cmp r3, #0 + 80033f6: d115 bne.n 8003424 (hadc->Init.ContinuousConvMode == DISABLE) ) - 800335c: 68fb ldr r3, [r7, #12] - 800335e: 7e5b ldrb r3, [r3, #25] + 80033f8: 68fb ldr r3, [r7, #12] + 80033fa: 7e5b ldrb r3, [r3, #25] if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && - 8003360: 2b00 cmp r3, #0 - 8003362: d111 bne.n 8003388 + 80033fc: 2b00 cmp r3, #0 + 80033fe: d111 bne.n 8003424 { /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); - 8003364: 68fb ldr r3, [r7, #12] - 8003366: 6c1b ldr r3, [r3, #64] @ 0x40 - 8003368: f423 7280 bic.w r2, r3, #256 @ 0x100 - 800336c: 68fb ldr r3, [r7, #12] - 800336e: 641a str r2, [r3, #64] @ 0x40 + 8003400: 68fb ldr r3, [r7, #12] + 8003402: 6c1b ldr r3, [r3, #64] @ 0x40 + 8003404: f423 7280 bic.w r2, r3, #256 @ 0x100 + 8003408: 68fb ldr r3, [r7, #12] + 800340a: 641a str r2, [r3, #64] @ 0x40 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) - 8003370: 68fb ldr r3, [r7, #12] - 8003372: 6c1b ldr r3, [r3, #64] @ 0x40 - 8003374: f403 5380 and.w r3, r3, #4096 @ 0x1000 - 8003378: 2b00 cmp r3, #0 - 800337a: d105 bne.n 8003388 + 800340c: 68fb ldr r3, [r7, #12] + 800340e: 6c1b ldr r3, [r3, #64] @ 0x40 + 8003410: f403 5380 and.w r3, r3, #4096 @ 0x1000 + 8003414: 2b00 cmp r3, #0 + 8003416: d105 bne.n 8003424 { SET_BIT(hadc->State, HAL_ADC_STATE_READY); - 800337c: 68fb ldr r3, [r7, #12] - 800337e: 6c1b ldr r3, [r3, #64] @ 0x40 - 8003380: f043 0201 orr.w r2, r3, #1 - 8003384: 68fb ldr r3, [r7, #12] - 8003386: 641a str r2, [r3, #64] @ 0x40 + 8003418: 68fb ldr r3, [r7, #12] + 800341a: 6c1b ldr r3, [r3, #64] @ 0x40 + 800341c: f043 0201 orr.w r2, r3, #1 + 8003420: 68fb ldr r3, [r7, #12] + 8003422: 641a str r2, [r3, #64] @ 0x40 /* Conversion complete callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvCpltCallback(hadc); #else HAL_ADC_ConvCpltCallback(hadc); - 8003388: 68f8 ldr r0, [r7, #12] - 800338a: f7fd fd9d bl 8000ec8 + 8003424: 68f8 ldr r0, [r7, #12] + 8003426: f7fd fd5b bl 8000ee0 else { /* Call DMA error callback */ hadc->DMA_Handle->XferErrorCallback(hdma); } } - 800338e: e004 b.n 800339a + 800342a: e004 b.n 8003436 hadc->DMA_Handle->XferErrorCallback(hdma); - 8003390: 68fb ldr r3, [r7, #12] - 8003392: 6b9b ldr r3, [r3, #56] @ 0x38 - 8003394: 6b1b ldr r3, [r3, #48] @ 0x30 - 8003396: 6878 ldr r0, [r7, #4] - 8003398: 4798 blx r3 + 800342c: 68fb ldr r3, [r7, #12] + 800342e: 6b9b ldr r3, [r3, #56] @ 0x38 + 8003430: 6b1b ldr r3, [r3, #48] @ 0x30 + 8003432: 6878 ldr r0, [r7, #4] + 8003434: 4798 blx r3 } - 800339a: bf00 nop - 800339c: 3710 adds r7, #16 - 800339e: 46bd mov sp, r7 - 80033a0: bd80 pop {r7, pc} + 8003436: bf00 nop + 8003438: 3710 adds r7, #16 + 800343a: 46bd mov sp, r7 + 800343c: bd80 pop {r7, pc} -080033a2 : +0800343e : * @brief DMA half transfer complete callback. * @param hdma pointer to DMA handle. * @retval None */ static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) { - 80033a2: b580 push {r7, lr} - 80033a4: b084 sub sp, #16 - 80033a6: af00 add r7, sp, #0 - 80033a8: 6078 str r0, [r7, #4] + 800343e: b580 push {r7, lr} + 8003440: b084 sub sp, #16 + 8003442: af00 add r7, sp, #0 + 8003444: 6078 str r0, [r7, #4] /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - 80033aa: 687b ldr r3, [r7, #4] - 80033ac: 6a5b ldr r3, [r3, #36] @ 0x24 - 80033ae: 60fb str r3, [r7, #12] + 8003446: 687b ldr r3, [r7, #4] + 8003448: 6a5b ldr r3, [r3, #36] @ 0x24 + 800344a: 60fb str r3, [r7, #12] /* Half conversion callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvHalfCpltCallback(hadc); #else HAL_ADC_ConvHalfCpltCallback(hadc); - 80033b0: 68f8 ldr r0, [r7, #12] - 80033b2: f7fe ff89 bl 80022c8 + 800344c: 68f8 ldr r0, [r7, #12] + 800344e: f7fe ff89 bl 8002364 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } - 80033b6: bf00 nop - 80033b8: 3710 adds r7, #16 - 80033ba: 46bd mov sp, r7 - 80033bc: bd80 pop {r7, pc} + 8003452: bf00 nop + 8003454: 3710 adds r7, #16 + 8003456: 46bd mov sp, r7 + 8003458: bd80 pop {r7, pc} -080033be : +0800345a : * @brief DMA error callback * @param hdma pointer to DMA handle. * @retval None */ static void ADC_DMAError(DMA_HandleTypeDef *hdma) { - 80033be: b580 push {r7, lr} - 80033c0: b084 sub sp, #16 - 80033c2: af00 add r7, sp, #0 - 80033c4: 6078 str r0, [r7, #4] + 800345a: b580 push {r7, lr} + 800345c: b084 sub sp, #16 + 800345e: af00 add r7, sp, #0 + 8003460: 6078 str r0, [r7, #4] /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - 80033c6: 687b ldr r3, [r7, #4] - 80033c8: 6a5b ldr r3, [r3, #36] @ 0x24 - 80033ca: 60fb str r3, [r7, #12] + 8003462: 687b ldr r3, [r7, #4] + 8003464: 6a5b ldr r3, [r3, #36] @ 0x24 + 8003466: 60fb str r3, [r7, #12] /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); - 80033cc: 68fb ldr r3, [r7, #12] - 80033ce: 6c1b ldr r3, [r3, #64] @ 0x40 - 80033d0: f043 0240 orr.w r2, r3, #64 @ 0x40 - 80033d4: 68fb ldr r3, [r7, #12] - 80033d6: 641a str r2, [r3, #64] @ 0x40 + 8003468: 68fb ldr r3, [r7, #12] + 800346a: 6c1b ldr r3, [r3, #64] @ 0x40 + 800346c: f043 0240 orr.w r2, r3, #64 @ 0x40 + 8003470: 68fb ldr r3, [r7, #12] + 8003472: 641a str r2, [r3, #64] @ 0x40 /* Set ADC error code to DMA error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA); - 80033d8: 68fb ldr r3, [r7, #12] - 80033da: 6c5b ldr r3, [r3, #68] @ 0x44 - 80033dc: f043 0204 orr.w r2, r3, #4 - 80033e0: 68fb ldr r3, [r7, #12] - 80033e2: 645a str r2, [r3, #68] @ 0x44 + 8003474: 68fb ldr r3, [r7, #12] + 8003476: 6c5b ldr r3, [r3, #68] @ 0x44 + 8003478: f043 0204 orr.w r2, r3, #4 + 800347c: 68fb ldr r3, [r7, #12] + 800347e: 645a str r2, [r3, #68] @ 0x44 /* Error callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ErrorCallback(hadc); #else HAL_ADC_ErrorCallback(hadc); - 80033e4: 68f8 ldr r0, [r7, #12] - 80033e6: f7fe ff83 bl 80022f0 + 8003480: 68f8 ldr r0, [r7, #12] + 8003482: f7fe ff83 bl 800238c #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } - 80033ea: bf00 nop - 80033ec: 3710 adds r7, #16 - 80033ee: 46bd mov sp, r7 - 80033f0: bd80 pop {r7, pc} + 8003486: bf00 nop + 8003488: 3710 adds r7, #16 + 800348a: 46bd mov sp, r7 + 800348c: bd80 pop {r7, pc} ... -080033f4 : +08003490 : * and voltage regulator must be enabled (done into HAL_ADC_Init()). * @param hadc ADC handle * @retval HAL status. */ static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) { - 80033f4: b580 push {r7, lr} - 80033f6: b084 sub sp, #16 - 80033f8: af00 add r7, sp, #0 - 80033fa: 6078 str r0, [r7, #4] + 8003490: b580 push {r7, lr} + 8003492: b084 sub sp, #16 + 8003494: af00 add r7, sp, #0 + 8003496: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; - 80033fc: 2300 movs r3, #0 - 80033fe: 60fb str r3, [r7, #12] + 8003498: 2300 movs r3, #0 + 800349a: 60fb str r3, [r7, #12] /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ /* enabling phase not yet completed: flag ADC ready not yet set). */ /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ /* causes: ADC clock not running, ...). */ if (ADC_IS_ENABLE(hadc) == RESET) - 8003400: 687b ldr r3, [r7, #4] - 8003402: 681b ldr r3, [r3, #0] - 8003404: 689b ldr r3, [r3, #8] - 8003406: f003 0303 and.w r3, r3, #3 - 800340a: 2b01 cmp r3, #1 - 800340c: d108 bne.n 8003420 - 800340e: 687b ldr r3, [r7, #4] - 8003410: 681b ldr r3, [r3, #0] - 8003412: 681b ldr r3, [r3, #0] - 8003414: f003 0301 and.w r3, r3, #1 - 8003418: 2b01 cmp r3, #1 - 800341a: d101 bne.n 8003420 - 800341c: 2301 movs r3, #1 - 800341e: e000 b.n 8003422 - 8003420: 2300 movs r3, #0 - 8003422: 2b00 cmp r3, #0 - 8003424: d143 bne.n 80034ae + 800349c: 687b ldr r3, [r7, #4] + 800349e: 681b ldr r3, [r3, #0] + 80034a0: 689b ldr r3, [r3, #8] + 80034a2: f003 0303 and.w r3, r3, #3 + 80034a6: 2b01 cmp r3, #1 + 80034a8: d108 bne.n 80034bc + 80034aa: 687b ldr r3, [r7, #4] + 80034ac: 681b ldr r3, [r3, #0] + 80034ae: 681b ldr r3, [r3, #0] + 80034b0: f003 0301 and.w r3, r3, #1 + 80034b4: 2b01 cmp r3, #1 + 80034b6: d101 bne.n 80034bc + 80034b8: 2301 movs r3, #1 + 80034ba: e000 b.n 80034be + 80034bc: 2300 movs r3, #0 + 80034be: 2b00 cmp r3, #0 + 80034c0: d143 bne.n 800354a { /* Check if conditions to enable the ADC are fulfilled */ if (ADC_ENABLING_CONDITIONS(hadc) == RESET) - 8003426: 687b ldr r3, [r7, #4] - 8003428: 681b ldr r3, [r3, #0] - 800342a: 689a ldr r2, [r3, #8] - 800342c: 4b22 ldr r3, [pc, #136] @ (80034b8 ) - 800342e: 4013 ands r3, r2 - 8003430: 2b00 cmp r3, #0 - 8003432: d00d beq.n 8003450 + 80034c2: 687b ldr r3, [r7, #4] + 80034c4: 681b ldr r3, [r3, #0] + 80034c6: 689a ldr r2, [r3, #8] + 80034c8: 4b22 ldr r3, [pc, #136] @ (8003554 ) + 80034ca: 4013 ands r3, r2 + 80034cc: 2b00 cmp r3, #0 + 80034ce: d00d beq.n 80034ec { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - 8003434: 687b ldr r3, [r7, #4] - 8003436: 6c1b ldr r3, [r3, #64] @ 0x40 - 8003438: f043 0210 orr.w r2, r3, #16 - 800343c: 687b ldr r3, [r7, #4] - 800343e: 641a str r2, [r3, #64] @ 0x40 + 80034d0: 687b ldr r3, [r7, #4] + 80034d2: 6c1b ldr r3, [r3, #64] @ 0x40 + 80034d4: f043 0210 orr.w r2, r3, #16 + 80034d8: 687b ldr r3, [r7, #4] + 80034da: 641a str r2, [r3, #64] @ 0x40 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - 8003440: 687b ldr r3, [r7, #4] - 8003442: 6c5b ldr r3, [r3, #68] @ 0x44 - 8003444: f043 0201 orr.w r2, r3, #1 - 8003448: 687b ldr r3, [r7, #4] - 800344a: 645a str r2, [r3, #68] @ 0x44 + 80034dc: 687b ldr r3, [r7, #4] + 80034de: 6c5b ldr r3, [r3, #68] @ 0x44 + 80034e0: f043 0201 orr.w r2, r3, #1 + 80034e4: 687b ldr r3, [r7, #4] + 80034e6: 645a str r2, [r3, #68] @ 0x44 return HAL_ERROR; - 800344c: 2301 movs r3, #1 - 800344e: e02f b.n 80034b0 + 80034e8: 2301 movs r3, #1 + 80034ea: e02f b.n 800354c } /* Enable the ADC peripheral */ __HAL_ADC_ENABLE(hadc); - 8003450: 687b ldr r3, [r7, #4] - 8003452: 681b ldr r3, [r3, #0] - 8003454: 689a ldr r2, [r3, #8] - 8003456: 687b ldr r3, [r7, #4] - 8003458: 681b ldr r3, [r3, #0] - 800345a: f042 0201 orr.w r2, r2, #1 - 800345e: 609a str r2, [r3, #8] + 80034ec: 687b ldr r3, [r7, #4] + 80034ee: 681b ldr r3, [r3, #0] + 80034f0: 689a ldr r2, [r3, #8] + 80034f2: 687b ldr r3, [r7, #4] + 80034f4: 681b ldr r3, [r3, #0] + 80034f6: f042 0201 orr.w r2, r2, #1 + 80034fa: 609a str r2, [r3, #8] /* Wait for ADC effectively enabled */ tickstart = HAL_GetTick(); - 8003460: f7fe ff02 bl 8002268 - 8003464: 60f8 str r0, [r7, #12] + 80034fc: f7fe ff02 bl 8002304 + 8003500: 60f8 str r0, [r7, #12] while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET) - 8003466: e01b b.n 80034a0 + 8003502: e01b b.n 800353c { if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) - 8003468: f7fe fefe bl 8002268 - 800346c: 4602 mov r2, r0 - 800346e: 68fb ldr r3, [r7, #12] - 8003470: 1ad3 subs r3, r2, r3 - 8003472: 2b02 cmp r3, #2 - 8003474: d914 bls.n 80034a0 + 8003504: f7fe fefe bl 8002304 + 8003508: 4602 mov r2, r0 + 800350a: 68fb ldr r3, [r7, #12] + 800350c: 1ad3 subs r3, r2, r3 + 800350e: 2b02 cmp r3, #2 + 8003510: d914 bls.n 800353c { /* New check to avoid false timeout detection in case of preemption */ if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET) - 8003476: 687b ldr r3, [r7, #4] - 8003478: 681b ldr r3, [r3, #0] - 800347a: 681b ldr r3, [r3, #0] - 800347c: f003 0301 and.w r3, r3, #1 - 8003480: 2b01 cmp r3, #1 - 8003482: d00d beq.n 80034a0 + 8003512: 687b ldr r3, [r7, #4] + 8003514: 681b ldr r3, [r3, #0] + 8003516: 681b ldr r3, [r3, #0] + 8003518: f003 0301 and.w r3, r3, #1 + 800351c: 2b01 cmp r3, #1 + 800351e: d00d beq.n 800353c { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - 8003484: 687b ldr r3, [r7, #4] - 8003486: 6c1b ldr r3, [r3, #64] @ 0x40 - 8003488: f043 0210 orr.w r2, r3, #16 - 800348c: 687b ldr r3, [r7, #4] - 800348e: 641a str r2, [r3, #64] @ 0x40 + 8003520: 687b ldr r3, [r7, #4] + 8003522: 6c1b ldr r3, [r3, #64] @ 0x40 + 8003524: f043 0210 orr.w r2, r3, #16 + 8003528: 687b ldr r3, [r7, #4] + 800352a: 641a str r2, [r3, #64] @ 0x40 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - 8003490: 687b ldr r3, [r7, #4] - 8003492: 6c5b ldr r3, [r3, #68] @ 0x44 - 8003494: f043 0201 orr.w r2, r3, #1 - 8003498: 687b ldr r3, [r7, #4] - 800349a: 645a str r2, [r3, #68] @ 0x44 + 800352c: 687b ldr r3, [r7, #4] + 800352e: 6c5b ldr r3, [r3, #68] @ 0x44 + 8003530: f043 0201 orr.w r2, r3, #1 + 8003534: 687b ldr r3, [r7, #4] + 8003536: 645a str r2, [r3, #68] @ 0x44 return HAL_ERROR; - 800349c: 2301 movs r3, #1 - 800349e: e007 b.n 80034b0 + 8003538: 2301 movs r3, #1 + 800353a: e007 b.n 800354c while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET) - 80034a0: 687b ldr r3, [r7, #4] - 80034a2: 681b ldr r3, [r3, #0] - 80034a4: 681b ldr r3, [r3, #0] - 80034a6: f003 0301 and.w r3, r3, #1 - 80034aa: 2b01 cmp r3, #1 - 80034ac: d1dc bne.n 8003468 + 800353c: 687b ldr r3, [r7, #4] + 800353e: 681b ldr r3, [r3, #0] + 8003540: 681b ldr r3, [r3, #0] + 8003542: f003 0301 and.w r3, r3, #1 + 8003546: 2b01 cmp r3, #1 + 8003548: d1dc bne.n 8003504 } } } /* Return HAL status */ return HAL_OK; - 80034ae: 2300 movs r3, #0 + 800354a: 2300 movs r3, #0 } - 80034b0: 4618 mov r0, r3 - 80034b2: 3710 adds r7, #16 - 80034b4: 46bd mov sp, r7 - 80034b6: bd80 pop {r7, pc} - 80034b8: 8000003f .word 0x8000003f + 800354c: 4618 mov r0, r3 + 800354e: 3710 adds r7, #16 + 8003550: 46bd mov sp, r7 + 8003552: bd80 pop {r7, pc} + 8003554: 8000003f .word 0x8000003f -080034bc : +08003558 : * stopped. * @param hadc ADC handle * @retval HAL status. */ static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc) { - 80034bc: b580 push {r7, lr} - 80034be: b084 sub sp, #16 - 80034c0: af00 add r7, sp, #0 - 80034c2: 6078 str r0, [r7, #4] + 8003558: b580 push {r7, lr} + 800355a: b084 sub sp, #16 + 800355c: af00 add r7, sp, #0 + 800355e: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; - 80034c4: 2300 movs r3, #0 - 80034c6: 60fb str r3, [r7, #12] + 8003560: 2300 movs r3, #0 + 8003562: 60fb str r3, [r7, #12] /* Verification if ADC is not already disabled: */ /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */ /* disabled. */ if (ADC_IS_ENABLE(hadc) != RESET ) - 80034c8: 687b ldr r3, [r7, #4] - 80034ca: 681b ldr r3, [r3, #0] - 80034cc: 689b ldr r3, [r3, #8] - 80034ce: f003 0303 and.w r3, r3, #3 - 80034d2: 2b01 cmp r3, #1 - 80034d4: d108 bne.n 80034e8 - 80034d6: 687b ldr r3, [r7, #4] - 80034d8: 681b ldr r3, [r3, #0] - 80034da: 681b ldr r3, [r3, #0] - 80034dc: f003 0301 and.w r3, r3, #1 - 80034e0: 2b01 cmp r3, #1 - 80034e2: d101 bne.n 80034e8 - 80034e4: 2301 movs r3, #1 - 80034e6: e000 b.n 80034ea - 80034e8: 2300 movs r3, #0 - 80034ea: 2b00 cmp r3, #0 - 80034ec: d047 beq.n 800357e + 8003564: 687b ldr r3, [r7, #4] + 8003566: 681b ldr r3, [r3, #0] + 8003568: 689b ldr r3, [r3, #8] + 800356a: f003 0303 and.w r3, r3, #3 + 800356e: 2b01 cmp r3, #1 + 8003570: d108 bne.n 8003584 + 8003572: 687b ldr r3, [r7, #4] + 8003574: 681b ldr r3, [r3, #0] + 8003576: 681b ldr r3, [r3, #0] + 8003578: f003 0301 and.w r3, r3, #1 + 800357c: 2b01 cmp r3, #1 + 800357e: d101 bne.n 8003584 + 8003580: 2301 movs r3, #1 + 8003582: e000 b.n 8003586 + 8003584: 2300 movs r3, #0 + 8003586: 2b00 cmp r3, #0 + 8003588: d047 beq.n 800361a { /* Check if conditions to disable the ADC are fulfilled */ if (ADC_DISABLING_CONDITIONS(hadc) != RESET) - 80034ee: 687b ldr r3, [r7, #4] - 80034f0: 681b ldr r3, [r3, #0] - 80034f2: 689b ldr r3, [r3, #8] - 80034f4: f003 030d and.w r3, r3, #13 - 80034f8: 2b01 cmp r3, #1 - 80034fa: d10f bne.n 800351c + 800358a: 687b ldr r3, [r7, #4] + 800358c: 681b ldr r3, [r3, #0] + 800358e: 689b ldr r3, [r3, #8] + 8003590: f003 030d and.w r3, r3, #13 + 8003594: 2b01 cmp r3, #1 + 8003596: d10f bne.n 80035b8 { /* Disable the ADC peripheral */ __HAL_ADC_DISABLE(hadc); - 80034fc: 687b ldr r3, [r7, #4] - 80034fe: 681b ldr r3, [r3, #0] - 8003500: 689a ldr r2, [r3, #8] - 8003502: 687b ldr r3, [r7, #4] - 8003504: 681b ldr r3, [r3, #0] - 8003506: f042 0202 orr.w r2, r2, #2 - 800350a: 609a str r2, [r3, #8] - 800350c: 687b ldr r3, [r7, #4] - 800350e: 681b ldr r3, [r3, #0] - 8003510: 2203 movs r2, #3 - 8003512: 601a str r2, [r3, #0] + 8003598: 687b ldr r3, [r7, #4] + 800359a: 681b ldr r3, [r3, #0] + 800359c: 689a ldr r2, [r3, #8] + 800359e: 687b ldr r3, [r7, #4] + 80035a0: 681b ldr r3, [r3, #0] + 80035a2: f042 0202 orr.w r2, r2, #2 + 80035a6: 609a str r2, [r3, #8] + 80035a8: 687b ldr r3, [r7, #4] + 80035aa: 681b ldr r3, [r3, #0] + 80035ac: 2203 movs r2, #3 + 80035ae: 601a str r2, [r3, #0] return HAL_ERROR; } /* Wait for ADC effectively disabled */ tickstart = HAL_GetTick(); - 8003514: f7fe fea8 bl 8002268 - 8003518: 60f8 str r0, [r7, #12] + 80035b0: f7fe fea8 bl 8002304 + 80035b4: 60f8 str r0, [r7, #12] while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN)) - 800351a: e029 b.n 8003570 + 80035b6: e029 b.n 800360c SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - 800351c: 687b ldr r3, [r7, #4] - 800351e: 6c1b ldr r3, [r3, #64] @ 0x40 - 8003520: f043 0210 orr.w r2, r3, #16 - 8003524: 687b ldr r3, [r7, #4] - 8003526: 641a str r2, [r3, #64] @ 0x40 + 80035b8: 687b ldr r3, [r7, #4] + 80035ba: 6c1b ldr r3, [r3, #64] @ 0x40 + 80035bc: f043 0210 orr.w r2, r3, #16 + 80035c0: 687b ldr r3, [r7, #4] + 80035c2: 641a str r2, [r3, #64] @ 0x40 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - 8003528: 687b ldr r3, [r7, #4] - 800352a: 6c5b ldr r3, [r3, #68] @ 0x44 - 800352c: f043 0201 orr.w r2, r3, #1 - 8003530: 687b ldr r3, [r7, #4] - 8003532: 645a str r2, [r3, #68] @ 0x44 + 80035c4: 687b ldr r3, [r7, #4] + 80035c6: 6c5b ldr r3, [r3, #68] @ 0x44 + 80035c8: f043 0201 orr.w r2, r3, #1 + 80035cc: 687b ldr r3, [r7, #4] + 80035ce: 645a str r2, [r3, #68] @ 0x44 return HAL_ERROR; - 8003534: 2301 movs r3, #1 - 8003536: e023 b.n 8003580 + 80035d0: 2301 movs r3, #1 + 80035d2: e023 b.n 800361c { if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) - 8003538: f7fe fe96 bl 8002268 - 800353c: 4602 mov r2, r0 - 800353e: 68fb ldr r3, [r7, #12] - 8003540: 1ad3 subs r3, r2, r3 - 8003542: 2b02 cmp r3, #2 - 8003544: d914 bls.n 8003570 + 80035d4: f7fe fe96 bl 8002304 + 80035d8: 4602 mov r2, r0 + 80035da: 68fb ldr r3, [r7, #12] + 80035dc: 1ad3 subs r3, r2, r3 + 80035de: 2b02 cmp r3, #2 + 80035e0: d914 bls.n 800360c { /* New check to avoid false timeout detection in case of preemption */ if(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN)) - 8003546: 687b ldr r3, [r7, #4] - 8003548: 681b ldr r3, [r3, #0] - 800354a: 689b ldr r3, [r3, #8] - 800354c: f003 0301 and.w r3, r3, #1 - 8003550: 2b01 cmp r3, #1 - 8003552: d10d bne.n 8003570 + 80035e2: 687b ldr r3, [r7, #4] + 80035e4: 681b ldr r3, [r3, #0] + 80035e6: 689b ldr r3, [r3, #8] + 80035e8: f003 0301 and.w r3, r3, #1 + 80035ec: 2b01 cmp r3, #1 + 80035ee: d10d bne.n 800360c { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - 8003554: 687b ldr r3, [r7, #4] - 8003556: 6c1b ldr r3, [r3, #64] @ 0x40 - 8003558: f043 0210 orr.w r2, r3, #16 - 800355c: 687b ldr r3, [r7, #4] - 800355e: 641a str r2, [r3, #64] @ 0x40 + 80035f0: 687b ldr r3, [r7, #4] + 80035f2: 6c1b ldr r3, [r3, #64] @ 0x40 + 80035f4: f043 0210 orr.w r2, r3, #16 + 80035f8: 687b ldr r3, [r7, #4] + 80035fa: 641a str r2, [r3, #64] @ 0x40 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - 8003560: 687b ldr r3, [r7, #4] - 8003562: 6c5b ldr r3, [r3, #68] @ 0x44 - 8003564: f043 0201 orr.w r2, r3, #1 - 8003568: 687b ldr r3, [r7, #4] - 800356a: 645a str r2, [r3, #68] @ 0x44 + 80035fc: 687b ldr r3, [r7, #4] + 80035fe: 6c5b ldr r3, [r3, #68] @ 0x44 + 8003600: f043 0201 orr.w r2, r3, #1 + 8003604: 687b ldr r3, [r7, #4] + 8003606: 645a str r2, [r3, #68] @ 0x44 return HAL_ERROR; - 800356c: 2301 movs r3, #1 - 800356e: e007 b.n 8003580 + 8003608: 2301 movs r3, #1 + 800360a: e007 b.n 800361c while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN)) - 8003570: 687b ldr r3, [r7, #4] - 8003572: 681b ldr r3, [r3, #0] - 8003574: 689b ldr r3, [r3, #8] - 8003576: f003 0301 and.w r3, r3, #1 - 800357a: 2b01 cmp r3, #1 - 800357c: d0dc beq.n 8003538 + 800360c: 687b ldr r3, [r7, #4] + 800360e: 681b ldr r3, [r3, #0] + 8003610: 689b ldr r3, [r3, #8] + 8003612: f003 0301 and.w r3, r3, #1 + 8003616: 2b01 cmp r3, #1 + 8003618: d0dc beq.n 80035d4 } } } /* Return HAL status */ return HAL_OK; - 800357e: 2300 movs r3, #0 + 800361a: 2300 movs r3, #0 } - 8003580: 4618 mov r0, r3 - 8003582: 3710 adds r7, #16 - 8003584: 46bd mov sp, r7 - 8003586: bd80 pop {r7, pc} + 800361c: 4618 mov r0, r3 + 800361e: 3710 adds r7, #16 + 8003620: 46bd mov sp, r7 + 8003622: bd80 pop {r7, pc} -08003588 : +08003624 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan) { - 8003588: b580 push {r7, lr} - 800358a: b084 sub sp, #16 - 800358c: af00 add r7, sp, #0 - 800358e: 6078 str r0, [r7, #4] + 8003624: b580 push {r7, lr} + 8003626: b084 sub sp, #16 + 8003628: af00 add r7, sp, #0 + 800362a: 6078 str r0, [r7, #4] uint32_t tickstart; /* Check CAN handle */ if (hcan == NULL) - 8003590: 687b ldr r3, [r7, #4] - 8003592: 2b00 cmp r3, #0 - 8003594: d101 bne.n 800359a + 800362c: 687b ldr r3, [r7, #4] + 800362e: 2b00 cmp r3, #0 + 8003630: d101 bne.n 8003636 { return HAL_ERROR; - 8003596: 2301 movs r3, #1 - 8003598: e0ed b.n 8003776 + 8003632: 2301 movs r3, #1 + 8003634: e0ed b.n 8003812 /* Init the low level hardware: CLOCK, NVIC */ hcan->MspInitCallback(hcan); } #else if (hcan->State == HAL_CAN_STATE_RESET) - 800359a: 687b ldr r3, [r7, #4] - 800359c: f893 3020 ldrb.w r3, [r3, #32] - 80035a0: b2db uxtb r3, r3 - 80035a2: 2b00 cmp r3, #0 - 80035a4: d102 bne.n 80035ac + 8003636: 687b ldr r3, [r7, #4] + 8003638: f893 3020 ldrb.w r3, [r3, #32] + 800363c: b2db uxtb r3, r3 + 800363e: 2b00 cmp r3, #0 + 8003640: d102 bne.n 8003648 { /* Init the low level hardware: CLOCK, NVIC */ HAL_CAN_MspInit(hcan); - 80035a6: 6878 ldr r0, [r7, #4] - 80035a8: f7fe fc9a bl 8001ee0 + 8003642: 6878 ldr r0, [r7, #4] + 8003644: f7fe fc9a bl 8001f7c } #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ /* Request initialisation */ SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); - 80035ac: 687b ldr r3, [r7, #4] - 80035ae: 681b ldr r3, [r3, #0] - 80035b0: 681a ldr r2, [r3, #0] - 80035b2: 687b ldr r3, [r7, #4] - 80035b4: 681b ldr r3, [r3, #0] - 80035b6: f042 0201 orr.w r2, r2, #1 - 80035ba: 601a str r2, [r3, #0] + 8003648: 687b ldr r3, [r7, #4] + 800364a: 681b ldr r3, [r3, #0] + 800364c: 681a ldr r2, [r3, #0] + 800364e: 687b ldr r3, [r7, #4] + 8003650: 681b ldr r3, [r3, #0] + 8003652: f042 0201 orr.w r2, r2, #1 + 8003656: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); - 80035bc: f7fe fe54 bl 8002268 - 80035c0: 60f8 str r0, [r7, #12] + 8003658: f7fe fe54 bl 8002304 + 800365c: 60f8 str r0, [r7, #12] /* Wait initialisation acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) - 80035c2: e012 b.n 80035ea + 800365e: e012 b.n 8003686 { if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) - 80035c4: f7fe fe50 bl 8002268 - 80035c8: 4602 mov r2, r0 - 80035ca: 68fb ldr r3, [r7, #12] - 80035cc: 1ad3 subs r3, r2, r3 - 80035ce: 2b0a cmp r3, #10 - 80035d0: d90b bls.n 80035ea + 8003660: f7fe fe50 bl 8002304 + 8003664: 4602 mov r2, r0 + 8003666: 68fb ldr r3, [r7, #12] + 8003668: 1ad3 subs r3, r2, r3 + 800366a: 2b0a cmp r3, #10 + 800366c: d90b bls.n 8003686 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; - 80035d2: 687b ldr r3, [r7, #4] - 80035d4: 6a5b ldr r3, [r3, #36] @ 0x24 - 80035d6: f443 3200 orr.w r2, r3, #131072 @ 0x20000 - 80035da: 687b ldr r3, [r7, #4] - 80035dc: 625a str r2, [r3, #36] @ 0x24 + 800366e: 687b ldr r3, [r7, #4] + 8003670: 6a5b ldr r3, [r3, #36] @ 0x24 + 8003672: f443 3200 orr.w r2, r3, #131072 @ 0x20000 + 8003676: 687b ldr r3, [r7, #4] + 8003678: 625a str r2, [r3, #36] @ 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; - 80035de: 687b ldr r3, [r7, #4] - 80035e0: 2205 movs r2, #5 - 80035e2: f883 2020 strb.w r2, [r3, #32] + 800367a: 687b ldr r3, [r7, #4] + 800367c: 2205 movs r2, #5 + 800367e: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; - 80035e6: 2301 movs r3, #1 - 80035e8: e0c5 b.n 8003776 + 8003682: 2301 movs r3, #1 + 8003684: e0c5 b.n 8003812 while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) - 80035ea: 687b ldr r3, [r7, #4] - 80035ec: 681b ldr r3, [r3, #0] - 80035ee: 685b ldr r3, [r3, #4] - 80035f0: f003 0301 and.w r3, r3, #1 - 80035f4: 2b00 cmp r3, #0 - 80035f6: d0e5 beq.n 80035c4 + 8003686: 687b ldr r3, [r7, #4] + 8003688: 681b ldr r3, [r3, #0] + 800368a: 685b ldr r3, [r3, #4] + 800368c: f003 0301 and.w r3, r3, #1 + 8003690: 2b00 cmp r3, #0 + 8003692: d0e5 beq.n 8003660 } } /* Exit from sleep mode */ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); - 80035f8: 687b ldr r3, [r7, #4] - 80035fa: 681b ldr r3, [r3, #0] - 80035fc: 681a ldr r2, [r3, #0] - 80035fe: 687b ldr r3, [r7, #4] - 8003600: 681b ldr r3, [r3, #0] - 8003602: f022 0202 bic.w r2, r2, #2 - 8003606: 601a str r2, [r3, #0] + 8003694: 687b ldr r3, [r7, #4] + 8003696: 681b ldr r3, [r3, #0] + 8003698: 681a ldr r2, [r3, #0] + 800369a: 687b ldr r3, [r7, #4] + 800369c: 681b ldr r3, [r3, #0] + 800369e: f022 0202 bic.w r2, r2, #2 + 80036a2: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); - 8003608: f7fe fe2e bl 8002268 - 800360c: 60f8 str r0, [r7, #12] + 80036a4: f7fe fe2e bl 8002304 + 80036a8: 60f8 str r0, [r7, #12] /* Check Sleep mode leave acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) - 800360e: e012 b.n 8003636 + 80036aa: e012 b.n 80036d2 { if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) - 8003610: f7fe fe2a bl 8002268 - 8003614: 4602 mov r2, r0 - 8003616: 68fb ldr r3, [r7, #12] - 8003618: 1ad3 subs r3, r2, r3 - 800361a: 2b0a cmp r3, #10 - 800361c: d90b bls.n 8003636 + 80036ac: f7fe fe2a bl 8002304 + 80036b0: 4602 mov r2, r0 + 80036b2: 68fb ldr r3, [r7, #12] + 80036b4: 1ad3 subs r3, r2, r3 + 80036b6: 2b0a cmp r3, #10 + 80036b8: d90b bls.n 80036d2 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; - 800361e: 687b ldr r3, [r7, #4] - 8003620: 6a5b ldr r3, [r3, #36] @ 0x24 - 8003622: f443 3200 orr.w r2, r3, #131072 @ 0x20000 - 8003626: 687b ldr r3, [r7, #4] - 8003628: 625a str r2, [r3, #36] @ 0x24 + 80036ba: 687b ldr r3, [r7, #4] + 80036bc: 6a5b ldr r3, [r3, #36] @ 0x24 + 80036be: f443 3200 orr.w r2, r3, #131072 @ 0x20000 + 80036c2: 687b ldr r3, [r7, #4] + 80036c4: 625a str r2, [r3, #36] @ 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; - 800362a: 687b ldr r3, [r7, #4] - 800362c: 2205 movs r2, #5 - 800362e: f883 2020 strb.w r2, [r3, #32] + 80036c6: 687b ldr r3, [r7, #4] + 80036c8: 2205 movs r2, #5 + 80036ca: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; - 8003632: 2301 movs r3, #1 - 8003634: e09f b.n 8003776 + 80036ce: 2301 movs r3, #1 + 80036d0: e09f b.n 8003812 while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) - 8003636: 687b ldr r3, [r7, #4] - 8003638: 681b ldr r3, [r3, #0] - 800363a: 685b ldr r3, [r3, #4] - 800363c: f003 0302 and.w r3, r3, #2 - 8003640: 2b00 cmp r3, #0 - 8003642: d1e5 bne.n 8003610 + 80036d2: 687b ldr r3, [r7, #4] + 80036d4: 681b ldr r3, [r3, #0] + 80036d6: 685b ldr r3, [r3, #4] + 80036d8: f003 0302 and.w r3, r3, #2 + 80036dc: 2b00 cmp r3, #0 + 80036de: d1e5 bne.n 80036ac } } /* Set the time triggered communication mode */ if (hcan->Init.TimeTriggeredMode == ENABLE) - 8003644: 687b ldr r3, [r7, #4] - 8003646: 7e1b ldrb r3, [r3, #24] - 8003648: 2b01 cmp r3, #1 - 800364a: d108 bne.n 800365e + 80036e0: 687b ldr r3, [r7, #4] + 80036e2: 7e1b ldrb r3, [r3, #24] + 80036e4: 2b01 cmp r3, #1 + 80036e6: d108 bne.n 80036fa { SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); - 800364c: 687b ldr r3, [r7, #4] - 800364e: 681b ldr r3, [r3, #0] - 8003650: 681a ldr r2, [r3, #0] - 8003652: 687b ldr r3, [r7, #4] - 8003654: 681b ldr r3, [r3, #0] - 8003656: f042 0280 orr.w r2, r2, #128 @ 0x80 - 800365a: 601a str r2, [r3, #0] - 800365c: e007 b.n 800366e + 80036e8: 687b ldr r3, [r7, #4] + 80036ea: 681b ldr r3, [r3, #0] + 80036ec: 681a ldr r2, [r3, #0] + 80036ee: 687b ldr r3, [r7, #4] + 80036f0: 681b ldr r3, [r3, #0] + 80036f2: f042 0280 orr.w r2, r2, #128 @ 0x80 + 80036f6: 601a str r2, [r3, #0] + 80036f8: e007 b.n 800370a } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); - 800365e: 687b ldr r3, [r7, #4] - 8003660: 681b ldr r3, [r3, #0] - 8003662: 681a ldr r2, [r3, #0] - 8003664: 687b ldr r3, [r7, #4] - 8003666: 681b ldr r3, [r3, #0] - 8003668: f022 0280 bic.w r2, r2, #128 @ 0x80 - 800366c: 601a str r2, [r3, #0] + 80036fa: 687b ldr r3, [r7, #4] + 80036fc: 681b ldr r3, [r3, #0] + 80036fe: 681a ldr r2, [r3, #0] + 8003700: 687b ldr r3, [r7, #4] + 8003702: 681b ldr r3, [r3, #0] + 8003704: f022 0280 bic.w r2, r2, #128 @ 0x80 + 8003708: 601a str r2, [r3, #0] } /* Set the automatic bus-off management */ if (hcan->Init.AutoBusOff == ENABLE) - 800366e: 687b ldr r3, [r7, #4] - 8003670: 7e5b ldrb r3, [r3, #25] - 8003672: 2b01 cmp r3, #1 - 8003674: d108 bne.n 8003688 + 800370a: 687b ldr r3, [r7, #4] + 800370c: 7e5b ldrb r3, [r3, #25] + 800370e: 2b01 cmp r3, #1 + 8003710: d108 bne.n 8003724 { SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); - 8003676: 687b ldr r3, [r7, #4] - 8003678: 681b ldr r3, [r3, #0] - 800367a: 681a ldr r2, [r3, #0] - 800367c: 687b ldr r3, [r7, #4] - 800367e: 681b ldr r3, [r3, #0] - 8003680: f042 0240 orr.w r2, r2, #64 @ 0x40 - 8003684: 601a str r2, [r3, #0] - 8003686: e007 b.n 8003698 + 8003712: 687b ldr r3, [r7, #4] + 8003714: 681b ldr r3, [r3, #0] + 8003716: 681a ldr r2, [r3, #0] + 8003718: 687b ldr r3, [r7, #4] + 800371a: 681b ldr r3, [r3, #0] + 800371c: f042 0240 orr.w r2, r2, #64 @ 0x40 + 8003720: 601a str r2, [r3, #0] + 8003722: e007 b.n 8003734 } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); - 8003688: 687b ldr r3, [r7, #4] - 800368a: 681b ldr r3, [r3, #0] - 800368c: 681a ldr r2, [r3, #0] - 800368e: 687b ldr r3, [r7, #4] - 8003690: 681b ldr r3, [r3, #0] - 8003692: f022 0240 bic.w r2, r2, #64 @ 0x40 - 8003696: 601a str r2, [r3, #0] + 8003724: 687b ldr r3, [r7, #4] + 8003726: 681b ldr r3, [r3, #0] + 8003728: 681a ldr r2, [r3, #0] + 800372a: 687b ldr r3, [r7, #4] + 800372c: 681b ldr r3, [r3, #0] + 800372e: f022 0240 bic.w r2, r2, #64 @ 0x40 + 8003732: 601a str r2, [r3, #0] } /* Set the automatic wake-up mode */ if (hcan->Init.AutoWakeUp == ENABLE) - 8003698: 687b ldr r3, [r7, #4] - 800369a: 7e9b ldrb r3, [r3, #26] - 800369c: 2b01 cmp r3, #1 - 800369e: d108 bne.n 80036b2 + 8003734: 687b ldr r3, [r7, #4] + 8003736: 7e9b ldrb r3, [r3, #26] + 8003738: 2b01 cmp r3, #1 + 800373a: d108 bne.n 800374e { SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); - 80036a0: 687b ldr r3, [r7, #4] - 80036a2: 681b ldr r3, [r3, #0] - 80036a4: 681a ldr r2, [r3, #0] - 80036a6: 687b ldr r3, [r7, #4] - 80036a8: 681b ldr r3, [r3, #0] - 80036aa: f042 0220 orr.w r2, r2, #32 - 80036ae: 601a str r2, [r3, #0] - 80036b0: e007 b.n 80036c2 + 800373c: 687b ldr r3, [r7, #4] + 800373e: 681b ldr r3, [r3, #0] + 8003740: 681a ldr r2, [r3, #0] + 8003742: 687b ldr r3, [r7, #4] + 8003744: 681b ldr r3, [r3, #0] + 8003746: f042 0220 orr.w r2, r2, #32 + 800374a: 601a str r2, [r3, #0] + 800374c: e007 b.n 800375e } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); - 80036b2: 687b ldr r3, [r7, #4] - 80036b4: 681b ldr r3, [r3, #0] - 80036b6: 681a ldr r2, [r3, #0] - 80036b8: 687b ldr r3, [r7, #4] - 80036ba: 681b ldr r3, [r3, #0] - 80036bc: f022 0220 bic.w r2, r2, #32 - 80036c0: 601a str r2, [r3, #0] + 800374e: 687b ldr r3, [r7, #4] + 8003750: 681b ldr r3, [r3, #0] + 8003752: 681a ldr r2, [r3, #0] + 8003754: 687b ldr r3, [r7, #4] + 8003756: 681b ldr r3, [r3, #0] + 8003758: f022 0220 bic.w r2, r2, #32 + 800375c: 601a str r2, [r3, #0] } /* Set the automatic retransmission */ if (hcan->Init.AutoRetransmission == ENABLE) - 80036c2: 687b ldr r3, [r7, #4] - 80036c4: 7edb ldrb r3, [r3, #27] - 80036c6: 2b01 cmp r3, #1 - 80036c8: d108 bne.n 80036dc + 800375e: 687b ldr r3, [r7, #4] + 8003760: 7edb ldrb r3, [r3, #27] + 8003762: 2b01 cmp r3, #1 + 8003764: d108 bne.n 8003778 { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART); - 80036ca: 687b ldr r3, [r7, #4] - 80036cc: 681b ldr r3, [r3, #0] - 80036ce: 681a ldr r2, [r3, #0] - 80036d0: 687b ldr r3, [r7, #4] - 80036d2: 681b ldr r3, [r3, #0] - 80036d4: f022 0210 bic.w r2, r2, #16 - 80036d8: 601a str r2, [r3, #0] - 80036da: e007 b.n 80036ec + 8003766: 687b ldr r3, [r7, #4] + 8003768: 681b ldr r3, [r3, #0] + 800376a: 681a ldr r2, [r3, #0] + 800376c: 687b ldr r3, [r7, #4] + 800376e: 681b ldr r3, [r3, #0] + 8003770: f022 0210 bic.w r2, r2, #16 + 8003774: 601a str r2, [r3, #0] + 8003776: e007 b.n 8003788 } else { SET_BIT(hcan->Instance->MCR, CAN_MCR_NART); - 80036dc: 687b ldr r3, [r7, #4] - 80036de: 681b ldr r3, [r3, #0] - 80036e0: 681a ldr r2, [r3, #0] - 80036e2: 687b ldr r3, [r7, #4] - 80036e4: 681b ldr r3, [r3, #0] - 80036e6: f042 0210 orr.w r2, r2, #16 - 80036ea: 601a str r2, [r3, #0] + 8003778: 687b ldr r3, [r7, #4] + 800377a: 681b ldr r3, [r3, #0] + 800377c: 681a ldr r2, [r3, #0] + 800377e: 687b ldr r3, [r7, #4] + 8003780: 681b ldr r3, [r3, #0] + 8003782: f042 0210 orr.w r2, r2, #16 + 8003786: 601a str r2, [r3, #0] } /* Set the receive FIFO locked mode */ if (hcan->Init.ReceiveFifoLocked == ENABLE) - 80036ec: 687b ldr r3, [r7, #4] - 80036ee: 7f1b ldrb r3, [r3, #28] - 80036f0: 2b01 cmp r3, #1 - 80036f2: d108 bne.n 8003706 + 8003788: 687b ldr r3, [r7, #4] + 800378a: 7f1b ldrb r3, [r3, #28] + 800378c: 2b01 cmp r3, #1 + 800378e: d108 bne.n 80037a2 { SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); - 80036f4: 687b ldr r3, [r7, #4] - 80036f6: 681b ldr r3, [r3, #0] - 80036f8: 681a ldr r2, [r3, #0] - 80036fa: 687b ldr r3, [r7, #4] - 80036fc: 681b ldr r3, [r3, #0] - 80036fe: f042 0208 orr.w r2, r2, #8 - 8003702: 601a str r2, [r3, #0] - 8003704: e007 b.n 8003716 + 8003790: 687b ldr r3, [r7, #4] + 8003792: 681b ldr r3, [r3, #0] + 8003794: 681a ldr r2, [r3, #0] + 8003796: 687b ldr r3, [r7, #4] + 8003798: 681b ldr r3, [r3, #0] + 800379a: f042 0208 orr.w r2, r2, #8 + 800379e: 601a str r2, [r3, #0] + 80037a0: e007 b.n 80037b2 } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); - 8003706: 687b ldr r3, [r7, #4] - 8003708: 681b ldr r3, [r3, #0] - 800370a: 681a ldr r2, [r3, #0] - 800370c: 687b ldr r3, [r7, #4] - 800370e: 681b ldr r3, [r3, #0] - 8003710: f022 0208 bic.w r2, r2, #8 - 8003714: 601a str r2, [r3, #0] + 80037a2: 687b ldr r3, [r7, #4] + 80037a4: 681b ldr r3, [r3, #0] + 80037a6: 681a ldr r2, [r3, #0] + 80037a8: 687b ldr r3, [r7, #4] + 80037aa: 681b ldr r3, [r3, #0] + 80037ac: f022 0208 bic.w r2, r2, #8 + 80037b0: 601a str r2, [r3, #0] } /* Set the transmit FIFO priority */ if (hcan->Init.TransmitFifoPriority == ENABLE) - 8003716: 687b ldr r3, [r7, #4] - 8003718: 7f5b ldrb r3, [r3, #29] - 800371a: 2b01 cmp r3, #1 - 800371c: d108 bne.n 8003730 + 80037b2: 687b ldr r3, [r7, #4] + 80037b4: 7f5b ldrb r3, [r3, #29] + 80037b6: 2b01 cmp r3, #1 + 80037b8: d108 bne.n 80037cc { SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); - 800371e: 687b ldr r3, [r7, #4] - 8003720: 681b ldr r3, [r3, #0] - 8003722: 681a ldr r2, [r3, #0] - 8003724: 687b ldr r3, [r7, #4] - 8003726: 681b ldr r3, [r3, #0] - 8003728: f042 0204 orr.w r2, r2, #4 - 800372c: 601a str r2, [r3, #0] - 800372e: e007 b.n 8003740 + 80037ba: 687b ldr r3, [r7, #4] + 80037bc: 681b ldr r3, [r3, #0] + 80037be: 681a ldr r2, [r3, #0] + 80037c0: 687b ldr r3, [r7, #4] + 80037c2: 681b ldr r3, [r3, #0] + 80037c4: f042 0204 orr.w r2, r2, #4 + 80037c8: 601a str r2, [r3, #0] + 80037ca: e007 b.n 80037dc } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); - 8003730: 687b ldr r3, [r7, #4] - 8003732: 681b ldr r3, [r3, #0] - 8003734: 681a ldr r2, [r3, #0] - 8003736: 687b ldr r3, [r7, #4] - 8003738: 681b ldr r3, [r3, #0] - 800373a: f022 0204 bic.w r2, r2, #4 - 800373e: 601a str r2, [r3, #0] + 80037cc: 687b ldr r3, [r7, #4] + 80037ce: 681b ldr r3, [r3, #0] + 80037d0: 681a ldr r2, [r3, #0] + 80037d2: 687b ldr r3, [r7, #4] + 80037d4: 681b ldr r3, [r3, #0] + 80037d6: f022 0204 bic.w r2, r2, #4 + 80037da: 601a str r2, [r3, #0] } /* Set the bit timing register */ WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode | - 8003740: 687b ldr r3, [r7, #4] - 8003742: 689a ldr r2, [r3, #8] - 8003744: 687b ldr r3, [r7, #4] - 8003746: 68db ldr r3, [r3, #12] - 8003748: 431a orrs r2, r3 - 800374a: 687b ldr r3, [r7, #4] - 800374c: 691b ldr r3, [r3, #16] - 800374e: 431a orrs r2, r3 - 8003750: 687b ldr r3, [r7, #4] - 8003752: 695b ldr r3, [r3, #20] - 8003754: ea42 0103 orr.w r1, r2, r3 - 8003758: 687b ldr r3, [r7, #4] - 800375a: 685b ldr r3, [r3, #4] - 800375c: 1e5a subs r2, r3, #1 - 800375e: 687b ldr r3, [r7, #4] - 8003760: 681b ldr r3, [r3, #0] - 8003762: 430a orrs r2, r1 - 8003764: 61da str r2, [r3, #28] + 80037dc: 687b ldr r3, [r7, #4] + 80037de: 689a ldr r2, [r3, #8] + 80037e0: 687b ldr r3, [r7, #4] + 80037e2: 68db ldr r3, [r3, #12] + 80037e4: 431a orrs r2, r3 + 80037e6: 687b ldr r3, [r7, #4] + 80037e8: 691b ldr r3, [r3, #16] + 80037ea: 431a orrs r2, r3 + 80037ec: 687b ldr r3, [r7, #4] + 80037ee: 695b ldr r3, [r3, #20] + 80037f0: ea42 0103 orr.w r1, r2, r3 + 80037f4: 687b ldr r3, [r7, #4] + 80037f6: 685b ldr r3, [r3, #4] + 80037f8: 1e5a subs r2, r3, #1 + 80037fa: 687b ldr r3, [r7, #4] + 80037fc: 681b ldr r3, [r3, #0] + 80037fe: 430a orrs r2, r1 + 8003800: 61da str r2, [r3, #28] hcan->Init.TimeSeg1 | hcan->Init.TimeSeg2 | (hcan->Init.Prescaler - 1U))); /* Initialize the error code */ hcan->ErrorCode = HAL_CAN_ERROR_NONE; - 8003766: 687b ldr r3, [r7, #4] - 8003768: 2200 movs r2, #0 - 800376a: 625a str r2, [r3, #36] @ 0x24 + 8003802: 687b ldr r3, [r7, #4] + 8003804: 2200 movs r2, #0 + 8003806: 625a str r2, [r3, #36] @ 0x24 /* Initialize the CAN state */ hcan->State = HAL_CAN_STATE_READY; - 800376c: 687b ldr r3, [r7, #4] - 800376e: 2201 movs r2, #1 - 8003770: f883 2020 strb.w r2, [r3, #32] + 8003808: 687b ldr r3, [r7, #4] + 800380a: 2201 movs r2, #1 + 800380c: f883 2020 strb.w r2, [r3, #32] /* Return function status */ return HAL_OK; - 8003774: 2300 movs r3, #0 + 8003810: 2300 movs r3, #0 } - 8003776: 4618 mov r0, r3 - 8003778: 3710 adds r7, #16 - 800377a: 46bd mov sp, r7 - 800377c: bd80 pop {r7, pc} + 8003812: 4618 mov r0, r3 + 8003814: 3710 adds r7, #16 + 8003816: 46bd mov sp, r7 + 8003818: bd80 pop {r7, pc} -0800377e : +0800381a : * @param sFilterConfig pointer to a CAN_FilterTypeDef structure that * contains the filter configuration information. * @retval None */ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_FilterTypeDef *sFilterConfig) { - 800377e: b480 push {r7} - 8003780: b087 sub sp, #28 - 8003782: af00 add r7, sp, #0 - 8003784: 6078 str r0, [r7, #4] - 8003786: 6039 str r1, [r7, #0] + 800381a: b480 push {r7} + 800381c: b087 sub sp, #28 + 800381e: af00 add r7, sp, #0 + 8003820: 6078 str r0, [r7, #4] + 8003822: 6039 str r1, [r7, #0] uint32_t filternbrbitpos; CAN_TypeDef *can_ip = hcan->Instance; - 8003788: 687b ldr r3, [r7, #4] - 800378a: 681b ldr r3, [r3, #0] - 800378c: 617b str r3, [r7, #20] + 8003824: 687b ldr r3, [r7, #4] + 8003826: 681b ldr r3, [r3, #0] + 8003828: 617b str r3, [r7, #20] HAL_CAN_StateTypeDef state = hcan->State; - 800378e: 687b ldr r3, [r7, #4] - 8003790: f893 3020 ldrb.w r3, [r3, #32] - 8003794: 74fb strb r3, [r7, #19] + 800382a: 687b ldr r3, [r7, #4] + 800382c: f893 3020 ldrb.w r3, [r3, #32] + 8003830: 74fb strb r3, [r7, #19] if ((state == HAL_CAN_STATE_READY) || - 8003796: 7cfb ldrb r3, [r7, #19] - 8003798: 2b01 cmp r3, #1 - 800379a: d003 beq.n 80037a4 - 800379c: 7cfb ldrb r3, [r7, #19] - 800379e: 2b02 cmp r3, #2 - 80037a0: f040 80aa bne.w 80038f8 + 8003832: 7cfb ldrb r3, [r7, #19] + 8003834: 2b01 cmp r3, #1 + 8003836: d003 beq.n 8003840 + 8003838: 7cfb ldrb r3, [r7, #19] + 800383a: 2b02 cmp r3, #2 + 800383c: f040 80aa bne.w 8003994 /* Check the parameters */ assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank)); /* Initialisation mode for the filter */ SET_BIT(can_ip->FMR, CAN_FMR_FINIT); - 80037a4: 697b ldr r3, [r7, #20] - 80037a6: f8d3 3200 ldr.w r3, [r3, #512] @ 0x200 - 80037aa: f043 0201 orr.w r2, r3, #1 - 80037ae: 697b ldr r3, [r7, #20] - 80037b0: f8c3 2200 str.w r2, [r3, #512] @ 0x200 + 8003840: 697b ldr r3, [r7, #20] + 8003842: f8d3 3200 ldr.w r3, [r3, #512] @ 0x200 + 8003846: f043 0201 orr.w r2, r3, #1 + 800384a: 697b ldr r3, [r7, #20] + 800384c: f8c3 2200 str.w r2, [r3, #512] @ 0x200 /* Convert filter number into bit position */ filternbrbitpos = (uint32_t)1 << (sFilterConfig->FilterBank & 0x1FU); - 80037b4: 683b ldr r3, [r7, #0] - 80037b6: 695b ldr r3, [r3, #20] - 80037b8: f003 031f and.w r3, r3, #31 - 80037bc: 2201 movs r2, #1 - 80037be: fa02 f303 lsl.w r3, r2, r3 - 80037c2: 60fb str r3, [r7, #12] + 8003850: 683b ldr r3, [r7, #0] + 8003852: 695b ldr r3, [r3, #20] + 8003854: f003 031f and.w r3, r3, #31 + 8003858: 2201 movs r2, #1 + 800385a: fa02 f303 lsl.w r3, r2, r3 + 800385e: 60fb str r3, [r7, #12] /* Filter Deactivation */ CLEAR_BIT(can_ip->FA1R, filternbrbitpos); - 80037c4: 697b ldr r3, [r7, #20] - 80037c6: f8d3 221c ldr.w r2, [r3, #540] @ 0x21c - 80037ca: 68fb ldr r3, [r7, #12] - 80037cc: 43db mvns r3, r3 - 80037ce: 401a ands r2, r3 - 80037d0: 697b ldr r3, [r7, #20] - 80037d2: f8c3 221c str.w r2, [r3, #540] @ 0x21c + 8003860: 697b ldr r3, [r7, #20] + 8003862: f8d3 221c ldr.w r2, [r3, #540] @ 0x21c + 8003866: 68fb ldr r3, [r7, #12] + 8003868: 43db mvns r3, r3 + 800386a: 401a ands r2, r3 + 800386c: 697b ldr r3, [r7, #20] + 800386e: f8c3 221c str.w r2, [r3, #540] @ 0x21c /* Filter Scale */ if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT) - 80037d6: 683b ldr r3, [r7, #0] - 80037d8: 69db ldr r3, [r3, #28] - 80037da: 2b00 cmp r3, #0 - 80037dc: d123 bne.n 8003826 + 8003872: 683b ldr r3, [r7, #0] + 8003874: 69db ldr r3, [r3, #28] + 8003876: 2b00 cmp r3, #0 + 8003878: d123 bne.n 80038c2 { /* 16-bit scale for the filter */ CLEAR_BIT(can_ip->FS1R, filternbrbitpos); - 80037de: 697b ldr r3, [r7, #20] - 80037e0: f8d3 220c ldr.w r2, [r3, #524] @ 0x20c - 80037e4: 68fb ldr r3, [r7, #12] - 80037e6: 43db mvns r3, r3 - 80037e8: 401a ands r2, r3 - 80037ea: 697b ldr r3, [r7, #20] - 80037ec: f8c3 220c str.w r2, [r3, #524] @ 0x20c + 800387a: 697b ldr r3, [r7, #20] + 800387c: f8d3 220c ldr.w r2, [r3, #524] @ 0x20c + 8003880: 68fb ldr r3, [r7, #12] + 8003882: 43db mvns r3, r3 + 8003884: 401a ands r2, r3 + 8003886: 697b ldr r3, [r7, #20] + 8003888: f8c3 220c str.w r2, [r3, #524] @ 0x20c /* First 16-bit identifier and First 16-bit mask */ /* Or First 16-bit identifier and Second 16-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | - 80037f0: 683b ldr r3, [r7, #0] - 80037f2: 68db ldr r3, [r3, #12] - 80037f4: 0419 lsls r1, r3, #16 + 800388c: 683b ldr r3, [r7, #0] + 800388e: 68db ldr r3, [r3, #12] + 8003890: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); - 80037f6: 683b ldr r3, [r7, #0] - 80037f8: 685b ldr r3, [r3, #4] - 80037fa: b29b uxth r3, r3 + 8003892: 683b ldr r3, [r7, #0] + 8003894: 685b ldr r3, [r3, #4] + 8003896: b29b uxth r3, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = - 80037fc: 683a ldr r2, [r7, #0] - 80037fe: 6952 ldr r2, [r2, #20] + 8003898: 683a ldr r2, [r7, #0] + 800389a: 6952 ldr r2, [r2, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | - 8003800: 4319 orrs r1, r3 + 800389c: 4319 orrs r1, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = - 8003802: 697b ldr r3, [r7, #20] - 8003804: 3248 adds r2, #72 @ 0x48 - 8003806: f843 1032 str.w r1, [r3, r2, lsl #3] + 800389e: 697b ldr r3, [r7, #20] + 80038a0: 3248 adds r2, #72 @ 0x48 + 80038a2: f843 1032 str.w r1, [r3, r2, lsl #3] /* Second 16-bit identifier and Second 16-bit mask */ /* Or Third 16-bit identifier and Fourth 16-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | - 800380a: 683b ldr r3, [r7, #0] - 800380c: 689b ldr r3, [r3, #8] - 800380e: 0419 lsls r1, r3, #16 + 80038a6: 683b ldr r3, [r7, #0] + 80038a8: 689b ldr r3, [r3, #8] + 80038aa: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh); - 8003810: 683b ldr r3, [r7, #0] - 8003812: 681b ldr r3, [r3, #0] - 8003814: b29a uxth r2, r3 + 80038ac: 683b ldr r3, [r7, #0] + 80038ae: 681b ldr r3, [r3, #0] + 80038b0: b29a uxth r2, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = - 8003816: 683b ldr r3, [r7, #0] - 8003818: 695b ldr r3, [r3, #20] + 80038b2: 683b ldr r3, [r7, #0] + 80038b4: 695b ldr r3, [r3, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | - 800381a: 430a orrs r2, r1 + 80038b6: 430a orrs r2, r1 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = - 800381c: 6979 ldr r1, [r7, #20] - 800381e: 3348 adds r3, #72 @ 0x48 - 8003820: 00db lsls r3, r3, #3 - 8003822: 440b add r3, r1 - 8003824: 605a str r2, [r3, #4] + 80038b8: 6979 ldr r1, [r7, #20] + 80038ba: 3348 adds r3, #72 @ 0x48 + 80038bc: 00db lsls r3, r3, #3 + 80038be: 440b add r3, r1 + 80038c0: 605a str r2, [r3, #4] } if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT) - 8003826: 683b ldr r3, [r7, #0] - 8003828: 69db ldr r3, [r3, #28] - 800382a: 2b01 cmp r3, #1 - 800382c: d122 bne.n 8003874 + 80038c2: 683b ldr r3, [r7, #0] + 80038c4: 69db ldr r3, [r3, #28] + 80038c6: 2b01 cmp r3, #1 + 80038c8: d122 bne.n 8003910 { /* 32-bit scale for the filter */ SET_BIT(can_ip->FS1R, filternbrbitpos); - 800382e: 697b ldr r3, [r7, #20] - 8003830: f8d3 220c ldr.w r2, [r3, #524] @ 0x20c - 8003834: 68fb ldr r3, [r7, #12] - 8003836: 431a orrs r2, r3 - 8003838: 697b ldr r3, [r7, #20] - 800383a: f8c3 220c str.w r2, [r3, #524] @ 0x20c + 80038ca: 697b ldr r3, [r7, #20] + 80038cc: f8d3 220c ldr.w r2, [r3, #524] @ 0x20c + 80038d0: 68fb ldr r3, [r7, #12] + 80038d2: 431a orrs r2, r3 + 80038d4: 697b ldr r3, [r7, #20] + 80038d6: f8c3 220c str.w r2, [r3, #524] @ 0x20c /* 32-bit identifier or First 32-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | - 800383e: 683b ldr r3, [r7, #0] - 8003840: 681b ldr r3, [r3, #0] - 8003842: 0419 lsls r1, r3, #16 + 80038da: 683b ldr r3, [r7, #0] + 80038dc: 681b ldr r3, [r3, #0] + 80038de: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); - 8003844: 683b ldr r3, [r7, #0] - 8003846: 685b ldr r3, [r3, #4] - 8003848: b29b uxth r3, r3 + 80038e0: 683b ldr r3, [r7, #0] + 80038e2: 685b ldr r3, [r3, #4] + 80038e4: b29b uxth r3, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = - 800384a: 683a ldr r2, [r7, #0] - 800384c: 6952 ldr r2, [r2, #20] + 80038e6: 683a ldr r2, [r7, #0] + 80038e8: 6952 ldr r2, [r2, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | - 800384e: 4319 orrs r1, r3 + 80038ea: 4319 orrs r1, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = - 8003850: 697b ldr r3, [r7, #20] - 8003852: 3248 adds r2, #72 @ 0x48 - 8003854: f843 1032 str.w r1, [r3, r2, lsl #3] + 80038ec: 697b ldr r3, [r7, #20] + 80038ee: 3248 adds r2, #72 @ 0x48 + 80038f0: f843 1032 str.w r1, [r3, r2, lsl #3] /* 32-bit mask or Second 32-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | - 8003858: 683b ldr r3, [r7, #0] - 800385a: 689b ldr r3, [r3, #8] - 800385c: 0419 lsls r1, r3, #16 + 80038f4: 683b ldr r3, [r7, #0] + 80038f6: 689b ldr r3, [r3, #8] + 80038f8: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow); - 800385e: 683b ldr r3, [r7, #0] - 8003860: 68db ldr r3, [r3, #12] - 8003862: b29a uxth r2, r3 + 80038fa: 683b ldr r3, [r7, #0] + 80038fc: 68db ldr r3, [r3, #12] + 80038fe: b29a uxth r2, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = - 8003864: 683b ldr r3, [r7, #0] - 8003866: 695b ldr r3, [r3, #20] + 8003900: 683b ldr r3, [r7, #0] + 8003902: 695b ldr r3, [r3, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | - 8003868: 430a orrs r2, r1 + 8003904: 430a orrs r2, r1 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = - 800386a: 6979 ldr r1, [r7, #20] - 800386c: 3348 adds r3, #72 @ 0x48 - 800386e: 00db lsls r3, r3, #3 - 8003870: 440b add r3, r1 - 8003872: 605a str r2, [r3, #4] + 8003906: 6979 ldr r1, [r7, #20] + 8003908: 3348 adds r3, #72 @ 0x48 + 800390a: 00db lsls r3, r3, #3 + 800390c: 440b add r3, r1 + 800390e: 605a str r2, [r3, #4] } /* Filter Mode */ if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK) - 8003874: 683b ldr r3, [r7, #0] - 8003876: 699b ldr r3, [r3, #24] - 8003878: 2b00 cmp r3, #0 - 800387a: d109 bne.n 8003890 + 8003910: 683b ldr r3, [r7, #0] + 8003912: 699b ldr r3, [r3, #24] + 8003914: 2b00 cmp r3, #0 + 8003916: d109 bne.n 800392c { /* Id/Mask mode for the filter*/ CLEAR_BIT(can_ip->FM1R, filternbrbitpos); - 800387c: 697b ldr r3, [r7, #20] - 800387e: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204 - 8003882: 68fb ldr r3, [r7, #12] - 8003884: 43db mvns r3, r3 - 8003886: 401a ands r2, r3 - 8003888: 697b ldr r3, [r7, #20] - 800388a: f8c3 2204 str.w r2, [r3, #516] @ 0x204 - 800388e: e007 b.n 80038a0 + 8003918: 697b ldr r3, [r7, #20] + 800391a: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204 + 800391e: 68fb ldr r3, [r7, #12] + 8003920: 43db mvns r3, r3 + 8003922: 401a ands r2, r3 + 8003924: 697b ldr r3, [r7, #20] + 8003926: f8c3 2204 str.w r2, [r3, #516] @ 0x204 + 800392a: e007 b.n 800393c } else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ { /* Identifier list mode for the filter*/ SET_BIT(can_ip->FM1R, filternbrbitpos); - 8003890: 697b ldr r3, [r7, #20] - 8003892: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204 - 8003896: 68fb ldr r3, [r7, #12] - 8003898: 431a orrs r2, r3 - 800389a: 697b ldr r3, [r7, #20] - 800389c: f8c3 2204 str.w r2, [r3, #516] @ 0x204 + 800392c: 697b ldr r3, [r7, #20] + 800392e: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204 + 8003932: 68fb ldr r3, [r7, #12] + 8003934: 431a orrs r2, r3 + 8003936: 697b ldr r3, [r7, #20] + 8003938: f8c3 2204 str.w r2, [r3, #516] @ 0x204 } /* Filter FIFO assignment */ if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0) - 80038a0: 683b ldr r3, [r7, #0] - 80038a2: 691b ldr r3, [r3, #16] - 80038a4: 2b00 cmp r3, #0 - 80038a6: d109 bne.n 80038bc + 800393c: 683b ldr r3, [r7, #0] + 800393e: 691b ldr r3, [r3, #16] + 8003940: 2b00 cmp r3, #0 + 8003942: d109 bne.n 8003958 { /* FIFO 0 assignation for the filter */ CLEAR_BIT(can_ip->FFA1R, filternbrbitpos); - 80038a8: 697b ldr r3, [r7, #20] - 80038aa: f8d3 2214 ldr.w r2, [r3, #532] @ 0x214 - 80038ae: 68fb ldr r3, [r7, #12] - 80038b0: 43db mvns r3, r3 - 80038b2: 401a ands r2, r3 - 80038b4: 697b ldr r3, [r7, #20] - 80038b6: f8c3 2214 str.w r2, [r3, #532] @ 0x214 - 80038ba: e007 b.n 80038cc + 8003944: 697b ldr r3, [r7, #20] + 8003946: f8d3 2214 ldr.w r2, [r3, #532] @ 0x214 + 800394a: 68fb ldr r3, [r7, #12] + 800394c: 43db mvns r3, r3 + 800394e: 401a ands r2, r3 + 8003950: 697b ldr r3, [r7, #20] + 8003952: f8c3 2214 str.w r2, [r3, #532] @ 0x214 + 8003956: e007 b.n 8003968 } else { /* FIFO 1 assignation for the filter */ SET_BIT(can_ip->FFA1R, filternbrbitpos); - 80038bc: 697b ldr r3, [r7, #20] - 80038be: f8d3 2214 ldr.w r2, [r3, #532] @ 0x214 - 80038c2: 68fb ldr r3, [r7, #12] - 80038c4: 431a orrs r2, r3 - 80038c6: 697b ldr r3, [r7, #20] - 80038c8: f8c3 2214 str.w r2, [r3, #532] @ 0x214 + 8003958: 697b ldr r3, [r7, #20] + 800395a: f8d3 2214 ldr.w r2, [r3, #532] @ 0x214 + 800395e: 68fb ldr r3, [r7, #12] + 8003960: 431a orrs r2, r3 + 8003962: 697b ldr r3, [r7, #20] + 8003964: f8c3 2214 str.w r2, [r3, #532] @ 0x214 } /* Filter activation */ if (sFilterConfig->FilterActivation == CAN_FILTER_ENABLE) - 80038cc: 683b ldr r3, [r7, #0] - 80038ce: 6a1b ldr r3, [r3, #32] - 80038d0: 2b01 cmp r3, #1 - 80038d2: d107 bne.n 80038e4 + 8003968: 683b ldr r3, [r7, #0] + 800396a: 6a1b ldr r3, [r3, #32] + 800396c: 2b01 cmp r3, #1 + 800396e: d107 bne.n 8003980 { SET_BIT(can_ip->FA1R, filternbrbitpos); - 80038d4: 697b ldr r3, [r7, #20] - 80038d6: f8d3 221c ldr.w r2, [r3, #540] @ 0x21c - 80038da: 68fb ldr r3, [r7, #12] - 80038dc: 431a orrs r2, r3 - 80038de: 697b ldr r3, [r7, #20] - 80038e0: f8c3 221c str.w r2, [r3, #540] @ 0x21c + 8003970: 697b ldr r3, [r7, #20] + 8003972: f8d3 221c ldr.w r2, [r3, #540] @ 0x21c + 8003976: 68fb ldr r3, [r7, #12] + 8003978: 431a orrs r2, r3 + 800397a: 697b ldr r3, [r7, #20] + 800397c: f8c3 221c str.w r2, [r3, #540] @ 0x21c } /* Leave the initialisation mode for the filter */ CLEAR_BIT(can_ip->FMR, CAN_FMR_FINIT); - 80038e4: 697b ldr r3, [r7, #20] - 80038e6: f8d3 3200 ldr.w r3, [r3, #512] @ 0x200 - 80038ea: f023 0201 bic.w r2, r3, #1 - 80038ee: 697b ldr r3, [r7, #20] - 80038f0: f8c3 2200 str.w r2, [r3, #512] @ 0x200 + 8003980: 697b ldr r3, [r7, #20] + 8003982: f8d3 3200 ldr.w r3, [r3, #512] @ 0x200 + 8003986: f023 0201 bic.w r2, r3, #1 + 800398a: 697b ldr r3, [r7, #20] + 800398c: f8c3 2200 str.w r2, [r3, #512] @ 0x200 /* Return function status */ return HAL_OK; - 80038f4: 2300 movs r3, #0 - 80038f6: e006 b.n 8003906 + 8003990: 2300 movs r3, #0 + 8003992: e006 b.n 80039a2 } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; - 80038f8: 687b ldr r3, [r7, #4] - 80038fa: 6a5b ldr r3, [r3, #36] @ 0x24 - 80038fc: f443 2280 orr.w r2, r3, #262144 @ 0x40000 - 8003900: 687b ldr r3, [r7, #4] - 8003902: 625a str r2, [r3, #36] @ 0x24 + 8003994: 687b ldr r3, [r7, #4] + 8003996: 6a5b ldr r3, [r3, #36] @ 0x24 + 8003998: f443 2280 orr.w r2, r3, #262144 @ 0x40000 + 800399c: 687b ldr r3, [r7, #4] + 800399e: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; - 8003904: 2301 movs r3, #1 + 80039a0: 2301 movs r3, #1 } } - 8003906: 4618 mov r0, r3 - 8003908: 371c adds r7, #28 - 800390a: 46bd mov sp, r7 - 800390c: f85d 7b04 ldr.w r7, [sp], #4 - 8003910: 4770 bx lr + 80039a2: 4618 mov r0, r3 + 80039a4: 371c adds r7, #28 + 80039a6: 46bd mov sp, r7 + 80039a8: f85d 7b04 ldr.w r7, [sp], #4 + 80039ac: 4770 bx lr -08003912 : +080039ae : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan) { - 8003912: b580 push {r7, lr} - 8003914: b084 sub sp, #16 - 8003916: af00 add r7, sp, #0 - 8003918: 6078 str r0, [r7, #4] + 80039ae: b580 push {r7, lr} + 80039b0: b084 sub sp, #16 + 80039b2: af00 add r7, sp, #0 + 80039b4: 6078 str r0, [r7, #4] uint32_t tickstart; if (hcan->State == HAL_CAN_STATE_READY) - 800391a: 687b ldr r3, [r7, #4] - 800391c: f893 3020 ldrb.w r3, [r3, #32] - 8003920: b2db uxtb r3, r3 - 8003922: 2b01 cmp r3, #1 - 8003924: d12e bne.n 8003984 + 80039b6: 687b ldr r3, [r7, #4] + 80039b8: f893 3020 ldrb.w r3, [r3, #32] + 80039bc: b2db uxtb r3, r3 + 80039be: 2b01 cmp r3, #1 + 80039c0: d12e bne.n 8003a20 { /* Change CAN peripheral state */ hcan->State = HAL_CAN_STATE_LISTENING; - 8003926: 687b ldr r3, [r7, #4] - 8003928: 2202 movs r2, #2 - 800392a: f883 2020 strb.w r2, [r3, #32] + 80039c2: 687b ldr r3, [r7, #4] + 80039c4: 2202 movs r2, #2 + 80039c6: f883 2020 strb.w r2, [r3, #32] /* Request leave initialisation */ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); - 800392e: 687b ldr r3, [r7, #4] - 8003930: 681b ldr r3, [r3, #0] - 8003932: 681a ldr r2, [r3, #0] - 8003934: 687b ldr r3, [r7, #4] - 8003936: 681b ldr r3, [r3, #0] - 8003938: f022 0201 bic.w r2, r2, #1 - 800393c: 601a str r2, [r3, #0] + 80039ca: 687b ldr r3, [r7, #4] + 80039cc: 681b ldr r3, [r3, #0] + 80039ce: 681a ldr r2, [r3, #0] + 80039d0: 687b ldr r3, [r7, #4] + 80039d2: 681b ldr r3, [r3, #0] + 80039d4: f022 0201 bic.w r2, r2, #1 + 80039d8: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); - 800393e: f7fe fc93 bl 8002268 - 8003942: 60f8 str r0, [r7, #12] + 80039da: f7fe fc93 bl 8002304 + 80039de: 60f8 str r0, [r7, #12] /* Wait the acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U) - 8003944: e012 b.n 800396c + 80039e0: e012 b.n 8003a08 { /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) - 8003946: f7fe fc8f bl 8002268 - 800394a: 4602 mov r2, r0 - 800394c: 68fb ldr r3, [r7, #12] - 800394e: 1ad3 subs r3, r2, r3 - 8003950: 2b0a cmp r3, #10 - 8003952: d90b bls.n 800396c + 80039e2: f7fe fc8f bl 8002304 + 80039e6: 4602 mov r2, r0 + 80039e8: 68fb ldr r3, [r7, #12] + 80039ea: 1ad3 subs r3, r2, r3 + 80039ec: 2b0a cmp r3, #10 + 80039ee: d90b bls.n 8003a08 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; - 8003954: 687b ldr r3, [r7, #4] - 8003956: 6a5b ldr r3, [r3, #36] @ 0x24 - 8003958: f443 3200 orr.w r2, r3, #131072 @ 0x20000 - 800395c: 687b ldr r3, [r7, #4] - 800395e: 625a str r2, [r3, #36] @ 0x24 + 80039f0: 687b ldr r3, [r7, #4] + 80039f2: 6a5b ldr r3, [r3, #36] @ 0x24 + 80039f4: f443 3200 orr.w r2, r3, #131072 @ 0x20000 + 80039f8: 687b ldr r3, [r7, #4] + 80039fa: 625a str r2, [r3, #36] @ 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; - 8003960: 687b ldr r3, [r7, #4] - 8003962: 2205 movs r2, #5 - 8003964: f883 2020 strb.w r2, [r3, #32] + 80039fc: 687b ldr r3, [r7, #4] + 80039fe: 2205 movs r2, #5 + 8003a00: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; - 8003968: 2301 movs r3, #1 - 800396a: e012 b.n 8003992 + 8003a04: 2301 movs r3, #1 + 8003a06: e012 b.n 8003a2e while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U) - 800396c: 687b ldr r3, [r7, #4] - 800396e: 681b ldr r3, [r3, #0] - 8003970: 685b ldr r3, [r3, #4] - 8003972: f003 0301 and.w r3, r3, #1 - 8003976: 2b00 cmp r3, #0 - 8003978: d1e5 bne.n 8003946 + 8003a08: 687b ldr r3, [r7, #4] + 8003a0a: 681b ldr r3, [r3, #0] + 8003a0c: 685b ldr r3, [r3, #4] + 8003a0e: f003 0301 and.w r3, r3, #1 + 8003a12: 2b00 cmp r3, #0 + 8003a14: d1e5 bne.n 80039e2 } } /* Reset the CAN ErrorCode */ hcan->ErrorCode = HAL_CAN_ERROR_NONE; - 800397a: 687b ldr r3, [r7, #4] - 800397c: 2200 movs r2, #0 - 800397e: 625a str r2, [r3, #36] @ 0x24 + 8003a16: 687b ldr r3, [r7, #4] + 8003a18: 2200 movs r2, #0 + 8003a1a: 625a str r2, [r3, #36] @ 0x24 /* Return function status */ return HAL_OK; - 8003980: 2300 movs r3, #0 - 8003982: e006 b.n 8003992 + 8003a1c: 2300 movs r3, #0 + 8003a1e: e006 b.n 8003a2e } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_READY; - 8003984: 687b ldr r3, [r7, #4] - 8003986: 6a5b ldr r3, [r3, #36] @ 0x24 - 8003988: f443 2200 orr.w r2, r3, #524288 @ 0x80000 - 800398c: 687b ldr r3, [r7, #4] - 800398e: 625a str r2, [r3, #36] @ 0x24 + 8003a20: 687b ldr r3, [r7, #4] + 8003a22: 6a5b ldr r3, [r3, #36] @ 0x24 + 8003a24: f443 2200 orr.w r2, r3, #524288 @ 0x80000 + 8003a28: 687b ldr r3, [r7, #4] + 8003a2a: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; - 8003990: 2301 movs r3, #1 + 8003a2c: 2301 movs r3, #1 } } - 8003992: 4618 mov r0, r3 - 8003994: 3710 adds r7, #16 - 8003996: 46bd mov sp, r7 - 8003998: bd80 pop {r7, pc} + 8003a2e: 4618 mov r0, r3 + 8003a30: 3710 adds r7, #16 + 8003a32: 46bd mov sp, r7 + 8003a34: bd80 pop {r7, pc} -0800399a : +08003a36 : * This parameter can be a value of @arg CAN_Tx_Mailboxes. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, const CAN_TxHeaderTypeDef *pHeader, const uint8_t aData[], uint32_t *pTxMailbox) { - 800399a: b480 push {r7} - 800399c: b089 sub sp, #36 @ 0x24 - 800399e: af00 add r7, sp, #0 - 80039a0: 60f8 str r0, [r7, #12] - 80039a2: 60b9 str r1, [r7, #8] - 80039a4: 607a str r2, [r7, #4] - 80039a6: 603b str r3, [r7, #0] + 8003a36: b480 push {r7} + 8003a38: b089 sub sp, #36 @ 0x24 + 8003a3a: af00 add r7, sp, #0 + 8003a3c: 60f8 str r0, [r7, #12] + 8003a3e: 60b9 str r1, [r7, #8] + 8003a40: 607a str r2, [r7, #4] + 8003a42: 603b str r3, [r7, #0] uint32_t transmitmailbox; HAL_CAN_StateTypeDef state = hcan->State; - 80039a8: 68fb ldr r3, [r7, #12] - 80039aa: f893 3020 ldrb.w r3, [r3, #32] - 80039ae: 77fb strb r3, [r7, #31] + 8003a44: 68fb ldr r3, [r7, #12] + 8003a46: f893 3020 ldrb.w r3, [r3, #32] + 8003a4a: 77fb strb r3, [r7, #31] uint32_t tsr = READ_REG(hcan->Instance->TSR); - 80039b0: 68fb ldr r3, [r7, #12] - 80039b2: 681b ldr r3, [r3, #0] - 80039b4: 689b ldr r3, [r3, #8] - 80039b6: 61bb str r3, [r7, #24] + 8003a4c: 68fb ldr r3, [r7, #12] + 8003a4e: 681b ldr r3, [r3, #0] + 8003a50: 689b ldr r3, [r3, #8] + 8003a52: 61bb str r3, [r7, #24] { assert_param(IS_CAN_EXTID(pHeader->ExtId)); } assert_param(IS_FUNCTIONAL_STATE(pHeader->TransmitGlobalTime)); if ((state == HAL_CAN_STATE_READY) || - 80039b8: 7ffb ldrb r3, [r7, #31] - 80039ba: 2b01 cmp r3, #1 - 80039bc: d003 beq.n 80039c6 - 80039be: 7ffb ldrb r3, [r7, #31] - 80039c0: 2b02 cmp r3, #2 - 80039c2: f040 80ad bne.w 8003b20 + 8003a54: 7ffb ldrb r3, [r7, #31] + 8003a56: 2b01 cmp r3, #1 + 8003a58: d003 beq.n 8003a62 + 8003a5a: 7ffb ldrb r3, [r7, #31] + 8003a5c: 2b02 cmp r3, #2 + 8003a5e: f040 80ad bne.w 8003bbc (state == HAL_CAN_STATE_LISTENING)) { /* Check that all the Tx mailboxes are not full */ if (((tsr & CAN_TSR_TME0) != 0U) || - 80039c6: 69bb ldr r3, [r7, #24] - 80039c8: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 - 80039cc: 2b00 cmp r3, #0 - 80039ce: d10a bne.n 80039e6 + 8003a62: 69bb ldr r3, [r7, #24] + 8003a64: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 + 8003a68: 2b00 cmp r3, #0 + 8003a6a: d10a bne.n 8003a82 ((tsr & CAN_TSR_TME1) != 0U) || - 80039d0: 69bb ldr r3, [r7, #24] - 80039d2: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 + 8003a6c: 69bb ldr r3, [r7, #24] + 8003a6e: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 if (((tsr & CAN_TSR_TME0) != 0U) || - 80039d6: 2b00 cmp r3, #0 - 80039d8: d105 bne.n 80039e6 + 8003a72: 2b00 cmp r3, #0 + 8003a74: d105 bne.n 8003a82 ((tsr & CAN_TSR_TME2) != 0U)) - 80039da: 69bb ldr r3, [r7, #24] - 80039dc: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 8003a76: 69bb ldr r3, [r7, #24] + 8003a78: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 ((tsr & CAN_TSR_TME1) != 0U) || - 80039e0: 2b00 cmp r3, #0 - 80039e2: f000 8095 beq.w 8003b10 + 8003a7c: 2b00 cmp r3, #0 + 8003a7e: f000 8095 beq.w 8003bac { /* Select an empty transmit mailbox */ transmitmailbox = (tsr & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos; - 80039e6: 69bb ldr r3, [r7, #24] - 80039e8: 0e1b lsrs r3, r3, #24 - 80039ea: f003 0303 and.w r3, r3, #3 - 80039ee: 617b str r3, [r7, #20] + 8003a82: 69bb ldr r3, [r7, #24] + 8003a84: 0e1b lsrs r3, r3, #24 + 8003a86: f003 0303 and.w r3, r3, #3 + 8003a8a: 617b str r3, [r7, #20] /* Store the Tx mailbox */ *pTxMailbox = (uint32_t)1 << transmitmailbox; - 80039f0: 2201 movs r2, #1 - 80039f2: 697b ldr r3, [r7, #20] - 80039f4: 409a lsls r2, r3 - 80039f6: 683b ldr r3, [r7, #0] - 80039f8: 601a str r2, [r3, #0] + 8003a8c: 2201 movs r2, #1 + 8003a8e: 697b ldr r3, [r7, #20] + 8003a90: 409a lsls r2, r3 + 8003a92: 683b ldr r3, [r7, #0] + 8003a94: 601a str r2, [r3, #0] /* Set up the Id */ if (pHeader->IDE == CAN_ID_STD) - 80039fa: 68bb ldr r3, [r7, #8] - 80039fc: 689b ldr r3, [r3, #8] - 80039fe: 2b00 cmp r3, #0 - 8003a00: d10d bne.n 8003a1e + 8003a96: 68bb ldr r3, [r7, #8] + 8003a98: 689b ldr r3, [r3, #8] + 8003a9a: 2b00 cmp r3, #0 + 8003a9c: d10d bne.n 8003aba { hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) | - 8003a02: 68bb ldr r3, [r7, #8] - 8003a04: 681b ldr r3, [r3, #0] - 8003a06: 055a lsls r2, r3, #21 + 8003a9e: 68bb ldr r3, [r7, #8] + 8003aa0: 681b ldr r3, [r3, #0] + 8003aa2: 055a lsls r2, r3, #21 pHeader->RTR); - 8003a08: 68bb ldr r3, [r7, #8] - 8003a0a: 68db ldr r3, [r3, #12] + 8003aa4: 68bb ldr r3, [r7, #8] + 8003aa6: 68db ldr r3, [r3, #12] hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) | - 8003a0c: 68f9 ldr r1, [r7, #12] - 8003a0e: 6809 ldr r1, [r1, #0] - 8003a10: 431a orrs r2, r3 - 8003a12: 697b ldr r3, [r7, #20] - 8003a14: 3318 adds r3, #24 - 8003a16: 011b lsls r3, r3, #4 - 8003a18: 440b add r3, r1 - 8003a1a: 601a str r2, [r3, #0] - 8003a1c: e00f b.n 8003a3e + 8003aa8: 68f9 ldr r1, [r7, #12] + 8003aaa: 6809 ldr r1, [r1, #0] + 8003aac: 431a orrs r2, r3 + 8003aae: 697b ldr r3, [r7, #20] + 8003ab0: 3318 adds r3, #24 + 8003ab2: 011b lsls r3, r3, #4 + 8003ab4: 440b add r3, r1 + 8003ab6: 601a str r2, [r3, #0] + 8003ab8: e00f b.n 8003ada } else { hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | - 8003a1e: 68bb ldr r3, [r7, #8] - 8003a20: 685b ldr r3, [r3, #4] - 8003a22: 00da lsls r2, r3, #3 + 8003aba: 68bb ldr r3, [r7, #8] + 8003abc: 685b ldr r3, [r3, #4] + 8003abe: 00da lsls r2, r3, #3 pHeader->IDE | - 8003a24: 68bb ldr r3, [r7, #8] - 8003a26: 689b ldr r3, [r3, #8] + 8003ac0: 68bb ldr r3, [r7, #8] + 8003ac2: 689b ldr r3, [r3, #8] hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | - 8003a28: 431a orrs r2, r3 + 8003ac4: 431a orrs r2, r3 pHeader->RTR); - 8003a2a: 68bb ldr r3, [r7, #8] - 8003a2c: 68db ldr r3, [r3, #12] + 8003ac6: 68bb ldr r3, [r7, #8] + 8003ac8: 68db ldr r3, [r3, #12] hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | - 8003a2e: 68f9 ldr r1, [r7, #12] - 8003a30: 6809 ldr r1, [r1, #0] + 8003aca: 68f9 ldr r1, [r7, #12] + 8003acc: 6809 ldr r1, [r1, #0] pHeader->IDE | - 8003a32: 431a orrs r2, r3 + 8003ace: 431a orrs r2, r3 hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | - 8003a34: 697b ldr r3, [r7, #20] - 8003a36: 3318 adds r3, #24 - 8003a38: 011b lsls r3, r3, #4 - 8003a3a: 440b add r3, r1 - 8003a3c: 601a str r2, [r3, #0] + 8003ad0: 697b ldr r3, [r7, #20] + 8003ad2: 3318 adds r3, #24 + 8003ad4: 011b lsls r3, r3, #4 + 8003ad6: 440b add r3, r1 + 8003ad8: 601a str r2, [r3, #0] } /* Set up the DLC */ hcan->Instance->sTxMailBox[transmitmailbox].TDTR = (pHeader->DLC); - 8003a3e: 68fb ldr r3, [r7, #12] - 8003a40: 6819 ldr r1, [r3, #0] - 8003a42: 68bb ldr r3, [r7, #8] - 8003a44: 691a ldr r2, [r3, #16] - 8003a46: 697b ldr r3, [r7, #20] - 8003a48: 3318 adds r3, #24 - 8003a4a: 011b lsls r3, r3, #4 - 8003a4c: 440b add r3, r1 - 8003a4e: 3304 adds r3, #4 - 8003a50: 601a str r2, [r3, #0] + 8003ada: 68fb ldr r3, [r7, #12] + 8003adc: 6819 ldr r1, [r3, #0] + 8003ade: 68bb ldr r3, [r7, #8] + 8003ae0: 691a ldr r2, [r3, #16] + 8003ae2: 697b ldr r3, [r7, #20] + 8003ae4: 3318 adds r3, #24 + 8003ae6: 011b lsls r3, r3, #4 + 8003ae8: 440b add r3, r1 + 8003aea: 3304 adds r3, #4 + 8003aec: 601a str r2, [r3, #0] /* Set up the Transmit Global Time mode */ if (pHeader->TransmitGlobalTime == ENABLE) - 8003a52: 68bb ldr r3, [r7, #8] - 8003a54: 7d1b ldrb r3, [r3, #20] - 8003a56: 2b01 cmp r3, #1 - 8003a58: d111 bne.n 8003a7e + 8003aee: 68bb ldr r3, [r7, #8] + 8003af0: 7d1b ldrb r3, [r3, #20] + 8003af2: 2b01 cmp r3, #1 + 8003af4: d111 bne.n 8003b1a { SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TDTR, CAN_TDT0R_TGT); - 8003a5a: 68fb ldr r3, [r7, #12] - 8003a5c: 681a ldr r2, [r3, #0] - 8003a5e: 697b ldr r3, [r7, #20] - 8003a60: 3318 adds r3, #24 - 8003a62: 011b lsls r3, r3, #4 - 8003a64: 4413 add r3, r2 - 8003a66: 3304 adds r3, #4 - 8003a68: 681b ldr r3, [r3, #0] - 8003a6a: 68fa ldr r2, [r7, #12] - 8003a6c: 6811 ldr r1, [r2, #0] - 8003a6e: f443 7280 orr.w r2, r3, #256 @ 0x100 - 8003a72: 697b ldr r3, [r7, #20] - 8003a74: 3318 adds r3, #24 - 8003a76: 011b lsls r3, r3, #4 - 8003a78: 440b add r3, r1 - 8003a7a: 3304 adds r3, #4 - 8003a7c: 601a str r2, [r3, #0] + 8003af6: 68fb ldr r3, [r7, #12] + 8003af8: 681a ldr r2, [r3, #0] + 8003afa: 697b ldr r3, [r7, #20] + 8003afc: 3318 adds r3, #24 + 8003afe: 011b lsls r3, r3, #4 + 8003b00: 4413 add r3, r2 + 8003b02: 3304 adds r3, #4 + 8003b04: 681b ldr r3, [r3, #0] + 8003b06: 68fa ldr r2, [r7, #12] + 8003b08: 6811 ldr r1, [r2, #0] + 8003b0a: f443 7280 orr.w r2, r3, #256 @ 0x100 + 8003b0e: 697b ldr r3, [r7, #20] + 8003b10: 3318 adds r3, #24 + 8003b12: 011b lsls r3, r3, #4 + 8003b14: 440b add r3, r1 + 8003b16: 3304 adds r3, #4 + 8003b18: 601a str r2, [r3, #0] } /* Set up the data field */ WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, - 8003a7e: 687b ldr r3, [r7, #4] - 8003a80: 3307 adds r3, #7 - 8003a82: 781b ldrb r3, [r3, #0] - 8003a84: 061a lsls r2, r3, #24 - 8003a86: 687b ldr r3, [r7, #4] - 8003a88: 3306 adds r3, #6 - 8003a8a: 781b ldrb r3, [r3, #0] - 8003a8c: 041b lsls r3, r3, #16 - 8003a8e: 431a orrs r2, r3 - 8003a90: 687b ldr r3, [r7, #4] - 8003a92: 3305 adds r3, #5 - 8003a94: 781b ldrb r3, [r3, #0] - 8003a96: 021b lsls r3, r3, #8 - 8003a98: 4313 orrs r3, r2 - 8003a9a: 687a ldr r2, [r7, #4] - 8003a9c: 3204 adds r2, #4 - 8003a9e: 7812 ldrb r2, [r2, #0] - 8003aa0: 4610 mov r0, r2 - 8003aa2: 68fa ldr r2, [r7, #12] - 8003aa4: 6811 ldr r1, [r2, #0] - 8003aa6: ea43 0200 orr.w r2, r3, r0 - 8003aaa: 697b ldr r3, [r7, #20] - 8003aac: 011b lsls r3, r3, #4 - 8003aae: 440b add r3, r1 - 8003ab0: f503 73c6 add.w r3, r3, #396 @ 0x18c - 8003ab4: 601a str r2, [r3, #0] + 8003b1a: 687b ldr r3, [r7, #4] + 8003b1c: 3307 adds r3, #7 + 8003b1e: 781b ldrb r3, [r3, #0] + 8003b20: 061a lsls r2, r3, #24 + 8003b22: 687b ldr r3, [r7, #4] + 8003b24: 3306 adds r3, #6 + 8003b26: 781b ldrb r3, [r3, #0] + 8003b28: 041b lsls r3, r3, #16 + 8003b2a: 431a orrs r2, r3 + 8003b2c: 687b ldr r3, [r7, #4] + 8003b2e: 3305 adds r3, #5 + 8003b30: 781b ldrb r3, [r3, #0] + 8003b32: 021b lsls r3, r3, #8 + 8003b34: 4313 orrs r3, r2 + 8003b36: 687a ldr r2, [r7, #4] + 8003b38: 3204 adds r2, #4 + 8003b3a: 7812 ldrb r2, [r2, #0] + 8003b3c: 4610 mov r0, r2 + 8003b3e: 68fa ldr r2, [r7, #12] + 8003b40: 6811 ldr r1, [r2, #0] + 8003b42: ea43 0200 orr.w r2, r3, r0 + 8003b46: 697b ldr r3, [r7, #20] + 8003b48: 011b lsls r3, r3, #4 + 8003b4a: 440b add r3, r1 + 8003b4c: f503 73c6 add.w r3, r3, #396 @ 0x18c + 8003b50: 601a str r2, [r3, #0] ((uint32_t)aData[7] << CAN_TDH0R_DATA7_Pos) | ((uint32_t)aData[6] << CAN_TDH0R_DATA6_Pos) | ((uint32_t)aData[5] << CAN_TDH0R_DATA5_Pos) | ((uint32_t)aData[4] << CAN_TDH0R_DATA4_Pos)); WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, - 8003ab6: 687b ldr r3, [r7, #4] - 8003ab8: 3303 adds r3, #3 - 8003aba: 781b ldrb r3, [r3, #0] - 8003abc: 061a lsls r2, r3, #24 - 8003abe: 687b ldr r3, [r7, #4] - 8003ac0: 3302 adds r3, #2 - 8003ac2: 781b ldrb r3, [r3, #0] - 8003ac4: 041b lsls r3, r3, #16 - 8003ac6: 431a orrs r2, r3 - 8003ac8: 687b ldr r3, [r7, #4] - 8003aca: 3301 adds r3, #1 - 8003acc: 781b ldrb r3, [r3, #0] - 8003ace: 021b lsls r3, r3, #8 - 8003ad0: 4313 orrs r3, r2 - 8003ad2: 687a ldr r2, [r7, #4] - 8003ad4: 7812 ldrb r2, [r2, #0] - 8003ad6: 4610 mov r0, r2 - 8003ad8: 68fa ldr r2, [r7, #12] - 8003ada: 6811 ldr r1, [r2, #0] - 8003adc: ea43 0200 orr.w r2, r3, r0 - 8003ae0: 697b ldr r3, [r7, #20] - 8003ae2: 011b lsls r3, r3, #4 - 8003ae4: 440b add r3, r1 - 8003ae6: f503 73c4 add.w r3, r3, #392 @ 0x188 - 8003aea: 601a str r2, [r3, #0] + 8003b52: 687b ldr r3, [r7, #4] + 8003b54: 3303 adds r3, #3 + 8003b56: 781b ldrb r3, [r3, #0] + 8003b58: 061a lsls r2, r3, #24 + 8003b5a: 687b ldr r3, [r7, #4] + 8003b5c: 3302 adds r3, #2 + 8003b5e: 781b ldrb r3, [r3, #0] + 8003b60: 041b lsls r3, r3, #16 + 8003b62: 431a orrs r2, r3 + 8003b64: 687b ldr r3, [r7, #4] + 8003b66: 3301 adds r3, #1 + 8003b68: 781b ldrb r3, [r3, #0] + 8003b6a: 021b lsls r3, r3, #8 + 8003b6c: 4313 orrs r3, r2 + 8003b6e: 687a ldr r2, [r7, #4] + 8003b70: 7812 ldrb r2, [r2, #0] + 8003b72: 4610 mov r0, r2 + 8003b74: 68fa ldr r2, [r7, #12] + 8003b76: 6811 ldr r1, [r2, #0] + 8003b78: ea43 0200 orr.w r2, r3, r0 + 8003b7c: 697b ldr r3, [r7, #20] + 8003b7e: 011b lsls r3, r3, #4 + 8003b80: 440b add r3, r1 + 8003b82: f503 73c4 add.w r3, r3, #392 @ 0x188 + 8003b86: 601a str r2, [r3, #0] ((uint32_t)aData[2] << CAN_TDL0R_DATA2_Pos) | ((uint32_t)aData[1] << CAN_TDL0R_DATA1_Pos) | ((uint32_t)aData[0] << CAN_TDL0R_DATA0_Pos)); /* Request transmission */ SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ); - 8003aec: 68fb ldr r3, [r7, #12] - 8003aee: 681a ldr r2, [r3, #0] - 8003af0: 697b ldr r3, [r7, #20] - 8003af2: 3318 adds r3, #24 - 8003af4: 011b lsls r3, r3, #4 - 8003af6: 4413 add r3, r2 - 8003af8: 681b ldr r3, [r3, #0] - 8003afa: 68fa ldr r2, [r7, #12] - 8003afc: 6811 ldr r1, [r2, #0] - 8003afe: f043 0201 orr.w r2, r3, #1 - 8003b02: 697b ldr r3, [r7, #20] - 8003b04: 3318 adds r3, #24 - 8003b06: 011b lsls r3, r3, #4 - 8003b08: 440b add r3, r1 - 8003b0a: 601a str r2, [r3, #0] + 8003b88: 68fb ldr r3, [r7, #12] + 8003b8a: 681a ldr r2, [r3, #0] + 8003b8c: 697b ldr r3, [r7, #20] + 8003b8e: 3318 adds r3, #24 + 8003b90: 011b lsls r3, r3, #4 + 8003b92: 4413 add r3, r2 + 8003b94: 681b ldr r3, [r3, #0] + 8003b96: 68fa ldr r2, [r7, #12] + 8003b98: 6811 ldr r1, [r2, #0] + 8003b9a: f043 0201 orr.w r2, r3, #1 + 8003b9e: 697b ldr r3, [r7, #20] + 8003ba0: 3318 adds r3, #24 + 8003ba2: 011b lsls r3, r3, #4 + 8003ba4: 440b add r3, r1 + 8003ba6: 601a str r2, [r3, #0] /* Return function status */ return HAL_OK; - 8003b0c: 2300 movs r3, #0 - 8003b0e: e00e b.n 8003b2e + 8003ba8: 2300 movs r3, #0 + 8003baa: e00e b.n 8003bca } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; - 8003b10: 68fb ldr r3, [r7, #12] - 8003b12: 6a5b ldr r3, [r3, #36] @ 0x24 - 8003b14: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 - 8003b18: 68fb ldr r3, [r7, #12] - 8003b1a: 625a str r2, [r3, #36] @ 0x24 + 8003bac: 68fb ldr r3, [r7, #12] + 8003bae: 6a5b ldr r3, [r3, #36] @ 0x24 + 8003bb0: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 + 8003bb4: 68fb ldr r3, [r7, #12] + 8003bb6: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; - 8003b1c: 2301 movs r3, #1 - 8003b1e: e006 b.n 8003b2e + 8003bb8: 2301 movs r3, #1 + 8003bba: e006 b.n 8003bca } } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; - 8003b20: 68fb ldr r3, [r7, #12] - 8003b22: 6a5b ldr r3, [r3, #36] @ 0x24 - 8003b24: f443 2280 orr.w r2, r3, #262144 @ 0x40000 - 8003b28: 68fb ldr r3, [r7, #12] - 8003b2a: 625a str r2, [r3, #36] @ 0x24 + 8003bbc: 68fb ldr r3, [r7, #12] + 8003bbe: 6a5b ldr r3, [r3, #36] @ 0x24 + 8003bc0: f443 2280 orr.w r2, r3, #262144 @ 0x40000 + 8003bc4: 68fb ldr r3, [r7, #12] + 8003bc6: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; - 8003b2c: 2301 movs r3, #1 + 8003bc8: 2301 movs r3, #1 } } - 8003b2e: 4618 mov r0, r3 - 8003b30: 3724 adds r7, #36 @ 0x24 - 8003b32: 46bd mov sp, r7 - 8003b34: f85d 7b04 ldr.w r7, [sp], #4 - 8003b38: 4770 bx lr + 8003bca: 4618 mov r0, r3 + 8003bcc: 3724 adds r7, #36 @ 0x24 + 8003bce: 46bd mov sp, r7 + 8003bd0: f85d 7b04 ldr.w r7, [sp], #4 + 8003bd4: 4770 bx lr -08003b3a : +08003bd6 : * @param aData array where the payload of the Rx frame will be stored. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]) { - 8003b3a: b480 push {r7} - 8003b3c: b087 sub sp, #28 - 8003b3e: af00 add r7, sp, #0 - 8003b40: 60f8 str r0, [r7, #12] - 8003b42: 60b9 str r1, [r7, #8] - 8003b44: 607a str r2, [r7, #4] - 8003b46: 603b str r3, [r7, #0] + 8003bd6: b480 push {r7} + 8003bd8: b087 sub sp, #28 + 8003bda: af00 add r7, sp, #0 + 8003bdc: 60f8 str r0, [r7, #12] + 8003bde: 60b9 str r1, [r7, #8] + 8003be0: 607a str r2, [r7, #4] + 8003be2: 603b str r3, [r7, #0] HAL_CAN_StateTypeDef state = hcan->State; - 8003b48: 68fb ldr r3, [r7, #12] - 8003b4a: f893 3020 ldrb.w r3, [r3, #32] - 8003b4e: 75fb strb r3, [r7, #23] + 8003be4: 68fb ldr r3, [r7, #12] + 8003be6: f893 3020 ldrb.w r3, [r3, #32] + 8003bea: 75fb strb r3, [r7, #23] assert_param(IS_CAN_RX_FIFO(RxFifo)); if ((state == HAL_CAN_STATE_READY) || - 8003b50: 7dfb ldrb r3, [r7, #23] - 8003b52: 2b01 cmp r3, #1 - 8003b54: d003 beq.n 8003b5e - 8003b56: 7dfb ldrb r3, [r7, #23] - 8003b58: 2b02 cmp r3, #2 - 8003b5a: f040 8103 bne.w 8003d64 + 8003bec: 7dfb ldrb r3, [r7, #23] + 8003bee: 2b01 cmp r3, #1 + 8003bf0: d003 beq.n 8003bfa + 8003bf2: 7dfb ldrb r3, [r7, #23] + 8003bf4: 2b02 cmp r3, #2 + 8003bf6: f040 8103 bne.w 8003e00 (state == HAL_CAN_STATE_LISTENING)) { /* Check the Rx FIFO */ if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ - 8003b5e: 68bb ldr r3, [r7, #8] - 8003b60: 2b00 cmp r3, #0 - 8003b62: d10e bne.n 8003b82 + 8003bfa: 68bb ldr r3, [r7, #8] + 8003bfc: 2b00 cmp r3, #0 + 8003bfe: d10e bne.n 8003c1e { /* Check that the Rx FIFO 0 is not empty */ if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == 0U) - 8003b64: 68fb ldr r3, [r7, #12] - 8003b66: 681b ldr r3, [r3, #0] - 8003b68: 68db ldr r3, [r3, #12] - 8003b6a: f003 0303 and.w r3, r3, #3 - 8003b6e: 2b00 cmp r3, #0 - 8003b70: d116 bne.n 8003ba0 + 8003c00: 68fb ldr r3, [r7, #12] + 8003c02: 681b ldr r3, [r3, #0] + 8003c04: 68db ldr r3, [r3, #12] + 8003c06: f003 0303 and.w r3, r3, #3 + 8003c0a: 2b00 cmp r3, #0 + 8003c0c: d116 bne.n 8003c3c { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; - 8003b72: 68fb ldr r3, [r7, #12] - 8003b74: 6a5b ldr r3, [r3, #36] @ 0x24 - 8003b76: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 - 8003b7a: 68fb ldr r3, [r7, #12] - 8003b7c: 625a str r2, [r3, #36] @ 0x24 + 8003c0e: 68fb ldr r3, [r7, #12] + 8003c10: 6a5b ldr r3, [r3, #36] @ 0x24 + 8003c12: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 + 8003c16: 68fb ldr r3, [r7, #12] + 8003c18: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; - 8003b7e: 2301 movs r3, #1 - 8003b80: e0f7 b.n 8003d72 + 8003c1a: 2301 movs r3, #1 + 8003c1c: e0f7 b.n 8003e0e } } else /* Rx element is assigned to Rx FIFO 1 */ { /* Check that the Rx FIFO 1 is not empty */ if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == 0U) - 8003b82: 68fb ldr r3, [r7, #12] - 8003b84: 681b ldr r3, [r3, #0] - 8003b86: 691b ldr r3, [r3, #16] - 8003b88: f003 0303 and.w r3, r3, #3 - 8003b8c: 2b00 cmp r3, #0 - 8003b8e: d107 bne.n 8003ba0 + 8003c1e: 68fb ldr r3, [r7, #12] + 8003c20: 681b ldr r3, [r3, #0] + 8003c22: 691b ldr r3, [r3, #16] + 8003c24: f003 0303 and.w r3, r3, #3 + 8003c28: 2b00 cmp r3, #0 + 8003c2a: d107 bne.n 8003c3c { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; - 8003b90: 68fb ldr r3, [r7, #12] - 8003b92: 6a5b ldr r3, [r3, #36] @ 0x24 - 8003b94: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 - 8003b98: 68fb ldr r3, [r7, #12] - 8003b9a: 625a str r2, [r3, #36] @ 0x24 + 8003c2c: 68fb ldr r3, [r7, #12] + 8003c2e: 6a5b ldr r3, [r3, #36] @ 0x24 + 8003c30: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 + 8003c34: 68fb ldr r3, [r7, #12] + 8003c36: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; - 8003b9c: 2301 movs r3, #1 - 8003b9e: e0e8 b.n 8003d72 + 8003c38: 2301 movs r3, #1 + 8003c3a: e0e8 b.n 8003e0e } } /* Get the header */ pHeader->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[RxFifo].RIR; - 8003ba0: 68fb ldr r3, [r7, #12] - 8003ba2: 681a ldr r2, [r3, #0] - 8003ba4: 68bb ldr r3, [r7, #8] - 8003ba6: 331b adds r3, #27 - 8003ba8: 011b lsls r3, r3, #4 - 8003baa: 4413 add r3, r2 - 8003bac: 681b ldr r3, [r3, #0] - 8003bae: f003 0204 and.w r2, r3, #4 - 8003bb2: 687b ldr r3, [r7, #4] - 8003bb4: 609a str r2, [r3, #8] + 8003c3c: 68fb ldr r3, [r7, #12] + 8003c3e: 681a ldr r2, [r3, #0] + 8003c40: 68bb ldr r3, [r7, #8] + 8003c42: 331b adds r3, #27 + 8003c44: 011b lsls r3, r3, #4 + 8003c46: 4413 add r3, r2 + 8003c48: 681b ldr r3, [r3, #0] + 8003c4a: f003 0204 and.w r2, r3, #4 + 8003c4e: 687b ldr r3, [r7, #4] + 8003c50: 609a str r2, [r3, #8] if (pHeader->IDE == CAN_ID_STD) - 8003bb6: 687b ldr r3, [r7, #4] - 8003bb8: 689b ldr r3, [r3, #8] - 8003bba: 2b00 cmp r3, #0 - 8003bbc: d10c bne.n 8003bd8 + 8003c52: 687b ldr r3, [r7, #4] + 8003c54: 689b ldr r3, [r3, #8] + 8003c56: 2b00 cmp r3, #0 + 8003c58: d10c bne.n 8003c74 { pHeader->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_TI0R_STID_Pos; - 8003bbe: 68fb ldr r3, [r7, #12] - 8003bc0: 681a ldr r2, [r3, #0] - 8003bc2: 68bb ldr r3, [r7, #8] - 8003bc4: 331b adds r3, #27 - 8003bc6: 011b lsls r3, r3, #4 - 8003bc8: 4413 add r3, r2 - 8003bca: 681b ldr r3, [r3, #0] - 8003bcc: 0d5b lsrs r3, r3, #21 - 8003bce: f3c3 020a ubfx r2, r3, #0, #11 - 8003bd2: 687b ldr r3, [r7, #4] - 8003bd4: 601a str r2, [r3, #0] - 8003bd6: e00b b.n 8003bf0 + 8003c5a: 68fb ldr r3, [r7, #12] + 8003c5c: 681a ldr r2, [r3, #0] + 8003c5e: 68bb ldr r3, [r7, #8] + 8003c60: 331b adds r3, #27 + 8003c62: 011b lsls r3, r3, #4 + 8003c64: 4413 add r3, r2 + 8003c66: 681b ldr r3, [r3, #0] + 8003c68: 0d5b lsrs r3, r3, #21 + 8003c6a: f3c3 020a ubfx r2, r3, #0, #11 + 8003c6e: 687b ldr r3, [r7, #4] + 8003c70: 601a str r2, [r3, #0] + 8003c72: e00b b.n 8003c8c } else { pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos; - 8003bd8: 68fb ldr r3, [r7, #12] - 8003bda: 681a ldr r2, [r3, #0] - 8003bdc: 68bb ldr r3, [r7, #8] - 8003bde: 331b adds r3, #27 - 8003be0: 011b lsls r3, r3, #4 - 8003be2: 4413 add r3, r2 - 8003be4: 681b ldr r3, [r3, #0] - 8003be6: 08db lsrs r3, r3, #3 - 8003be8: f023 4260 bic.w r2, r3, #3758096384 @ 0xe0000000 + 8003c74: 68fb ldr r3, [r7, #12] + 8003c76: 681a ldr r2, [r3, #0] + 8003c78: 68bb ldr r3, [r7, #8] + 8003c7a: 331b adds r3, #27 + 8003c7c: 011b lsls r3, r3, #4 + 8003c7e: 4413 add r3, r2 + 8003c80: 681b ldr r3, [r3, #0] + 8003c82: 08db lsrs r3, r3, #3 + 8003c84: f023 4260 bic.w r2, r3, #3758096384 @ 0xe0000000 pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & - 8003bec: 687b ldr r3, [r7, #4] - 8003bee: 605a str r2, [r3, #4] + 8003c88: 687b ldr r3, [r7, #4] + 8003c8a: 605a str r2, [r3, #4] } pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR); - 8003bf0: 68fb ldr r3, [r7, #12] - 8003bf2: 681a ldr r2, [r3, #0] - 8003bf4: 68bb ldr r3, [r7, #8] - 8003bf6: 331b adds r3, #27 - 8003bf8: 011b lsls r3, r3, #4 - 8003bfa: 4413 add r3, r2 - 8003bfc: 681b ldr r3, [r3, #0] - 8003bfe: f003 0202 and.w r2, r3, #2 - 8003c02: 687b ldr r3, [r7, #4] - 8003c04: 60da str r2, [r3, #12] + 8003c8c: 68fb ldr r3, [r7, #12] + 8003c8e: 681a ldr r2, [r3, #0] + 8003c90: 68bb ldr r3, [r7, #8] + 8003c92: 331b adds r3, #27 + 8003c94: 011b lsls r3, r3, #4 + 8003c96: 4413 add r3, r2 + 8003c98: 681b ldr r3, [r3, #0] + 8003c9a: f003 0202 and.w r2, r3, #2 + 8003c9e: 687b ldr r3, [r7, #4] + 8003ca0: 60da str r2, [r3, #12] if (((CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos) >= 8U) - 8003c06: 68fb ldr r3, [r7, #12] - 8003c08: 681a ldr r2, [r3, #0] - 8003c0a: 68bb ldr r3, [r7, #8] - 8003c0c: 331b adds r3, #27 - 8003c0e: 011b lsls r3, r3, #4 - 8003c10: 4413 add r3, r2 - 8003c12: 3304 adds r3, #4 - 8003c14: 681b ldr r3, [r3, #0] - 8003c16: f003 0308 and.w r3, r3, #8 - 8003c1a: 2b00 cmp r3, #0 - 8003c1c: d003 beq.n 8003c26 + 8003ca2: 68fb ldr r3, [r7, #12] + 8003ca4: 681a ldr r2, [r3, #0] + 8003ca6: 68bb ldr r3, [r7, #8] + 8003ca8: 331b adds r3, #27 + 8003caa: 011b lsls r3, r3, #4 + 8003cac: 4413 add r3, r2 + 8003cae: 3304 adds r3, #4 + 8003cb0: 681b ldr r3, [r3, #0] + 8003cb2: f003 0308 and.w r3, r3, #8 + 8003cb6: 2b00 cmp r3, #0 + 8003cb8: d003 beq.n 8003cc2 { /* Truncate DLC to 8 if received field is over range */ pHeader->DLC = 8U; - 8003c1e: 687b ldr r3, [r7, #4] - 8003c20: 2208 movs r2, #8 - 8003c22: 611a str r2, [r3, #16] - 8003c24: e00b b.n 8003c3e + 8003cba: 687b ldr r3, [r7, #4] + 8003cbc: 2208 movs r2, #8 + 8003cbe: 611a str r2, [r3, #16] + 8003cc0: e00b b.n 8003cda } else { pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos; - 8003c26: 68fb ldr r3, [r7, #12] - 8003c28: 681a ldr r2, [r3, #0] - 8003c2a: 68bb ldr r3, [r7, #8] - 8003c2c: 331b adds r3, #27 - 8003c2e: 011b lsls r3, r3, #4 - 8003c30: 4413 add r3, r2 - 8003c32: 3304 adds r3, #4 - 8003c34: 681b ldr r3, [r3, #0] - 8003c36: f003 020f and.w r2, r3, #15 - 8003c3a: 687b ldr r3, [r7, #4] - 8003c3c: 611a str r2, [r3, #16] + 8003cc2: 68fb ldr r3, [r7, #12] + 8003cc4: 681a ldr r2, [r3, #0] + 8003cc6: 68bb ldr r3, [r7, #8] + 8003cc8: 331b adds r3, #27 + 8003cca: 011b lsls r3, r3, #4 + 8003ccc: 4413 add r3, r2 + 8003cce: 3304 adds r3, #4 + 8003cd0: 681b ldr r3, [r3, #0] + 8003cd2: f003 020f and.w r2, r3, #15 + 8003cd6: 687b ldr r3, [r7, #4] + 8003cd8: 611a str r2, [r3, #16] } pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos; - 8003c3e: 68fb ldr r3, [r7, #12] - 8003c40: 681a ldr r2, [r3, #0] - 8003c42: 68bb ldr r3, [r7, #8] - 8003c44: 331b adds r3, #27 - 8003c46: 011b lsls r3, r3, #4 - 8003c48: 4413 add r3, r2 - 8003c4a: 3304 adds r3, #4 - 8003c4c: 681b ldr r3, [r3, #0] - 8003c4e: 0a1b lsrs r3, r3, #8 - 8003c50: b2da uxtb r2, r3 - 8003c52: 687b ldr r3, [r7, #4] - 8003c54: 619a str r2, [r3, #24] + 8003cda: 68fb ldr r3, [r7, #12] + 8003cdc: 681a ldr r2, [r3, #0] + 8003cde: 68bb ldr r3, [r7, #8] + 8003ce0: 331b adds r3, #27 + 8003ce2: 011b lsls r3, r3, #4 + 8003ce4: 4413 add r3, r2 + 8003ce6: 3304 adds r3, #4 + 8003ce8: 681b ldr r3, [r3, #0] + 8003cea: 0a1b lsrs r3, r3, #8 + 8003cec: b2da uxtb r2, r3 + 8003cee: 687b ldr r3, [r7, #4] + 8003cf0: 619a str r2, [r3, #24] pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos; - 8003c56: 68fb ldr r3, [r7, #12] - 8003c58: 681a ldr r2, [r3, #0] - 8003c5a: 68bb ldr r3, [r7, #8] - 8003c5c: 331b adds r3, #27 - 8003c5e: 011b lsls r3, r3, #4 - 8003c60: 4413 add r3, r2 - 8003c62: 3304 adds r3, #4 - 8003c64: 681b ldr r3, [r3, #0] - 8003c66: 0c1b lsrs r3, r3, #16 - 8003c68: b29a uxth r2, r3 - 8003c6a: 687b ldr r3, [r7, #4] - 8003c6c: 615a str r2, [r3, #20] + 8003cf2: 68fb ldr r3, [r7, #12] + 8003cf4: 681a ldr r2, [r3, #0] + 8003cf6: 68bb ldr r3, [r7, #8] + 8003cf8: 331b adds r3, #27 + 8003cfa: 011b lsls r3, r3, #4 + 8003cfc: 4413 add r3, r2 + 8003cfe: 3304 adds r3, #4 + 8003d00: 681b ldr r3, [r3, #0] + 8003d02: 0c1b lsrs r3, r3, #16 + 8003d04: b29a uxth r2, r3 + 8003d06: 687b ldr r3, [r7, #4] + 8003d08: 615a str r2, [r3, #20] /* Get the data */ aData[0] = (uint8_t)((CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos); - 8003c6e: 68fb ldr r3, [r7, #12] - 8003c70: 681a ldr r2, [r3, #0] - 8003c72: 68bb ldr r3, [r7, #8] - 8003c74: 011b lsls r3, r3, #4 - 8003c76: 4413 add r3, r2 - 8003c78: f503 73dc add.w r3, r3, #440 @ 0x1b8 - 8003c7c: 681b ldr r3, [r3, #0] - 8003c7e: b2da uxtb r2, r3 - 8003c80: 683b ldr r3, [r7, #0] - 8003c82: 701a strb r2, [r3, #0] + 8003d0a: 68fb ldr r3, [r7, #12] + 8003d0c: 681a ldr r2, [r3, #0] + 8003d0e: 68bb ldr r3, [r7, #8] + 8003d10: 011b lsls r3, r3, #4 + 8003d12: 4413 add r3, r2 + 8003d14: f503 73dc add.w r3, r3, #440 @ 0x1b8 + 8003d18: 681b ldr r3, [r3, #0] + 8003d1a: b2da uxtb r2, r3 + 8003d1c: 683b ldr r3, [r7, #0] + 8003d1e: 701a strb r2, [r3, #0] aData[1] = (uint8_t)((CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos); - 8003c84: 68fb ldr r3, [r7, #12] - 8003c86: 681a ldr r2, [r3, #0] - 8003c88: 68bb ldr r3, [r7, #8] - 8003c8a: 011b lsls r3, r3, #4 - 8003c8c: 4413 add r3, r2 - 8003c8e: f503 73dc add.w r3, r3, #440 @ 0x1b8 - 8003c92: 681b ldr r3, [r3, #0] - 8003c94: 0a1a lsrs r2, r3, #8 - 8003c96: 683b ldr r3, [r7, #0] - 8003c98: 3301 adds r3, #1 - 8003c9a: b2d2 uxtb r2, r2 - 8003c9c: 701a strb r2, [r3, #0] + 8003d20: 68fb ldr r3, [r7, #12] + 8003d22: 681a ldr r2, [r3, #0] + 8003d24: 68bb ldr r3, [r7, #8] + 8003d26: 011b lsls r3, r3, #4 + 8003d28: 4413 add r3, r2 + 8003d2a: f503 73dc add.w r3, r3, #440 @ 0x1b8 + 8003d2e: 681b ldr r3, [r3, #0] + 8003d30: 0a1a lsrs r2, r3, #8 + 8003d32: 683b ldr r3, [r7, #0] + 8003d34: 3301 adds r3, #1 + 8003d36: b2d2 uxtb r2, r2 + 8003d38: 701a strb r2, [r3, #0] aData[2] = (uint8_t)((CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos); - 8003c9e: 68fb ldr r3, [r7, #12] - 8003ca0: 681a ldr r2, [r3, #0] - 8003ca2: 68bb ldr r3, [r7, #8] - 8003ca4: 011b lsls r3, r3, #4 - 8003ca6: 4413 add r3, r2 - 8003ca8: f503 73dc add.w r3, r3, #440 @ 0x1b8 - 8003cac: 681b ldr r3, [r3, #0] - 8003cae: 0c1a lsrs r2, r3, #16 - 8003cb0: 683b ldr r3, [r7, #0] - 8003cb2: 3302 adds r3, #2 - 8003cb4: b2d2 uxtb r2, r2 - 8003cb6: 701a strb r2, [r3, #0] + 8003d3a: 68fb ldr r3, [r7, #12] + 8003d3c: 681a ldr r2, [r3, #0] + 8003d3e: 68bb ldr r3, [r7, #8] + 8003d40: 011b lsls r3, r3, #4 + 8003d42: 4413 add r3, r2 + 8003d44: f503 73dc add.w r3, r3, #440 @ 0x1b8 + 8003d48: 681b ldr r3, [r3, #0] + 8003d4a: 0c1a lsrs r2, r3, #16 + 8003d4c: 683b ldr r3, [r7, #0] + 8003d4e: 3302 adds r3, #2 + 8003d50: b2d2 uxtb r2, r2 + 8003d52: 701a strb r2, [r3, #0] aData[3] = (uint8_t)((CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos); - 8003cb8: 68fb ldr r3, [r7, #12] - 8003cba: 681a ldr r2, [r3, #0] - 8003cbc: 68bb ldr r3, [r7, #8] - 8003cbe: 011b lsls r3, r3, #4 - 8003cc0: 4413 add r3, r2 - 8003cc2: f503 73dc add.w r3, r3, #440 @ 0x1b8 - 8003cc6: 681b ldr r3, [r3, #0] - 8003cc8: 0e1a lsrs r2, r3, #24 - 8003cca: 683b ldr r3, [r7, #0] - 8003ccc: 3303 adds r3, #3 - 8003cce: b2d2 uxtb r2, r2 - 8003cd0: 701a strb r2, [r3, #0] + 8003d54: 68fb ldr r3, [r7, #12] + 8003d56: 681a ldr r2, [r3, #0] + 8003d58: 68bb ldr r3, [r7, #8] + 8003d5a: 011b lsls r3, r3, #4 + 8003d5c: 4413 add r3, r2 + 8003d5e: f503 73dc add.w r3, r3, #440 @ 0x1b8 + 8003d62: 681b ldr r3, [r3, #0] + 8003d64: 0e1a lsrs r2, r3, #24 + 8003d66: 683b ldr r3, [r7, #0] + 8003d68: 3303 adds r3, #3 + 8003d6a: b2d2 uxtb r2, r2 + 8003d6c: 701a strb r2, [r3, #0] aData[4] = (uint8_t)((CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos); - 8003cd2: 68fb ldr r3, [r7, #12] - 8003cd4: 681a ldr r2, [r3, #0] - 8003cd6: 68bb ldr r3, [r7, #8] - 8003cd8: 011b lsls r3, r3, #4 - 8003cda: 4413 add r3, r2 - 8003cdc: f503 73de add.w r3, r3, #444 @ 0x1bc - 8003ce0: 681a ldr r2, [r3, #0] - 8003ce2: 683b ldr r3, [r7, #0] - 8003ce4: 3304 adds r3, #4 - 8003ce6: b2d2 uxtb r2, r2 - 8003ce8: 701a strb r2, [r3, #0] + 8003d6e: 68fb ldr r3, [r7, #12] + 8003d70: 681a ldr r2, [r3, #0] + 8003d72: 68bb ldr r3, [r7, #8] + 8003d74: 011b lsls r3, r3, #4 + 8003d76: 4413 add r3, r2 + 8003d78: f503 73de add.w r3, r3, #444 @ 0x1bc + 8003d7c: 681a ldr r2, [r3, #0] + 8003d7e: 683b ldr r3, [r7, #0] + 8003d80: 3304 adds r3, #4 + 8003d82: b2d2 uxtb r2, r2 + 8003d84: 701a strb r2, [r3, #0] aData[5] = (uint8_t)((CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos); - 8003cea: 68fb ldr r3, [r7, #12] - 8003cec: 681a ldr r2, [r3, #0] - 8003cee: 68bb ldr r3, [r7, #8] - 8003cf0: 011b lsls r3, r3, #4 - 8003cf2: 4413 add r3, r2 - 8003cf4: f503 73de add.w r3, r3, #444 @ 0x1bc - 8003cf8: 681b ldr r3, [r3, #0] - 8003cfa: 0a1a lsrs r2, r3, #8 - 8003cfc: 683b ldr r3, [r7, #0] - 8003cfe: 3305 adds r3, #5 - 8003d00: b2d2 uxtb r2, r2 - 8003d02: 701a strb r2, [r3, #0] + 8003d86: 68fb ldr r3, [r7, #12] + 8003d88: 681a ldr r2, [r3, #0] + 8003d8a: 68bb ldr r3, [r7, #8] + 8003d8c: 011b lsls r3, r3, #4 + 8003d8e: 4413 add r3, r2 + 8003d90: f503 73de add.w r3, r3, #444 @ 0x1bc + 8003d94: 681b ldr r3, [r3, #0] + 8003d96: 0a1a lsrs r2, r3, #8 + 8003d98: 683b ldr r3, [r7, #0] + 8003d9a: 3305 adds r3, #5 + 8003d9c: b2d2 uxtb r2, r2 + 8003d9e: 701a strb r2, [r3, #0] aData[6] = (uint8_t)((CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos); - 8003d04: 68fb ldr r3, [r7, #12] - 8003d06: 681a ldr r2, [r3, #0] - 8003d08: 68bb ldr r3, [r7, #8] - 8003d0a: 011b lsls r3, r3, #4 - 8003d0c: 4413 add r3, r2 - 8003d0e: f503 73de add.w r3, r3, #444 @ 0x1bc - 8003d12: 681b ldr r3, [r3, #0] - 8003d14: 0c1a lsrs r2, r3, #16 - 8003d16: 683b ldr r3, [r7, #0] - 8003d18: 3306 adds r3, #6 - 8003d1a: b2d2 uxtb r2, r2 - 8003d1c: 701a strb r2, [r3, #0] + 8003da0: 68fb ldr r3, [r7, #12] + 8003da2: 681a ldr r2, [r3, #0] + 8003da4: 68bb ldr r3, [r7, #8] + 8003da6: 011b lsls r3, r3, #4 + 8003da8: 4413 add r3, r2 + 8003daa: f503 73de add.w r3, r3, #444 @ 0x1bc + 8003dae: 681b ldr r3, [r3, #0] + 8003db0: 0c1a lsrs r2, r3, #16 + 8003db2: 683b ldr r3, [r7, #0] + 8003db4: 3306 adds r3, #6 + 8003db6: b2d2 uxtb r2, r2 + 8003db8: 701a strb r2, [r3, #0] aData[7] = (uint8_t)((CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos); - 8003d1e: 68fb ldr r3, [r7, #12] - 8003d20: 681a ldr r2, [r3, #0] - 8003d22: 68bb ldr r3, [r7, #8] - 8003d24: 011b lsls r3, r3, #4 - 8003d26: 4413 add r3, r2 - 8003d28: f503 73de add.w r3, r3, #444 @ 0x1bc - 8003d2c: 681b ldr r3, [r3, #0] - 8003d2e: 0e1a lsrs r2, r3, #24 - 8003d30: 683b ldr r3, [r7, #0] - 8003d32: 3307 adds r3, #7 - 8003d34: b2d2 uxtb r2, r2 - 8003d36: 701a strb r2, [r3, #0] + 8003dba: 68fb ldr r3, [r7, #12] + 8003dbc: 681a ldr r2, [r3, #0] + 8003dbe: 68bb ldr r3, [r7, #8] + 8003dc0: 011b lsls r3, r3, #4 + 8003dc2: 4413 add r3, r2 + 8003dc4: f503 73de add.w r3, r3, #444 @ 0x1bc + 8003dc8: 681b ldr r3, [r3, #0] + 8003dca: 0e1a lsrs r2, r3, #24 + 8003dcc: 683b ldr r3, [r7, #0] + 8003dce: 3307 adds r3, #7 + 8003dd0: b2d2 uxtb r2, r2 + 8003dd2: 701a strb r2, [r3, #0] /* Release the FIFO */ if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ - 8003d38: 68bb ldr r3, [r7, #8] - 8003d3a: 2b00 cmp r3, #0 - 8003d3c: d108 bne.n 8003d50 + 8003dd4: 68bb ldr r3, [r7, #8] + 8003dd6: 2b00 cmp r3, #0 + 8003dd8: d108 bne.n 8003dec { /* Release RX FIFO 0 */ SET_BIT(hcan->Instance->RF0R, CAN_RF0R_RFOM0); - 8003d3e: 68fb ldr r3, [r7, #12] - 8003d40: 681b ldr r3, [r3, #0] - 8003d42: 68da ldr r2, [r3, #12] - 8003d44: 68fb ldr r3, [r7, #12] - 8003d46: 681b ldr r3, [r3, #0] - 8003d48: f042 0220 orr.w r2, r2, #32 - 8003d4c: 60da str r2, [r3, #12] - 8003d4e: e007 b.n 8003d60 + 8003dda: 68fb ldr r3, [r7, #12] + 8003ddc: 681b ldr r3, [r3, #0] + 8003dde: 68da ldr r2, [r3, #12] + 8003de0: 68fb ldr r3, [r7, #12] + 8003de2: 681b ldr r3, [r3, #0] + 8003de4: f042 0220 orr.w r2, r2, #32 + 8003de8: 60da str r2, [r3, #12] + 8003dea: e007 b.n 8003dfc } else /* Rx element is assigned to Rx FIFO 1 */ { /* Release RX FIFO 1 */ SET_BIT(hcan->Instance->RF1R, CAN_RF1R_RFOM1); - 8003d50: 68fb ldr r3, [r7, #12] - 8003d52: 681b ldr r3, [r3, #0] - 8003d54: 691a ldr r2, [r3, #16] - 8003d56: 68fb ldr r3, [r7, #12] - 8003d58: 681b ldr r3, [r3, #0] - 8003d5a: f042 0220 orr.w r2, r2, #32 - 8003d5e: 611a str r2, [r3, #16] + 8003dec: 68fb ldr r3, [r7, #12] + 8003dee: 681b ldr r3, [r3, #0] + 8003df0: 691a ldr r2, [r3, #16] + 8003df2: 68fb ldr r3, [r7, #12] + 8003df4: 681b ldr r3, [r3, #0] + 8003df6: f042 0220 orr.w r2, r2, #32 + 8003dfa: 611a str r2, [r3, #16] } /* Return function status */ return HAL_OK; - 8003d60: 2300 movs r3, #0 - 8003d62: e006 b.n 8003d72 + 8003dfc: 2300 movs r3, #0 + 8003dfe: e006 b.n 8003e0e } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; - 8003d64: 68fb ldr r3, [r7, #12] - 8003d66: 6a5b ldr r3, [r3, #36] @ 0x24 - 8003d68: f443 2280 orr.w r2, r3, #262144 @ 0x40000 - 8003d6c: 68fb ldr r3, [r7, #12] - 8003d6e: 625a str r2, [r3, #36] @ 0x24 + 8003e00: 68fb ldr r3, [r7, #12] + 8003e02: 6a5b ldr r3, [r3, #36] @ 0x24 + 8003e04: f443 2280 orr.w r2, r3, #262144 @ 0x40000 + 8003e08: 68fb ldr r3, [r7, #12] + 8003e0a: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; - 8003d70: 2301 movs r3, #1 + 8003e0c: 2301 movs r3, #1 } } - 8003d72: 4618 mov r0, r3 - 8003d74: 371c adds r7, #28 - 8003d76: 46bd mov sp, r7 - 8003d78: f85d 7b04 ldr.w r7, [sp], #4 - 8003d7c: 4770 bx lr + 8003e0e: 4618 mov r0, r3 + 8003e10: 371c adds r7, #28 + 8003e12: 46bd mov sp, r7 + 8003e14: f85d 7b04 ldr.w r7, [sp], #4 + 8003e18: 4770 bx lr -08003d7e : +08003e1a : * @param ActiveITs indicates which interrupts will be enabled. * This parameter can be any combination of @arg CAN_Interrupts. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs) { - 8003d7e: b480 push {r7} - 8003d80: b085 sub sp, #20 - 8003d82: af00 add r7, sp, #0 - 8003d84: 6078 str r0, [r7, #4] - 8003d86: 6039 str r1, [r7, #0] + 8003e1a: b480 push {r7} + 8003e1c: b085 sub sp, #20 + 8003e1e: af00 add r7, sp, #0 + 8003e20: 6078 str r0, [r7, #4] + 8003e22: 6039 str r1, [r7, #0] HAL_CAN_StateTypeDef state = hcan->State; - 8003d88: 687b ldr r3, [r7, #4] - 8003d8a: f893 3020 ldrb.w r3, [r3, #32] - 8003d8e: 73fb strb r3, [r7, #15] + 8003e24: 687b ldr r3, [r7, #4] + 8003e26: f893 3020 ldrb.w r3, [r3, #32] + 8003e2a: 73fb strb r3, [r7, #15] /* Check function parameters */ assert_param(IS_CAN_IT(ActiveITs)); if ((state == HAL_CAN_STATE_READY) || - 8003d90: 7bfb ldrb r3, [r7, #15] - 8003d92: 2b01 cmp r3, #1 - 8003d94: d002 beq.n 8003d9c - 8003d96: 7bfb ldrb r3, [r7, #15] - 8003d98: 2b02 cmp r3, #2 - 8003d9a: d109 bne.n 8003db0 + 8003e2c: 7bfb ldrb r3, [r7, #15] + 8003e2e: 2b01 cmp r3, #1 + 8003e30: d002 beq.n 8003e38 + 8003e32: 7bfb ldrb r3, [r7, #15] + 8003e34: 2b02 cmp r3, #2 + 8003e36: d109 bne.n 8003e4c (state == HAL_CAN_STATE_LISTENING)) { /* Enable the selected interrupts */ __HAL_CAN_ENABLE_IT(hcan, ActiveITs); - 8003d9c: 687b ldr r3, [r7, #4] - 8003d9e: 681b ldr r3, [r3, #0] - 8003da0: 6959 ldr r1, [r3, #20] - 8003da2: 687b ldr r3, [r7, #4] - 8003da4: 681b ldr r3, [r3, #0] - 8003da6: 683a ldr r2, [r7, #0] - 8003da8: 430a orrs r2, r1 - 8003daa: 615a str r2, [r3, #20] + 8003e38: 687b ldr r3, [r7, #4] + 8003e3a: 681b ldr r3, [r3, #0] + 8003e3c: 6959 ldr r1, [r3, #20] + 8003e3e: 687b ldr r3, [r7, #4] + 8003e40: 681b ldr r3, [r3, #0] + 8003e42: 683a ldr r2, [r7, #0] + 8003e44: 430a orrs r2, r1 + 8003e46: 615a str r2, [r3, #20] /* Return function status */ return HAL_OK; - 8003dac: 2300 movs r3, #0 - 8003dae: e006 b.n 8003dbe + 8003e48: 2300 movs r3, #0 + 8003e4a: e006 b.n 8003e5a } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; - 8003db0: 687b ldr r3, [r7, #4] - 8003db2: 6a5b ldr r3, [r3, #36] @ 0x24 - 8003db4: f443 2280 orr.w r2, r3, #262144 @ 0x40000 - 8003db8: 687b ldr r3, [r7, #4] - 8003dba: 625a str r2, [r3, #36] @ 0x24 + 8003e4c: 687b ldr r3, [r7, #4] + 8003e4e: 6a5b ldr r3, [r3, #36] @ 0x24 + 8003e50: f443 2280 orr.w r2, r3, #262144 @ 0x40000 + 8003e54: 687b ldr r3, [r7, #4] + 8003e56: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; - 8003dbc: 2301 movs r3, #1 + 8003e58: 2301 movs r3, #1 } } - 8003dbe: 4618 mov r0, r3 - 8003dc0: 3714 adds r7, #20 - 8003dc2: 46bd mov sp, r7 - 8003dc4: f85d 7b04 ldr.w r7, [sp], #4 - 8003dc8: 4770 bx lr + 8003e5a: 4618 mov r0, r3 + 8003e5c: 3714 adds r7, #20 + 8003e5e: 46bd mov sp, r7 + 8003e60: f85d 7b04 ldr.w r7, [sp], #4 + 8003e64: 4770 bx lr -08003dca : +08003e66 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan) { - 8003dca: b580 push {r7, lr} - 8003dcc: b08a sub sp, #40 @ 0x28 - 8003dce: af00 add r7, sp, #0 - 8003dd0: 6078 str r0, [r7, #4] + 8003e66: b580 push {r7, lr} + 8003e68: b08a sub sp, #40 @ 0x28 + 8003e6a: af00 add r7, sp, #0 + 8003e6c: 6078 str r0, [r7, #4] uint32_t errorcode = HAL_CAN_ERROR_NONE; - 8003dd2: 2300 movs r3, #0 - 8003dd4: 627b str r3, [r7, #36] @ 0x24 + 8003e6e: 2300 movs r3, #0 + 8003e70: 627b str r3, [r7, #36] @ 0x24 uint32_t interrupts = READ_REG(hcan->Instance->IER); - 8003dd6: 687b ldr r3, [r7, #4] - 8003dd8: 681b ldr r3, [r3, #0] - 8003dda: 695b ldr r3, [r3, #20] - 8003ddc: 623b str r3, [r7, #32] + 8003e72: 687b ldr r3, [r7, #4] + 8003e74: 681b ldr r3, [r3, #0] + 8003e76: 695b ldr r3, [r3, #20] + 8003e78: 623b str r3, [r7, #32] uint32_t msrflags = READ_REG(hcan->Instance->MSR); - 8003dde: 687b ldr r3, [r7, #4] - 8003de0: 681b ldr r3, [r3, #0] - 8003de2: 685b ldr r3, [r3, #4] - 8003de4: 61fb str r3, [r7, #28] + 8003e7a: 687b ldr r3, [r7, #4] + 8003e7c: 681b ldr r3, [r3, #0] + 8003e7e: 685b ldr r3, [r3, #4] + 8003e80: 61fb str r3, [r7, #28] uint32_t tsrflags = READ_REG(hcan->Instance->TSR); - 8003de6: 687b ldr r3, [r7, #4] - 8003de8: 681b ldr r3, [r3, #0] - 8003dea: 689b ldr r3, [r3, #8] - 8003dec: 61bb str r3, [r7, #24] + 8003e82: 687b ldr r3, [r7, #4] + 8003e84: 681b ldr r3, [r3, #0] + 8003e86: 689b ldr r3, [r3, #8] + 8003e88: 61bb str r3, [r7, #24] uint32_t rf0rflags = READ_REG(hcan->Instance->RF0R); - 8003dee: 687b ldr r3, [r7, #4] - 8003df0: 681b ldr r3, [r3, #0] - 8003df2: 68db ldr r3, [r3, #12] - 8003df4: 617b str r3, [r7, #20] + 8003e8a: 687b ldr r3, [r7, #4] + 8003e8c: 681b ldr r3, [r3, #0] + 8003e8e: 68db ldr r3, [r3, #12] + 8003e90: 617b str r3, [r7, #20] uint32_t rf1rflags = READ_REG(hcan->Instance->RF1R); - 8003df6: 687b ldr r3, [r7, #4] - 8003df8: 681b ldr r3, [r3, #0] - 8003dfa: 691b ldr r3, [r3, #16] - 8003dfc: 613b str r3, [r7, #16] + 8003e92: 687b ldr r3, [r7, #4] + 8003e94: 681b ldr r3, [r3, #0] + 8003e96: 691b ldr r3, [r3, #16] + 8003e98: 613b str r3, [r7, #16] uint32_t esrflags = READ_REG(hcan->Instance->ESR); - 8003dfe: 687b ldr r3, [r7, #4] - 8003e00: 681b ldr r3, [r3, #0] - 8003e02: 699b ldr r3, [r3, #24] - 8003e04: 60fb str r3, [r7, #12] + 8003e9a: 687b ldr r3, [r7, #4] + 8003e9c: 681b ldr r3, [r3, #0] + 8003e9e: 699b ldr r3, [r3, #24] + 8003ea0: 60fb str r3, [r7, #12] /* Transmit Mailbox empty interrupt management *****************************/ if ((interrupts & CAN_IT_TX_MAILBOX_EMPTY) != 0U) - 8003e06: 6a3b ldr r3, [r7, #32] - 8003e08: f003 0301 and.w r3, r3, #1 - 8003e0c: 2b00 cmp r3, #0 - 8003e0e: d07c beq.n 8003f0a + 8003ea2: 6a3b ldr r3, [r7, #32] + 8003ea4: f003 0301 and.w r3, r3, #1 + 8003ea8: 2b00 cmp r3, #0 + 8003eaa: d07c beq.n 8003fa6 { /* Transmit Mailbox 0 management *****************************************/ if ((tsrflags & CAN_TSR_RQCP0) != 0U) - 8003e10: 69bb ldr r3, [r7, #24] - 8003e12: f003 0301 and.w r3, r3, #1 - 8003e16: 2b00 cmp r3, #0 - 8003e18: d023 beq.n 8003e62 + 8003eac: 69bb ldr r3, [r7, #24] + 8003eae: f003 0301 and.w r3, r3, #1 + 8003eb2: 2b00 cmp r3, #0 + 8003eb4: d023 beq.n 8003efe { /* Clear the Transmission Complete flag (and TXOK0,ALST0,TERR0 bits) */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP0); - 8003e1a: 687b ldr r3, [r7, #4] - 8003e1c: 681b ldr r3, [r3, #0] - 8003e1e: 2201 movs r2, #1 - 8003e20: 609a str r2, [r3, #8] + 8003eb6: 687b ldr r3, [r7, #4] + 8003eb8: 681b ldr r3, [r3, #0] + 8003eba: 2201 movs r2, #1 + 8003ebc: 609a str r2, [r3, #8] if ((tsrflags & CAN_TSR_TXOK0) != 0U) - 8003e22: 69bb ldr r3, [r7, #24] - 8003e24: f003 0302 and.w r3, r3, #2 - 8003e28: 2b00 cmp r3, #0 - 8003e2a: d003 beq.n 8003e34 + 8003ebe: 69bb ldr r3, [r7, #24] + 8003ec0: f003 0302 and.w r3, r3, #2 + 8003ec4: 2b00 cmp r3, #0 + 8003ec6: d003 beq.n 8003ed0 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox0CompleteCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox0CompleteCallback(hcan); - 8003e2c: 6878 ldr r0, [r7, #4] - 8003e2e: f000 f983 bl 8004138 - 8003e32: e016 b.n 8003e62 + 8003ec8: 6878 ldr r0, [r7, #4] + 8003eca: f000 f983 bl 80041d4 + 8003ece: e016 b.n 8003efe #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } else { if ((tsrflags & CAN_TSR_ALST0) != 0U) - 8003e34: 69bb ldr r3, [r7, #24] - 8003e36: f003 0304 and.w r3, r3, #4 - 8003e3a: 2b00 cmp r3, #0 - 8003e3c: d004 beq.n 8003e48 + 8003ed0: 69bb ldr r3, [r7, #24] + 8003ed2: f003 0304 and.w r3, r3, #4 + 8003ed6: 2b00 cmp r3, #0 + 8003ed8: d004 beq.n 8003ee4 { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_ALST0; - 8003e3e: 6a7b ldr r3, [r7, #36] @ 0x24 - 8003e40: f443 6300 orr.w r3, r3, #2048 @ 0x800 - 8003e44: 627b str r3, [r7, #36] @ 0x24 - 8003e46: e00c b.n 8003e62 + 8003eda: 6a7b ldr r3, [r7, #36] @ 0x24 + 8003edc: f443 6300 orr.w r3, r3, #2048 @ 0x800 + 8003ee0: 627b str r3, [r7, #36] @ 0x24 + 8003ee2: e00c b.n 8003efe } else if ((tsrflags & CAN_TSR_TERR0) != 0U) - 8003e48: 69bb ldr r3, [r7, #24] - 8003e4a: f003 0308 and.w r3, r3, #8 - 8003e4e: 2b00 cmp r3, #0 - 8003e50: d004 beq.n 8003e5c + 8003ee4: 69bb ldr r3, [r7, #24] + 8003ee6: f003 0308 and.w r3, r3, #8 + 8003eea: 2b00 cmp r3, #0 + 8003eec: d004 beq.n 8003ef8 { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_TERR0; - 8003e52: 6a7b ldr r3, [r7, #36] @ 0x24 - 8003e54: f443 5380 orr.w r3, r3, #4096 @ 0x1000 - 8003e58: 627b str r3, [r7, #36] @ 0x24 - 8003e5a: e002 b.n 8003e62 + 8003eee: 6a7b ldr r3, [r7, #36] @ 0x24 + 8003ef0: f443 5380 orr.w r3, r3, #4096 @ 0x1000 + 8003ef4: 627b str r3, [r7, #36] @ 0x24 + 8003ef6: e002 b.n 8003efe #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox0AbortCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox0AbortCallback(hcan); - 8003e5c: 6878 ldr r0, [r7, #4] - 8003e5e: f000 f989 bl 8004174 + 8003ef8: 6878 ldr r0, [r7, #4] + 8003efa: f000 f989 bl 8004210 } } } /* Transmit Mailbox 1 management *****************************************/ if ((tsrflags & CAN_TSR_RQCP1) != 0U) - 8003e62: 69bb ldr r3, [r7, #24] - 8003e64: f403 7380 and.w r3, r3, #256 @ 0x100 - 8003e68: 2b00 cmp r3, #0 - 8003e6a: d024 beq.n 8003eb6 + 8003efe: 69bb ldr r3, [r7, #24] + 8003f00: f403 7380 and.w r3, r3, #256 @ 0x100 + 8003f04: 2b00 cmp r3, #0 + 8003f06: d024 beq.n 8003f52 { /* Clear the Transmission Complete flag (and TXOK1,ALST1,TERR1 bits) */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP1); - 8003e6c: 687b ldr r3, [r7, #4] - 8003e6e: 681b ldr r3, [r3, #0] - 8003e70: f44f 7280 mov.w r2, #256 @ 0x100 - 8003e74: 609a str r2, [r3, #8] + 8003f08: 687b ldr r3, [r7, #4] + 8003f0a: 681b ldr r3, [r3, #0] + 8003f0c: f44f 7280 mov.w r2, #256 @ 0x100 + 8003f10: 609a str r2, [r3, #8] if ((tsrflags & CAN_TSR_TXOK1) != 0U) - 8003e76: 69bb ldr r3, [r7, #24] - 8003e78: f403 7300 and.w r3, r3, #512 @ 0x200 - 8003e7c: 2b00 cmp r3, #0 - 8003e7e: d003 beq.n 8003e88 + 8003f12: 69bb ldr r3, [r7, #24] + 8003f14: f403 7300 and.w r3, r3, #512 @ 0x200 + 8003f18: 2b00 cmp r3, #0 + 8003f1a: d003 beq.n 8003f24 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox1CompleteCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox1CompleteCallback(hcan); - 8003e80: 6878 ldr r0, [r7, #4] - 8003e82: f000 f963 bl 800414c - 8003e86: e016 b.n 8003eb6 + 8003f1c: 6878 ldr r0, [r7, #4] + 8003f1e: f000 f963 bl 80041e8 + 8003f22: e016 b.n 8003f52 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } else { if ((tsrflags & CAN_TSR_ALST1) != 0U) - 8003e88: 69bb ldr r3, [r7, #24] - 8003e8a: f403 6380 and.w r3, r3, #1024 @ 0x400 - 8003e8e: 2b00 cmp r3, #0 - 8003e90: d004 beq.n 8003e9c + 8003f24: 69bb ldr r3, [r7, #24] + 8003f26: f403 6380 and.w r3, r3, #1024 @ 0x400 + 8003f2a: 2b00 cmp r3, #0 + 8003f2c: d004 beq.n 8003f38 { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_ALST1; - 8003e92: 6a7b ldr r3, [r7, #36] @ 0x24 - 8003e94: f443 5300 orr.w r3, r3, #8192 @ 0x2000 - 8003e98: 627b str r3, [r7, #36] @ 0x24 - 8003e9a: e00c b.n 8003eb6 + 8003f2e: 6a7b ldr r3, [r7, #36] @ 0x24 + 8003f30: f443 5300 orr.w r3, r3, #8192 @ 0x2000 + 8003f34: 627b str r3, [r7, #36] @ 0x24 + 8003f36: e00c b.n 8003f52 } else if ((tsrflags & CAN_TSR_TERR1) != 0U) - 8003e9c: 69bb ldr r3, [r7, #24] - 8003e9e: f403 6300 and.w r3, r3, #2048 @ 0x800 - 8003ea2: 2b00 cmp r3, #0 - 8003ea4: d004 beq.n 8003eb0 + 8003f38: 69bb ldr r3, [r7, #24] + 8003f3a: f403 6300 and.w r3, r3, #2048 @ 0x800 + 8003f3e: 2b00 cmp r3, #0 + 8003f40: d004 beq.n 8003f4c { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_TERR1; - 8003ea6: 6a7b ldr r3, [r7, #36] @ 0x24 - 8003ea8: f443 4380 orr.w r3, r3, #16384 @ 0x4000 - 8003eac: 627b str r3, [r7, #36] @ 0x24 - 8003eae: e002 b.n 8003eb6 + 8003f42: 6a7b ldr r3, [r7, #36] @ 0x24 + 8003f44: f443 4380 orr.w r3, r3, #16384 @ 0x4000 + 8003f48: 627b str r3, [r7, #36] @ 0x24 + 8003f4a: e002 b.n 8003f52 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox1AbortCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox1AbortCallback(hcan); - 8003eb0: 6878 ldr r0, [r7, #4] - 8003eb2: f000 f969 bl 8004188 + 8003f4c: 6878 ldr r0, [r7, #4] + 8003f4e: f000 f969 bl 8004224 } } } /* Transmit Mailbox 2 management *****************************************/ if ((tsrflags & CAN_TSR_RQCP2) != 0U) - 8003eb6: 69bb ldr r3, [r7, #24] - 8003eb8: f403 3380 and.w r3, r3, #65536 @ 0x10000 - 8003ebc: 2b00 cmp r3, #0 - 8003ebe: d024 beq.n 8003f0a + 8003f52: 69bb ldr r3, [r7, #24] + 8003f54: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 8003f58: 2b00 cmp r3, #0 + 8003f5a: d024 beq.n 8003fa6 { /* Clear the Transmission Complete flag (and TXOK2,ALST2,TERR2 bits) */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP2); - 8003ec0: 687b ldr r3, [r7, #4] - 8003ec2: 681b ldr r3, [r3, #0] - 8003ec4: f44f 3280 mov.w r2, #65536 @ 0x10000 - 8003ec8: 609a str r2, [r3, #8] + 8003f5c: 687b ldr r3, [r7, #4] + 8003f5e: 681b ldr r3, [r3, #0] + 8003f60: f44f 3280 mov.w r2, #65536 @ 0x10000 + 8003f64: 609a str r2, [r3, #8] if ((tsrflags & CAN_TSR_TXOK2) != 0U) - 8003eca: 69bb ldr r3, [r7, #24] - 8003ecc: f403 3300 and.w r3, r3, #131072 @ 0x20000 - 8003ed0: 2b00 cmp r3, #0 - 8003ed2: d003 beq.n 8003edc + 8003f66: 69bb ldr r3, [r7, #24] + 8003f68: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 8003f6c: 2b00 cmp r3, #0 + 8003f6e: d003 beq.n 8003f78 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox2CompleteCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox2CompleteCallback(hcan); - 8003ed4: 6878 ldr r0, [r7, #4] - 8003ed6: f000 f943 bl 8004160 - 8003eda: e016 b.n 8003f0a + 8003f70: 6878 ldr r0, [r7, #4] + 8003f72: f000 f943 bl 80041fc + 8003f76: e016 b.n 8003fa6 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } else { if ((tsrflags & CAN_TSR_ALST2) != 0U) - 8003edc: 69bb ldr r3, [r7, #24] - 8003ede: f403 2380 and.w r3, r3, #262144 @ 0x40000 - 8003ee2: 2b00 cmp r3, #0 - 8003ee4: d004 beq.n 8003ef0 + 8003f78: 69bb ldr r3, [r7, #24] + 8003f7a: f403 2380 and.w r3, r3, #262144 @ 0x40000 + 8003f7e: 2b00 cmp r3, #0 + 8003f80: d004 beq.n 8003f8c { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_ALST2; - 8003ee6: 6a7b ldr r3, [r7, #36] @ 0x24 - 8003ee8: f443 4300 orr.w r3, r3, #32768 @ 0x8000 - 8003eec: 627b str r3, [r7, #36] @ 0x24 - 8003eee: e00c b.n 8003f0a + 8003f82: 6a7b ldr r3, [r7, #36] @ 0x24 + 8003f84: f443 4300 orr.w r3, r3, #32768 @ 0x8000 + 8003f88: 627b str r3, [r7, #36] @ 0x24 + 8003f8a: e00c b.n 8003fa6 } else if ((tsrflags & CAN_TSR_TERR2) != 0U) - 8003ef0: 69bb ldr r3, [r7, #24] - 8003ef2: f403 2300 and.w r3, r3, #524288 @ 0x80000 - 8003ef6: 2b00 cmp r3, #0 - 8003ef8: d004 beq.n 8003f04 + 8003f8c: 69bb ldr r3, [r7, #24] + 8003f8e: f403 2300 and.w r3, r3, #524288 @ 0x80000 + 8003f92: 2b00 cmp r3, #0 + 8003f94: d004 beq.n 8003fa0 { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_TERR2; - 8003efa: 6a7b ldr r3, [r7, #36] @ 0x24 - 8003efc: f443 3380 orr.w r3, r3, #65536 @ 0x10000 - 8003f00: 627b str r3, [r7, #36] @ 0x24 - 8003f02: e002 b.n 8003f0a + 8003f96: 6a7b ldr r3, [r7, #36] @ 0x24 + 8003f98: f443 3380 orr.w r3, r3, #65536 @ 0x10000 + 8003f9c: 627b str r3, [r7, #36] @ 0x24 + 8003f9e: e002 b.n 8003fa6 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox2AbortCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox2AbortCallback(hcan); - 8003f04: 6878 ldr r0, [r7, #4] - 8003f06: f000 f949 bl 800419c + 8003fa0: 6878 ldr r0, [r7, #4] + 8003fa2: f000 f949 bl 8004238 } } } /* Receive FIFO 0 overrun interrupt management *****************************/ if ((interrupts & CAN_IT_RX_FIFO0_OVERRUN) != 0U) - 8003f0a: 6a3b ldr r3, [r7, #32] - 8003f0c: f003 0308 and.w r3, r3, #8 - 8003f10: 2b00 cmp r3, #0 - 8003f12: d00c beq.n 8003f2e + 8003fa6: 6a3b ldr r3, [r7, #32] + 8003fa8: f003 0308 and.w r3, r3, #8 + 8003fac: 2b00 cmp r3, #0 + 8003fae: d00c beq.n 8003fca { if ((rf0rflags & CAN_RF0R_FOVR0) != 0U) - 8003f14: 697b ldr r3, [r7, #20] - 8003f16: f003 0310 and.w r3, r3, #16 - 8003f1a: 2b00 cmp r3, #0 - 8003f1c: d007 beq.n 8003f2e + 8003fb0: 697b ldr r3, [r7, #20] + 8003fb2: f003 0310 and.w r3, r3, #16 + 8003fb6: 2b00 cmp r3, #0 + 8003fb8: d007 beq.n 8003fca { /* Set CAN error code to Rx Fifo 0 overrun error */ errorcode |= HAL_CAN_ERROR_RX_FOV0; - 8003f1e: 6a7b ldr r3, [r7, #36] @ 0x24 - 8003f20: f443 7300 orr.w r3, r3, #512 @ 0x200 - 8003f24: 627b str r3, [r7, #36] @ 0x24 + 8003fba: 6a7b ldr r3, [r7, #36] @ 0x24 + 8003fbc: f443 7300 orr.w r3, r3, #512 @ 0x200 + 8003fc0: 627b str r3, [r7, #36] @ 0x24 /* Clear FIFO0 Overrun Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0); - 8003f26: 687b ldr r3, [r7, #4] - 8003f28: 681b ldr r3, [r3, #0] - 8003f2a: 2210 movs r2, #16 - 8003f2c: 60da str r2, [r3, #12] + 8003fc2: 687b ldr r3, [r7, #4] + 8003fc4: 681b ldr r3, [r3, #0] + 8003fc6: 2210 movs r2, #16 + 8003fc8: 60da str r2, [r3, #12] } } /* Receive FIFO 0 full interrupt management ********************************/ if ((interrupts & CAN_IT_RX_FIFO0_FULL) != 0U) - 8003f2e: 6a3b ldr r3, [r7, #32] - 8003f30: f003 0304 and.w r3, r3, #4 - 8003f34: 2b00 cmp r3, #0 - 8003f36: d00b beq.n 8003f50 + 8003fca: 6a3b ldr r3, [r7, #32] + 8003fcc: f003 0304 and.w r3, r3, #4 + 8003fd0: 2b00 cmp r3, #0 + 8003fd2: d00b beq.n 8003fec { if ((rf0rflags & CAN_RF0R_FULL0) != 0U) - 8003f38: 697b ldr r3, [r7, #20] - 8003f3a: f003 0308 and.w r3, r3, #8 - 8003f3e: 2b00 cmp r3, #0 - 8003f40: d006 beq.n 8003f50 + 8003fd4: 697b ldr r3, [r7, #20] + 8003fd6: f003 0308 and.w r3, r3, #8 + 8003fda: 2b00 cmp r3, #0 + 8003fdc: d006 beq.n 8003fec { /* Clear FIFO 0 full Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0); - 8003f42: 687b ldr r3, [r7, #4] - 8003f44: 681b ldr r3, [r3, #0] - 8003f46: 2208 movs r2, #8 - 8003f48: 60da str r2, [r3, #12] + 8003fde: 687b ldr r3, [r7, #4] + 8003fe0: 681b ldr r3, [r3, #0] + 8003fe2: 2208 movs r2, #8 + 8003fe4: 60da str r2, [r3, #12] #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo0FullCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo0FullCallback(hcan); - 8003f4a: 6878 ldr r0, [r7, #4] - 8003f4c: f000 f930 bl 80041b0 + 8003fe6: 6878 ldr r0, [r7, #4] + 8003fe8: f000 f930 bl 800424c #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Receive FIFO 0 message pending interrupt management *********************/ if ((interrupts & CAN_IT_RX_FIFO0_MSG_PENDING) != 0U) - 8003f50: 6a3b ldr r3, [r7, #32] - 8003f52: f003 0302 and.w r3, r3, #2 - 8003f56: 2b00 cmp r3, #0 - 8003f58: d009 beq.n 8003f6e + 8003fec: 6a3b ldr r3, [r7, #32] + 8003fee: f003 0302 and.w r3, r3, #2 + 8003ff2: 2b00 cmp r3, #0 + 8003ff4: d009 beq.n 800400a { /* Check if message is still pending */ if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != 0U) - 8003f5a: 687b ldr r3, [r7, #4] - 8003f5c: 681b ldr r3, [r3, #0] - 8003f5e: 68db ldr r3, [r3, #12] - 8003f60: f003 0303 and.w r3, r3, #3 - 8003f64: 2b00 cmp r3, #0 - 8003f66: d002 beq.n 8003f6e + 8003ff6: 687b ldr r3, [r7, #4] + 8003ff8: 681b ldr r3, [r3, #0] + 8003ffa: 68db ldr r3, [r3, #12] + 8003ffc: f003 0303 and.w r3, r3, #3 + 8004000: 2b00 cmp r3, #0 + 8004002: d002 beq.n 800400a #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo0MsgPendingCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo0MsgPendingCallback(hcan); - 8003f68: 6878 ldr r0, [r7, #4] - 8003f6a: f7fc fe17 bl 8000b9c + 8004004: 6878 ldr r0, [r7, #4] + 8004006: f7fc fddf bl 8000bc8 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Receive FIFO 1 overrun interrupt management *****************************/ if ((interrupts & CAN_IT_RX_FIFO1_OVERRUN) != 0U) - 8003f6e: 6a3b ldr r3, [r7, #32] - 8003f70: f003 0340 and.w r3, r3, #64 @ 0x40 - 8003f74: 2b00 cmp r3, #0 - 8003f76: d00c beq.n 8003f92 + 800400a: 6a3b ldr r3, [r7, #32] + 800400c: f003 0340 and.w r3, r3, #64 @ 0x40 + 8004010: 2b00 cmp r3, #0 + 8004012: d00c beq.n 800402e { if ((rf1rflags & CAN_RF1R_FOVR1) != 0U) - 8003f78: 693b ldr r3, [r7, #16] - 8003f7a: f003 0310 and.w r3, r3, #16 - 8003f7e: 2b00 cmp r3, #0 - 8003f80: d007 beq.n 8003f92 + 8004014: 693b ldr r3, [r7, #16] + 8004016: f003 0310 and.w r3, r3, #16 + 800401a: 2b00 cmp r3, #0 + 800401c: d007 beq.n 800402e { /* Set CAN error code to Rx Fifo 1 overrun error */ errorcode |= HAL_CAN_ERROR_RX_FOV1; - 8003f82: 6a7b ldr r3, [r7, #36] @ 0x24 - 8003f84: f443 6380 orr.w r3, r3, #1024 @ 0x400 - 8003f88: 627b str r3, [r7, #36] @ 0x24 + 800401e: 6a7b ldr r3, [r7, #36] @ 0x24 + 8004020: f443 6380 orr.w r3, r3, #1024 @ 0x400 + 8004024: 627b str r3, [r7, #36] @ 0x24 /* Clear FIFO1 Overrun Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1); - 8003f8a: 687b ldr r3, [r7, #4] - 8003f8c: 681b ldr r3, [r3, #0] - 8003f8e: 2210 movs r2, #16 - 8003f90: 611a str r2, [r3, #16] + 8004026: 687b ldr r3, [r7, #4] + 8004028: 681b ldr r3, [r3, #0] + 800402a: 2210 movs r2, #16 + 800402c: 611a str r2, [r3, #16] } } /* Receive FIFO 1 full interrupt management ********************************/ if ((interrupts & CAN_IT_RX_FIFO1_FULL) != 0U) - 8003f92: 6a3b ldr r3, [r7, #32] - 8003f94: f003 0320 and.w r3, r3, #32 - 8003f98: 2b00 cmp r3, #0 - 8003f9a: d00b beq.n 8003fb4 + 800402e: 6a3b ldr r3, [r7, #32] + 8004030: f003 0320 and.w r3, r3, #32 + 8004034: 2b00 cmp r3, #0 + 8004036: d00b beq.n 8004050 { if ((rf1rflags & CAN_RF1R_FULL1) != 0U) - 8003f9c: 693b ldr r3, [r7, #16] - 8003f9e: f003 0308 and.w r3, r3, #8 - 8003fa2: 2b00 cmp r3, #0 - 8003fa4: d006 beq.n 8003fb4 + 8004038: 693b ldr r3, [r7, #16] + 800403a: f003 0308 and.w r3, r3, #8 + 800403e: 2b00 cmp r3, #0 + 8004040: d006 beq.n 8004050 { /* Clear FIFO 1 full Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1); - 8003fa6: 687b ldr r3, [r7, #4] - 8003fa8: 681b ldr r3, [r3, #0] - 8003faa: 2208 movs r2, #8 - 8003fac: 611a str r2, [r3, #16] + 8004042: 687b ldr r3, [r7, #4] + 8004044: 681b ldr r3, [r3, #0] + 8004046: 2208 movs r2, #8 + 8004048: 611a str r2, [r3, #16] #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo1FullCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo1FullCallback(hcan); - 8003fae: 6878 ldr r0, [r7, #4] - 8003fb0: f000 f912 bl 80041d8 + 800404a: 6878 ldr r0, [r7, #4] + 800404c: f000 f912 bl 8004274 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Receive FIFO 1 message pending interrupt management *********************/ if ((interrupts & CAN_IT_RX_FIFO1_MSG_PENDING) != 0U) - 8003fb4: 6a3b ldr r3, [r7, #32] - 8003fb6: f003 0310 and.w r3, r3, #16 - 8003fba: 2b00 cmp r3, #0 - 8003fbc: d009 beq.n 8003fd2 + 8004050: 6a3b ldr r3, [r7, #32] + 8004052: f003 0310 and.w r3, r3, #16 + 8004056: 2b00 cmp r3, #0 + 8004058: d009 beq.n 800406e { /* Check if message is still pending */ if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != 0U) - 8003fbe: 687b ldr r3, [r7, #4] - 8003fc0: 681b ldr r3, [r3, #0] - 8003fc2: 691b ldr r3, [r3, #16] - 8003fc4: f003 0303 and.w r3, r3, #3 - 8003fc8: 2b00 cmp r3, #0 - 8003fca: d002 beq.n 8003fd2 + 800405a: 687b ldr r3, [r7, #4] + 800405c: 681b ldr r3, [r3, #0] + 800405e: 691b ldr r3, [r3, #16] + 8004060: f003 0303 and.w r3, r3, #3 + 8004064: 2b00 cmp r3, #0 + 8004066: d002 beq.n 800406e #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo1MsgPendingCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo1MsgPendingCallback(hcan); - 8003fcc: 6878 ldr r0, [r7, #4] - 8003fce: f000 f8f9 bl 80041c4 + 8004068: 6878 ldr r0, [r7, #4] + 800406a: f000 f8f9 bl 8004260 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Sleep interrupt management *********************************************/ if ((interrupts & CAN_IT_SLEEP_ACK) != 0U) - 8003fd2: 6a3b ldr r3, [r7, #32] - 8003fd4: f403 3300 and.w r3, r3, #131072 @ 0x20000 - 8003fd8: 2b00 cmp r3, #0 - 8003fda: d00b beq.n 8003ff4 + 800406e: 6a3b ldr r3, [r7, #32] + 8004070: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 8004074: 2b00 cmp r3, #0 + 8004076: d00b beq.n 8004090 { if ((msrflags & CAN_MSR_SLAKI) != 0U) - 8003fdc: 69fb ldr r3, [r7, #28] - 8003fde: f003 0310 and.w r3, r3, #16 - 8003fe2: 2b00 cmp r3, #0 - 8003fe4: d006 beq.n 8003ff4 + 8004078: 69fb ldr r3, [r7, #28] + 800407a: f003 0310 and.w r3, r3, #16 + 800407e: 2b00 cmp r3, #0 + 8004080: d006 beq.n 8004090 { /* Clear Sleep interrupt Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_SLAKI); - 8003fe6: 687b ldr r3, [r7, #4] - 8003fe8: 681b ldr r3, [r3, #0] - 8003fea: 2210 movs r2, #16 - 8003fec: 605a str r2, [r3, #4] + 8004082: 687b ldr r3, [r7, #4] + 8004084: 681b ldr r3, [r3, #0] + 8004086: 2210 movs r2, #16 + 8004088: 605a str r2, [r3, #4] #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->SleepCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_SleepCallback(hcan); - 8003fee: 6878 ldr r0, [r7, #4] - 8003ff0: f000 f8fc bl 80041ec + 800408a: 6878 ldr r0, [r7, #4] + 800408c: f000 f8fc bl 8004288 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* WakeUp interrupt management *********************************************/ if ((interrupts & CAN_IT_WAKEUP) != 0U) - 8003ff4: 6a3b ldr r3, [r7, #32] - 8003ff6: f403 3380 and.w r3, r3, #65536 @ 0x10000 - 8003ffa: 2b00 cmp r3, #0 - 8003ffc: d00b beq.n 8004016 + 8004090: 6a3b ldr r3, [r7, #32] + 8004092: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 8004096: 2b00 cmp r3, #0 + 8004098: d00b beq.n 80040b2 { if ((msrflags & CAN_MSR_WKUI) != 0U) - 8003ffe: 69fb ldr r3, [r7, #28] - 8004000: f003 0308 and.w r3, r3, #8 - 8004004: 2b00 cmp r3, #0 - 8004006: d006 beq.n 8004016 + 800409a: 69fb ldr r3, [r7, #28] + 800409c: f003 0308 and.w r3, r3, #8 + 80040a0: 2b00 cmp r3, #0 + 80040a2: d006 beq.n 80040b2 { /* Clear WakeUp Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_WKU); - 8004008: 687b ldr r3, [r7, #4] - 800400a: 681b ldr r3, [r3, #0] - 800400c: 2208 movs r2, #8 - 800400e: 605a str r2, [r3, #4] + 80040a4: 687b ldr r3, [r7, #4] + 80040a6: 681b ldr r3, [r3, #0] + 80040a8: 2208 movs r2, #8 + 80040aa: 605a str r2, [r3, #4] #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->WakeUpFromRxMsgCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_WakeUpFromRxMsgCallback(hcan); - 8004010: 6878 ldr r0, [r7, #4] - 8004012: f000 f8f5 bl 8004200 + 80040ac: 6878 ldr r0, [r7, #4] + 80040ae: f000 f8f5 bl 800429c #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Error interrupts management *********************************************/ if ((interrupts & CAN_IT_ERROR) != 0U) - 8004016: 6a3b ldr r3, [r7, #32] - 8004018: f403 4300 and.w r3, r3, #32768 @ 0x8000 - 800401c: 2b00 cmp r3, #0 - 800401e: d07b beq.n 8004118 + 80040b2: 6a3b ldr r3, [r7, #32] + 80040b4: f403 4300 and.w r3, r3, #32768 @ 0x8000 + 80040b8: 2b00 cmp r3, #0 + 80040ba: d07b beq.n 80041b4 { if ((msrflags & CAN_MSR_ERRI) != 0U) - 8004020: 69fb ldr r3, [r7, #28] - 8004022: f003 0304 and.w r3, r3, #4 - 8004026: 2b00 cmp r3, #0 - 8004028: d072 beq.n 8004110 + 80040bc: 69fb ldr r3, [r7, #28] + 80040be: f003 0304 and.w r3, r3, #4 + 80040c2: 2b00 cmp r3, #0 + 80040c4: d072 beq.n 80041ac { /* Check Error Warning Flag */ if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) && - 800402a: 6a3b ldr r3, [r7, #32] - 800402c: f403 7380 and.w r3, r3, #256 @ 0x100 - 8004030: 2b00 cmp r3, #0 - 8004032: d008 beq.n 8004046 + 80040c6: 6a3b ldr r3, [r7, #32] + 80040c8: f403 7380 and.w r3, r3, #256 @ 0x100 + 80040cc: 2b00 cmp r3, #0 + 80040ce: d008 beq.n 80040e2 ((esrflags & CAN_ESR_EWGF) != 0U)) - 8004034: 68fb ldr r3, [r7, #12] - 8004036: f003 0301 and.w r3, r3, #1 + 80040d0: 68fb ldr r3, [r7, #12] + 80040d2: f003 0301 and.w r3, r3, #1 if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) && - 800403a: 2b00 cmp r3, #0 - 800403c: d003 beq.n 8004046 + 80040d6: 2b00 cmp r3, #0 + 80040d8: d003 beq.n 80040e2 { /* Set CAN error code to Error Warning */ errorcode |= HAL_CAN_ERROR_EWG; - 800403e: 6a7b ldr r3, [r7, #36] @ 0x24 - 8004040: f043 0301 orr.w r3, r3, #1 - 8004044: 627b str r3, [r7, #36] @ 0x24 + 80040da: 6a7b ldr r3, [r7, #36] @ 0x24 + 80040dc: f043 0301 orr.w r3, r3, #1 + 80040e0: 627b str r3, [r7, #36] @ 0x24 /* No need for clear of Error Warning Flag as read-only */ } /* Check Error Passive Flag */ if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) && - 8004046: 6a3b ldr r3, [r7, #32] - 8004048: f403 7300 and.w r3, r3, #512 @ 0x200 - 800404c: 2b00 cmp r3, #0 - 800404e: d008 beq.n 8004062 + 80040e2: 6a3b ldr r3, [r7, #32] + 80040e4: f403 7300 and.w r3, r3, #512 @ 0x200 + 80040e8: 2b00 cmp r3, #0 + 80040ea: d008 beq.n 80040fe ((esrflags & CAN_ESR_EPVF) != 0U)) - 8004050: 68fb ldr r3, [r7, #12] - 8004052: f003 0302 and.w r3, r3, #2 + 80040ec: 68fb ldr r3, [r7, #12] + 80040ee: f003 0302 and.w r3, r3, #2 if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) && - 8004056: 2b00 cmp r3, #0 - 8004058: d003 beq.n 8004062 + 80040f2: 2b00 cmp r3, #0 + 80040f4: d003 beq.n 80040fe { /* Set CAN error code to Error Passive */ errorcode |= HAL_CAN_ERROR_EPV; - 800405a: 6a7b ldr r3, [r7, #36] @ 0x24 - 800405c: f043 0302 orr.w r3, r3, #2 - 8004060: 627b str r3, [r7, #36] @ 0x24 + 80040f6: 6a7b ldr r3, [r7, #36] @ 0x24 + 80040f8: f043 0302 orr.w r3, r3, #2 + 80040fc: 627b str r3, [r7, #36] @ 0x24 /* No need for clear of Error Passive Flag as read-only */ } /* Check Bus-off Flag */ if (((interrupts & CAN_IT_BUSOFF) != 0U) && - 8004062: 6a3b ldr r3, [r7, #32] - 8004064: f403 6380 and.w r3, r3, #1024 @ 0x400 - 8004068: 2b00 cmp r3, #0 - 800406a: d008 beq.n 800407e + 80040fe: 6a3b ldr r3, [r7, #32] + 8004100: f403 6380 and.w r3, r3, #1024 @ 0x400 + 8004104: 2b00 cmp r3, #0 + 8004106: d008 beq.n 800411a ((esrflags & CAN_ESR_BOFF) != 0U)) - 800406c: 68fb ldr r3, [r7, #12] - 800406e: f003 0304 and.w r3, r3, #4 + 8004108: 68fb ldr r3, [r7, #12] + 800410a: f003 0304 and.w r3, r3, #4 if (((interrupts & CAN_IT_BUSOFF) != 0U) && - 8004072: 2b00 cmp r3, #0 - 8004074: d003 beq.n 800407e + 800410e: 2b00 cmp r3, #0 + 8004110: d003 beq.n 800411a { /* Set CAN error code to Bus-Off */ errorcode |= HAL_CAN_ERROR_BOF; - 8004076: 6a7b ldr r3, [r7, #36] @ 0x24 - 8004078: f043 0304 orr.w r3, r3, #4 - 800407c: 627b str r3, [r7, #36] @ 0x24 + 8004112: 6a7b ldr r3, [r7, #36] @ 0x24 + 8004114: f043 0304 orr.w r3, r3, #4 + 8004118: 627b str r3, [r7, #36] @ 0x24 /* No need for clear of Error Bus-Off as read-only */ } /* Check Last Error Code Flag */ if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) && - 800407e: 6a3b ldr r3, [r7, #32] - 8004080: f403 6300 and.w r3, r3, #2048 @ 0x800 - 8004084: 2b00 cmp r3, #0 - 8004086: d043 beq.n 8004110 + 800411a: 6a3b ldr r3, [r7, #32] + 800411c: f403 6300 and.w r3, r3, #2048 @ 0x800 + 8004120: 2b00 cmp r3, #0 + 8004122: d043 beq.n 80041ac ((esrflags & CAN_ESR_LEC) != 0U)) - 8004088: 68fb ldr r3, [r7, #12] - 800408a: f003 0370 and.w r3, r3, #112 @ 0x70 + 8004124: 68fb ldr r3, [r7, #12] + 8004126: f003 0370 and.w r3, r3, #112 @ 0x70 if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) && - 800408e: 2b00 cmp r3, #0 - 8004090: d03e beq.n 8004110 + 800412a: 2b00 cmp r3, #0 + 800412c: d03e beq.n 80041ac { switch (esrflags & CAN_ESR_LEC) - 8004092: 68fb ldr r3, [r7, #12] - 8004094: f003 0370 and.w r3, r3, #112 @ 0x70 - 8004098: 2b60 cmp r3, #96 @ 0x60 - 800409a: d02b beq.n 80040f4 - 800409c: 2b60 cmp r3, #96 @ 0x60 - 800409e: d82e bhi.n 80040fe - 80040a0: 2b50 cmp r3, #80 @ 0x50 - 80040a2: d022 beq.n 80040ea - 80040a4: 2b50 cmp r3, #80 @ 0x50 - 80040a6: d82a bhi.n 80040fe - 80040a8: 2b40 cmp r3, #64 @ 0x40 - 80040aa: d019 beq.n 80040e0 - 80040ac: 2b40 cmp r3, #64 @ 0x40 - 80040ae: d826 bhi.n 80040fe - 80040b0: 2b30 cmp r3, #48 @ 0x30 - 80040b2: d010 beq.n 80040d6 - 80040b4: 2b30 cmp r3, #48 @ 0x30 - 80040b6: d822 bhi.n 80040fe - 80040b8: 2b10 cmp r3, #16 - 80040ba: d002 beq.n 80040c2 - 80040bc: 2b20 cmp r3, #32 - 80040be: d005 beq.n 80040cc + 800412e: 68fb ldr r3, [r7, #12] + 8004130: f003 0370 and.w r3, r3, #112 @ 0x70 + 8004134: 2b60 cmp r3, #96 @ 0x60 + 8004136: d02b beq.n 8004190 + 8004138: 2b60 cmp r3, #96 @ 0x60 + 800413a: d82e bhi.n 800419a + 800413c: 2b50 cmp r3, #80 @ 0x50 + 800413e: d022 beq.n 8004186 + 8004140: 2b50 cmp r3, #80 @ 0x50 + 8004142: d82a bhi.n 800419a + 8004144: 2b40 cmp r3, #64 @ 0x40 + 8004146: d019 beq.n 800417c + 8004148: 2b40 cmp r3, #64 @ 0x40 + 800414a: d826 bhi.n 800419a + 800414c: 2b30 cmp r3, #48 @ 0x30 + 800414e: d010 beq.n 8004172 + 8004150: 2b30 cmp r3, #48 @ 0x30 + 8004152: d822 bhi.n 800419a + 8004154: 2b10 cmp r3, #16 + 8004156: d002 beq.n 800415e + 8004158: 2b20 cmp r3, #32 + 800415a: d005 beq.n 8004168 case (CAN_ESR_LEC_2 | CAN_ESR_LEC_1): /* Set CAN error code to CRC error */ errorcode |= HAL_CAN_ERROR_CRC; break; default: break; - 80040c0: e01d b.n 80040fe + 800415c: e01d b.n 800419a errorcode |= HAL_CAN_ERROR_STF; - 80040c2: 6a7b ldr r3, [r7, #36] @ 0x24 - 80040c4: f043 0308 orr.w r3, r3, #8 - 80040c8: 627b str r3, [r7, #36] @ 0x24 + 800415e: 6a7b ldr r3, [r7, #36] @ 0x24 + 8004160: f043 0308 orr.w r3, r3, #8 + 8004164: 627b str r3, [r7, #36] @ 0x24 break; - 80040ca: e019 b.n 8004100 + 8004166: e019 b.n 800419c errorcode |= HAL_CAN_ERROR_FOR; - 80040cc: 6a7b ldr r3, [r7, #36] @ 0x24 - 80040ce: f043 0310 orr.w r3, r3, #16 - 80040d2: 627b str r3, [r7, #36] @ 0x24 + 8004168: 6a7b ldr r3, [r7, #36] @ 0x24 + 800416a: f043 0310 orr.w r3, r3, #16 + 800416e: 627b str r3, [r7, #36] @ 0x24 break; - 80040d4: e014 b.n 8004100 + 8004170: e014 b.n 800419c errorcode |= HAL_CAN_ERROR_ACK; - 80040d6: 6a7b ldr r3, [r7, #36] @ 0x24 - 80040d8: f043 0320 orr.w r3, r3, #32 - 80040dc: 627b str r3, [r7, #36] @ 0x24 + 8004172: 6a7b ldr r3, [r7, #36] @ 0x24 + 8004174: f043 0320 orr.w r3, r3, #32 + 8004178: 627b str r3, [r7, #36] @ 0x24 break; - 80040de: e00f b.n 8004100 + 800417a: e00f b.n 800419c errorcode |= HAL_CAN_ERROR_BR; - 80040e0: 6a7b ldr r3, [r7, #36] @ 0x24 - 80040e2: f043 0340 orr.w r3, r3, #64 @ 0x40 - 80040e6: 627b str r3, [r7, #36] @ 0x24 + 800417c: 6a7b ldr r3, [r7, #36] @ 0x24 + 800417e: f043 0340 orr.w r3, r3, #64 @ 0x40 + 8004182: 627b str r3, [r7, #36] @ 0x24 break; - 80040e8: e00a b.n 8004100 + 8004184: e00a b.n 800419c errorcode |= HAL_CAN_ERROR_BD; - 80040ea: 6a7b ldr r3, [r7, #36] @ 0x24 - 80040ec: f043 0380 orr.w r3, r3, #128 @ 0x80 - 80040f0: 627b str r3, [r7, #36] @ 0x24 + 8004186: 6a7b ldr r3, [r7, #36] @ 0x24 + 8004188: f043 0380 orr.w r3, r3, #128 @ 0x80 + 800418c: 627b str r3, [r7, #36] @ 0x24 break; - 80040f2: e005 b.n 8004100 + 800418e: e005 b.n 800419c errorcode |= HAL_CAN_ERROR_CRC; - 80040f4: 6a7b ldr r3, [r7, #36] @ 0x24 - 80040f6: f443 7380 orr.w r3, r3, #256 @ 0x100 - 80040fa: 627b str r3, [r7, #36] @ 0x24 + 8004190: 6a7b ldr r3, [r7, #36] @ 0x24 + 8004192: f443 7380 orr.w r3, r3, #256 @ 0x100 + 8004196: 627b str r3, [r7, #36] @ 0x24 break; - 80040fc: e000 b.n 8004100 + 8004198: e000 b.n 800419c break; - 80040fe: bf00 nop + 800419a: bf00 nop } /* Clear Last error code Flag */ CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC); - 8004100: 687b ldr r3, [r7, #4] - 8004102: 681b ldr r3, [r3, #0] - 8004104: 699a ldr r2, [r3, #24] - 8004106: 687b ldr r3, [r7, #4] - 8004108: 681b ldr r3, [r3, #0] - 800410a: f022 0270 bic.w r2, r2, #112 @ 0x70 - 800410e: 619a str r2, [r3, #24] + 800419c: 687b ldr r3, [r7, #4] + 800419e: 681b ldr r3, [r3, #0] + 80041a0: 699a ldr r2, [r3, #24] + 80041a2: 687b ldr r3, [r7, #4] + 80041a4: 681b ldr r3, [r3, #0] + 80041a6: f022 0270 bic.w r2, r2, #112 @ 0x70 + 80041aa: 619a str r2, [r3, #24] } } /* Clear ERRI Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_ERRI); - 8004110: 687b ldr r3, [r7, #4] - 8004112: 681b ldr r3, [r3, #0] - 8004114: 2204 movs r2, #4 - 8004116: 605a str r2, [r3, #4] + 80041ac: 687b ldr r3, [r7, #4] + 80041ae: 681b ldr r3, [r3, #0] + 80041b0: 2204 movs r2, #4 + 80041b2: 605a str r2, [r3, #4] } /* Call the Error call Back in case of Errors */ if (errorcode != HAL_CAN_ERROR_NONE) - 8004118: 6a7b ldr r3, [r7, #36] @ 0x24 - 800411a: 2b00 cmp r3, #0 - 800411c: d008 beq.n 8004130 + 80041b4: 6a7b ldr r3, [r7, #36] @ 0x24 + 80041b6: 2b00 cmp r3, #0 + 80041b8: d008 beq.n 80041cc { /* Update error code in handle */ hcan->ErrorCode |= errorcode; - 800411e: 687b ldr r3, [r7, #4] - 8004120: 6a5a ldr r2, [r3, #36] @ 0x24 - 8004122: 6a7b ldr r3, [r7, #36] @ 0x24 - 8004124: 431a orrs r2, r3 - 8004126: 687b ldr r3, [r7, #4] - 8004128: 625a str r2, [r3, #36] @ 0x24 + 80041ba: 687b ldr r3, [r7, #4] + 80041bc: 6a5a ldr r2, [r3, #36] @ 0x24 + 80041be: 6a7b ldr r3, [r7, #36] @ 0x24 + 80041c0: 431a orrs r2, r3 + 80041c2: 687b ldr r3, [r7, #4] + 80041c4: 625a str r2, [r3, #36] @ 0x24 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->ErrorCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_ErrorCallback(hcan); - 800412a: 6878 ldr r0, [r7, #4] - 800412c: f000 f872 bl 8004214 + 80041c6: 6878 ldr r0, [r7, #4] + 80041c8: f000 f872 bl 80042b0 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } - 8004130: bf00 nop - 8004132: 3728 adds r7, #40 @ 0x28 - 8004134: 46bd mov sp, r7 - 8004136: bd80 pop {r7, pc} + 80041cc: bf00 nop + 80041ce: 3728 adds r7, #40 @ 0x28 + 80041d0: 46bd mov sp, r7 + 80041d2: bd80 pop {r7, pc} -08004138 : +080041d4 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan) { - 8004138: b480 push {r7} - 800413a: b083 sub sp, #12 - 800413c: af00 add r7, sp, #0 - 800413e: 6078 str r0, [r7, #4] + 80041d4: b480 push {r7} + 80041d6: b083 sub sp, #12 + 80041d8: af00 add r7, sp, #0 + 80041da: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox0CompleteCallback could be implemented in the user file */ } - 8004140: bf00 nop - 8004142: 370c adds r7, #12 - 8004144: 46bd mov sp, r7 - 8004146: f85d 7b04 ldr.w r7, [sp], #4 - 800414a: 4770 bx lr + 80041dc: bf00 nop + 80041de: 370c adds r7, #12 + 80041e0: 46bd mov sp, r7 + 80041e2: f85d 7b04 ldr.w r7, [sp], #4 + 80041e6: 4770 bx lr -0800414c : +080041e8 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan) { - 800414c: b480 push {r7} - 800414e: b083 sub sp, #12 - 8004150: af00 add r7, sp, #0 - 8004152: 6078 str r0, [r7, #4] + 80041e8: b480 push {r7} + 80041ea: b083 sub sp, #12 + 80041ec: af00 add r7, sp, #0 + 80041ee: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox1CompleteCallback could be implemented in the user file */ } - 8004154: bf00 nop - 8004156: 370c adds r7, #12 - 8004158: 46bd mov sp, r7 - 800415a: f85d 7b04 ldr.w r7, [sp], #4 - 800415e: 4770 bx lr + 80041f0: bf00 nop + 80041f2: 370c adds r7, #12 + 80041f4: 46bd mov sp, r7 + 80041f6: f85d 7b04 ldr.w r7, [sp], #4 + 80041fa: 4770 bx lr -08004160 : +080041fc : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan) { - 8004160: b480 push {r7} - 8004162: b083 sub sp, #12 - 8004164: af00 add r7, sp, #0 - 8004166: 6078 str r0, [r7, #4] + 80041fc: b480 push {r7} + 80041fe: b083 sub sp, #12 + 8004200: af00 add r7, sp, #0 + 8004202: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox2CompleteCallback could be implemented in the user file */ } - 8004168: bf00 nop - 800416a: 370c adds r7, #12 - 800416c: 46bd mov sp, r7 - 800416e: f85d 7b04 ldr.w r7, [sp], #4 - 8004172: 4770 bx lr + 8004204: bf00 nop + 8004206: 370c adds r7, #12 + 8004208: 46bd mov sp, r7 + 800420a: f85d 7b04 ldr.w r7, [sp], #4 + 800420e: 4770 bx lr -08004174 : +08004210 : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan) { - 8004174: b480 push {r7} - 8004176: b083 sub sp, #12 - 8004178: af00 add r7, sp, #0 - 800417a: 6078 str r0, [r7, #4] + 8004210: b480 push {r7} + 8004212: b083 sub sp, #12 + 8004214: af00 add r7, sp, #0 + 8004216: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox0AbortCallback could be implemented in the user file */ } - 800417c: bf00 nop - 800417e: 370c adds r7, #12 - 8004180: 46bd mov sp, r7 - 8004182: f85d 7b04 ldr.w r7, [sp], #4 - 8004186: 4770 bx lr + 8004218: bf00 nop + 800421a: 370c adds r7, #12 + 800421c: 46bd mov sp, r7 + 800421e: f85d 7b04 ldr.w r7, [sp], #4 + 8004222: 4770 bx lr -08004188 : +08004224 : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan) { - 8004188: b480 push {r7} - 800418a: b083 sub sp, #12 - 800418c: af00 add r7, sp, #0 - 800418e: 6078 str r0, [r7, #4] + 8004224: b480 push {r7} + 8004226: b083 sub sp, #12 + 8004228: af00 add r7, sp, #0 + 800422a: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox1AbortCallback could be implemented in the user file */ } - 8004190: bf00 nop - 8004192: 370c adds r7, #12 - 8004194: 46bd mov sp, r7 - 8004196: f85d 7b04 ldr.w r7, [sp], #4 - 800419a: 4770 bx lr + 800422c: bf00 nop + 800422e: 370c adds r7, #12 + 8004230: 46bd mov sp, r7 + 8004232: f85d 7b04 ldr.w r7, [sp], #4 + 8004236: 4770 bx lr -0800419c : +08004238 : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan) { - 800419c: b480 push {r7} - 800419e: b083 sub sp, #12 - 80041a0: af00 add r7, sp, #0 - 80041a2: 6078 str r0, [r7, #4] + 8004238: b480 push {r7} + 800423a: b083 sub sp, #12 + 800423c: af00 add r7, sp, #0 + 800423e: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox2AbortCallback could be implemented in the user file */ } - 80041a4: bf00 nop - 80041a6: 370c adds r7, #12 - 80041a8: 46bd mov sp, r7 - 80041aa: f85d 7b04 ldr.w r7, [sp], #4 - 80041ae: 4770 bx lr + 8004240: bf00 nop + 8004242: 370c adds r7, #12 + 8004244: 46bd mov sp, r7 + 8004246: f85d 7b04 ldr.w r7, [sp], #4 + 800424a: 4770 bx lr -080041b0 : +0800424c : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan) { - 80041b0: b480 push {r7} - 80041b2: b083 sub sp, #12 - 80041b4: af00 add r7, sp, #0 - 80041b6: 6078 str r0, [r7, #4] + 800424c: b480 push {r7} + 800424e: b083 sub sp, #12 + 8004250: af00 add r7, sp, #0 + 8004252: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_RxFifo0FullCallback could be implemented in the user file */ } - 80041b8: bf00 nop - 80041ba: 370c adds r7, #12 - 80041bc: 46bd mov sp, r7 - 80041be: f85d 7b04 ldr.w r7, [sp], #4 - 80041c2: 4770 bx lr + 8004254: bf00 nop + 8004256: 370c adds r7, #12 + 8004258: 46bd mov sp, r7 + 800425a: f85d 7b04 ldr.w r7, [sp], #4 + 800425e: 4770 bx lr -080041c4 : +08004260 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan) { - 80041c4: b480 push {r7} - 80041c6: b083 sub sp, #12 - 80041c8: af00 add r7, sp, #0 - 80041ca: 6078 str r0, [r7, #4] + 8004260: b480 push {r7} + 8004262: b083 sub sp, #12 + 8004264: af00 add r7, sp, #0 + 8004266: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_RxFifo1MsgPendingCallback could be implemented in the user file */ } - 80041cc: bf00 nop - 80041ce: 370c adds r7, #12 - 80041d0: 46bd mov sp, r7 - 80041d2: f85d 7b04 ldr.w r7, [sp], #4 - 80041d6: 4770 bx lr + 8004268: bf00 nop + 800426a: 370c adds r7, #12 + 800426c: 46bd mov sp, r7 + 800426e: f85d 7b04 ldr.w r7, [sp], #4 + 8004272: 4770 bx lr -080041d8 : +08004274 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan) { - 80041d8: b480 push {r7} - 80041da: b083 sub sp, #12 - 80041dc: af00 add r7, sp, #0 - 80041de: 6078 str r0, [r7, #4] + 8004274: b480 push {r7} + 8004276: b083 sub sp, #12 + 8004278: af00 add r7, sp, #0 + 800427a: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_RxFifo1FullCallback could be implemented in the user file */ } - 80041e0: bf00 nop - 80041e2: 370c adds r7, #12 - 80041e4: 46bd mov sp, r7 - 80041e6: f85d 7b04 ldr.w r7, [sp], #4 - 80041ea: 4770 bx lr + 800427c: bf00 nop + 800427e: 370c adds r7, #12 + 8004280: 46bd mov sp, r7 + 8004282: f85d 7b04 ldr.w r7, [sp], #4 + 8004286: 4770 bx lr -080041ec : +08004288 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan) { - 80041ec: b480 push {r7} - 80041ee: b083 sub sp, #12 - 80041f0: af00 add r7, sp, #0 - 80041f2: 6078 str r0, [r7, #4] + 8004288: b480 push {r7} + 800428a: b083 sub sp, #12 + 800428c: af00 add r7, sp, #0 + 800428e: 6078 str r0, [r7, #4] UNUSED(hcan); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_SleepCallback could be implemented in the user file */ } - 80041f4: bf00 nop - 80041f6: 370c adds r7, #12 - 80041f8: 46bd mov sp, r7 - 80041fa: f85d 7b04 ldr.w r7, [sp], #4 - 80041fe: 4770 bx lr + 8004290: bf00 nop + 8004292: 370c adds r7, #12 + 8004294: 46bd mov sp, r7 + 8004296: f85d 7b04 ldr.w r7, [sp], #4 + 800429a: 4770 bx lr -08004200 : +0800429c : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan) { - 8004200: b480 push {r7} - 8004202: b083 sub sp, #12 - 8004204: af00 add r7, sp, #0 - 8004206: 6078 str r0, [r7, #4] + 800429c: b480 push {r7} + 800429e: b083 sub sp, #12 + 80042a0: af00 add r7, sp, #0 + 80042a2: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_WakeUpFromRxMsgCallback could be implemented in the user file */ } - 8004208: bf00 nop - 800420a: 370c adds r7, #12 - 800420c: 46bd mov sp, r7 - 800420e: f85d 7b04 ldr.w r7, [sp], #4 - 8004212: 4770 bx lr + 80042a4: bf00 nop + 80042a6: 370c adds r7, #12 + 80042a8: 46bd mov sp, r7 + 80042aa: f85d 7b04 ldr.w r7, [sp], #4 + 80042ae: 4770 bx lr -08004214 : +080042b0 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) { - 8004214: b480 push {r7} - 8004216: b083 sub sp, #12 - 8004218: af00 add r7, sp, #0 - 800421a: 6078 str r0, [r7, #4] + 80042b0: b480 push {r7} + 80042b2: b083 sub sp, #12 + 80042b4: af00 add r7, sp, #0 + 80042b6: 6078 str r0, [r7, #4] UNUSED(hcan); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_ErrorCallback could be implemented in the user file */ } - 800421c: bf00 nop - 800421e: 370c adds r7, #12 - 8004220: 46bd mov sp, r7 - 8004222: f85d 7b04 ldr.w r7, [sp], #4 - 8004226: 4770 bx lr + 80042b8: bf00 nop + 80042ba: 370c adds r7, #12 + 80042bc: 46bd mov sp, r7 + 80042be: f85d 7b04 ldr.w r7, [sp], #4 + 80042c2: 4770 bx lr -08004228 <__NVIC_SetPriorityGrouping>: +080042c4 <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { - 8004228: b480 push {r7} - 800422a: b085 sub sp, #20 - 800422c: af00 add r7, sp, #0 - 800422e: 6078 str r0, [r7, #4] + 80042c4: b480 push {r7} + 80042c6: b085 sub sp, #20 + 80042c8: af00 add r7, sp, #0 + 80042ca: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - 8004230: 687b ldr r3, [r7, #4] - 8004232: f003 0307 and.w r3, r3, #7 - 8004236: 60fb str r3, [r7, #12] + 80042cc: 687b ldr r3, [r7, #4] + 80042ce: f003 0307 and.w r3, r3, #7 + 80042d2: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ - 8004238: 4b0c ldr r3, [pc, #48] @ (800426c <__NVIC_SetPriorityGrouping+0x44>) - 800423a: 68db ldr r3, [r3, #12] - 800423c: 60bb str r3, [r7, #8] + 80042d4: 4b0c ldr r3, [pc, #48] @ (8004308 <__NVIC_SetPriorityGrouping+0x44>) + 80042d6: 68db ldr r3, [r3, #12] + 80042d8: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - 800423e: 68ba ldr r2, [r7, #8] - 8004240: f64f 03ff movw r3, #63743 @ 0xf8ff - 8004244: 4013 ands r3, r2 - 8004246: 60bb str r3, [r7, #8] + 80042da: 68ba ldr r2, [r7, #8] + 80042dc: f64f 03ff movw r3, #63743 @ 0xf8ff + 80042e0: 4013 ands r3, r2 + 80042e2: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - 8004248: 68fb ldr r3, [r7, #12] - 800424a: 021a lsls r2, r3, #8 + 80042e4: 68fb ldr r3, [r7, #12] + 80042e6: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - 800424c: 68bb ldr r3, [r7, #8] - 800424e: 4313 orrs r3, r2 + 80042e8: 68bb ldr r3, [r7, #8] + 80042ea: 4313 orrs r3, r2 reg_value = (reg_value | - 8004250: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 - 8004254: f443 3300 orr.w r3, r3, #131072 @ 0x20000 - 8004258: 60bb str r3, [r7, #8] + 80042ec: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 + 80042f0: f443 3300 orr.w r3, r3, #131072 @ 0x20000 + 80042f4: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; - 800425a: 4a04 ldr r2, [pc, #16] @ (800426c <__NVIC_SetPriorityGrouping+0x44>) - 800425c: 68bb ldr r3, [r7, #8] - 800425e: 60d3 str r3, [r2, #12] + 80042f6: 4a04 ldr r2, [pc, #16] @ (8004308 <__NVIC_SetPriorityGrouping+0x44>) + 80042f8: 68bb ldr r3, [r7, #8] + 80042fa: 60d3 str r3, [r2, #12] } - 8004260: bf00 nop - 8004262: 3714 adds r7, #20 - 8004264: 46bd mov sp, r7 - 8004266: f85d 7b04 ldr.w r7, [sp], #4 - 800426a: 4770 bx lr - 800426c: e000ed00 .word 0xe000ed00 + 80042fc: bf00 nop + 80042fe: 3714 adds r7, #20 + 8004300: 46bd mov sp, r7 + 8004302: f85d 7b04 ldr.w r7, [sp], #4 + 8004306: 4770 bx lr + 8004308: e000ed00 .word 0xe000ed00 -08004270 <__NVIC_GetPriorityGrouping>: +0800430c <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { - 8004270: b480 push {r7} - 8004272: af00 add r7, sp, #0 + 800430c: b480 push {r7} + 800430e: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); - 8004274: 4b04 ldr r3, [pc, #16] @ (8004288 <__NVIC_GetPriorityGrouping+0x18>) - 8004276: 68db ldr r3, [r3, #12] - 8004278: 0a1b lsrs r3, r3, #8 - 800427a: f003 0307 and.w r3, r3, #7 + 8004310: 4b04 ldr r3, [pc, #16] @ (8004324 <__NVIC_GetPriorityGrouping+0x18>) + 8004312: 68db ldr r3, [r3, #12] + 8004314: 0a1b lsrs r3, r3, #8 + 8004316: f003 0307 and.w r3, r3, #7 } - 800427e: 4618 mov r0, r3 - 8004280: 46bd mov sp, r7 - 8004282: f85d 7b04 ldr.w r7, [sp], #4 - 8004286: 4770 bx lr - 8004288: e000ed00 .word 0xe000ed00 + 800431a: 4618 mov r0, r3 + 800431c: 46bd mov sp, r7 + 800431e: f85d 7b04 ldr.w r7, [sp], #4 + 8004322: 4770 bx lr + 8004324: e000ed00 .word 0xe000ed00 -0800428c <__NVIC_EnableIRQ>: +08004328 <__NVIC_EnableIRQ>: \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { - 800428c: b480 push {r7} - 800428e: b083 sub sp, #12 - 8004290: af00 add r7, sp, #0 - 8004292: 4603 mov r3, r0 - 8004294: 71fb strb r3, [r7, #7] + 8004328: b480 push {r7} + 800432a: b083 sub sp, #12 + 800432c: af00 add r7, sp, #0 + 800432e: 4603 mov r3, r0 + 8004330: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) - 8004296: f997 3007 ldrsb.w r3, [r7, #7] - 800429a: 2b00 cmp r3, #0 - 800429c: db0b blt.n 80042b6 <__NVIC_EnableIRQ+0x2a> + 8004332: f997 3007 ldrsb.w r3, [r7, #7] + 8004336: 2b00 cmp r3, #0 + 8004338: db0b blt.n 8004352 <__NVIC_EnableIRQ+0x2a> { NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - 800429e: 79fb ldrb r3, [r7, #7] - 80042a0: f003 021f and.w r2, r3, #31 - 80042a4: 4907 ldr r1, [pc, #28] @ (80042c4 <__NVIC_EnableIRQ+0x38>) - 80042a6: f997 3007 ldrsb.w r3, [r7, #7] - 80042aa: 095b lsrs r3, r3, #5 - 80042ac: 2001 movs r0, #1 - 80042ae: fa00 f202 lsl.w r2, r0, r2 - 80042b2: f841 2023 str.w r2, [r1, r3, lsl #2] + 800433a: 79fb ldrb r3, [r7, #7] + 800433c: f003 021f and.w r2, r3, #31 + 8004340: 4907 ldr r1, [pc, #28] @ (8004360 <__NVIC_EnableIRQ+0x38>) + 8004342: f997 3007 ldrsb.w r3, [r7, #7] + 8004346: 095b lsrs r3, r3, #5 + 8004348: 2001 movs r0, #1 + 800434a: fa00 f202 lsl.w r2, r0, r2 + 800434e: f841 2023 str.w r2, [r1, r3, lsl #2] } } - 80042b6: bf00 nop - 80042b8: 370c adds r7, #12 - 80042ba: 46bd mov sp, r7 - 80042bc: f85d 7b04 ldr.w r7, [sp], #4 - 80042c0: 4770 bx lr - 80042c2: bf00 nop - 80042c4: e000e100 .word 0xe000e100 + 8004352: bf00 nop + 8004354: 370c adds r7, #12 + 8004356: 46bd mov sp, r7 + 8004358: f85d 7b04 ldr.w r7, [sp], #4 + 800435c: 4770 bx lr + 800435e: bf00 nop + 8004360: e000e100 .word 0xe000e100 -080042c8 <__NVIC_SetPriority>: +08004364 <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { - 80042c8: b480 push {r7} - 80042ca: b083 sub sp, #12 - 80042cc: af00 add r7, sp, #0 - 80042ce: 4603 mov r3, r0 - 80042d0: 6039 str r1, [r7, #0] - 80042d2: 71fb strb r3, [r7, #7] + 8004364: b480 push {r7} + 8004366: b083 sub sp, #12 + 8004368: af00 add r7, sp, #0 + 800436a: 4603 mov r3, r0 + 800436c: 6039 str r1, [r7, #0] + 800436e: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) - 80042d4: f997 3007 ldrsb.w r3, [r7, #7] - 80042d8: 2b00 cmp r3, #0 - 80042da: db0a blt.n 80042f2 <__NVIC_SetPriority+0x2a> + 8004370: f997 3007 ldrsb.w r3, [r7, #7] + 8004374: 2b00 cmp r3, #0 + 8004376: db0a blt.n 800438e <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - 80042dc: 683b ldr r3, [r7, #0] - 80042de: b2da uxtb r2, r3 - 80042e0: 490c ldr r1, [pc, #48] @ (8004314 <__NVIC_SetPriority+0x4c>) - 80042e2: f997 3007 ldrsb.w r3, [r7, #7] - 80042e6: 0112 lsls r2, r2, #4 - 80042e8: b2d2 uxtb r2, r2 - 80042ea: 440b add r3, r1 - 80042ec: f883 2300 strb.w r2, [r3, #768] @ 0x300 + 8004378: 683b ldr r3, [r7, #0] + 800437a: b2da uxtb r2, r3 + 800437c: 490c ldr r1, [pc, #48] @ (80043b0 <__NVIC_SetPriority+0x4c>) + 800437e: f997 3007 ldrsb.w r3, [r7, #7] + 8004382: 0112 lsls r2, r2, #4 + 8004384: b2d2 uxtb r2, r2 + 8004386: 440b add r3, r1 + 8004388: f883 2300 strb.w r2, [r3, #768] @ 0x300 } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } - 80042f0: e00a b.n 8004308 <__NVIC_SetPriority+0x40> + 800438c: e00a b.n 80043a4 <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - 80042f2: 683b ldr r3, [r7, #0] - 80042f4: b2da uxtb r2, r3 - 80042f6: 4908 ldr r1, [pc, #32] @ (8004318 <__NVIC_SetPriority+0x50>) - 80042f8: 79fb ldrb r3, [r7, #7] - 80042fa: f003 030f and.w r3, r3, #15 - 80042fe: 3b04 subs r3, #4 - 8004300: 0112 lsls r2, r2, #4 - 8004302: b2d2 uxtb r2, r2 - 8004304: 440b add r3, r1 - 8004306: 761a strb r2, [r3, #24] + 800438e: 683b ldr r3, [r7, #0] + 8004390: b2da uxtb r2, r3 + 8004392: 4908 ldr r1, [pc, #32] @ (80043b4 <__NVIC_SetPriority+0x50>) + 8004394: 79fb ldrb r3, [r7, #7] + 8004396: f003 030f and.w r3, r3, #15 + 800439a: 3b04 subs r3, #4 + 800439c: 0112 lsls r2, r2, #4 + 800439e: b2d2 uxtb r2, r2 + 80043a0: 440b add r3, r1 + 80043a2: 761a strb r2, [r3, #24] } - 8004308: bf00 nop - 800430a: 370c adds r7, #12 - 800430c: 46bd mov sp, r7 - 800430e: f85d 7b04 ldr.w r7, [sp], #4 - 8004312: 4770 bx lr - 8004314: e000e100 .word 0xe000e100 - 8004318: e000ed00 .word 0xe000ed00 + 80043a4: bf00 nop + 80043a6: 370c adds r7, #12 + 80043a8: 46bd mov sp, r7 + 80043aa: f85d 7b04 ldr.w r7, [sp], #4 + 80043ae: 4770 bx lr + 80043b0: e000e100 .word 0xe000e100 + 80043b4: e000ed00 .word 0xe000ed00 -0800431c : +080043b8 : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { - 800431c: b480 push {r7} - 800431e: b089 sub sp, #36 @ 0x24 - 8004320: af00 add r7, sp, #0 - 8004322: 60f8 str r0, [r7, #12] - 8004324: 60b9 str r1, [r7, #8] - 8004326: 607a str r2, [r7, #4] + 80043b8: b480 push {r7} + 80043ba: b089 sub sp, #36 @ 0x24 + 80043bc: af00 add r7, sp, #0 + 80043be: 60f8 str r0, [r7, #12] + 80043c0: 60b9 str r1, [r7, #8] + 80043c2: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - 8004328: 68fb ldr r3, [r7, #12] - 800432a: f003 0307 and.w r3, r3, #7 - 800432e: 61fb str r3, [r7, #28] + 80043c4: 68fb ldr r3, [r7, #12] + 80043c6: f003 0307 and.w r3, r3, #7 + 80043ca: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - 8004330: 69fb ldr r3, [r7, #28] - 8004332: f1c3 0307 rsb r3, r3, #7 - 8004336: 2b04 cmp r3, #4 - 8004338: bf28 it cs - 800433a: 2304 movcs r3, #4 - 800433c: 61bb str r3, [r7, #24] + 80043cc: 69fb ldr r3, [r7, #28] + 80043ce: f1c3 0307 rsb r3, r3, #7 + 80043d2: 2b04 cmp r3, #4 + 80043d4: bf28 it cs + 80043d6: 2304 movcs r3, #4 + 80043d8: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - 800433e: 69fb ldr r3, [r7, #28] - 8004340: 3304 adds r3, #4 - 8004342: 2b06 cmp r3, #6 - 8004344: d902 bls.n 800434c - 8004346: 69fb ldr r3, [r7, #28] - 8004348: 3b03 subs r3, #3 - 800434a: e000 b.n 800434e - 800434c: 2300 movs r3, #0 - 800434e: 617b str r3, [r7, #20] + 80043da: 69fb ldr r3, [r7, #28] + 80043dc: 3304 adds r3, #4 + 80043de: 2b06 cmp r3, #6 + 80043e0: d902 bls.n 80043e8 + 80043e2: 69fb ldr r3, [r7, #28] + 80043e4: 3b03 subs r3, #3 + 80043e6: e000 b.n 80043ea + 80043e8: 2300 movs r3, #0 + 80043ea: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - 8004350: f04f 32ff mov.w r2, #4294967295 - 8004354: 69bb ldr r3, [r7, #24] - 8004356: fa02 f303 lsl.w r3, r2, r3 - 800435a: 43da mvns r2, r3 - 800435c: 68bb ldr r3, [r7, #8] - 800435e: 401a ands r2, r3 - 8004360: 697b ldr r3, [r7, #20] - 8004362: 409a lsls r2, r3 + 80043ec: f04f 32ff mov.w r2, #4294967295 + 80043f0: 69bb ldr r3, [r7, #24] + 80043f2: fa02 f303 lsl.w r3, r2, r3 + 80043f6: 43da mvns r2, r3 + 80043f8: 68bb ldr r3, [r7, #8] + 80043fa: 401a ands r2, r3 + 80043fc: 697b ldr r3, [r7, #20] + 80043fe: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - 8004364: f04f 31ff mov.w r1, #4294967295 - 8004368: 697b ldr r3, [r7, #20] - 800436a: fa01 f303 lsl.w r3, r1, r3 - 800436e: 43d9 mvns r1, r3 - 8004370: 687b ldr r3, [r7, #4] - 8004372: 400b ands r3, r1 + 8004400: f04f 31ff mov.w r1, #4294967295 + 8004404: 697b ldr r3, [r7, #20] + 8004406: fa01 f303 lsl.w r3, r1, r3 + 800440a: 43d9 mvns r1, r3 + 800440c: 687b ldr r3, [r7, #4] + 800440e: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - 8004374: 4313 orrs r3, r2 + 8004410: 4313 orrs r3, r2 ); } - 8004376: 4618 mov r0, r3 - 8004378: 3724 adds r7, #36 @ 0x24 - 800437a: 46bd mov sp, r7 - 800437c: f85d 7b04 ldr.w r7, [sp], #4 - 8004380: 4770 bx lr + 8004412: 4618 mov r0, r3 + 8004414: 3724 adds r7, #36 @ 0x24 + 8004416: 46bd mov sp, r7 + 8004418: f85d 7b04 ldr.w r7, [sp], #4 + 800441c: 4770 bx lr ... -08004384 : +08004420 : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { - 8004384: b580 push {r7, lr} - 8004386: b082 sub sp, #8 - 8004388: af00 add r7, sp, #0 - 800438a: 6078 str r0, [r7, #4] + 8004420: b580 push {r7, lr} + 8004422: b082 sub sp, #8 + 8004424: af00 add r7, sp, #0 + 8004426: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - 800438c: 687b ldr r3, [r7, #4] - 800438e: 3b01 subs r3, #1 - 8004390: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 - 8004394: d301 bcc.n 800439a + 8004428: 687b ldr r3, [r7, #4] + 800442a: 3b01 subs r3, #1 + 800442c: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 + 8004430: d301 bcc.n 8004436 { return (1UL); /* Reload value impossible */ - 8004396: 2301 movs r3, #1 - 8004398: e00f b.n 80043ba + 8004432: 2301 movs r3, #1 + 8004434: e00f b.n 8004456 } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - 800439a: 4a0a ldr r2, [pc, #40] @ (80043c4 ) - 800439c: 687b ldr r3, [r7, #4] - 800439e: 3b01 subs r3, #1 - 80043a0: 6053 str r3, [r2, #4] + 8004436: 4a0a ldr r2, [pc, #40] @ (8004460 ) + 8004438: 687b ldr r3, [r7, #4] + 800443a: 3b01 subs r3, #1 + 800443c: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - 80043a2: 210f movs r1, #15 - 80043a4: f04f 30ff mov.w r0, #4294967295 - 80043a8: f7ff ff8e bl 80042c8 <__NVIC_SetPriority> + 800443e: 210f movs r1, #15 + 8004440: f04f 30ff mov.w r0, #4294967295 + 8004444: f7ff ff8e bl 8004364 <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - 80043ac: 4b05 ldr r3, [pc, #20] @ (80043c4 ) - 80043ae: 2200 movs r2, #0 - 80043b0: 609a str r2, [r3, #8] + 8004448: 4b05 ldr r3, [pc, #20] @ (8004460 ) + 800444a: 2200 movs r2, #0 + 800444c: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - 80043b2: 4b04 ldr r3, [pc, #16] @ (80043c4 ) - 80043b4: 2207 movs r2, #7 - 80043b6: 601a str r2, [r3, #0] + 800444e: 4b04 ldr r3, [pc, #16] @ (8004460 ) + 8004450: 2207 movs r2, #7 + 8004452: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ - 80043b8: 2300 movs r3, #0 + 8004454: 2300 movs r3, #0 } - 80043ba: 4618 mov r0, r3 - 80043bc: 3708 adds r7, #8 - 80043be: 46bd mov sp, r7 - 80043c0: bd80 pop {r7, pc} - 80043c2: bf00 nop - 80043c4: e000e010 .word 0xe000e010 + 8004456: 4618 mov r0, r3 + 8004458: 3708 adds r7, #8 + 800445a: 46bd mov sp, r7 + 800445c: bd80 pop {r7, pc} + 800445e: bf00 nop + 8004460: e000e010 .word 0xe000e010 -080043c8 : +08004464 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { - 80043c8: b580 push {r7, lr} - 80043ca: b082 sub sp, #8 - 80043cc: af00 add r7, sp, #0 - 80043ce: 6078 str r0, [r7, #4] + 8004464: b580 push {r7, lr} + 8004466: b082 sub sp, #8 + 8004468: af00 add r7, sp, #0 + 800446a: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); - 80043d0: 6878 ldr r0, [r7, #4] - 80043d2: f7ff ff29 bl 8004228 <__NVIC_SetPriorityGrouping> + 800446c: 6878 ldr r0, [r7, #4] + 800446e: f7ff ff29 bl 80042c4 <__NVIC_SetPriorityGrouping> } - 80043d6: bf00 nop - 80043d8: 3708 adds r7, #8 - 80043da: 46bd mov sp, r7 - 80043dc: bd80 pop {r7, pc} + 8004472: bf00 nop + 8004474: 3708 adds r7, #8 + 8004476: 46bd mov sp, r7 + 8004478: bd80 pop {r7, pc} -080043de : +0800447a : * This parameter can be a value between 0 and 15 as described in the table CORTEX_NVIC_Priority_Table * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { - 80043de: b580 push {r7, lr} - 80043e0: b086 sub sp, #24 - 80043e2: af00 add r7, sp, #0 - 80043e4: 4603 mov r3, r0 - 80043e6: 60b9 str r1, [r7, #8] - 80043e8: 607a str r2, [r7, #4] - 80043ea: 73fb strb r3, [r7, #15] + 800447a: b580 push {r7, lr} + 800447c: b086 sub sp, #24 + 800447e: af00 add r7, sp, #0 + 8004480: 4603 mov r3, r0 + 8004482: 60b9 str r1, [r7, #8] + 8004484: 607a str r2, [r7, #4] + 8004486: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00U; - 80043ec: 2300 movs r3, #0 - 80043ee: 617b str r3, [r7, #20] + 8004488: 2300 movs r3, #0 + 800448a: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); - 80043f0: f7ff ff3e bl 8004270 <__NVIC_GetPriorityGrouping> - 80043f4: 6178 str r0, [r7, #20] + 800448c: f7ff ff3e bl 800430c <__NVIC_GetPriorityGrouping> + 8004490: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); - 80043f6: 687a ldr r2, [r7, #4] - 80043f8: 68b9 ldr r1, [r7, #8] - 80043fa: 6978 ldr r0, [r7, #20] - 80043fc: f7ff ff8e bl 800431c - 8004400: 4602 mov r2, r0 - 8004402: f997 300f ldrsb.w r3, [r7, #15] - 8004406: 4611 mov r1, r2 - 8004408: 4618 mov r0, r3 - 800440a: f7ff ff5d bl 80042c8 <__NVIC_SetPriority> + 8004492: 687a ldr r2, [r7, #4] + 8004494: 68b9 ldr r1, [r7, #8] + 8004496: 6978 ldr r0, [r7, #20] + 8004498: f7ff ff8e bl 80043b8 + 800449c: 4602 mov r2, r0 + 800449e: f997 300f ldrsb.w r3, [r7, #15] + 80044a2: 4611 mov r1, r2 + 80044a4: 4618 mov r0, r3 + 80044a6: f7ff ff5d bl 8004364 <__NVIC_SetPriority> } - 800440e: bf00 nop - 8004410: 3718 adds r7, #24 - 8004412: 46bd mov sp, r7 - 8004414: bd80 pop {r7, pc} + 80044aa: bf00 nop + 80044ac: 3718 adds r7, #24 + 80044ae: 46bd mov sp, r7 + 80044b0: bd80 pop {r7, pc} -08004416 : +080044b2 : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { - 8004416: b580 push {r7, lr} - 8004418: b082 sub sp, #8 - 800441a: af00 add r7, sp, #0 - 800441c: 4603 mov r3, r0 - 800441e: 71fb strb r3, [r7, #7] + 80044b2: b580 push {r7, lr} + 80044b4: b082 sub sp, #8 + 80044b6: af00 add r7, sp, #0 + 80044b8: 4603 mov r3, r0 + 80044ba: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); - 8004420: f997 3007 ldrsb.w r3, [r7, #7] - 8004424: 4618 mov r0, r3 - 8004426: f7ff ff31 bl 800428c <__NVIC_EnableIRQ> + 80044bc: f997 3007 ldrsb.w r3, [r7, #7] + 80044c0: 4618 mov r0, r3 + 80044c2: f7ff ff31 bl 8004328 <__NVIC_EnableIRQ> } - 800442a: bf00 nop - 800442c: 3708 adds r7, #8 - 800442e: 46bd mov sp, r7 - 8004430: bd80 pop {r7, pc} + 80044c6: bf00 nop + 80044c8: 3708 adds r7, #8 + 80044ca: 46bd mov sp, r7 + 80044cc: bd80 pop {r7, pc} -08004432 : +080044ce : * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { - 8004432: b580 push {r7, lr} - 8004434: b082 sub sp, #8 - 8004436: af00 add r7, sp, #0 - 8004438: 6078 str r0, [r7, #4] + 80044ce: b580 push {r7, lr} + 80044d0: b082 sub sp, #8 + 80044d2: af00 add r7, sp, #0 + 80044d4: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); - 800443a: 6878 ldr r0, [r7, #4] - 800443c: f7ff ffa2 bl 8004384 - 8004440: 4603 mov r3, r0 + 80044d6: 6878 ldr r0, [r7, #4] + 80044d8: f7ff ffa2 bl 8004420 + 80044dc: 4603 mov r3, r0 } - 8004442: 4618 mov r0, r3 - 8004444: 3708 adds r7, #8 - 8004446: 46bd mov sp, r7 - 8004448: bd80 pop {r7, pc} + 80044de: 4618 mov r0, r3 + 80044e0: 3708 adds r7, #8 + 80044e2: 46bd mov sp, r7 + 80044e4: bd80 pop {r7, pc} -0800444a : +080044e6 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) { - 800444a: b580 push {r7, lr} - 800444c: b084 sub sp, #16 - 800444e: af00 add r7, sp, #0 - 8004450: 6078 str r0, [r7, #4] + 80044e6: b580 push {r7, lr} + 80044e8: b084 sub sp, #16 + 80044ea: af00 add r7, sp, #0 + 80044ec: 6078 str r0, [r7, #4] uint32_t tmp = 0U; - 8004452: 2300 movs r3, #0 - 8004454: 60fb str r3, [r7, #12] + 80044ee: 2300 movs r3, #0 + 80044f0: 60fb str r3, [r7, #12] /* Check the DMA handle allocation */ if(NULL == hdma) - 8004456: 687b ldr r3, [r7, #4] - 8004458: 2b00 cmp r3, #0 - 800445a: d101 bne.n 8004460 + 80044f2: 687b ldr r3, [r7, #4] + 80044f4: 2b00 cmp r3, #0 + 80044f6: d101 bne.n 80044fc { return HAL_ERROR; - 800445c: 2301 movs r3, #1 - 800445e: e037 b.n 80044d0 + 80044f8: 2301 movs r3, #1 + 80044fa: e037 b.n 800456c assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); assert_param(IS_DMA_MODE(hdma->Init.Mode)); assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; - 8004460: 687b ldr r3, [r7, #4] - 8004462: 2202 movs r2, #2 - 8004464: f883 2021 strb.w r2, [r3, #33] @ 0x21 + 80044fc: 687b ldr r3, [r7, #4] + 80044fe: 2202 movs r2, #2 + 8004500: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Get the CR register value */ tmp = hdma->Instance->CCR; - 8004468: 687b ldr r3, [r7, #4] - 800446a: 681b ldr r3, [r3, #0] - 800446c: 681b ldr r3, [r3, #0] - 800446e: 60fb str r3, [r7, #12] + 8004504: 687b ldr r3, [r7, #4] + 8004506: 681b ldr r3, [r3, #0] + 8004508: 681b ldr r3, [r3, #0] + 800450a: 60fb str r3, [r7, #12] /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR bits */ tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \ - 8004470: 68fb ldr r3, [r7, #12] - 8004472: f423 537f bic.w r3, r3, #16320 @ 0x3fc0 - 8004476: f023 0330 bic.w r3, r3, #48 @ 0x30 - 800447a: 60fb str r3, [r7, #12] + 800450c: 68fb ldr r3, [r7, #12] + 800450e: f423 537f bic.w r3, r3, #16320 @ 0x3fc0 + 8004512: f023 0330 bic.w r3, r3, #48 @ 0x30 + 8004516: 60fb str r3, [r7, #12] DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \ DMA_CCR_DIR)); /* Prepare the DMA Channel configuration */ tmp |= hdma->Init.Direction | - 800447c: 687b ldr r3, [r7, #4] - 800447e: 685a ldr r2, [r3, #4] + 8004518: 687b ldr r3, [r7, #4] + 800451a: 685a ldr r2, [r3, #4] hdma->Init.PeriphInc | hdma->Init.MemInc | - 8004480: 687b ldr r3, [r7, #4] - 8004482: 689b ldr r3, [r3, #8] + 800451c: 687b ldr r3, [r7, #4] + 800451e: 689b ldr r3, [r3, #8] tmp |= hdma->Init.Direction | - 8004484: 431a orrs r2, r3 + 8004520: 431a orrs r2, r3 hdma->Init.PeriphInc | hdma->Init.MemInc | - 8004486: 687b ldr r3, [r7, #4] - 8004488: 68db ldr r3, [r3, #12] - 800448a: 431a orrs r2, r3 + 8004522: 687b ldr r3, [r7, #4] + 8004524: 68db ldr r3, [r3, #12] + 8004526: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | - 800448c: 687b ldr r3, [r7, #4] - 800448e: 691b ldr r3, [r3, #16] + 8004528: 687b ldr r3, [r7, #4] + 800452a: 691b ldr r3, [r3, #16] hdma->Init.PeriphInc | hdma->Init.MemInc | - 8004490: 431a orrs r2, r3 + 800452c: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | - 8004492: 687b ldr r3, [r7, #4] - 8004494: 695b ldr r3, [r3, #20] - 8004496: 431a orrs r2, r3 + 800452e: 687b ldr r3, [r7, #4] + 8004530: 695b ldr r3, [r3, #20] + 8004532: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; - 8004498: 687b ldr r3, [r7, #4] - 800449a: 699b ldr r3, [r3, #24] + 8004534: 687b ldr r3, [r7, #4] + 8004536: 699b ldr r3, [r3, #24] hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | - 800449c: 431a orrs r2, r3 + 8004538: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; - 800449e: 687b ldr r3, [r7, #4] - 80044a0: 69db ldr r3, [r3, #28] - 80044a2: 4313 orrs r3, r2 + 800453a: 687b ldr r3, [r7, #4] + 800453c: 69db ldr r3, [r3, #28] + 800453e: 4313 orrs r3, r2 tmp |= hdma->Init.Direction | - 80044a4: 68fa ldr r2, [r7, #12] - 80044a6: 4313 orrs r3, r2 - 80044a8: 60fb str r3, [r7, #12] + 8004540: 68fa ldr r2, [r7, #12] + 8004542: 4313 orrs r3, r2 + 8004544: 60fb str r3, [r7, #12] /* Write to DMA Channel CR register */ hdma->Instance->CCR = tmp; - 80044aa: 687b ldr r3, [r7, #4] - 80044ac: 681b ldr r3, [r3, #0] - 80044ae: 68fa ldr r2, [r7, #12] - 80044b0: 601a str r2, [r3, #0] + 8004546: 687b ldr r3, [r7, #4] + 8004548: 681b ldr r3, [r3, #0] + 800454a: 68fa ldr r2, [r7, #12] + 800454c: 601a str r2, [r3, #0] /* Initialize DmaBaseAddress and ChannelIndex parameters used by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ DMA_CalcBaseAndBitshift(hdma); - 80044b2: 6878 ldr r0, [r7, #4] - 80044b4: f000 f940 bl 8004738 + 800454e: 6878 ldr r0, [r7, #4] + 8004550: f000 f940 bl 80047d4 /* Initialise the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; - 80044b8: 687b ldr r3, [r7, #4] - 80044ba: 2200 movs r2, #0 - 80044bc: 639a str r2, [r3, #56] @ 0x38 + 8004554: 687b ldr r3, [r7, #4] + 8004556: 2200 movs r2, #0 + 8004558: 639a str r2, [r3, #56] @ 0x38 /* Initialize the DMA state*/ hdma->State = HAL_DMA_STATE_READY; - 80044be: 687b ldr r3, [r7, #4] - 80044c0: 2201 movs r2, #1 - 80044c2: f883 2021 strb.w r2, [r3, #33] @ 0x21 + 800455a: 687b ldr r3, [r7, #4] + 800455c: 2201 movs r2, #1 + 800455e: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Allocate lock resource and initialize it */ hdma->Lock = HAL_UNLOCKED; - 80044c6: 687b ldr r3, [r7, #4] - 80044c8: 2200 movs r2, #0 - 80044ca: f883 2020 strb.w r2, [r3, #32] + 8004562: 687b ldr r3, [r7, #4] + 8004564: 2200 movs r2, #0 + 8004566: f883 2020 strb.w r2, [r3, #32] return HAL_OK; - 80044ce: 2300 movs r3, #0 + 800456a: 2300 movs r3, #0 } - 80044d0: 4618 mov r0, r3 - 80044d2: 3710 adds r7, #16 - 80044d4: 46bd mov sp, r7 - 80044d6: bd80 pop {r7, pc} + 800456c: 4618 mov r0, r3 + 800456e: 3710 adds r7, #16 + 8004570: 46bd mov sp, r7 + 8004572: bd80 pop {r7, pc} -080044d8 : +08004574 : * @param DstAddress The destination memory Buffer address * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { - 80044d8: b580 push {r7, lr} - 80044da: b086 sub sp, #24 - 80044dc: af00 add r7, sp, #0 - 80044de: 60f8 str r0, [r7, #12] - 80044e0: 60b9 str r1, [r7, #8] - 80044e2: 607a str r2, [r7, #4] - 80044e4: 603b str r3, [r7, #0] + 8004574: b580 push {r7, lr} + 8004576: b086 sub sp, #24 + 8004578: af00 add r7, sp, #0 + 800457a: 60f8 str r0, [r7, #12] + 800457c: 60b9 str r1, [r7, #8] + 800457e: 607a str r2, [r7, #4] + 8004580: 603b str r3, [r7, #0] HAL_StatusTypeDef status = HAL_OK; - 80044e6: 2300 movs r3, #0 - 80044e8: 75fb strb r3, [r7, #23] + 8004582: 2300 movs r3, #0 + 8004584: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); /* Process locked */ __HAL_LOCK(hdma); - 80044ea: 68fb ldr r3, [r7, #12] - 80044ec: f893 3020 ldrb.w r3, [r3, #32] - 80044f0: 2b01 cmp r3, #1 - 80044f2: d101 bne.n 80044f8 - 80044f4: 2302 movs r3, #2 - 80044f6: e04a b.n 800458e - 80044f8: 68fb ldr r3, [r7, #12] - 80044fa: 2201 movs r2, #1 - 80044fc: f883 2020 strb.w r2, [r3, #32] + 8004586: 68fb ldr r3, [r7, #12] + 8004588: f893 3020 ldrb.w r3, [r3, #32] + 800458c: 2b01 cmp r3, #1 + 800458e: d101 bne.n 8004594 + 8004590: 2302 movs r3, #2 + 8004592: e04a b.n 800462a + 8004594: 68fb ldr r3, [r7, #12] + 8004596: 2201 movs r2, #1 + 8004598: f883 2020 strb.w r2, [r3, #32] if(HAL_DMA_STATE_READY == hdma->State) - 8004500: 68fb ldr r3, [r7, #12] - 8004502: f893 3021 ldrb.w r3, [r3, #33] @ 0x21 - 8004506: 2b01 cmp r3, #1 - 8004508: d13a bne.n 8004580 + 800459c: 68fb ldr r3, [r7, #12] + 800459e: f893 3021 ldrb.w r3, [r3, #33] @ 0x21 + 80045a2: 2b01 cmp r3, #1 + 80045a4: d13a bne.n 800461c { /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; - 800450a: 68fb ldr r3, [r7, #12] - 800450c: 2202 movs r2, #2 - 800450e: f883 2021 strb.w r2, [r3, #33] @ 0x21 + 80045a6: 68fb ldr r3, [r7, #12] + 80045a8: 2202 movs r2, #2 + 80045aa: f883 2021 strb.w r2, [r3, #33] @ 0x21 hdma->ErrorCode = HAL_DMA_ERROR_NONE; - 8004512: 68fb ldr r3, [r7, #12] - 8004514: 2200 movs r2, #0 - 8004516: 639a str r2, [r3, #56] @ 0x38 + 80045ae: 68fb ldr r3, [r7, #12] + 80045b0: 2200 movs r2, #0 + 80045b2: 639a str r2, [r3, #56] @ 0x38 /* Disable the peripheral */ hdma->Instance->CCR &= ~DMA_CCR_EN; - 8004518: 68fb ldr r3, [r7, #12] - 800451a: 681b ldr r3, [r3, #0] - 800451c: 681a ldr r2, [r3, #0] - 800451e: 68fb ldr r3, [r7, #12] - 8004520: 681b ldr r3, [r3, #0] - 8004522: f022 0201 bic.w r2, r2, #1 - 8004526: 601a str r2, [r3, #0] + 80045b4: 68fb ldr r3, [r7, #12] + 80045b6: 681b ldr r3, [r3, #0] + 80045b8: 681a ldr r2, [r3, #0] + 80045ba: 68fb ldr r3, [r7, #12] + 80045bc: 681b ldr r3, [r3, #0] + 80045be: f022 0201 bic.w r2, r2, #1 + 80045c2: 601a str r2, [r3, #0] /* Configure the source, destination address and the data length */ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); - 8004528: 683b ldr r3, [r7, #0] - 800452a: 687a ldr r2, [r7, #4] - 800452c: 68b9 ldr r1, [r7, #8] - 800452e: 68f8 ldr r0, [r7, #12] - 8004530: f000 f8d4 bl 80046dc + 80045c4: 683b ldr r3, [r7, #0] + 80045c6: 687a ldr r2, [r7, #4] + 80045c8: 68b9 ldr r1, [r7, #8] + 80045ca: 68f8 ldr r0, [r7, #12] + 80045cc: f000 f8d4 bl 8004778 /* Enable the transfer complete, & transfer error interrupts */ /* Half transfer interrupt is optional: enable it only if associated callback is available */ if(NULL != hdma->XferHalfCpltCallback ) - 8004534: 68fb ldr r3, [r7, #12] - 8004536: 6adb ldr r3, [r3, #44] @ 0x2c - 8004538: 2b00 cmp r3, #0 - 800453a: d008 beq.n 800454e + 80045d0: 68fb ldr r3, [r7, #12] + 80045d2: 6adb ldr r3, [r3, #44] @ 0x2c + 80045d4: 2b00 cmp r3, #0 + 80045d6: d008 beq.n 80045ea { hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE); - 800453c: 68fb ldr r3, [r7, #12] - 800453e: 681b ldr r3, [r3, #0] - 8004540: 681a ldr r2, [r3, #0] - 8004542: 68fb ldr r3, [r7, #12] - 8004544: 681b ldr r3, [r3, #0] - 8004546: f042 020e orr.w r2, r2, #14 - 800454a: 601a str r2, [r3, #0] - 800454c: e00f b.n 800456e + 80045d8: 68fb ldr r3, [r7, #12] + 80045da: 681b ldr r3, [r3, #0] + 80045dc: 681a ldr r2, [r3, #0] + 80045de: 68fb ldr r3, [r7, #12] + 80045e0: 681b ldr r3, [r3, #0] + 80045e2: f042 020e orr.w r2, r2, #14 + 80045e6: 601a str r2, [r3, #0] + 80045e8: e00f b.n 800460a } else { hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_TE); - 800454e: 68fb ldr r3, [r7, #12] - 8004550: 681b ldr r3, [r3, #0] - 8004552: 681a ldr r2, [r3, #0] - 8004554: 68fb ldr r3, [r7, #12] - 8004556: 681b ldr r3, [r3, #0] - 8004558: f042 020a orr.w r2, r2, #10 - 800455c: 601a str r2, [r3, #0] + 80045ea: 68fb ldr r3, [r7, #12] + 80045ec: 681b ldr r3, [r3, #0] + 80045ee: 681a ldr r2, [r3, #0] + 80045f0: 68fb ldr r3, [r7, #12] + 80045f2: 681b ldr r3, [r3, #0] + 80045f4: f042 020a orr.w r2, r2, #10 + 80045f8: 601a str r2, [r3, #0] hdma->Instance->CCR &= ~DMA_IT_HT; - 800455e: 68fb ldr r3, [r7, #12] - 8004560: 681b ldr r3, [r3, #0] - 8004562: 681a ldr r2, [r3, #0] - 8004564: 68fb ldr r3, [r7, #12] - 8004566: 681b ldr r3, [r3, #0] - 8004568: f022 0204 bic.w r2, r2, #4 - 800456c: 601a str r2, [r3, #0] + 80045fa: 68fb ldr r3, [r7, #12] + 80045fc: 681b ldr r3, [r3, #0] + 80045fe: 681a ldr r2, [r3, #0] + 8004600: 68fb ldr r3, [r7, #12] + 8004602: 681b ldr r3, [r3, #0] + 8004604: f022 0204 bic.w r2, r2, #4 + 8004608: 601a str r2, [r3, #0] } /* Enable the Peripheral */ hdma->Instance->CCR |= DMA_CCR_EN; - 800456e: 68fb ldr r3, [r7, #12] - 8004570: 681b ldr r3, [r3, #0] - 8004572: 681a ldr r2, [r3, #0] - 8004574: 68fb ldr r3, [r7, #12] - 8004576: 681b ldr r3, [r3, #0] - 8004578: f042 0201 orr.w r2, r2, #1 - 800457c: 601a str r2, [r3, #0] - 800457e: e005 b.n 800458c + 800460a: 68fb ldr r3, [r7, #12] + 800460c: 681b ldr r3, [r3, #0] + 800460e: 681a ldr r2, [r3, #0] + 8004610: 68fb ldr r3, [r7, #12] + 8004612: 681b ldr r3, [r3, #0] + 8004614: f042 0201 orr.w r2, r2, #1 + 8004618: 601a str r2, [r3, #0] + 800461a: e005 b.n 8004628 } else { /* Process Unlocked */ __HAL_UNLOCK(hdma); - 8004580: 68fb ldr r3, [r7, #12] - 8004582: 2200 movs r2, #0 - 8004584: f883 2020 strb.w r2, [r3, #32] + 800461c: 68fb ldr r3, [r7, #12] + 800461e: 2200 movs r2, #0 + 8004620: f883 2020 strb.w r2, [r3, #32] /* Remain BUSY */ status = HAL_BUSY; - 8004588: 2302 movs r3, #2 - 800458a: 75fb strb r3, [r7, #23] + 8004624: 2302 movs r3, #2 + 8004626: 75fb strb r3, [r7, #23] } return status; - 800458c: 7dfb ldrb r3, [r7, #23] + 8004628: 7dfb ldrb r3, [r7, #23] } - 800458e: 4618 mov r0, r3 - 8004590: 3718 adds r7, #24 - 8004592: 46bd mov sp, r7 - 8004594: bd80 pop {r7, pc} + 800462a: 4618 mov r0, r3 + 800462c: 3718 adds r7, #24 + 800462e: 46bd mov sp, r7 + 8004630: bd80 pop {r7, pc} -08004596 : +08004632 : * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval None */ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) { - 8004596: b580 push {r7, lr} - 8004598: b084 sub sp, #16 - 800459a: af00 add r7, sp, #0 - 800459c: 6078 str r0, [r7, #4] + 8004632: b580 push {r7, lr} + 8004634: b084 sub sp, #16 + 8004636: af00 add r7, sp, #0 + 8004638: 6078 str r0, [r7, #4] uint32_t flag_it = hdma->DmaBaseAddress->ISR; - 800459e: 687b ldr r3, [r7, #4] - 80045a0: 6bdb ldr r3, [r3, #60] @ 0x3c - 80045a2: 681b ldr r3, [r3, #0] - 80045a4: 60fb str r3, [r7, #12] + 800463a: 687b ldr r3, [r7, #4] + 800463c: 6bdb ldr r3, [r3, #60] @ 0x3c + 800463e: 681b ldr r3, [r3, #0] + 8004640: 60fb str r3, [r7, #12] uint32_t source_it = hdma->Instance->CCR; - 80045a6: 687b ldr r3, [r7, #4] - 80045a8: 681b ldr r3, [r3, #0] - 80045aa: 681b ldr r3, [r3, #0] - 80045ac: 60bb str r3, [r7, #8] + 8004642: 687b ldr r3, [r7, #4] + 8004644: 681b ldr r3, [r3, #0] + 8004646: 681b ldr r3, [r3, #0] + 8004648: 60bb str r3, [r7, #8] /* Half Transfer Complete Interrupt management ******************************/ if ((RESET != (flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_HT))) - 80045ae: 687b ldr r3, [r7, #4] - 80045b0: 6c1b ldr r3, [r3, #64] @ 0x40 - 80045b2: 2204 movs r2, #4 - 80045b4: 409a lsls r2, r3 - 80045b6: 68fb ldr r3, [r7, #12] - 80045b8: 4013 ands r3, r2 - 80045ba: 2b00 cmp r3, #0 - 80045bc: d024 beq.n 8004608 - 80045be: 68bb ldr r3, [r7, #8] - 80045c0: f003 0304 and.w r3, r3, #4 - 80045c4: 2b00 cmp r3, #0 - 80045c6: d01f beq.n 8004608 + 800464a: 687b ldr r3, [r7, #4] + 800464c: 6c1b ldr r3, [r3, #64] @ 0x40 + 800464e: 2204 movs r2, #4 + 8004650: 409a lsls r2, r3 + 8004652: 68fb ldr r3, [r7, #12] + 8004654: 4013 ands r3, r2 + 8004656: 2b00 cmp r3, #0 + 8004658: d024 beq.n 80046a4 + 800465a: 68bb ldr r3, [r7, #8] + 800465c: f003 0304 and.w r3, r3, #4 + 8004660: 2b00 cmp r3, #0 + 8004662: d01f beq.n 80046a4 { /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) - 80045c8: 687b ldr r3, [r7, #4] - 80045ca: 681b ldr r3, [r3, #0] - 80045cc: 681b ldr r3, [r3, #0] - 80045ce: f003 0320 and.w r3, r3, #32 - 80045d2: 2b00 cmp r3, #0 - 80045d4: d107 bne.n 80045e6 + 8004664: 687b ldr r3, [r7, #4] + 8004666: 681b ldr r3, [r3, #0] + 8004668: 681b ldr r3, [r3, #0] + 800466a: f003 0320 and.w r3, r3, #32 + 800466e: 2b00 cmp r3, #0 + 8004670: d107 bne.n 8004682 { /* Disable the half transfer interrupt */ hdma->Instance->CCR &= ~DMA_IT_HT; - 80045d6: 687b ldr r3, [r7, #4] - 80045d8: 681b ldr r3, [r3, #0] - 80045da: 681a ldr r2, [r3, #0] - 80045dc: 687b ldr r3, [r7, #4] - 80045de: 681b ldr r3, [r3, #0] - 80045e0: f022 0204 bic.w r2, r2, #4 - 80045e4: 601a str r2, [r3, #0] + 8004672: 687b ldr r3, [r7, #4] + 8004674: 681b ldr r3, [r3, #0] + 8004676: 681a ldr r2, [r3, #0] + 8004678: 687b ldr r3, [r7, #4] + 800467a: 681b ldr r3, [r3, #0] + 800467c: f022 0204 bic.w r2, r2, #4 + 8004680: 601a str r2, [r3, #0] } /* Clear the half transfer complete flag */ hdma->DmaBaseAddress->IFCR = DMA_FLAG_HT1 << hdma->ChannelIndex; - 80045e6: 687b ldr r3, [r7, #4] - 80045e8: 6c1a ldr r2, [r3, #64] @ 0x40 - 80045ea: 687b ldr r3, [r7, #4] - 80045ec: 6bdb ldr r3, [r3, #60] @ 0x3c - 80045ee: 2104 movs r1, #4 - 80045f0: fa01 f202 lsl.w r2, r1, r2 - 80045f4: 605a str r2, [r3, #4] + 8004682: 687b ldr r3, [r7, #4] + 8004684: 6c1a ldr r2, [r3, #64] @ 0x40 + 8004686: 687b ldr r3, [r7, #4] + 8004688: 6bdb ldr r3, [r3, #60] @ 0x3c + 800468a: 2104 movs r1, #4 + 800468c: fa01 f202 lsl.w r2, r1, r2 + 8004690: 605a str r2, [r3, #4] /* DMA peripheral state is not updated in Half Transfer */ /* State is updated only in Transfer Complete case */ if(hdma->XferHalfCpltCallback != NULL) - 80045f6: 687b ldr r3, [r7, #4] - 80045f8: 6adb ldr r3, [r3, #44] @ 0x2c - 80045fa: 2b00 cmp r3, #0 - 80045fc: d06a beq.n 80046d4 + 8004692: 687b ldr r3, [r7, #4] + 8004694: 6adb ldr r3, [r3, #44] @ 0x2c + 8004696: 2b00 cmp r3, #0 + 8004698: d06a beq.n 8004770 { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); - 80045fe: 687b ldr r3, [r7, #4] - 8004600: 6adb ldr r3, [r3, #44] @ 0x2c - 8004602: 6878 ldr r0, [r7, #4] - 8004604: 4798 blx r3 + 800469a: 687b ldr r3, [r7, #4] + 800469c: 6adb ldr r3, [r3, #44] @ 0x2c + 800469e: 6878 ldr r0, [r7, #4] + 80046a0: 4798 blx r3 if(hdma->XferHalfCpltCallback != NULL) - 8004606: e065 b.n 80046d4 + 80046a2: e065 b.n 8004770 } } /* Transfer Complete Interrupt management ***********************************/ else if ((RESET != (flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TC))) - 8004608: 687b ldr r3, [r7, #4] - 800460a: 6c1b ldr r3, [r3, #64] @ 0x40 - 800460c: 2202 movs r2, #2 - 800460e: 409a lsls r2, r3 - 8004610: 68fb ldr r3, [r7, #12] - 8004612: 4013 ands r3, r2 - 8004614: 2b00 cmp r3, #0 - 8004616: d02c beq.n 8004672 - 8004618: 68bb ldr r3, [r7, #8] - 800461a: f003 0302 and.w r3, r3, #2 - 800461e: 2b00 cmp r3, #0 - 8004620: d027 beq.n 8004672 + 80046a4: 687b ldr r3, [r7, #4] + 80046a6: 6c1b ldr r3, [r3, #64] @ 0x40 + 80046a8: 2202 movs r2, #2 + 80046aa: 409a lsls r2, r3 + 80046ac: 68fb ldr r3, [r7, #12] + 80046ae: 4013 ands r3, r2 + 80046b0: 2b00 cmp r3, #0 + 80046b2: d02c beq.n 800470e + 80046b4: 68bb ldr r3, [r7, #8] + 80046b6: f003 0302 and.w r3, r3, #2 + 80046ba: 2b00 cmp r3, #0 + 80046bc: d027 beq.n 800470e { if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) - 8004622: 687b ldr r3, [r7, #4] - 8004624: 681b ldr r3, [r3, #0] - 8004626: 681b ldr r3, [r3, #0] - 8004628: f003 0320 and.w r3, r3, #32 - 800462c: 2b00 cmp r3, #0 - 800462e: d10b bne.n 8004648 + 80046be: 687b ldr r3, [r7, #4] + 80046c0: 681b ldr r3, [r3, #0] + 80046c2: 681b ldr r3, [r3, #0] + 80046c4: f003 0320 and.w r3, r3, #32 + 80046c8: 2b00 cmp r3, #0 + 80046ca: d10b bne.n 80046e4 { /* Disable the transfer complete & transfer error interrupts */ /* if the DMA mode is not CIRCULAR */ hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_TE); - 8004630: 687b ldr r3, [r7, #4] - 8004632: 681b ldr r3, [r3, #0] - 8004634: 681a ldr r2, [r3, #0] - 8004636: 687b ldr r3, [r7, #4] - 8004638: 681b ldr r3, [r3, #0] - 800463a: f022 020a bic.w r2, r2, #10 - 800463e: 601a str r2, [r3, #0] + 80046cc: 687b ldr r3, [r7, #4] + 80046ce: 681b ldr r3, [r3, #0] + 80046d0: 681a ldr r2, [r3, #0] + 80046d2: 687b ldr r3, [r7, #4] + 80046d4: 681b ldr r3, [r3, #0] + 80046d6: f022 020a bic.w r2, r2, #10 + 80046da: 601a str r2, [r3, #0] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; - 8004640: 687b ldr r3, [r7, #4] - 8004642: 2201 movs r2, #1 - 8004644: f883 2021 strb.w r2, [r3, #33] @ 0x21 + 80046dc: 687b ldr r3, [r7, #4] + 80046de: 2201 movs r2, #1 + 80046e0: f883 2021 strb.w r2, [r3, #33] @ 0x21 } /* Clear the transfer complete flag */ hdma->DmaBaseAddress->IFCR = DMA_FLAG_TC1 << hdma->ChannelIndex; - 8004648: 687b ldr r3, [r7, #4] - 800464a: 6c1a ldr r2, [r3, #64] @ 0x40 - 800464c: 687b ldr r3, [r7, #4] - 800464e: 6bdb ldr r3, [r3, #60] @ 0x3c - 8004650: 2102 movs r1, #2 - 8004652: fa01 f202 lsl.w r2, r1, r2 - 8004656: 605a str r2, [r3, #4] + 80046e4: 687b ldr r3, [r7, #4] + 80046e6: 6c1a ldr r2, [r3, #64] @ 0x40 + 80046e8: 687b ldr r3, [r7, #4] + 80046ea: 6bdb ldr r3, [r3, #60] @ 0x3c + 80046ec: 2102 movs r1, #2 + 80046ee: fa01 f202 lsl.w r2, r1, r2 + 80046f2: 605a str r2, [r3, #4] /* Process Unlocked */ __HAL_UNLOCK(hdma); - 8004658: 687b ldr r3, [r7, #4] - 800465a: 2200 movs r2, #0 - 800465c: f883 2020 strb.w r2, [r3, #32] + 80046f4: 687b ldr r3, [r7, #4] + 80046f6: 2200 movs r2, #0 + 80046f8: f883 2020 strb.w r2, [r3, #32] if(hdma->XferCpltCallback != NULL) - 8004660: 687b ldr r3, [r7, #4] - 8004662: 6a9b ldr r3, [r3, #40] @ 0x28 - 8004664: 2b00 cmp r3, #0 - 8004666: d035 beq.n 80046d4 + 80046fc: 687b ldr r3, [r7, #4] + 80046fe: 6a9b ldr r3, [r3, #40] @ 0x28 + 8004700: 2b00 cmp r3, #0 + 8004702: d035 beq.n 8004770 { /* Transfer complete callback */ hdma->XferCpltCallback(hdma); - 8004668: 687b ldr r3, [r7, #4] - 800466a: 6a9b ldr r3, [r3, #40] @ 0x28 - 800466c: 6878 ldr r0, [r7, #4] - 800466e: 4798 blx r3 + 8004704: 687b ldr r3, [r7, #4] + 8004706: 6a9b ldr r3, [r3, #40] @ 0x28 + 8004708: 6878 ldr r0, [r7, #4] + 800470a: 4798 blx r3 if(hdma->XferCpltCallback != NULL) - 8004670: e030 b.n 80046d4 + 800470c: e030 b.n 8004770 } } /* Transfer Error Interrupt management ***************************************/ else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE))) - 8004672: 687b ldr r3, [r7, #4] - 8004674: 6c1b ldr r3, [r3, #64] @ 0x40 - 8004676: 2208 movs r2, #8 - 8004678: 409a lsls r2, r3 - 800467a: 68fb ldr r3, [r7, #12] - 800467c: 4013 ands r3, r2 - 800467e: 2b00 cmp r3, #0 - 8004680: d028 beq.n 80046d4 - 8004682: 68bb ldr r3, [r7, #8] - 8004684: f003 0308 and.w r3, r3, #8 - 8004688: 2b00 cmp r3, #0 - 800468a: d023 beq.n 80046d4 + 800470e: 687b ldr r3, [r7, #4] + 8004710: 6c1b ldr r3, [r3, #64] @ 0x40 + 8004712: 2208 movs r2, #8 + 8004714: 409a lsls r2, r3 + 8004716: 68fb ldr r3, [r7, #12] + 8004718: 4013 ands r3, r2 + 800471a: 2b00 cmp r3, #0 + 800471c: d028 beq.n 8004770 + 800471e: 68bb ldr r3, [r7, #8] + 8004720: f003 0308 and.w r3, r3, #8 + 8004724: 2b00 cmp r3, #0 + 8004726: d023 beq.n 8004770 { /* When a DMA transfer error occurs */ /* A hardware clear of its EN bits is performed */ /* Then, disable all DMA interrupts */ hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE); - 800468c: 687b ldr r3, [r7, #4] - 800468e: 681b ldr r3, [r3, #0] - 8004690: 681a ldr r2, [r3, #0] - 8004692: 687b ldr r3, [r7, #4] - 8004694: 681b ldr r3, [r3, #0] - 8004696: f022 020e bic.w r2, r2, #14 - 800469a: 601a str r2, [r3, #0] + 8004728: 687b ldr r3, [r7, #4] + 800472a: 681b ldr r3, [r3, #0] + 800472c: 681a ldr r2, [r3, #0] + 800472e: 687b ldr r3, [r7, #4] + 8004730: 681b ldr r3, [r3, #0] + 8004732: f022 020e bic.w r2, r2, #14 + 8004736: 601a str r2, [r3, #0] /* Clear all flags */ hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex; - 800469c: 687b ldr r3, [r7, #4] - 800469e: 6c1a ldr r2, [r3, #64] @ 0x40 - 80046a0: 687b ldr r3, [r7, #4] - 80046a2: 6bdb ldr r3, [r3, #60] @ 0x3c - 80046a4: 2101 movs r1, #1 - 80046a6: fa01 f202 lsl.w r2, r1, r2 - 80046aa: 605a str r2, [r3, #4] + 8004738: 687b ldr r3, [r7, #4] + 800473a: 6c1a ldr r2, [r3, #64] @ 0x40 + 800473c: 687b ldr r3, [r7, #4] + 800473e: 6bdb ldr r3, [r3, #60] @ 0x3c + 8004740: 2101 movs r1, #1 + 8004742: fa01 f202 lsl.w r2, r1, r2 + 8004746: 605a str r2, [r3, #4] /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TE; - 80046ac: 687b ldr r3, [r7, #4] - 80046ae: 2201 movs r2, #1 - 80046b0: 639a str r2, [r3, #56] @ 0x38 + 8004748: 687b ldr r3, [r7, #4] + 800474a: 2201 movs r2, #1 + 800474c: 639a str r2, [r3, #56] @ 0x38 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; - 80046b2: 687b ldr r3, [r7, #4] - 80046b4: 2201 movs r2, #1 - 80046b6: f883 2021 strb.w r2, [r3, #33] @ 0x21 + 800474e: 687b ldr r3, [r7, #4] + 8004750: 2201 movs r2, #1 + 8004752: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Process Unlocked */ __HAL_UNLOCK(hdma); - 80046ba: 687b ldr r3, [r7, #4] - 80046bc: 2200 movs r2, #0 - 80046be: f883 2020 strb.w r2, [r3, #32] + 8004756: 687b ldr r3, [r7, #4] + 8004758: 2200 movs r2, #0 + 800475a: f883 2020 strb.w r2, [r3, #32] if(hdma->XferErrorCallback != NULL) - 80046c2: 687b ldr r3, [r7, #4] - 80046c4: 6b1b ldr r3, [r3, #48] @ 0x30 - 80046c6: 2b00 cmp r3, #0 - 80046c8: d004 beq.n 80046d4 + 800475e: 687b ldr r3, [r7, #4] + 8004760: 6b1b ldr r3, [r3, #48] @ 0x30 + 8004762: 2b00 cmp r3, #0 + 8004764: d004 beq.n 8004770 { /* Transfer error callback */ hdma->XferErrorCallback(hdma); - 80046ca: 687b ldr r3, [r7, #4] - 80046cc: 6b1b ldr r3, [r3, #48] @ 0x30 - 80046ce: 6878 ldr r0, [r7, #4] - 80046d0: 4798 blx r3 + 8004766: 687b ldr r3, [r7, #4] + 8004768: 6b1b ldr r3, [r3, #48] @ 0x30 + 800476a: 6878 ldr r0, [r7, #4] + 800476c: 4798 blx r3 } } } - 80046d2: e7ff b.n 80046d4 - 80046d4: bf00 nop - 80046d6: 3710 adds r7, #16 - 80046d8: 46bd mov sp, r7 - 80046da: bd80 pop {r7, pc} + 800476e: e7ff b.n 8004770 + 8004770: bf00 nop + 8004772: 3710 adds r7, #16 + 8004774: 46bd mov sp, r7 + 8004776: bd80 pop {r7, pc} -080046dc : +08004778 : * @param DstAddress The destination memory Buffer address * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { - 80046dc: b480 push {r7} - 80046de: b085 sub sp, #20 - 80046e0: af00 add r7, sp, #0 - 80046e2: 60f8 str r0, [r7, #12] - 80046e4: 60b9 str r1, [r7, #8] - 80046e6: 607a str r2, [r7, #4] - 80046e8: 603b str r3, [r7, #0] + 8004778: b480 push {r7} + 800477a: b085 sub sp, #20 + 800477c: af00 add r7, sp, #0 + 800477e: 60f8 str r0, [r7, #12] + 8004780: 60b9 str r1, [r7, #8] + 8004782: 607a str r2, [r7, #4] + 8004784: 603b str r3, [r7, #0] /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_FLAG_GL1 << hdma->ChannelIndex); - 80046ea: 68fb ldr r3, [r7, #12] - 80046ec: 6c1a ldr r2, [r3, #64] @ 0x40 - 80046ee: 68fb ldr r3, [r7, #12] - 80046f0: 6bdb ldr r3, [r3, #60] @ 0x3c - 80046f2: 2101 movs r1, #1 - 80046f4: fa01 f202 lsl.w r2, r1, r2 - 80046f8: 605a str r2, [r3, #4] + 8004786: 68fb ldr r3, [r7, #12] + 8004788: 6c1a ldr r2, [r3, #64] @ 0x40 + 800478a: 68fb ldr r3, [r7, #12] + 800478c: 6bdb ldr r3, [r3, #60] @ 0x3c + 800478e: 2101 movs r1, #1 + 8004790: fa01 f202 lsl.w r2, r1, r2 + 8004794: 605a str r2, [r3, #4] /* Configure DMA Channel data length */ hdma->Instance->CNDTR = DataLength; - 80046fa: 68fb ldr r3, [r7, #12] - 80046fc: 681b ldr r3, [r3, #0] - 80046fe: 683a ldr r2, [r7, #0] - 8004700: 605a str r2, [r3, #4] + 8004796: 68fb ldr r3, [r7, #12] + 8004798: 681b ldr r3, [r3, #0] + 800479a: 683a ldr r2, [r7, #0] + 800479c: 605a str r2, [r3, #4] /* Peripheral to Memory */ if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) - 8004702: 68fb ldr r3, [r7, #12] - 8004704: 685b ldr r3, [r3, #4] - 8004706: 2b10 cmp r3, #16 - 8004708: d108 bne.n 800471c + 800479e: 68fb ldr r3, [r7, #12] + 80047a0: 685b ldr r3, [r3, #4] + 80047a2: 2b10 cmp r3, #16 + 80047a4: d108 bne.n 80047b8 { /* Configure DMA Channel destination address */ hdma->Instance->CPAR = DstAddress; - 800470a: 68fb ldr r3, [r7, #12] - 800470c: 681b ldr r3, [r3, #0] - 800470e: 687a ldr r2, [r7, #4] - 8004710: 609a str r2, [r3, #8] + 80047a6: 68fb ldr r3, [r7, #12] + 80047a8: 681b ldr r3, [r3, #0] + 80047aa: 687a ldr r2, [r7, #4] + 80047ac: 609a str r2, [r3, #8] /* Configure DMA Channel source address */ hdma->Instance->CMAR = SrcAddress; - 8004712: 68fb ldr r3, [r7, #12] - 8004714: 681b ldr r3, [r3, #0] - 8004716: 68ba ldr r2, [r7, #8] - 8004718: 60da str r2, [r3, #12] + 80047ae: 68fb ldr r3, [r7, #12] + 80047b0: 681b ldr r3, [r3, #0] + 80047b2: 68ba ldr r2, [r7, #8] + 80047b4: 60da str r2, [r3, #12] hdma->Instance->CPAR = SrcAddress; /* Configure DMA Channel destination address */ hdma->Instance->CMAR = DstAddress; } } - 800471a: e007 b.n 800472c + 80047b6: e007 b.n 80047c8 hdma->Instance->CPAR = SrcAddress; - 800471c: 68fb ldr r3, [r7, #12] - 800471e: 681b ldr r3, [r3, #0] - 8004720: 68ba ldr r2, [r7, #8] - 8004722: 609a str r2, [r3, #8] + 80047b8: 68fb ldr r3, [r7, #12] + 80047ba: 681b ldr r3, [r3, #0] + 80047bc: 68ba ldr r2, [r7, #8] + 80047be: 609a str r2, [r3, #8] hdma->Instance->CMAR = DstAddress; - 8004724: 68fb ldr r3, [r7, #12] - 8004726: 681b ldr r3, [r3, #0] - 8004728: 687a ldr r2, [r7, #4] - 800472a: 60da str r2, [r3, #12] + 80047c0: 68fb ldr r3, [r7, #12] + 80047c2: 681b ldr r3, [r3, #0] + 80047c4: 687a ldr r2, [r7, #4] + 80047c6: 60da str r2, [r3, #12] } - 800472c: bf00 nop - 800472e: 3714 adds r7, #20 - 8004730: 46bd mov sp, r7 - 8004732: f85d 7b04 ldr.w r7, [sp], #4 - 8004736: 4770 bx lr + 80047c8: bf00 nop + 80047ca: 3714 adds r7, #20 + 80047cc: 46bd mov sp, r7 + 80047ce: f85d 7b04 ldr.w r7, [sp], #4 + 80047d2: 4770 bx lr -08004738 : +080047d4 : * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval None */ static void DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) { - 8004738: b480 push {r7} - 800473a: b083 sub sp, #12 - 800473c: af00 add r7, sp, #0 - 800473e: 6078 str r0, [r7, #4] + 80047d4: b480 push {r7} + 80047d6: b083 sub sp, #12 + 80047d8: af00 add r7, sp, #0 + 80047da: 6078 str r0, [r7, #4] #if defined (DMA2) /* calculation of the channel index */ if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) - 8004740: 687b ldr r3, [r7, #4] - 8004742: 681b ldr r3, [r3, #0] - 8004744: 461a mov r2, r3 - 8004746: 4b14 ldr r3, [pc, #80] @ (8004798 ) - 8004748: 429a cmp r2, r3 - 800474a: d80f bhi.n 800476c + 80047dc: 687b ldr r3, [r7, #4] + 80047de: 681b ldr r3, [r3, #0] + 80047e0: 461a mov r2, r3 + 80047e2: 4b14 ldr r3, [pc, #80] @ (8004834 ) + 80047e4: 429a cmp r2, r3 + 80047e6: d80f bhi.n 8004808 { /* DMA1 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; - 800474c: 687b ldr r3, [r7, #4] - 800474e: 681b ldr r3, [r3, #0] - 8004750: 461a mov r2, r3 - 8004752: 4b12 ldr r3, [pc, #72] @ (800479c ) - 8004754: 4413 add r3, r2 - 8004756: 4a12 ldr r2, [pc, #72] @ (80047a0 ) - 8004758: fba2 2303 umull r2, r3, r2, r3 - 800475c: 091b lsrs r3, r3, #4 - 800475e: 009a lsls r2, r3, #2 - 8004760: 687b ldr r3, [r7, #4] - 8004762: 641a str r2, [r3, #64] @ 0x40 + 80047e8: 687b ldr r3, [r7, #4] + 80047ea: 681b ldr r3, [r3, #0] + 80047ec: 461a mov r2, r3 + 80047ee: 4b12 ldr r3, [pc, #72] @ (8004838 ) + 80047f0: 4413 add r3, r2 + 80047f2: 4a12 ldr r2, [pc, #72] @ (800483c ) + 80047f4: fba2 2303 umull r2, r3, r2, r3 + 80047f8: 091b lsrs r3, r3, #4 + 80047fa: 009a lsls r2, r3, #2 + 80047fc: 687b ldr r3, [r7, #4] + 80047fe: 641a str r2, [r3, #64] @ 0x40 hdma->DmaBaseAddress = DMA1; - 8004764: 687b ldr r3, [r7, #4] - 8004766: 4a0f ldr r2, [pc, #60] @ (80047a4 ) - 8004768: 63da str r2, [r3, #60] @ 0x3c + 8004800: 687b ldr r3, [r7, #4] + 8004802: 4a0f ldr r2, [pc, #60] @ (8004840 ) + 8004804: 63da str r2, [r3, #60] @ 0x3c /* calculation of the channel index */ /* DMA1 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; hdma->DmaBaseAddress = DMA1; #endif } - 800476a: e00e b.n 800478a + 8004806: e00e b.n 8004826 hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U; - 800476c: 687b ldr r3, [r7, #4] - 800476e: 681b ldr r3, [r3, #0] - 8004770: 461a mov r2, r3 - 8004772: 4b0d ldr r3, [pc, #52] @ (80047a8 ) - 8004774: 4413 add r3, r2 - 8004776: 4a0a ldr r2, [pc, #40] @ (80047a0 ) - 8004778: fba2 2303 umull r2, r3, r2, r3 - 800477c: 091b lsrs r3, r3, #4 - 800477e: 009a lsls r2, r3, #2 - 8004780: 687b ldr r3, [r7, #4] - 8004782: 641a str r2, [r3, #64] @ 0x40 + 8004808: 687b ldr r3, [r7, #4] + 800480a: 681b ldr r3, [r3, #0] + 800480c: 461a mov r2, r3 + 800480e: 4b0d ldr r3, [pc, #52] @ (8004844 ) + 8004810: 4413 add r3, r2 + 8004812: 4a0a ldr r2, [pc, #40] @ (800483c ) + 8004814: fba2 2303 umull r2, r3, r2, r3 + 8004818: 091b lsrs r3, r3, #4 + 800481a: 009a lsls r2, r3, #2 + 800481c: 687b ldr r3, [r7, #4] + 800481e: 641a str r2, [r3, #64] @ 0x40 hdma->DmaBaseAddress = DMA2; - 8004784: 687b ldr r3, [r7, #4] - 8004786: 4a09 ldr r2, [pc, #36] @ (80047ac ) - 8004788: 63da str r2, [r3, #60] @ 0x3c + 8004820: 687b ldr r3, [r7, #4] + 8004822: 4a09 ldr r2, [pc, #36] @ (8004848 ) + 8004824: 63da str r2, [r3, #60] @ 0x3c } - 800478a: bf00 nop - 800478c: 370c adds r7, #12 - 800478e: 46bd mov sp, r7 - 8004790: f85d 7b04 ldr.w r7, [sp], #4 - 8004794: 4770 bx lr - 8004796: bf00 nop - 8004798: 40020407 .word 0x40020407 - 800479c: bffdfff8 .word 0xbffdfff8 - 80047a0: cccccccd .word 0xcccccccd - 80047a4: 40020000 .word 0x40020000 - 80047a8: bffdfbf8 .word 0xbffdfbf8 - 80047ac: 40020400 .word 0x40020400 + 8004826: bf00 nop + 8004828: 370c adds r7, #12 + 800482a: 46bd mov sp, r7 + 800482c: f85d 7b04 ldr.w r7, [sp], #4 + 8004830: 4770 bx lr + 8004832: bf00 nop + 8004834: 40020407 .word 0x40020407 + 8004838: bffdfff8 .word 0xbffdfff8 + 800483c: cccccccd .word 0xcccccccd + 8004840: 40020000 .word 0x40020000 + 8004844: bffdfbf8 .word 0xbffdfbf8 + 8004848: 40020400 .word 0x40020400 -080047b0 : +0800484c : * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { - 80047b0: b480 push {r7} - 80047b2: b087 sub sp, #28 - 80047b4: af00 add r7, sp, #0 - 80047b6: 6078 str r0, [r7, #4] - 80047b8: 6039 str r1, [r7, #0] + 800484c: b480 push {r7} + 800484e: b087 sub sp, #28 + 8004850: af00 add r7, sp, #0 + 8004852: 6078 str r0, [r7, #4] + 8004854: 6039 str r1, [r7, #0] uint32_t position = 0x00u; - 80047ba: 2300 movs r3, #0 - 80047bc: 617b str r3, [r7, #20] + 8004856: 2300 movs r3, #0 + 8004858: 617b str r3, [r7, #20] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00u) - 80047be: e154 b.n 8004a6a + 800485a: e154 b.n 8004b06 { /* Get current io position */ iocurrent = (GPIO_Init->Pin) & (1uL << position); - 80047c0: 683b ldr r3, [r7, #0] - 80047c2: 681a ldr r2, [r3, #0] - 80047c4: 2101 movs r1, #1 - 80047c6: 697b ldr r3, [r7, #20] - 80047c8: fa01 f303 lsl.w r3, r1, r3 - 80047cc: 4013 ands r3, r2 - 80047ce: 60fb str r3, [r7, #12] + 800485c: 683b ldr r3, [r7, #0] + 800485e: 681a ldr r2, [r3, #0] + 8004860: 2101 movs r1, #1 + 8004862: 697b ldr r3, [r7, #20] + 8004864: fa01 f303 lsl.w r3, r1, r3 + 8004868: 4013 ands r3, r2 + 800486a: 60fb str r3, [r7, #12] if (iocurrent != 0x00u) - 80047d0: 68fb ldr r3, [r7, #12] - 80047d2: 2b00 cmp r3, #0 - 80047d4: f000 8146 beq.w 8004a64 + 800486c: 68fb ldr r3, [r7, #12] + 800486e: 2b00 cmp r3, #0 + 8004870: f000 8146 beq.w 8004b00 { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) - 80047d8: 683b ldr r3, [r7, #0] - 80047da: 685b ldr r3, [r3, #4] - 80047dc: f003 0303 and.w r3, r3, #3 - 80047e0: 2b01 cmp r3, #1 - 80047e2: d005 beq.n 80047f0 - 80047e4: 683b ldr r3, [r7, #0] - 80047e6: 685b ldr r3, [r3, #4] - 80047e8: f003 0303 and.w r3, r3, #3 - 80047ec: 2b02 cmp r3, #2 - 80047ee: d130 bne.n 8004852 + 8004874: 683b ldr r3, [r7, #0] + 8004876: 685b ldr r3, [r3, #4] + 8004878: f003 0303 and.w r3, r3, #3 + 800487c: 2b01 cmp r3, #1 + 800487e: d005 beq.n 800488c + 8004880: 683b ldr r3, [r7, #0] + 8004882: 685b ldr r3, [r3, #4] + 8004884: f003 0303 and.w r3, r3, #3 + 8004888: 2b02 cmp r3, #2 + 800488a: d130 bne.n 80048ee { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; - 80047f0: 687b ldr r3, [r7, #4] - 80047f2: 689b ldr r3, [r3, #8] - 80047f4: 613b str r3, [r7, #16] + 800488c: 687b ldr r3, [r7, #4] + 800488e: 689b ldr r3, [r3, #8] + 8004890: 613b str r3, [r7, #16] temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2u)); - 80047f6: 697b ldr r3, [r7, #20] - 80047f8: 005b lsls r3, r3, #1 - 80047fa: 2203 movs r2, #3 - 80047fc: fa02 f303 lsl.w r3, r2, r3 - 8004800: 43db mvns r3, r3 - 8004802: 693a ldr r2, [r7, #16] - 8004804: 4013 ands r3, r2 - 8004806: 613b str r3, [r7, #16] + 8004892: 697b ldr r3, [r7, #20] + 8004894: 005b lsls r3, r3, #1 + 8004896: 2203 movs r2, #3 + 8004898: fa02 f303 lsl.w r3, r2, r3 + 800489c: 43db mvns r3, r3 + 800489e: 693a ldr r2, [r7, #16] + 80048a0: 4013 ands r3, r2 + 80048a2: 613b str r3, [r7, #16] temp |= (GPIO_Init->Speed << (position * 2u)); - 8004808: 683b ldr r3, [r7, #0] - 800480a: 68da ldr r2, [r3, #12] - 800480c: 697b ldr r3, [r7, #20] - 800480e: 005b lsls r3, r3, #1 - 8004810: fa02 f303 lsl.w r3, r2, r3 - 8004814: 693a ldr r2, [r7, #16] - 8004816: 4313 orrs r3, r2 - 8004818: 613b str r3, [r7, #16] + 80048a4: 683b ldr r3, [r7, #0] + 80048a6: 68da ldr r2, [r3, #12] + 80048a8: 697b ldr r3, [r7, #20] + 80048aa: 005b lsls r3, r3, #1 + 80048ac: fa02 f303 lsl.w r3, r2, r3 + 80048b0: 693a ldr r2, [r7, #16] + 80048b2: 4313 orrs r3, r2 + 80048b4: 613b str r3, [r7, #16] GPIOx->OSPEEDR = temp; - 800481a: 687b ldr r3, [r7, #4] - 800481c: 693a ldr r2, [r7, #16] - 800481e: 609a str r2, [r3, #8] + 80048b6: 687b ldr r3, [r7, #4] + 80048b8: 693a ldr r2, [r7, #16] + 80048ba: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; - 8004820: 687b ldr r3, [r7, #4] - 8004822: 685b ldr r3, [r3, #4] - 8004824: 613b str r3, [r7, #16] + 80048bc: 687b ldr r3, [r7, #4] + 80048be: 685b ldr r3, [r3, #4] + 80048c0: 613b str r3, [r7, #16] temp &= ~(GPIO_OTYPER_OT_0 << position) ; - 8004826: 2201 movs r2, #1 - 8004828: 697b ldr r3, [r7, #20] - 800482a: fa02 f303 lsl.w r3, r2, r3 - 800482e: 43db mvns r3, r3 - 8004830: 693a ldr r2, [r7, #16] - 8004832: 4013 ands r3, r2 - 8004834: 613b str r3, [r7, #16] + 80048c2: 2201 movs r2, #1 + 80048c4: 697b ldr r3, [r7, #20] + 80048c6: fa02 f303 lsl.w r3, r2, r3 + 80048ca: 43db mvns r3, r3 + 80048cc: 693a ldr r2, [r7, #16] + 80048ce: 4013 ands r3, r2 + 80048d0: 613b str r3, [r7, #16] temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); - 8004836: 683b ldr r3, [r7, #0] - 8004838: 685b ldr r3, [r3, #4] - 800483a: 091b lsrs r3, r3, #4 - 800483c: f003 0201 and.w r2, r3, #1 - 8004840: 697b ldr r3, [r7, #20] - 8004842: fa02 f303 lsl.w r3, r2, r3 - 8004846: 693a ldr r2, [r7, #16] - 8004848: 4313 orrs r3, r2 - 800484a: 613b str r3, [r7, #16] + 80048d2: 683b ldr r3, [r7, #0] + 80048d4: 685b ldr r3, [r3, #4] + 80048d6: 091b lsrs r3, r3, #4 + 80048d8: f003 0201 and.w r2, r3, #1 + 80048dc: 697b ldr r3, [r7, #20] + 80048de: fa02 f303 lsl.w r3, r2, r3 + 80048e2: 693a ldr r2, [r7, #16] + 80048e4: 4313 orrs r3, r2 + 80048e6: 613b str r3, [r7, #16] GPIOx->OTYPER = temp; - 800484c: 687b ldr r3, [r7, #4] - 800484e: 693a ldr r2, [r7, #16] - 8004850: 605a str r2, [r3, #4] + 80048e8: 687b ldr r3, [r7, #4] + 80048ea: 693a ldr r2, [r7, #16] + 80048ec: 605a str r2, [r3, #4] } if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) - 8004852: 683b ldr r3, [r7, #0] - 8004854: 685b ldr r3, [r3, #4] - 8004856: f003 0303 and.w r3, r3, #3 - 800485a: 2b03 cmp r3, #3 - 800485c: d017 beq.n 800488e + 80048ee: 683b ldr r3, [r7, #0] + 80048f0: 685b ldr r3, [r3, #4] + 80048f2: f003 0303 and.w r3, r3, #3 + 80048f6: 2b03 cmp r3, #3 + 80048f8: d017 beq.n 800492a { /* Check the Pull parameter */ assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; - 800485e: 687b ldr r3, [r7, #4] - 8004860: 68db ldr r3, [r3, #12] - 8004862: 613b str r3, [r7, #16] + 80048fa: 687b ldr r3, [r7, #4] + 80048fc: 68db ldr r3, [r3, #12] + 80048fe: 613b str r3, [r7, #16] temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2u)); - 8004864: 697b ldr r3, [r7, #20] - 8004866: 005b lsls r3, r3, #1 - 8004868: 2203 movs r2, #3 - 800486a: fa02 f303 lsl.w r3, r2, r3 - 800486e: 43db mvns r3, r3 - 8004870: 693a ldr r2, [r7, #16] - 8004872: 4013 ands r3, r2 - 8004874: 613b str r3, [r7, #16] + 8004900: 697b ldr r3, [r7, #20] + 8004902: 005b lsls r3, r3, #1 + 8004904: 2203 movs r2, #3 + 8004906: fa02 f303 lsl.w r3, r2, r3 + 800490a: 43db mvns r3, r3 + 800490c: 693a ldr r2, [r7, #16] + 800490e: 4013 ands r3, r2 + 8004910: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Pull) << (position * 2u)); - 8004876: 683b ldr r3, [r7, #0] - 8004878: 689a ldr r2, [r3, #8] - 800487a: 697b ldr r3, [r7, #20] - 800487c: 005b lsls r3, r3, #1 - 800487e: fa02 f303 lsl.w r3, r2, r3 - 8004882: 693a ldr r2, [r7, #16] - 8004884: 4313 orrs r3, r2 - 8004886: 613b str r3, [r7, #16] + 8004912: 683b ldr r3, [r7, #0] + 8004914: 689a ldr r2, [r3, #8] + 8004916: 697b ldr r3, [r7, #20] + 8004918: 005b lsls r3, r3, #1 + 800491a: fa02 f303 lsl.w r3, r2, r3 + 800491e: 693a ldr r2, [r7, #16] + 8004920: 4313 orrs r3, r2 + 8004922: 613b str r3, [r7, #16] GPIOx->PUPDR = temp; - 8004888: 687b ldr r3, [r7, #4] - 800488a: 693a ldr r2, [r7, #16] - 800488c: 60da str r2, [r3, #12] + 8004924: 687b ldr r3, [r7, #4] + 8004926: 693a ldr r2, [r7, #16] + 8004928: 60da str r2, [r3, #12] } /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Alternate function mode selection */ if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) - 800488e: 683b ldr r3, [r7, #0] - 8004890: 685b ldr r3, [r3, #4] - 8004892: f003 0303 and.w r3, r3, #3 - 8004896: 2b02 cmp r3, #2 - 8004898: d123 bne.n 80048e2 + 800492a: 683b ldr r3, [r7, #0] + 800492c: 685b ldr r3, [r3, #4] + 800492e: f003 0303 and.w r3, r3, #3 + 8004932: 2b02 cmp r3, #2 + 8004934: d123 bne.n 800497e /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3u]; - 800489a: 697b ldr r3, [r7, #20] - 800489c: 08da lsrs r2, r3, #3 - 800489e: 687b ldr r3, [r7, #4] - 80048a0: 3208 adds r2, #8 - 80048a2: f853 3022 ldr.w r3, [r3, r2, lsl #2] - 80048a6: 613b str r3, [r7, #16] + 8004936: 697b ldr r3, [r7, #20] + 8004938: 08da lsrs r2, r3, #3 + 800493a: 687b ldr r3, [r7, #4] + 800493c: 3208 adds r2, #8 + 800493e: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8004942: 613b str r3, [r7, #16] temp &= ~(0xFu << ((position & 0x07u) * 4u)); - 80048a8: 697b ldr r3, [r7, #20] - 80048aa: f003 0307 and.w r3, r3, #7 - 80048ae: 009b lsls r3, r3, #2 - 80048b0: 220f movs r2, #15 - 80048b2: fa02 f303 lsl.w r3, r2, r3 - 80048b6: 43db mvns r3, r3 - 80048b8: 693a ldr r2, [r7, #16] - 80048ba: 4013 ands r3, r2 - 80048bc: 613b str r3, [r7, #16] + 8004944: 697b ldr r3, [r7, #20] + 8004946: f003 0307 and.w r3, r3, #7 + 800494a: 009b lsls r3, r3, #2 + 800494c: 220f movs r2, #15 + 800494e: fa02 f303 lsl.w r3, r2, r3 + 8004952: 43db mvns r3, r3 + 8004954: 693a ldr r2, [r7, #16] + 8004956: 4013 ands r3, r2 + 8004958: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u)); - 80048be: 683b ldr r3, [r7, #0] - 80048c0: 691a ldr r2, [r3, #16] - 80048c2: 697b ldr r3, [r7, #20] - 80048c4: f003 0307 and.w r3, r3, #7 - 80048c8: 009b lsls r3, r3, #2 - 80048ca: fa02 f303 lsl.w r3, r2, r3 - 80048ce: 693a ldr r2, [r7, #16] - 80048d0: 4313 orrs r3, r2 - 80048d2: 613b str r3, [r7, #16] + 800495a: 683b ldr r3, [r7, #0] + 800495c: 691a ldr r2, [r3, #16] + 800495e: 697b ldr r3, [r7, #20] + 8004960: f003 0307 and.w r3, r3, #7 + 8004964: 009b lsls r3, r3, #2 + 8004966: fa02 f303 lsl.w r3, r2, r3 + 800496a: 693a ldr r2, [r7, #16] + 800496c: 4313 orrs r3, r2 + 800496e: 613b str r3, [r7, #16] GPIOx->AFR[position >> 3u] = temp; - 80048d4: 697b ldr r3, [r7, #20] - 80048d6: 08da lsrs r2, r3, #3 - 80048d8: 687b ldr r3, [r7, #4] - 80048da: 3208 adds r2, #8 - 80048dc: 6939 ldr r1, [r7, #16] - 80048de: f843 1022 str.w r1, [r3, r2, lsl #2] + 8004970: 697b ldr r3, [r7, #20] + 8004972: 08da lsrs r2, r3, #3 + 8004974: 687b ldr r3, [r7, #4] + 8004976: 3208 adds r2, #8 + 8004978: 6939 ldr r1, [r7, #16] + 800497a: f843 1022 str.w r1, [r3, r2, lsl #2] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; - 80048e2: 687b ldr r3, [r7, #4] - 80048e4: 681b ldr r3, [r3, #0] - 80048e6: 613b str r3, [r7, #16] + 800497e: 687b ldr r3, [r7, #4] + 8004980: 681b ldr r3, [r3, #0] + 8004982: 613b str r3, [r7, #16] temp &= ~(GPIO_MODER_MODER0 << (position * 2u)); - 80048e8: 697b ldr r3, [r7, #20] - 80048ea: 005b lsls r3, r3, #1 - 80048ec: 2203 movs r2, #3 - 80048ee: fa02 f303 lsl.w r3, r2, r3 - 80048f2: 43db mvns r3, r3 - 80048f4: 693a ldr r2, [r7, #16] - 80048f6: 4013 ands r3, r2 - 80048f8: 613b str r3, [r7, #16] + 8004984: 697b ldr r3, [r7, #20] + 8004986: 005b lsls r3, r3, #1 + 8004988: 2203 movs r2, #3 + 800498a: fa02 f303 lsl.w r3, r2, r3 + 800498e: 43db mvns r3, r3 + 8004990: 693a ldr r2, [r7, #16] + 8004992: 4013 ands r3, r2 + 8004994: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u)); - 80048fa: 683b ldr r3, [r7, #0] - 80048fc: 685b ldr r3, [r3, #4] - 80048fe: f003 0203 and.w r2, r3, #3 - 8004902: 697b ldr r3, [r7, #20] - 8004904: 005b lsls r3, r3, #1 - 8004906: fa02 f303 lsl.w r3, r2, r3 - 800490a: 693a ldr r2, [r7, #16] - 800490c: 4313 orrs r3, r2 - 800490e: 613b str r3, [r7, #16] + 8004996: 683b ldr r3, [r7, #0] + 8004998: 685b ldr r3, [r3, #4] + 800499a: f003 0203 and.w r2, r3, #3 + 800499e: 697b ldr r3, [r7, #20] + 80049a0: 005b lsls r3, r3, #1 + 80049a2: fa02 f303 lsl.w r3, r2, r3 + 80049a6: 693a ldr r2, [r7, #16] + 80049a8: 4313 orrs r3, r2 + 80049aa: 613b str r3, [r7, #16] GPIOx->MODER = temp; - 8004910: 687b ldr r3, [r7, #4] - 8004912: 693a ldr r2, [r7, #16] - 8004914: 601a str r2, [r3, #0] + 80049ac: 687b ldr r3, [r7, #4] + 80049ae: 693a ldr r2, [r7, #16] + 80049b0: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if((GPIO_Init->Mode & EXTI_MODE) != 0x00u) - 8004916: 683b ldr r3, [r7, #0] - 8004918: 685b ldr r3, [r3, #4] - 800491a: f403 3340 and.w r3, r3, #196608 @ 0x30000 - 800491e: 2b00 cmp r3, #0 - 8004920: f000 80a0 beq.w 8004a64 + 80049b2: 683b ldr r3, [r7, #0] + 80049b4: 685b ldr r3, [r3, #4] + 80049b6: f403 3340 and.w r3, r3, #196608 @ 0x30000 + 80049ba: 2b00 cmp r3, #0 + 80049bc: f000 80a0 beq.w 8004b00 { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); - 8004924: 4b58 ldr r3, [pc, #352] @ (8004a88 ) - 8004926: 699b ldr r3, [r3, #24] - 8004928: 4a57 ldr r2, [pc, #348] @ (8004a88 ) - 800492a: f043 0301 orr.w r3, r3, #1 - 800492e: 6193 str r3, [r2, #24] - 8004930: 4b55 ldr r3, [pc, #340] @ (8004a88 ) - 8004932: 699b ldr r3, [r3, #24] - 8004934: f003 0301 and.w r3, r3, #1 - 8004938: 60bb str r3, [r7, #8] - 800493a: 68bb ldr r3, [r7, #8] + 80049c0: 4b58 ldr r3, [pc, #352] @ (8004b24 ) + 80049c2: 699b ldr r3, [r3, #24] + 80049c4: 4a57 ldr r2, [pc, #348] @ (8004b24 ) + 80049c6: f043 0301 orr.w r3, r3, #1 + 80049ca: 6193 str r3, [r2, #24] + 80049cc: 4b55 ldr r3, [pc, #340] @ (8004b24 ) + 80049ce: 699b ldr r3, [r3, #24] + 80049d0: f003 0301 and.w r3, r3, #1 + 80049d4: 60bb str r3, [r7, #8] + 80049d6: 68bb ldr r3, [r7, #8] temp = SYSCFG->EXTICR[position >> 2u]; - 800493c: 4a53 ldr r2, [pc, #332] @ (8004a8c ) - 800493e: 697b ldr r3, [r7, #20] - 8004940: 089b lsrs r3, r3, #2 - 8004942: 3302 adds r3, #2 - 8004944: f852 3023 ldr.w r3, [r2, r3, lsl #2] - 8004948: 613b str r3, [r7, #16] + 80049d8: 4a53 ldr r2, [pc, #332] @ (8004b28 ) + 80049da: 697b ldr r3, [r7, #20] + 80049dc: 089b lsrs r3, r3, #2 + 80049de: 3302 adds r3, #2 + 80049e0: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 80049e4: 613b str r3, [r7, #16] temp &= ~(0x0FuL << (4u * (position & 0x03u))); - 800494a: 697b ldr r3, [r7, #20] - 800494c: f003 0303 and.w r3, r3, #3 - 8004950: 009b lsls r3, r3, #2 - 8004952: 220f movs r2, #15 - 8004954: fa02 f303 lsl.w r3, r2, r3 - 8004958: 43db mvns r3, r3 - 800495a: 693a ldr r2, [r7, #16] - 800495c: 4013 ands r3, r2 - 800495e: 613b str r3, [r7, #16] + 80049e6: 697b ldr r3, [r7, #20] + 80049e8: f003 0303 and.w r3, r3, #3 + 80049ec: 009b lsls r3, r3, #2 + 80049ee: 220f movs r2, #15 + 80049f0: fa02 f303 lsl.w r3, r2, r3 + 80049f4: 43db mvns r3, r3 + 80049f6: 693a ldr r2, [r7, #16] + 80049f8: 4013 ands r3, r2 + 80049fa: 613b str r3, [r7, #16] temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u))); - 8004960: 687b ldr r3, [r7, #4] - 8004962: f1b3 4f90 cmp.w r3, #1207959552 @ 0x48000000 - 8004966: d019 beq.n 800499c - 8004968: 687b ldr r3, [r7, #4] - 800496a: 4a49 ldr r2, [pc, #292] @ (8004a90 ) - 800496c: 4293 cmp r3, r2 - 800496e: d013 beq.n 8004998 - 8004970: 687b ldr r3, [r7, #4] - 8004972: 4a48 ldr r2, [pc, #288] @ (8004a94 ) - 8004974: 4293 cmp r3, r2 - 8004976: d00d beq.n 8004994 - 8004978: 687b ldr r3, [r7, #4] - 800497a: 4a47 ldr r2, [pc, #284] @ (8004a98 ) - 800497c: 4293 cmp r3, r2 - 800497e: d007 beq.n 8004990 - 8004980: 687b ldr r3, [r7, #4] - 8004982: 4a46 ldr r2, [pc, #280] @ (8004a9c ) - 8004984: 4293 cmp r3, r2 - 8004986: d101 bne.n 800498c - 8004988: 2304 movs r3, #4 - 800498a: e008 b.n 800499e - 800498c: 2305 movs r3, #5 - 800498e: e006 b.n 800499e - 8004990: 2303 movs r3, #3 - 8004992: e004 b.n 800499e - 8004994: 2302 movs r3, #2 - 8004996: e002 b.n 800499e - 8004998: 2301 movs r3, #1 - 800499a: e000 b.n 800499e - 800499c: 2300 movs r3, #0 - 800499e: 697a ldr r2, [r7, #20] - 80049a0: f002 0203 and.w r2, r2, #3 - 80049a4: 0092 lsls r2, r2, #2 - 80049a6: 4093 lsls r3, r2 - 80049a8: 693a ldr r2, [r7, #16] - 80049aa: 4313 orrs r3, r2 - 80049ac: 613b str r3, [r7, #16] + 80049fc: 687b ldr r3, [r7, #4] + 80049fe: f1b3 4f90 cmp.w r3, #1207959552 @ 0x48000000 + 8004a02: d019 beq.n 8004a38 + 8004a04: 687b ldr r3, [r7, #4] + 8004a06: 4a49 ldr r2, [pc, #292] @ (8004b2c ) + 8004a08: 4293 cmp r3, r2 + 8004a0a: d013 beq.n 8004a34 + 8004a0c: 687b ldr r3, [r7, #4] + 8004a0e: 4a48 ldr r2, [pc, #288] @ (8004b30 ) + 8004a10: 4293 cmp r3, r2 + 8004a12: d00d beq.n 8004a30 + 8004a14: 687b ldr r3, [r7, #4] + 8004a16: 4a47 ldr r2, [pc, #284] @ (8004b34 ) + 8004a18: 4293 cmp r3, r2 + 8004a1a: d007 beq.n 8004a2c + 8004a1c: 687b ldr r3, [r7, #4] + 8004a1e: 4a46 ldr r2, [pc, #280] @ (8004b38 ) + 8004a20: 4293 cmp r3, r2 + 8004a22: d101 bne.n 8004a28 + 8004a24: 2304 movs r3, #4 + 8004a26: e008 b.n 8004a3a + 8004a28: 2305 movs r3, #5 + 8004a2a: e006 b.n 8004a3a + 8004a2c: 2303 movs r3, #3 + 8004a2e: e004 b.n 8004a3a + 8004a30: 2302 movs r3, #2 + 8004a32: e002 b.n 8004a3a + 8004a34: 2301 movs r3, #1 + 8004a36: e000 b.n 8004a3a + 8004a38: 2300 movs r3, #0 + 8004a3a: 697a ldr r2, [r7, #20] + 8004a3c: f002 0203 and.w r2, r2, #3 + 8004a40: 0092 lsls r2, r2, #2 + 8004a42: 4093 lsls r3, r2 + 8004a44: 693a ldr r2, [r7, #16] + 8004a46: 4313 orrs r3, r2 + 8004a48: 613b str r3, [r7, #16] SYSCFG->EXTICR[position >> 2u] = temp; - 80049ae: 4937 ldr r1, [pc, #220] @ (8004a8c ) - 80049b0: 697b ldr r3, [r7, #20] - 80049b2: 089b lsrs r3, r3, #2 - 80049b4: 3302 adds r3, #2 - 80049b6: 693a ldr r2, [r7, #16] - 80049b8: f841 2023 str.w r2, [r1, r3, lsl #2] + 8004a4a: 4937 ldr r1, [pc, #220] @ (8004b28 ) + 8004a4c: 697b ldr r3, [r7, #20] + 8004a4e: 089b lsrs r3, r3, #2 + 8004a50: 3302 adds r3, #2 + 8004a52: 693a ldr r2, [r7, #16] + 8004a54: f841 2023 str.w r2, [r1, r3, lsl #2] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR; - 80049bc: 4b38 ldr r3, [pc, #224] @ (8004aa0 ) - 80049be: 689b ldr r3, [r3, #8] - 80049c0: 613b str r3, [r7, #16] + 8004a58: 4b38 ldr r3, [pc, #224] @ (8004b3c ) + 8004a5a: 689b ldr r3, [r3, #8] + 8004a5c: 613b str r3, [r7, #16] temp &= ~(iocurrent); - 80049c2: 68fb ldr r3, [r7, #12] - 80049c4: 43db mvns r3, r3 - 80049c6: 693a ldr r2, [r7, #16] - 80049c8: 4013 ands r3, r2 - 80049ca: 613b str r3, [r7, #16] + 8004a5e: 68fb ldr r3, [r7, #12] + 8004a60: 43db mvns r3, r3 + 8004a62: 693a ldr r2, [r7, #16] + 8004a64: 4013 ands r3, r2 + 8004a66: 613b str r3, [r7, #16] if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u) - 80049cc: 683b ldr r3, [r7, #0] - 80049ce: 685b ldr r3, [r3, #4] - 80049d0: f403 1380 and.w r3, r3, #1048576 @ 0x100000 - 80049d4: 2b00 cmp r3, #0 - 80049d6: d003 beq.n 80049e0 + 8004a68: 683b ldr r3, [r7, #0] + 8004a6a: 685b ldr r3, [r3, #4] + 8004a6c: f403 1380 and.w r3, r3, #1048576 @ 0x100000 + 8004a70: 2b00 cmp r3, #0 + 8004a72: d003 beq.n 8004a7c { temp |= iocurrent; - 80049d8: 693a ldr r2, [r7, #16] - 80049da: 68fb ldr r3, [r7, #12] - 80049dc: 4313 orrs r3, r2 - 80049de: 613b str r3, [r7, #16] + 8004a74: 693a ldr r2, [r7, #16] + 8004a76: 68fb ldr r3, [r7, #12] + 8004a78: 4313 orrs r3, r2 + 8004a7a: 613b str r3, [r7, #16] } EXTI->RTSR = temp; - 80049e0: 4a2f ldr r2, [pc, #188] @ (8004aa0 ) - 80049e2: 693b ldr r3, [r7, #16] - 80049e4: 6093 str r3, [r2, #8] + 8004a7c: 4a2f ldr r2, [pc, #188] @ (8004b3c ) + 8004a7e: 693b ldr r3, [r7, #16] + 8004a80: 6093 str r3, [r2, #8] temp = EXTI->FTSR; - 80049e6: 4b2e ldr r3, [pc, #184] @ (8004aa0 ) - 80049e8: 68db ldr r3, [r3, #12] - 80049ea: 613b str r3, [r7, #16] + 8004a82: 4b2e ldr r3, [pc, #184] @ (8004b3c ) + 8004a84: 68db ldr r3, [r3, #12] + 8004a86: 613b str r3, [r7, #16] temp &= ~(iocurrent); - 80049ec: 68fb ldr r3, [r7, #12] - 80049ee: 43db mvns r3, r3 - 80049f0: 693a ldr r2, [r7, #16] - 80049f2: 4013 ands r3, r2 - 80049f4: 613b str r3, [r7, #16] + 8004a88: 68fb ldr r3, [r7, #12] + 8004a8a: 43db mvns r3, r3 + 8004a8c: 693a ldr r2, [r7, #16] + 8004a8e: 4013 ands r3, r2 + 8004a90: 613b str r3, [r7, #16] if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u) - 80049f6: 683b ldr r3, [r7, #0] - 80049f8: 685b ldr r3, [r3, #4] - 80049fa: f403 1300 and.w r3, r3, #2097152 @ 0x200000 - 80049fe: 2b00 cmp r3, #0 - 8004a00: d003 beq.n 8004a0a + 8004a92: 683b ldr r3, [r7, #0] + 8004a94: 685b ldr r3, [r3, #4] + 8004a96: f403 1300 and.w r3, r3, #2097152 @ 0x200000 + 8004a9a: 2b00 cmp r3, #0 + 8004a9c: d003 beq.n 8004aa6 { temp |= iocurrent; - 8004a02: 693a ldr r2, [r7, #16] - 8004a04: 68fb ldr r3, [r7, #12] - 8004a06: 4313 orrs r3, r2 - 8004a08: 613b str r3, [r7, #16] + 8004a9e: 693a ldr r2, [r7, #16] + 8004aa0: 68fb ldr r3, [r7, #12] + 8004aa2: 4313 orrs r3, r2 + 8004aa4: 613b str r3, [r7, #16] } EXTI->FTSR = temp; - 8004a0a: 4a25 ldr r2, [pc, #148] @ (8004aa0 ) - 8004a0c: 693b ldr r3, [r7, #16] - 8004a0e: 60d3 str r3, [r2, #12] + 8004aa6: 4a25 ldr r2, [pc, #148] @ (8004b3c ) + 8004aa8: 693b ldr r3, [r7, #16] + 8004aaa: 60d3 str r3, [r2, #12] temp = EXTI->EMR; - 8004a10: 4b23 ldr r3, [pc, #140] @ (8004aa0 ) - 8004a12: 685b ldr r3, [r3, #4] - 8004a14: 613b str r3, [r7, #16] + 8004aac: 4b23 ldr r3, [pc, #140] @ (8004b3c ) + 8004aae: 685b ldr r3, [r3, #4] + 8004ab0: 613b str r3, [r7, #16] temp &= ~(iocurrent); - 8004a16: 68fb ldr r3, [r7, #12] - 8004a18: 43db mvns r3, r3 - 8004a1a: 693a ldr r2, [r7, #16] - 8004a1c: 4013 ands r3, r2 - 8004a1e: 613b str r3, [r7, #16] + 8004ab2: 68fb ldr r3, [r7, #12] + 8004ab4: 43db mvns r3, r3 + 8004ab6: 693a ldr r2, [r7, #16] + 8004ab8: 4013 ands r3, r2 + 8004aba: 613b str r3, [r7, #16] if((GPIO_Init->Mode & EXTI_EVT) != 0x00u) - 8004a20: 683b ldr r3, [r7, #0] - 8004a22: 685b ldr r3, [r3, #4] - 8004a24: f403 3300 and.w r3, r3, #131072 @ 0x20000 - 8004a28: 2b00 cmp r3, #0 - 8004a2a: d003 beq.n 8004a34 + 8004abc: 683b ldr r3, [r7, #0] + 8004abe: 685b ldr r3, [r3, #4] + 8004ac0: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 8004ac4: 2b00 cmp r3, #0 + 8004ac6: d003 beq.n 8004ad0 { temp |= iocurrent; - 8004a2c: 693a ldr r2, [r7, #16] - 8004a2e: 68fb ldr r3, [r7, #12] - 8004a30: 4313 orrs r3, r2 - 8004a32: 613b str r3, [r7, #16] + 8004ac8: 693a ldr r2, [r7, #16] + 8004aca: 68fb ldr r3, [r7, #12] + 8004acc: 4313 orrs r3, r2 + 8004ace: 613b str r3, [r7, #16] } EXTI->EMR = temp; - 8004a34: 4a1a ldr r2, [pc, #104] @ (8004aa0 ) - 8004a36: 693b ldr r3, [r7, #16] - 8004a38: 6053 str r3, [r2, #4] + 8004ad0: 4a1a ldr r2, [pc, #104] @ (8004b3c ) + 8004ad2: 693b ldr r3, [r7, #16] + 8004ad4: 6053 str r3, [r2, #4] /* Clear EXTI line configuration */ temp = EXTI->IMR; - 8004a3a: 4b19 ldr r3, [pc, #100] @ (8004aa0 ) - 8004a3c: 681b ldr r3, [r3, #0] - 8004a3e: 613b str r3, [r7, #16] + 8004ad6: 4b19 ldr r3, [pc, #100] @ (8004b3c ) + 8004ad8: 681b ldr r3, [r3, #0] + 8004ada: 613b str r3, [r7, #16] temp &= ~(iocurrent); - 8004a40: 68fb ldr r3, [r7, #12] - 8004a42: 43db mvns r3, r3 - 8004a44: 693a ldr r2, [r7, #16] - 8004a46: 4013 ands r3, r2 - 8004a48: 613b str r3, [r7, #16] + 8004adc: 68fb ldr r3, [r7, #12] + 8004ade: 43db mvns r3, r3 + 8004ae0: 693a ldr r2, [r7, #16] + 8004ae2: 4013 ands r3, r2 + 8004ae4: 613b str r3, [r7, #16] if((GPIO_Init->Mode & EXTI_IT) != 0x00u) - 8004a4a: 683b ldr r3, [r7, #0] - 8004a4c: 685b ldr r3, [r3, #4] - 8004a4e: f403 3380 and.w r3, r3, #65536 @ 0x10000 - 8004a52: 2b00 cmp r3, #0 - 8004a54: d003 beq.n 8004a5e + 8004ae6: 683b ldr r3, [r7, #0] + 8004ae8: 685b ldr r3, [r3, #4] + 8004aea: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 8004aee: 2b00 cmp r3, #0 + 8004af0: d003 beq.n 8004afa { temp |= iocurrent; - 8004a56: 693a ldr r2, [r7, #16] - 8004a58: 68fb ldr r3, [r7, #12] - 8004a5a: 4313 orrs r3, r2 - 8004a5c: 613b str r3, [r7, #16] + 8004af2: 693a ldr r2, [r7, #16] + 8004af4: 68fb ldr r3, [r7, #12] + 8004af6: 4313 orrs r3, r2 + 8004af8: 613b str r3, [r7, #16] } EXTI->IMR = temp; - 8004a5e: 4a10 ldr r2, [pc, #64] @ (8004aa0 ) - 8004a60: 693b ldr r3, [r7, #16] - 8004a62: 6013 str r3, [r2, #0] + 8004afa: 4a10 ldr r2, [pc, #64] @ (8004b3c ) + 8004afc: 693b ldr r3, [r7, #16] + 8004afe: 6013 str r3, [r2, #0] } } position++; - 8004a64: 697b ldr r3, [r7, #20] - 8004a66: 3301 adds r3, #1 - 8004a68: 617b str r3, [r7, #20] + 8004b00: 697b ldr r3, [r7, #20] + 8004b02: 3301 adds r3, #1 + 8004b04: 617b str r3, [r7, #20] while (((GPIO_Init->Pin) >> position) != 0x00u) - 8004a6a: 683b ldr r3, [r7, #0] - 8004a6c: 681a ldr r2, [r3, #0] - 8004a6e: 697b ldr r3, [r7, #20] - 8004a70: fa22 f303 lsr.w r3, r2, r3 - 8004a74: 2b00 cmp r3, #0 - 8004a76: f47f aea3 bne.w 80047c0 + 8004b06: 683b ldr r3, [r7, #0] + 8004b08: 681a ldr r2, [r3, #0] + 8004b0a: 697b ldr r3, [r7, #20] + 8004b0c: fa22 f303 lsr.w r3, r2, r3 + 8004b10: 2b00 cmp r3, #0 + 8004b12: f47f aea3 bne.w 800485c } } - 8004a7a: bf00 nop - 8004a7c: bf00 nop - 8004a7e: 371c adds r7, #28 - 8004a80: 46bd mov sp, r7 - 8004a82: f85d 7b04 ldr.w r7, [sp], #4 - 8004a86: 4770 bx lr - 8004a88: 40021000 .word 0x40021000 - 8004a8c: 40010000 .word 0x40010000 - 8004a90: 48000400 .word 0x48000400 - 8004a94: 48000800 .word 0x48000800 - 8004a98: 48000c00 .word 0x48000c00 - 8004a9c: 48001000 .word 0x48001000 - 8004aa0: 40010400 .word 0x40010400 + 8004b16: bf00 nop + 8004b18: bf00 nop + 8004b1a: 371c adds r7, #28 + 8004b1c: 46bd mov sp, r7 + 8004b1e: f85d 7b04 ldr.w r7, [sp], #4 + 8004b22: 4770 bx lr + 8004b24: 40021000 .word 0x40021000 + 8004b28: 40010000 .word 0x40010000 + 8004b2c: 48000400 .word 0x48000400 + 8004b30: 48000800 .word 0x48000800 + 8004b34: 48000c00 .word 0x48000c00 + 8004b38: 48001000 .word 0x48001000 + 8004b3c: 40010400 .word 0x40010400 -08004aa4 : +08004b40 : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { - 8004aa4: b480 push {r7} - 8004aa6: b083 sub sp, #12 - 8004aa8: af00 add r7, sp, #0 - 8004aaa: 6078 str r0, [r7, #4] - 8004aac: 460b mov r3, r1 - 8004aae: 807b strh r3, [r7, #2] - 8004ab0: 4613 mov r3, r2 - 8004ab2: 707b strb r3, [r7, #1] + 8004b40: b480 push {r7} + 8004b42: b083 sub sp, #12 + 8004b44: af00 add r7, sp, #0 + 8004b46: 6078 str r0, [r7, #4] + 8004b48: 460b mov r3, r1 + 8004b4a: 807b strh r3, [r7, #2] + 8004b4c: 4613 mov r3, r2 + 8004b4e: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if(PinState != GPIO_PIN_RESET) - 8004ab4: 787b ldrb r3, [r7, #1] - 8004ab6: 2b00 cmp r3, #0 - 8004ab8: d003 beq.n 8004ac2 + 8004b50: 787b ldrb r3, [r7, #1] + 8004b52: 2b00 cmp r3, #0 + 8004b54: d003 beq.n 8004b5e { GPIOx->BSRR = (uint32_t)GPIO_Pin; - 8004aba: 887a ldrh r2, [r7, #2] - 8004abc: 687b ldr r3, [r7, #4] - 8004abe: 619a str r2, [r3, #24] + 8004b56: 887a ldrh r2, [r7, #2] + 8004b58: 687b ldr r3, [r7, #4] + 8004b5a: 619a str r2, [r3, #24] } else { GPIOx->BRR = (uint32_t)GPIO_Pin; } } - 8004ac0: e002 b.n 8004ac8 + 8004b5c: e002 b.n 8004b64 GPIOx->BRR = (uint32_t)GPIO_Pin; - 8004ac2: 887a ldrh r2, [r7, #2] - 8004ac4: 687b ldr r3, [r7, #4] - 8004ac6: 629a str r2, [r3, #40] @ 0x28 + 8004b5e: 887a ldrh r2, [r7, #2] + 8004b60: 687b ldr r3, [r7, #4] + 8004b62: 629a str r2, [r3, #40] @ 0x28 } - 8004ac8: bf00 nop - 8004aca: 370c adds r7, #12 - 8004acc: 46bd mov sp, r7 - 8004ace: f85d 7b04 ldr.w r7, [sp], #4 - 8004ad2: 4770 bx lr + 8004b64: bf00 nop + 8004b66: 370c adds r7, #12 + 8004b68: 46bd mov sp, r7 + 8004b6a: f85d 7b04 ldr.w r7, [sp], #4 + 8004b6e: 4770 bx lr -08004ad4 : +08004b70 : * supported by this macro. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { - 8004ad4: b580 push {r7, lr} - 8004ad6: f5ad 7d00 sub.w sp, sp, #512 @ 0x200 - 8004ada: af00 add r7, sp, #0 - 8004adc: f507 7300 add.w r3, r7, #512 @ 0x200 - 8004ae0: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc - 8004ae4: 6018 str r0, [r3, #0] + 8004b70: b580 push {r7, lr} + 8004b72: f5ad 7d00 sub.w sp, sp, #512 @ 0x200 + 8004b76: af00 add r7, sp, #0 + 8004b78: f507 7300 add.w r3, r7, #512 @ 0x200 + 8004b7c: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc + 8004b80: 6018 str r0, [r3, #0] #if defined(RCC_CFGR_PLLSRC_HSI_PREDIV) uint32_t pll_config2; #endif /* RCC_CFGR_PLLSRC_HSI_PREDIV */ /* Check Null pointer */ if(RCC_OscInitStruct == NULL) - 8004ae6: f507 7300 add.w r3, r7, #512 @ 0x200 - 8004aea: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc - 8004aee: 681b ldr r3, [r3, #0] - 8004af0: 2b00 cmp r3, #0 - 8004af2: d102 bne.n 8004afa + 8004b82: f507 7300 add.w r3, r7, #512 @ 0x200 + 8004b86: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc + 8004b8a: 681b ldr r3, [r3, #0] + 8004b8c: 2b00 cmp r3, #0 + 8004b8e: d102 bne.n 8004b96 { return HAL_ERROR; - 8004af4: 2301 movs r3, #1 - 8004af6: f001 b823 b.w 8005b40 + 8004b90: 2301 movs r3, #1 + 8004b92: f001 b823 b.w 8005bdc /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) - 8004afa: f507 7300 add.w r3, r7, #512 @ 0x200 - 8004afe: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc - 8004b02: 681b ldr r3, [r3, #0] - 8004b04: 681b ldr r3, [r3, #0] - 8004b06: f003 0301 and.w r3, r3, #1 - 8004b0a: 2b00 cmp r3, #0 - 8004b0c: f000 817d beq.w 8004e0a + 8004b96: f507 7300 add.w r3, r7, #512 @ 0x200 + 8004b9a: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc + 8004b9e: 681b ldr r3, [r3, #0] + 8004ba0: 681b ldr r3, [r3, #0] + 8004ba2: f003 0301 and.w r3, r3, #1 + 8004ba6: 2b00 cmp r3, #0 + 8004ba8: f000 817d beq.w 8004ea6 { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) - 8004b10: 4bbc ldr r3, [pc, #752] @ (8004e04 ) - 8004b12: 685b ldr r3, [r3, #4] - 8004b14: f003 030c and.w r3, r3, #12 - 8004b18: 2b04 cmp r3, #4 - 8004b1a: d00c beq.n 8004b36 + 8004bac: 4bbc ldr r3, [pc, #752] @ (8004ea0 ) + 8004bae: 685b ldr r3, [r3, #4] + 8004bb0: f003 030c and.w r3, r3, #12 + 8004bb4: 2b04 cmp r3, #4 + 8004bb6: d00c beq.n 8004bd2 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) - 8004b1c: 4bb9 ldr r3, [pc, #740] @ (8004e04 ) - 8004b1e: 685b ldr r3, [r3, #4] - 8004b20: f003 030c and.w r3, r3, #12 - 8004b24: 2b08 cmp r3, #8 - 8004b26: d15c bne.n 8004be2 - 8004b28: 4bb6 ldr r3, [pc, #728] @ (8004e04 ) - 8004b2a: 685b ldr r3, [r3, #4] - 8004b2c: f403 3380 and.w r3, r3, #65536 @ 0x10000 - 8004b30: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 - 8004b34: d155 bne.n 8004be2 - 8004b36: f44f 3300 mov.w r3, #131072 @ 0x20000 - 8004b3a: f8c7 31f0 str.w r3, [r7, #496] @ 0x1f0 + 8004bb8: 4bb9 ldr r3, [pc, #740] @ (8004ea0 ) + 8004bba: 685b ldr r3, [r3, #4] + 8004bbc: f003 030c and.w r3, r3, #12 + 8004bc0: 2b08 cmp r3, #8 + 8004bc2: d15c bne.n 8004c7e + 8004bc4: 4bb6 ldr r3, [pc, #728] @ (8004ea0 ) + 8004bc6: 685b ldr r3, [r3, #4] + 8004bc8: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 8004bcc: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 + 8004bd0: d155 bne.n 8004c7e + 8004bd2: f44f 3300 mov.w r3, #131072 @ 0x20000 + 8004bd6: f8c7 31f0 str.w r3, [r7, #496] @ 0x1f0 uint32_t result; #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8004b3e: f8d7 31f0 ldr.w r3, [r7, #496] @ 0x1f0 - 8004b42: fa93 f3a3 rbit r3, r3 - 8004b46: f8c7 31ec str.w r3, [r7, #492] @ 0x1ec + 8004bda: f8d7 31f0 ldr.w r3, [r7, #496] @ 0x1f0 + 8004bde: fa93 f3a3 rbit r3, r3 + 8004be2: f8c7 31ec str.w r3, [r7, #492] @ 0x1ec result |= value & 1U; s--; } result <<= s; /* shift when v's highest bits are zero */ #endif return result; - 8004b4a: f8d7 31ec ldr.w r3, [r7, #492] @ 0x1ec + 8004be6: f8d7 31ec ldr.w r3, [r7, #492] @ 0x1ec { if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) - 8004b4e: fab3 f383 clz r3, r3 - 8004b52: b2db uxtb r3, r3 - 8004b54: 095b lsrs r3, r3, #5 - 8004b56: b2db uxtb r3, r3 - 8004b58: f043 0301 orr.w r3, r3, #1 - 8004b5c: b2db uxtb r3, r3 - 8004b5e: 2b01 cmp r3, #1 - 8004b60: d102 bne.n 8004b68 - 8004b62: 4ba8 ldr r3, [pc, #672] @ (8004e04 ) - 8004b64: 681b ldr r3, [r3, #0] - 8004b66: e015 b.n 8004b94 - 8004b68: f44f 3300 mov.w r3, #131072 @ 0x20000 - 8004b6c: f8c7 31e8 str.w r3, [r7, #488] @ 0x1e8 + 8004bea: fab3 f383 clz r3, r3 + 8004bee: b2db uxtb r3, r3 + 8004bf0: 095b lsrs r3, r3, #5 + 8004bf2: b2db uxtb r3, r3 + 8004bf4: f043 0301 orr.w r3, r3, #1 + 8004bf8: b2db uxtb r3, r3 + 8004bfa: 2b01 cmp r3, #1 + 8004bfc: d102 bne.n 8004c04 + 8004bfe: 4ba8 ldr r3, [pc, #672] @ (8004ea0 ) + 8004c00: 681b ldr r3, [r3, #0] + 8004c02: e015 b.n 8004c30 + 8004c04: f44f 3300 mov.w r3, #131072 @ 0x20000 + 8004c08: f8c7 31e8 str.w r3, [r7, #488] @ 0x1e8 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8004b70: f8d7 31e8 ldr.w r3, [r7, #488] @ 0x1e8 - 8004b74: fa93 f3a3 rbit r3, r3 - 8004b78: f8c7 31e4 str.w r3, [r7, #484] @ 0x1e4 - 8004b7c: f44f 3300 mov.w r3, #131072 @ 0x20000 - 8004b80: f8c7 31e0 str.w r3, [r7, #480] @ 0x1e0 - 8004b84: f8d7 31e0 ldr.w r3, [r7, #480] @ 0x1e0 - 8004b88: fa93 f3a3 rbit r3, r3 - 8004b8c: f8c7 31dc str.w r3, [r7, #476] @ 0x1dc - 8004b90: 4b9c ldr r3, [pc, #624] @ (8004e04 ) - 8004b92: 6a5b ldr r3, [r3, #36] @ 0x24 - 8004b94: f44f 3200 mov.w r2, #131072 @ 0x20000 - 8004b98: f8c7 21d8 str.w r2, [r7, #472] @ 0x1d8 - 8004b9c: f8d7 21d8 ldr.w r2, [r7, #472] @ 0x1d8 - 8004ba0: fa92 f2a2 rbit r2, r2 - 8004ba4: f8c7 21d4 str.w r2, [r7, #468] @ 0x1d4 + 8004c0c: f8d7 31e8 ldr.w r3, [r7, #488] @ 0x1e8 + 8004c10: fa93 f3a3 rbit r3, r3 + 8004c14: f8c7 31e4 str.w r3, [r7, #484] @ 0x1e4 + 8004c18: f44f 3300 mov.w r3, #131072 @ 0x20000 + 8004c1c: f8c7 31e0 str.w r3, [r7, #480] @ 0x1e0 + 8004c20: f8d7 31e0 ldr.w r3, [r7, #480] @ 0x1e0 + 8004c24: fa93 f3a3 rbit r3, r3 + 8004c28: f8c7 31dc str.w r3, [r7, #476] @ 0x1dc + 8004c2c: 4b9c ldr r3, [pc, #624] @ (8004ea0 ) + 8004c2e: 6a5b ldr r3, [r3, #36] @ 0x24 + 8004c30: f44f 3200 mov.w r2, #131072 @ 0x20000 + 8004c34: f8c7 21d8 str.w r2, [r7, #472] @ 0x1d8 + 8004c38: f8d7 21d8 ldr.w r2, [r7, #472] @ 0x1d8 + 8004c3c: fa92 f2a2 rbit r2, r2 + 8004c40: f8c7 21d4 str.w r2, [r7, #468] @ 0x1d4 return result; - 8004ba8: f8d7 21d4 ldr.w r2, [r7, #468] @ 0x1d4 - 8004bac: fab2 f282 clz r2, r2 - 8004bb0: b2d2 uxtb r2, r2 - 8004bb2: f042 0220 orr.w r2, r2, #32 - 8004bb6: b2d2 uxtb r2, r2 - 8004bb8: f002 021f and.w r2, r2, #31 - 8004bbc: 2101 movs r1, #1 - 8004bbe: fa01 f202 lsl.w r2, r1, r2 - 8004bc2: 4013 ands r3, r2 - 8004bc4: 2b00 cmp r3, #0 - 8004bc6: f000 811f beq.w 8004e08 - 8004bca: f507 7300 add.w r3, r7, #512 @ 0x200 - 8004bce: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc - 8004bd2: 681b ldr r3, [r3, #0] - 8004bd4: 685b ldr r3, [r3, #4] - 8004bd6: 2b00 cmp r3, #0 - 8004bd8: f040 8116 bne.w 8004e08 + 8004c44: f8d7 21d4 ldr.w r2, [r7, #468] @ 0x1d4 + 8004c48: fab2 f282 clz r2, r2 + 8004c4c: b2d2 uxtb r2, r2 + 8004c4e: f042 0220 orr.w r2, r2, #32 + 8004c52: b2d2 uxtb r2, r2 + 8004c54: f002 021f and.w r2, r2, #31 + 8004c58: 2101 movs r1, #1 + 8004c5a: fa01 f202 lsl.w r2, r1, r2 + 8004c5e: 4013 ands r3, r2 + 8004c60: 2b00 cmp r3, #0 + 8004c62: f000 811f beq.w 8004ea4 + 8004c66: f507 7300 add.w r3, r7, #512 @ 0x200 + 8004c6a: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc + 8004c6e: 681b ldr r3, [r3, #0] + 8004c70: 685b ldr r3, [r3, #4] + 8004c72: 2b00 cmp r3, #0 + 8004c74: f040 8116 bne.w 8004ea4 { return HAL_ERROR; - 8004bdc: 2301 movs r3, #1 - 8004bde: f000 bfaf b.w 8005b40 + 8004c78: 2301 movs r3, #1 + 8004c7a: f000 bfaf b.w 8005bdc } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); - 8004be2: f507 7300 add.w r3, r7, #512 @ 0x200 - 8004be6: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc - 8004bea: 681b ldr r3, [r3, #0] - 8004bec: 685b ldr r3, [r3, #4] - 8004bee: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 - 8004bf2: d106 bne.n 8004c02 - 8004bf4: 4b83 ldr r3, [pc, #524] @ (8004e04 ) - 8004bf6: 681b ldr r3, [r3, #0] - 8004bf8: 4a82 ldr r2, [pc, #520] @ (8004e04 ) - 8004bfa: f443 3380 orr.w r3, r3, #65536 @ 0x10000 - 8004bfe: 6013 str r3, [r2, #0] - 8004c00: e036 b.n 8004c70 - 8004c02: f507 7300 add.w r3, r7, #512 @ 0x200 - 8004c06: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc - 8004c0a: 681b ldr r3, [r3, #0] - 8004c0c: 685b ldr r3, [r3, #4] - 8004c0e: 2b00 cmp r3, #0 - 8004c10: d10c bne.n 8004c2c - 8004c12: 4b7c ldr r3, [pc, #496] @ (8004e04 ) - 8004c14: 681b ldr r3, [r3, #0] - 8004c16: 4a7b ldr r2, [pc, #492] @ (8004e04 ) - 8004c18: f423 3380 bic.w r3, r3, #65536 @ 0x10000 - 8004c1c: 6013 str r3, [r2, #0] - 8004c1e: 4b79 ldr r3, [pc, #484] @ (8004e04 ) - 8004c20: 681b ldr r3, [r3, #0] - 8004c22: 4a78 ldr r2, [pc, #480] @ (8004e04 ) - 8004c24: f423 2380 bic.w r3, r3, #262144 @ 0x40000 - 8004c28: 6013 str r3, [r2, #0] - 8004c2a: e021 b.n 8004c70 - 8004c2c: f507 7300 add.w r3, r7, #512 @ 0x200 - 8004c30: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc - 8004c34: 681b ldr r3, [r3, #0] - 8004c36: 685b ldr r3, [r3, #4] - 8004c38: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 - 8004c3c: d10c bne.n 8004c58 - 8004c3e: 4b71 ldr r3, [pc, #452] @ (8004e04 ) - 8004c40: 681b ldr r3, [r3, #0] - 8004c42: 4a70 ldr r2, [pc, #448] @ (8004e04 ) - 8004c44: f443 2380 orr.w r3, r3, #262144 @ 0x40000 - 8004c48: 6013 str r3, [r2, #0] - 8004c4a: 4b6e ldr r3, [pc, #440] @ (8004e04 ) - 8004c4c: 681b ldr r3, [r3, #0] - 8004c4e: 4a6d ldr r2, [pc, #436] @ (8004e04 ) - 8004c50: f443 3380 orr.w r3, r3, #65536 @ 0x10000 - 8004c54: 6013 str r3, [r2, #0] - 8004c56: e00b b.n 8004c70 - 8004c58: 4b6a ldr r3, [pc, #424] @ (8004e04 ) - 8004c5a: 681b ldr r3, [r3, #0] - 8004c5c: 4a69 ldr r2, [pc, #420] @ (8004e04 ) - 8004c5e: f423 3380 bic.w r3, r3, #65536 @ 0x10000 - 8004c62: 6013 str r3, [r2, #0] - 8004c64: 4b67 ldr r3, [pc, #412] @ (8004e04 ) - 8004c66: 681b ldr r3, [r3, #0] - 8004c68: 4a66 ldr r2, [pc, #408] @ (8004e04 ) - 8004c6a: f423 2380 bic.w r3, r3, #262144 @ 0x40000 - 8004c6e: 6013 str r3, [r2, #0] + 8004c7e: f507 7300 add.w r3, r7, #512 @ 0x200 + 8004c82: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc + 8004c86: 681b ldr r3, [r3, #0] + 8004c88: 685b ldr r3, [r3, #4] + 8004c8a: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 + 8004c8e: d106 bne.n 8004c9e + 8004c90: 4b83 ldr r3, [pc, #524] @ (8004ea0 ) + 8004c92: 681b ldr r3, [r3, #0] + 8004c94: 4a82 ldr r2, [pc, #520] @ (8004ea0 ) + 8004c96: f443 3380 orr.w r3, r3, #65536 @ 0x10000 + 8004c9a: 6013 str r3, [r2, #0] + 8004c9c: e036 b.n 8004d0c + 8004c9e: f507 7300 add.w r3, r7, #512 @ 0x200 + 8004ca2: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc + 8004ca6: 681b ldr r3, [r3, #0] + 8004ca8: 685b ldr r3, [r3, #4] + 8004caa: 2b00 cmp r3, #0 + 8004cac: d10c bne.n 8004cc8 + 8004cae: 4b7c ldr r3, [pc, #496] @ (8004ea0 ) + 8004cb0: 681b ldr r3, [r3, #0] + 8004cb2: 4a7b ldr r2, [pc, #492] @ (8004ea0 ) + 8004cb4: f423 3380 bic.w r3, r3, #65536 @ 0x10000 + 8004cb8: 6013 str r3, [r2, #0] + 8004cba: 4b79 ldr r3, [pc, #484] @ (8004ea0 ) + 8004cbc: 681b ldr r3, [r3, #0] + 8004cbe: 4a78 ldr r2, [pc, #480] @ (8004ea0 ) + 8004cc0: f423 2380 bic.w r3, r3, #262144 @ 0x40000 + 8004cc4: 6013 str r3, [r2, #0] + 8004cc6: e021 b.n 8004d0c + 8004cc8: f507 7300 add.w r3, r7, #512 @ 0x200 + 8004ccc: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc + 8004cd0: 681b ldr r3, [r3, #0] + 8004cd2: 685b ldr r3, [r3, #4] + 8004cd4: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 + 8004cd8: d10c bne.n 8004cf4 + 8004cda: 4b71 ldr r3, [pc, #452] @ (8004ea0 ) + 8004cdc: 681b ldr r3, [r3, #0] + 8004cde: 4a70 ldr r2, [pc, #448] @ (8004ea0 ) + 8004ce0: f443 2380 orr.w r3, r3, #262144 @ 0x40000 + 8004ce4: 6013 str r3, [r2, #0] + 8004ce6: 4b6e ldr r3, [pc, #440] @ (8004ea0 ) + 8004ce8: 681b ldr r3, [r3, #0] + 8004cea: 4a6d ldr r2, [pc, #436] @ (8004ea0 ) + 8004cec: f443 3380 orr.w r3, r3, #65536 @ 0x10000 + 8004cf0: 6013 str r3, [r2, #0] + 8004cf2: e00b b.n 8004d0c + 8004cf4: 4b6a ldr r3, [pc, #424] @ (8004ea0 ) + 8004cf6: 681b ldr r3, [r3, #0] + 8004cf8: 4a69 ldr r2, [pc, #420] @ (8004ea0 ) + 8004cfa: f423 3380 bic.w r3, r3, #65536 @ 0x10000 + 8004cfe: 6013 str r3, [r2, #0] + 8004d00: 4b67 ldr r3, [pc, #412] @ (8004ea0 ) + 8004d02: 681b ldr r3, [r3, #0] + 8004d04: 4a66 ldr r2, [pc, #408] @ (8004ea0 ) + 8004d06: f423 2380 bic.w r3, r3, #262144 @ 0x40000 + 8004d0a: 6013 str r3, [r2, #0] #if defined(RCC_CFGR_PLLSRC_HSI_DIV2) /* Configure the HSE predivision factor --------------------------------*/ __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue); - 8004c70: 4b64 ldr r3, [pc, #400] @ (8004e04 ) - 8004c72: 6adb ldr r3, [r3, #44] @ 0x2c - 8004c74: f023 020f bic.w r2, r3, #15 - 8004c78: f507 7300 add.w r3, r7, #512 @ 0x200 - 8004c7c: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc - 8004c80: 681b ldr r3, [r3, #0] - 8004c82: 689b ldr r3, [r3, #8] - 8004c84: 495f ldr r1, [pc, #380] @ (8004e04 ) - 8004c86: 4313 orrs r3, r2 - 8004c88: 62cb str r3, [r1, #44] @ 0x2c + 8004d0c: 4b64 ldr r3, [pc, #400] @ (8004ea0 ) + 8004d0e: 6adb ldr r3, [r3, #44] @ 0x2c + 8004d10: f023 020f bic.w r2, r3, #15 + 8004d14: f507 7300 add.w r3, r7, #512 @ 0x200 + 8004d18: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc + 8004d1c: 681b ldr r3, [r3, #0] + 8004d1e: 689b ldr r3, [r3, #8] + 8004d20: 495f ldr r1, [pc, #380] @ (8004ea0 ) + 8004d22: 4313 orrs r3, r2 + 8004d24: 62cb str r3, [r1, #44] @ 0x2c #endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */ /* Check the HSE State */ if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) - 8004c8a: f507 7300 add.w r3, r7, #512 @ 0x200 - 8004c8e: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc - 8004c92: 681b ldr r3, [r3, #0] - 8004c94: 685b ldr r3, [r3, #4] - 8004c96: 2b00 cmp r3, #0 - 8004c98: d059 beq.n 8004d4e + 8004d26: f507 7300 add.w r3, r7, #512 @ 0x200 + 8004d2a: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc + 8004d2e: 681b ldr r3, [r3, #0] + 8004d30: 685b ldr r3, [r3, #4] + 8004d32: 2b00 cmp r3, #0 + 8004d34: d059 beq.n 8004dea { /* Get Start Tick */ tickstart = HAL_GetTick(); - 8004c9a: f7fd fae5 bl 8002268 - 8004c9e: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8 + 8004d36: f7fd fae5 bl 8002304 + 8004d3a: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8 /* Wait till HSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) - 8004ca2: e00a b.n 8004cba + 8004d3e: e00a b.n 8004d56 { if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) - 8004ca4: f7fd fae0 bl 8002268 - 8004ca8: 4602 mov r2, r0 - 8004caa: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8 - 8004cae: 1ad3 subs r3, r2, r3 - 8004cb0: 2b64 cmp r3, #100 @ 0x64 - 8004cb2: d902 bls.n 8004cba + 8004d40: f7fd fae0 bl 8002304 + 8004d44: 4602 mov r2, r0 + 8004d46: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8 + 8004d4a: 1ad3 subs r3, r2, r3 + 8004d4c: 2b64 cmp r3, #100 @ 0x64 + 8004d4e: d902 bls.n 8004d56 { return HAL_TIMEOUT; - 8004cb4: 2303 movs r3, #3 - 8004cb6: f000 bf43 b.w 8005b40 - 8004cba: f44f 3300 mov.w r3, #131072 @ 0x20000 - 8004cbe: f8c7 31d0 str.w r3, [r7, #464] @ 0x1d0 + 8004d50: 2303 movs r3, #3 + 8004d52: f000 bf43 b.w 8005bdc + 8004d56: f44f 3300 mov.w r3, #131072 @ 0x20000 + 8004d5a: f8c7 31d0 str.w r3, [r7, #464] @ 0x1d0 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8004cc2: f8d7 31d0 ldr.w r3, [r7, #464] @ 0x1d0 - 8004cc6: fa93 f3a3 rbit r3, r3 - 8004cca: f8c7 31cc str.w r3, [r7, #460] @ 0x1cc + 8004d5e: f8d7 31d0 ldr.w r3, [r7, #464] @ 0x1d0 + 8004d62: fa93 f3a3 rbit r3, r3 + 8004d66: f8c7 31cc str.w r3, [r7, #460] @ 0x1cc return result; - 8004cce: f8d7 31cc ldr.w r3, [r7, #460] @ 0x1cc + 8004d6a: f8d7 31cc ldr.w r3, [r7, #460] @ 0x1cc while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) - 8004cd2: fab3 f383 clz r3, r3 - 8004cd6: b2db uxtb r3, r3 - 8004cd8: 095b lsrs r3, r3, #5 - 8004cda: b2db uxtb r3, r3 - 8004cdc: f043 0301 orr.w r3, r3, #1 - 8004ce0: b2db uxtb r3, r3 - 8004ce2: 2b01 cmp r3, #1 - 8004ce4: d102 bne.n 8004cec - 8004ce6: 4b47 ldr r3, [pc, #284] @ (8004e04 ) - 8004ce8: 681b ldr r3, [r3, #0] - 8004cea: e015 b.n 8004d18 - 8004cec: f44f 3300 mov.w r3, #131072 @ 0x20000 - 8004cf0: f8c7 31c8 str.w r3, [r7, #456] @ 0x1c8 + 8004d6e: fab3 f383 clz r3, r3 + 8004d72: b2db uxtb r3, r3 + 8004d74: 095b lsrs r3, r3, #5 + 8004d76: b2db uxtb r3, r3 + 8004d78: f043 0301 orr.w r3, r3, #1 + 8004d7c: b2db uxtb r3, r3 + 8004d7e: 2b01 cmp r3, #1 + 8004d80: d102 bne.n 8004d88 + 8004d82: 4b47 ldr r3, [pc, #284] @ (8004ea0 ) + 8004d84: 681b ldr r3, [r3, #0] + 8004d86: e015 b.n 8004db4 + 8004d88: f44f 3300 mov.w r3, #131072 @ 0x20000 + 8004d8c: f8c7 31c8 str.w r3, [r7, #456] @ 0x1c8 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8004cf4: f8d7 31c8 ldr.w r3, [r7, #456] @ 0x1c8 - 8004cf8: fa93 f3a3 rbit r3, r3 - 8004cfc: f8c7 31c4 str.w r3, [r7, #452] @ 0x1c4 - 8004d00: f44f 3300 mov.w r3, #131072 @ 0x20000 - 8004d04: f8c7 31c0 str.w r3, [r7, #448] @ 0x1c0 - 8004d08: f8d7 31c0 ldr.w r3, [r7, #448] @ 0x1c0 - 8004d0c: fa93 f3a3 rbit r3, r3 - 8004d10: f8c7 31bc str.w r3, [r7, #444] @ 0x1bc - 8004d14: 4b3b ldr r3, [pc, #236] @ (8004e04 ) - 8004d16: 6a5b ldr r3, [r3, #36] @ 0x24 - 8004d18: f44f 3200 mov.w r2, #131072 @ 0x20000 - 8004d1c: f8c7 21b8 str.w r2, [r7, #440] @ 0x1b8 - 8004d20: f8d7 21b8 ldr.w r2, [r7, #440] @ 0x1b8 - 8004d24: fa92 f2a2 rbit r2, r2 - 8004d28: f8c7 21b4 str.w r2, [r7, #436] @ 0x1b4 + 8004d90: f8d7 31c8 ldr.w r3, [r7, #456] @ 0x1c8 + 8004d94: fa93 f3a3 rbit r3, r3 + 8004d98: f8c7 31c4 str.w r3, [r7, #452] @ 0x1c4 + 8004d9c: f44f 3300 mov.w r3, #131072 @ 0x20000 + 8004da0: f8c7 31c0 str.w r3, [r7, #448] @ 0x1c0 + 8004da4: f8d7 31c0 ldr.w r3, [r7, #448] @ 0x1c0 + 8004da8: fa93 f3a3 rbit r3, r3 + 8004dac: f8c7 31bc str.w r3, [r7, #444] @ 0x1bc + 8004db0: 4b3b ldr r3, [pc, #236] @ (8004ea0 ) + 8004db2: 6a5b ldr r3, [r3, #36] @ 0x24 + 8004db4: f44f 3200 mov.w r2, #131072 @ 0x20000 + 8004db8: f8c7 21b8 str.w r2, [r7, #440] @ 0x1b8 + 8004dbc: f8d7 21b8 ldr.w r2, [r7, #440] @ 0x1b8 + 8004dc0: fa92 f2a2 rbit r2, r2 + 8004dc4: f8c7 21b4 str.w r2, [r7, #436] @ 0x1b4 return result; - 8004d2c: f8d7 21b4 ldr.w r2, [r7, #436] @ 0x1b4 - 8004d30: fab2 f282 clz r2, r2 - 8004d34: b2d2 uxtb r2, r2 - 8004d36: f042 0220 orr.w r2, r2, #32 - 8004d3a: b2d2 uxtb r2, r2 - 8004d3c: f002 021f and.w r2, r2, #31 - 8004d40: 2101 movs r1, #1 - 8004d42: fa01 f202 lsl.w r2, r1, r2 - 8004d46: 4013 ands r3, r2 - 8004d48: 2b00 cmp r3, #0 - 8004d4a: d0ab beq.n 8004ca4 - 8004d4c: e05d b.n 8004e0a + 8004dc8: f8d7 21b4 ldr.w r2, [r7, #436] @ 0x1b4 + 8004dcc: fab2 f282 clz r2, r2 + 8004dd0: b2d2 uxtb r2, r2 + 8004dd2: f042 0220 orr.w r2, r2, #32 + 8004dd6: b2d2 uxtb r2, r2 + 8004dd8: f002 021f and.w r2, r2, #31 + 8004ddc: 2101 movs r1, #1 + 8004dde: fa01 f202 lsl.w r2, r1, r2 + 8004de2: 4013 ands r3, r2 + 8004de4: 2b00 cmp r3, #0 + 8004de6: d0ab beq.n 8004d40 + 8004de8: e05d b.n 8004ea6 } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); - 8004d4e: f7fd fa8b bl 8002268 - 8004d52: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8 + 8004dea: f7fd fa8b bl 8002304 + 8004dee: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8 /* Wait till HSE is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) - 8004d56: e00a b.n 8004d6e + 8004df2: e00a b.n 8004e0a { if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) - 8004d58: f7fd fa86 bl 8002268 - 8004d5c: 4602 mov r2, r0 - 8004d5e: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8 - 8004d62: 1ad3 subs r3, r2, r3 - 8004d64: 2b64 cmp r3, #100 @ 0x64 - 8004d66: d902 bls.n 8004d6e + 8004df4: f7fd fa86 bl 8002304 + 8004df8: 4602 mov r2, r0 + 8004dfa: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8 + 8004dfe: 1ad3 subs r3, r2, r3 + 8004e00: 2b64 cmp r3, #100 @ 0x64 + 8004e02: d902 bls.n 8004e0a { return HAL_TIMEOUT; - 8004d68: 2303 movs r3, #3 - 8004d6a: f000 bee9 b.w 8005b40 - 8004d6e: f44f 3300 mov.w r3, #131072 @ 0x20000 - 8004d72: f8c7 31b0 str.w r3, [r7, #432] @ 0x1b0 + 8004e04: 2303 movs r3, #3 + 8004e06: f000 bee9 b.w 8005bdc + 8004e0a: f44f 3300 mov.w r3, #131072 @ 0x20000 + 8004e0e: f8c7 31b0 str.w r3, [r7, #432] @ 0x1b0 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8004d76: f8d7 31b0 ldr.w r3, [r7, #432] @ 0x1b0 - 8004d7a: fa93 f3a3 rbit r3, r3 - 8004d7e: f8c7 31ac str.w r3, [r7, #428] @ 0x1ac + 8004e12: f8d7 31b0 ldr.w r3, [r7, #432] @ 0x1b0 + 8004e16: fa93 f3a3 rbit r3, r3 + 8004e1a: f8c7 31ac str.w r3, [r7, #428] @ 0x1ac return result; - 8004d82: f8d7 31ac ldr.w r3, [r7, #428] @ 0x1ac + 8004e1e: f8d7 31ac ldr.w r3, [r7, #428] @ 0x1ac while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) - 8004d86: fab3 f383 clz r3, r3 - 8004d8a: b2db uxtb r3, r3 - 8004d8c: 095b lsrs r3, r3, #5 - 8004d8e: b2db uxtb r3, r3 - 8004d90: f043 0301 orr.w r3, r3, #1 - 8004d94: b2db uxtb r3, r3 - 8004d96: 2b01 cmp r3, #1 - 8004d98: d102 bne.n 8004da0 - 8004d9a: 4b1a ldr r3, [pc, #104] @ (8004e04 ) - 8004d9c: 681b ldr r3, [r3, #0] - 8004d9e: e015 b.n 8004dcc - 8004da0: f44f 3300 mov.w r3, #131072 @ 0x20000 - 8004da4: f8c7 31a8 str.w r3, [r7, #424] @ 0x1a8 + 8004e22: fab3 f383 clz r3, r3 + 8004e26: b2db uxtb r3, r3 + 8004e28: 095b lsrs r3, r3, #5 + 8004e2a: b2db uxtb r3, r3 + 8004e2c: f043 0301 orr.w r3, r3, #1 + 8004e30: b2db uxtb r3, r3 + 8004e32: 2b01 cmp r3, #1 + 8004e34: d102 bne.n 8004e3c + 8004e36: 4b1a ldr r3, [pc, #104] @ (8004ea0 ) + 8004e38: 681b ldr r3, [r3, #0] + 8004e3a: e015 b.n 8004e68 + 8004e3c: f44f 3300 mov.w r3, #131072 @ 0x20000 + 8004e40: f8c7 31a8 str.w r3, [r7, #424] @ 0x1a8 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8004da8: f8d7 31a8 ldr.w r3, [r7, #424] @ 0x1a8 - 8004dac: fa93 f3a3 rbit r3, r3 - 8004db0: f8c7 31a4 str.w r3, [r7, #420] @ 0x1a4 - 8004db4: f44f 3300 mov.w r3, #131072 @ 0x20000 - 8004db8: f8c7 31a0 str.w r3, [r7, #416] @ 0x1a0 - 8004dbc: f8d7 31a0 ldr.w r3, [r7, #416] @ 0x1a0 - 8004dc0: fa93 f3a3 rbit r3, r3 - 8004dc4: f8c7 319c str.w r3, [r7, #412] @ 0x19c - 8004dc8: 4b0e ldr r3, [pc, #56] @ (8004e04 ) - 8004dca: 6a5b ldr r3, [r3, #36] @ 0x24 - 8004dcc: f44f 3200 mov.w r2, #131072 @ 0x20000 - 8004dd0: f8c7 2198 str.w r2, [r7, #408] @ 0x198 - 8004dd4: f8d7 2198 ldr.w r2, [r7, #408] @ 0x198 - 8004dd8: fa92 f2a2 rbit r2, r2 - 8004ddc: f8c7 2194 str.w r2, [r7, #404] @ 0x194 + 8004e44: f8d7 31a8 ldr.w r3, [r7, #424] @ 0x1a8 + 8004e48: fa93 f3a3 rbit r3, r3 + 8004e4c: f8c7 31a4 str.w r3, [r7, #420] @ 0x1a4 + 8004e50: f44f 3300 mov.w r3, #131072 @ 0x20000 + 8004e54: f8c7 31a0 str.w r3, [r7, #416] @ 0x1a0 + 8004e58: f8d7 31a0 ldr.w r3, [r7, #416] @ 0x1a0 + 8004e5c: fa93 f3a3 rbit r3, r3 + 8004e60: f8c7 319c str.w r3, [r7, #412] @ 0x19c + 8004e64: 4b0e ldr r3, [pc, #56] @ (8004ea0 ) + 8004e66: 6a5b ldr r3, [r3, #36] @ 0x24 + 8004e68: f44f 3200 mov.w r2, #131072 @ 0x20000 + 8004e6c: f8c7 2198 str.w r2, [r7, #408] @ 0x198 + 8004e70: f8d7 2198 ldr.w r2, [r7, #408] @ 0x198 + 8004e74: fa92 f2a2 rbit r2, r2 + 8004e78: f8c7 2194 str.w r2, [r7, #404] @ 0x194 return result; - 8004de0: f8d7 2194 ldr.w r2, [r7, #404] @ 0x194 - 8004de4: fab2 f282 clz r2, r2 - 8004de8: b2d2 uxtb r2, r2 - 8004dea: f042 0220 orr.w r2, r2, #32 - 8004dee: b2d2 uxtb r2, r2 - 8004df0: f002 021f and.w r2, r2, #31 - 8004df4: 2101 movs r1, #1 - 8004df6: fa01 f202 lsl.w r2, r1, r2 - 8004dfa: 4013 ands r3, r2 - 8004dfc: 2b00 cmp r3, #0 - 8004dfe: d1ab bne.n 8004d58 - 8004e00: e003 b.n 8004e0a - 8004e02: bf00 nop - 8004e04: 40021000 .word 0x40021000 + 8004e7c: f8d7 2194 ldr.w r2, [r7, #404] @ 0x194 + 8004e80: fab2 f282 clz r2, r2 + 8004e84: b2d2 uxtb r2, r2 + 8004e86: f042 0220 orr.w r2, r2, #32 + 8004e8a: b2d2 uxtb r2, r2 + 8004e8c: f002 021f and.w r2, r2, #31 + 8004e90: 2101 movs r1, #1 + 8004e92: fa01 f202 lsl.w r2, r1, r2 + 8004e96: 4013 ands r3, r2 + 8004e98: 2b00 cmp r3, #0 + 8004e9a: d1ab bne.n 8004df4 + 8004e9c: e003 b.n 8004ea6 + 8004e9e: bf00 nop + 8004ea0: 40021000 .word 0x40021000 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) - 8004e08: bf00 nop + 8004ea4: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) - 8004e0a: f507 7300 add.w r3, r7, #512 @ 0x200 - 8004e0e: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc - 8004e12: 681b ldr r3, [r3, #0] - 8004e14: 681b ldr r3, [r3, #0] - 8004e16: f003 0302 and.w r3, r3, #2 - 8004e1a: 2b00 cmp r3, #0 - 8004e1c: f000 817d beq.w 800511a + 8004ea6: f507 7300 add.w r3, r7, #512 @ 0x200 + 8004eaa: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc + 8004eae: 681b ldr r3, [r3, #0] + 8004eb0: 681b ldr r3, [r3, #0] + 8004eb2: f003 0302 and.w r3, r3, #2 + 8004eb6: 2b00 cmp r3, #0 + 8004eb8: f000 817d beq.w 80051b6 /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) - 8004e20: 4ba6 ldr r3, [pc, #664] @ (80050bc ) - 8004e22: 685b ldr r3, [r3, #4] - 8004e24: f003 030c and.w r3, r3, #12 - 8004e28: 2b00 cmp r3, #0 - 8004e2a: d00b beq.n 8004e44 + 8004ebc: 4ba6 ldr r3, [pc, #664] @ (8005158 ) + 8004ebe: 685b ldr r3, [r3, #4] + 8004ec0: f003 030c and.w r3, r3, #12 + 8004ec4: 2b00 cmp r3, #0 + 8004ec6: d00b beq.n 8004ee0 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI))) - 8004e2c: 4ba3 ldr r3, [pc, #652] @ (80050bc ) - 8004e2e: 685b ldr r3, [r3, #4] - 8004e30: f003 030c and.w r3, r3, #12 - 8004e34: 2b08 cmp r3, #8 - 8004e36: d172 bne.n 8004f1e - 8004e38: 4ba0 ldr r3, [pc, #640] @ (80050bc ) - 8004e3a: 685b ldr r3, [r3, #4] - 8004e3c: f403 3380 and.w r3, r3, #65536 @ 0x10000 - 8004e40: 2b00 cmp r3, #0 - 8004e42: d16c bne.n 8004f1e - 8004e44: 2302 movs r3, #2 - 8004e46: f8c7 3190 str.w r3, [r7, #400] @ 0x190 + 8004ec8: 4ba3 ldr r3, [pc, #652] @ (8005158 ) + 8004eca: 685b ldr r3, [r3, #4] + 8004ecc: f003 030c and.w r3, r3, #12 + 8004ed0: 2b08 cmp r3, #8 + 8004ed2: d172 bne.n 8004fba + 8004ed4: 4ba0 ldr r3, [pc, #640] @ (8005158 ) + 8004ed6: 685b ldr r3, [r3, #4] + 8004ed8: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 8004edc: 2b00 cmp r3, #0 + 8004ede: d16c bne.n 8004fba + 8004ee0: 2302 movs r3, #2 + 8004ee2: f8c7 3190 str.w r3, [r7, #400] @ 0x190 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8004e4a: f8d7 3190 ldr.w r3, [r7, #400] @ 0x190 - 8004e4e: fa93 f3a3 rbit r3, r3 - 8004e52: f8c7 318c str.w r3, [r7, #396] @ 0x18c + 8004ee6: f8d7 3190 ldr.w r3, [r7, #400] @ 0x190 + 8004eea: fa93 f3a3 rbit r3, r3 + 8004eee: f8c7 318c str.w r3, [r7, #396] @ 0x18c return result; - 8004e56: f8d7 318c ldr.w r3, [r7, #396] @ 0x18c + 8004ef2: f8d7 318c ldr.w r3, [r7, #396] @ 0x18c { /* When HSI is used as system clock it will not disabled */ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) - 8004e5a: fab3 f383 clz r3, r3 - 8004e5e: b2db uxtb r3, r3 - 8004e60: 095b lsrs r3, r3, #5 - 8004e62: b2db uxtb r3, r3 - 8004e64: f043 0301 orr.w r3, r3, #1 - 8004e68: b2db uxtb r3, r3 - 8004e6a: 2b01 cmp r3, #1 - 8004e6c: d102 bne.n 8004e74 - 8004e6e: 4b93 ldr r3, [pc, #588] @ (80050bc ) - 8004e70: 681b ldr r3, [r3, #0] - 8004e72: e013 b.n 8004e9c - 8004e74: 2302 movs r3, #2 - 8004e76: f8c7 3188 str.w r3, [r7, #392] @ 0x188 + 8004ef6: fab3 f383 clz r3, r3 + 8004efa: b2db uxtb r3, r3 + 8004efc: 095b lsrs r3, r3, #5 + 8004efe: b2db uxtb r3, r3 + 8004f00: f043 0301 orr.w r3, r3, #1 + 8004f04: b2db uxtb r3, r3 + 8004f06: 2b01 cmp r3, #1 + 8004f08: d102 bne.n 8004f10 + 8004f0a: 4b93 ldr r3, [pc, #588] @ (8005158 ) + 8004f0c: 681b ldr r3, [r3, #0] + 8004f0e: e013 b.n 8004f38 + 8004f10: 2302 movs r3, #2 + 8004f12: f8c7 3188 str.w r3, [r7, #392] @ 0x188 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8004e7a: f8d7 3188 ldr.w r3, [r7, #392] @ 0x188 - 8004e7e: fa93 f3a3 rbit r3, r3 - 8004e82: f8c7 3184 str.w r3, [r7, #388] @ 0x184 - 8004e86: 2302 movs r3, #2 - 8004e88: f8c7 3180 str.w r3, [r7, #384] @ 0x180 - 8004e8c: f8d7 3180 ldr.w r3, [r7, #384] @ 0x180 - 8004e90: fa93 f3a3 rbit r3, r3 - 8004e94: f8c7 317c str.w r3, [r7, #380] @ 0x17c - 8004e98: 4b88 ldr r3, [pc, #544] @ (80050bc ) - 8004e9a: 6a5b ldr r3, [r3, #36] @ 0x24 - 8004e9c: 2202 movs r2, #2 - 8004e9e: f8c7 2178 str.w r2, [r7, #376] @ 0x178 - 8004ea2: f8d7 2178 ldr.w r2, [r7, #376] @ 0x178 - 8004ea6: fa92 f2a2 rbit r2, r2 - 8004eaa: f8c7 2174 str.w r2, [r7, #372] @ 0x174 + 8004f16: f8d7 3188 ldr.w r3, [r7, #392] @ 0x188 + 8004f1a: fa93 f3a3 rbit r3, r3 + 8004f1e: f8c7 3184 str.w r3, [r7, #388] @ 0x184 + 8004f22: 2302 movs r3, #2 + 8004f24: f8c7 3180 str.w r3, [r7, #384] @ 0x180 + 8004f28: f8d7 3180 ldr.w r3, [r7, #384] @ 0x180 + 8004f2c: fa93 f3a3 rbit r3, r3 + 8004f30: f8c7 317c str.w r3, [r7, #380] @ 0x17c + 8004f34: 4b88 ldr r3, [pc, #544] @ (8005158 ) + 8004f36: 6a5b ldr r3, [r3, #36] @ 0x24 + 8004f38: 2202 movs r2, #2 + 8004f3a: f8c7 2178 str.w r2, [r7, #376] @ 0x178 + 8004f3e: f8d7 2178 ldr.w r2, [r7, #376] @ 0x178 + 8004f42: fa92 f2a2 rbit r2, r2 + 8004f46: f8c7 2174 str.w r2, [r7, #372] @ 0x174 return result; - 8004eae: f8d7 2174 ldr.w r2, [r7, #372] @ 0x174 - 8004eb2: fab2 f282 clz r2, r2 - 8004eb6: b2d2 uxtb r2, r2 - 8004eb8: f042 0220 orr.w r2, r2, #32 - 8004ebc: b2d2 uxtb r2, r2 - 8004ebe: f002 021f and.w r2, r2, #31 - 8004ec2: 2101 movs r1, #1 - 8004ec4: fa01 f202 lsl.w r2, r1, r2 - 8004ec8: 4013 ands r3, r2 - 8004eca: 2b00 cmp r3, #0 - 8004ecc: d00a beq.n 8004ee4 - 8004ece: f507 7300 add.w r3, r7, #512 @ 0x200 - 8004ed2: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc - 8004ed6: 681b ldr r3, [r3, #0] - 8004ed8: 691b ldr r3, [r3, #16] - 8004eda: 2b01 cmp r3, #1 - 8004edc: d002 beq.n 8004ee4 + 8004f4a: f8d7 2174 ldr.w r2, [r7, #372] @ 0x174 + 8004f4e: fab2 f282 clz r2, r2 + 8004f52: b2d2 uxtb r2, r2 + 8004f54: f042 0220 orr.w r2, r2, #32 + 8004f58: b2d2 uxtb r2, r2 + 8004f5a: f002 021f and.w r2, r2, #31 + 8004f5e: 2101 movs r1, #1 + 8004f60: fa01 f202 lsl.w r2, r1, r2 + 8004f64: 4013 ands r3, r2 + 8004f66: 2b00 cmp r3, #0 + 8004f68: d00a beq.n 8004f80 + 8004f6a: f507 7300 add.w r3, r7, #512 @ 0x200 + 8004f6e: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc + 8004f72: 681b ldr r3, [r3, #0] + 8004f74: 691b ldr r3, [r3, #16] + 8004f76: 2b01 cmp r3, #1 + 8004f78: d002 beq.n 8004f80 { return HAL_ERROR; - 8004ede: 2301 movs r3, #1 - 8004ee0: f000 be2e b.w 8005b40 + 8004f7a: 2301 movs r3, #1 + 8004f7c: f000 be2e b.w 8005bdc } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); - 8004ee4: 4b75 ldr r3, [pc, #468] @ (80050bc ) - 8004ee6: 681b ldr r3, [r3, #0] - 8004ee8: f023 02f8 bic.w r2, r3, #248 @ 0xf8 - 8004eec: f507 7300 add.w r3, r7, #512 @ 0x200 - 8004ef0: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc - 8004ef4: 681b ldr r3, [r3, #0] - 8004ef6: 695b ldr r3, [r3, #20] - 8004ef8: 21f8 movs r1, #248 @ 0xf8 - 8004efa: f8c7 1170 str.w r1, [r7, #368] @ 0x170 + 8004f80: 4b75 ldr r3, [pc, #468] @ (8005158 ) + 8004f82: 681b ldr r3, [r3, #0] + 8004f84: f023 02f8 bic.w r2, r3, #248 @ 0xf8 + 8004f88: f507 7300 add.w r3, r7, #512 @ 0x200 + 8004f8c: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc + 8004f90: 681b ldr r3, [r3, #0] + 8004f92: 695b ldr r3, [r3, #20] + 8004f94: 21f8 movs r1, #248 @ 0xf8 + 8004f96: f8c7 1170 str.w r1, [r7, #368] @ 0x170 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8004efe: f8d7 1170 ldr.w r1, [r7, #368] @ 0x170 - 8004f02: fa91 f1a1 rbit r1, r1 - 8004f06: f8c7 116c str.w r1, [r7, #364] @ 0x16c + 8004f9a: f8d7 1170 ldr.w r1, [r7, #368] @ 0x170 + 8004f9e: fa91 f1a1 rbit r1, r1 + 8004fa2: f8c7 116c str.w r1, [r7, #364] @ 0x16c return result; - 8004f0a: f8d7 116c ldr.w r1, [r7, #364] @ 0x16c - 8004f0e: fab1 f181 clz r1, r1 - 8004f12: b2c9 uxtb r1, r1 - 8004f14: 408b lsls r3, r1 - 8004f16: 4969 ldr r1, [pc, #420] @ (80050bc ) - 8004f18: 4313 orrs r3, r2 - 8004f1a: 600b str r3, [r1, #0] + 8004fa6: f8d7 116c ldr.w r1, [r7, #364] @ 0x16c + 8004faa: fab1 f181 clz r1, r1 + 8004fae: b2c9 uxtb r1, r1 + 8004fb0: 408b lsls r3, r1 + 8004fb2: 4969 ldr r1, [pc, #420] @ (8005158 ) + 8004fb4: 4313 orrs r3, r2 + 8004fb6: 600b str r3, [r1, #0] if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) - 8004f1c: e0fd b.n 800511a + 8004fb8: e0fd b.n 80051b6 } } else { /* Check the HSI State */ if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF) - 8004f1e: f507 7300 add.w r3, r7, #512 @ 0x200 - 8004f22: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc - 8004f26: 681b ldr r3, [r3, #0] - 8004f28: 691b ldr r3, [r3, #16] - 8004f2a: 2b00 cmp r3, #0 - 8004f2c: f000 8088 beq.w 8005040 - 8004f30: 2301 movs r3, #1 - 8004f32: f8c7 3168 str.w r3, [r7, #360] @ 0x168 + 8004fba: f507 7300 add.w r3, r7, #512 @ 0x200 + 8004fbe: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc + 8004fc2: 681b ldr r3, [r3, #0] + 8004fc4: 691b ldr r3, [r3, #16] + 8004fc6: 2b00 cmp r3, #0 + 8004fc8: f000 8088 beq.w 80050dc + 8004fcc: 2301 movs r3, #1 + 8004fce: f8c7 3168 str.w r3, [r7, #360] @ 0x168 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8004f36: f8d7 3168 ldr.w r3, [r7, #360] @ 0x168 - 8004f3a: fa93 f3a3 rbit r3, r3 - 8004f3e: f8c7 3164 str.w r3, [r7, #356] @ 0x164 + 8004fd2: f8d7 3168 ldr.w r3, [r7, #360] @ 0x168 + 8004fd6: fa93 f3a3 rbit r3, r3 + 8004fda: f8c7 3164 str.w r3, [r7, #356] @ 0x164 return result; - 8004f42: f8d7 3164 ldr.w r3, [r7, #356] @ 0x164 + 8004fde: f8d7 3164 ldr.w r3, [r7, #356] @ 0x164 { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); - 8004f46: fab3 f383 clz r3, r3 - 8004f4a: b2db uxtb r3, r3 - 8004f4c: f103 5384 add.w r3, r3, #276824064 @ 0x10800000 - 8004f50: f503 1384 add.w r3, r3, #1081344 @ 0x108000 - 8004f54: 009b lsls r3, r3, #2 - 8004f56: 461a mov r2, r3 - 8004f58: 2301 movs r3, #1 - 8004f5a: 6013 str r3, [r2, #0] + 8004fe2: fab3 f383 clz r3, r3 + 8004fe6: b2db uxtb r3, r3 + 8004fe8: f103 5384 add.w r3, r3, #276824064 @ 0x10800000 + 8004fec: f503 1384 add.w r3, r3, #1081344 @ 0x108000 + 8004ff0: 009b lsls r3, r3, #2 + 8004ff2: 461a mov r2, r3 + 8004ff4: 2301 movs r3, #1 + 8004ff6: 6013 str r3, [r2, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); - 8004f5c: f7fd f984 bl 8002268 - 8004f60: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8 + 8004ff8: f7fd f984 bl 8002304 + 8004ffc: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8 /* Wait till HSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) - 8004f64: e00a b.n 8004f7c + 8005000: e00a b.n 8005018 { if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) - 8004f66: f7fd f97f bl 8002268 - 8004f6a: 4602 mov r2, r0 - 8004f6c: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8 - 8004f70: 1ad3 subs r3, r2, r3 - 8004f72: 2b02 cmp r3, #2 - 8004f74: d902 bls.n 8004f7c + 8005002: f7fd f97f bl 8002304 + 8005006: 4602 mov r2, r0 + 8005008: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8 + 800500c: 1ad3 subs r3, r2, r3 + 800500e: 2b02 cmp r3, #2 + 8005010: d902 bls.n 8005018 { return HAL_TIMEOUT; - 8004f76: 2303 movs r3, #3 - 8004f78: f000 bde2 b.w 8005b40 - 8004f7c: 2302 movs r3, #2 - 8004f7e: f8c7 3160 str.w r3, [r7, #352] @ 0x160 + 8005012: 2303 movs r3, #3 + 8005014: f000 bde2 b.w 8005bdc + 8005018: 2302 movs r3, #2 + 800501a: f8c7 3160 str.w r3, [r7, #352] @ 0x160 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8004f82: f8d7 3160 ldr.w r3, [r7, #352] @ 0x160 - 8004f86: fa93 f3a3 rbit r3, r3 - 8004f8a: f8c7 315c str.w r3, [r7, #348] @ 0x15c + 800501e: f8d7 3160 ldr.w r3, [r7, #352] @ 0x160 + 8005022: fa93 f3a3 rbit r3, r3 + 8005026: f8c7 315c str.w r3, [r7, #348] @ 0x15c return result; - 8004f8e: f8d7 315c ldr.w r3, [r7, #348] @ 0x15c + 800502a: f8d7 315c ldr.w r3, [r7, #348] @ 0x15c while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) - 8004f92: fab3 f383 clz r3, r3 - 8004f96: b2db uxtb r3, r3 - 8004f98: 095b lsrs r3, r3, #5 - 8004f9a: b2db uxtb r3, r3 - 8004f9c: f043 0301 orr.w r3, r3, #1 - 8004fa0: b2db uxtb r3, r3 - 8004fa2: 2b01 cmp r3, #1 - 8004fa4: d102 bne.n 8004fac - 8004fa6: 4b45 ldr r3, [pc, #276] @ (80050bc ) - 8004fa8: 681b ldr r3, [r3, #0] - 8004faa: e013 b.n 8004fd4 - 8004fac: 2302 movs r3, #2 - 8004fae: f8c7 3158 str.w r3, [r7, #344] @ 0x158 + 800502e: fab3 f383 clz r3, r3 + 8005032: b2db uxtb r3, r3 + 8005034: 095b lsrs r3, r3, #5 + 8005036: b2db uxtb r3, r3 + 8005038: f043 0301 orr.w r3, r3, #1 + 800503c: b2db uxtb r3, r3 + 800503e: 2b01 cmp r3, #1 + 8005040: d102 bne.n 8005048 + 8005042: 4b45 ldr r3, [pc, #276] @ (8005158 ) + 8005044: 681b ldr r3, [r3, #0] + 8005046: e013 b.n 8005070 + 8005048: 2302 movs r3, #2 + 800504a: f8c7 3158 str.w r3, [r7, #344] @ 0x158 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8004fb2: f8d7 3158 ldr.w r3, [r7, #344] @ 0x158 - 8004fb6: fa93 f3a3 rbit r3, r3 - 8004fba: f8c7 3154 str.w r3, [r7, #340] @ 0x154 - 8004fbe: 2302 movs r3, #2 - 8004fc0: f8c7 3150 str.w r3, [r7, #336] @ 0x150 - 8004fc4: f8d7 3150 ldr.w r3, [r7, #336] @ 0x150 - 8004fc8: fa93 f3a3 rbit r3, r3 - 8004fcc: f8c7 314c str.w r3, [r7, #332] @ 0x14c - 8004fd0: 4b3a ldr r3, [pc, #232] @ (80050bc ) - 8004fd2: 6a5b ldr r3, [r3, #36] @ 0x24 - 8004fd4: 2202 movs r2, #2 - 8004fd6: f8c7 2148 str.w r2, [r7, #328] @ 0x148 - 8004fda: f8d7 2148 ldr.w r2, [r7, #328] @ 0x148 - 8004fde: fa92 f2a2 rbit r2, r2 - 8004fe2: f8c7 2144 str.w r2, [r7, #324] @ 0x144 + 800504e: f8d7 3158 ldr.w r3, [r7, #344] @ 0x158 + 8005052: fa93 f3a3 rbit r3, r3 + 8005056: f8c7 3154 str.w r3, [r7, #340] @ 0x154 + 800505a: 2302 movs r3, #2 + 800505c: f8c7 3150 str.w r3, [r7, #336] @ 0x150 + 8005060: f8d7 3150 ldr.w r3, [r7, #336] @ 0x150 + 8005064: fa93 f3a3 rbit r3, r3 + 8005068: f8c7 314c str.w r3, [r7, #332] @ 0x14c + 800506c: 4b3a ldr r3, [pc, #232] @ (8005158 ) + 800506e: 6a5b ldr r3, [r3, #36] @ 0x24 + 8005070: 2202 movs r2, #2 + 8005072: f8c7 2148 str.w r2, [r7, #328] @ 0x148 + 8005076: f8d7 2148 ldr.w r2, [r7, #328] @ 0x148 + 800507a: fa92 f2a2 rbit r2, r2 + 800507e: f8c7 2144 str.w r2, [r7, #324] @ 0x144 return result; - 8004fe6: f8d7 2144 ldr.w r2, [r7, #324] @ 0x144 - 8004fea: fab2 f282 clz r2, r2 - 8004fee: b2d2 uxtb r2, r2 - 8004ff0: f042 0220 orr.w r2, r2, #32 - 8004ff4: b2d2 uxtb r2, r2 - 8004ff6: f002 021f and.w r2, r2, #31 - 8004ffa: 2101 movs r1, #1 - 8004ffc: fa01 f202 lsl.w r2, r1, r2 - 8005000: 4013 ands r3, r2 - 8005002: 2b00 cmp r3, #0 - 8005004: d0af beq.n 8004f66 + 8005082: f8d7 2144 ldr.w r2, [r7, #324] @ 0x144 + 8005086: fab2 f282 clz r2, r2 + 800508a: b2d2 uxtb r2, r2 + 800508c: f042 0220 orr.w r2, r2, #32 + 8005090: b2d2 uxtb r2, r2 + 8005092: f002 021f and.w r2, r2, #31 + 8005096: 2101 movs r1, #1 + 8005098: fa01 f202 lsl.w r2, r1, r2 + 800509c: 4013 ands r3, r2 + 800509e: 2b00 cmp r3, #0 + 80050a0: d0af beq.n 8005002 } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); - 8005006: 4b2d ldr r3, [pc, #180] @ (80050bc ) - 8005008: 681b ldr r3, [r3, #0] - 800500a: f023 02f8 bic.w r2, r3, #248 @ 0xf8 - 800500e: f507 7300 add.w r3, r7, #512 @ 0x200 - 8005012: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc - 8005016: 681b ldr r3, [r3, #0] - 8005018: 695b ldr r3, [r3, #20] - 800501a: 21f8 movs r1, #248 @ 0xf8 - 800501c: f8c7 1140 str.w r1, [r7, #320] @ 0x140 + 80050a2: 4b2d ldr r3, [pc, #180] @ (8005158 ) + 80050a4: 681b ldr r3, [r3, #0] + 80050a6: f023 02f8 bic.w r2, r3, #248 @ 0xf8 + 80050aa: f507 7300 add.w r3, r7, #512 @ 0x200 + 80050ae: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc + 80050b2: 681b ldr r3, [r3, #0] + 80050b4: 695b ldr r3, [r3, #20] + 80050b6: 21f8 movs r1, #248 @ 0xf8 + 80050b8: f8c7 1140 str.w r1, [r7, #320] @ 0x140 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8005020: f8d7 1140 ldr.w r1, [r7, #320] @ 0x140 - 8005024: fa91 f1a1 rbit r1, r1 - 8005028: f8c7 113c str.w r1, [r7, #316] @ 0x13c + 80050bc: f8d7 1140 ldr.w r1, [r7, #320] @ 0x140 + 80050c0: fa91 f1a1 rbit r1, r1 + 80050c4: f8c7 113c str.w r1, [r7, #316] @ 0x13c return result; - 800502c: f8d7 113c ldr.w r1, [r7, #316] @ 0x13c - 8005030: fab1 f181 clz r1, r1 - 8005034: b2c9 uxtb r1, r1 - 8005036: 408b lsls r3, r1 - 8005038: 4920 ldr r1, [pc, #128] @ (80050bc ) - 800503a: 4313 orrs r3, r2 - 800503c: 600b str r3, [r1, #0] - 800503e: e06c b.n 800511a - 8005040: 2301 movs r3, #1 - 8005042: f8c7 3138 str.w r3, [r7, #312] @ 0x138 + 80050c8: f8d7 113c ldr.w r1, [r7, #316] @ 0x13c + 80050cc: fab1 f181 clz r1, r1 + 80050d0: b2c9 uxtb r1, r1 + 80050d2: 408b lsls r3, r1 + 80050d4: 4920 ldr r1, [pc, #128] @ (8005158 ) + 80050d6: 4313 orrs r3, r2 + 80050d8: 600b str r3, [r1, #0] + 80050da: e06c b.n 80051b6 + 80050dc: 2301 movs r3, #1 + 80050de: f8c7 3138 str.w r3, [r7, #312] @ 0x138 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8005046: f8d7 3138 ldr.w r3, [r7, #312] @ 0x138 - 800504a: fa93 f3a3 rbit r3, r3 - 800504e: f8c7 3134 str.w r3, [r7, #308] @ 0x134 + 80050e2: f8d7 3138 ldr.w r3, [r7, #312] @ 0x138 + 80050e6: fa93 f3a3 rbit r3, r3 + 80050ea: f8c7 3134 str.w r3, [r7, #308] @ 0x134 return result; - 8005052: f8d7 3134 ldr.w r3, [r7, #308] @ 0x134 + 80050ee: f8d7 3134 ldr.w r3, [r7, #308] @ 0x134 } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); - 8005056: fab3 f383 clz r3, r3 - 800505a: b2db uxtb r3, r3 - 800505c: f103 5384 add.w r3, r3, #276824064 @ 0x10800000 - 8005060: f503 1384 add.w r3, r3, #1081344 @ 0x108000 - 8005064: 009b lsls r3, r3, #2 - 8005066: 461a mov r2, r3 - 8005068: 2300 movs r3, #0 - 800506a: 6013 str r3, [r2, #0] + 80050f2: fab3 f383 clz r3, r3 + 80050f6: b2db uxtb r3, r3 + 80050f8: f103 5384 add.w r3, r3, #276824064 @ 0x10800000 + 80050fc: f503 1384 add.w r3, r3, #1081344 @ 0x108000 + 8005100: 009b lsls r3, r3, #2 + 8005102: 461a mov r2, r3 + 8005104: 2300 movs r3, #0 + 8005106: 6013 str r3, [r2, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); - 800506c: f7fd f8fc bl 8002268 - 8005070: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8 + 8005108: f7fd f8fc bl 8002304 + 800510c: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8 /* Wait till HSI is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) - 8005074: e00a b.n 800508c + 8005110: e00a b.n 8005128 { if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) - 8005076: f7fd f8f7 bl 8002268 - 800507a: 4602 mov r2, r0 - 800507c: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8 - 8005080: 1ad3 subs r3, r2, r3 - 8005082: 2b02 cmp r3, #2 - 8005084: d902 bls.n 800508c + 8005112: f7fd f8f7 bl 8002304 + 8005116: 4602 mov r2, r0 + 8005118: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8 + 800511c: 1ad3 subs r3, r2, r3 + 800511e: 2b02 cmp r3, #2 + 8005120: d902 bls.n 8005128 { return HAL_TIMEOUT; - 8005086: 2303 movs r3, #3 - 8005088: f000 bd5a b.w 8005b40 - 800508c: 2302 movs r3, #2 - 800508e: f8c7 3130 str.w r3, [r7, #304] @ 0x130 + 8005122: 2303 movs r3, #3 + 8005124: f000 bd5a b.w 8005bdc + 8005128: 2302 movs r3, #2 + 800512a: f8c7 3130 str.w r3, [r7, #304] @ 0x130 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8005092: f8d7 3130 ldr.w r3, [r7, #304] @ 0x130 - 8005096: fa93 f3a3 rbit r3, r3 - 800509a: f8c7 312c str.w r3, [r7, #300] @ 0x12c + 800512e: f8d7 3130 ldr.w r3, [r7, #304] @ 0x130 + 8005132: fa93 f3a3 rbit r3, r3 + 8005136: f8c7 312c str.w r3, [r7, #300] @ 0x12c return result; - 800509e: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c + 800513a: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) - 80050a2: fab3 f383 clz r3, r3 - 80050a6: b2db uxtb r3, r3 - 80050a8: 095b lsrs r3, r3, #5 - 80050aa: b2db uxtb r3, r3 - 80050ac: f043 0301 orr.w r3, r3, #1 - 80050b0: b2db uxtb r3, r3 - 80050b2: 2b01 cmp r3, #1 - 80050b4: d104 bne.n 80050c0 - 80050b6: 4b01 ldr r3, [pc, #4] @ (80050bc ) - 80050b8: 681b ldr r3, [r3, #0] - 80050ba: e015 b.n 80050e8 - 80050bc: 40021000 .word 0x40021000 - 80050c0: 2302 movs r3, #2 - 80050c2: f8c7 3128 str.w r3, [r7, #296] @ 0x128 + 800513e: fab3 f383 clz r3, r3 + 8005142: b2db uxtb r3, r3 + 8005144: 095b lsrs r3, r3, #5 + 8005146: b2db uxtb r3, r3 + 8005148: f043 0301 orr.w r3, r3, #1 + 800514c: b2db uxtb r3, r3 + 800514e: 2b01 cmp r3, #1 + 8005150: d104 bne.n 800515c + 8005152: 4b01 ldr r3, [pc, #4] @ (8005158 ) + 8005154: 681b ldr r3, [r3, #0] + 8005156: e015 b.n 8005184 + 8005158: 40021000 .word 0x40021000 + 800515c: 2302 movs r3, #2 + 800515e: f8c7 3128 str.w r3, [r7, #296] @ 0x128 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 80050c6: f8d7 3128 ldr.w r3, [r7, #296] @ 0x128 - 80050ca: fa93 f3a3 rbit r3, r3 - 80050ce: f8c7 3124 str.w r3, [r7, #292] @ 0x124 - 80050d2: 2302 movs r3, #2 - 80050d4: f8c7 3120 str.w r3, [r7, #288] @ 0x120 - 80050d8: f8d7 3120 ldr.w r3, [r7, #288] @ 0x120 - 80050dc: fa93 f3a3 rbit r3, r3 - 80050e0: f8c7 311c str.w r3, [r7, #284] @ 0x11c - 80050e4: 4bc8 ldr r3, [pc, #800] @ (8005408 ) - 80050e6: 6a5b ldr r3, [r3, #36] @ 0x24 - 80050e8: 2202 movs r2, #2 - 80050ea: f8c7 2118 str.w r2, [r7, #280] @ 0x118 - 80050ee: f8d7 2118 ldr.w r2, [r7, #280] @ 0x118 - 80050f2: fa92 f2a2 rbit r2, r2 - 80050f6: f8c7 2114 str.w r2, [r7, #276] @ 0x114 + 8005162: f8d7 3128 ldr.w r3, [r7, #296] @ 0x128 + 8005166: fa93 f3a3 rbit r3, r3 + 800516a: f8c7 3124 str.w r3, [r7, #292] @ 0x124 + 800516e: 2302 movs r3, #2 + 8005170: f8c7 3120 str.w r3, [r7, #288] @ 0x120 + 8005174: f8d7 3120 ldr.w r3, [r7, #288] @ 0x120 + 8005178: fa93 f3a3 rbit r3, r3 + 800517c: f8c7 311c str.w r3, [r7, #284] @ 0x11c + 8005180: 4bc8 ldr r3, [pc, #800] @ (80054a4 ) + 8005182: 6a5b ldr r3, [r3, #36] @ 0x24 + 8005184: 2202 movs r2, #2 + 8005186: f8c7 2118 str.w r2, [r7, #280] @ 0x118 + 800518a: f8d7 2118 ldr.w r2, [r7, #280] @ 0x118 + 800518e: fa92 f2a2 rbit r2, r2 + 8005192: f8c7 2114 str.w r2, [r7, #276] @ 0x114 return result; - 80050fa: f8d7 2114 ldr.w r2, [r7, #276] @ 0x114 - 80050fe: fab2 f282 clz r2, r2 - 8005102: b2d2 uxtb r2, r2 - 8005104: f042 0220 orr.w r2, r2, #32 - 8005108: b2d2 uxtb r2, r2 - 800510a: f002 021f and.w r2, r2, #31 - 800510e: 2101 movs r1, #1 - 8005110: fa01 f202 lsl.w r2, r1, r2 - 8005114: 4013 ands r3, r2 - 8005116: 2b00 cmp r3, #0 - 8005118: d1ad bne.n 8005076 + 8005196: f8d7 2114 ldr.w r2, [r7, #276] @ 0x114 + 800519a: fab2 f282 clz r2, r2 + 800519e: b2d2 uxtb r2, r2 + 80051a0: f042 0220 orr.w r2, r2, #32 + 80051a4: b2d2 uxtb r2, r2 + 80051a6: f002 021f and.w r2, r2, #31 + 80051aa: 2101 movs r1, #1 + 80051ac: fa01 f202 lsl.w r2, r1, r2 + 80051b0: 4013 ands r3, r2 + 80051b2: 2b00 cmp r3, #0 + 80051b4: d1ad bne.n 8005112 } } } } /*------------------------------ LSI Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) - 800511a: f507 7300 add.w r3, r7, #512 @ 0x200 - 800511e: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc - 8005122: 681b ldr r3, [r3, #0] - 8005124: 681b ldr r3, [r3, #0] - 8005126: f003 0308 and.w r3, r3, #8 - 800512a: 2b00 cmp r3, #0 - 800512c: f000 8110 beq.w 8005350 + 80051b6: f507 7300 add.w r3, r7, #512 @ 0x200 + 80051ba: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc + 80051be: 681b ldr r3, [r3, #0] + 80051c0: 681b ldr r3, [r3, #0] + 80051c2: f003 0308 and.w r3, r3, #8 + 80051c6: 2b00 cmp r3, #0 + 80051c8: f000 8110 beq.w 80053ec { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) - 8005130: f507 7300 add.w r3, r7, #512 @ 0x200 - 8005134: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc - 8005138: 681b ldr r3, [r3, #0] - 800513a: 699b ldr r3, [r3, #24] - 800513c: 2b00 cmp r3, #0 - 800513e: d079 beq.n 8005234 - 8005140: 2301 movs r3, #1 - 8005142: f8c7 3110 str.w r3, [r7, #272] @ 0x110 + 80051cc: f507 7300 add.w r3, r7, #512 @ 0x200 + 80051d0: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc + 80051d4: 681b ldr r3, [r3, #0] + 80051d6: 699b ldr r3, [r3, #24] + 80051d8: 2b00 cmp r3, #0 + 80051da: d079 beq.n 80052d0 + 80051dc: 2301 movs r3, #1 + 80051de: f8c7 3110 str.w r3, [r7, #272] @ 0x110 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8005146: f8d7 3110 ldr.w r3, [r7, #272] @ 0x110 - 800514a: fa93 f3a3 rbit r3, r3 - 800514e: f8c7 310c str.w r3, [r7, #268] @ 0x10c + 80051e2: f8d7 3110 ldr.w r3, [r7, #272] @ 0x110 + 80051e6: fa93 f3a3 rbit r3, r3 + 80051ea: f8c7 310c str.w r3, [r7, #268] @ 0x10c return result; - 8005152: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c + 80051ee: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); - 8005156: fab3 f383 clz r3, r3 - 800515a: b2db uxtb r3, r3 - 800515c: 461a mov r2, r3 - 800515e: 4bab ldr r3, [pc, #684] @ (800540c ) - 8005160: 4413 add r3, r2 - 8005162: 009b lsls r3, r3, #2 - 8005164: 461a mov r2, r3 - 8005166: 2301 movs r3, #1 - 8005168: 6013 str r3, [r2, #0] + 80051f2: fab3 f383 clz r3, r3 + 80051f6: b2db uxtb r3, r3 + 80051f8: 461a mov r2, r3 + 80051fa: 4bab ldr r3, [pc, #684] @ (80054a8 ) + 80051fc: 4413 add r3, r2 + 80051fe: 009b lsls r3, r3, #2 + 8005200: 461a mov r2, r3 + 8005202: 2301 movs r3, #1 + 8005204: 6013 str r3, [r2, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); - 800516a: f7fd f87d bl 8002268 - 800516e: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8 + 8005206: f7fd f87d bl 8002304 + 800520a: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8 /* Wait till LSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) - 8005172: e00a b.n 800518a + 800520e: e00a b.n 8005226 { if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) - 8005174: f7fd f878 bl 8002268 - 8005178: 4602 mov r2, r0 - 800517a: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8 - 800517e: 1ad3 subs r3, r2, r3 - 8005180: 2b02 cmp r3, #2 - 8005182: d902 bls.n 800518a + 8005210: f7fd f878 bl 8002304 + 8005214: 4602 mov r2, r0 + 8005216: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8 + 800521a: 1ad3 subs r3, r2, r3 + 800521c: 2b02 cmp r3, #2 + 800521e: d902 bls.n 8005226 { return HAL_TIMEOUT; - 8005184: 2303 movs r3, #3 - 8005186: f000 bcdb b.w 8005b40 - 800518a: 2302 movs r3, #2 - 800518c: f8c7 3108 str.w r3, [r7, #264] @ 0x108 + 8005220: 2303 movs r3, #3 + 8005222: f000 bcdb b.w 8005bdc + 8005226: 2302 movs r3, #2 + 8005228: f8c7 3108 str.w r3, [r7, #264] @ 0x108 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8005190: f8d7 3108 ldr.w r3, [r7, #264] @ 0x108 - 8005194: fa93 f3a3 rbit r3, r3 - 8005198: f8c7 3104 str.w r3, [r7, #260] @ 0x104 - 800519c: f507 7300 add.w r3, r7, #512 @ 0x200 - 80051a0: f5a3 7380 sub.w r3, r3, #256 @ 0x100 - 80051a4: 2202 movs r2, #2 - 80051a6: 601a str r2, [r3, #0] - 80051a8: f507 7300 add.w r3, r7, #512 @ 0x200 - 80051ac: f5a3 7380 sub.w r3, r3, #256 @ 0x100 - 80051b0: 681b ldr r3, [r3, #0] - 80051b2: fa93 f2a3 rbit r2, r3 - 80051b6: f507 7300 add.w r3, r7, #512 @ 0x200 - 80051ba: f5a3 7382 sub.w r3, r3, #260 @ 0x104 - 80051be: 601a str r2, [r3, #0] - 80051c0: f507 7300 add.w r3, r7, #512 @ 0x200 - 80051c4: f5a3 7384 sub.w r3, r3, #264 @ 0x108 - 80051c8: 2202 movs r2, #2 - 80051ca: 601a str r2, [r3, #0] - 80051cc: f507 7300 add.w r3, r7, #512 @ 0x200 - 80051d0: f5a3 7384 sub.w r3, r3, #264 @ 0x108 - 80051d4: 681b ldr r3, [r3, #0] - 80051d6: fa93 f2a3 rbit r2, r3 - 80051da: f507 7300 add.w r3, r7, #512 @ 0x200 - 80051de: f5a3 7386 sub.w r3, r3, #268 @ 0x10c - 80051e2: 601a str r2, [r3, #0] + 800522c: f8d7 3108 ldr.w r3, [r7, #264] @ 0x108 + 8005230: fa93 f3a3 rbit r3, r3 + 8005234: f8c7 3104 str.w r3, [r7, #260] @ 0x104 + 8005238: f507 7300 add.w r3, r7, #512 @ 0x200 + 800523c: f5a3 7380 sub.w r3, r3, #256 @ 0x100 + 8005240: 2202 movs r2, #2 + 8005242: 601a str r2, [r3, #0] + 8005244: f507 7300 add.w r3, r7, #512 @ 0x200 + 8005248: f5a3 7380 sub.w r3, r3, #256 @ 0x100 + 800524c: 681b ldr r3, [r3, #0] + 800524e: fa93 f2a3 rbit r2, r3 + 8005252: f507 7300 add.w r3, r7, #512 @ 0x200 + 8005256: f5a3 7382 sub.w r3, r3, #260 @ 0x104 + 800525a: 601a str r2, [r3, #0] + 800525c: f507 7300 add.w r3, r7, #512 @ 0x200 + 8005260: f5a3 7384 sub.w r3, r3, #264 @ 0x108 + 8005264: 2202 movs r2, #2 + 8005266: 601a str r2, [r3, #0] + 8005268: f507 7300 add.w r3, r7, #512 @ 0x200 + 800526c: f5a3 7384 sub.w r3, r3, #264 @ 0x108 + 8005270: 681b ldr r3, [r3, #0] + 8005272: fa93 f2a3 rbit r2, r3 + 8005276: f507 7300 add.w r3, r7, #512 @ 0x200 + 800527a: f5a3 7386 sub.w r3, r3, #268 @ 0x10c + 800527e: 601a str r2, [r3, #0] while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) - 80051e4: 4b88 ldr r3, [pc, #544] @ (8005408 ) - 80051e6: 6a5a ldr r2, [r3, #36] @ 0x24 - 80051e8: f507 7300 add.w r3, r7, #512 @ 0x200 - 80051ec: f5a3 7388 sub.w r3, r3, #272 @ 0x110 - 80051f0: 2102 movs r1, #2 - 80051f2: 6019 str r1, [r3, #0] - 80051f4: f507 7300 add.w r3, r7, #512 @ 0x200 - 80051f8: f5a3 7388 sub.w r3, r3, #272 @ 0x110 - 80051fc: 681b ldr r3, [r3, #0] - 80051fe: fa93 f1a3 rbit r1, r3 - 8005202: f507 7300 add.w r3, r7, #512 @ 0x200 - 8005206: f5a3 738a sub.w r3, r3, #276 @ 0x114 - 800520a: 6019 str r1, [r3, #0] + 8005280: 4b88 ldr r3, [pc, #544] @ (80054a4 ) + 8005282: 6a5a ldr r2, [r3, #36] @ 0x24 + 8005284: f507 7300 add.w r3, r7, #512 @ 0x200 + 8005288: f5a3 7388 sub.w r3, r3, #272 @ 0x110 + 800528c: 2102 movs r1, #2 + 800528e: 6019 str r1, [r3, #0] + 8005290: f507 7300 add.w r3, r7, #512 @ 0x200 + 8005294: f5a3 7388 sub.w r3, r3, #272 @ 0x110 + 8005298: 681b ldr r3, [r3, #0] + 800529a: fa93 f1a3 rbit r1, r3 + 800529e: f507 7300 add.w r3, r7, #512 @ 0x200 + 80052a2: f5a3 738a sub.w r3, r3, #276 @ 0x114 + 80052a6: 6019 str r1, [r3, #0] return result; - 800520c: f507 7300 add.w r3, r7, #512 @ 0x200 - 8005210: f5a3 738a sub.w r3, r3, #276 @ 0x114 - 8005214: 681b ldr r3, [r3, #0] - 8005216: fab3 f383 clz r3, r3 - 800521a: b2db uxtb r3, r3 - 800521c: f043 0360 orr.w r3, r3, #96 @ 0x60 - 8005220: b2db uxtb r3, r3 - 8005222: f003 031f and.w r3, r3, #31 - 8005226: 2101 movs r1, #1 - 8005228: fa01 f303 lsl.w r3, r1, r3 - 800522c: 4013 ands r3, r2 - 800522e: 2b00 cmp r3, #0 - 8005230: d0a0 beq.n 8005174 - 8005232: e08d b.n 8005350 - 8005234: f507 7300 add.w r3, r7, #512 @ 0x200 - 8005238: f5a3 738c sub.w r3, r3, #280 @ 0x118 - 800523c: 2201 movs r2, #1 - 800523e: 601a str r2, [r3, #0] + 80052a8: f507 7300 add.w r3, r7, #512 @ 0x200 + 80052ac: f5a3 738a sub.w r3, r3, #276 @ 0x114 + 80052b0: 681b ldr r3, [r3, #0] + 80052b2: fab3 f383 clz r3, r3 + 80052b6: b2db uxtb r3, r3 + 80052b8: f043 0360 orr.w r3, r3, #96 @ 0x60 + 80052bc: b2db uxtb r3, r3 + 80052be: f003 031f and.w r3, r3, #31 + 80052c2: 2101 movs r1, #1 + 80052c4: fa01 f303 lsl.w r3, r1, r3 + 80052c8: 4013 ands r3, r2 + 80052ca: 2b00 cmp r3, #0 + 80052cc: d0a0 beq.n 8005210 + 80052ce: e08d b.n 80053ec + 80052d0: f507 7300 add.w r3, r7, #512 @ 0x200 + 80052d4: f5a3 738c sub.w r3, r3, #280 @ 0x118 + 80052d8: 2201 movs r2, #1 + 80052da: 601a str r2, [r3, #0] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8005240: f507 7300 add.w r3, r7, #512 @ 0x200 - 8005244: f5a3 738c sub.w r3, r3, #280 @ 0x118 - 8005248: 681b ldr r3, [r3, #0] - 800524a: fa93 f2a3 rbit r2, r3 - 800524e: f507 7300 add.w r3, r7, #512 @ 0x200 - 8005252: f5a3 738e sub.w r3, r3, #284 @ 0x11c - 8005256: 601a str r2, [r3, #0] + 80052dc: f507 7300 add.w r3, r7, #512 @ 0x200 + 80052e0: f5a3 738c sub.w r3, r3, #280 @ 0x118 + 80052e4: 681b ldr r3, [r3, #0] + 80052e6: fa93 f2a3 rbit r2, r3 + 80052ea: f507 7300 add.w r3, r7, #512 @ 0x200 + 80052ee: f5a3 738e sub.w r3, r3, #284 @ 0x11c + 80052f2: 601a str r2, [r3, #0] return result; - 8005258: f507 7300 add.w r3, r7, #512 @ 0x200 - 800525c: f5a3 738e sub.w r3, r3, #284 @ 0x11c - 8005260: 681b ldr r3, [r3, #0] + 80052f4: f507 7300 add.w r3, r7, #512 @ 0x200 + 80052f8: f5a3 738e sub.w r3, r3, #284 @ 0x11c + 80052fc: 681b ldr r3, [r3, #0] } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); - 8005262: fab3 f383 clz r3, r3 - 8005266: b2db uxtb r3, r3 - 8005268: 461a mov r2, r3 - 800526a: 4b68 ldr r3, [pc, #416] @ (800540c ) - 800526c: 4413 add r3, r2 - 800526e: 009b lsls r3, r3, #2 - 8005270: 461a mov r2, r3 - 8005272: 2300 movs r3, #0 - 8005274: 6013 str r3, [r2, #0] + 80052fe: fab3 f383 clz r3, r3 + 8005302: b2db uxtb r3, r3 + 8005304: 461a mov r2, r3 + 8005306: 4b68 ldr r3, [pc, #416] @ (80054a8 ) + 8005308: 4413 add r3, r2 + 800530a: 009b lsls r3, r3, #2 + 800530c: 461a mov r2, r3 + 800530e: 2300 movs r3, #0 + 8005310: 6013 str r3, [r2, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); - 8005276: f7fc fff7 bl 8002268 - 800527a: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8 + 8005312: f7fc fff7 bl 8002304 + 8005316: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8 /* Wait till LSI is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) - 800527e: e00a b.n 8005296 + 800531a: e00a b.n 8005332 { if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) - 8005280: f7fc fff2 bl 8002268 - 8005284: 4602 mov r2, r0 - 8005286: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8 - 800528a: 1ad3 subs r3, r2, r3 - 800528c: 2b02 cmp r3, #2 - 800528e: d902 bls.n 8005296 + 800531c: f7fc fff2 bl 8002304 + 8005320: 4602 mov r2, r0 + 8005322: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8 + 8005326: 1ad3 subs r3, r2, r3 + 8005328: 2b02 cmp r3, #2 + 800532a: d902 bls.n 8005332 { return HAL_TIMEOUT; - 8005290: 2303 movs r3, #3 - 8005292: f000 bc55 b.w 8005b40 - 8005296: f507 7300 add.w r3, r7, #512 @ 0x200 - 800529a: f5a3 7390 sub.w r3, r3, #288 @ 0x120 - 800529e: 2202 movs r2, #2 - 80052a0: 601a str r2, [r3, #0] + 800532c: 2303 movs r3, #3 + 800532e: f000 bc55 b.w 8005bdc + 8005332: f507 7300 add.w r3, r7, #512 @ 0x200 + 8005336: f5a3 7390 sub.w r3, r3, #288 @ 0x120 + 800533a: 2202 movs r2, #2 + 800533c: 601a str r2, [r3, #0] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 80052a2: f507 7300 add.w r3, r7, #512 @ 0x200 - 80052a6: f5a3 7390 sub.w r3, r3, #288 @ 0x120 - 80052aa: 681b ldr r3, [r3, #0] - 80052ac: fa93 f2a3 rbit r2, r3 - 80052b0: f507 7300 add.w r3, r7, #512 @ 0x200 - 80052b4: f5a3 7392 sub.w r3, r3, #292 @ 0x124 - 80052b8: 601a str r2, [r3, #0] - 80052ba: f507 7300 add.w r3, r7, #512 @ 0x200 - 80052be: f5a3 7394 sub.w r3, r3, #296 @ 0x128 - 80052c2: 2202 movs r2, #2 - 80052c4: 601a str r2, [r3, #0] - 80052c6: f507 7300 add.w r3, r7, #512 @ 0x200 - 80052ca: f5a3 7394 sub.w r3, r3, #296 @ 0x128 - 80052ce: 681b ldr r3, [r3, #0] - 80052d0: fa93 f2a3 rbit r2, r3 - 80052d4: f507 7300 add.w r3, r7, #512 @ 0x200 - 80052d8: f5a3 7396 sub.w r3, r3, #300 @ 0x12c - 80052dc: 601a str r2, [r3, #0] - 80052de: f507 7300 add.w r3, r7, #512 @ 0x200 - 80052e2: f5a3 7398 sub.w r3, r3, #304 @ 0x130 - 80052e6: 2202 movs r2, #2 - 80052e8: 601a str r2, [r3, #0] - 80052ea: f507 7300 add.w r3, r7, #512 @ 0x200 - 80052ee: f5a3 7398 sub.w r3, r3, #304 @ 0x130 - 80052f2: 681b ldr r3, [r3, #0] - 80052f4: fa93 f2a3 rbit r2, r3 - 80052f8: f507 7300 add.w r3, r7, #512 @ 0x200 - 80052fc: f5a3 739a sub.w r3, r3, #308 @ 0x134 - 8005300: 601a str r2, [r3, #0] + 800533e: f507 7300 add.w r3, r7, #512 @ 0x200 + 8005342: f5a3 7390 sub.w r3, r3, #288 @ 0x120 + 8005346: 681b ldr r3, [r3, #0] + 8005348: fa93 f2a3 rbit r2, r3 + 800534c: f507 7300 add.w r3, r7, #512 @ 0x200 + 8005350: f5a3 7392 sub.w r3, r3, #292 @ 0x124 + 8005354: 601a str r2, [r3, #0] + 8005356: f507 7300 add.w r3, r7, #512 @ 0x200 + 800535a: f5a3 7394 sub.w r3, r3, #296 @ 0x128 + 800535e: 2202 movs r2, #2 + 8005360: 601a str r2, [r3, #0] + 8005362: f507 7300 add.w r3, r7, #512 @ 0x200 + 8005366: f5a3 7394 sub.w r3, r3, #296 @ 0x128 + 800536a: 681b ldr r3, [r3, #0] + 800536c: fa93 f2a3 rbit r2, r3 + 8005370: f507 7300 add.w r3, r7, #512 @ 0x200 + 8005374: f5a3 7396 sub.w r3, r3, #300 @ 0x12c + 8005378: 601a str r2, [r3, #0] + 800537a: f507 7300 add.w r3, r7, #512 @ 0x200 + 800537e: f5a3 7398 sub.w r3, r3, #304 @ 0x130 + 8005382: 2202 movs r2, #2 + 8005384: 601a str r2, [r3, #0] + 8005386: f507 7300 add.w r3, r7, #512 @ 0x200 + 800538a: f5a3 7398 sub.w r3, r3, #304 @ 0x130 + 800538e: 681b ldr r3, [r3, #0] + 8005390: fa93 f2a3 rbit r2, r3 + 8005394: f507 7300 add.w r3, r7, #512 @ 0x200 + 8005398: f5a3 739a sub.w r3, r3, #308 @ 0x134 + 800539c: 601a str r2, [r3, #0] while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) - 8005302: 4b41 ldr r3, [pc, #260] @ (8005408 ) - 8005304: 6a5a ldr r2, [r3, #36] @ 0x24 - 8005306: f507 7300 add.w r3, r7, #512 @ 0x200 - 800530a: f5a3 739c sub.w r3, r3, #312 @ 0x138 - 800530e: 2102 movs r1, #2 - 8005310: 6019 str r1, [r3, #0] - 8005312: f507 7300 add.w r3, r7, #512 @ 0x200 - 8005316: f5a3 739c sub.w r3, r3, #312 @ 0x138 - 800531a: 681b ldr r3, [r3, #0] - 800531c: fa93 f1a3 rbit r1, r3 - 8005320: f507 7300 add.w r3, r7, #512 @ 0x200 - 8005324: f5a3 739e sub.w r3, r3, #316 @ 0x13c - 8005328: 6019 str r1, [r3, #0] + 800539e: 4b41 ldr r3, [pc, #260] @ (80054a4 ) + 80053a0: 6a5a ldr r2, [r3, #36] @ 0x24 + 80053a2: f507 7300 add.w r3, r7, #512 @ 0x200 + 80053a6: f5a3 739c sub.w r3, r3, #312 @ 0x138 + 80053aa: 2102 movs r1, #2 + 80053ac: 6019 str r1, [r3, #0] + 80053ae: f507 7300 add.w r3, r7, #512 @ 0x200 + 80053b2: f5a3 739c sub.w r3, r3, #312 @ 0x138 + 80053b6: 681b ldr r3, [r3, #0] + 80053b8: fa93 f1a3 rbit r1, r3 + 80053bc: f507 7300 add.w r3, r7, #512 @ 0x200 + 80053c0: f5a3 739e sub.w r3, r3, #316 @ 0x13c + 80053c4: 6019 str r1, [r3, #0] return result; - 800532a: f507 7300 add.w r3, r7, #512 @ 0x200 - 800532e: f5a3 739e sub.w r3, r3, #316 @ 0x13c - 8005332: 681b ldr r3, [r3, #0] - 8005334: fab3 f383 clz r3, r3 - 8005338: b2db uxtb r3, r3 - 800533a: f043 0360 orr.w r3, r3, #96 @ 0x60 - 800533e: b2db uxtb r3, r3 - 8005340: f003 031f and.w r3, r3, #31 - 8005344: 2101 movs r1, #1 - 8005346: fa01 f303 lsl.w r3, r1, r3 - 800534a: 4013 ands r3, r2 - 800534c: 2b00 cmp r3, #0 - 800534e: d197 bne.n 8005280 + 80053c6: f507 7300 add.w r3, r7, #512 @ 0x200 + 80053ca: f5a3 739e sub.w r3, r3, #316 @ 0x13c + 80053ce: 681b ldr r3, [r3, #0] + 80053d0: fab3 f383 clz r3, r3 + 80053d4: b2db uxtb r3, r3 + 80053d6: f043 0360 orr.w r3, r3, #96 @ 0x60 + 80053da: b2db uxtb r3, r3 + 80053dc: f003 031f and.w r3, r3, #31 + 80053e0: 2101 movs r1, #1 + 80053e2: fa01 f303 lsl.w r3, r1, r3 + 80053e6: 4013 ands r3, r2 + 80053e8: 2b00 cmp r3, #0 + 80053ea: d197 bne.n 800531c } } } } /*------------------------------ LSE Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) - 8005350: f507 7300 add.w r3, r7, #512 @ 0x200 - 8005354: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc - 8005358: 681b ldr r3, [r3, #0] - 800535a: 681b ldr r3, [r3, #0] - 800535c: f003 0304 and.w r3, r3, #4 - 8005360: 2b00 cmp r3, #0 - 8005362: f000 81a1 beq.w 80056a8 + 80053ec: f507 7300 add.w r3, r7, #512 @ 0x200 + 80053f0: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc + 80053f4: 681b ldr r3, [r3, #0] + 80053f6: 681b ldr r3, [r3, #0] + 80053f8: f003 0304 and.w r3, r3, #4 + 80053fc: 2b00 cmp r3, #0 + 80053fe: f000 81a1 beq.w 8005744 { FlagStatus pwrclkchanged = RESET; - 8005366: 2300 movs r3, #0 - 8005368: f887 31ff strb.w r3, [r7, #511] @ 0x1ff + 8005402: 2300 movs r3, #0 + 8005404: f887 31ff strb.w r3, [r7, #511] @ 0x1ff /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if(__HAL_RCC_PWR_IS_CLK_DISABLED()) - 800536c: 4b26 ldr r3, [pc, #152] @ (8005408 ) - 800536e: 69db ldr r3, [r3, #28] - 8005370: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 - 8005374: 2b00 cmp r3, #0 - 8005376: d116 bne.n 80053a6 + 8005408: 4b26 ldr r3, [pc, #152] @ (80054a4 ) + 800540a: 69db ldr r3, [r3, #28] + 800540c: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 8005410: 2b00 cmp r3, #0 + 8005412: d116 bne.n 8005442 { __HAL_RCC_PWR_CLK_ENABLE(); - 8005378: 4b23 ldr r3, [pc, #140] @ (8005408 ) - 800537a: 69db ldr r3, [r3, #28] - 800537c: 4a22 ldr r2, [pc, #136] @ (8005408 ) - 800537e: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 - 8005382: 61d3 str r3, [r2, #28] - 8005384: 4b20 ldr r3, [pc, #128] @ (8005408 ) - 8005386: 69db ldr r3, [r3, #28] - 8005388: f003 5280 and.w r2, r3, #268435456 @ 0x10000000 - 800538c: f507 7300 add.w r3, r7, #512 @ 0x200 - 8005390: f5a3 73fc sub.w r3, r3, #504 @ 0x1f8 - 8005394: 601a str r2, [r3, #0] - 8005396: f507 7300 add.w r3, r7, #512 @ 0x200 - 800539a: f5a3 73fc sub.w r3, r3, #504 @ 0x1f8 - 800539e: 681b ldr r3, [r3, #0] + 8005414: 4b23 ldr r3, [pc, #140] @ (80054a4 ) + 8005416: 69db ldr r3, [r3, #28] + 8005418: 4a22 ldr r2, [pc, #136] @ (80054a4 ) + 800541a: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 800541e: 61d3 str r3, [r2, #28] + 8005420: 4b20 ldr r3, [pc, #128] @ (80054a4 ) + 8005422: 69db ldr r3, [r3, #28] + 8005424: f003 5280 and.w r2, r3, #268435456 @ 0x10000000 + 8005428: f507 7300 add.w r3, r7, #512 @ 0x200 + 800542c: f5a3 73fc sub.w r3, r3, #504 @ 0x1f8 + 8005430: 601a str r2, [r3, #0] + 8005432: f507 7300 add.w r3, r7, #512 @ 0x200 + 8005436: f5a3 73fc sub.w r3, r3, #504 @ 0x1f8 + 800543a: 681b ldr r3, [r3, #0] pwrclkchanged = SET; - 80053a0: 2301 movs r3, #1 - 80053a2: f887 31ff strb.w r3, [r7, #511] @ 0x1ff + 800543c: 2301 movs r3, #1 + 800543e: f887 31ff strb.w r3, [r7, #511] @ 0x1ff } if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) - 80053a6: 4b1a ldr r3, [pc, #104] @ (8005410 ) - 80053a8: 681b ldr r3, [r3, #0] - 80053aa: f403 7380 and.w r3, r3, #256 @ 0x100 - 80053ae: 2b00 cmp r3, #0 - 80053b0: d11a bne.n 80053e8 + 8005442: 4b1a ldr r3, [pc, #104] @ (80054ac ) + 8005444: 681b ldr r3, [r3, #0] + 8005446: f403 7380 and.w r3, r3, #256 @ 0x100 + 800544a: 2b00 cmp r3, #0 + 800544c: d11a bne.n 8005484 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); - 80053b2: 4b17 ldr r3, [pc, #92] @ (8005410 ) - 80053b4: 681b ldr r3, [r3, #0] - 80053b6: 4a16 ldr r2, [pc, #88] @ (8005410 ) - 80053b8: f443 7380 orr.w r3, r3, #256 @ 0x100 - 80053bc: 6013 str r3, [r2, #0] + 800544e: 4b17 ldr r3, [pc, #92] @ (80054ac ) + 8005450: 681b ldr r3, [r3, #0] + 8005452: 4a16 ldr r2, [pc, #88] @ (80054ac ) + 8005454: f443 7380 orr.w r3, r3, #256 @ 0x100 + 8005458: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); - 80053be: f7fc ff53 bl 8002268 - 80053c2: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8 + 800545a: f7fc ff53 bl 8002304 + 800545e: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8 while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) - 80053c6: e009 b.n 80053dc + 8005462: e009 b.n 8005478 { if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) - 80053c8: f7fc ff4e bl 8002268 - 80053cc: 4602 mov r2, r0 - 80053ce: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8 - 80053d2: 1ad3 subs r3, r2, r3 - 80053d4: 2b64 cmp r3, #100 @ 0x64 - 80053d6: d901 bls.n 80053dc + 8005464: f7fc ff4e bl 8002304 + 8005468: 4602 mov r2, r0 + 800546a: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8 + 800546e: 1ad3 subs r3, r2, r3 + 8005470: 2b64 cmp r3, #100 @ 0x64 + 8005472: d901 bls.n 8005478 { return HAL_TIMEOUT; - 80053d8: 2303 movs r3, #3 - 80053da: e3b1 b.n 8005b40 + 8005474: 2303 movs r3, #3 + 8005476: e3b1 b.n 8005bdc while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) - 80053dc: 4b0c ldr r3, [pc, #48] @ (8005410 ) - 80053de: 681b ldr r3, [r3, #0] - 80053e0: f403 7380 and.w r3, r3, #256 @ 0x100 - 80053e4: 2b00 cmp r3, #0 - 80053e6: d0ef beq.n 80053c8 + 8005478: 4b0c ldr r3, [pc, #48] @ (80054ac ) + 800547a: 681b ldr r3, [r3, #0] + 800547c: f403 7380 and.w r3, r3, #256 @ 0x100 + 8005480: 2b00 cmp r3, #0 + 8005482: d0ef beq.n 8005464 } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); - 80053e8: f507 7300 add.w r3, r7, #512 @ 0x200 - 80053ec: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc - 80053f0: 681b ldr r3, [r3, #0] - 80053f2: 68db ldr r3, [r3, #12] - 80053f4: 2b01 cmp r3, #1 - 80053f6: d10d bne.n 8005414 - 80053f8: 4b03 ldr r3, [pc, #12] @ (8005408 ) - 80053fa: 6a1b ldr r3, [r3, #32] - 80053fc: 4a02 ldr r2, [pc, #8] @ (8005408 ) - 80053fe: f043 0301 orr.w r3, r3, #1 - 8005402: 6213 str r3, [r2, #32] - 8005404: e03c b.n 8005480 - 8005406: bf00 nop - 8005408: 40021000 .word 0x40021000 - 800540c: 10908120 .word 0x10908120 - 8005410: 40007000 .word 0x40007000 - 8005414: f507 7300 add.w r3, r7, #512 @ 0x200 - 8005418: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc - 800541c: 681b ldr r3, [r3, #0] - 800541e: 68db ldr r3, [r3, #12] - 8005420: 2b00 cmp r3, #0 - 8005422: d10c bne.n 800543e - 8005424: 4bc1 ldr r3, [pc, #772] @ (800572c ) - 8005426: 6a1b ldr r3, [r3, #32] - 8005428: 4ac0 ldr r2, [pc, #768] @ (800572c ) - 800542a: f023 0301 bic.w r3, r3, #1 - 800542e: 6213 str r3, [r2, #32] - 8005430: 4bbe ldr r3, [pc, #760] @ (800572c ) - 8005432: 6a1b ldr r3, [r3, #32] - 8005434: 4abd ldr r2, [pc, #756] @ (800572c ) - 8005436: f023 0304 bic.w r3, r3, #4 - 800543a: 6213 str r3, [r2, #32] - 800543c: e020 b.n 8005480 - 800543e: f507 7300 add.w r3, r7, #512 @ 0x200 - 8005442: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc - 8005446: 681b ldr r3, [r3, #0] - 8005448: 68db ldr r3, [r3, #12] - 800544a: 2b05 cmp r3, #5 - 800544c: d10c bne.n 8005468 - 800544e: 4bb7 ldr r3, [pc, #732] @ (800572c ) - 8005450: 6a1b ldr r3, [r3, #32] - 8005452: 4ab6 ldr r2, [pc, #728] @ (800572c ) - 8005454: f043 0304 orr.w r3, r3, #4 - 8005458: 6213 str r3, [r2, #32] - 800545a: 4bb4 ldr r3, [pc, #720] @ (800572c ) - 800545c: 6a1b ldr r3, [r3, #32] - 800545e: 4ab3 ldr r2, [pc, #716] @ (800572c ) - 8005460: f043 0301 orr.w r3, r3, #1 - 8005464: 6213 str r3, [r2, #32] - 8005466: e00b b.n 8005480 - 8005468: 4bb0 ldr r3, [pc, #704] @ (800572c ) - 800546a: 6a1b ldr r3, [r3, #32] - 800546c: 4aaf ldr r2, [pc, #700] @ (800572c ) - 800546e: f023 0301 bic.w r3, r3, #1 - 8005472: 6213 str r3, [r2, #32] - 8005474: 4bad ldr r3, [pc, #692] @ (800572c ) - 8005476: 6a1b ldr r3, [r3, #32] - 8005478: 4aac ldr r2, [pc, #688] @ (800572c ) - 800547a: f023 0304 bic.w r3, r3, #4 - 800547e: 6213 str r3, [r2, #32] + 8005484: f507 7300 add.w r3, r7, #512 @ 0x200 + 8005488: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc + 800548c: 681b ldr r3, [r3, #0] + 800548e: 68db ldr r3, [r3, #12] + 8005490: 2b01 cmp r3, #1 + 8005492: d10d bne.n 80054b0 + 8005494: 4b03 ldr r3, [pc, #12] @ (80054a4 ) + 8005496: 6a1b ldr r3, [r3, #32] + 8005498: 4a02 ldr r2, [pc, #8] @ (80054a4 ) + 800549a: f043 0301 orr.w r3, r3, #1 + 800549e: 6213 str r3, [r2, #32] + 80054a0: e03c b.n 800551c + 80054a2: bf00 nop + 80054a4: 40021000 .word 0x40021000 + 80054a8: 10908120 .word 0x10908120 + 80054ac: 40007000 .word 0x40007000 + 80054b0: f507 7300 add.w r3, r7, #512 @ 0x200 + 80054b4: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc + 80054b8: 681b ldr r3, [r3, #0] + 80054ba: 68db ldr r3, [r3, #12] + 80054bc: 2b00 cmp r3, #0 + 80054be: d10c bne.n 80054da + 80054c0: 4bc1 ldr r3, [pc, #772] @ (80057c8 ) + 80054c2: 6a1b ldr r3, [r3, #32] + 80054c4: 4ac0 ldr r2, [pc, #768] @ (80057c8 ) + 80054c6: f023 0301 bic.w r3, r3, #1 + 80054ca: 6213 str r3, [r2, #32] + 80054cc: 4bbe ldr r3, [pc, #760] @ (80057c8 ) + 80054ce: 6a1b ldr r3, [r3, #32] + 80054d0: 4abd ldr r2, [pc, #756] @ (80057c8 ) + 80054d2: f023 0304 bic.w r3, r3, #4 + 80054d6: 6213 str r3, [r2, #32] + 80054d8: e020 b.n 800551c + 80054da: f507 7300 add.w r3, r7, #512 @ 0x200 + 80054de: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc + 80054e2: 681b ldr r3, [r3, #0] + 80054e4: 68db ldr r3, [r3, #12] + 80054e6: 2b05 cmp r3, #5 + 80054e8: d10c bne.n 8005504 + 80054ea: 4bb7 ldr r3, [pc, #732] @ (80057c8 ) + 80054ec: 6a1b ldr r3, [r3, #32] + 80054ee: 4ab6 ldr r2, [pc, #728] @ (80057c8 ) + 80054f0: f043 0304 orr.w r3, r3, #4 + 80054f4: 6213 str r3, [r2, #32] + 80054f6: 4bb4 ldr r3, [pc, #720] @ (80057c8 ) + 80054f8: 6a1b ldr r3, [r3, #32] + 80054fa: 4ab3 ldr r2, [pc, #716] @ (80057c8 ) + 80054fc: f043 0301 orr.w r3, r3, #1 + 8005500: 6213 str r3, [r2, #32] + 8005502: e00b b.n 800551c + 8005504: 4bb0 ldr r3, [pc, #704] @ (80057c8 ) + 8005506: 6a1b ldr r3, [r3, #32] + 8005508: 4aaf ldr r2, [pc, #700] @ (80057c8 ) + 800550a: f023 0301 bic.w r3, r3, #1 + 800550e: 6213 str r3, [r2, #32] + 8005510: 4bad ldr r3, [pc, #692] @ (80057c8 ) + 8005512: 6a1b ldr r3, [r3, #32] + 8005514: 4aac ldr r2, [pc, #688] @ (80057c8 ) + 8005516: f023 0304 bic.w r3, r3, #4 + 800551a: 6213 str r3, [r2, #32] /* Check the LSE State */ if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF) - 8005480: f507 7300 add.w r3, r7, #512 @ 0x200 - 8005484: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc - 8005488: 681b ldr r3, [r3, #0] - 800548a: 68db ldr r3, [r3, #12] - 800548c: 2b00 cmp r3, #0 - 800548e: f000 8081 beq.w 8005594 + 800551c: f507 7300 add.w r3, r7, #512 @ 0x200 + 8005520: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc + 8005524: 681b ldr r3, [r3, #0] + 8005526: 68db ldr r3, [r3, #12] + 8005528: 2b00 cmp r3, #0 + 800552a: f000 8081 beq.w 8005630 { /* Get Start Tick */ tickstart = HAL_GetTick(); - 8005492: f7fc fee9 bl 8002268 - 8005496: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8 + 800552e: f7fc fee9 bl 8002304 + 8005532: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8 /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) - 800549a: e00b b.n 80054b4 + 8005536: e00b b.n 8005550 { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) - 800549c: f7fc fee4 bl 8002268 - 80054a0: 4602 mov r2, r0 - 80054a2: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8 - 80054a6: 1ad3 subs r3, r2, r3 - 80054a8: f241 3288 movw r2, #5000 @ 0x1388 - 80054ac: 4293 cmp r3, r2 - 80054ae: d901 bls.n 80054b4 + 8005538: f7fc fee4 bl 8002304 + 800553c: 4602 mov r2, r0 + 800553e: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8 + 8005542: 1ad3 subs r3, r2, r3 + 8005544: f241 3288 movw r2, #5000 @ 0x1388 + 8005548: 4293 cmp r3, r2 + 800554a: d901 bls.n 8005550 { return HAL_TIMEOUT; - 80054b0: 2303 movs r3, #3 - 80054b2: e345 b.n 8005b40 - 80054b4: f507 7300 add.w r3, r7, #512 @ 0x200 - 80054b8: f5a3 73a0 sub.w r3, r3, #320 @ 0x140 - 80054bc: 2202 movs r2, #2 - 80054be: 601a str r2, [r3, #0] + 800554c: 2303 movs r3, #3 + 800554e: e345 b.n 8005bdc + 8005550: f507 7300 add.w r3, r7, #512 @ 0x200 + 8005554: f5a3 73a0 sub.w r3, r3, #320 @ 0x140 + 8005558: 2202 movs r2, #2 + 800555a: 601a str r2, [r3, #0] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 80054c0: f507 7300 add.w r3, r7, #512 @ 0x200 - 80054c4: f5a3 73a0 sub.w r3, r3, #320 @ 0x140 - 80054c8: 681b ldr r3, [r3, #0] - 80054ca: fa93 f2a3 rbit r2, r3 - 80054ce: f507 7300 add.w r3, r7, #512 @ 0x200 - 80054d2: f5a3 73a2 sub.w r3, r3, #324 @ 0x144 - 80054d6: 601a str r2, [r3, #0] - 80054d8: f507 7300 add.w r3, r7, #512 @ 0x200 - 80054dc: f5a3 73a4 sub.w r3, r3, #328 @ 0x148 - 80054e0: 2202 movs r2, #2 - 80054e2: 601a str r2, [r3, #0] - 80054e4: f507 7300 add.w r3, r7, #512 @ 0x200 - 80054e8: f5a3 73a4 sub.w r3, r3, #328 @ 0x148 - 80054ec: 681b ldr r3, [r3, #0] - 80054ee: fa93 f2a3 rbit r2, r3 - 80054f2: f507 7300 add.w r3, r7, #512 @ 0x200 - 80054f6: f5a3 73a6 sub.w r3, r3, #332 @ 0x14c - 80054fa: 601a str r2, [r3, #0] + 800555c: f507 7300 add.w r3, r7, #512 @ 0x200 + 8005560: f5a3 73a0 sub.w r3, r3, #320 @ 0x140 + 8005564: 681b ldr r3, [r3, #0] + 8005566: fa93 f2a3 rbit r2, r3 + 800556a: f507 7300 add.w r3, r7, #512 @ 0x200 + 800556e: f5a3 73a2 sub.w r3, r3, #324 @ 0x144 + 8005572: 601a str r2, [r3, #0] + 8005574: f507 7300 add.w r3, r7, #512 @ 0x200 + 8005578: f5a3 73a4 sub.w r3, r3, #328 @ 0x148 + 800557c: 2202 movs r2, #2 + 800557e: 601a str r2, [r3, #0] + 8005580: f507 7300 add.w r3, r7, #512 @ 0x200 + 8005584: f5a3 73a4 sub.w r3, r3, #328 @ 0x148 + 8005588: 681b ldr r3, [r3, #0] + 800558a: fa93 f2a3 rbit r2, r3 + 800558e: f507 7300 add.w r3, r7, #512 @ 0x200 + 8005592: f5a3 73a6 sub.w r3, r3, #332 @ 0x14c + 8005596: 601a str r2, [r3, #0] return result; - 80054fc: f507 7300 add.w r3, r7, #512 @ 0x200 - 8005500: f5a3 73a6 sub.w r3, r3, #332 @ 0x14c - 8005504: 681b ldr r3, [r3, #0] + 8005598: f507 7300 add.w r3, r7, #512 @ 0x200 + 800559c: f5a3 73a6 sub.w r3, r3, #332 @ 0x14c + 80055a0: 681b ldr r3, [r3, #0] while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) - 8005506: fab3 f383 clz r3, r3 - 800550a: b2db uxtb r3, r3 - 800550c: 095b lsrs r3, r3, #5 - 800550e: b2db uxtb r3, r3 - 8005510: f043 0302 orr.w r3, r3, #2 - 8005514: b2db uxtb r3, r3 - 8005516: 2b02 cmp r3, #2 - 8005518: d102 bne.n 8005520 - 800551a: 4b84 ldr r3, [pc, #528] @ (800572c ) - 800551c: 6a1b ldr r3, [r3, #32] - 800551e: e013 b.n 8005548 - 8005520: f507 7300 add.w r3, r7, #512 @ 0x200 - 8005524: f5a3 73a8 sub.w r3, r3, #336 @ 0x150 - 8005528: 2202 movs r2, #2 - 800552a: 601a str r2, [r3, #0] + 80055a2: fab3 f383 clz r3, r3 + 80055a6: b2db uxtb r3, r3 + 80055a8: 095b lsrs r3, r3, #5 + 80055aa: b2db uxtb r3, r3 + 80055ac: f043 0302 orr.w r3, r3, #2 + 80055b0: b2db uxtb r3, r3 + 80055b2: 2b02 cmp r3, #2 + 80055b4: d102 bne.n 80055bc + 80055b6: 4b84 ldr r3, [pc, #528] @ (80057c8 ) + 80055b8: 6a1b ldr r3, [r3, #32] + 80055ba: e013 b.n 80055e4 + 80055bc: f507 7300 add.w r3, r7, #512 @ 0x200 + 80055c0: f5a3 73a8 sub.w r3, r3, #336 @ 0x150 + 80055c4: 2202 movs r2, #2 + 80055c6: 601a str r2, [r3, #0] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 800552c: f507 7300 add.w r3, r7, #512 @ 0x200 - 8005530: f5a3 73a8 sub.w r3, r3, #336 @ 0x150 - 8005534: 681b ldr r3, [r3, #0] - 8005536: fa93 f2a3 rbit r2, r3 - 800553a: f507 7300 add.w r3, r7, #512 @ 0x200 - 800553e: f5a3 73aa sub.w r3, r3, #340 @ 0x154 - 8005542: 601a str r2, [r3, #0] - 8005544: 4b79 ldr r3, [pc, #484] @ (800572c ) - 8005546: 6a5b ldr r3, [r3, #36] @ 0x24 - 8005548: f507 7200 add.w r2, r7, #512 @ 0x200 - 800554c: f5a2 72ac sub.w r2, r2, #344 @ 0x158 - 8005550: 2102 movs r1, #2 - 8005552: 6011 str r1, [r2, #0] - 8005554: f507 7200 add.w r2, r7, #512 @ 0x200 - 8005558: f5a2 72ac sub.w r2, r2, #344 @ 0x158 - 800555c: 6812 ldr r2, [r2, #0] - 800555e: fa92 f1a2 rbit r1, r2 - 8005562: f507 7200 add.w r2, r7, #512 @ 0x200 - 8005566: f5a2 72ae sub.w r2, r2, #348 @ 0x15c - 800556a: 6011 str r1, [r2, #0] + 80055c8: f507 7300 add.w r3, r7, #512 @ 0x200 + 80055cc: f5a3 73a8 sub.w r3, r3, #336 @ 0x150 + 80055d0: 681b ldr r3, [r3, #0] + 80055d2: fa93 f2a3 rbit r2, r3 + 80055d6: f507 7300 add.w r3, r7, #512 @ 0x200 + 80055da: f5a3 73aa sub.w r3, r3, #340 @ 0x154 + 80055de: 601a str r2, [r3, #0] + 80055e0: 4b79 ldr r3, [pc, #484] @ (80057c8 ) + 80055e2: 6a5b ldr r3, [r3, #36] @ 0x24 + 80055e4: f507 7200 add.w r2, r7, #512 @ 0x200 + 80055e8: f5a2 72ac sub.w r2, r2, #344 @ 0x158 + 80055ec: 2102 movs r1, #2 + 80055ee: 6011 str r1, [r2, #0] + 80055f0: f507 7200 add.w r2, r7, #512 @ 0x200 + 80055f4: f5a2 72ac sub.w r2, r2, #344 @ 0x158 + 80055f8: 6812 ldr r2, [r2, #0] + 80055fa: fa92 f1a2 rbit r1, r2 + 80055fe: f507 7200 add.w r2, r7, #512 @ 0x200 + 8005602: f5a2 72ae sub.w r2, r2, #348 @ 0x15c + 8005606: 6011 str r1, [r2, #0] return result; - 800556c: f507 7200 add.w r2, r7, #512 @ 0x200 - 8005570: f5a2 72ae sub.w r2, r2, #348 @ 0x15c - 8005574: 6812 ldr r2, [r2, #0] - 8005576: fab2 f282 clz r2, r2 - 800557a: b2d2 uxtb r2, r2 - 800557c: f042 0240 orr.w r2, r2, #64 @ 0x40 - 8005580: b2d2 uxtb r2, r2 - 8005582: f002 021f and.w r2, r2, #31 - 8005586: 2101 movs r1, #1 - 8005588: fa01 f202 lsl.w r2, r1, r2 - 800558c: 4013 ands r3, r2 - 800558e: 2b00 cmp r3, #0 - 8005590: d084 beq.n 800549c - 8005592: e07f b.n 8005694 + 8005608: f507 7200 add.w r2, r7, #512 @ 0x200 + 800560c: f5a2 72ae sub.w r2, r2, #348 @ 0x15c + 8005610: 6812 ldr r2, [r2, #0] + 8005612: fab2 f282 clz r2, r2 + 8005616: b2d2 uxtb r2, r2 + 8005618: f042 0240 orr.w r2, r2, #64 @ 0x40 + 800561c: b2d2 uxtb r2, r2 + 800561e: f002 021f and.w r2, r2, #31 + 8005622: 2101 movs r1, #1 + 8005624: fa01 f202 lsl.w r2, r1, r2 + 8005628: 4013 ands r3, r2 + 800562a: 2b00 cmp r3, #0 + 800562c: d084 beq.n 8005538 + 800562e: e07f b.n 8005730 } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); - 8005594: f7fc fe68 bl 8002268 - 8005598: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8 + 8005630: f7fc fe68 bl 8002304 + 8005634: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8 /* Wait till LSE is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) - 800559c: e00b b.n 80055b6 + 8005638: e00b b.n 8005652 { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) - 800559e: f7fc fe63 bl 8002268 - 80055a2: 4602 mov r2, r0 - 80055a4: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8 - 80055a8: 1ad3 subs r3, r2, r3 - 80055aa: f241 3288 movw r2, #5000 @ 0x1388 - 80055ae: 4293 cmp r3, r2 - 80055b0: d901 bls.n 80055b6 + 800563a: f7fc fe63 bl 8002304 + 800563e: 4602 mov r2, r0 + 8005640: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8 + 8005644: 1ad3 subs r3, r2, r3 + 8005646: f241 3288 movw r2, #5000 @ 0x1388 + 800564a: 4293 cmp r3, r2 + 800564c: d901 bls.n 8005652 { return HAL_TIMEOUT; - 80055b2: 2303 movs r3, #3 - 80055b4: e2c4 b.n 8005b40 - 80055b6: f507 7300 add.w r3, r7, #512 @ 0x200 - 80055ba: f5a3 73b0 sub.w r3, r3, #352 @ 0x160 - 80055be: 2202 movs r2, #2 - 80055c0: 601a str r2, [r3, #0] + 800564e: 2303 movs r3, #3 + 8005650: e2c4 b.n 8005bdc + 8005652: f507 7300 add.w r3, r7, #512 @ 0x200 + 8005656: f5a3 73b0 sub.w r3, r3, #352 @ 0x160 + 800565a: 2202 movs r2, #2 + 800565c: 601a str r2, [r3, #0] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 80055c2: f507 7300 add.w r3, r7, #512 @ 0x200 - 80055c6: f5a3 73b0 sub.w r3, r3, #352 @ 0x160 - 80055ca: 681b ldr r3, [r3, #0] - 80055cc: fa93 f2a3 rbit r2, r3 - 80055d0: f507 7300 add.w r3, r7, #512 @ 0x200 - 80055d4: f5a3 73b2 sub.w r3, r3, #356 @ 0x164 - 80055d8: 601a str r2, [r3, #0] - 80055da: f507 7300 add.w r3, r7, #512 @ 0x200 - 80055de: f5a3 73b4 sub.w r3, r3, #360 @ 0x168 - 80055e2: 2202 movs r2, #2 - 80055e4: 601a str r2, [r3, #0] - 80055e6: f507 7300 add.w r3, r7, #512 @ 0x200 - 80055ea: f5a3 73b4 sub.w r3, r3, #360 @ 0x168 - 80055ee: 681b ldr r3, [r3, #0] - 80055f0: fa93 f2a3 rbit r2, r3 - 80055f4: f507 7300 add.w r3, r7, #512 @ 0x200 - 80055f8: f5a3 73b6 sub.w r3, r3, #364 @ 0x16c - 80055fc: 601a str r2, [r3, #0] + 800565e: f507 7300 add.w r3, r7, #512 @ 0x200 + 8005662: f5a3 73b0 sub.w r3, r3, #352 @ 0x160 + 8005666: 681b ldr r3, [r3, #0] + 8005668: fa93 f2a3 rbit r2, r3 + 800566c: f507 7300 add.w r3, r7, #512 @ 0x200 + 8005670: f5a3 73b2 sub.w r3, r3, #356 @ 0x164 + 8005674: 601a str r2, [r3, #0] + 8005676: f507 7300 add.w r3, r7, #512 @ 0x200 + 800567a: f5a3 73b4 sub.w r3, r3, #360 @ 0x168 + 800567e: 2202 movs r2, #2 + 8005680: 601a str r2, [r3, #0] + 8005682: f507 7300 add.w r3, r7, #512 @ 0x200 + 8005686: f5a3 73b4 sub.w r3, r3, #360 @ 0x168 + 800568a: 681b ldr r3, [r3, #0] + 800568c: fa93 f2a3 rbit r2, r3 + 8005690: f507 7300 add.w r3, r7, #512 @ 0x200 + 8005694: f5a3 73b6 sub.w r3, r3, #364 @ 0x16c + 8005698: 601a str r2, [r3, #0] return result; - 80055fe: f507 7300 add.w r3, r7, #512 @ 0x200 - 8005602: f5a3 73b6 sub.w r3, r3, #364 @ 0x16c - 8005606: 681b ldr r3, [r3, #0] + 800569a: f507 7300 add.w r3, r7, #512 @ 0x200 + 800569e: f5a3 73b6 sub.w r3, r3, #364 @ 0x16c + 80056a2: 681b ldr r3, [r3, #0] while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) - 8005608: fab3 f383 clz r3, r3 - 800560c: b2db uxtb r3, r3 - 800560e: 095b lsrs r3, r3, #5 - 8005610: b2db uxtb r3, r3 - 8005612: f043 0302 orr.w r3, r3, #2 - 8005616: b2db uxtb r3, r3 - 8005618: 2b02 cmp r3, #2 - 800561a: d102 bne.n 8005622 - 800561c: 4b43 ldr r3, [pc, #268] @ (800572c ) - 800561e: 6a1b ldr r3, [r3, #32] - 8005620: e013 b.n 800564a - 8005622: f507 7300 add.w r3, r7, #512 @ 0x200 - 8005626: f5a3 73b8 sub.w r3, r3, #368 @ 0x170 - 800562a: 2202 movs r2, #2 - 800562c: 601a str r2, [r3, #0] + 80056a4: fab3 f383 clz r3, r3 + 80056a8: b2db uxtb r3, r3 + 80056aa: 095b lsrs r3, r3, #5 + 80056ac: b2db uxtb r3, r3 + 80056ae: f043 0302 orr.w r3, r3, #2 + 80056b2: b2db uxtb r3, r3 + 80056b4: 2b02 cmp r3, #2 + 80056b6: d102 bne.n 80056be + 80056b8: 4b43 ldr r3, [pc, #268] @ (80057c8 ) + 80056ba: 6a1b ldr r3, [r3, #32] + 80056bc: e013 b.n 80056e6 + 80056be: f507 7300 add.w r3, r7, #512 @ 0x200 + 80056c2: f5a3 73b8 sub.w r3, r3, #368 @ 0x170 + 80056c6: 2202 movs r2, #2 + 80056c8: 601a str r2, [r3, #0] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 800562e: f507 7300 add.w r3, r7, #512 @ 0x200 - 8005632: f5a3 73b8 sub.w r3, r3, #368 @ 0x170 - 8005636: 681b ldr r3, [r3, #0] - 8005638: fa93 f2a3 rbit r2, r3 - 800563c: f507 7300 add.w r3, r7, #512 @ 0x200 - 8005640: f5a3 73ba sub.w r3, r3, #372 @ 0x174 - 8005644: 601a str r2, [r3, #0] - 8005646: 4b39 ldr r3, [pc, #228] @ (800572c ) - 8005648: 6a5b ldr r3, [r3, #36] @ 0x24 - 800564a: f507 7200 add.w r2, r7, #512 @ 0x200 - 800564e: f5a2 72bc sub.w r2, r2, #376 @ 0x178 - 8005652: 2102 movs r1, #2 - 8005654: 6011 str r1, [r2, #0] - 8005656: f507 7200 add.w r2, r7, #512 @ 0x200 - 800565a: f5a2 72bc sub.w r2, r2, #376 @ 0x178 - 800565e: 6812 ldr r2, [r2, #0] - 8005660: fa92 f1a2 rbit r1, r2 - 8005664: f507 7200 add.w r2, r7, #512 @ 0x200 - 8005668: f5a2 72be sub.w r2, r2, #380 @ 0x17c - 800566c: 6011 str r1, [r2, #0] + 80056ca: f507 7300 add.w r3, r7, #512 @ 0x200 + 80056ce: f5a3 73b8 sub.w r3, r3, #368 @ 0x170 + 80056d2: 681b ldr r3, [r3, #0] + 80056d4: fa93 f2a3 rbit r2, r3 + 80056d8: f507 7300 add.w r3, r7, #512 @ 0x200 + 80056dc: f5a3 73ba sub.w r3, r3, #372 @ 0x174 + 80056e0: 601a str r2, [r3, #0] + 80056e2: 4b39 ldr r3, [pc, #228] @ (80057c8 ) + 80056e4: 6a5b ldr r3, [r3, #36] @ 0x24 + 80056e6: f507 7200 add.w r2, r7, #512 @ 0x200 + 80056ea: f5a2 72bc sub.w r2, r2, #376 @ 0x178 + 80056ee: 2102 movs r1, #2 + 80056f0: 6011 str r1, [r2, #0] + 80056f2: f507 7200 add.w r2, r7, #512 @ 0x200 + 80056f6: f5a2 72bc sub.w r2, r2, #376 @ 0x178 + 80056fa: 6812 ldr r2, [r2, #0] + 80056fc: fa92 f1a2 rbit r1, r2 + 8005700: f507 7200 add.w r2, r7, #512 @ 0x200 + 8005704: f5a2 72be sub.w r2, r2, #380 @ 0x17c + 8005708: 6011 str r1, [r2, #0] return result; - 800566e: f507 7200 add.w r2, r7, #512 @ 0x200 - 8005672: f5a2 72be sub.w r2, r2, #380 @ 0x17c - 8005676: 6812 ldr r2, [r2, #0] - 8005678: fab2 f282 clz r2, r2 - 800567c: b2d2 uxtb r2, r2 - 800567e: f042 0240 orr.w r2, r2, #64 @ 0x40 - 8005682: b2d2 uxtb r2, r2 - 8005684: f002 021f and.w r2, r2, #31 - 8005688: 2101 movs r1, #1 - 800568a: fa01 f202 lsl.w r2, r1, r2 - 800568e: 4013 ands r3, r2 - 8005690: 2b00 cmp r3, #0 - 8005692: d184 bne.n 800559e + 800570a: f507 7200 add.w r2, r7, #512 @ 0x200 + 800570e: f5a2 72be sub.w r2, r2, #380 @ 0x17c + 8005712: 6812 ldr r2, [r2, #0] + 8005714: fab2 f282 clz r2, r2 + 8005718: b2d2 uxtb r2, r2 + 800571a: f042 0240 orr.w r2, r2, #64 @ 0x40 + 800571e: b2d2 uxtb r2, r2 + 8005720: f002 021f and.w r2, r2, #31 + 8005724: 2101 movs r1, #1 + 8005726: fa01 f202 lsl.w r2, r1, r2 + 800572a: 4013 ands r3, r2 + 800572c: 2b00 cmp r3, #0 + 800572e: d184 bne.n 800563a } } } /* Require to disable power clock if necessary */ if(pwrclkchanged == SET) - 8005694: f897 31ff ldrb.w r3, [r7, #511] @ 0x1ff - 8005698: 2b01 cmp r3, #1 - 800569a: d105 bne.n 80056a8 + 8005730: f897 31ff ldrb.w r3, [r7, #511] @ 0x1ff + 8005734: 2b01 cmp r3, #1 + 8005736: d105 bne.n 8005744 { __HAL_RCC_PWR_CLK_DISABLE(); - 800569c: 4b23 ldr r3, [pc, #140] @ (800572c ) - 800569e: 69db ldr r3, [r3, #28] - 80056a0: 4a22 ldr r2, [pc, #136] @ (800572c ) - 80056a2: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 - 80056a6: 61d3 str r3, [r2, #28] + 8005738: 4b23 ldr r3, [pc, #140] @ (80057c8 ) + 800573a: 69db ldr r3, [r3, #28] + 800573c: 4a22 ldr r2, [pc, #136] @ (80057c8 ) + 800573e: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 + 8005742: 61d3 str r3, [r2, #28] } /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) - 80056a8: f507 7300 add.w r3, r7, #512 @ 0x200 - 80056ac: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc - 80056b0: 681b ldr r3, [r3, #0] - 80056b2: 69db ldr r3, [r3, #28] - 80056b4: 2b00 cmp r3, #0 - 80056b6: f000 8242 beq.w 8005b3e + 8005744: f507 7300 add.w r3, r7, #512 @ 0x200 + 8005748: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc + 800574c: 681b ldr r3, [r3, #0] + 800574e: 69db ldr r3, [r3, #28] + 8005750: 2b00 cmp r3, #0 + 8005752: f000 8242 beq.w 8005bda { /* Check if the PLL is used as system clock or not */ if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) - 80056ba: 4b1c ldr r3, [pc, #112] @ (800572c ) - 80056bc: 685b ldr r3, [r3, #4] - 80056be: f003 030c and.w r3, r3, #12 - 80056c2: 2b08 cmp r3, #8 - 80056c4: f000 8213 beq.w 8005aee + 8005756: 4b1c ldr r3, [pc, #112] @ (80057c8 ) + 8005758: 685b ldr r3, [r3, #4] + 800575a: f003 030c and.w r3, r3, #12 + 800575e: 2b08 cmp r3, #8 + 8005760: f000 8213 beq.w 8005b8a { if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) - 80056c8: f507 7300 add.w r3, r7, #512 @ 0x200 - 80056cc: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc - 80056d0: 681b ldr r3, [r3, #0] - 80056d2: 69db ldr r3, [r3, #28] - 80056d4: 2b02 cmp r3, #2 - 80056d6: f040 8162 bne.w 800599e - 80056da: f507 7300 add.w r3, r7, #512 @ 0x200 - 80056de: f5a3 73c0 sub.w r3, r3, #384 @ 0x180 - 80056e2: f04f 7280 mov.w r2, #16777216 @ 0x1000000 - 80056e6: 601a str r2, [r3, #0] + 8005764: f507 7300 add.w r3, r7, #512 @ 0x200 + 8005768: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc + 800576c: 681b ldr r3, [r3, #0] + 800576e: 69db ldr r3, [r3, #28] + 8005770: 2b02 cmp r3, #2 + 8005772: f040 8162 bne.w 8005a3a + 8005776: f507 7300 add.w r3, r7, #512 @ 0x200 + 800577a: f5a3 73c0 sub.w r3, r3, #384 @ 0x180 + 800577e: f04f 7280 mov.w r2, #16777216 @ 0x1000000 + 8005782: 601a str r2, [r3, #0] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 80056e8: f507 7300 add.w r3, r7, #512 @ 0x200 - 80056ec: f5a3 73c0 sub.w r3, r3, #384 @ 0x180 - 80056f0: 681b ldr r3, [r3, #0] - 80056f2: fa93 f2a3 rbit r2, r3 - 80056f6: f507 7300 add.w r3, r7, #512 @ 0x200 - 80056fa: f5a3 73c2 sub.w r3, r3, #388 @ 0x184 - 80056fe: 601a str r2, [r3, #0] + 8005784: f507 7300 add.w r3, r7, #512 @ 0x200 + 8005788: f5a3 73c0 sub.w r3, r3, #384 @ 0x180 + 800578c: 681b ldr r3, [r3, #0] + 800578e: fa93 f2a3 rbit r2, r3 + 8005792: f507 7300 add.w r3, r7, #512 @ 0x200 + 8005796: f5a3 73c2 sub.w r3, r3, #388 @ 0x184 + 800579a: 601a str r2, [r3, #0] return result; - 8005700: f507 7300 add.w r3, r7, #512 @ 0x200 - 8005704: f5a3 73c2 sub.w r3, r3, #388 @ 0x184 - 8005708: 681b ldr r3, [r3, #0] + 800579c: f507 7300 add.w r3, r7, #512 @ 0x200 + 80057a0: f5a3 73c2 sub.w r3, r3, #388 @ 0x184 + 80057a4: 681b ldr r3, [r3, #0] #if defined(RCC_CFGR_PLLSRC_HSI_PREDIV) assert_param(IS_RCC_PREDIV(RCC_OscInitStruct->PLL.PREDIV)); #endif /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); - 800570a: fab3 f383 clz r3, r3 - 800570e: b2db uxtb r3, r3 - 8005710: f103 5384 add.w r3, r3, #276824064 @ 0x10800000 - 8005714: f503 1384 add.w r3, r3, #1081344 @ 0x108000 - 8005718: 009b lsls r3, r3, #2 - 800571a: 461a mov r2, r3 - 800571c: 2300 movs r3, #0 - 800571e: 6013 str r3, [r2, #0] + 80057a6: fab3 f383 clz r3, r3 + 80057aa: b2db uxtb r3, r3 + 80057ac: f103 5384 add.w r3, r3, #276824064 @ 0x10800000 + 80057b0: f503 1384 add.w r3, r3, #1081344 @ 0x108000 + 80057b4: 009b lsls r3, r3, #2 + 80057b6: 461a mov r2, r3 + 80057b8: 2300 movs r3, #0 + 80057ba: 6013 str r3, [r2, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); - 8005720: f7fc fda2 bl 8002268 - 8005724: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8 + 80057bc: f7fc fda2 bl 8002304 + 80057c0: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8 /* Wait till PLL is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) - 8005728: e00c b.n 8005744 - 800572a: bf00 nop - 800572c: 40021000 .word 0x40021000 + 80057c4: e00c b.n 80057e0 + 80057c6: bf00 nop + 80057c8: 40021000 .word 0x40021000 { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) - 8005730: f7fc fd9a bl 8002268 - 8005734: 4602 mov r2, r0 - 8005736: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8 - 800573a: 1ad3 subs r3, r2, r3 - 800573c: 2b02 cmp r3, #2 - 800573e: d901 bls.n 8005744 + 80057cc: f7fc fd9a bl 8002304 + 80057d0: 4602 mov r2, r0 + 80057d2: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8 + 80057d6: 1ad3 subs r3, r2, r3 + 80057d8: 2b02 cmp r3, #2 + 80057da: d901 bls.n 80057e0 { return HAL_TIMEOUT; - 8005740: 2303 movs r3, #3 - 8005742: e1fd b.n 8005b40 - 8005744: f507 7300 add.w r3, r7, #512 @ 0x200 - 8005748: f5a3 73c4 sub.w r3, r3, #392 @ 0x188 - 800574c: f04f 7200 mov.w r2, #33554432 @ 0x2000000 - 8005750: 601a str r2, [r3, #0] + 80057dc: 2303 movs r3, #3 + 80057de: e1fd b.n 8005bdc + 80057e0: f507 7300 add.w r3, r7, #512 @ 0x200 + 80057e4: f5a3 73c4 sub.w r3, r3, #392 @ 0x188 + 80057e8: f04f 7200 mov.w r2, #33554432 @ 0x2000000 + 80057ec: 601a str r2, [r3, #0] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8005752: f507 7300 add.w r3, r7, #512 @ 0x200 - 8005756: f5a3 73c4 sub.w r3, r3, #392 @ 0x188 - 800575a: 681b ldr r3, [r3, #0] - 800575c: fa93 f2a3 rbit r2, r3 - 8005760: f507 7300 add.w r3, r7, #512 @ 0x200 - 8005764: f5a3 73c6 sub.w r3, r3, #396 @ 0x18c - 8005768: 601a str r2, [r3, #0] + 80057ee: f507 7300 add.w r3, r7, #512 @ 0x200 + 80057f2: f5a3 73c4 sub.w r3, r3, #392 @ 0x188 + 80057f6: 681b ldr r3, [r3, #0] + 80057f8: fa93 f2a3 rbit r2, r3 + 80057fc: f507 7300 add.w r3, r7, #512 @ 0x200 + 8005800: f5a3 73c6 sub.w r3, r3, #396 @ 0x18c + 8005804: 601a str r2, [r3, #0] return result; - 800576a: f507 7300 add.w r3, r7, #512 @ 0x200 - 800576e: f5a3 73c6 sub.w r3, r3, #396 @ 0x18c - 8005772: 681b ldr r3, [r3, #0] + 8005806: f507 7300 add.w r3, r7, #512 @ 0x200 + 800580a: f5a3 73c6 sub.w r3, r3, #396 @ 0x18c + 800580e: 681b ldr r3, [r3, #0] while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) - 8005774: fab3 f383 clz r3, r3 - 8005778: b2db uxtb r3, r3 - 800577a: 095b lsrs r3, r3, #5 - 800577c: b2db uxtb r3, r3 - 800577e: f043 0301 orr.w r3, r3, #1 - 8005782: b2db uxtb r3, r3 - 8005784: 2b01 cmp r3, #1 - 8005786: d102 bne.n 800578e - 8005788: 4bb0 ldr r3, [pc, #704] @ (8005a4c ) - 800578a: 681b ldr r3, [r3, #0] - 800578c: e027 b.n 80057de - 800578e: f507 7300 add.w r3, r7, #512 @ 0x200 - 8005792: f5a3 73c8 sub.w r3, r3, #400 @ 0x190 - 8005796: f04f 7200 mov.w r2, #33554432 @ 0x2000000 - 800579a: 601a str r2, [r3, #0] + 8005810: fab3 f383 clz r3, r3 + 8005814: b2db uxtb r3, r3 + 8005816: 095b lsrs r3, r3, #5 + 8005818: b2db uxtb r3, r3 + 800581a: f043 0301 orr.w r3, r3, #1 + 800581e: b2db uxtb r3, r3 + 8005820: 2b01 cmp r3, #1 + 8005822: d102 bne.n 800582a + 8005824: 4bb0 ldr r3, [pc, #704] @ (8005ae8 ) + 8005826: 681b ldr r3, [r3, #0] + 8005828: e027 b.n 800587a + 800582a: f507 7300 add.w r3, r7, #512 @ 0x200 + 800582e: f5a3 73c8 sub.w r3, r3, #400 @ 0x190 + 8005832: f04f 7200 mov.w r2, #33554432 @ 0x2000000 + 8005836: 601a str r2, [r3, #0] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 800579c: f507 7300 add.w r3, r7, #512 @ 0x200 - 80057a0: f5a3 73c8 sub.w r3, r3, #400 @ 0x190 - 80057a4: 681b ldr r3, [r3, #0] - 80057a6: fa93 f2a3 rbit r2, r3 - 80057aa: f507 7300 add.w r3, r7, #512 @ 0x200 - 80057ae: f5a3 73ca sub.w r3, r3, #404 @ 0x194 - 80057b2: 601a str r2, [r3, #0] - 80057b4: f507 7300 add.w r3, r7, #512 @ 0x200 - 80057b8: f5a3 73cc sub.w r3, r3, #408 @ 0x198 - 80057bc: f04f 7200 mov.w r2, #33554432 @ 0x2000000 - 80057c0: 601a str r2, [r3, #0] - 80057c2: f507 7300 add.w r3, r7, #512 @ 0x200 - 80057c6: f5a3 73cc sub.w r3, r3, #408 @ 0x198 - 80057ca: 681b ldr r3, [r3, #0] - 80057cc: fa93 f2a3 rbit r2, r3 - 80057d0: f507 7300 add.w r3, r7, #512 @ 0x200 - 80057d4: f5a3 73ce sub.w r3, r3, #412 @ 0x19c - 80057d8: 601a str r2, [r3, #0] - 80057da: 4b9c ldr r3, [pc, #624] @ (8005a4c ) - 80057dc: 6a5b ldr r3, [r3, #36] @ 0x24 - 80057de: f507 7200 add.w r2, r7, #512 @ 0x200 - 80057e2: f5a2 72d0 sub.w r2, r2, #416 @ 0x1a0 - 80057e6: f04f 7100 mov.w r1, #33554432 @ 0x2000000 - 80057ea: 6011 str r1, [r2, #0] - 80057ec: f507 7200 add.w r2, r7, #512 @ 0x200 - 80057f0: f5a2 72d0 sub.w r2, r2, #416 @ 0x1a0 - 80057f4: 6812 ldr r2, [r2, #0] - 80057f6: fa92 f1a2 rbit r1, r2 - 80057fa: f507 7200 add.w r2, r7, #512 @ 0x200 - 80057fe: f5a2 72d2 sub.w r2, r2, #420 @ 0x1a4 - 8005802: 6011 str r1, [r2, #0] + 8005838: f507 7300 add.w r3, r7, #512 @ 0x200 + 800583c: f5a3 73c8 sub.w r3, r3, #400 @ 0x190 + 8005840: 681b ldr r3, [r3, #0] + 8005842: fa93 f2a3 rbit r2, r3 + 8005846: f507 7300 add.w r3, r7, #512 @ 0x200 + 800584a: f5a3 73ca sub.w r3, r3, #404 @ 0x194 + 800584e: 601a str r2, [r3, #0] + 8005850: f507 7300 add.w r3, r7, #512 @ 0x200 + 8005854: f5a3 73cc sub.w r3, r3, #408 @ 0x198 + 8005858: f04f 7200 mov.w r2, #33554432 @ 0x2000000 + 800585c: 601a str r2, [r3, #0] + 800585e: f507 7300 add.w r3, r7, #512 @ 0x200 + 8005862: f5a3 73cc sub.w r3, r3, #408 @ 0x198 + 8005866: 681b ldr r3, [r3, #0] + 8005868: fa93 f2a3 rbit r2, r3 + 800586c: f507 7300 add.w r3, r7, #512 @ 0x200 + 8005870: f5a3 73ce sub.w r3, r3, #412 @ 0x19c + 8005874: 601a str r2, [r3, #0] + 8005876: 4b9c ldr r3, [pc, #624] @ (8005ae8 ) + 8005878: 6a5b ldr r3, [r3, #36] @ 0x24 + 800587a: f507 7200 add.w r2, r7, #512 @ 0x200 + 800587e: f5a2 72d0 sub.w r2, r2, #416 @ 0x1a0 + 8005882: f04f 7100 mov.w r1, #33554432 @ 0x2000000 + 8005886: 6011 str r1, [r2, #0] + 8005888: f507 7200 add.w r2, r7, #512 @ 0x200 + 800588c: f5a2 72d0 sub.w r2, r2, #416 @ 0x1a0 + 8005890: 6812 ldr r2, [r2, #0] + 8005892: fa92 f1a2 rbit r1, r2 + 8005896: f507 7200 add.w r2, r7, #512 @ 0x200 + 800589a: f5a2 72d2 sub.w r2, r2, #420 @ 0x1a4 + 800589e: 6011 str r1, [r2, #0] return result; - 8005804: f507 7200 add.w r2, r7, #512 @ 0x200 - 8005808: f5a2 72d2 sub.w r2, r2, #420 @ 0x1a4 - 800580c: 6812 ldr r2, [r2, #0] - 800580e: fab2 f282 clz r2, r2 - 8005812: b2d2 uxtb r2, r2 - 8005814: f042 0220 orr.w r2, r2, #32 - 8005818: b2d2 uxtb r2, r2 - 800581a: f002 021f and.w r2, r2, #31 - 800581e: 2101 movs r1, #1 - 8005820: fa01 f202 lsl.w r2, r1, r2 - 8005824: 4013 ands r3, r2 - 8005826: 2b00 cmp r3, #0 - 8005828: d182 bne.n 8005730 + 80058a0: f507 7200 add.w r2, r7, #512 @ 0x200 + 80058a4: f5a2 72d2 sub.w r2, r2, #420 @ 0x1a4 + 80058a8: 6812 ldr r2, [r2, #0] + 80058aa: fab2 f282 clz r2, r2 + 80058ae: b2d2 uxtb r2, r2 + 80058b0: f042 0220 orr.w r2, r2, #32 + 80058b4: b2d2 uxtb r2, r2 + 80058b6: f002 021f and.w r2, r2, #31 + 80058ba: 2101 movs r1, #1 + 80058bc: fa01 f202 lsl.w r2, r1, r2 + 80058c0: 4013 ands r3, r2 + 80058c2: 2b00 cmp r3, #0 + 80058c4: d182 bne.n 80057cc __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, RCC_OscInitStruct->PLL.PREDIV, RCC_OscInitStruct->PLL.PLLMUL); #else /* Configure the main PLL clock source and multiplication factor. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, - 800582a: 4b88 ldr r3, [pc, #544] @ (8005a4c ) - 800582c: 685b ldr r3, [r3, #4] - 800582e: f423 1274 bic.w r2, r3, #3997696 @ 0x3d0000 - 8005832: f507 7300 add.w r3, r7, #512 @ 0x200 - 8005836: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc - 800583a: 681b ldr r3, [r3, #0] - 800583c: 6a59 ldr r1, [r3, #36] @ 0x24 - 800583e: f507 7300 add.w r3, r7, #512 @ 0x200 - 8005842: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc - 8005846: 681b ldr r3, [r3, #0] - 8005848: 6a1b ldr r3, [r3, #32] - 800584a: 430b orrs r3, r1 - 800584c: 497f ldr r1, [pc, #508] @ (8005a4c ) - 800584e: 4313 orrs r3, r2 - 8005850: 604b str r3, [r1, #4] - 8005852: f507 7300 add.w r3, r7, #512 @ 0x200 - 8005856: f5a3 73d4 sub.w r3, r3, #424 @ 0x1a8 - 800585a: f04f 7280 mov.w r2, #16777216 @ 0x1000000 - 800585e: 601a str r2, [r3, #0] + 80058c6: 4b88 ldr r3, [pc, #544] @ (8005ae8 ) + 80058c8: 685b ldr r3, [r3, #4] + 80058ca: f423 1274 bic.w r2, r3, #3997696 @ 0x3d0000 + 80058ce: f507 7300 add.w r3, r7, #512 @ 0x200 + 80058d2: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc + 80058d6: 681b ldr r3, [r3, #0] + 80058d8: 6a59 ldr r1, [r3, #36] @ 0x24 + 80058da: f507 7300 add.w r3, r7, #512 @ 0x200 + 80058de: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc + 80058e2: 681b ldr r3, [r3, #0] + 80058e4: 6a1b ldr r3, [r3, #32] + 80058e6: 430b orrs r3, r1 + 80058e8: 497f ldr r1, [pc, #508] @ (8005ae8 ) + 80058ea: 4313 orrs r3, r2 + 80058ec: 604b str r3, [r1, #4] + 80058ee: f507 7300 add.w r3, r7, #512 @ 0x200 + 80058f2: f5a3 73d4 sub.w r3, r3, #424 @ 0x1a8 + 80058f6: f04f 7280 mov.w r2, #16777216 @ 0x1000000 + 80058fa: 601a str r2, [r3, #0] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8005860: f507 7300 add.w r3, r7, #512 @ 0x200 - 8005864: f5a3 73d4 sub.w r3, r3, #424 @ 0x1a8 - 8005868: 681b ldr r3, [r3, #0] - 800586a: fa93 f2a3 rbit r2, r3 - 800586e: f507 7300 add.w r3, r7, #512 @ 0x200 - 8005872: f5a3 73d6 sub.w r3, r3, #428 @ 0x1ac - 8005876: 601a str r2, [r3, #0] + 80058fc: f507 7300 add.w r3, r7, #512 @ 0x200 + 8005900: f5a3 73d4 sub.w r3, r3, #424 @ 0x1a8 + 8005904: 681b ldr r3, [r3, #0] + 8005906: fa93 f2a3 rbit r2, r3 + 800590a: f507 7300 add.w r3, r7, #512 @ 0x200 + 800590e: f5a3 73d6 sub.w r3, r3, #428 @ 0x1ac + 8005912: 601a str r2, [r3, #0] return result; - 8005878: f507 7300 add.w r3, r7, #512 @ 0x200 - 800587c: f5a3 73d6 sub.w r3, r3, #428 @ 0x1ac - 8005880: 681b ldr r3, [r3, #0] + 8005914: f507 7300 add.w r3, r7, #512 @ 0x200 + 8005918: f5a3 73d6 sub.w r3, r3, #428 @ 0x1ac + 800591c: 681b ldr r3, [r3, #0] RCC_OscInitStruct->PLL.PLLMUL); #endif /* RCC_CFGR_PLLSRC_HSI_PREDIV */ /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); - 8005882: fab3 f383 clz r3, r3 - 8005886: b2db uxtb r3, r3 - 8005888: f103 5384 add.w r3, r3, #276824064 @ 0x10800000 - 800588c: f503 1384 add.w r3, r3, #1081344 @ 0x108000 - 8005890: 009b lsls r3, r3, #2 - 8005892: 461a mov r2, r3 - 8005894: 2301 movs r3, #1 - 8005896: 6013 str r3, [r2, #0] + 800591e: fab3 f383 clz r3, r3 + 8005922: b2db uxtb r3, r3 + 8005924: f103 5384 add.w r3, r3, #276824064 @ 0x10800000 + 8005928: f503 1384 add.w r3, r3, #1081344 @ 0x108000 + 800592c: 009b lsls r3, r3, #2 + 800592e: 461a mov r2, r3 + 8005930: 2301 movs r3, #1 + 8005932: 6013 str r3, [r2, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); - 8005898: f7fc fce6 bl 8002268 - 800589c: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8 + 8005934: f7fc fce6 bl 8002304 + 8005938: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8 /* Wait till PLL is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) - 80058a0: e009 b.n 80058b6 + 800593c: e009 b.n 8005952 { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) - 80058a2: f7fc fce1 bl 8002268 - 80058a6: 4602 mov r2, r0 - 80058a8: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8 - 80058ac: 1ad3 subs r3, r2, r3 - 80058ae: 2b02 cmp r3, #2 - 80058b0: d901 bls.n 80058b6 + 800593e: f7fc fce1 bl 8002304 + 8005942: 4602 mov r2, r0 + 8005944: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8 + 8005948: 1ad3 subs r3, r2, r3 + 800594a: 2b02 cmp r3, #2 + 800594c: d901 bls.n 8005952 { return HAL_TIMEOUT; - 80058b2: 2303 movs r3, #3 - 80058b4: e144 b.n 8005b40 - 80058b6: f507 7300 add.w r3, r7, #512 @ 0x200 - 80058ba: f5a3 73d8 sub.w r3, r3, #432 @ 0x1b0 - 80058be: f04f 7200 mov.w r2, #33554432 @ 0x2000000 - 80058c2: 601a str r2, [r3, #0] + 800594e: 2303 movs r3, #3 + 8005950: e144 b.n 8005bdc + 8005952: f507 7300 add.w r3, r7, #512 @ 0x200 + 8005956: f5a3 73d8 sub.w r3, r3, #432 @ 0x1b0 + 800595a: f04f 7200 mov.w r2, #33554432 @ 0x2000000 + 800595e: 601a str r2, [r3, #0] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 80058c4: f507 7300 add.w r3, r7, #512 @ 0x200 - 80058c8: f5a3 73d8 sub.w r3, r3, #432 @ 0x1b0 - 80058cc: 681b ldr r3, [r3, #0] - 80058ce: fa93 f2a3 rbit r2, r3 - 80058d2: f507 7300 add.w r3, r7, #512 @ 0x200 - 80058d6: f5a3 73da sub.w r3, r3, #436 @ 0x1b4 - 80058da: 601a str r2, [r3, #0] + 8005960: f507 7300 add.w r3, r7, #512 @ 0x200 + 8005964: f5a3 73d8 sub.w r3, r3, #432 @ 0x1b0 + 8005968: 681b ldr r3, [r3, #0] + 800596a: fa93 f2a3 rbit r2, r3 + 800596e: f507 7300 add.w r3, r7, #512 @ 0x200 + 8005972: f5a3 73da sub.w r3, r3, #436 @ 0x1b4 + 8005976: 601a str r2, [r3, #0] return result; - 80058dc: f507 7300 add.w r3, r7, #512 @ 0x200 - 80058e0: f5a3 73da sub.w r3, r3, #436 @ 0x1b4 - 80058e4: 681b ldr r3, [r3, #0] + 8005978: f507 7300 add.w r3, r7, #512 @ 0x200 + 800597c: f5a3 73da sub.w r3, r3, #436 @ 0x1b4 + 8005980: 681b ldr r3, [r3, #0] while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) - 80058e6: fab3 f383 clz r3, r3 - 80058ea: b2db uxtb r3, r3 - 80058ec: 095b lsrs r3, r3, #5 - 80058ee: b2db uxtb r3, r3 - 80058f0: f043 0301 orr.w r3, r3, #1 - 80058f4: b2db uxtb r3, r3 - 80058f6: 2b01 cmp r3, #1 - 80058f8: d102 bne.n 8005900 - 80058fa: 4b54 ldr r3, [pc, #336] @ (8005a4c ) - 80058fc: 681b ldr r3, [r3, #0] - 80058fe: e027 b.n 8005950 - 8005900: f507 7300 add.w r3, r7, #512 @ 0x200 - 8005904: f5a3 73dc sub.w r3, r3, #440 @ 0x1b8 - 8005908: f04f 7200 mov.w r2, #33554432 @ 0x2000000 - 800590c: 601a str r2, [r3, #0] + 8005982: fab3 f383 clz r3, r3 + 8005986: b2db uxtb r3, r3 + 8005988: 095b lsrs r3, r3, #5 + 800598a: b2db uxtb r3, r3 + 800598c: f043 0301 orr.w r3, r3, #1 + 8005990: b2db uxtb r3, r3 + 8005992: 2b01 cmp r3, #1 + 8005994: d102 bne.n 800599c + 8005996: 4b54 ldr r3, [pc, #336] @ (8005ae8 ) + 8005998: 681b ldr r3, [r3, #0] + 800599a: e027 b.n 80059ec + 800599c: f507 7300 add.w r3, r7, #512 @ 0x200 + 80059a0: f5a3 73dc sub.w r3, r3, #440 @ 0x1b8 + 80059a4: f04f 7200 mov.w r2, #33554432 @ 0x2000000 + 80059a8: 601a str r2, [r3, #0] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 800590e: f507 7300 add.w r3, r7, #512 @ 0x200 - 8005912: f5a3 73dc sub.w r3, r3, #440 @ 0x1b8 - 8005916: 681b ldr r3, [r3, #0] - 8005918: fa93 f2a3 rbit r2, r3 - 800591c: f507 7300 add.w r3, r7, #512 @ 0x200 - 8005920: f5a3 73de sub.w r3, r3, #444 @ 0x1bc - 8005924: 601a str r2, [r3, #0] - 8005926: f507 7300 add.w r3, r7, #512 @ 0x200 - 800592a: f5a3 73e0 sub.w r3, r3, #448 @ 0x1c0 - 800592e: f04f 7200 mov.w r2, #33554432 @ 0x2000000 - 8005932: 601a str r2, [r3, #0] - 8005934: f507 7300 add.w r3, r7, #512 @ 0x200 - 8005938: f5a3 73e0 sub.w r3, r3, #448 @ 0x1c0 - 800593c: 681b ldr r3, [r3, #0] - 800593e: fa93 f2a3 rbit r2, r3 - 8005942: f507 7300 add.w r3, r7, #512 @ 0x200 - 8005946: f5a3 73e2 sub.w r3, r3, #452 @ 0x1c4 - 800594a: 601a str r2, [r3, #0] - 800594c: 4b3f ldr r3, [pc, #252] @ (8005a4c ) - 800594e: 6a5b ldr r3, [r3, #36] @ 0x24 - 8005950: f507 7200 add.w r2, r7, #512 @ 0x200 - 8005954: f5a2 72e4 sub.w r2, r2, #456 @ 0x1c8 - 8005958: f04f 7100 mov.w r1, #33554432 @ 0x2000000 - 800595c: 6011 str r1, [r2, #0] - 800595e: f507 7200 add.w r2, r7, #512 @ 0x200 - 8005962: f5a2 72e4 sub.w r2, r2, #456 @ 0x1c8 - 8005966: 6812 ldr r2, [r2, #0] - 8005968: fa92 f1a2 rbit r1, r2 - 800596c: f507 7200 add.w r2, r7, #512 @ 0x200 - 8005970: f5a2 72e6 sub.w r2, r2, #460 @ 0x1cc - 8005974: 6011 str r1, [r2, #0] + 80059aa: f507 7300 add.w r3, r7, #512 @ 0x200 + 80059ae: f5a3 73dc sub.w r3, r3, #440 @ 0x1b8 + 80059b2: 681b ldr r3, [r3, #0] + 80059b4: fa93 f2a3 rbit r2, r3 + 80059b8: f507 7300 add.w r3, r7, #512 @ 0x200 + 80059bc: f5a3 73de sub.w r3, r3, #444 @ 0x1bc + 80059c0: 601a str r2, [r3, #0] + 80059c2: f507 7300 add.w r3, r7, #512 @ 0x200 + 80059c6: f5a3 73e0 sub.w r3, r3, #448 @ 0x1c0 + 80059ca: f04f 7200 mov.w r2, #33554432 @ 0x2000000 + 80059ce: 601a str r2, [r3, #0] + 80059d0: f507 7300 add.w r3, r7, #512 @ 0x200 + 80059d4: f5a3 73e0 sub.w r3, r3, #448 @ 0x1c0 + 80059d8: 681b ldr r3, [r3, #0] + 80059da: fa93 f2a3 rbit r2, r3 + 80059de: f507 7300 add.w r3, r7, #512 @ 0x200 + 80059e2: f5a3 73e2 sub.w r3, r3, #452 @ 0x1c4 + 80059e6: 601a str r2, [r3, #0] + 80059e8: 4b3f ldr r3, [pc, #252] @ (8005ae8 ) + 80059ea: 6a5b ldr r3, [r3, #36] @ 0x24 + 80059ec: f507 7200 add.w r2, r7, #512 @ 0x200 + 80059f0: f5a2 72e4 sub.w r2, r2, #456 @ 0x1c8 + 80059f4: f04f 7100 mov.w r1, #33554432 @ 0x2000000 + 80059f8: 6011 str r1, [r2, #0] + 80059fa: f507 7200 add.w r2, r7, #512 @ 0x200 + 80059fe: f5a2 72e4 sub.w r2, r2, #456 @ 0x1c8 + 8005a02: 6812 ldr r2, [r2, #0] + 8005a04: fa92 f1a2 rbit r1, r2 + 8005a08: f507 7200 add.w r2, r7, #512 @ 0x200 + 8005a0c: f5a2 72e6 sub.w r2, r2, #460 @ 0x1cc + 8005a10: 6011 str r1, [r2, #0] return result; - 8005976: f507 7200 add.w r2, r7, #512 @ 0x200 - 800597a: f5a2 72e6 sub.w r2, r2, #460 @ 0x1cc - 800597e: 6812 ldr r2, [r2, #0] - 8005980: fab2 f282 clz r2, r2 - 8005984: b2d2 uxtb r2, r2 - 8005986: f042 0220 orr.w r2, r2, #32 - 800598a: b2d2 uxtb r2, r2 - 800598c: f002 021f and.w r2, r2, #31 - 8005990: 2101 movs r1, #1 - 8005992: fa01 f202 lsl.w r2, r1, r2 - 8005996: 4013 ands r3, r2 - 8005998: 2b00 cmp r3, #0 - 800599a: d082 beq.n 80058a2 - 800599c: e0cf b.n 8005b3e - 800599e: f507 7300 add.w r3, r7, #512 @ 0x200 - 80059a2: f5a3 73e8 sub.w r3, r3, #464 @ 0x1d0 - 80059a6: f04f 7280 mov.w r2, #16777216 @ 0x1000000 - 80059aa: 601a str r2, [r3, #0] + 8005a12: f507 7200 add.w r2, r7, #512 @ 0x200 + 8005a16: f5a2 72e6 sub.w r2, r2, #460 @ 0x1cc + 8005a1a: 6812 ldr r2, [r2, #0] + 8005a1c: fab2 f282 clz r2, r2 + 8005a20: b2d2 uxtb r2, r2 + 8005a22: f042 0220 orr.w r2, r2, #32 + 8005a26: b2d2 uxtb r2, r2 + 8005a28: f002 021f and.w r2, r2, #31 + 8005a2c: 2101 movs r1, #1 + 8005a2e: fa01 f202 lsl.w r2, r1, r2 + 8005a32: 4013 ands r3, r2 + 8005a34: 2b00 cmp r3, #0 + 8005a36: d082 beq.n 800593e + 8005a38: e0cf b.n 8005bda + 8005a3a: f507 7300 add.w r3, r7, #512 @ 0x200 + 8005a3e: f5a3 73e8 sub.w r3, r3, #464 @ 0x1d0 + 8005a42: f04f 7280 mov.w r2, #16777216 @ 0x1000000 + 8005a46: 601a str r2, [r3, #0] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 80059ac: f507 7300 add.w r3, r7, #512 @ 0x200 - 80059b0: f5a3 73e8 sub.w r3, r3, #464 @ 0x1d0 - 80059b4: 681b ldr r3, [r3, #0] - 80059b6: fa93 f2a3 rbit r2, r3 - 80059ba: f507 7300 add.w r3, r7, #512 @ 0x200 - 80059be: f5a3 73ea sub.w r3, r3, #468 @ 0x1d4 - 80059c2: 601a str r2, [r3, #0] + 8005a48: f507 7300 add.w r3, r7, #512 @ 0x200 + 8005a4c: f5a3 73e8 sub.w r3, r3, #464 @ 0x1d0 + 8005a50: 681b ldr r3, [r3, #0] + 8005a52: fa93 f2a3 rbit r2, r3 + 8005a56: f507 7300 add.w r3, r7, #512 @ 0x200 + 8005a5a: f5a3 73ea sub.w r3, r3, #468 @ 0x1d4 + 8005a5e: 601a str r2, [r3, #0] return result; - 80059c4: f507 7300 add.w r3, r7, #512 @ 0x200 - 80059c8: f5a3 73ea sub.w r3, r3, #468 @ 0x1d4 - 80059cc: 681b ldr r3, [r3, #0] + 8005a60: f507 7300 add.w r3, r7, #512 @ 0x200 + 8005a64: f5a3 73ea sub.w r3, r3, #468 @ 0x1d4 + 8005a68: 681b ldr r3, [r3, #0] } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); - 80059ce: fab3 f383 clz r3, r3 - 80059d2: b2db uxtb r3, r3 - 80059d4: f103 5384 add.w r3, r3, #276824064 @ 0x10800000 - 80059d8: f503 1384 add.w r3, r3, #1081344 @ 0x108000 - 80059dc: 009b lsls r3, r3, #2 - 80059de: 461a mov r2, r3 - 80059e0: 2300 movs r3, #0 - 80059e2: 6013 str r3, [r2, #0] + 8005a6a: fab3 f383 clz r3, r3 + 8005a6e: b2db uxtb r3, r3 + 8005a70: f103 5384 add.w r3, r3, #276824064 @ 0x10800000 + 8005a74: f503 1384 add.w r3, r3, #1081344 @ 0x108000 + 8005a78: 009b lsls r3, r3, #2 + 8005a7a: 461a mov r2, r3 + 8005a7c: 2300 movs r3, #0 + 8005a7e: 6013 str r3, [r2, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); - 80059e4: f7fc fc40 bl 8002268 - 80059e8: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8 + 8005a80: f7fc fc40 bl 8002304 + 8005a84: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8 /* Wait till PLL is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) - 80059ec: e009 b.n 8005a02 + 8005a88: e009 b.n 8005a9e { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) - 80059ee: f7fc fc3b bl 8002268 - 80059f2: 4602 mov r2, r0 - 80059f4: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8 - 80059f8: 1ad3 subs r3, r2, r3 - 80059fa: 2b02 cmp r3, #2 - 80059fc: d901 bls.n 8005a02 + 8005a8a: f7fc fc3b bl 8002304 + 8005a8e: 4602 mov r2, r0 + 8005a90: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8 + 8005a94: 1ad3 subs r3, r2, r3 + 8005a96: 2b02 cmp r3, #2 + 8005a98: d901 bls.n 8005a9e { return HAL_TIMEOUT; - 80059fe: 2303 movs r3, #3 - 8005a00: e09e b.n 8005b40 - 8005a02: f507 7300 add.w r3, r7, #512 @ 0x200 - 8005a06: f5a3 73ec sub.w r3, r3, #472 @ 0x1d8 - 8005a0a: f04f 7200 mov.w r2, #33554432 @ 0x2000000 - 8005a0e: 601a str r2, [r3, #0] + 8005a9a: 2303 movs r3, #3 + 8005a9c: e09e b.n 8005bdc + 8005a9e: f507 7300 add.w r3, r7, #512 @ 0x200 + 8005aa2: f5a3 73ec sub.w r3, r3, #472 @ 0x1d8 + 8005aa6: f04f 7200 mov.w r2, #33554432 @ 0x2000000 + 8005aaa: 601a str r2, [r3, #0] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8005a10: f507 7300 add.w r3, r7, #512 @ 0x200 - 8005a14: f5a3 73ec sub.w r3, r3, #472 @ 0x1d8 - 8005a18: 681b ldr r3, [r3, #0] - 8005a1a: fa93 f2a3 rbit r2, r3 - 8005a1e: f507 7300 add.w r3, r7, #512 @ 0x200 - 8005a22: f5a3 73ee sub.w r3, r3, #476 @ 0x1dc - 8005a26: 601a str r2, [r3, #0] + 8005aac: f507 7300 add.w r3, r7, #512 @ 0x200 + 8005ab0: f5a3 73ec sub.w r3, r3, #472 @ 0x1d8 + 8005ab4: 681b ldr r3, [r3, #0] + 8005ab6: fa93 f2a3 rbit r2, r3 + 8005aba: f507 7300 add.w r3, r7, #512 @ 0x200 + 8005abe: f5a3 73ee sub.w r3, r3, #476 @ 0x1dc + 8005ac2: 601a str r2, [r3, #0] return result; - 8005a28: f507 7300 add.w r3, r7, #512 @ 0x200 - 8005a2c: f5a3 73ee sub.w r3, r3, #476 @ 0x1dc - 8005a30: 681b ldr r3, [r3, #0] + 8005ac4: f507 7300 add.w r3, r7, #512 @ 0x200 + 8005ac8: f5a3 73ee sub.w r3, r3, #476 @ 0x1dc + 8005acc: 681b ldr r3, [r3, #0] while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) - 8005a32: fab3 f383 clz r3, r3 - 8005a36: b2db uxtb r3, r3 - 8005a38: 095b lsrs r3, r3, #5 - 8005a3a: b2db uxtb r3, r3 - 8005a3c: f043 0301 orr.w r3, r3, #1 - 8005a40: b2db uxtb r3, r3 - 8005a42: 2b01 cmp r3, #1 - 8005a44: d104 bne.n 8005a50 - 8005a46: 4b01 ldr r3, [pc, #4] @ (8005a4c ) - 8005a48: 681b ldr r3, [r3, #0] - 8005a4a: e029 b.n 8005aa0 - 8005a4c: 40021000 .word 0x40021000 - 8005a50: f507 7300 add.w r3, r7, #512 @ 0x200 - 8005a54: f5a3 73f0 sub.w r3, r3, #480 @ 0x1e0 - 8005a58: f04f 7200 mov.w r2, #33554432 @ 0x2000000 - 8005a5c: 601a str r2, [r3, #0] + 8005ace: fab3 f383 clz r3, r3 + 8005ad2: b2db uxtb r3, r3 + 8005ad4: 095b lsrs r3, r3, #5 + 8005ad6: b2db uxtb r3, r3 + 8005ad8: f043 0301 orr.w r3, r3, #1 + 8005adc: b2db uxtb r3, r3 + 8005ade: 2b01 cmp r3, #1 + 8005ae0: d104 bne.n 8005aec + 8005ae2: 4b01 ldr r3, [pc, #4] @ (8005ae8 ) + 8005ae4: 681b ldr r3, [r3, #0] + 8005ae6: e029 b.n 8005b3c + 8005ae8: 40021000 .word 0x40021000 + 8005aec: f507 7300 add.w r3, r7, #512 @ 0x200 + 8005af0: f5a3 73f0 sub.w r3, r3, #480 @ 0x1e0 + 8005af4: f04f 7200 mov.w r2, #33554432 @ 0x2000000 + 8005af8: 601a str r2, [r3, #0] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8005a5e: f507 7300 add.w r3, r7, #512 @ 0x200 - 8005a62: f5a3 73f0 sub.w r3, r3, #480 @ 0x1e0 - 8005a66: 681b ldr r3, [r3, #0] - 8005a68: fa93 f2a3 rbit r2, r3 - 8005a6c: f507 7300 add.w r3, r7, #512 @ 0x200 - 8005a70: f5a3 73f2 sub.w r3, r3, #484 @ 0x1e4 - 8005a74: 601a str r2, [r3, #0] - 8005a76: f507 7300 add.w r3, r7, #512 @ 0x200 - 8005a7a: f5a3 73f4 sub.w r3, r3, #488 @ 0x1e8 - 8005a7e: f04f 7200 mov.w r2, #33554432 @ 0x2000000 - 8005a82: 601a str r2, [r3, #0] - 8005a84: f507 7300 add.w r3, r7, #512 @ 0x200 - 8005a88: f5a3 73f4 sub.w r3, r3, #488 @ 0x1e8 - 8005a8c: 681b ldr r3, [r3, #0] - 8005a8e: fa93 f2a3 rbit r2, r3 - 8005a92: f507 7300 add.w r3, r7, #512 @ 0x200 - 8005a96: f5a3 73f6 sub.w r3, r3, #492 @ 0x1ec - 8005a9a: 601a str r2, [r3, #0] - 8005a9c: 4b2b ldr r3, [pc, #172] @ (8005b4c ) - 8005a9e: 6a5b ldr r3, [r3, #36] @ 0x24 - 8005aa0: f507 7200 add.w r2, r7, #512 @ 0x200 - 8005aa4: f5a2 72f8 sub.w r2, r2, #496 @ 0x1f0 - 8005aa8: f04f 7100 mov.w r1, #33554432 @ 0x2000000 - 8005aac: 6011 str r1, [r2, #0] - 8005aae: f507 7200 add.w r2, r7, #512 @ 0x200 - 8005ab2: f5a2 72f8 sub.w r2, r2, #496 @ 0x1f0 - 8005ab6: 6812 ldr r2, [r2, #0] - 8005ab8: fa92 f1a2 rbit r1, r2 - 8005abc: f507 7200 add.w r2, r7, #512 @ 0x200 - 8005ac0: f5a2 72fa sub.w r2, r2, #500 @ 0x1f4 - 8005ac4: 6011 str r1, [r2, #0] + 8005afa: f507 7300 add.w r3, r7, #512 @ 0x200 + 8005afe: f5a3 73f0 sub.w r3, r3, #480 @ 0x1e0 + 8005b02: 681b ldr r3, [r3, #0] + 8005b04: fa93 f2a3 rbit r2, r3 + 8005b08: f507 7300 add.w r3, r7, #512 @ 0x200 + 8005b0c: f5a3 73f2 sub.w r3, r3, #484 @ 0x1e4 + 8005b10: 601a str r2, [r3, #0] + 8005b12: f507 7300 add.w r3, r7, #512 @ 0x200 + 8005b16: f5a3 73f4 sub.w r3, r3, #488 @ 0x1e8 + 8005b1a: f04f 7200 mov.w r2, #33554432 @ 0x2000000 + 8005b1e: 601a str r2, [r3, #0] + 8005b20: f507 7300 add.w r3, r7, #512 @ 0x200 + 8005b24: f5a3 73f4 sub.w r3, r3, #488 @ 0x1e8 + 8005b28: 681b ldr r3, [r3, #0] + 8005b2a: fa93 f2a3 rbit r2, r3 + 8005b2e: f507 7300 add.w r3, r7, #512 @ 0x200 + 8005b32: f5a3 73f6 sub.w r3, r3, #492 @ 0x1ec + 8005b36: 601a str r2, [r3, #0] + 8005b38: 4b2b ldr r3, [pc, #172] @ (8005be8 ) + 8005b3a: 6a5b ldr r3, [r3, #36] @ 0x24 + 8005b3c: f507 7200 add.w r2, r7, #512 @ 0x200 + 8005b40: f5a2 72f8 sub.w r2, r2, #496 @ 0x1f0 + 8005b44: f04f 7100 mov.w r1, #33554432 @ 0x2000000 + 8005b48: 6011 str r1, [r2, #0] + 8005b4a: f507 7200 add.w r2, r7, #512 @ 0x200 + 8005b4e: f5a2 72f8 sub.w r2, r2, #496 @ 0x1f0 + 8005b52: 6812 ldr r2, [r2, #0] + 8005b54: fa92 f1a2 rbit r1, r2 + 8005b58: f507 7200 add.w r2, r7, #512 @ 0x200 + 8005b5c: f5a2 72fa sub.w r2, r2, #500 @ 0x1f4 + 8005b60: 6011 str r1, [r2, #0] return result; - 8005ac6: f507 7200 add.w r2, r7, #512 @ 0x200 - 8005aca: f5a2 72fa sub.w r2, r2, #500 @ 0x1f4 - 8005ace: 6812 ldr r2, [r2, #0] - 8005ad0: fab2 f282 clz r2, r2 - 8005ad4: b2d2 uxtb r2, r2 - 8005ad6: f042 0220 orr.w r2, r2, #32 - 8005ada: b2d2 uxtb r2, r2 - 8005adc: f002 021f and.w r2, r2, #31 - 8005ae0: 2101 movs r1, #1 - 8005ae2: fa01 f202 lsl.w r2, r1, r2 - 8005ae6: 4013 ands r3, r2 - 8005ae8: 2b00 cmp r3, #0 - 8005aea: d180 bne.n 80059ee - 8005aec: e027 b.n 8005b3e + 8005b62: f507 7200 add.w r2, r7, #512 @ 0x200 + 8005b66: f5a2 72fa sub.w r2, r2, #500 @ 0x1f4 + 8005b6a: 6812 ldr r2, [r2, #0] + 8005b6c: fab2 f282 clz r2, r2 + 8005b70: b2d2 uxtb r2, r2 + 8005b72: f042 0220 orr.w r2, r2, #32 + 8005b76: b2d2 uxtb r2, r2 + 8005b78: f002 021f and.w r2, r2, #31 + 8005b7c: 2101 movs r1, #1 + 8005b7e: fa01 f202 lsl.w r2, r1, r2 + 8005b82: 4013 ands r3, r2 + 8005b84: 2b00 cmp r3, #0 + 8005b86: d180 bne.n 8005a8a + 8005b88: e027 b.n 8005bda } } else { /* Check if there is a request to disable the PLL used as System clock source */ if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) - 8005aee: f507 7300 add.w r3, r7, #512 @ 0x200 - 8005af2: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc - 8005af6: 681b ldr r3, [r3, #0] - 8005af8: 69db ldr r3, [r3, #28] - 8005afa: 2b01 cmp r3, #1 - 8005afc: d101 bne.n 8005b02 + 8005b8a: f507 7300 add.w r3, r7, #512 @ 0x200 + 8005b8e: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc + 8005b92: 681b ldr r3, [r3, #0] + 8005b94: 69db ldr r3, [r3, #28] + 8005b96: 2b01 cmp r3, #1 + 8005b98: d101 bne.n 8005b9e { return HAL_ERROR; - 8005afe: 2301 movs r3, #1 - 8005b00: e01e b.n 8005b40 + 8005b9a: 2301 movs r3, #1 + 8005b9c: e01e b.n 8005bdc } else { /* Do not return HAL_ERROR if request repeats the current configuration */ pll_config = RCC->CFGR; - 8005b02: 4b12 ldr r3, [pc, #72] @ (8005b4c ) - 8005b04: 685b ldr r3, [r3, #4] - 8005b06: f8c7 31f4 str.w r3, [r7, #500] @ 0x1f4 + 8005b9e: 4b12 ldr r3, [pc, #72] @ (8005be8 ) + 8005ba0: 685b ldr r3, [r3, #4] + 8005ba2: f8c7 31f4 str.w r3, [r7, #500] @ 0x1f4 pll_config2 = RCC->CFGR2; if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) || (READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV)) #else if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || - 8005b0a: f8d7 31f4 ldr.w r3, [r7, #500] @ 0x1f4 - 8005b0e: f403 3280 and.w r2, r3, #65536 @ 0x10000 - 8005b12: f507 7300 add.w r3, r7, #512 @ 0x200 - 8005b16: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc - 8005b1a: 681b ldr r3, [r3, #0] - 8005b1c: 6a1b ldr r3, [r3, #32] - 8005b1e: 429a cmp r2, r3 - 8005b20: d10b bne.n 8005b3a + 8005ba6: f8d7 31f4 ldr.w r3, [r7, #500] @ 0x1f4 + 8005baa: f403 3280 and.w r2, r3, #65536 @ 0x10000 + 8005bae: f507 7300 add.w r3, r7, #512 @ 0x200 + 8005bb2: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc + 8005bb6: 681b ldr r3, [r3, #0] + 8005bb8: 6a1b ldr r3, [r3, #32] + 8005bba: 429a cmp r2, r3 + 8005bbc: d10b bne.n 8005bd6 (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL)) - 8005b22: f8d7 31f4 ldr.w r3, [r7, #500] @ 0x1f4 - 8005b26: f403 1270 and.w r2, r3, #3932160 @ 0x3c0000 - 8005b2a: f507 7300 add.w r3, r7, #512 @ 0x200 - 8005b2e: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc - 8005b32: 681b ldr r3, [r3, #0] - 8005b34: 6a5b ldr r3, [r3, #36] @ 0x24 + 8005bbe: f8d7 31f4 ldr.w r3, [r7, #500] @ 0x1f4 + 8005bc2: f403 1270 and.w r2, r3, #3932160 @ 0x3c0000 + 8005bc6: f507 7300 add.w r3, r7, #512 @ 0x200 + 8005bca: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc + 8005bce: 681b ldr r3, [r3, #0] + 8005bd0: 6a5b ldr r3, [r3, #36] @ 0x24 if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || - 8005b36: 429a cmp r2, r3 - 8005b38: d001 beq.n 8005b3e + 8005bd2: 429a cmp r2, r3 + 8005bd4: d001 beq.n 8005bda #endif { return HAL_ERROR; - 8005b3a: 2301 movs r3, #1 - 8005b3c: e000 b.n 8005b40 + 8005bd6: 2301 movs r3, #1 + 8005bd8: e000 b.n 8005bdc } } } } return HAL_OK; - 8005b3e: 2300 movs r3, #0 + 8005bda: 2300 movs r3, #0 } - 8005b40: 4618 mov r0, r3 - 8005b42: f507 7700 add.w r7, r7, #512 @ 0x200 - 8005b46: 46bd mov sp, r7 - 8005b48: bd80 pop {r7, pc} - 8005b4a: bf00 nop - 8005b4c: 40021000 .word 0x40021000 + 8005bdc: 4618 mov r0, r3 + 8005bde: f507 7700 add.w r7, r7, #512 @ 0x200 + 8005be2: 46bd mov sp, r7 + 8005be4: bd80 pop {r7, pc} + 8005be6: bf00 nop + 8005be8: 40021000 .word 0x40021000 -08005b50 : +08005bec : * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is * currently used as system clock source. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { - 8005b50: b580 push {r7, lr} - 8005b52: b09e sub sp, #120 @ 0x78 - 8005b54: af00 add r7, sp, #0 - 8005b56: 6078 str r0, [r7, #4] - 8005b58: 6039 str r1, [r7, #0] + 8005bec: b580 push {r7, lr} + 8005bee: b09e sub sp, #120 @ 0x78 + 8005bf0: af00 add r7, sp, #0 + 8005bf2: 6078 str r0, [r7, #4] + 8005bf4: 6039 str r1, [r7, #0] uint32_t tickstart = 0U; - 8005b5a: 2300 movs r3, #0 - 8005b5c: 677b str r3, [r7, #116] @ 0x74 + 8005bf6: 2300 movs r3, #0 + 8005bf8: 677b str r3, [r7, #116] @ 0x74 /* Check Null pointer */ if(RCC_ClkInitStruct == NULL) - 8005b5e: 687b ldr r3, [r7, #4] - 8005b60: 2b00 cmp r3, #0 - 8005b62: d101 bne.n 8005b68 + 8005bfa: 687b ldr r3, [r7, #4] + 8005bfc: 2b00 cmp r3, #0 + 8005bfe: d101 bne.n 8005c04 { return HAL_ERROR; - 8005b64: 2301 movs r3, #1 - 8005b66: e162 b.n 8005e2e + 8005c00: 2301 movs r3, #1 + 8005c02: e162 b.n 8005eca /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) of the device. */ /* Increasing the number of wait states because of higher CPU frequency */ if(FLatency > __HAL_FLASH_GET_LATENCY()) - 8005b68: 4b90 ldr r3, [pc, #576] @ (8005dac ) - 8005b6a: 681b ldr r3, [r3, #0] - 8005b6c: f003 0307 and.w r3, r3, #7 - 8005b70: 683a ldr r2, [r7, #0] - 8005b72: 429a cmp r2, r3 - 8005b74: d910 bls.n 8005b98 + 8005c04: 4b90 ldr r3, [pc, #576] @ (8005e48 ) + 8005c06: 681b ldr r3, [r3, #0] + 8005c08: f003 0307 and.w r3, r3, #7 + 8005c0c: 683a ldr r2, [r7, #0] + 8005c0e: 429a cmp r2, r3 + 8005c10: d910 bls.n 8005c34 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); - 8005b76: 4b8d ldr r3, [pc, #564] @ (8005dac ) - 8005b78: 681b ldr r3, [r3, #0] - 8005b7a: f023 0207 bic.w r2, r3, #7 - 8005b7e: 498b ldr r1, [pc, #556] @ (8005dac ) - 8005b80: 683b ldr r3, [r7, #0] - 8005b82: 4313 orrs r3, r2 - 8005b84: 600b str r3, [r1, #0] + 8005c12: 4b8d ldr r3, [pc, #564] @ (8005e48 ) + 8005c14: 681b ldr r3, [r3, #0] + 8005c16: f023 0207 bic.w r2, r3, #7 + 8005c1a: 498b ldr r1, [pc, #556] @ (8005e48 ) + 8005c1c: 683b ldr r3, [r7, #0] + 8005c1e: 4313 orrs r3, r2 + 8005c20: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if(__HAL_FLASH_GET_LATENCY() != FLatency) - 8005b86: 4b89 ldr r3, [pc, #548] @ (8005dac ) - 8005b88: 681b ldr r3, [r3, #0] - 8005b8a: f003 0307 and.w r3, r3, #7 - 8005b8e: 683a ldr r2, [r7, #0] - 8005b90: 429a cmp r2, r3 - 8005b92: d001 beq.n 8005b98 + 8005c22: 4b89 ldr r3, [pc, #548] @ (8005e48 ) + 8005c24: 681b ldr r3, [r3, #0] + 8005c26: f003 0307 and.w r3, r3, #7 + 8005c2a: 683a ldr r2, [r7, #0] + 8005c2c: 429a cmp r2, r3 + 8005c2e: d001 beq.n 8005c34 { return HAL_ERROR; - 8005b94: 2301 movs r3, #1 - 8005b96: e14a b.n 8005e2e + 8005c30: 2301 movs r3, #1 + 8005c32: e14a b.n 8005eca } } /*-------------------------- HCLK Configuration --------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) - 8005b98: 687b ldr r3, [r7, #4] - 8005b9a: 681b ldr r3, [r3, #0] - 8005b9c: f003 0302 and.w r3, r3, #2 - 8005ba0: 2b00 cmp r3, #0 - 8005ba2: d008 beq.n 8005bb6 + 8005c34: 687b ldr r3, [r7, #4] + 8005c36: 681b ldr r3, [r3, #0] + 8005c38: f003 0302 and.w r3, r3, #2 + 8005c3c: 2b00 cmp r3, #0 + 8005c3e: d008 beq.n 8005c52 { assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); - 8005ba4: 4b82 ldr r3, [pc, #520] @ (8005db0 ) - 8005ba6: 685b ldr r3, [r3, #4] - 8005ba8: f023 02f0 bic.w r2, r3, #240 @ 0xf0 - 8005bac: 687b ldr r3, [r7, #4] - 8005bae: 689b ldr r3, [r3, #8] - 8005bb0: 497f ldr r1, [pc, #508] @ (8005db0 ) - 8005bb2: 4313 orrs r3, r2 - 8005bb4: 604b str r3, [r1, #4] + 8005c40: 4b82 ldr r3, [pc, #520] @ (8005e4c ) + 8005c42: 685b ldr r3, [r3, #4] + 8005c44: f023 02f0 bic.w r2, r3, #240 @ 0xf0 + 8005c48: 687b ldr r3, [r7, #4] + 8005c4a: 689b ldr r3, [r3, #8] + 8005c4c: 497f ldr r1, [pc, #508] @ (8005e4c ) + 8005c4e: 4313 orrs r3, r2 + 8005c50: 604b str r3, [r1, #4] } /*------------------------- SYSCLK Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) - 8005bb6: 687b ldr r3, [r7, #4] - 8005bb8: 681b ldr r3, [r3, #0] - 8005bba: f003 0301 and.w r3, r3, #1 - 8005bbe: 2b00 cmp r3, #0 - 8005bc0: f000 80dc beq.w 8005d7c + 8005c52: 687b ldr r3, [r7, #4] + 8005c54: 681b ldr r3, [r3, #0] + 8005c56: f003 0301 and.w r3, r3, #1 + 8005c5a: 2b00 cmp r3, #0 + 8005c5c: f000 80dc beq.w 8005e18 { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) - 8005bc4: 687b ldr r3, [r7, #4] - 8005bc6: 685b ldr r3, [r3, #4] - 8005bc8: 2b01 cmp r3, #1 - 8005bca: d13c bne.n 8005c46 - 8005bcc: f44f 3300 mov.w r3, #131072 @ 0x20000 - 8005bd0: 673b str r3, [r7, #112] @ 0x70 + 8005c60: 687b ldr r3, [r7, #4] + 8005c62: 685b ldr r3, [r3, #4] + 8005c64: 2b01 cmp r3, #1 + 8005c66: d13c bne.n 8005ce2 + 8005c68: f44f 3300 mov.w r3, #131072 @ 0x20000 + 8005c6c: 673b str r3, [r7, #112] @ 0x70 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8005bd2: 6f3b ldr r3, [r7, #112] @ 0x70 - 8005bd4: fa93 f3a3 rbit r3, r3 - 8005bd8: 66fb str r3, [r7, #108] @ 0x6c + 8005c6e: 6f3b ldr r3, [r7, #112] @ 0x70 + 8005c70: fa93 f3a3 rbit r3, r3 + 8005c74: 66fb str r3, [r7, #108] @ 0x6c return result; - 8005bda: 6efb ldr r3, [r7, #108] @ 0x6c + 8005c76: 6efb ldr r3, [r7, #108] @ 0x6c { /* Check the HSE ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) - 8005bdc: fab3 f383 clz r3, r3 - 8005be0: b2db uxtb r3, r3 - 8005be2: 095b lsrs r3, r3, #5 - 8005be4: b2db uxtb r3, r3 - 8005be6: f043 0301 orr.w r3, r3, #1 - 8005bea: b2db uxtb r3, r3 - 8005bec: 2b01 cmp r3, #1 - 8005bee: d102 bne.n 8005bf6 - 8005bf0: 4b6f ldr r3, [pc, #444] @ (8005db0 ) - 8005bf2: 681b ldr r3, [r3, #0] - 8005bf4: e00f b.n 8005c16 - 8005bf6: f44f 3300 mov.w r3, #131072 @ 0x20000 - 8005bfa: 66bb str r3, [r7, #104] @ 0x68 + 8005c78: fab3 f383 clz r3, r3 + 8005c7c: b2db uxtb r3, r3 + 8005c7e: 095b lsrs r3, r3, #5 + 8005c80: b2db uxtb r3, r3 + 8005c82: f043 0301 orr.w r3, r3, #1 + 8005c86: b2db uxtb r3, r3 + 8005c88: 2b01 cmp r3, #1 + 8005c8a: d102 bne.n 8005c92 + 8005c8c: 4b6f ldr r3, [pc, #444] @ (8005e4c ) + 8005c8e: 681b ldr r3, [r3, #0] + 8005c90: e00f b.n 8005cb2 + 8005c92: f44f 3300 mov.w r3, #131072 @ 0x20000 + 8005c96: 66bb str r3, [r7, #104] @ 0x68 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8005bfc: 6ebb ldr r3, [r7, #104] @ 0x68 - 8005bfe: fa93 f3a3 rbit r3, r3 - 8005c02: 667b str r3, [r7, #100] @ 0x64 - 8005c04: f44f 3300 mov.w r3, #131072 @ 0x20000 - 8005c08: 663b str r3, [r7, #96] @ 0x60 - 8005c0a: 6e3b ldr r3, [r7, #96] @ 0x60 - 8005c0c: fa93 f3a3 rbit r3, r3 - 8005c10: 65fb str r3, [r7, #92] @ 0x5c - 8005c12: 4b67 ldr r3, [pc, #412] @ (8005db0 ) - 8005c14: 6a5b ldr r3, [r3, #36] @ 0x24 - 8005c16: f44f 3200 mov.w r2, #131072 @ 0x20000 - 8005c1a: 65ba str r2, [r7, #88] @ 0x58 - 8005c1c: 6dba ldr r2, [r7, #88] @ 0x58 - 8005c1e: fa92 f2a2 rbit r2, r2 - 8005c22: 657a str r2, [r7, #84] @ 0x54 + 8005c98: 6ebb ldr r3, [r7, #104] @ 0x68 + 8005c9a: fa93 f3a3 rbit r3, r3 + 8005c9e: 667b str r3, [r7, #100] @ 0x64 + 8005ca0: f44f 3300 mov.w r3, #131072 @ 0x20000 + 8005ca4: 663b str r3, [r7, #96] @ 0x60 + 8005ca6: 6e3b ldr r3, [r7, #96] @ 0x60 + 8005ca8: fa93 f3a3 rbit r3, r3 + 8005cac: 65fb str r3, [r7, #92] @ 0x5c + 8005cae: 4b67 ldr r3, [pc, #412] @ (8005e4c ) + 8005cb0: 6a5b ldr r3, [r3, #36] @ 0x24 + 8005cb2: f44f 3200 mov.w r2, #131072 @ 0x20000 + 8005cb6: 65ba str r2, [r7, #88] @ 0x58 + 8005cb8: 6dba ldr r2, [r7, #88] @ 0x58 + 8005cba: fa92 f2a2 rbit r2, r2 + 8005cbe: 657a str r2, [r7, #84] @ 0x54 return result; - 8005c24: 6d7a ldr r2, [r7, #84] @ 0x54 - 8005c26: fab2 f282 clz r2, r2 - 8005c2a: b2d2 uxtb r2, r2 - 8005c2c: f042 0220 orr.w r2, r2, #32 - 8005c30: b2d2 uxtb r2, r2 - 8005c32: f002 021f and.w r2, r2, #31 - 8005c36: 2101 movs r1, #1 - 8005c38: fa01 f202 lsl.w r2, r1, r2 - 8005c3c: 4013 ands r3, r2 - 8005c3e: 2b00 cmp r3, #0 - 8005c40: d17b bne.n 8005d3a + 8005cc0: 6d7a ldr r2, [r7, #84] @ 0x54 + 8005cc2: fab2 f282 clz r2, r2 + 8005cc6: b2d2 uxtb r2, r2 + 8005cc8: f042 0220 orr.w r2, r2, #32 + 8005ccc: b2d2 uxtb r2, r2 + 8005cce: f002 021f and.w r2, r2, #31 + 8005cd2: 2101 movs r1, #1 + 8005cd4: fa01 f202 lsl.w r2, r1, r2 + 8005cd8: 4013 ands r3, r2 + 8005cda: 2b00 cmp r3, #0 + 8005cdc: d17b bne.n 8005dd6 { return HAL_ERROR; - 8005c42: 2301 movs r3, #1 - 8005c44: e0f3 b.n 8005e2e + 8005cde: 2301 movs r3, #1 + 8005ce0: e0f3 b.n 8005eca } } /* PLL is selected as System Clock Source */ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) - 8005c46: 687b ldr r3, [r7, #4] - 8005c48: 685b ldr r3, [r3, #4] - 8005c4a: 2b02 cmp r3, #2 - 8005c4c: d13c bne.n 8005cc8 - 8005c4e: f04f 7300 mov.w r3, #33554432 @ 0x2000000 - 8005c52: 653b str r3, [r7, #80] @ 0x50 + 8005ce2: 687b ldr r3, [r7, #4] + 8005ce4: 685b ldr r3, [r3, #4] + 8005ce6: 2b02 cmp r3, #2 + 8005ce8: d13c bne.n 8005d64 + 8005cea: f04f 7300 mov.w r3, #33554432 @ 0x2000000 + 8005cee: 653b str r3, [r7, #80] @ 0x50 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8005c54: 6d3b ldr r3, [r7, #80] @ 0x50 - 8005c56: fa93 f3a3 rbit r3, r3 - 8005c5a: 64fb str r3, [r7, #76] @ 0x4c + 8005cf0: 6d3b ldr r3, [r7, #80] @ 0x50 + 8005cf2: fa93 f3a3 rbit r3, r3 + 8005cf6: 64fb str r3, [r7, #76] @ 0x4c return result; - 8005c5c: 6cfb ldr r3, [r7, #76] @ 0x4c + 8005cf8: 6cfb ldr r3, [r7, #76] @ 0x4c { /* Check the PLL ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) - 8005c5e: fab3 f383 clz r3, r3 - 8005c62: b2db uxtb r3, r3 - 8005c64: 095b lsrs r3, r3, #5 - 8005c66: b2db uxtb r3, r3 - 8005c68: f043 0301 orr.w r3, r3, #1 - 8005c6c: b2db uxtb r3, r3 - 8005c6e: 2b01 cmp r3, #1 - 8005c70: d102 bne.n 8005c78 - 8005c72: 4b4f ldr r3, [pc, #316] @ (8005db0 ) - 8005c74: 681b ldr r3, [r3, #0] - 8005c76: e00f b.n 8005c98 - 8005c78: f04f 7300 mov.w r3, #33554432 @ 0x2000000 - 8005c7c: 64bb str r3, [r7, #72] @ 0x48 + 8005cfa: fab3 f383 clz r3, r3 + 8005cfe: b2db uxtb r3, r3 + 8005d00: 095b lsrs r3, r3, #5 + 8005d02: b2db uxtb r3, r3 + 8005d04: f043 0301 orr.w r3, r3, #1 + 8005d08: b2db uxtb r3, r3 + 8005d0a: 2b01 cmp r3, #1 + 8005d0c: d102 bne.n 8005d14 + 8005d0e: 4b4f ldr r3, [pc, #316] @ (8005e4c ) + 8005d10: 681b ldr r3, [r3, #0] + 8005d12: e00f b.n 8005d34 + 8005d14: f04f 7300 mov.w r3, #33554432 @ 0x2000000 + 8005d18: 64bb str r3, [r7, #72] @ 0x48 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8005c7e: 6cbb ldr r3, [r7, #72] @ 0x48 - 8005c80: fa93 f3a3 rbit r3, r3 - 8005c84: 647b str r3, [r7, #68] @ 0x44 - 8005c86: f04f 7300 mov.w r3, #33554432 @ 0x2000000 - 8005c8a: 643b str r3, [r7, #64] @ 0x40 - 8005c8c: 6c3b ldr r3, [r7, #64] @ 0x40 - 8005c8e: fa93 f3a3 rbit r3, r3 - 8005c92: 63fb str r3, [r7, #60] @ 0x3c - 8005c94: 4b46 ldr r3, [pc, #280] @ (8005db0 ) - 8005c96: 6a5b ldr r3, [r3, #36] @ 0x24 - 8005c98: f04f 7200 mov.w r2, #33554432 @ 0x2000000 - 8005c9c: 63ba str r2, [r7, #56] @ 0x38 - 8005c9e: 6bba ldr r2, [r7, #56] @ 0x38 - 8005ca0: fa92 f2a2 rbit r2, r2 - 8005ca4: 637a str r2, [r7, #52] @ 0x34 + 8005d1a: 6cbb ldr r3, [r7, #72] @ 0x48 + 8005d1c: fa93 f3a3 rbit r3, r3 + 8005d20: 647b str r3, [r7, #68] @ 0x44 + 8005d22: f04f 7300 mov.w r3, #33554432 @ 0x2000000 + 8005d26: 643b str r3, [r7, #64] @ 0x40 + 8005d28: 6c3b ldr r3, [r7, #64] @ 0x40 + 8005d2a: fa93 f3a3 rbit r3, r3 + 8005d2e: 63fb str r3, [r7, #60] @ 0x3c + 8005d30: 4b46 ldr r3, [pc, #280] @ (8005e4c ) + 8005d32: 6a5b ldr r3, [r3, #36] @ 0x24 + 8005d34: f04f 7200 mov.w r2, #33554432 @ 0x2000000 + 8005d38: 63ba str r2, [r7, #56] @ 0x38 + 8005d3a: 6bba ldr r2, [r7, #56] @ 0x38 + 8005d3c: fa92 f2a2 rbit r2, r2 + 8005d40: 637a str r2, [r7, #52] @ 0x34 return result; - 8005ca6: 6b7a ldr r2, [r7, #52] @ 0x34 - 8005ca8: fab2 f282 clz r2, r2 - 8005cac: b2d2 uxtb r2, r2 - 8005cae: f042 0220 orr.w r2, r2, #32 - 8005cb2: b2d2 uxtb r2, r2 - 8005cb4: f002 021f and.w r2, r2, #31 - 8005cb8: 2101 movs r1, #1 - 8005cba: fa01 f202 lsl.w r2, r1, r2 - 8005cbe: 4013 ands r3, r2 - 8005cc0: 2b00 cmp r3, #0 - 8005cc2: d13a bne.n 8005d3a + 8005d42: 6b7a ldr r2, [r7, #52] @ 0x34 + 8005d44: fab2 f282 clz r2, r2 + 8005d48: b2d2 uxtb r2, r2 + 8005d4a: f042 0220 orr.w r2, r2, #32 + 8005d4e: b2d2 uxtb r2, r2 + 8005d50: f002 021f and.w r2, r2, #31 + 8005d54: 2101 movs r1, #1 + 8005d56: fa01 f202 lsl.w r2, r1, r2 + 8005d5a: 4013 ands r3, r2 + 8005d5c: 2b00 cmp r3, #0 + 8005d5e: d13a bne.n 8005dd6 { return HAL_ERROR; - 8005cc4: 2301 movs r3, #1 - 8005cc6: e0b2 b.n 8005e2e - 8005cc8: 2302 movs r3, #2 - 8005cca: 633b str r3, [r7, #48] @ 0x30 + 8005d60: 2301 movs r3, #1 + 8005d62: e0b2 b.n 8005eca + 8005d64: 2302 movs r3, #2 + 8005d66: 633b str r3, [r7, #48] @ 0x30 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8005ccc: 6b3b ldr r3, [r7, #48] @ 0x30 - 8005cce: fa93 f3a3 rbit r3, r3 - 8005cd2: 62fb str r3, [r7, #44] @ 0x2c + 8005d68: 6b3b ldr r3, [r7, #48] @ 0x30 + 8005d6a: fa93 f3a3 rbit r3, r3 + 8005d6e: 62fb str r3, [r7, #44] @ 0x2c return result; - 8005cd4: 6afb ldr r3, [r7, #44] @ 0x2c + 8005d70: 6afb ldr r3, [r7, #44] @ 0x2c } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) - 8005cd6: fab3 f383 clz r3, r3 - 8005cda: b2db uxtb r3, r3 - 8005cdc: 095b lsrs r3, r3, #5 - 8005cde: b2db uxtb r3, r3 - 8005ce0: f043 0301 orr.w r3, r3, #1 - 8005ce4: b2db uxtb r3, r3 - 8005ce6: 2b01 cmp r3, #1 - 8005ce8: d102 bne.n 8005cf0 - 8005cea: 4b31 ldr r3, [pc, #196] @ (8005db0 ) - 8005cec: 681b ldr r3, [r3, #0] - 8005cee: e00d b.n 8005d0c - 8005cf0: 2302 movs r3, #2 - 8005cf2: 62bb str r3, [r7, #40] @ 0x28 + 8005d72: fab3 f383 clz r3, r3 + 8005d76: b2db uxtb r3, r3 + 8005d78: 095b lsrs r3, r3, #5 + 8005d7a: b2db uxtb r3, r3 + 8005d7c: f043 0301 orr.w r3, r3, #1 + 8005d80: b2db uxtb r3, r3 + 8005d82: 2b01 cmp r3, #1 + 8005d84: d102 bne.n 8005d8c + 8005d86: 4b31 ldr r3, [pc, #196] @ (8005e4c ) + 8005d88: 681b ldr r3, [r3, #0] + 8005d8a: e00d b.n 8005da8 + 8005d8c: 2302 movs r3, #2 + 8005d8e: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8005cf4: 6abb ldr r3, [r7, #40] @ 0x28 - 8005cf6: fa93 f3a3 rbit r3, r3 - 8005cfa: 627b str r3, [r7, #36] @ 0x24 - 8005cfc: 2302 movs r3, #2 - 8005cfe: 623b str r3, [r7, #32] - 8005d00: 6a3b ldr r3, [r7, #32] - 8005d02: fa93 f3a3 rbit r3, r3 - 8005d06: 61fb str r3, [r7, #28] - 8005d08: 4b29 ldr r3, [pc, #164] @ (8005db0 ) - 8005d0a: 6a5b ldr r3, [r3, #36] @ 0x24 - 8005d0c: 2202 movs r2, #2 - 8005d0e: 61ba str r2, [r7, #24] - 8005d10: 69ba ldr r2, [r7, #24] - 8005d12: fa92 f2a2 rbit r2, r2 - 8005d16: 617a str r2, [r7, #20] + 8005d90: 6abb ldr r3, [r7, #40] @ 0x28 + 8005d92: fa93 f3a3 rbit r3, r3 + 8005d96: 627b str r3, [r7, #36] @ 0x24 + 8005d98: 2302 movs r3, #2 + 8005d9a: 623b str r3, [r7, #32] + 8005d9c: 6a3b ldr r3, [r7, #32] + 8005d9e: fa93 f3a3 rbit r3, r3 + 8005da2: 61fb str r3, [r7, #28] + 8005da4: 4b29 ldr r3, [pc, #164] @ (8005e4c ) + 8005da6: 6a5b ldr r3, [r3, #36] @ 0x24 + 8005da8: 2202 movs r2, #2 + 8005daa: 61ba str r2, [r7, #24] + 8005dac: 69ba ldr r2, [r7, #24] + 8005dae: fa92 f2a2 rbit r2, r2 + 8005db2: 617a str r2, [r7, #20] return result; - 8005d18: 697a ldr r2, [r7, #20] - 8005d1a: fab2 f282 clz r2, r2 - 8005d1e: b2d2 uxtb r2, r2 - 8005d20: f042 0220 orr.w r2, r2, #32 - 8005d24: b2d2 uxtb r2, r2 - 8005d26: f002 021f and.w r2, r2, #31 - 8005d2a: 2101 movs r1, #1 - 8005d2c: fa01 f202 lsl.w r2, r1, r2 - 8005d30: 4013 ands r3, r2 - 8005d32: 2b00 cmp r3, #0 - 8005d34: d101 bne.n 8005d3a + 8005db4: 697a ldr r2, [r7, #20] + 8005db6: fab2 f282 clz r2, r2 + 8005dba: b2d2 uxtb r2, r2 + 8005dbc: f042 0220 orr.w r2, r2, #32 + 8005dc0: b2d2 uxtb r2, r2 + 8005dc2: f002 021f and.w r2, r2, #31 + 8005dc6: 2101 movs r1, #1 + 8005dc8: fa01 f202 lsl.w r2, r1, r2 + 8005dcc: 4013 ands r3, r2 + 8005dce: 2b00 cmp r3, #0 + 8005dd0: d101 bne.n 8005dd6 { return HAL_ERROR; - 8005d36: 2301 movs r3, #1 - 8005d38: e079 b.n 8005e2e + 8005dd2: 2301 movs r3, #1 + 8005dd4: e079 b.n 8005eca } } __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); - 8005d3a: 4b1d ldr r3, [pc, #116] @ (8005db0 ) - 8005d3c: 685b ldr r3, [r3, #4] - 8005d3e: f023 0203 bic.w r2, r3, #3 - 8005d42: 687b ldr r3, [r7, #4] - 8005d44: 685b ldr r3, [r3, #4] - 8005d46: 491a ldr r1, [pc, #104] @ (8005db0 ) - 8005d48: 4313 orrs r3, r2 - 8005d4a: 604b str r3, [r1, #4] + 8005dd6: 4b1d ldr r3, [pc, #116] @ (8005e4c ) + 8005dd8: 685b ldr r3, [r3, #4] + 8005dda: f023 0203 bic.w r2, r3, #3 + 8005dde: 687b ldr r3, [r7, #4] + 8005de0: 685b ldr r3, [r3, #4] + 8005de2: 491a ldr r1, [pc, #104] @ (8005e4c ) + 8005de4: 4313 orrs r3, r2 + 8005de6: 604b str r3, [r1, #4] /* Get Start Tick */ tickstart = HAL_GetTick(); - 8005d4c: f7fc fa8c bl 8002268 - 8005d50: 6778 str r0, [r7, #116] @ 0x74 + 8005de8: f7fc fa8c bl 8002304 + 8005dec: 6778 str r0, [r7, #116] @ 0x74 while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) - 8005d52: e00a b.n 8005d6a + 8005dee: e00a b.n 8005e06 { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) - 8005d54: f7fc fa88 bl 8002268 - 8005d58: 4602 mov r2, r0 - 8005d5a: 6f7b ldr r3, [r7, #116] @ 0x74 - 8005d5c: 1ad3 subs r3, r2, r3 - 8005d5e: f241 3288 movw r2, #5000 @ 0x1388 - 8005d62: 4293 cmp r3, r2 - 8005d64: d901 bls.n 8005d6a + 8005df0: f7fc fa88 bl 8002304 + 8005df4: 4602 mov r2, r0 + 8005df6: 6f7b ldr r3, [r7, #116] @ 0x74 + 8005df8: 1ad3 subs r3, r2, r3 + 8005dfa: f241 3288 movw r2, #5000 @ 0x1388 + 8005dfe: 4293 cmp r3, r2 + 8005e00: d901 bls.n 8005e06 { return HAL_TIMEOUT; - 8005d66: 2303 movs r3, #3 - 8005d68: e061 b.n 8005e2e + 8005e02: 2303 movs r3, #3 + 8005e04: e061 b.n 8005eca while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) - 8005d6a: 4b11 ldr r3, [pc, #68] @ (8005db0 ) - 8005d6c: 685b ldr r3, [r3, #4] - 8005d6e: f003 020c and.w r2, r3, #12 - 8005d72: 687b ldr r3, [r7, #4] - 8005d74: 685b ldr r3, [r3, #4] - 8005d76: 009b lsls r3, r3, #2 - 8005d78: 429a cmp r2, r3 - 8005d7a: d1eb bne.n 8005d54 + 8005e06: 4b11 ldr r3, [pc, #68] @ (8005e4c ) + 8005e08: 685b ldr r3, [r3, #4] + 8005e0a: f003 020c and.w r2, r3, #12 + 8005e0e: 687b ldr r3, [r7, #4] + 8005e10: 685b ldr r3, [r3, #4] + 8005e12: 009b lsls r3, r3, #2 + 8005e14: 429a cmp r2, r3 + 8005e16: d1eb bne.n 8005df0 } } } /* Decreasing the number of wait states because of lower CPU frequency */ if(FLatency < __HAL_FLASH_GET_LATENCY()) - 8005d7c: 4b0b ldr r3, [pc, #44] @ (8005dac ) - 8005d7e: 681b ldr r3, [r3, #0] - 8005d80: f003 0307 and.w r3, r3, #7 - 8005d84: 683a ldr r2, [r7, #0] - 8005d86: 429a cmp r2, r3 - 8005d88: d214 bcs.n 8005db4 + 8005e18: 4b0b ldr r3, [pc, #44] @ (8005e48 ) + 8005e1a: 681b ldr r3, [r3, #0] + 8005e1c: f003 0307 and.w r3, r3, #7 + 8005e20: 683a ldr r2, [r7, #0] + 8005e22: 429a cmp r2, r3 + 8005e24: d214 bcs.n 8005e50 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); - 8005d8a: 4b08 ldr r3, [pc, #32] @ (8005dac ) - 8005d8c: 681b ldr r3, [r3, #0] - 8005d8e: f023 0207 bic.w r2, r3, #7 - 8005d92: 4906 ldr r1, [pc, #24] @ (8005dac ) - 8005d94: 683b ldr r3, [r7, #0] - 8005d96: 4313 orrs r3, r2 - 8005d98: 600b str r3, [r1, #0] + 8005e26: 4b08 ldr r3, [pc, #32] @ (8005e48 ) + 8005e28: 681b ldr r3, [r3, #0] + 8005e2a: f023 0207 bic.w r2, r3, #7 + 8005e2e: 4906 ldr r1, [pc, #24] @ (8005e48 ) + 8005e30: 683b ldr r3, [r7, #0] + 8005e32: 4313 orrs r3, r2 + 8005e34: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if(__HAL_FLASH_GET_LATENCY() != FLatency) - 8005d9a: 4b04 ldr r3, [pc, #16] @ (8005dac ) - 8005d9c: 681b ldr r3, [r3, #0] - 8005d9e: f003 0307 and.w r3, r3, #7 - 8005da2: 683a ldr r2, [r7, #0] - 8005da4: 429a cmp r2, r3 - 8005da6: d005 beq.n 8005db4 + 8005e36: 4b04 ldr r3, [pc, #16] @ (8005e48 ) + 8005e38: 681b ldr r3, [r3, #0] + 8005e3a: f003 0307 and.w r3, r3, #7 + 8005e3e: 683a ldr r2, [r7, #0] + 8005e40: 429a cmp r2, r3 + 8005e42: d005 beq.n 8005e50 { return HAL_ERROR; - 8005da8: 2301 movs r3, #1 - 8005daa: e040 b.n 8005e2e - 8005dac: 40022000 .word 0x40022000 - 8005db0: 40021000 .word 0x40021000 + 8005e44: 2301 movs r3, #1 + 8005e46: e040 b.n 8005eca + 8005e48: 40022000 .word 0x40022000 + 8005e4c: 40021000 .word 0x40021000 } } /*-------------------------- PCLK1 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) - 8005db4: 687b ldr r3, [r7, #4] - 8005db6: 681b ldr r3, [r3, #0] - 8005db8: f003 0304 and.w r3, r3, #4 - 8005dbc: 2b00 cmp r3, #0 - 8005dbe: d008 beq.n 8005dd2 + 8005e50: 687b ldr r3, [r7, #4] + 8005e52: 681b ldr r3, [r3, #0] + 8005e54: f003 0304 and.w r3, r3, #4 + 8005e58: 2b00 cmp r3, #0 + 8005e5a: d008 beq.n 8005e6e { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); - 8005dc0: 4b1d ldr r3, [pc, #116] @ (8005e38 ) - 8005dc2: 685b ldr r3, [r3, #4] - 8005dc4: f423 62e0 bic.w r2, r3, #1792 @ 0x700 - 8005dc8: 687b ldr r3, [r7, #4] - 8005dca: 68db ldr r3, [r3, #12] - 8005dcc: 491a ldr r1, [pc, #104] @ (8005e38 ) - 8005dce: 4313 orrs r3, r2 - 8005dd0: 604b str r3, [r1, #4] + 8005e5c: 4b1d ldr r3, [pc, #116] @ (8005ed4 ) + 8005e5e: 685b ldr r3, [r3, #4] + 8005e60: f423 62e0 bic.w r2, r3, #1792 @ 0x700 + 8005e64: 687b ldr r3, [r7, #4] + 8005e66: 68db ldr r3, [r3, #12] + 8005e68: 491a ldr r1, [pc, #104] @ (8005ed4 ) + 8005e6a: 4313 orrs r3, r2 + 8005e6c: 604b str r3, [r1, #4] } /*-------------------------- PCLK2 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) - 8005dd2: 687b ldr r3, [r7, #4] - 8005dd4: 681b ldr r3, [r3, #0] - 8005dd6: f003 0308 and.w r3, r3, #8 - 8005dda: 2b00 cmp r3, #0 - 8005ddc: d009 beq.n 8005df2 + 8005e6e: 687b ldr r3, [r7, #4] + 8005e70: 681b ldr r3, [r3, #0] + 8005e72: f003 0308 and.w r3, r3, #8 + 8005e76: 2b00 cmp r3, #0 + 8005e78: d009 beq.n 8005e8e { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); - 8005dde: 4b16 ldr r3, [pc, #88] @ (8005e38 ) - 8005de0: 685b ldr r3, [r3, #4] - 8005de2: f423 5260 bic.w r2, r3, #14336 @ 0x3800 - 8005de6: 687b ldr r3, [r7, #4] - 8005de8: 691b ldr r3, [r3, #16] - 8005dea: 00db lsls r3, r3, #3 - 8005dec: 4912 ldr r1, [pc, #72] @ (8005e38 ) - 8005dee: 4313 orrs r3, r2 - 8005df0: 604b str r3, [r1, #4] + 8005e7a: 4b16 ldr r3, [pc, #88] @ (8005ed4 ) + 8005e7c: 685b ldr r3, [r3, #4] + 8005e7e: f423 5260 bic.w r2, r3, #14336 @ 0x3800 + 8005e82: 687b ldr r3, [r7, #4] + 8005e84: 691b ldr r3, [r3, #16] + 8005e86: 00db lsls r3, r3, #3 + 8005e88: 4912 ldr r1, [pc, #72] @ (8005ed4 ) + 8005e8a: 4313 orrs r3, r2 + 8005e8c: 604b str r3, [r1, #4] } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER]; - 8005df2: f000 f829 bl 8005e48 - 8005df6: 4601 mov r1, r0 - 8005df8: 4b0f ldr r3, [pc, #60] @ (8005e38 ) - 8005dfa: 685b ldr r3, [r3, #4] - 8005dfc: f003 03f0 and.w r3, r3, #240 @ 0xf0 - 8005e00: 22f0 movs r2, #240 @ 0xf0 - 8005e02: 613a str r2, [r7, #16] + 8005e8e: f000 f829 bl 8005ee4 + 8005e92: 4601 mov r1, r0 + 8005e94: 4b0f ldr r3, [pc, #60] @ (8005ed4 ) + 8005e96: 685b ldr r3, [r3, #4] + 8005e98: f003 03f0 and.w r3, r3, #240 @ 0xf0 + 8005e9c: 22f0 movs r2, #240 @ 0xf0 + 8005e9e: 613a str r2, [r7, #16] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8005e04: 693a ldr r2, [r7, #16] - 8005e06: fa92 f2a2 rbit r2, r2 - 8005e0a: 60fa str r2, [r7, #12] + 8005ea0: 693a ldr r2, [r7, #16] + 8005ea2: fa92 f2a2 rbit r2, r2 + 8005ea6: 60fa str r2, [r7, #12] return result; - 8005e0c: 68fa ldr r2, [r7, #12] - 8005e0e: fab2 f282 clz r2, r2 - 8005e12: b2d2 uxtb r2, r2 - 8005e14: 40d3 lsrs r3, r2 - 8005e16: 4a09 ldr r2, [pc, #36] @ (8005e3c ) - 8005e18: 5cd3 ldrb r3, [r2, r3] - 8005e1a: fa21 f303 lsr.w r3, r1, r3 - 8005e1e: 4a08 ldr r2, [pc, #32] @ (8005e40 ) - 8005e20: 6013 str r3, [r2, #0] + 8005ea8: 68fa ldr r2, [r7, #12] + 8005eaa: fab2 f282 clz r2, r2 + 8005eae: b2d2 uxtb r2, r2 + 8005eb0: 40d3 lsrs r3, r2 + 8005eb2: 4a09 ldr r2, [pc, #36] @ (8005ed8 ) + 8005eb4: 5cd3 ldrb r3, [r2, r3] + 8005eb6: fa21 f303 lsr.w r3, r1, r3 + 8005eba: 4a08 ldr r2, [pc, #32] @ (8005edc ) + 8005ebc: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings*/ HAL_InitTick (uwTickPrio); - 8005e22: 4b08 ldr r3, [pc, #32] @ (8005e44 ) - 8005e24: 681b ldr r3, [r3, #0] - 8005e26: 4618 mov r0, r3 - 8005e28: f7fc f9da bl 80021e0 + 8005ebe: 4b08 ldr r3, [pc, #32] @ (8005ee0 ) + 8005ec0: 681b ldr r3, [r3, #0] + 8005ec2: 4618 mov r0, r3 + 8005ec4: f7fc f9da bl 800227c return HAL_OK; - 8005e2c: 2300 movs r3, #0 + 8005ec8: 2300 movs r3, #0 } - 8005e2e: 4618 mov r0, r3 - 8005e30: 3778 adds r7, #120 @ 0x78 - 8005e32: 46bd mov sp, r7 - 8005e34: bd80 pop {r7, pc} - 8005e36: bf00 nop - 8005e38: 40021000 .word 0x40021000 - 8005e3c: 080071b0 .word 0x080071b0 - 8005e40: 20000000 .word 0x20000000 - 8005e44: 20000004 .word 0x20000004 + 8005eca: 4618 mov r0, r3 + 8005ecc: 3778 adds r7, #120 @ 0x78 + 8005ece: 46bd mov sp, r7 + 8005ed0: bd80 pop {r7, pc} + 8005ed2: bf00 nop + 8005ed4: 40021000 .word 0x40021000 + 8005ed8: 0800724c .word 0x0800724c + 8005edc: 20000000 .word 0x20000000 + 8005ee0: 20000004 .word 0x20000004 -08005e48 : +08005ee4 : * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { - 8005e48: b480 push {r7} - 8005e4a: b087 sub sp, #28 - 8005e4c: af00 add r7, sp, #0 + 8005ee4: b480 push {r7} + 8005ee6: b087 sub sp, #28 + 8005ee8: af00 add r7, sp, #0 uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U; - 8005e4e: 2300 movs r3, #0 - 8005e50: 60fb str r3, [r7, #12] - 8005e52: 2300 movs r3, #0 - 8005e54: 60bb str r3, [r7, #8] - 8005e56: 2300 movs r3, #0 - 8005e58: 617b str r3, [r7, #20] - 8005e5a: 2300 movs r3, #0 - 8005e5c: 607b str r3, [r7, #4] + 8005eea: 2300 movs r3, #0 + 8005eec: 60fb str r3, [r7, #12] + 8005eee: 2300 movs r3, #0 + 8005ef0: 60bb str r3, [r7, #8] + 8005ef2: 2300 movs r3, #0 + 8005ef4: 617b str r3, [r7, #20] + 8005ef6: 2300 movs r3, #0 + 8005ef8: 607b str r3, [r7, #4] uint32_t sysclockfreq = 0U; - 8005e5e: 2300 movs r3, #0 - 8005e60: 613b str r3, [r7, #16] + 8005efa: 2300 movs r3, #0 + 8005efc: 613b str r3, [r7, #16] tmpreg = RCC->CFGR; - 8005e62: 4b1e ldr r3, [pc, #120] @ (8005edc ) - 8005e64: 685b ldr r3, [r3, #4] - 8005e66: 60fb str r3, [r7, #12] + 8005efe: 4b1e ldr r3, [pc, #120] @ (8005f78 ) + 8005f00: 685b ldr r3, [r3, #4] + 8005f02: 60fb str r3, [r7, #12] /* Get SYSCLK source -------------------------------------------------------*/ switch (tmpreg & RCC_CFGR_SWS) - 8005e68: 68fb ldr r3, [r7, #12] - 8005e6a: f003 030c and.w r3, r3, #12 - 8005e6e: 2b04 cmp r3, #4 - 8005e70: d002 beq.n 8005e78 - 8005e72: 2b08 cmp r3, #8 - 8005e74: d003 beq.n 8005e7e - 8005e76: e026 b.n 8005ec6 + 8005f04: 68fb ldr r3, [r7, #12] + 8005f06: f003 030c and.w r3, r3, #12 + 8005f0a: 2b04 cmp r3, #4 + 8005f0c: d002 beq.n 8005f14 + 8005f0e: 2b08 cmp r3, #8 + 8005f10: d003 beq.n 8005f1a + 8005f12: e026 b.n 8005f62 { case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ { sysclockfreq = HSE_VALUE; - 8005e78: 4b19 ldr r3, [pc, #100] @ (8005ee0 ) - 8005e7a: 613b str r3, [r7, #16] + 8005f14: 4b19 ldr r3, [pc, #100] @ (8005f7c ) + 8005f16: 613b str r3, [r7, #16] break; - 8005e7c: e026 b.n 8005ecc + 8005f18: e026 b.n 8005f68 } case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ { pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_Pos]; - 8005e7e: 68fb ldr r3, [r7, #12] - 8005e80: 0c9b lsrs r3, r3, #18 - 8005e82: f003 030f and.w r3, r3, #15 - 8005e86: 4a17 ldr r2, [pc, #92] @ (8005ee4 ) - 8005e88: 5cd3 ldrb r3, [r2, r3] - 8005e8a: 607b str r3, [r7, #4] + 8005f1a: 68fb ldr r3, [r7, #12] + 8005f1c: 0c9b lsrs r3, r3, #18 + 8005f1e: f003 030f and.w r3, r3, #15 + 8005f22: 4a17 ldr r2, [pc, #92] @ (8005f80 ) + 8005f24: 5cd3 ldrb r3, [r2, r3] + 8005f26: 607b str r3, [r7, #4] prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV) >> RCC_CFGR2_PREDIV_Pos]; - 8005e8c: 4b13 ldr r3, [pc, #76] @ (8005edc ) - 8005e8e: 6adb ldr r3, [r3, #44] @ 0x2c - 8005e90: f003 030f and.w r3, r3, #15 - 8005e94: 4a14 ldr r2, [pc, #80] @ (8005ee8 ) - 8005e96: 5cd3 ldrb r3, [r2, r3] - 8005e98: 60bb str r3, [r7, #8] + 8005f28: 4b13 ldr r3, [pc, #76] @ (8005f78 ) + 8005f2a: 6adb ldr r3, [r3, #44] @ 0x2c + 8005f2c: f003 030f and.w r3, r3, #15 + 8005f30: 4a14 ldr r2, [pc, #80] @ (8005f84 ) + 8005f32: 5cd3 ldrb r3, [r2, r3] + 8005f34: 60bb str r3, [r7, #8] #if defined(RCC_CFGR_PLLSRC_HSI_DIV2) if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI) - 8005e9a: 68fb ldr r3, [r7, #12] - 8005e9c: f403 3380 and.w r3, r3, #65536 @ 0x10000 - 8005ea0: 2b00 cmp r3, #0 - 8005ea2: d008 beq.n 8005eb6 + 8005f36: 68fb ldr r3, [r7, #12] + 8005f38: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 8005f3c: 2b00 cmp r3, #0 + 8005f3e: d008 beq.n 8005f52 { /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */ pllclk = (uint32_t)((uint64_t) HSE_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul); - 8005ea4: 4a0e ldr r2, [pc, #56] @ (8005ee0 ) - 8005ea6: 68bb ldr r3, [r7, #8] - 8005ea8: fbb2 f2f3 udiv r2, r2, r3 - 8005eac: 687b ldr r3, [r7, #4] - 8005eae: fb02 f303 mul.w r3, r2, r3 - 8005eb2: 617b str r3, [r7, #20] - 8005eb4: e004 b.n 8005ec0 + 8005f40: 4a0e ldr r2, [pc, #56] @ (8005f7c ) + 8005f42: 68bb ldr r3, [r7, #8] + 8005f44: fbb2 f2f3 udiv r2, r2, r3 + 8005f48: 687b ldr r3, [r7, #4] + 8005f4a: fb02 f303 mul.w r3, r2, r3 + 8005f4e: 617b str r3, [r7, #20] + 8005f50: e004 b.n 8005f5c } else { /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ pllclk = (uint32_t)((uint64_t) (HSI_VALUE >> 1U) * ((uint64_t) pllmul)); - 8005eb6: 687b ldr r3, [r7, #4] - 8005eb8: 4a0c ldr r2, [pc, #48] @ (8005eec ) - 8005eba: fb02 f303 mul.w r3, r2, r3 - 8005ebe: 617b str r3, [r7, #20] + 8005f52: 687b ldr r3, [r7, #4] + 8005f54: 4a0c ldr r2, [pc, #48] @ (8005f88 ) + 8005f56: fb02 f303 mul.w r3, r2, r3 + 8005f5a: 617b str r3, [r7, #20] { /* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */ pllclk = (uint32_t)((uint64_t) HSI_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul); } #endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */ sysclockfreq = pllclk; - 8005ec0: 697b ldr r3, [r7, #20] - 8005ec2: 613b str r3, [r7, #16] + 8005f5c: 697b ldr r3, [r7, #20] + 8005f5e: 613b str r3, [r7, #16] break; - 8005ec4: e002 b.n 8005ecc + 8005f60: e002 b.n 8005f68 } case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ default: /* HSI used as system clock */ { sysclockfreq = HSI_VALUE; - 8005ec6: 4b0a ldr r3, [pc, #40] @ (8005ef0 ) - 8005ec8: 613b str r3, [r7, #16] + 8005f62: 4b0a ldr r3, [pc, #40] @ (8005f8c ) + 8005f64: 613b str r3, [r7, #16] break; - 8005eca: bf00 nop + 8005f66: bf00 nop } } return sysclockfreq; - 8005ecc: 693b ldr r3, [r7, #16] + 8005f68: 693b ldr r3, [r7, #16] } - 8005ece: 4618 mov r0, r3 - 8005ed0: 371c adds r7, #28 - 8005ed2: 46bd mov sp, r7 - 8005ed4: f85d 7b04 ldr.w r7, [sp], #4 - 8005ed8: 4770 bx lr - 8005eda: bf00 nop - 8005edc: 40021000 .word 0x40021000 - 8005ee0: 00f42400 .word 0x00f42400 - 8005ee4: 080071c8 .word 0x080071c8 - 8005ee8: 080071d8 .word 0x080071d8 - 8005eec: 003d0900 .word 0x003d0900 - 8005ef0: 007a1200 .word 0x007a1200 + 8005f6a: 4618 mov r0, r3 + 8005f6c: 371c adds r7, #28 + 8005f6e: 46bd mov sp, r7 + 8005f70: f85d 7b04 ldr.w r7, [sp], #4 + 8005f74: 4770 bx lr + 8005f76: bf00 nop + 8005f78: 40021000 .word 0x40021000 + 8005f7c: 00f42400 .word 0x00f42400 + 8005f80: 08007264 .word 0x08007264 + 8005f84: 08007274 .word 0x08007274 + 8005f88: 003d0900 .word 0x003d0900 + 8005f8c: 007a1200 .word 0x007a1200 -08005ef4 : +08005f90 : * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency * and updated within this function * @retval HCLK frequency */ uint32_t HAL_RCC_GetHCLKFreq(void) { - 8005ef4: b480 push {r7} - 8005ef6: af00 add r7, sp, #0 + 8005f90: b480 push {r7} + 8005f92: af00 add r7, sp, #0 return SystemCoreClock; - 8005ef8: 4b03 ldr r3, [pc, #12] @ (8005f08 ) - 8005efa: 681b ldr r3, [r3, #0] + 8005f94: 4b03 ldr r3, [pc, #12] @ (8005fa4 ) + 8005f96: 681b ldr r3, [r3, #0] } - 8005efc: 4618 mov r0, r3 - 8005efe: 46bd mov sp, r7 - 8005f00: f85d 7b04 ldr.w r7, [sp], #4 - 8005f04: 4770 bx lr - 8005f06: bf00 nop - 8005f08: 20000000 .word 0x20000000 + 8005f98: 4618 mov r0, r3 + 8005f9a: 46bd mov sp, r7 + 8005f9c: f85d 7b04 ldr.w r7, [sp], #4 + 8005fa0: 4770 bx lr + 8005fa2: bf00 nop + 8005fa4: 20000000 .word 0x20000000 -08005f0c : +08005fa8 : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK1Freq(void) { - 8005f0c: b580 push {r7, lr} - 8005f0e: b082 sub sp, #8 - 8005f10: af00 add r7, sp, #0 + 8005fa8: b580 push {r7, lr} + 8005faa: b082 sub sp, #8 + 8005fac: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_BITNUMBER]); - 8005f12: f7ff ffef bl 8005ef4 - 8005f16: 4601 mov r1, r0 - 8005f18: 4b0b ldr r3, [pc, #44] @ (8005f48 ) - 8005f1a: 685b ldr r3, [r3, #4] - 8005f1c: f403 63e0 and.w r3, r3, #1792 @ 0x700 - 8005f20: f44f 62e0 mov.w r2, #1792 @ 0x700 - 8005f24: 607a str r2, [r7, #4] + 8005fae: f7ff ffef bl 8005f90 + 8005fb2: 4601 mov r1, r0 + 8005fb4: 4b0b ldr r3, [pc, #44] @ (8005fe4 ) + 8005fb6: 685b ldr r3, [r3, #4] + 8005fb8: f403 63e0 and.w r3, r3, #1792 @ 0x700 + 8005fbc: f44f 62e0 mov.w r2, #1792 @ 0x700 + 8005fc0: 607a str r2, [r7, #4] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8005f26: 687a ldr r2, [r7, #4] - 8005f28: fa92 f2a2 rbit r2, r2 - 8005f2c: 603a str r2, [r7, #0] + 8005fc2: 687a ldr r2, [r7, #4] + 8005fc4: fa92 f2a2 rbit r2, r2 + 8005fc8: 603a str r2, [r7, #0] return result; - 8005f2e: 683a ldr r2, [r7, #0] - 8005f30: fab2 f282 clz r2, r2 - 8005f34: b2d2 uxtb r2, r2 - 8005f36: 40d3 lsrs r3, r2 - 8005f38: 4a04 ldr r2, [pc, #16] @ (8005f4c ) - 8005f3a: 5cd3 ldrb r3, [r2, r3] - 8005f3c: fa21 f303 lsr.w r3, r1, r3 + 8005fca: 683a ldr r2, [r7, #0] + 8005fcc: fab2 f282 clz r2, r2 + 8005fd0: b2d2 uxtb r2, r2 + 8005fd2: 40d3 lsrs r3, r2 + 8005fd4: 4a04 ldr r2, [pc, #16] @ (8005fe8 ) + 8005fd6: 5cd3 ldrb r3, [r2, r3] + 8005fd8: fa21 f303 lsr.w r3, r1, r3 } - 8005f40: 4618 mov r0, r3 - 8005f42: 3708 adds r7, #8 - 8005f44: 46bd mov sp, r7 - 8005f46: bd80 pop {r7, pc} - 8005f48: 40021000 .word 0x40021000 - 8005f4c: 080071c0 .word 0x080071c0 + 8005fdc: 4618 mov r0, r3 + 8005fde: 3708 adds r7, #8 + 8005fe0: 46bd mov sp, r7 + 8005fe2: bd80 pop {r7, pc} + 8005fe4: 40021000 .word 0x40021000 + 8005fe8: 0800725c .word 0x0800725c -08005f50 : +08005fec : * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK2 frequency */ uint32_t HAL_RCC_GetPCLK2Freq(void) { - 8005f50: b580 push {r7, lr} - 8005f52: b082 sub sp, #8 - 8005f54: af00 add r7, sp, #0 + 8005fec: b580 push {r7, lr} + 8005fee: b082 sub sp, #8 + 8005ff0: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_BITNUMBER]); - 8005f56: f7ff ffcd bl 8005ef4 - 8005f5a: 4601 mov r1, r0 - 8005f5c: 4b0b ldr r3, [pc, #44] @ (8005f8c ) - 8005f5e: 685b ldr r3, [r3, #4] - 8005f60: f403 5360 and.w r3, r3, #14336 @ 0x3800 - 8005f64: f44f 5260 mov.w r2, #14336 @ 0x3800 - 8005f68: 607a str r2, [r7, #4] + 8005ff2: f7ff ffcd bl 8005f90 + 8005ff6: 4601 mov r1, r0 + 8005ff8: 4b0b ldr r3, [pc, #44] @ (8006028 ) + 8005ffa: 685b ldr r3, [r3, #4] + 8005ffc: f403 5360 and.w r3, r3, #14336 @ 0x3800 + 8006000: f44f 5260 mov.w r2, #14336 @ 0x3800 + 8006004: 607a str r2, [r7, #4] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8005f6a: 687a ldr r2, [r7, #4] - 8005f6c: fa92 f2a2 rbit r2, r2 - 8005f70: 603a str r2, [r7, #0] + 8006006: 687a ldr r2, [r7, #4] + 8006008: fa92 f2a2 rbit r2, r2 + 800600c: 603a str r2, [r7, #0] return result; - 8005f72: 683a ldr r2, [r7, #0] - 8005f74: fab2 f282 clz r2, r2 - 8005f78: b2d2 uxtb r2, r2 - 8005f7a: 40d3 lsrs r3, r2 - 8005f7c: 4a04 ldr r2, [pc, #16] @ (8005f90 ) - 8005f7e: 5cd3 ldrb r3, [r2, r3] - 8005f80: fa21 f303 lsr.w r3, r1, r3 + 800600e: 683a ldr r2, [r7, #0] + 8006010: fab2 f282 clz r2, r2 + 8006014: b2d2 uxtb r2, r2 + 8006016: 40d3 lsrs r3, r2 + 8006018: 4a04 ldr r2, [pc, #16] @ (800602c ) + 800601a: 5cd3 ldrb r3, [r2, r3] + 800601c: fa21 f303 lsr.w r3, r1, r3 } - 8005f84: 4618 mov r0, r3 - 8005f86: 3708 adds r7, #8 - 8005f88: 46bd mov sp, r7 - 8005f8a: bd80 pop {r7, pc} - 8005f8c: 40021000 .word 0x40021000 - 8005f90: 080071c0 .word 0x080071c0 + 8006020: 4618 mov r0, r3 + 8006022: 3708 adds r7, #8 + 8006024: 46bd mov sp, r7 + 8006026: bd80 pop {r7, pc} + 8006028: 40021000 .word 0x40021000 + 800602c: 0800725c .word 0x0800725c -08005f94 : +08006030 : * When the TIMx clock source is PLL clock, so the TIMx clock is PLL clock x 2. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { - 8005f94: b580 push {r7, lr} - 8005f96: b092 sub sp, #72 @ 0x48 - 8005f98: af00 add r7, sp, #0 - 8005f9a: 6078 str r0, [r7, #4] + 8006030: b580 push {r7, lr} + 8006032: b092 sub sp, #72 @ 0x48 + 8006034: af00 add r7, sp, #0 + 8006036: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; - 8005f9c: 2300 movs r3, #0 - 8005f9e: 643b str r3, [r7, #64] @ 0x40 + 8006038: 2300 movs r3, #0 + 800603a: 643b str r3, [r7, #64] @ 0x40 uint32_t temp_reg = 0U; - 8005fa0: 2300 movs r3, #0 - 8005fa2: 63fb str r3, [r7, #60] @ 0x3c + 800603c: 2300 movs r3, #0 + 800603e: 63fb str r3, [r7, #60] @ 0x3c FlagStatus pwrclkchanged = RESET; - 8005fa4: 2300 movs r3, #0 - 8005fa6: f887 3047 strb.w r3, [r7, #71] @ 0x47 + 8006040: 2300 movs r3, #0 + 8006042: f887 3047 strb.w r3, [r7, #71] @ 0x47 /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); /*---------------------------- RTC configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) - 8005faa: 687b ldr r3, [r7, #4] - 8005fac: 681b ldr r3, [r3, #0] - 8005fae: f403 3380 and.w r3, r3, #65536 @ 0x10000 - 8005fb2: 2b00 cmp r3, #0 - 8005fb4: f000 80d4 beq.w 8006160 + 8006046: 687b ldr r3, [r7, #4] + 8006048: 681b ldr r3, [r3, #0] + 800604a: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 800604e: 2b00 cmp r3, #0 + 8006050: f000 80d4 beq.w 80061fc /* As soon as function is called to change RTC clock source, activation of the power domain is done. */ /* Requires to enable write access to Backup Domain of necessary */ if(__HAL_RCC_PWR_IS_CLK_DISABLED()) - 8005fb8: 4b4e ldr r3, [pc, #312] @ (80060f4 ) - 8005fba: 69db ldr r3, [r3, #28] - 8005fbc: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 - 8005fc0: 2b00 cmp r3, #0 - 8005fc2: d10e bne.n 8005fe2 + 8006054: 4b4e ldr r3, [pc, #312] @ (8006190 ) + 8006056: 69db ldr r3, [r3, #28] + 8006058: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 800605c: 2b00 cmp r3, #0 + 800605e: d10e bne.n 800607e { __HAL_RCC_PWR_CLK_ENABLE(); - 8005fc4: 4b4b ldr r3, [pc, #300] @ (80060f4 ) - 8005fc6: 69db ldr r3, [r3, #28] - 8005fc8: 4a4a ldr r2, [pc, #296] @ (80060f4 ) - 8005fca: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 - 8005fce: 61d3 str r3, [r2, #28] - 8005fd0: 4b48 ldr r3, [pc, #288] @ (80060f4 ) - 8005fd2: 69db ldr r3, [r3, #28] - 8005fd4: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 - 8005fd8: 60bb str r3, [r7, #8] - 8005fda: 68bb ldr r3, [r7, #8] + 8006060: 4b4b ldr r3, [pc, #300] @ (8006190 ) + 8006062: 69db ldr r3, [r3, #28] + 8006064: 4a4a ldr r2, [pc, #296] @ (8006190 ) + 8006066: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 800606a: 61d3 str r3, [r2, #28] + 800606c: 4b48 ldr r3, [pc, #288] @ (8006190 ) + 800606e: 69db ldr r3, [r3, #28] + 8006070: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 8006074: 60bb str r3, [r7, #8] + 8006076: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; - 8005fdc: 2301 movs r3, #1 - 8005fde: f887 3047 strb.w r3, [r7, #71] @ 0x47 + 8006078: 2301 movs r3, #1 + 800607a: f887 3047 strb.w r3, [r7, #71] @ 0x47 } if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) - 8005fe2: 4b45 ldr r3, [pc, #276] @ (80060f8 ) - 8005fe4: 681b ldr r3, [r3, #0] - 8005fe6: f403 7380 and.w r3, r3, #256 @ 0x100 - 8005fea: 2b00 cmp r3, #0 - 8005fec: d118 bne.n 8006020 + 800607e: 4b45 ldr r3, [pc, #276] @ (8006194 ) + 8006080: 681b ldr r3, [r3, #0] + 8006082: f403 7380 and.w r3, r3, #256 @ 0x100 + 8006086: 2b00 cmp r3, #0 + 8006088: d118 bne.n 80060bc { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); - 8005fee: 4b42 ldr r3, [pc, #264] @ (80060f8 ) - 8005ff0: 681b ldr r3, [r3, #0] - 8005ff2: 4a41 ldr r2, [pc, #260] @ (80060f8 ) - 8005ff4: f443 7380 orr.w r3, r3, #256 @ 0x100 - 8005ff8: 6013 str r3, [r2, #0] + 800608a: 4b42 ldr r3, [pc, #264] @ (8006194 ) + 800608c: 681b ldr r3, [r3, #0] + 800608e: 4a41 ldr r2, [pc, #260] @ (8006194 ) + 8006090: f443 7380 orr.w r3, r3, #256 @ 0x100 + 8006094: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); - 8005ffa: f7fc f935 bl 8002268 - 8005ffe: 6438 str r0, [r7, #64] @ 0x40 + 8006096: f7fc f935 bl 8002304 + 800609a: 6438 str r0, [r7, #64] @ 0x40 while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) - 8006000: e008 b.n 8006014 + 800609c: e008 b.n 80060b0 { if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) - 8006002: f7fc f931 bl 8002268 - 8006006: 4602 mov r2, r0 - 8006008: 6c3b ldr r3, [r7, #64] @ 0x40 - 800600a: 1ad3 subs r3, r2, r3 - 800600c: 2b64 cmp r3, #100 @ 0x64 - 800600e: d901 bls.n 8006014 + 800609e: f7fc f931 bl 8002304 + 80060a2: 4602 mov r2, r0 + 80060a4: 6c3b ldr r3, [r7, #64] @ 0x40 + 80060a6: 1ad3 subs r3, r2, r3 + 80060a8: 2b64 cmp r3, #100 @ 0x64 + 80060aa: d901 bls.n 80060b0 { return HAL_TIMEOUT; - 8006010: 2303 movs r3, #3 - 8006012: e14b b.n 80062ac + 80060ac: 2303 movs r3, #3 + 80060ae: e14b b.n 8006348 while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) - 8006014: 4b38 ldr r3, [pc, #224] @ (80060f8 ) - 8006016: 681b ldr r3, [r3, #0] - 8006018: f403 7380 and.w r3, r3, #256 @ 0x100 - 800601c: 2b00 cmp r3, #0 - 800601e: d0f0 beq.n 8006002 + 80060b0: 4b38 ldr r3, [pc, #224] @ (8006194 ) + 80060b2: 681b ldr r3, [r3, #0] + 80060b4: f403 7380 and.w r3, r3, #256 @ 0x100 + 80060b8: 2b00 cmp r3, #0 + 80060ba: d0f0 beq.n 800609e } } } /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL); - 8006020: 4b34 ldr r3, [pc, #208] @ (80060f4 ) - 8006022: 6a1b ldr r3, [r3, #32] - 8006024: f403 7340 and.w r3, r3, #768 @ 0x300 - 8006028: 63fb str r3, [r7, #60] @ 0x3c + 80060bc: 4b34 ldr r3, [pc, #208] @ (8006190 ) + 80060be: 6a1b ldr r3, [r3, #32] + 80060c0: f403 7340 and.w r3, r3, #768 @ 0x300 + 80060c4: 63fb str r3, [r7, #60] @ 0x3c if((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) - 800602a: 6bfb ldr r3, [r7, #60] @ 0x3c - 800602c: 2b00 cmp r3, #0 - 800602e: f000 8084 beq.w 800613a - 8006032: 687b ldr r3, [r7, #4] - 8006034: 685b ldr r3, [r3, #4] - 8006036: f403 7340 and.w r3, r3, #768 @ 0x300 - 800603a: 6bfa ldr r2, [r7, #60] @ 0x3c - 800603c: 429a cmp r2, r3 - 800603e: d07c beq.n 800613a + 80060c6: 6bfb ldr r3, [r7, #60] @ 0x3c + 80060c8: 2b00 cmp r3, #0 + 80060ca: f000 8084 beq.w 80061d6 + 80060ce: 687b ldr r3, [r7, #4] + 80060d0: 685b ldr r3, [r3, #4] + 80060d2: f403 7340 and.w r3, r3, #768 @ 0x300 + 80060d6: 6bfa ldr r2, [r7, #60] @ 0x3c + 80060d8: 429a cmp r2, r3 + 80060da: d07c beq.n 80061d6 { /* Store the content of BDCR register before the reset of Backup Domain */ temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); - 8006040: 4b2c ldr r3, [pc, #176] @ (80060f4 ) - 8006042: 6a1b ldr r3, [r3, #32] - 8006044: f423 7340 bic.w r3, r3, #768 @ 0x300 - 8006048: 63fb str r3, [r7, #60] @ 0x3c - 800604a: f44f 3380 mov.w r3, #65536 @ 0x10000 - 800604e: 633b str r3, [r7, #48] @ 0x30 + 80060dc: 4b2c ldr r3, [pc, #176] @ (8006190 ) + 80060de: 6a1b ldr r3, [r3, #32] + 80060e0: f423 7340 bic.w r3, r3, #768 @ 0x300 + 80060e4: 63fb str r3, [r7, #60] @ 0x3c + 80060e6: f44f 3380 mov.w r3, #65536 @ 0x10000 + 80060ea: 633b str r3, [r7, #48] @ 0x30 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8006050: 6b3b ldr r3, [r7, #48] @ 0x30 - 8006052: fa93 f3a3 rbit r3, r3 - 8006056: 62fb str r3, [r7, #44] @ 0x2c + 80060ec: 6b3b ldr r3, [r7, #48] @ 0x30 + 80060ee: fa93 f3a3 rbit r3, r3 + 80060f2: 62fb str r3, [r7, #44] @ 0x2c return result; - 8006058: 6afb ldr r3, [r7, #44] @ 0x2c + 80060f4: 6afb ldr r3, [r7, #44] @ 0x2c /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); - 800605a: fab3 f383 clz r3, r3 - 800605e: b2db uxtb r3, r3 - 8006060: 461a mov r2, r3 - 8006062: 4b26 ldr r3, [pc, #152] @ (80060fc ) - 8006064: 4413 add r3, r2 - 8006066: 009b lsls r3, r3, #2 - 8006068: 461a mov r2, r3 - 800606a: 2301 movs r3, #1 - 800606c: 6013 str r3, [r2, #0] - 800606e: f44f 3380 mov.w r3, #65536 @ 0x10000 - 8006072: 63bb str r3, [r7, #56] @ 0x38 + 80060f6: fab3 f383 clz r3, r3 + 80060fa: b2db uxtb r3, r3 + 80060fc: 461a mov r2, r3 + 80060fe: 4b26 ldr r3, [pc, #152] @ (8006198 ) + 8006100: 4413 add r3, r2 + 8006102: 009b lsls r3, r3, #2 + 8006104: 461a mov r2, r3 + 8006106: 2301 movs r3, #1 + 8006108: 6013 str r3, [r2, #0] + 800610a: f44f 3380 mov.w r3, #65536 @ 0x10000 + 800610e: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8006074: 6bbb ldr r3, [r7, #56] @ 0x38 - 8006076: fa93 f3a3 rbit r3, r3 - 800607a: 637b str r3, [r7, #52] @ 0x34 + 8006110: 6bbb ldr r3, [r7, #56] @ 0x38 + 8006112: fa93 f3a3 rbit r3, r3 + 8006116: 637b str r3, [r7, #52] @ 0x34 return result; - 800607c: 6b7b ldr r3, [r7, #52] @ 0x34 + 8006118: 6b7b ldr r3, [r7, #52] @ 0x34 __HAL_RCC_BACKUPRESET_RELEASE(); - 800607e: fab3 f383 clz r3, r3 - 8006082: b2db uxtb r3, r3 - 8006084: 461a mov r2, r3 - 8006086: 4b1d ldr r3, [pc, #116] @ (80060fc ) - 8006088: 4413 add r3, r2 - 800608a: 009b lsls r3, r3, #2 - 800608c: 461a mov r2, r3 - 800608e: 2300 movs r3, #0 - 8006090: 6013 str r3, [r2, #0] + 800611a: fab3 f383 clz r3, r3 + 800611e: b2db uxtb r3, r3 + 8006120: 461a mov r2, r3 + 8006122: 4b1d ldr r3, [pc, #116] @ (8006198 ) + 8006124: 4413 add r3, r2 + 8006126: 009b lsls r3, r3, #2 + 8006128: 461a mov r2, r3 + 800612a: 2300 movs r3, #0 + 800612c: 6013 str r3, [r2, #0] /* Restore the Content of BDCR register */ RCC->BDCR = temp_reg; - 8006092: 4a18 ldr r2, [pc, #96] @ (80060f4 ) - 8006094: 6bfb ldr r3, [r7, #60] @ 0x3c - 8006096: 6213 str r3, [r2, #32] + 800612e: 4a18 ldr r2, [pc, #96] @ (8006190 ) + 8006130: 6bfb ldr r3, [r7, #60] @ 0x3c + 8006132: 6213 str r3, [r2, #32] /* Wait for LSERDY if LSE was enabled */ if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON)) - 8006098: 6bfb ldr r3, [r7, #60] @ 0x3c - 800609a: f003 0301 and.w r3, r3, #1 - 800609e: 2b00 cmp r3, #0 - 80060a0: d04b beq.n 800613a + 8006134: 6bfb ldr r3, [r7, #60] @ 0x3c + 8006136: f003 0301 and.w r3, r3, #1 + 800613a: 2b00 cmp r3, #0 + 800613c: d04b beq.n 80061d6 { /* Get Start Tick */ tickstart = HAL_GetTick(); - 80060a2: f7fc f8e1 bl 8002268 - 80060a6: 6438 str r0, [r7, #64] @ 0x40 + 800613e: f7fc f8e1 bl 8002304 + 8006142: 6438 str r0, [r7, #64] @ 0x40 /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) - 80060a8: e00a b.n 80060c0 + 8006144: e00a b.n 800615c { if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) - 80060aa: f7fc f8dd bl 8002268 - 80060ae: 4602 mov r2, r0 - 80060b0: 6c3b ldr r3, [r7, #64] @ 0x40 - 80060b2: 1ad3 subs r3, r2, r3 - 80060b4: f241 3288 movw r2, #5000 @ 0x1388 - 80060b8: 4293 cmp r3, r2 - 80060ba: d901 bls.n 80060c0 + 8006146: f7fc f8dd bl 8002304 + 800614a: 4602 mov r2, r0 + 800614c: 6c3b ldr r3, [r7, #64] @ 0x40 + 800614e: 1ad3 subs r3, r2, r3 + 8006150: f241 3288 movw r2, #5000 @ 0x1388 + 8006154: 4293 cmp r3, r2 + 8006156: d901 bls.n 800615c { return HAL_TIMEOUT; - 80060bc: 2303 movs r3, #3 - 80060be: e0f5 b.n 80062ac - 80060c0: 2302 movs r3, #2 - 80060c2: 62bb str r3, [r7, #40] @ 0x28 + 8006158: 2303 movs r3, #3 + 800615a: e0f5 b.n 8006348 + 800615c: 2302 movs r3, #2 + 800615e: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 80060c4: 6abb ldr r3, [r7, #40] @ 0x28 - 80060c6: fa93 f3a3 rbit r3, r3 - 80060ca: 627b str r3, [r7, #36] @ 0x24 - 80060cc: 2302 movs r3, #2 - 80060ce: 623b str r3, [r7, #32] - 80060d0: 6a3b ldr r3, [r7, #32] - 80060d2: fa93 f3a3 rbit r3, r3 - 80060d6: 61fb str r3, [r7, #28] + 8006160: 6abb ldr r3, [r7, #40] @ 0x28 + 8006162: fa93 f3a3 rbit r3, r3 + 8006166: 627b str r3, [r7, #36] @ 0x24 + 8006168: 2302 movs r3, #2 + 800616a: 623b str r3, [r7, #32] + 800616c: 6a3b ldr r3, [r7, #32] + 800616e: fa93 f3a3 rbit r3, r3 + 8006172: 61fb str r3, [r7, #28] return result; - 80060d8: 69fb ldr r3, [r7, #28] + 8006174: 69fb ldr r3, [r7, #28] while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) - 80060da: fab3 f383 clz r3, r3 - 80060de: b2db uxtb r3, r3 - 80060e0: 095b lsrs r3, r3, #5 - 80060e2: b2db uxtb r3, r3 - 80060e4: f043 0302 orr.w r3, r3, #2 - 80060e8: b2db uxtb r3, r3 - 80060ea: 2b02 cmp r3, #2 - 80060ec: d108 bne.n 8006100 - 80060ee: 4b01 ldr r3, [pc, #4] @ (80060f4 ) - 80060f0: 6a1b ldr r3, [r3, #32] - 80060f2: e00d b.n 8006110 - 80060f4: 40021000 .word 0x40021000 - 80060f8: 40007000 .word 0x40007000 - 80060fc: 10908100 .word 0x10908100 - 8006100: 2302 movs r3, #2 - 8006102: 61bb str r3, [r7, #24] + 8006176: fab3 f383 clz r3, r3 + 800617a: b2db uxtb r3, r3 + 800617c: 095b lsrs r3, r3, #5 + 800617e: b2db uxtb r3, r3 + 8006180: f043 0302 orr.w r3, r3, #2 + 8006184: b2db uxtb r3, r3 + 8006186: 2b02 cmp r3, #2 + 8006188: d108 bne.n 800619c + 800618a: 4b01 ldr r3, [pc, #4] @ (8006190 ) + 800618c: 6a1b ldr r3, [r3, #32] + 800618e: e00d b.n 80061ac + 8006190: 40021000 .word 0x40021000 + 8006194: 40007000 .word 0x40007000 + 8006198: 10908100 .word 0x10908100 + 800619c: 2302 movs r3, #2 + 800619e: 61bb str r3, [r7, #24] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8006104: 69bb ldr r3, [r7, #24] - 8006106: fa93 f3a3 rbit r3, r3 - 800610a: 617b str r3, [r7, #20] - 800610c: 4b69 ldr r3, [pc, #420] @ (80062b4 ) - 800610e: 6a5b ldr r3, [r3, #36] @ 0x24 - 8006110: 2202 movs r2, #2 - 8006112: 613a str r2, [r7, #16] - 8006114: 693a ldr r2, [r7, #16] - 8006116: fa92 f2a2 rbit r2, r2 - 800611a: 60fa str r2, [r7, #12] + 80061a0: 69bb ldr r3, [r7, #24] + 80061a2: fa93 f3a3 rbit r3, r3 + 80061a6: 617b str r3, [r7, #20] + 80061a8: 4b69 ldr r3, [pc, #420] @ (8006350 ) + 80061aa: 6a5b ldr r3, [r3, #36] @ 0x24 + 80061ac: 2202 movs r2, #2 + 80061ae: 613a str r2, [r7, #16] + 80061b0: 693a ldr r2, [r7, #16] + 80061b2: fa92 f2a2 rbit r2, r2 + 80061b6: 60fa str r2, [r7, #12] return result; - 800611c: 68fa ldr r2, [r7, #12] - 800611e: fab2 f282 clz r2, r2 - 8006122: b2d2 uxtb r2, r2 - 8006124: f042 0240 orr.w r2, r2, #64 @ 0x40 - 8006128: b2d2 uxtb r2, r2 - 800612a: f002 021f and.w r2, r2, #31 - 800612e: 2101 movs r1, #1 - 8006130: fa01 f202 lsl.w r2, r1, r2 - 8006134: 4013 ands r3, r2 - 8006136: 2b00 cmp r3, #0 - 8006138: d0b7 beq.n 80060aa + 80061b8: 68fa ldr r2, [r7, #12] + 80061ba: fab2 f282 clz r2, r2 + 80061be: b2d2 uxtb r2, r2 + 80061c0: f042 0240 orr.w r2, r2, #64 @ 0x40 + 80061c4: b2d2 uxtb r2, r2 + 80061c6: f002 021f and.w r2, r2, #31 + 80061ca: 2101 movs r1, #1 + 80061cc: fa01 f202 lsl.w r2, r1, r2 + 80061d0: 4013 ands r3, r2 + 80061d2: 2b00 cmp r3, #0 + 80061d4: d0b7 beq.n 8006146 } } } } __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); - 800613a: 4b5e ldr r3, [pc, #376] @ (80062b4 ) - 800613c: 6a1b ldr r3, [r3, #32] - 800613e: f423 7240 bic.w r2, r3, #768 @ 0x300 - 8006142: 687b ldr r3, [r7, #4] - 8006144: 685b ldr r3, [r3, #4] - 8006146: 495b ldr r1, [pc, #364] @ (80062b4 ) - 8006148: 4313 orrs r3, r2 - 800614a: 620b str r3, [r1, #32] + 80061d6: 4b5e ldr r3, [pc, #376] @ (8006350 ) + 80061d8: 6a1b ldr r3, [r3, #32] + 80061da: f423 7240 bic.w r2, r3, #768 @ 0x300 + 80061de: 687b ldr r3, [r7, #4] + 80061e0: 685b ldr r3, [r3, #4] + 80061e2: 495b ldr r1, [pc, #364] @ (8006350 ) + 80061e4: 4313 orrs r3, r2 + 80061e6: 620b str r3, [r1, #32] /* Require to disable power clock if necessary */ if(pwrclkchanged == SET) - 800614c: f897 3047 ldrb.w r3, [r7, #71] @ 0x47 - 8006150: 2b01 cmp r3, #1 - 8006152: d105 bne.n 8006160 + 80061e8: f897 3047 ldrb.w r3, [r7, #71] @ 0x47 + 80061ec: 2b01 cmp r3, #1 + 80061ee: d105 bne.n 80061fc { __HAL_RCC_PWR_CLK_DISABLE(); - 8006154: 4b57 ldr r3, [pc, #348] @ (80062b4 ) - 8006156: 69db ldr r3, [r3, #28] - 8006158: 4a56 ldr r2, [pc, #344] @ (80062b4 ) - 800615a: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 - 800615e: 61d3 str r3, [r2, #28] + 80061f0: 4b57 ldr r3, [pc, #348] @ (8006350 ) + 80061f2: 69db ldr r3, [r3, #28] + 80061f4: 4a56 ldr r2, [pc, #344] @ (8006350 ) + 80061f6: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 + 80061fa: 61d3 str r3, [r2, #28] } } /*------------------------------- USART1 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) - 8006160: 687b ldr r3, [r7, #4] - 8006162: 681b ldr r3, [r3, #0] - 8006164: f003 0301 and.w r3, r3, #1 - 8006168: 2b00 cmp r3, #0 - 800616a: d008 beq.n 800617e + 80061fc: 687b ldr r3, [r7, #4] + 80061fe: 681b ldr r3, [r3, #0] + 8006200: f003 0301 and.w r3, r3, #1 + 8006204: 2b00 cmp r3, #0 + 8006206: d008 beq.n 800621a { /* Check the parameters */ assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); /* Configure the USART1 clock source */ __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); - 800616c: 4b51 ldr r3, [pc, #324] @ (80062b4 ) - 800616e: 6b1b ldr r3, [r3, #48] @ 0x30 - 8006170: f023 0203 bic.w r2, r3, #3 - 8006174: 687b ldr r3, [r7, #4] - 8006176: 689b ldr r3, [r3, #8] - 8006178: 494e ldr r1, [pc, #312] @ (80062b4 ) - 800617a: 4313 orrs r3, r2 - 800617c: 630b str r3, [r1, #48] @ 0x30 + 8006208: 4b51 ldr r3, [pc, #324] @ (8006350 ) + 800620a: 6b1b ldr r3, [r3, #48] @ 0x30 + 800620c: f023 0203 bic.w r2, r3, #3 + 8006210: 687b ldr r3, [r7, #4] + 8006212: 689b ldr r3, [r3, #8] + 8006214: 494e ldr r1, [pc, #312] @ (8006350 ) + 8006216: 4313 orrs r3, r2 + 8006218: 630b str r3, [r1, #48] @ 0x30 } #if defined(RCC_CFGR3_USART2SW) /*----------------------------- USART2 Configuration --------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) - 800617e: 687b ldr r3, [r7, #4] - 8006180: 681b ldr r3, [r3, #0] - 8006182: f003 0302 and.w r3, r3, #2 - 8006186: 2b00 cmp r3, #0 - 8006188: d008 beq.n 800619c + 800621a: 687b ldr r3, [r7, #4] + 800621c: 681b ldr r3, [r3, #0] + 800621e: f003 0302 and.w r3, r3, #2 + 8006222: 2b00 cmp r3, #0 + 8006224: d008 beq.n 8006238 { /* Check the parameters */ assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); /* Configure the USART2 clock source */ __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); - 800618a: 4b4a ldr r3, [pc, #296] @ (80062b4 ) - 800618c: 6b1b ldr r3, [r3, #48] @ 0x30 - 800618e: f423 3240 bic.w r2, r3, #196608 @ 0x30000 - 8006192: 687b ldr r3, [r7, #4] - 8006194: 68db ldr r3, [r3, #12] - 8006196: 4947 ldr r1, [pc, #284] @ (80062b4 ) - 8006198: 4313 orrs r3, r2 - 800619a: 630b str r3, [r1, #48] @ 0x30 + 8006226: 4b4a ldr r3, [pc, #296] @ (8006350 ) + 8006228: 6b1b ldr r3, [r3, #48] @ 0x30 + 800622a: f423 3240 bic.w r2, r3, #196608 @ 0x30000 + 800622e: 687b ldr r3, [r7, #4] + 8006230: 68db ldr r3, [r3, #12] + 8006232: 4947 ldr r1, [pc, #284] @ (8006350 ) + 8006234: 4313 orrs r3, r2 + 8006236: 630b str r3, [r1, #48] @ 0x30 } #endif /* RCC_CFGR3_USART2SW */ #if defined(RCC_CFGR3_USART3SW) /*------------------------------ USART3 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) - 800619c: 687b ldr r3, [r7, #4] - 800619e: 681b ldr r3, [r3, #0] - 80061a0: f003 0304 and.w r3, r3, #4 - 80061a4: 2b00 cmp r3, #0 - 80061a6: d008 beq.n 80061ba + 8006238: 687b ldr r3, [r7, #4] + 800623a: 681b ldr r3, [r3, #0] + 800623c: f003 0304 and.w r3, r3, #4 + 8006240: 2b00 cmp r3, #0 + 8006242: d008 beq.n 8006256 { /* Check the parameters */ assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection)); /* Configure the USART3 clock source */ __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection); - 80061a8: 4b42 ldr r3, [pc, #264] @ (80062b4 ) - 80061aa: 6b1b ldr r3, [r3, #48] @ 0x30 - 80061ac: f423 2240 bic.w r2, r3, #786432 @ 0xc0000 - 80061b0: 687b ldr r3, [r7, #4] - 80061b2: 691b ldr r3, [r3, #16] - 80061b4: 493f ldr r1, [pc, #252] @ (80062b4 ) - 80061b6: 4313 orrs r3, r2 - 80061b8: 630b str r3, [r1, #48] @ 0x30 + 8006244: 4b42 ldr r3, [pc, #264] @ (8006350 ) + 8006246: 6b1b ldr r3, [r3, #48] @ 0x30 + 8006248: f423 2240 bic.w r2, r3, #786432 @ 0xc0000 + 800624c: 687b ldr r3, [r7, #4] + 800624e: 691b ldr r3, [r3, #16] + 8006250: 493f ldr r1, [pc, #252] @ (8006350 ) + 8006252: 4313 orrs r3, r2 + 8006254: 630b str r3, [r1, #48] @ 0x30 } #endif /* RCC_CFGR3_USART3SW */ /*------------------------------ I2C1 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) - 80061ba: 687b ldr r3, [r7, #4] - 80061bc: 681b ldr r3, [r3, #0] - 80061be: f003 0320 and.w r3, r3, #32 - 80061c2: 2b00 cmp r3, #0 - 80061c4: d008 beq.n 80061d8 + 8006256: 687b ldr r3, [r7, #4] + 8006258: 681b ldr r3, [r3, #0] + 800625a: f003 0320 and.w r3, r3, #32 + 800625e: 2b00 cmp r3, #0 + 8006260: d008 beq.n 8006274 { /* Check the parameters */ assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); /* Configure the I2C1 clock source */ __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); - 80061c6: 4b3b ldr r3, [pc, #236] @ (80062b4 ) - 80061c8: 6b1b ldr r3, [r3, #48] @ 0x30 - 80061ca: f023 0210 bic.w r2, r3, #16 - 80061ce: 687b ldr r3, [r7, #4] - 80061d0: 69db ldr r3, [r3, #28] - 80061d2: 4938 ldr r1, [pc, #224] @ (80062b4 ) - 80061d4: 4313 orrs r3, r2 - 80061d6: 630b str r3, [r1, #48] @ 0x30 + 8006262: 4b3b ldr r3, [pc, #236] @ (8006350 ) + 8006264: 6b1b ldr r3, [r3, #48] @ 0x30 + 8006266: f023 0210 bic.w r2, r3, #16 + 800626a: 687b ldr r3, [r7, #4] + 800626c: 69db ldr r3, [r3, #28] + 800626e: 4938 ldr r1, [pc, #224] @ (8006350 ) + 8006270: 4313 orrs r3, r2 + 8006272: 630b str r3, [r1, #48] @ 0x30 #if defined(STM32F302xE) || defined(STM32F303xE)\ || defined(STM32F302xC) || defined(STM32F303xC)\ || defined(STM32F302x8) \ || defined(STM32F373xC) /*------------------------------ USB Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) - 80061d8: 687b ldr r3, [r7, #4] - 80061da: 681b ldr r3, [r3, #0] - 80061dc: f403 3300 and.w r3, r3, #131072 @ 0x20000 - 80061e0: 2b00 cmp r3, #0 - 80061e2: d008 beq.n 80061f6 + 8006274: 687b ldr r3, [r7, #4] + 8006276: 681b ldr r3, [r3, #0] + 8006278: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 800627c: 2b00 cmp r3, #0 + 800627e: d008 beq.n 8006292 { /* Check the parameters */ assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->USBClockSelection)); /* Configure the USB clock source */ __HAL_RCC_USB_CONFIG(PeriphClkInit->USBClockSelection); - 80061e4: 4b33 ldr r3, [pc, #204] @ (80062b4 ) - 80061e6: 685b ldr r3, [r3, #4] - 80061e8: f423 0280 bic.w r2, r3, #4194304 @ 0x400000 - 80061ec: 687b ldr r3, [r7, #4] - 80061ee: 6b1b ldr r3, [r3, #48] @ 0x30 - 80061f0: 4930 ldr r1, [pc, #192] @ (80062b4 ) - 80061f2: 4313 orrs r3, r2 - 80061f4: 604b str r3, [r1, #4] + 8006280: 4b33 ldr r3, [pc, #204] @ (8006350 ) + 8006282: 685b ldr r3, [r3, #4] + 8006284: f423 0280 bic.w r2, r3, #4194304 @ 0x400000 + 8006288: 687b ldr r3, [r7, #4] + 800628a: 6b1b ldr r3, [r3, #48] @ 0x30 + 800628c: 4930 ldr r1, [pc, #192] @ (8006350 ) + 800628e: 4313 orrs r3, r2 + 8006290: 604b str r3, [r1, #4] || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\ || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)\ || defined(STM32F373xC) || defined(STM32F378xx) /*------------------------------ I2C2 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) - 80061f6: 687b ldr r3, [r7, #4] - 80061f8: 681b ldr r3, [r3, #0] - 80061fa: f003 0340 and.w r3, r3, #64 @ 0x40 - 80061fe: 2b00 cmp r3, #0 - 8006200: d008 beq.n 8006214 + 8006292: 687b ldr r3, [r7, #4] + 8006294: 681b ldr r3, [r3, #0] + 8006296: f003 0340 and.w r3, r3, #64 @ 0x40 + 800629a: 2b00 cmp r3, #0 + 800629c: d008 beq.n 80062b0 { /* Check the parameters */ assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection)); /* Configure the I2C2 clock source */ __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection); - 8006202: 4b2c ldr r3, [pc, #176] @ (80062b4 ) - 8006204: 6b1b ldr r3, [r3, #48] @ 0x30 - 8006206: f023 0220 bic.w r2, r3, #32 - 800620a: 687b ldr r3, [r7, #4] - 800620c: 6a1b ldr r3, [r3, #32] - 800620e: 4929 ldr r1, [pc, #164] @ (80062b4 ) - 8006210: 4313 orrs r3, r2 - 8006212: 630b str r3, [r1, #48] @ 0x30 + 800629e: 4b2c ldr r3, [pc, #176] @ (8006350 ) + 80062a0: 6b1b ldr r3, [r3, #48] @ 0x30 + 80062a2: f023 0220 bic.w r2, r3, #32 + 80062a6: 687b ldr r3, [r7, #4] + 80062a8: 6a1b ldr r3, [r3, #32] + 80062aa: 4929 ldr r1, [pc, #164] @ (8006350 ) + 80062ac: 4313 orrs r3, r2 + 80062ae: 630b str r3, [r1, #48] @ 0x30 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) /*------------------------------ UART4 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) - 8006214: 687b ldr r3, [r7, #4] - 8006216: 681b ldr r3, [r3, #0] - 8006218: f003 0308 and.w r3, r3, #8 - 800621c: 2b00 cmp r3, #0 - 800621e: d008 beq.n 8006232 + 80062b0: 687b ldr r3, [r7, #4] + 80062b2: 681b ldr r3, [r3, #0] + 80062b4: f003 0308 and.w r3, r3, #8 + 80062b8: 2b00 cmp r3, #0 + 80062ba: d008 beq.n 80062ce { /* Check the parameters */ assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection)); /* Configure the UART4 clock source */ __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection); - 8006220: 4b24 ldr r3, [pc, #144] @ (80062b4 ) - 8006222: 6b1b ldr r3, [r3, #48] @ 0x30 - 8006224: f423 1240 bic.w r2, r3, #3145728 @ 0x300000 - 8006228: 687b ldr r3, [r7, #4] - 800622a: 695b ldr r3, [r3, #20] - 800622c: 4921 ldr r1, [pc, #132] @ (80062b4 ) - 800622e: 4313 orrs r3, r2 - 8006230: 630b str r3, [r1, #48] @ 0x30 + 80062bc: 4b24 ldr r3, [pc, #144] @ (8006350 ) + 80062be: 6b1b ldr r3, [r3, #48] @ 0x30 + 80062c0: f423 1240 bic.w r2, r3, #3145728 @ 0x300000 + 80062c4: 687b ldr r3, [r7, #4] + 80062c6: 695b ldr r3, [r3, #20] + 80062c8: 4921 ldr r1, [pc, #132] @ (8006350 ) + 80062ca: 4313 orrs r3, r2 + 80062cc: 630b str r3, [r1, #48] @ 0x30 } /*------------------------------ UART5 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) - 8006232: 687b ldr r3, [r7, #4] - 8006234: 681b ldr r3, [r3, #0] - 8006236: f003 0310 and.w r3, r3, #16 - 800623a: 2b00 cmp r3, #0 - 800623c: d008 beq.n 8006250 + 80062ce: 687b ldr r3, [r7, #4] + 80062d0: 681b ldr r3, [r3, #0] + 80062d2: f003 0310 and.w r3, r3, #16 + 80062d6: 2b00 cmp r3, #0 + 80062d8: d008 beq.n 80062ec { /* Check the parameters */ assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection)); /* Configure the UART5 clock source */ __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection); - 800623e: 4b1d ldr r3, [pc, #116] @ (80062b4 ) - 8006240: 6b1b ldr r3, [r3, #48] @ 0x30 - 8006242: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000 - 8006246: 687b ldr r3, [r7, #4] - 8006248: 699b ldr r3, [r3, #24] - 800624a: 491a ldr r1, [pc, #104] @ (80062b4 ) - 800624c: 4313 orrs r3, r2 - 800624e: 630b str r3, [r1, #48] @ 0x30 + 80062da: 4b1d ldr r3, [pc, #116] @ (8006350 ) + 80062dc: 6b1b ldr r3, [r3, #48] @ 0x30 + 80062de: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000 + 80062e2: 687b ldr r3, [r7, #4] + 80062e4: 699b ldr r3, [r3, #24] + 80062e6: 491a ldr r1, [pc, #104] @ (8006350 ) + 80062e8: 4313 orrs r3, r2 + 80062ea: 630b str r3, [r1, #48] @ 0x30 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\ || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) /*------------------------------ I2S Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) - 8006250: 687b ldr r3, [r7, #4] - 8006252: 681b ldr r3, [r3, #0] - 8006254: f403 7300 and.w r3, r3, #512 @ 0x200 - 8006258: 2b00 cmp r3, #0 - 800625a: d008 beq.n 800626e + 80062ec: 687b ldr r3, [r7, #4] + 80062ee: 681b ldr r3, [r3, #0] + 80062f0: f403 7300 and.w r3, r3, #512 @ 0x200 + 80062f4: 2b00 cmp r3, #0 + 80062f6: d008 beq.n 800630a { /* Check the parameters */ assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection)); /* Configure the I2S clock source */ __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection); - 800625c: 4b15 ldr r3, [pc, #84] @ (80062b4 ) - 800625e: 685b ldr r3, [r3, #4] - 8006260: f423 0200 bic.w r2, r3, #8388608 @ 0x800000 - 8006264: 687b ldr r3, [r7, #4] - 8006266: 6a9b ldr r3, [r3, #40] @ 0x28 - 8006268: 4912 ldr r1, [pc, #72] @ (80062b4 ) - 800626a: 4313 orrs r3, r2 - 800626c: 604b str r3, [r1, #4] + 80062f8: 4b15 ldr r3, [pc, #84] @ (8006350 ) + 80062fa: 685b ldr r3, [r3, #4] + 80062fc: f423 0200 bic.w r2, r3, #8388608 @ 0x800000 + 8006300: 687b ldr r3, [r7, #4] + 8006302: 6a9b ldr r3, [r3, #40] @ 0x28 + 8006304: 4912 ldr r1, [pc, #72] @ (8006350 ) + 8006306: 4313 orrs r3, r2 + 8006308: 604b str r3, [r1, #4] #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\ || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) /*------------------------------ ADC1 & ADC2 clock Configuration -------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) - 800626e: 687b ldr r3, [r7, #4] - 8006270: 681b ldr r3, [r3, #0] - 8006272: f003 0380 and.w r3, r3, #128 @ 0x80 - 8006276: 2b00 cmp r3, #0 - 8006278: d008 beq.n 800628c + 800630a: 687b ldr r3, [r7, #4] + 800630c: 681b ldr r3, [r3, #0] + 800630e: f003 0380 and.w r3, r3, #128 @ 0x80 + 8006312: 2b00 cmp r3, #0 + 8006314: d008 beq.n 8006328 { /* Check the parameters */ assert_param(IS_RCC_ADC12PLLCLK_DIV(PeriphClkInit->Adc12ClockSelection)); /* Configure the ADC12 clock source */ __HAL_RCC_ADC12_CONFIG(PeriphClkInit->Adc12ClockSelection); - 800627a: 4b0e ldr r3, [pc, #56] @ (80062b4 ) - 800627c: 6adb ldr r3, [r3, #44] @ 0x2c - 800627e: f423 72f8 bic.w r2, r3, #496 @ 0x1f0 - 8006282: 687b ldr r3, [r7, #4] - 8006284: 6a5b ldr r3, [r3, #36] @ 0x24 - 8006286: 490b ldr r1, [pc, #44] @ (80062b4 ) - 8006288: 4313 orrs r3, r2 - 800628a: 62cb str r3, [r1, #44] @ 0x2c + 8006316: 4b0e ldr r3, [pc, #56] @ (8006350 ) + 8006318: 6adb ldr r3, [r3, #44] @ 0x2c + 800631a: f423 72f8 bic.w r2, r3, #496 @ 0x1f0 + 800631e: 687b ldr r3, [r7, #4] + 8006320: 6a5b ldr r3, [r3, #36] @ 0x24 + 8006322: 490b ldr r1, [pc, #44] @ (8006350 ) + 8006324: 4313 orrs r3, r2 + 8006326: 62cb str r3, [r1, #44] @ 0x2c || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\ || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\ || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) /*------------------------------ TIM1 clock Configuration ----------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1) - 800628c: 687b ldr r3, [r7, #4] - 800628e: 681b ldr r3, [r3, #0] - 8006290: f403 5380 and.w r3, r3, #4096 @ 0x1000 - 8006294: 2b00 cmp r3, #0 - 8006296: d008 beq.n 80062aa + 8006328: 687b ldr r3, [r7, #4] + 800632a: 681b ldr r3, [r3, #0] + 800632c: f403 5380 and.w r3, r3, #4096 @ 0x1000 + 8006330: 2b00 cmp r3, #0 + 8006332: d008 beq.n 8006346 { /* Check the parameters */ assert_param(IS_RCC_TIM1CLKSOURCE(PeriphClkInit->Tim1ClockSelection)); /* Configure the TIM1 clock source */ __HAL_RCC_TIM1_CONFIG(PeriphClkInit->Tim1ClockSelection); - 8006298: 4b06 ldr r3, [pc, #24] @ (80062b4 ) - 800629a: 6b1b ldr r3, [r3, #48] @ 0x30 - 800629c: f423 7280 bic.w r2, r3, #256 @ 0x100 - 80062a0: 687b ldr r3, [r7, #4] - 80062a2: 6adb ldr r3, [r3, #44] @ 0x2c - 80062a4: 4903 ldr r1, [pc, #12] @ (80062b4 ) - 80062a6: 4313 orrs r3, r2 - 80062a8: 630b str r3, [r1, #48] @ 0x30 + 8006334: 4b06 ldr r3, [pc, #24] @ (8006350 ) + 8006336: 6b1b ldr r3, [r3, #48] @ 0x30 + 8006338: f423 7280 bic.w r2, r3, #256 @ 0x100 + 800633c: 687b ldr r3, [r7, #4] + 800633e: 6adb ldr r3, [r3, #44] @ 0x2c + 8006340: 4903 ldr r1, [pc, #12] @ (8006350 ) + 8006342: 4313 orrs r3, r2 + 8006344: 630b str r3, [r1, #48] @ 0x30 __HAL_RCC_TIM20_CONFIG(PeriphClkInit->Tim20ClockSelection); } #endif /* STM32F303xE || STM32F398xx */ return HAL_OK; - 80062aa: 2300 movs r3, #0 + 8006346: 2300 movs r3, #0 } - 80062ac: 4618 mov r0, r3 - 80062ae: 3748 adds r7, #72 @ 0x48 - 80062b0: 46bd mov sp, r7 - 80062b2: bd80 pop {r7, pc} - 80062b4: 40021000 .word 0x40021000 + 8006348: 4618 mov r0, r3 + 800634a: 3748 adds r7, #72 @ 0x48 + 800634c: 46bd mov sp, r7 + 800634e: bd80 pop {r7, pc} + 8006350: 40021000 .word 0x40021000 -080062b8 : +08006354 : * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { - 80062b8: b580 push {r7, lr} - 80062ba: b082 sub sp, #8 - 80062bc: af00 add r7, sp, #0 - 80062be: 6078 str r0, [r7, #4] + 8006354: b580 push {r7, lr} + 8006356: b082 sub sp, #8 + 8006358: af00 add r7, sp, #0 + 800635a: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) - 80062c0: 687b ldr r3, [r7, #4] - 80062c2: 2b00 cmp r3, #0 - 80062c4: d101 bne.n 80062ca + 800635c: 687b ldr r3, [r7, #4] + 800635e: 2b00 cmp r3, #0 + 8006360: d101 bne.n 8006366 { return HAL_ERROR; - 80062c6: 2301 movs r3, #1 - 80062c8: e049 b.n 800635e + 8006362: 2301 movs r3, #1 + 8006364: e049 b.n 80063fa assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) - 80062ca: 687b ldr r3, [r7, #4] - 80062cc: f893 303d ldrb.w r3, [r3, #61] @ 0x3d - 80062d0: b2db uxtb r3, r3 - 80062d2: 2b00 cmp r3, #0 - 80062d4: d106 bne.n 80062e4 + 8006366: 687b ldr r3, [r7, #4] + 8006368: f893 303d ldrb.w r3, [r3, #61] @ 0x3d + 800636c: b2db uxtb r3, r3 + 800636e: 2b00 cmp r3, #0 + 8006370: d106 bne.n 8006380 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; - 80062d6: 687b ldr r3, [r7, #4] - 80062d8: 2200 movs r2, #0 - 80062da: f883 203c strb.w r2, [r3, #60] @ 0x3c + 8006372: 687b ldr r3, [r7, #4] + 8006374: 2200 movs r2, #0 + 8006376: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Base_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspInit(htim); - 80062de: 6878 ldr r0, [r7, #4] - 80062e0: f7fb fe52 bl 8001f88 + 800637a: 6878 ldr r0, [r7, #4] + 800637c: f7fb fe52 bl 8002024 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_BUSY; - 80062e4: 687b ldr r3, [r7, #4] - 80062e6: 2202 movs r2, #2 - 80062e8: f883 203d strb.w r2, [r3, #61] @ 0x3d - - /* Set the Time Base configuration */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - 80062ec: 687b ldr r3, [r7, #4] - 80062ee: 681a ldr r2, [r3, #0] - 80062f0: 687b ldr r3, [r7, #4] - 80062f2: 3304 adds r3, #4 - 80062f4: 4619 mov r1, r3 - 80062f6: 4610 mov r0, r2 - 80062f8: f000 f9c4 bl 8006684 - - /* Initialize the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_READY; - 80062fc: 687b ldr r3, [r7, #4] - 80062fe: 2201 movs r2, #1 - 8006300: f883 2048 strb.w r2, [r3, #72] @ 0x48 - - /* Initialize the TIM channels state */ - TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); - 8006304: 687b ldr r3, [r7, #4] - 8006306: 2201 movs r2, #1 - 8006308: f883 203e strb.w r2, [r3, #62] @ 0x3e - 800630c: 687b ldr r3, [r7, #4] - 800630e: 2201 movs r2, #1 - 8006310: f883 203f strb.w r2, [r3, #63] @ 0x3f - 8006314: 687b ldr r3, [r7, #4] - 8006316: 2201 movs r2, #1 - 8006318: f883 2040 strb.w r2, [r3, #64] @ 0x40 - 800631c: 687b ldr r3, [r7, #4] - 800631e: 2201 movs r2, #1 - 8006320: f883 2041 strb.w r2, [r3, #65] @ 0x41 - 8006324: 687b ldr r3, [r7, #4] - 8006326: 2201 movs r2, #1 - 8006328: f883 2042 strb.w r2, [r3, #66] @ 0x42 - 800632c: 687b ldr r3, [r7, #4] - 800632e: 2201 movs r2, #1 - 8006330: f883 2043 strb.w r2, [r3, #67] @ 0x43 - TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); - 8006334: 687b ldr r3, [r7, #4] - 8006336: 2201 movs r2, #1 - 8006338: f883 2044 strb.w r2, [r3, #68] @ 0x44 - 800633c: 687b ldr r3, [r7, #4] - 800633e: 2201 movs r2, #1 - 8006340: f883 2045 strb.w r2, [r3, #69] @ 0x45 - 8006344: 687b ldr r3, [r7, #4] - 8006346: 2201 movs r2, #1 - 8006348: f883 2046 strb.w r2, [r3, #70] @ 0x46 - 800634c: 687b ldr r3, [r7, #4] - 800634e: 2201 movs r2, #1 - 8006350: f883 2047 strb.w r2, [r3, #71] @ 0x47 - - /* Initialize the TIM state*/ - htim->State = HAL_TIM_STATE_READY; - 8006354: 687b ldr r3, [r7, #4] - 8006356: 2201 movs r2, #1 - 8006358: f883 203d strb.w r2, [r3, #61] @ 0x3d - - return HAL_OK; - 800635c: 2300 movs r3, #0 -} - 800635e: 4618 mov r0, r3 - 8006360: 3708 adds r7, #8 - 8006362: 46bd mov sp, r7 - 8006364: bd80 pop {r7, pc} - ... - -08006368 : - * @brief Starts the TIM Base generation. - * @param htim TIM Base handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) -{ - 8006368: b480 push {r7} - 800636a: b085 sub sp, #20 - 800636c: af00 add r7, sp, #0 - 800636e: 6078 str r0, [r7, #4] - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - /* Check the TIM state */ - if (htim->State != HAL_TIM_STATE_READY) - 8006370: 687b ldr r3, [r7, #4] - 8006372: f893 303d ldrb.w r3, [r3, #61] @ 0x3d - 8006376: b2db uxtb r3, r3 - 8006378: 2b01 cmp r3, #1 - 800637a: d001 beq.n 8006380 - { - return HAL_ERROR; - 800637c: 2301 movs r3, #1 - 800637e: e03d b.n 80063fc - } - /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8006380: 687b ldr r3, [r7, #4] 8006382: 2202 movs r2, #2 8006384: f883 203d strb.w r2, [r3, #61] @ 0x3d + /* Set the Time Base configuration */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + 8006388: 687b ldr r3, [r7, #4] + 800638a: 681a ldr r2, [r3, #0] + 800638c: 687b ldr r3, [r7, #4] + 800638e: 3304 adds r3, #4 + 8006390: 4619 mov r1, r3 + 8006392: 4610 mov r0, r2 + 8006394: f000 f9c4 bl 8006720 + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + 8006398: 687b ldr r3, [r7, #4] + 800639a: 2201 movs r2, #1 + 800639c: f883 2048 strb.w r2, [r3, #72] @ 0x48 + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + 80063a0: 687b ldr r3, [r7, #4] + 80063a2: 2201 movs r2, #1 + 80063a4: f883 203e strb.w r2, [r3, #62] @ 0x3e + 80063a8: 687b ldr r3, [r7, #4] + 80063aa: 2201 movs r2, #1 + 80063ac: f883 203f strb.w r2, [r3, #63] @ 0x3f + 80063b0: 687b ldr r3, [r7, #4] + 80063b2: 2201 movs r2, #1 + 80063b4: f883 2040 strb.w r2, [r3, #64] @ 0x40 + 80063b8: 687b ldr r3, [r7, #4] + 80063ba: 2201 movs r2, #1 + 80063bc: f883 2041 strb.w r2, [r3, #65] @ 0x41 + 80063c0: 687b ldr r3, [r7, #4] + 80063c2: 2201 movs r2, #1 + 80063c4: f883 2042 strb.w r2, [r3, #66] @ 0x42 + 80063c8: 687b ldr r3, [r7, #4] + 80063ca: 2201 movs r2, #1 + 80063cc: f883 2043 strb.w r2, [r3, #67] @ 0x43 + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + 80063d0: 687b ldr r3, [r7, #4] + 80063d2: 2201 movs r2, #1 + 80063d4: f883 2044 strb.w r2, [r3, #68] @ 0x44 + 80063d8: 687b ldr r3, [r7, #4] + 80063da: 2201 movs r2, #1 + 80063dc: f883 2045 strb.w r2, [r3, #69] @ 0x45 + 80063e0: 687b ldr r3, [r7, #4] + 80063e2: 2201 movs r2, #1 + 80063e4: f883 2046 strb.w r2, [r3, #70] @ 0x46 + 80063e8: 687b ldr r3, [r7, #4] + 80063ea: 2201 movs r2, #1 + 80063ec: f883 2047 strb.w r2, [r3, #71] @ 0x47 + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + 80063f0: 687b ldr r3, [r7, #4] + 80063f2: 2201 movs r2, #1 + 80063f4: f883 203d strb.w r2, [r3, #61] @ 0x3d + + return HAL_OK; + 80063f8: 2300 movs r3, #0 +} + 80063fa: 4618 mov r0, r3 + 80063fc: 3708 adds r7, #8 + 80063fe: 46bd mov sp, r7 + 8006400: bd80 pop {r7, pc} + ... + +08006404 : + * @brief Starts the TIM Base generation. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) +{ + 8006404: b480 push {r7} + 8006406: b085 sub sp, #20 + 8006408: af00 add r7, sp, #0 + 800640a: 6078 str r0, [r7, #4] + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Check the TIM state */ + if (htim->State != HAL_TIM_STATE_READY) + 800640c: 687b ldr r3, [r7, #4] + 800640e: f893 303d ldrb.w r3, [r3, #61] @ 0x3d + 8006412: b2db uxtb r3, r3 + 8006414: 2b01 cmp r3, #1 + 8006416: d001 beq.n 800641c + { + return HAL_ERROR; + 8006418: 2301 movs r3, #1 + 800641a: e03d b.n 8006498 + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + 800641c: 687b ldr r3, [r7, #4] + 800641e: 2202 movs r2, #2 + 8006420: f883 203d strb.w r2, [r3, #61] @ 0x3d + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - 8006388: 687b ldr r3, [r7, #4] - 800638a: 681b ldr r3, [r3, #0] - 800638c: 4a1e ldr r2, [pc, #120] @ (8006408 ) - 800638e: 4293 cmp r3, r2 - 8006390: d013 beq.n 80063ba - 8006392: 687b ldr r3, [r7, #4] - 8006394: 681b ldr r3, [r3, #0] - 8006396: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 - 800639a: d00e beq.n 80063ba - 800639c: 687b ldr r3, [r7, #4] - 800639e: 681b ldr r3, [r3, #0] - 80063a0: 4a1a ldr r2, [pc, #104] @ (800640c ) - 80063a2: 4293 cmp r3, r2 - 80063a4: d009 beq.n 80063ba - 80063a6: 687b ldr r3, [r7, #4] - 80063a8: 681b ldr r3, [r3, #0] - 80063aa: 4a19 ldr r2, [pc, #100] @ (8006410 ) - 80063ac: 4293 cmp r3, r2 - 80063ae: d004 beq.n 80063ba - 80063b0: 687b ldr r3, [r7, #4] - 80063b2: 681b ldr r3, [r3, #0] - 80063b4: 4a17 ldr r2, [pc, #92] @ (8006414 ) - 80063b6: 4293 cmp r3, r2 - 80063b8: d115 bne.n 80063e6 + 8006424: 687b ldr r3, [r7, #4] + 8006426: 681b ldr r3, [r3, #0] + 8006428: 4a1e ldr r2, [pc, #120] @ (80064a4 ) + 800642a: 4293 cmp r3, r2 + 800642c: d013 beq.n 8006456 + 800642e: 687b ldr r3, [r7, #4] + 8006430: 681b ldr r3, [r3, #0] + 8006432: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 8006436: d00e beq.n 8006456 + 8006438: 687b ldr r3, [r7, #4] + 800643a: 681b ldr r3, [r3, #0] + 800643c: 4a1a ldr r2, [pc, #104] @ (80064a8 ) + 800643e: 4293 cmp r3, r2 + 8006440: d009 beq.n 8006456 + 8006442: 687b ldr r3, [r7, #4] + 8006444: 681b ldr r3, [r3, #0] + 8006446: 4a19 ldr r2, [pc, #100] @ (80064ac ) + 8006448: 4293 cmp r3, r2 + 800644a: d004 beq.n 8006456 + 800644c: 687b ldr r3, [r7, #4] + 800644e: 681b ldr r3, [r3, #0] + 8006450: 4a17 ldr r2, [pc, #92] @ (80064b0 ) + 8006452: 4293 cmp r3, r2 + 8006454: d115 bne.n 8006482 { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - 80063ba: 687b ldr r3, [r7, #4] - 80063bc: 681b ldr r3, [r3, #0] - 80063be: 689a ldr r2, [r3, #8] - 80063c0: 4b15 ldr r3, [pc, #84] @ (8006418 ) - 80063c2: 4013 ands r3, r2 - 80063c4: 60fb str r3, [r7, #12] + 8006456: 687b ldr r3, [r7, #4] + 8006458: 681b ldr r3, [r3, #0] + 800645a: 689a ldr r2, [r3, #8] + 800645c: 4b15 ldr r3, [pc, #84] @ (80064b4 ) + 800645e: 4013 ands r3, r2 + 8006460: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - 80063c6: 68fb ldr r3, [r7, #12] - 80063c8: 2b06 cmp r3, #6 - 80063ca: d015 beq.n 80063f8 - 80063cc: 68fb ldr r3, [r7, #12] - 80063ce: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 - 80063d2: d011 beq.n 80063f8 + 8006462: 68fb ldr r3, [r7, #12] + 8006464: 2b06 cmp r3, #6 + 8006466: d015 beq.n 8006494 + 8006468: 68fb ldr r3, [r7, #12] + 800646a: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 + 800646e: d011 beq.n 8006494 { __HAL_TIM_ENABLE(htim); - 80063d4: 687b ldr r3, [r7, #4] - 80063d6: 681b ldr r3, [r3, #0] - 80063d8: 681a ldr r2, [r3, #0] - 80063da: 687b ldr r3, [r7, #4] - 80063dc: 681b ldr r3, [r3, #0] - 80063de: f042 0201 orr.w r2, r2, #1 - 80063e2: 601a str r2, [r3, #0] + 8006470: 687b ldr r3, [r7, #4] + 8006472: 681b ldr r3, [r3, #0] + 8006474: 681a ldr r2, [r3, #0] + 8006476: 687b ldr r3, [r7, #4] + 8006478: 681b ldr r3, [r3, #0] + 800647a: f042 0201 orr.w r2, r2, #1 + 800647e: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - 80063e4: e008 b.n 80063f8 + 8006480: e008 b.n 8006494 } } else { __HAL_TIM_ENABLE(htim); - 80063e6: 687b ldr r3, [r7, #4] - 80063e8: 681b ldr r3, [r3, #0] - 80063ea: 681a ldr r2, [r3, #0] - 80063ec: 687b ldr r3, [r7, #4] - 80063ee: 681b ldr r3, [r3, #0] - 80063f0: f042 0201 orr.w r2, r2, #1 - 80063f4: 601a str r2, [r3, #0] - 80063f6: e000 b.n 80063fa + 8006482: 687b ldr r3, [r7, #4] + 8006484: 681b ldr r3, [r3, #0] + 8006486: 681a ldr r2, [r3, #0] + 8006488: 687b ldr r3, [r7, #4] + 800648a: 681b ldr r3, [r3, #0] + 800648c: f042 0201 orr.w r2, r2, #1 + 8006490: 601a str r2, [r3, #0] + 8006492: e000 b.n 8006496 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - 80063f8: bf00 nop + 8006494: bf00 nop } /* Return function status */ return HAL_OK; - 80063fa: 2300 movs r3, #0 + 8006496: 2300 movs r3, #0 } - 80063fc: 4618 mov r0, r3 - 80063fe: 3714 adds r7, #20 - 8006400: 46bd mov sp, r7 - 8006402: f85d 7b04 ldr.w r7, [sp], #4 - 8006406: 4770 bx lr - 8006408: 40012c00 .word 0x40012c00 - 800640c: 40000400 .word 0x40000400 - 8006410: 40000800 .word 0x40000800 - 8006414: 40014000 .word 0x40014000 - 8006418: 00010007 .word 0x00010007 + 8006498: 4618 mov r0, r3 + 800649a: 3714 adds r7, #20 + 800649c: 46bd mov sp, r7 + 800649e: f85d 7b04 ldr.w r7, [sp], #4 + 80064a2: 4770 bx lr + 80064a4: 40012c00 .word 0x40012c00 + 80064a8: 40000400 .word 0x40000400 + 80064ac: 40000800 .word 0x40000800 + 80064b0: 40014000 .word 0x40014000 + 80064b4: 00010007 .word 0x00010007 -0800641c : +080064b8 : * @brief This function handles TIM interrupts requests. * @param htim TIM handle * @retval None */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { - 800641c: b580 push {r7, lr} - 800641e: b084 sub sp, #16 - 8006420: af00 add r7, sp, #0 - 8006422: 6078 str r0, [r7, #4] + 80064b8: b580 push {r7, lr} + 80064ba: b084 sub sp, #16 + 80064bc: af00 add r7, sp, #0 + 80064be: 6078 str r0, [r7, #4] uint32_t itsource = htim->Instance->DIER; - 8006424: 687b ldr r3, [r7, #4] - 8006426: 681b ldr r3, [r3, #0] - 8006428: 68db ldr r3, [r3, #12] - 800642a: 60fb str r3, [r7, #12] + 80064c0: 687b ldr r3, [r7, #4] + 80064c2: 681b ldr r3, [r3, #0] + 80064c4: 68db ldr r3, [r3, #12] + 80064c6: 60fb str r3, [r7, #12] uint32_t itflag = htim->Instance->SR; - 800642c: 687b ldr r3, [r7, #4] - 800642e: 681b ldr r3, [r3, #0] - 8006430: 691b ldr r3, [r3, #16] - 8006432: 60bb str r3, [r7, #8] + 80064c8: 687b ldr r3, [r7, #4] + 80064ca: 681b ldr r3, [r3, #0] + 80064cc: 691b ldr r3, [r3, #16] + 80064ce: 60bb str r3, [r7, #8] /* Capture compare 1 event */ if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1)) - 8006434: 68bb ldr r3, [r7, #8] - 8006436: f003 0302 and.w r3, r3, #2 - 800643a: 2b00 cmp r3, #0 - 800643c: d020 beq.n 8006480 + 80064d0: 68bb ldr r3, [r7, #8] + 80064d2: f003 0302 and.w r3, r3, #2 + 80064d6: 2b00 cmp r3, #0 + 80064d8: d020 beq.n 800651c { if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1)) - 800643e: 68fb ldr r3, [r7, #12] - 8006440: f003 0302 and.w r3, r3, #2 - 8006444: 2b00 cmp r3, #0 - 8006446: d01b beq.n 8006480 + 80064da: 68fb ldr r3, [r7, #12] + 80064dc: f003 0302 and.w r3, r3, #2 + 80064e0: 2b00 cmp r3, #0 + 80064e2: d01b beq.n 800651c { { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1); - 8006448: 687b ldr r3, [r7, #4] - 800644a: 681b ldr r3, [r3, #0] - 800644c: f06f 0202 mvn.w r2, #2 - 8006450: 611a str r2, [r3, #16] + 80064e4: 687b ldr r3, [r7, #4] + 80064e6: 681b ldr r3, [r3, #0] + 80064e8: f06f 0202 mvn.w r2, #2 + 80064ec: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - 8006452: 687b ldr r3, [r7, #4] - 8006454: 2201 movs r2, #1 - 8006456: 771a strb r2, [r3, #28] + 80064ee: 687b ldr r3, [r7, #4] + 80064f0: 2201 movs r2, #1 + 80064f2: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) - 8006458: 687b ldr r3, [r7, #4] - 800645a: 681b ldr r3, [r3, #0] - 800645c: 699b ldr r3, [r3, #24] - 800645e: f003 0303 and.w r3, r3, #3 - 8006462: 2b00 cmp r3, #0 - 8006464: d003 beq.n 800646e + 80064f4: 687b ldr r3, [r7, #4] + 80064f6: 681b ldr r3, [r3, #0] + 80064f8: 699b ldr r3, [r3, #24] + 80064fa: f003 0303 and.w r3, r3, #3 + 80064fe: 2b00 cmp r3, #0 + 8006500: d003 beq.n 800650a { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); - 8006466: 6878 ldr r0, [r7, #4] - 8006468: f000 f8ee bl 8006648 - 800646c: e005 b.n 800647a + 8006502: 6878 ldr r0, [r7, #4] + 8006504: f000 f8ee bl 80066e4 + 8006508: e005 b.n 8006516 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); - 800646e: 6878 ldr r0, [r7, #4] - 8006470: f000 f8e0 bl 8006634 + 800650a: 6878 ldr r0, [r7, #4] + 800650c: f000 f8e0 bl 80066d0 HAL_TIM_PWM_PulseFinishedCallback(htim); - 8006474: 6878 ldr r0, [r7, #4] - 8006476: f000 f8f1 bl 800665c + 8006510: 6878 ldr r0, [r7, #4] + 8006512: f000 f8f1 bl 80066f8 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - 800647a: 687b ldr r3, [r7, #4] - 800647c: 2200 movs r2, #0 - 800647e: 771a strb r2, [r3, #28] + 8006516: 687b ldr r3, [r7, #4] + 8006518: 2200 movs r2, #0 + 800651a: 771a strb r2, [r3, #28] } } } /* Capture compare 2 event */ if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2)) - 8006480: 68bb ldr r3, [r7, #8] - 8006482: f003 0304 and.w r3, r3, #4 - 8006486: 2b00 cmp r3, #0 - 8006488: d020 beq.n 80064cc + 800651c: 68bb ldr r3, [r7, #8] + 800651e: f003 0304 and.w r3, r3, #4 + 8006522: 2b00 cmp r3, #0 + 8006524: d020 beq.n 8006568 { if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2)) - 800648a: 68fb ldr r3, [r7, #12] - 800648c: f003 0304 and.w r3, r3, #4 - 8006490: 2b00 cmp r3, #0 - 8006492: d01b beq.n 80064cc + 8006526: 68fb ldr r3, [r7, #12] + 8006528: f003 0304 and.w r3, r3, #4 + 800652c: 2b00 cmp r3, #0 + 800652e: d01b beq.n 8006568 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2); - 8006494: 687b ldr r3, [r7, #4] - 8006496: 681b ldr r3, [r3, #0] - 8006498: f06f 0204 mvn.w r2, #4 - 800649c: 611a str r2, [r3, #16] + 8006530: 687b ldr r3, [r7, #4] + 8006532: 681b ldr r3, [r3, #0] + 8006534: f06f 0204 mvn.w r2, #4 + 8006538: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - 800649e: 687b ldr r3, [r7, #4] - 80064a0: 2202 movs r2, #2 - 80064a2: 771a strb r2, [r3, #28] + 800653a: 687b ldr r3, [r7, #4] + 800653c: 2202 movs r2, #2 + 800653e: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) - 80064a4: 687b ldr r3, [r7, #4] - 80064a6: 681b ldr r3, [r3, #0] - 80064a8: 699b ldr r3, [r3, #24] - 80064aa: f403 7340 and.w r3, r3, #768 @ 0x300 - 80064ae: 2b00 cmp r3, #0 - 80064b0: d003 beq.n 80064ba + 8006540: 687b ldr r3, [r7, #4] + 8006542: 681b ldr r3, [r3, #0] + 8006544: 699b ldr r3, [r3, #24] + 8006546: f403 7340 and.w r3, r3, #768 @ 0x300 + 800654a: 2b00 cmp r3, #0 + 800654c: d003 beq.n 8006556 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); - 80064b2: 6878 ldr r0, [r7, #4] - 80064b4: f000 f8c8 bl 8006648 - 80064b8: e005 b.n 80064c6 + 800654e: 6878 ldr r0, [r7, #4] + 8006550: f000 f8c8 bl 80066e4 + 8006554: e005 b.n 8006562 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); - 80064ba: 6878 ldr r0, [r7, #4] - 80064bc: f000 f8ba bl 8006634 + 8006556: 6878 ldr r0, [r7, #4] + 8006558: f000 f8ba bl 80066d0 HAL_TIM_PWM_PulseFinishedCallback(htim); - 80064c0: 6878 ldr r0, [r7, #4] - 80064c2: f000 f8cb bl 800665c + 800655c: 6878 ldr r0, [r7, #4] + 800655e: f000 f8cb bl 80066f8 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - 80064c6: 687b ldr r3, [r7, #4] - 80064c8: 2200 movs r2, #0 - 80064ca: 771a strb r2, [r3, #28] + 8006562: 687b ldr r3, [r7, #4] + 8006564: 2200 movs r2, #0 + 8006566: 771a strb r2, [r3, #28] } } /* Capture compare 3 event */ if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3)) - 80064cc: 68bb ldr r3, [r7, #8] - 80064ce: f003 0308 and.w r3, r3, #8 - 80064d2: 2b00 cmp r3, #0 - 80064d4: d020 beq.n 8006518 + 8006568: 68bb ldr r3, [r7, #8] + 800656a: f003 0308 and.w r3, r3, #8 + 800656e: 2b00 cmp r3, #0 + 8006570: d020 beq.n 80065b4 { if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3)) - 80064d6: 68fb ldr r3, [r7, #12] - 80064d8: f003 0308 and.w r3, r3, #8 - 80064dc: 2b00 cmp r3, #0 - 80064de: d01b beq.n 8006518 + 8006572: 68fb ldr r3, [r7, #12] + 8006574: f003 0308 and.w r3, r3, #8 + 8006578: 2b00 cmp r3, #0 + 800657a: d01b beq.n 80065b4 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3); - 80064e0: 687b ldr r3, [r7, #4] - 80064e2: 681b ldr r3, [r3, #0] - 80064e4: f06f 0208 mvn.w r2, #8 - 80064e8: 611a str r2, [r3, #16] + 800657c: 687b ldr r3, [r7, #4] + 800657e: 681b ldr r3, [r3, #0] + 8006580: f06f 0208 mvn.w r2, #8 + 8006584: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - 80064ea: 687b ldr r3, [r7, #4] - 80064ec: 2204 movs r2, #4 - 80064ee: 771a strb r2, [r3, #28] + 8006586: 687b ldr r3, [r7, #4] + 8006588: 2204 movs r2, #4 + 800658a: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) - 80064f0: 687b ldr r3, [r7, #4] - 80064f2: 681b ldr r3, [r3, #0] - 80064f4: 69db ldr r3, [r3, #28] - 80064f6: f003 0303 and.w r3, r3, #3 - 80064fa: 2b00 cmp r3, #0 - 80064fc: d003 beq.n 8006506 + 800658c: 687b ldr r3, [r7, #4] + 800658e: 681b ldr r3, [r3, #0] + 8006590: 69db ldr r3, [r3, #28] + 8006592: f003 0303 and.w r3, r3, #3 + 8006596: 2b00 cmp r3, #0 + 8006598: d003 beq.n 80065a2 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); - 80064fe: 6878 ldr r0, [r7, #4] - 8006500: f000 f8a2 bl 8006648 - 8006504: e005 b.n 8006512 + 800659a: 6878 ldr r0, [r7, #4] + 800659c: f000 f8a2 bl 80066e4 + 80065a0: e005 b.n 80065ae { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); - 8006506: 6878 ldr r0, [r7, #4] - 8006508: f000 f894 bl 8006634 + 80065a2: 6878 ldr r0, [r7, #4] + 80065a4: f000 f894 bl 80066d0 HAL_TIM_PWM_PulseFinishedCallback(htim); - 800650c: 6878 ldr r0, [r7, #4] - 800650e: f000 f8a5 bl 800665c + 80065a8: 6878 ldr r0, [r7, #4] + 80065aa: f000 f8a5 bl 80066f8 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - 8006512: 687b ldr r3, [r7, #4] - 8006514: 2200 movs r2, #0 - 8006516: 771a strb r2, [r3, #28] + 80065ae: 687b ldr r3, [r7, #4] + 80065b0: 2200 movs r2, #0 + 80065b2: 771a strb r2, [r3, #28] } } /* Capture compare 4 event */ if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4)) - 8006518: 68bb ldr r3, [r7, #8] - 800651a: f003 0310 and.w r3, r3, #16 - 800651e: 2b00 cmp r3, #0 - 8006520: d020 beq.n 8006564 + 80065b4: 68bb ldr r3, [r7, #8] + 80065b6: f003 0310 and.w r3, r3, #16 + 80065ba: 2b00 cmp r3, #0 + 80065bc: d020 beq.n 8006600 { if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4)) - 8006522: 68fb ldr r3, [r7, #12] - 8006524: f003 0310 and.w r3, r3, #16 - 8006528: 2b00 cmp r3, #0 - 800652a: d01b beq.n 8006564 + 80065be: 68fb ldr r3, [r7, #12] + 80065c0: f003 0310 and.w r3, r3, #16 + 80065c4: 2b00 cmp r3, #0 + 80065c6: d01b beq.n 8006600 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4); - 800652c: 687b ldr r3, [r7, #4] - 800652e: 681b ldr r3, [r3, #0] - 8006530: f06f 0210 mvn.w r2, #16 - 8006534: 611a str r2, [r3, #16] + 80065c8: 687b ldr r3, [r7, #4] + 80065ca: 681b ldr r3, [r3, #0] + 80065cc: f06f 0210 mvn.w r2, #16 + 80065d0: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - 8006536: 687b ldr r3, [r7, #4] - 8006538: 2208 movs r2, #8 - 800653a: 771a strb r2, [r3, #28] + 80065d2: 687b ldr r3, [r7, #4] + 80065d4: 2208 movs r2, #8 + 80065d6: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) - 800653c: 687b ldr r3, [r7, #4] - 800653e: 681b ldr r3, [r3, #0] - 8006540: 69db ldr r3, [r3, #28] - 8006542: f403 7340 and.w r3, r3, #768 @ 0x300 - 8006546: 2b00 cmp r3, #0 - 8006548: d003 beq.n 8006552 + 80065d8: 687b ldr r3, [r7, #4] + 80065da: 681b ldr r3, [r3, #0] + 80065dc: 69db ldr r3, [r3, #28] + 80065de: f403 7340 and.w r3, r3, #768 @ 0x300 + 80065e2: 2b00 cmp r3, #0 + 80065e4: d003 beq.n 80065ee { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); - 800654a: 6878 ldr r0, [r7, #4] - 800654c: f000 f87c bl 8006648 - 8006550: e005 b.n 800655e + 80065e6: 6878 ldr r0, [r7, #4] + 80065e8: f000 f87c bl 80066e4 + 80065ec: e005 b.n 80065fa { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); - 8006552: 6878 ldr r0, [r7, #4] - 8006554: f000 f86e bl 8006634 + 80065ee: 6878 ldr r0, [r7, #4] + 80065f0: f000 f86e bl 80066d0 HAL_TIM_PWM_PulseFinishedCallback(htim); - 8006558: 6878 ldr r0, [r7, #4] - 800655a: f000 f87f bl 800665c + 80065f4: 6878 ldr r0, [r7, #4] + 80065f6: f000 f87f bl 80066f8 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - 800655e: 687b ldr r3, [r7, #4] - 8006560: 2200 movs r2, #0 - 8006562: 771a strb r2, [r3, #28] + 80065fa: 687b ldr r3, [r7, #4] + 80065fc: 2200 movs r2, #0 + 80065fe: 771a strb r2, [r3, #28] } } /* TIM Update event */ if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE)) - 8006564: 68bb ldr r3, [r7, #8] - 8006566: f003 0301 and.w r3, r3, #1 - 800656a: 2b00 cmp r3, #0 - 800656c: d00c beq.n 8006588 + 8006600: 68bb ldr r3, [r7, #8] + 8006602: f003 0301 and.w r3, r3, #1 + 8006606: 2b00 cmp r3, #0 + 8006608: d00c beq.n 8006624 { if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE)) - 800656e: 68fb ldr r3, [r7, #12] - 8006570: f003 0301 and.w r3, r3, #1 - 8006574: 2b00 cmp r3, #0 - 8006576: d007 beq.n 8006588 + 800660a: 68fb ldr r3, [r7, #12] + 800660c: f003 0301 and.w r3, r3, #1 + 8006610: 2b00 cmp r3, #0 + 8006612: d007 beq.n 8006624 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE); - 8006578: 687b ldr r3, [r7, #4] - 800657a: 681b ldr r3, [r3, #0] - 800657c: f06f 0201 mvn.w r2, #1 - 8006580: 611a str r2, [r3, #16] + 8006614: 687b ldr r3, [r7, #4] + 8006616: 681b ldr r3, [r3, #0] + 8006618: f06f 0201 mvn.w r2, #1 + 800661c: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else HAL_TIM_PeriodElapsedCallback(htim); - 8006582: 6878 ldr r0, [r7, #4] - 8006584: f000 f84c bl 8006620 + 800661e: 6878 ldr r0, [r7, #4] + 8006620: f000 f84c bl 80066bc #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break input event */ if ((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) - 8006588: 68bb ldr r3, [r7, #8] - 800658a: f003 0380 and.w r3, r3, #128 @ 0x80 - 800658e: 2b00 cmp r3, #0 - 8006590: d00c beq.n 80065ac + 8006624: 68bb ldr r3, [r7, #8] + 8006626: f003 0380 and.w r3, r3, #128 @ 0x80 + 800662a: 2b00 cmp r3, #0 + 800662c: d00c beq.n 8006648 { if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) - 8006592: 68fb ldr r3, [r7, #12] - 8006594: f003 0380 and.w r3, r3, #128 @ 0x80 - 8006598: 2b00 cmp r3, #0 - 800659a: d007 beq.n 80065ac + 800662e: 68fb ldr r3, [r7, #12] + 8006630: f003 0380 and.w r3, r3, #128 @ 0x80 + 8006634: 2b00 cmp r3, #0 + 8006636: d007 beq.n 8006648 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK); - 800659c: 687b ldr r3, [r7, #4] - 800659e: 681b ldr r3, [r3, #0] - 80065a0: f06f 0280 mvn.w r2, #128 @ 0x80 - 80065a4: 611a str r2, [r3, #16] + 8006638: 687b ldr r3, [r7, #4] + 800663a: 681b ldr r3, [r3, #0] + 800663c: f06f 0280 mvn.w r2, #128 @ 0x80 + 8006640: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->BreakCallback(htim); #else HAL_TIMEx_BreakCallback(htim); - 80065a6: 6878 ldr r0, [r7, #4] - 80065a8: f000 f978 bl 800689c + 8006642: 6878 ldr r0, [r7, #4] + 8006644: f000 f978 bl 8006938 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } #if defined(TIM_BDTR_BK2E) /* TIM Break2 input event */ if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2)) - 80065ac: 68bb ldr r3, [r7, #8] - 80065ae: f403 7380 and.w r3, r3, #256 @ 0x100 - 80065b2: 2b00 cmp r3, #0 - 80065b4: d00c beq.n 80065d0 + 8006648: 68bb ldr r3, [r7, #8] + 800664a: f403 7380 and.w r3, r3, #256 @ 0x100 + 800664e: 2b00 cmp r3, #0 + 8006650: d00c beq.n 800666c { if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) - 80065b6: 68fb ldr r3, [r7, #12] - 80065b8: f003 0380 and.w r3, r3, #128 @ 0x80 - 80065bc: 2b00 cmp r3, #0 - 80065be: d007 beq.n 80065d0 + 8006652: 68fb ldr r3, [r7, #12] + 8006654: f003 0380 and.w r3, r3, #128 @ 0x80 + 8006658: 2b00 cmp r3, #0 + 800665a: d007 beq.n 800666c { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2); - 80065c0: 687b ldr r3, [r7, #4] - 80065c2: 681b ldr r3, [r3, #0] - 80065c4: f46f 7280 mvn.w r2, #256 @ 0x100 - 80065c8: 611a str r2, [r3, #16] + 800665c: 687b ldr r3, [r7, #4] + 800665e: 681b ldr r3, [r3, #0] + 8006660: f46f 7280 mvn.w r2, #256 @ 0x100 + 8006664: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->Break2Callback(htim); #else HAL_TIMEx_Break2Callback(htim); - 80065ca: 6878 ldr r0, [r7, #4] - 80065cc: f000 f970 bl 80068b0 + 8006666: 6878 ldr r0, [r7, #4] + 8006668: f000 f970 bl 800694c #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } #endif /* TIM_BDTR_BK2E */ /* TIM Trigger detection event */ if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER)) - 80065d0: 68bb ldr r3, [r7, #8] - 80065d2: f003 0340 and.w r3, r3, #64 @ 0x40 - 80065d6: 2b00 cmp r3, #0 - 80065d8: d00c beq.n 80065f4 + 800666c: 68bb ldr r3, [r7, #8] + 800666e: f003 0340 and.w r3, r3, #64 @ 0x40 + 8006672: 2b00 cmp r3, #0 + 8006674: d00c beq.n 8006690 { if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER)) - 80065da: 68fb ldr r3, [r7, #12] - 80065dc: f003 0340 and.w r3, r3, #64 @ 0x40 - 80065e0: 2b00 cmp r3, #0 - 80065e2: d007 beq.n 80065f4 + 8006676: 68fb ldr r3, [r7, #12] + 8006678: f003 0340 and.w r3, r3, #64 @ 0x40 + 800667c: 2b00 cmp r3, #0 + 800667e: d007 beq.n 8006690 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER); - 80065e4: 687b ldr r3, [r7, #4] - 80065e6: 681b ldr r3, [r3, #0] - 80065e8: f06f 0240 mvn.w r2, #64 @ 0x40 - 80065ec: 611a str r2, [r3, #16] + 8006680: 687b ldr r3, [r7, #4] + 8006682: 681b ldr r3, [r3, #0] + 8006684: f06f 0240 mvn.w r2, #64 @ 0x40 + 8006688: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else HAL_TIM_TriggerCallback(htim); - 80065ee: 6878 ldr r0, [r7, #4] - 80065f0: f000 f83e bl 8006670 + 800668a: 6878 ldr r0, [r7, #4] + 800668c: f000 f83e bl 800670c #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM commutation event */ if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM)) - 80065f4: 68bb ldr r3, [r7, #8] - 80065f6: f003 0320 and.w r3, r3, #32 - 80065fa: 2b00 cmp r3, #0 - 80065fc: d00c beq.n 8006618 + 8006690: 68bb ldr r3, [r7, #8] + 8006692: f003 0320 and.w r3, r3, #32 + 8006696: 2b00 cmp r3, #0 + 8006698: d00c beq.n 80066b4 { if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM)) - 80065fe: 68fb ldr r3, [r7, #12] - 8006600: f003 0320 and.w r3, r3, #32 - 8006604: 2b00 cmp r3, #0 - 8006606: d007 beq.n 8006618 + 800669a: 68fb ldr r3, [r7, #12] + 800669c: f003 0320 and.w r3, r3, #32 + 80066a0: 2b00 cmp r3, #0 + 80066a2: d007 beq.n 80066b4 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM); - 8006608: 687b ldr r3, [r7, #4] - 800660a: 681b ldr r3, [r3, #0] - 800660c: f06f 0220 mvn.w r2, #32 - 8006610: 611a str r2, [r3, #16] + 80066a4: 687b ldr r3, [r7, #4] + 80066a6: 681b ldr r3, [r3, #0] + 80066a8: f06f 0220 mvn.w r2, #32 + 80066ac: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationCallback(htim); #else HAL_TIMEx_CommutCallback(htim); - 8006612: 6878 ldr r0, [r7, #4] - 8006614: f000 f938 bl 8006888 + 80066ae: 6878 ldr r0, [r7, #4] + 80066b0: f000 f938 bl 8006924 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } } - 8006618: bf00 nop - 800661a: 3710 adds r7, #16 - 800661c: 46bd mov sp, r7 - 800661e: bd80 pop {r7, pc} + 80066b4: bf00 nop + 80066b6: 3710 adds r7, #16 + 80066b8: 46bd mov sp, r7 + 80066ba: bd80 pop {r7, pc} -08006620 : +080066bc : * @brief Period elapsed callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { - 8006620: b480 push {r7} - 8006622: b083 sub sp, #12 - 8006624: af00 add r7, sp, #0 - 8006626: 6078 str r0, [r7, #4] + 80066bc: b480 push {r7} + 80066be: b083 sub sp, #12 + 80066c0: af00 add r7, sp, #0 + 80066c2: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PeriodElapsedCallback could be implemented in the user file */ } - 8006628: bf00 nop - 800662a: 370c adds r7, #12 - 800662c: 46bd mov sp, r7 - 800662e: f85d 7b04 ldr.w r7, [sp], #4 - 8006632: 4770 bx lr + 80066c4: bf00 nop + 80066c6: 370c adds r7, #12 + 80066c8: 46bd mov sp, r7 + 80066ca: f85d 7b04 ldr.w r7, [sp], #4 + 80066ce: 4770 bx lr -08006634 : +080066d0 : * @brief Output Compare callback in non-blocking mode * @param htim TIM OC handle * @retval None */ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) { - 8006634: b480 push {r7} - 8006636: b083 sub sp, #12 - 8006638: af00 add r7, sp, #0 - 800663a: 6078 str r0, [r7, #4] + 80066d0: b480 push {r7} + 80066d2: b083 sub sp, #12 + 80066d4: af00 add r7, sp, #0 + 80066d6: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file */ } - 800663c: bf00 nop - 800663e: 370c adds r7, #12 - 8006640: 46bd mov sp, r7 - 8006642: f85d 7b04 ldr.w r7, [sp], #4 - 8006646: 4770 bx lr + 80066d8: bf00 nop + 80066da: 370c adds r7, #12 + 80066dc: 46bd mov sp, r7 + 80066de: f85d 7b04 ldr.w r7, [sp], #4 + 80066e2: 4770 bx lr -08006648 : +080066e4 : * @brief Input Capture callback in non-blocking mode * @param htim TIM IC handle * @retval None */ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) { - 8006648: b480 push {r7} - 800664a: b083 sub sp, #12 - 800664c: af00 add r7, sp, #0 - 800664e: 6078 str r0, [r7, #4] + 80066e4: b480 push {r7} + 80066e6: b083 sub sp, #12 + 80066e8: af00 add r7, sp, #0 + 80066ea: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_CaptureCallback could be implemented in the user file */ } - 8006650: bf00 nop - 8006652: 370c adds r7, #12 - 8006654: 46bd mov sp, r7 - 8006656: f85d 7b04 ldr.w r7, [sp], #4 - 800665a: 4770 bx lr + 80066ec: bf00 nop + 80066ee: 370c adds r7, #12 + 80066f0: 46bd mov sp, r7 + 80066f2: f85d 7b04 ldr.w r7, [sp], #4 + 80066f6: 4770 bx lr -0800665c : +080066f8 : * @brief PWM Pulse finished callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) { - 800665c: b480 push {r7} - 800665e: b083 sub sp, #12 - 8006660: af00 add r7, sp, #0 - 8006662: 6078 str r0, [r7, #4] + 80066f8: b480 push {r7} + 80066fa: b083 sub sp, #12 + 80066fc: af00 add r7, sp, #0 + 80066fe: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file */ } - 8006664: bf00 nop - 8006666: 370c adds r7, #12 - 8006668: 46bd mov sp, r7 - 800666a: f85d 7b04 ldr.w r7, [sp], #4 - 800666e: 4770 bx lr + 8006700: bf00 nop + 8006702: 370c adds r7, #12 + 8006704: 46bd mov sp, r7 + 8006706: f85d 7b04 ldr.w r7, [sp], #4 + 800670a: 4770 bx lr -08006670 : +0800670c : * @brief Hall Trigger detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) { - 8006670: b480 push {r7} - 8006672: b083 sub sp, #12 - 8006674: af00 add r7, sp, #0 - 8006676: 6078 str r0, [r7, #4] + 800670c: b480 push {r7} + 800670e: b083 sub sp, #12 + 8006710: af00 add r7, sp, #0 + 8006712: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_TriggerCallback could be implemented in the user file */ } - 8006678: bf00 nop - 800667a: 370c adds r7, #12 - 800667c: 46bd mov sp, r7 - 800667e: f85d 7b04 ldr.w r7, [sp], #4 - 8006682: 4770 bx lr + 8006714: bf00 nop + 8006716: 370c adds r7, #12 + 8006718: 46bd mov sp, r7 + 800671a: f85d 7b04 ldr.w r7, [sp], #4 + 800671e: 4770 bx lr -08006684 : +08006720 : * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) { - 8006684: b480 push {r7} - 8006686: b085 sub sp, #20 - 8006688: af00 add r7, sp, #0 - 800668a: 6078 str r0, [r7, #4] - 800668c: 6039 str r1, [r7, #0] + 8006720: b480 push {r7} + 8006722: b085 sub sp, #20 + 8006724: af00 add r7, sp, #0 + 8006726: 6078 str r0, [r7, #4] + 8006728: 6039 str r1, [r7, #0] uint32_t tmpcr1; tmpcr1 = TIMx->CR1; - 800668e: 687b ldr r3, [r7, #4] - 8006690: 681b ldr r3, [r3, #0] - 8006692: 60fb str r3, [r7, #12] + 800672a: 687b ldr r3, [r7, #4] + 800672c: 681b ldr r3, [r3, #0] + 800672e: 60fb str r3, [r7, #12] /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) - 8006694: 687b ldr r3, [r7, #4] - 8006696: 4a3c ldr r2, [pc, #240] @ (8006788 ) - 8006698: 4293 cmp r3, r2 - 800669a: d00b beq.n 80066b4 - 800669c: 687b ldr r3, [r7, #4] - 800669e: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 - 80066a2: d007 beq.n 80066b4 - 80066a4: 687b ldr r3, [r7, #4] - 80066a6: 4a39 ldr r2, [pc, #228] @ (800678c ) - 80066a8: 4293 cmp r3, r2 - 80066aa: d003 beq.n 80066b4 - 80066ac: 687b ldr r3, [r7, #4] - 80066ae: 4a38 ldr r2, [pc, #224] @ (8006790 ) - 80066b0: 4293 cmp r3, r2 - 80066b2: d108 bne.n 80066c6 + 8006730: 687b ldr r3, [r7, #4] + 8006732: 4a3c ldr r2, [pc, #240] @ (8006824 ) + 8006734: 4293 cmp r3, r2 + 8006736: d00b beq.n 8006750 + 8006738: 687b ldr r3, [r7, #4] + 800673a: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 800673e: d007 beq.n 8006750 + 8006740: 687b ldr r3, [r7, #4] + 8006742: 4a39 ldr r2, [pc, #228] @ (8006828 ) + 8006744: 4293 cmp r3, r2 + 8006746: d003 beq.n 8006750 + 8006748: 687b ldr r3, [r7, #4] + 800674a: 4a38 ldr r2, [pc, #224] @ (800682c ) + 800674c: 4293 cmp r3, r2 + 800674e: d108 bne.n 8006762 { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); - 80066b4: 68fb ldr r3, [r7, #12] - 80066b6: f023 0370 bic.w r3, r3, #112 @ 0x70 - 80066ba: 60fb str r3, [r7, #12] + 8006750: 68fb ldr r3, [r7, #12] + 8006752: f023 0370 bic.w r3, r3, #112 @ 0x70 + 8006756: 60fb str r3, [r7, #12] tmpcr1 |= Structure->CounterMode; - 80066bc: 683b ldr r3, [r7, #0] - 80066be: 685b ldr r3, [r3, #4] - 80066c0: 68fa ldr r2, [r7, #12] - 80066c2: 4313 orrs r3, r2 - 80066c4: 60fb str r3, [r7, #12] + 8006758: 683b ldr r3, [r7, #0] + 800675a: 685b ldr r3, [r3, #4] + 800675c: 68fa ldr r2, [r7, #12] + 800675e: 4313 orrs r3, r2 + 8006760: 60fb str r3, [r7, #12] } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) - 80066c6: 687b ldr r3, [r7, #4] - 80066c8: 4a2f ldr r2, [pc, #188] @ (8006788 ) - 80066ca: 4293 cmp r3, r2 - 80066cc: d017 beq.n 80066fe - 80066ce: 687b ldr r3, [r7, #4] - 80066d0: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 - 80066d4: d013 beq.n 80066fe - 80066d6: 687b ldr r3, [r7, #4] - 80066d8: 4a2c ldr r2, [pc, #176] @ (800678c ) - 80066da: 4293 cmp r3, r2 - 80066dc: d00f beq.n 80066fe - 80066de: 687b ldr r3, [r7, #4] - 80066e0: 4a2b ldr r2, [pc, #172] @ (8006790 ) - 80066e2: 4293 cmp r3, r2 - 80066e4: d00b beq.n 80066fe - 80066e6: 687b ldr r3, [r7, #4] - 80066e8: 4a2a ldr r2, [pc, #168] @ (8006794 ) - 80066ea: 4293 cmp r3, r2 - 80066ec: d007 beq.n 80066fe - 80066ee: 687b ldr r3, [r7, #4] - 80066f0: 4a29 ldr r2, [pc, #164] @ (8006798 ) - 80066f2: 4293 cmp r3, r2 - 80066f4: d003 beq.n 80066fe - 80066f6: 687b ldr r3, [r7, #4] - 80066f8: 4a28 ldr r2, [pc, #160] @ (800679c ) - 80066fa: 4293 cmp r3, r2 - 80066fc: d108 bne.n 8006710 + 8006762: 687b ldr r3, [r7, #4] + 8006764: 4a2f ldr r2, [pc, #188] @ (8006824 ) + 8006766: 4293 cmp r3, r2 + 8006768: d017 beq.n 800679a + 800676a: 687b ldr r3, [r7, #4] + 800676c: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 8006770: d013 beq.n 800679a + 8006772: 687b ldr r3, [r7, #4] + 8006774: 4a2c ldr r2, [pc, #176] @ (8006828 ) + 8006776: 4293 cmp r3, r2 + 8006778: d00f beq.n 800679a + 800677a: 687b ldr r3, [r7, #4] + 800677c: 4a2b ldr r2, [pc, #172] @ (800682c ) + 800677e: 4293 cmp r3, r2 + 8006780: d00b beq.n 800679a + 8006782: 687b ldr r3, [r7, #4] + 8006784: 4a2a ldr r2, [pc, #168] @ (8006830 ) + 8006786: 4293 cmp r3, r2 + 8006788: d007 beq.n 800679a + 800678a: 687b ldr r3, [r7, #4] + 800678c: 4a29 ldr r2, [pc, #164] @ (8006834 ) + 800678e: 4293 cmp r3, r2 + 8006790: d003 beq.n 800679a + 8006792: 687b ldr r3, [r7, #4] + 8006794: 4a28 ldr r2, [pc, #160] @ (8006838 ) + 8006796: 4293 cmp r3, r2 + 8006798: d108 bne.n 80067ac { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; - 80066fe: 68fb ldr r3, [r7, #12] - 8006700: f423 7340 bic.w r3, r3, #768 @ 0x300 - 8006704: 60fb str r3, [r7, #12] + 800679a: 68fb ldr r3, [r7, #12] + 800679c: f423 7340 bic.w r3, r3, #768 @ 0x300 + 80067a0: 60fb str r3, [r7, #12] tmpcr1 |= (uint32_t)Structure->ClockDivision; - 8006706: 683b ldr r3, [r7, #0] - 8006708: 68db ldr r3, [r3, #12] - 800670a: 68fa ldr r2, [r7, #12] - 800670c: 4313 orrs r3, r2 - 800670e: 60fb str r3, [r7, #12] + 80067a2: 683b ldr r3, [r7, #0] + 80067a4: 68db ldr r3, [r3, #12] + 80067a6: 68fa ldr r2, [r7, #12] + 80067a8: 4313 orrs r3, r2 + 80067aa: 60fb str r3, [r7, #12] } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); - 8006710: 68fb ldr r3, [r7, #12] - 8006712: f023 0280 bic.w r2, r3, #128 @ 0x80 - 8006716: 683b ldr r3, [r7, #0] - 8006718: 695b ldr r3, [r3, #20] - 800671a: 4313 orrs r3, r2 - 800671c: 60fb str r3, [r7, #12] + 80067ac: 68fb ldr r3, [r7, #12] + 80067ae: f023 0280 bic.w r2, r3, #128 @ 0x80 + 80067b2: 683b ldr r3, [r7, #0] + 80067b4: 695b ldr r3, [r3, #20] + 80067b6: 4313 orrs r3, r2 + 80067b8: 60fb str r3, [r7, #12] TIMx->CR1 = tmpcr1; - 800671e: 687b ldr r3, [r7, #4] - 8006720: 68fa ldr r2, [r7, #12] - 8006722: 601a str r2, [r3, #0] + 80067ba: 687b ldr r3, [r7, #4] + 80067bc: 68fa ldr r2, [r7, #12] + 80067be: 601a str r2, [r3, #0] /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; - 8006724: 683b ldr r3, [r7, #0] - 8006726: 689a ldr r2, [r3, #8] - 8006728: 687b ldr r3, [r7, #4] - 800672a: 62da str r2, [r3, #44] @ 0x2c + 80067c0: 683b ldr r3, [r7, #0] + 80067c2: 689a ldr r2, [r3, #8] + 80067c4: 687b ldr r3, [r7, #4] + 80067c6: 62da str r2, [r3, #44] @ 0x2c /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; - 800672c: 683b ldr r3, [r7, #0] - 800672e: 681a ldr r2, [r3, #0] - 8006730: 687b ldr r3, [r7, #4] - 8006732: 629a str r2, [r3, #40] @ 0x28 + 80067c8: 683b ldr r3, [r7, #0] + 80067ca: 681a ldr r2, [r3, #0] + 80067cc: 687b ldr r3, [r7, #4] + 80067ce: 629a str r2, [r3, #40] @ 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) - 8006734: 687b ldr r3, [r7, #4] - 8006736: 4a14 ldr r2, [pc, #80] @ (8006788 ) - 8006738: 4293 cmp r3, r2 - 800673a: d00b beq.n 8006754 - 800673c: 687b ldr r3, [r7, #4] - 800673e: 4a15 ldr r2, [pc, #84] @ (8006794 ) - 8006740: 4293 cmp r3, r2 - 8006742: d007 beq.n 8006754 - 8006744: 687b ldr r3, [r7, #4] - 8006746: 4a14 ldr r2, [pc, #80] @ (8006798 ) - 8006748: 4293 cmp r3, r2 - 800674a: d003 beq.n 8006754 - 800674c: 687b ldr r3, [r7, #4] - 800674e: 4a13 ldr r2, [pc, #76] @ (800679c ) - 8006750: 4293 cmp r3, r2 - 8006752: d103 bne.n 800675c + 80067d0: 687b ldr r3, [r7, #4] + 80067d2: 4a14 ldr r2, [pc, #80] @ (8006824 ) + 80067d4: 4293 cmp r3, r2 + 80067d6: d00b beq.n 80067f0 + 80067d8: 687b ldr r3, [r7, #4] + 80067da: 4a15 ldr r2, [pc, #84] @ (8006830 ) + 80067dc: 4293 cmp r3, r2 + 80067de: d007 beq.n 80067f0 + 80067e0: 687b ldr r3, [r7, #4] + 80067e2: 4a14 ldr r2, [pc, #80] @ (8006834 ) + 80067e4: 4293 cmp r3, r2 + 80067e6: d003 beq.n 80067f0 + 80067e8: 687b ldr r3, [r7, #4] + 80067ea: 4a13 ldr r2, [pc, #76] @ (8006838 ) + 80067ec: 4293 cmp r3, r2 + 80067ee: d103 bne.n 80067f8 { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; - 8006754: 683b ldr r3, [r7, #0] - 8006756: 691a ldr r2, [r3, #16] - 8006758: 687b ldr r3, [r7, #4] - 800675a: 631a str r2, [r3, #48] @ 0x30 + 80067f0: 683b ldr r3, [r7, #0] + 80067f2: 691a ldr r2, [r3, #16] + 80067f4: 687b ldr r3, [r7, #4] + 80067f6: 631a str r2, [r3, #48] @ 0x30 } /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; - 800675c: 687b ldr r3, [r7, #4] - 800675e: 2201 movs r2, #1 - 8006760: 615a str r2, [r3, #20] + 80067f8: 687b ldr r3, [r7, #4] + 80067fa: 2201 movs r2, #1 + 80067fc: 615a str r2, [r3, #20] /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */ if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE)) - 8006762: 687b ldr r3, [r7, #4] - 8006764: 691b ldr r3, [r3, #16] - 8006766: f003 0301 and.w r3, r3, #1 - 800676a: 2b01 cmp r3, #1 - 800676c: d105 bne.n 800677a + 80067fe: 687b ldr r3, [r7, #4] + 8006800: 691b ldr r3, [r3, #16] + 8006802: f003 0301 and.w r3, r3, #1 + 8006806: 2b01 cmp r3, #1 + 8006808: d105 bne.n 8006816 { /* Clear the update flag */ CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE); - 800676e: 687b ldr r3, [r7, #4] - 8006770: 691b ldr r3, [r3, #16] - 8006772: f023 0201 bic.w r2, r3, #1 - 8006776: 687b ldr r3, [r7, #4] - 8006778: 611a str r2, [r3, #16] + 800680a: 687b ldr r3, [r7, #4] + 800680c: 691b ldr r3, [r3, #16] + 800680e: f023 0201 bic.w r2, r3, #1 + 8006812: 687b ldr r3, [r7, #4] + 8006814: 611a str r2, [r3, #16] } } - 800677a: bf00 nop - 800677c: 3714 adds r7, #20 - 800677e: 46bd mov sp, r7 - 8006780: f85d 7b04 ldr.w r7, [sp], #4 - 8006784: 4770 bx lr - 8006786: bf00 nop - 8006788: 40012c00 .word 0x40012c00 - 800678c: 40000400 .word 0x40000400 - 8006790: 40000800 .word 0x40000800 - 8006794: 40014000 .word 0x40014000 - 8006798: 40014400 .word 0x40014400 - 800679c: 40014800 .word 0x40014800 + 8006816: bf00 nop + 8006818: 3714 adds r7, #20 + 800681a: 46bd mov sp, r7 + 800681c: f85d 7b04 ldr.w r7, [sp], #4 + 8006820: 4770 bx lr + 8006822: bf00 nop + 8006824: 40012c00 .word 0x40012c00 + 8006828: 40000400 .word 0x40000400 + 800682c: 40000800 .word 0x40000800 + 8006830: 40014000 .word 0x40014000 + 8006834: 40014400 .word 0x40014400 + 8006838: 40014800 .word 0x40014800 -080067a0 : +0800683c : * mode. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, const TIM_MasterConfigTypeDef *sMasterConfig) { - 80067a0: b480 push {r7} - 80067a2: b085 sub sp, #20 - 80067a4: af00 add r7, sp, #0 - 80067a6: 6078 str r0, [r7, #4] - 80067a8: 6039 str r1, [r7, #0] + 800683c: b480 push {r7} + 800683e: b085 sub sp, #20 + 8006840: af00 add r7, sp, #0 + 8006842: 6078 str r0, [r7, #4] + 8006844: 6039 str r1, [r7, #0] assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); /* Check input state */ __HAL_LOCK(htim); - 80067aa: 687b ldr r3, [r7, #4] - 80067ac: f893 303c ldrb.w r3, [r3, #60] @ 0x3c - 80067b0: 2b01 cmp r3, #1 - 80067b2: d101 bne.n 80067b8 - 80067b4: 2302 movs r3, #2 - 80067b6: e059 b.n 800686c - 80067b8: 687b ldr r3, [r7, #4] - 80067ba: 2201 movs r2, #1 - 80067bc: f883 203c strb.w r2, [r3, #60] @ 0x3c + 8006846: 687b ldr r3, [r7, #4] + 8006848: f893 303c ldrb.w r3, [r3, #60] @ 0x3c + 800684c: 2b01 cmp r3, #1 + 800684e: d101 bne.n 8006854 + 8006850: 2302 movs r3, #2 + 8006852: e059 b.n 8006908 + 8006854: 687b ldr r3, [r7, #4] + 8006856: 2201 movs r2, #1 + 8006858: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Change the handler state */ htim->State = HAL_TIM_STATE_BUSY; - 80067c0: 687b ldr r3, [r7, #4] - 80067c2: 2202 movs r2, #2 - 80067c4: f883 203d strb.w r2, [r3, #61] @ 0x3d + 800685c: 687b ldr r3, [r7, #4] + 800685e: 2202 movs r2, #2 + 8006860: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; - 80067c8: 687b ldr r3, [r7, #4] - 80067ca: 681b ldr r3, [r3, #0] - 80067cc: 685b ldr r3, [r3, #4] - 80067ce: 60fb str r3, [r7, #12] + 8006864: 687b ldr r3, [r7, #4] + 8006866: 681b ldr r3, [r3, #0] + 8006868: 685b ldr r3, [r3, #4] + 800686a: 60fb str r3, [r7, #12] /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; - 80067d0: 687b ldr r3, [r7, #4] - 80067d2: 681b ldr r3, [r3, #0] - 80067d4: 689b ldr r3, [r3, #8] - 80067d6: 60bb str r3, [r7, #8] + 800686c: 687b ldr r3, [r7, #4] + 800686e: 681b ldr r3, [r3, #0] + 8006870: 689b ldr r3, [r3, #8] + 8006872: 60bb str r3, [r7, #8] #if defined(TIM_CR2_MMS2) /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */ if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) - 80067d8: 687b ldr r3, [r7, #4] - 80067da: 681b ldr r3, [r3, #0] - 80067dc: 4a26 ldr r2, [pc, #152] @ (8006878 ) - 80067de: 4293 cmp r3, r2 - 80067e0: d108 bne.n 80067f4 + 8006874: 687b ldr r3, [r7, #4] + 8006876: 681b ldr r3, [r3, #0] + 8006878: 4a26 ldr r2, [pc, #152] @ (8006914 ) + 800687a: 4293 cmp r3, r2 + 800687c: d108 bne.n 8006890 { /* Check the parameters */ assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2)); /* Clear the MMS2 bits */ tmpcr2 &= ~TIM_CR2_MMS2; - 80067e2: 68fb ldr r3, [r7, #12] - 80067e4: f423 0370 bic.w r3, r3, #15728640 @ 0xf00000 - 80067e8: 60fb str r3, [r7, #12] + 800687e: 68fb ldr r3, [r7, #12] + 8006880: f423 0370 bic.w r3, r3, #15728640 @ 0xf00000 + 8006884: 60fb str r3, [r7, #12] /* Select the TRGO2 source*/ tmpcr2 |= sMasterConfig->MasterOutputTrigger2; - 80067ea: 683b ldr r3, [r7, #0] - 80067ec: 685b ldr r3, [r3, #4] - 80067ee: 68fa ldr r2, [r7, #12] - 80067f0: 4313 orrs r3, r2 - 80067f2: 60fb str r3, [r7, #12] + 8006886: 683b ldr r3, [r7, #0] + 8006888: 685b ldr r3, [r3, #4] + 800688a: 68fa ldr r2, [r7, #12] + 800688c: 4313 orrs r3, r2 + 800688e: 60fb str r3, [r7, #12] } #endif /* TIM_CR2_MMS2 */ /* Reset the MMS Bits */ tmpcr2 &= ~TIM_CR2_MMS; - 80067f4: 68fb ldr r3, [r7, #12] - 80067f6: f023 0370 bic.w r3, r3, #112 @ 0x70 - 80067fa: 60fb str r3, [r7, #12] + 8006890: 68fb ldr r3, [r7, #12] + 8006892: f023 0370 bic.w r3, r3, #112 @ 0x70 + 8006896: 60fb str r3, [r7, #12] /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; - 80067fc: 683b ldr r3, [r7, #0] - 80067fe: 681b ldr r3, [r3, #0] - 8006800: 68fa ldr r2, [r7, #12] - 8006802: 4313 orrs r3, r2 - 8006804: 60fb str r3, [r7, #12] + 8006898: 683b ldr r3, [r7, #0] + 800689a: 681b ldr r3, [r3, #0] + 800689c: 68fa ldr r2, [r7, #12] + 800689e: 4313 orrs r3, r2 + 80068a0: 60fb str r3, [r7, #12] /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; - 8006806: 687b ldr r3, [r7, #4] - 8006808: 681b ldr r3, [r3, #0] - 800680a: 68fa ldr r2, [r7, #12] - 800680c: 605a str r2, [r3, #4] + 80068a2: 687b ldr r3, [r7, #4] + 80068a4: 681b ldr r3, [r3, #0] + 80068a6: 68fa ldr r2, [r7, #12] + 80068a8: 605a str r2, [r3, #4] if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - 800680e: 687b ldr r3, [r7, #4] - 8006810: 681b ldr r3, [r3, #0] - 8006812: 4a19 ldr r2, [pc, #100] @ (8006878 ) - 8006814: 4293 cmp r3, r2 - 8006816: d013 beq.n 8006840 - 8006818: 687b ldr r3, [r7, #4] - 800681a: 681b ldr r3, [r3, #0] - 800681c: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 - 8006820: d00e beq.n 8006840 - 8006822: 687b ldr r3, [r7, #4] - 8006824: 681b ldr r3, [r3, #0] - 8006826: 4a15 ldr r2, [pc, #84] @ (800687c ) - 8006828: 4293 cmp r3, r2 - 800682a: d009 beq.n 8006840 - 800682c: 687b ldr r3, [r7, #4] - 800682e: 681b ldr r3, [r3, #0] - 8006830: 4a13 ldr r2, [pc, #76] @ (8006880 ) - 8006832: 4293 cmp r3, r2 - 8006834: d004 beq.n 8006840 - 8006836: 687b ldr r3, [r7, #4] - 8006838: 681b ldr r3, [r3, #0] - 800683a: 4a12 ldr r2, [pc, #72] @ (8006884 ) - 800683c: 4293 cmp r3, r2 - 800683e: d10c bne.n 800685a + 80068aa: 687b ldr r3, [r7, #4] + 80068ac: 681b ldr r3, [r3, #0] + 80068ae: 4a19 ldr r2, [pc, #100] @ (8006914 ) + 80068b0: 4293 cmp r3, r2 + 80068b2: d013 beq.n 80068dc + 80068b4: 687b ldr r3, [r7, #4] + 80068b6: 681b ldr r3, [r3, #0] + 80068b8: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 80068bc: d00e beq.n 80068dc + 80068be: 687b ldr r3, [r7, #4] + 80068c0: 681b ldr r3, [r3, #0] + 80068c2: 4a15 ldr r2, [pc, #84] @ (8006918 ) + 80068c4: 4293 cmp r3, r2 + 80068c6: d009 beq.n 80068dc + 80068c8: 687b ldr r3, [r7, #4] + 80068ca: 681b ldr r3, [r3, #0] + 80068cc: 4a13 ldr r2, [pc, #76] @ (800691c ) + 80068ce: 4293 cmp r3, r2 + 80068d0: d004 beq.n 80068dc + 80068d2: 687b ldr r3, [r7, #4] + 80068d4: 681b ldr r3, [r3, #0] + 80068d6: 4a12 ldr r2, [pc, #72] @ (8006920 ) + 80068d8: 4293 cmp r3, r2 + 80068da: d10c bne.n 80068f6 { /* Reset the MSM Bit */ tmpsmcr &= ~TIM_SMCR_MSM; - 8006840: 68bb ldr r3, [r7, #8] - 8006842: f023 0380 bic.w r3, r3, #128 @ 0x80 - 8006846: 60bb str r3, [r7, #8] + 80068dc: 68bb ldr r3, [r7, #8] + 80068de: f023 0380 bic.w r3, r3, #128 @ 0x80 + 80068e2: 60bb str r3, [r7, #8] /* Set master mode */ tmpsmcr |= sMasterConfig->MasterSlaveMode; - 8006848: 683b ldr r3, [r7, #0] - 800684a: 689b ldr r3, [r3, #8] - 800684c: 68ba ldr r2, [r7, #8] - 800684e: 4313 orrs r3, r2 - 8006850: 60bb str r3, [r7, #8] + 80068e4: 683b ldr r3, [r7, #0] + 80068e6: 689b ldr r3, [r3, #8] + 80068e8: 68ba ldr r2, [r7, #8] + 80068ea: 4313 orrs r3, r2 + 80068ec: 60bb str r3, [r7, #8] /* Update TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; - 8006852: 687b ldr r3, [r7, #4] - 8006854: 681b ldr r3, [r3, #0] - 8006856: 68ba ldr r2, [r7, #8] - 8006858: 609a str r2, [r3, #8] + 80068ee: 687b ldr r3, [r7, #4] + 80068f0: 681b ldr r3, [r3, #0] + 80068f2: 68ba ldr r2, [r7, #8] + 80068f4: 609a str r2, [r3, #8] } /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; - 800685a: 687b ldr r3, [r7, #4] - 800685c: 2201 movs r2, #1 - 800685e: f883 203d strb.w r2, [r3, #61] @ 0x3d + 80068f6: 687b ldr r3, [r7, #4] + 80068f8: 2201 movs r2, #1 + 80068fa: f883 203d strb.w r2, [r3, #61] @ 0x3d __HAL_UNLOCK(htim); - 8006862: 687b ldr r3, [r7, #4] - 8006864: 2200 movs r2, #0 - 8006866: f883 203c strb.w r2, [r3, #60] @ 0x3c + 80068fe: 687b ldr r3, [r7, #4] + 8006900: 2200 movs r2, #0 + 8006902: f883 203c strb.w r2, [r3, #60] @ 0x3c return HAL_OK; - 800686a: 2300 movs r3, #0 + 8006906: 2300 movs r3, #0 } - 800686c: 4618 mov r0, r3 - 800686e: 3714 adds r7, #20 - 8006870: 46bd mov sp, r7 - 8006872: f85d 7b04 ldr.w r7, [sp], #4 - 8006876: 4770 bx lr - 8006878: 40012c00 .word 0x40012c00 - 800687c: 40000400 .word 0x40000400 - 8006880: 40000800 .word 0x40000800 - 8006884: 40014000 .word 0x40014000 + 8006908: 4618 mov r0, r3 + 800690a: 3714 adds r7, #20 + 800690c: 46bd mov sp, r7 + 800690e: f85d 7b04 ldr.w r7, [sp], #4 + 8006912: 4770 bx lr + 8006914: 40012c00 .word 0x40012c00 + 8006918: 40000400 .word 0x40000400 + 800691c: 40000800 .word 0x40000800 + 8006920: 40014000 .word 0x40014000 -08006888 : +08006924 : * @brief Commutation callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) { - 8006888: b480 push {r7} - 800688a: b083 sub sp, #12 - 800688c: af00 add r7, sp, #0 - 800688e: 6078 str r0, [r7, #4] + 8006924: b480 push {r7} + 8006926: b083 sub sp, #12 + 8006928: af00 add r7, sp, #0 + 800692a: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_CommutCallback could be implemented in the user file */ } - 8006890: bf00 nop - 8006892: 370c adds r7, #12 - 8006894: 46bd mov sp, r7 - 8006896: f85d 7b04 ldr.w r7, [sp], #4 - 800689a: 4770 bx lr + 800692c: bf00 nop + 800692e: 370c adds r7, #12 + 8006930: 46bd mov sp, r7 + 8006932: f85d 7b04 ldr.w r7, [sp], #4 + 8006936: 4770 bx lr -0800689c : +08006938 : * @brief Break detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) { - 800689c: b480 push {r7} - 800689e: b083 sub sp, #12 - 80068a0: af00 add r7, sp, #0 - 80068a2: 6078 str r0, [r7, #4] + 8006938: b480 push {r7} + 800693a: b083 sub sp, #12 + 800693c: af00 add r7, sp, #0 + 800693e: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_BreakCallback could be implemented in the user file */ } - 80068a4: bf00 nop - 80068a6: 370c adds r7, #12 - 80068a8: 46bd mov sp, r7 - 80068aa: f85d 7b04 ldr.w r7, [sp], #4 - 80068ae: 4770 bx lr + 8006940: bf00 nop + 8006942: 370c adds r7, #12 + 8006944: 46bd mov sp, r7 + 8006946: f85d 7b04 ldr.w r7, [sp], #4 + 800694a: 4770 bx lr -080068b0 : +0800694c : * @brief Break2 detection callback in non blocking mode * @param htim: TIM handle * @retval None */ __weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim) { - 80068b0: b480 push {r7} - 80068b2: b083 sub sp, #12 - 80068b4: af00 add r7, sp, #0 - 80068b6: 6078 str r0, [r7, #4] + 800694c: b480 push {r7} + 800694e: b083 sub sp, #12 + 8006950: af00 add r7, sp, #0 + 8006952: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_TIMEx_Break2Callback could be implemented in the user file */ } - 80068b8: bf00 nop - 80068ba: 370c adds r7, #12 - 80068bc: 46bd mov sp, r7 - 80068be: f85d 7b04 ldr.w r7, [sp], #4 - 80068c2: 4770 bx lr + 8006954: bf00 nop + 8006956: 370c adds r7, #12 + 8006958: 46bd mov sp, r7 + 800695a: f85d 7b04 ldr.w r7, [sp], #4 + 800695e: 4770 bx lr -080068c4 : +08006960 : * parameters in the UART_InitTypeDef and initialize the associated handle. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { - 80068c4: b580 push {r7, lr} - 80068c6: b082 sub sp, #8 - 80068c8: af00 add r7, sp, #0 - 80068ca: 6078 str r0, [r7, #4] + 8006960: b580 push {r7, lr} + 8006962: b082 sub sp, #8 + 8006964: af00 add r7, sp, #0 + 8006966: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) - 80068cc: 687b ldr r3, [r7, #4] - 80068ce: 2b00 cmp r3, #0 - 80068d0: d101 bne.n 80068d6 + 8006968: 687b ldr r3, [r7, #4] + 800696a: 2b00 cmp r3, #0 + 800696c: d101 bne.n 8006972 { return HAL_ERROR; - 80068d2: 2301 movs r3, #1 - 80068d4: e040 b.n 8006958 + 800696e: 2301 movs r3, #1 + 8006970: e040 b.n 80069f4 { /* Check the parameters */ assert_param(IS_UART_INSTANCE(huart->Instance)); } if (huart->gState == HAL_UART_STATE_RESET) - 80068d6: 687b ldr r3, [r7, #4] - 80068d8: 6fdb ldr r3, [r3, #124] @ 0x7c - 80068da: 2b00 cmp r3, #0 - 80068dc: d106 bne.n 80068ec + 8006972: 687b ldr r3, [r7, #4] + 8006974: 6fdb ldr r3, [r3, #124] @ 0x7c + 8006976: 2b00 cmp r3, #0 + 8006978: d106 bne.n 8006988 { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; - 80068de: 687b ldr r3, [r7, #4] - 80068e0: 2200 movs r2, #0 - 80068e2: f883 2078 strb.w r2, [r3, #120] @ 0x78 + 800697a: 687b ldr r3, [r7, #4] + 800697c: 2200 movs r2, #0 + 800697e: f883 2078 strb.w r2, [r3, #120] @ 0x78 /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); - 80068e6: 6878 ldr r0, [r7, #4] - 80068e8: f7fb fb74 bl 8001fd4 + 8006982: 6878 ldr r0, [r7, #4] + 8006984: f7fb fb74 bl 8002070 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; - 80068ec: 687b ldr r3, [r7, #4] - 80068ee: 2224 movs r2, #36 @ 0x24 - 80068f0: 67da str r2, [r3, #124] @ 0x7c + 8006988: 687b ldr r3, [r7, #4] + 800698a: 2224 movs r2, #36 @ 0x24 + 800698c: 67da str r2, [r3, #124] @ 0x7c __HAL_UART_DISABLE(huart); - 80068f2: 687b ldr r3, [r7, #4] - 80068f4: 681b ldr r3, [r3, #0] - 80068f6: 681a ldr r2, [r3, #0] - 80068f8: 687b ldr r3, [r7, #4] - 80068fa: 681b ldr r3, [r3, #0] - 80068fc: f022 0201 bic.w r2, r2, #1 - 8006900: 601a str r2, [r3, #0] + 800698e: 687b ldr r3, [r7, #4] + 8006990: 681b ldr r3, [r3, #0] + 8006992: 681a ldr r2, [r3, #0] + 8006994: 687b ldr r3, [r7, #4] + 8006996: 681b ldr r3, [r3, #0] + 8006998: f022 0201 bic.w r2, r2, #1 + 800699c: 601a str r2, [r3, #0] /* Perform advanced settings configuration */ /* For some items, configuration requires to be done prior TE and RE bits are set */ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) - 8006902: 687b ldr r3, [r7, #4] - 8006904: 6a5b ldr r3, [r3, #36] @ 0x24 - 8006906: 2b00 cmp r3, #0 - 8006908: d002 beq.n 8006910 + 800699e: 687b ldr r3, [r7, #4] + 80069a0: 6a5b ldr r3, [r3, #36] @ 0x24 + 80069a2: 2b00 cmp r3, #0 + 80069a4: d002 beq.n 80069ac { UART_AdvFeatureConfig(huart); - 800690a: 6878 ldr r0, [r7, #4] - 800690c: f000 f9fc bl 8006d08 + 80069a6: 6878 ldr r0, [r7, #4] + 80069a8: f000 f9fc bl 8006da4 } /* Set the UART Communication parameters */ if (UART_SetConfig(huart) == HAL_ERROR) - 8006910: 6878 ldr r0, [r7, #4] - 8006912: f000 f825 bl 8006960 - 8006916: 4603 mov r3, r0 - 8006918: 2b01 cmp r3, #1 - 800691a: d101 bne.n 8006920 + 80069ac: 6878 ldr r0, [r7, #4] + 80069ae: f000 f825 bl 80069fc + 80069b2: 4603 mov r3, r0 + 80069b4: 2b01 cmp r3, #1 + 80069b6: d101 bne.n 80069bc { return HAL_ERROR; - 800691c: 2301 movs r3, #1 - 800691e: e01b b.n 8006958 + 80069b8: 2301 movs r3, #1 + 80069ba: e01b b.n 80069f4 } /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); - 8006920: 687b ldr r3, [r7, #4] - 8006922: 681b ldr r3, [r3, #0] - 8006924: 685a ldr r2, [r3, #4] - 8006926: 687b ldr r3, [r7, #4] - 8006928: 681b ldr r3, [r3, #0] - 800692a: f422 4290 bic.w r2, r2, #18432 @ 0x4800 - 800692e: 605a str r2, [r3, #4] + 80069bc: 687b ldr r3, [r7, #4] + 80069be: 681b ldr r3, [r3, #0] + 80069c0: 685a ldr r2, [r3, #4] + 80069c2: 687b ldr r3, [r7, #4] + 80069c4: 681b ldr r3, [r3, #0] + 80069c6: f422 4290 bic.w r2, r2, #18432 @ 0x4800 + 80069ca: 605a str r2, [r3, #4] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); - 8006930: 687b ldr r3, [r7, #4] - 8006932: 681b ldr r3, [r3, #0] - 8006934: 689a ldr r2, [r3, #8] - 8006936: 687b ldr r3, [r7, #4] - 8006938: 681b ldr r3, [r3, #0] - 800693a: f022 022a bic.w r2, r2, #42 @ 0x2a - 800693e: 609a str r2, [r3, #8] + 80069cc: 687b ldr r3, [r7, #4] + 80069ce: 681b ldr r3, [r3, #0] + 80069d0: 689a ldr r2, [r3, #8] + 80069d2: 687b ldr r3, [r7, #4] + 80069d4: 681b ldr r3, [r3, #0] + 80069d6: f022 022a bic.w r2, r2, #42 @ 0x2a + 80069da: 609a str r2, [r3, #8] __HAL_UART_ENABLE(huart); - 8006940: 687b ldr r3, [r7, #4] - 8006942: 681b ldr r3, [r3, #0] - 8006944: 681a ldr r2, [r3, #0] - 8006946: 687b ldr r3, [r7, #4] - 8006948: 681b ldr r3, [r3, #0] - 800694a: f042 0201 orr.w r2, r2, #1 - 800694e: 601a str r2, [r3, #0] + 80069dc: 687b ldr r3, [r7, #4] + 80069de: 681b ldr r3, [r3, #0] + 80069e0: 681a ldr r2, [r3, #0] + 80069e2: 687b ldr r3, [r7, #4] + 80069e4: 681b ldr r3, [r3, #0] + 80069e6: f042 0201 orr.w r2, r2, #1 + 80069ea: 601a str r2, [r3, #0] /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); - 8006950: 6878 ldr r0, [r7, #4] - 8006952: f000 fa7b bl 8006e4c - 8006956: 4603 mov r3, r0 + 80069ec: 6878 ldr r0, [r7, #4] + 80069ee: f000 fa7b bl 8006ee8 + 80069f2: 4603 mov r3, r0 } - 8006958: 4618 mov r0, r3 - 800695a: 3708 adds r7, #8 - 800695c: 46bd mov sp, r7 - 800695e: bd80 pop {r7, pc} + 80069f4: 4618 mov r0, r3 + 80069f6: 3708 adds r7, #8 + 80069f8: 46bd mov sp, r7 + 80069fa: bd80 pop {r7, pc} -08006960 : +080069fc : * @brief Configure the UART peripheral. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) { - 8006960: b580 push {r7, lr} - 8006962: b088 sub sp, #32 - 8006964: af00 add r7, sp, #0 - 8006966: 6078 str r0, [r7, #4] + 80069fc: b580 push {r7, lr} + 80069fe: b088 sub sp, #32 + 8006a00: af00 add r7, sp, #0 + 8006a02: 6078 str r0, [r7, #4] uint32_t tmpreg; uint16_t brrtemp; UART_ClockSourceTypeDef clocksource; uint32_t usartdiv; HAL_StatusTypeDef ret = HAL_OK; - 8006968: 2300 movs r3, #0 - 800696a: 77bb strb r3, [r7, #30] + 8006a04: 2300 movs r3, #0 + 8006a06: 77bb strb r3, [r7, #30] * the UART Word Length, Parity, Mode and oversampling: * set the M bits according to huart->Init.WordLength value * set PCE and PS bits according to huart->Init.Parity value * set TE and RE bits according to huart->Init.Mode value * set OVER8 bit according to huart->Init.OverSampling value */ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; - 800696c: 687b ldr r3, [r7, #4] - 800696e: 689a ldr r2, [r3, #8] - 8006970: 687b ldr r3, [r7, #4] - 8006972: 691b ldr r3, [r3, #16] - 8006974: 431a orrs r2, r3 - 8006976: 687b ldr r3, [r7, #4] - 8006978: 695b ldr r3, [r3, #20] - 800697a: 431a orrs r2, r3 - 800697c: 687b ldr r3, [r7, #4] - 800697e: 69db ldr r3, [r3, #28] - 8006980: 4313 orrs r3, r2 - 8006982: 617b str r3, [r7, #20] + 8006a08: 687b ldr r3, [r7, #4] + 8006a0a: 689a ldr r2, [r3, #8] + 8006a0c: 687b ldr r3, [r7, #4] + 8006a0e: 691b ldr r3, [r3, #16] + 8006a10: 431a orrs r2, r3 + 8006a12: 687b ldr r3, [r7, #4] + 8006a14: 695b ldr r3, [r3, #20] + 8006a16: 431a orrs r2, r3 + 8006a18: 687b ldr r3, [r7, #4] + 8006a1a: 69db ldr r3, [r3, #28] + 8006a1c: 4313 orrs r3, r2 + 8006a1e: 617b str r3, [r7, #20] MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); - 8006984: 687b ldr r3, [r7, #4] - 8006986: 681b ldr r3, [r3, #0] - 8006988: 681b ldr r3, [r3, #0] - 800698a: f423 4316 bic.w r3, r3, #38400 @ 0x9600 - 800698e: f023 030c bic.w r3, r3, #12 - 8006992: 687a ldr r2, [r7, #4] - 8006994: 6812 ldr r2, [r2, #0] - 8006996: 6979 ldr r1, [r7, #20] - 8006998: 430b orrs r3, r1 - 800699a: 6013 str r3, [r2, #0] + 8006a20: 687b ldr r3, [r7, #4] + 8006a22: 681b ldr r3, [r3, #0] + 8006a24: 681b ldr r3, [r3, #0] + 8006a26: f423 4316 bic.w r3, r3, #38400 @ 0x9600 + 8006a2a: f023 030c bic.w r3, r3, #12 + 8006a2e: 687a ldr r2, [r7, #4] + 8006a30: 6812 ldr r2, [r2, #0] + 8006a32: 6979 ldr r1, [r7, #20] + 8006a34: 430b orrs r3, r1 + 8006a36: 6013 str r3, [r2, #0] /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according * to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); - 800699c: 687b ldr r3, [r7, #4] - 800699e: 681b ldr r3, [r3, #0] - 80069a0: 685b ldr r3, [r3, #4] - 80069a2: f423 5140 bic.w r1, r3, #12288 @ 0x3000 - 80069a6: 687b ldr r3, [r7, #4] - 80069a8: 68da ldr r2, [r3, #12] - 80069aa: 687b ldr r3, [r7, #4] - 80069ac: 681b ldr r3, [r3, #0] - 80069ae: 430a orrs r2, r1 - 80069b0: 605a str r2, [r3, #4] + 8006a38: 687b ldr r3, [r7, #4] + 8006a3a: 681b ldr r3, [r3, #0] + 8006a3c: 685b ldr r3, [r3, #4] + 8006a3e: f423 5140 bic.w r1, r3, #12288 @ 0x3000 + 8006a42: 687b ldr r3, [r7, #4] + 8006a44: 68da ldr r2, [r3, #12] + 8006a46: 687b ldr r3, [r7, #4] + 8006a48: 681b ldr r3, [r3, #0] + 8006a4a: 430a orrs r2, r1 + 8006a4c: 605a str r2, [r3, #4] /* Configure * - UART HardWare Flow Control: set CTSE and RTSE bits according * to huart->Init.HwFlowCtl value * - one-bit sampling method versus three samples' majority rule according * to huart->Init.OneBitSampling (not applicable to LPUART) */ tmpreg = (uint32_t)huart->Init.HwFlowCtl; - 80069b2: 687b ldr r3, [r7, #4] - 80069b4: 699b ldr r3, [r3, #24] - 80069b6: 617b str r3, [r7, #20] + 8006a4e: 687b ldr r3, [r7, #4] + 8006a50: 699b ldr r3, [r3, #24] + 8006a52: 617b str r3, [r7, #20] tmpreg |= huart->Init.OneBitSampling; - 80069b8: 687b ldr r3, [r7, #4] - 80069ba: 6a1b ldr r3, [r3, #32] - 80069bc: 697a ldr r2, [r7, #20] - 80069be: 4313 orrs r3, r2 - 80069c0: 617b str r3, [r7, #20] + 8006a54: 687b ldr r3, [r7, #4] + 8006a56: 6a1b ldr r3, [r3, #32] + 8006a58: 697a ldr r2, [r7, #20] + 8006a5a: 4313 orrs r3, r2 + 8006a5c: 617b str r3, [r7, #20] MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); - 80069c2: 687b ldr r3, [r7, #4] - 80069c4: 681b ldr r3, [r3, #0] - 80069c6: 689b ldr r3, [r3, #8] - 80069c8: f423 6130 bic.w r1, r3, #2816 @ 0xb00 - 80069cc: 687b ldr r3, [r7, #4] - 80069ce: 681b ldr r3, [r3, #0] - 80069d0: 697a ldr r2, [r7, #20] - 80069d2: 430a orrs r2, r1 - 80069d4: 609a str r2, [r3, #8] + 8006a5e: 687b ldr r3, [r7, #4] + 8006a60: 681b ldr r3, [r3, #0] + 8006a62: 689b ldr r3, [r3, #8] + 8006a64: f423 6130 bic.w r1, r3, #2816 @ 0xb00 + 8006a68: 687b ldr r3, [r7, #4] + 8006a6a: 681b ldr r3, [r3, #0] + 8006a6c: 697a ldr r2, [r7, #20] + 8006a6e: 430a orrs r2, r1 + 8006a70: 609a str r2, [r3, #8] /*-------------------------- USART BRR Configuration -----------------------*/ UART_GETCLOCKSOURCE(huart, clocksource); - 80069d6: 687b ldr r3, [r7, #4] - 80069d8: 681b ldr r3, [r3, #0] - 80069da: 4aa7 ldr r2, [pc, #668] @ (8006c78 ) - 80069dc: 4293 cmp r3, r2 - 80069de: d120 bne.n 8006a22 - 80069e0: 4ba6 ldr r3, [pc, #664] @ (8006c7c ) - 80069e2: 6b1b ldr r3, [r3, #48] @ 0x30 - 80069e4: f003 0303 and.w r3, r3, #3 - 80069e8: 2b03 cmp r3, #3 - 80069ea: d817 bhi.n 8006a1c - 80069ec: a201 add r2, pc, #4 @ (adr r2, 80069f4 ) - 80069ee: f852 f023 ldr.w pc, [r2, r3, lsl #2] - 80069f2: bf00 nop - 80069f4: 08006a05 .word 0x08006a05 - 80069f8: 08006a11 .word 0x08006a11 - 80069fc: 08006a17 .word 0x08006a17 - 8006a00: 08006a0b .word 0x08006a0b - 8006a04: 2301 movs r3, #1 - 8006a06: 77fb strb r3, [r7, #31] - 8006a08: e0b5 b.n 8006b76 - 8006a0a: 2302 movs r3, #2 - 8006a0c: 77fb strb r3, [r7, #31] - 8006a0e: e0b2 b.n 8006b76 - 8006a10: 2304 movs r3, #4 - 8006a12: 77fb strb r3, [r7, #31] - 8006a14: e0af b.n 8006b76 - 8006a16: 2308 movs r3, #8 - 8006a18: 77fb strb r3, [r7, #31] - 8006a1a: e0ac b.n 8006b76 - 8006a1c: 2310 movs r3, #16 - 8006a1e: 77fb strb r3, [r7, #31] - 8006a20: e0a9 b.n 8006b76 - 8006a22: 687b ldr r3, [r7, #4] - 8006a24: 681b ldr r3, [r3, #0] - 8006a26: 4a96 ldr r2, [pc, #600] @ (8006c80 ) - 8006a28: 4293 cmp r3, r2 - 8006a2a: d124 bne.n 8006a76 - 8006a2c: 4b93 ldr r3, [pc, #588] @ (8006c7c ) - 8006a2e: 6b1b ldr r3, [r3, #48] @ 0x30 - 8006a30: f403 3340 and.w r3, r3, #196608 @ 0x30000 - 8006a34: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 - 8006a38: d011 beq.n 8006a5e - 8006a3a: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 - 8006a3e: d817 bhi.n 8006a70 - 8006a40: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 - 8006a44: d011 beq.n 8006a6a - 8006a46: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 - 8006a4a: d811 bhi.n 8006a70 - 8006a4c: 2b00 cmp r3, #0 - 8006a4e: d003 beq.n 8006a58 - 8006a50: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 - 8006a54: d006 beq.n 8006a64 - 8006a56: e00b b.n 8006a70 - 8006a58: 2300 movs r3, #0 - 8006a5a: 77fb strb r3, [r7, #31] - 8006a5c: e08b b.n 8006b76 - 8006a5e: 2302 movs r3, #2 - 8006a60: 77fb strb r3, [r7, #31] - 8006a62: e088 b.n 8006b76 - 8006a64: 2304 movs r3, #4 - 8006a66: 77fb strb r3, [r7, #31] - 8006a68: e085 b.n 8006b76 - 8006a6a: 2308 movs r3, #8 - 8006a6c: 77fb strb r3, [r7, #31] - 8006a6e: e082 b.n 8006b76 - 8006a70: 2310 movs r3, #16 - 8006a72: 77fb strb r3, [r7, #31] - 8006a74: e07f b.n 8006b76 - 8006a76: 687b ldr r3, [r7, #4] - 8006a78: 681b ldr r3, [r3, #0] - 8006a7a: 4a82 ldr r2, [pc, #520] @ (8006c84 ) - 8006a7c: 4293 cmp r3, r2 - 8006a7e: d124 bne.n 8006aca - 8006a80: 4b7e ldr r3, [pc, #504] @ (8006c7c ) - 8006a82: 6b1b ldr r3, [r3, #48] @ 0x30 - 8006a84: f403 2340 and.w r3, r3, #786432 @ 0xc0000 - 8006a88: f5b3 2f40 cmp.w r3, #786432 @ 0xc0000 - 8006a8c: d011 beq.n 8006ab2 - 8006a8e: f5b3 2f40 cmp.w r3, #786432 @ 0xc0000 - 8006a92: d817 bhi.n 8006ac4 - 8006a94: f5b3 2f00 cmp.w r3, #524288 @ 0x80000 - 8006a98: d011 beq.n 8006abe - 8006a9a: f5b3 2f00 cmp.w r3, #524288 @ 0x80000 - 8006a9e: d811 bhi.n 8006ac4 - 8006aa0: 2b00 cmp r3, #0 - 8006aa2: d003 beq.n 8006aac - 8006aa4: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 - 8006aa8: d006 beq.n 8006ab8 - 8006aaa: e00b b.n 8006ac4 - 8006aac: 2300 movs r3, #0 + 8006a72: 687b ldr r3, [r7, #4] + 8006a74: 681b ldr r3, [r3, #0] + 8006a76: 4aa7 ldr r2, [pc, #668] @ (8006d14 ) + 8006a78: 4293 cmp r3, r2 + 8006a7a: d120 bne.n 8006abe + 8006a7c: 4ba6 ldr r3, [pc, #664] @ (8006d18 ) + 8006a7e: 6b1b ldr r3, [r3, #48] @ 0x30 + 8006a80: f003 0303 and.w r3, r3, #3 + 8006a84: 2b03 cmp r3, #3 + 8006a86: d817 bhi.n 8006ab8 + 8006a88: a201 add r2, pc, #4 @ (adr r2, 8006a90 ) + 8006a8a: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8006a8e: bf00 nop + 8006a90: 08006aa1 .word 0x08006aa1 + 8006a94: 08006aad .word 0x08006aad + 8006a98: 08006ab3 .word 0x08006ab3 + 8006a9c: 08006aa7 .word 0x08006aa7 + 8006aa0: 2301 movs r3, #1 + 8006aa2: 77fb strb r3, [r7, #31] + 8006aa4: e0b5 b.n 8006c12 + 8006aa6: 2302 movs r3, #2 + 8006aa8: 77fb strb r3, [r7, #31] + 8006aaa: e0b2 b.n 8006c12 + 8006aac: 2304 movs r3, #4 8006aae: 77fb strb r3, [r7, #31] - 8006ab0: e061 b.n 8006b76 - 8006ab2: 2302 movs r3, #2 + 8006ab0: e0af b.n 8006c12 + 8006ab2: 2308 movs r3, #8 8006ab4: 77fb strb r3, [r7, #31] - 8006ab6: e05e b.n 8006b76 - 8006ab8: 2304 movs r3, #4 + 8006ab6: e0ac b.n 8006c12 + 8006ab8: 2310 movs r3, #16 8006aba: 77fb strb r3, [r7, #31] - 8006abc: e05b b.n 8006b76 - 8006abe: 2308 movs r3, #8 - 8006ac0: 77fb strb r3, [r7, #31] - 8006ac2: e058 b.n 8006b76 - 8006ac4: 2310 movs r3, #16 - 8006ac6: 77fb strb r3, [r7, #31] - 8006ac8: e055 b.n 8006b76 - 8006aca: 687b ldr r3, [r7, #4] - 8006acc: 681b ldr r3, [r3, #0] - 8006ace: 4a6e ldr r2, [pc, #440] @ (8006c88 ) - 8006ad0: 4293 cmp r3, r2 - 8006ad2: d124 bne.n 8006b1e - 8006ad4: 4b69 ldr r3, [pc, #420] @ (8006c7c ) - 8006ad6: 6b1b ldr r3, [r3, #48] @ 0x30 - 8006ad8: f403 1340 and.w r3, r3, #3145728 @ 0x300000 - 8006adc: f5b3 1f40 cmp.w r3, #3145728 @ 0x300000 - 8006ae0: d011 beq.n 8006b06 - 8006ae2: f5b3 1f40 cmp.w r3, #3145728 @ 0x300000 - 8006ae6: d817 bhi.n 8006b18 - 8006ae8: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 - 8006aec: d011 beq.n 8006b12 - 8006aee: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 - 8006af2: d811 bhi.n 8006b18 - 8006af4: 2b00 cmp r3, #0 - 8006af6: d003 beq.n 8006b00 - 8006af8: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 - 8006afc: d006 beq.n 8006b0c - 8006afe: e00b b.n 8006b18 - 8006b00: 2300 movs r3, #0 + 8006abc: e0a9 b.n 8006c12 + 8006abe: 687b ldr r3, [r7, #4] + 8006ac0: 681b ldr r3, [r3, #0] + 8006ac2: 4a96 ldr r2, [pc, #600] @ (8006d1c ) + 8006ac4: 4293 cmp r3, r2 + 8006ac6: d124 bne.n 8006b12 + 8006ac8: 4b93 ldr r3, [pc, #588] @ (8006d18 ) + 8006aca: 6b1b ldr r3, [r3, #48] @ 0x30 + 8006acc: f403 3340 and.w r3, r3, #196608 @ 0x30000 + 8006ad0: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 + 8006ad4: d011 beq.n 8006afa + 8006ad6: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 + 8006ada: d817 bhi.n 8006b0c + 8006adc: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 + 8006ae0: d011 beq.n 8006b06 + 8006ae2: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 + 8006ae6: d811 bhi.n 8006b0c + 8006ae8: 2b00 cmp r3, #0 + 8006aea: d003 beq.n 8006af4 + 8006aec: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 + 8006af0: d006 beq.n 8006b00 + 8006af2: e00b b.n 8006b0c + 8006af4: 2300 movs r3, #0 + 8006af6: 77fb strb r3, [r7, #31] + 8006af8: e08b b.n 8006c12 + 8006afa: 2302 movs r3, #2 + 8006afc: 77fb strb r3, [r7, #31] + 8006afe: e088 b.n 8006c12 + 8006b00: 2304 movs r3, #4 8006b02: 77fb strb r3, [r7, #31] - 8006b04: e037 b.n 8006b76 - 8006b06: 2302 movs r3, #2 + 8006b04: e085 b.n 8006c12 + 8006b06: 2308 movs r3, #8 8006b08: 77fb strb r3, [r7, #31] - 8006b0a: e034 b.n 8006b76 - 8006b0c: 2304 movs r3, #4 + 8006b0a: e082 b.n 8006c12 + 8006b0c: 2310 movs r3, #16 8006b0e: 77fb strb r3, [r7, #31] - 8006b10: e031 b.n 8006b76 - 8006b12: 2308 movs r3, #8 - 8006b14: 77fb strb r3, [r7, #31] - 8006b16: e02e b.n 8006b76 - 8006b18: 2310 movs r3, #16 - 8006b1a: 77fb strb r3, [r7, #31] - 8006b1c: e02b b.n 8006b76 - 8006b1e: 687b ldr r3, [r7, #4] - 8006b20: 681b ldr r3, [r3, #0] - 8006b22: 4a5a ldr r2, [pc, #360] @ (8006c8c ) - 8006b24: 4293 cmp r3, r2 - 8006b26: d124 bne.n 8006b72 - 8006b28: 4b54 ldr r3, [pc, #336] @ (8006c7c ) - 8006b2a: 6b1b ldr r3, [r3, #48] @ 0x30 - 8006b2c: f403 0340 and.w r3, r3, #12582912 @ 0xc00000 - 8006b30: f5b3 0f40 cmp.w r3, #12582912 @ 0xc00000 - 8006b34: d011 beq.n 8006b5a - 8006b36: f5b3 0f40 cmp.w r3, #12582912 @ 0xc00000 - 8006b3a: d817 bhi.n 8006b6c - 8006b3c: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 - 8006b40: d011 beq.n 8006b66 - 8006b42: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 - 8006b46: d811 bhi.n 8006b6c - 8006b48: 2b00 cmp r3, #0 - 8006b4a: d003 beq.n 8006b54 - 8006b4c: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 - 8006b50: d006 beq.n 8006b60 - 8006b52: e00b b.n 8006b6c - 8006b54: 2300 movs r3, #0 + 8006b10: e07f b.n 8006c12 + 8006b12: 687b ldr r3, [r7, #4] + 8006b14: 681b ldr r3, [r3, #0] + 8006b16: 4a82 ldr r2, [pc, #520] @ (8006d20 ) + 8006b18: 4293 cmp r3, r2 + 8006b1a: d124 bne.n 8006b66 + 8006b1c: 4b7e ldr r3, [pc, #504] @ (8006d18 ) + 8006b1e: 6b1b ldr r3, [r3, #48] @ 0x30 + 8006b20: f403 2340 and.w r3, r3, #786432 @ 0xc0000 + 8006b24: f5b3 2f40 cmp.w r3, #786432 @ 0xc0000 + 8006b28: d011 beq.n 8006b4e + 8006b2a: f5b3 2f40 cmp.w r3, #786432 @ 0xc0000 + 8006b2e: d817 bhi.n 8006b60 + 8006b30: f5b3 2f00 cmp.w r3, #524288 @ 0x80000 + 8006b34: d011 beq.n 8006b5a + 8006b36: f5b3 2f00 cmp.w r3, #524288 @ 0x80000 + 8006b3a: d811 bhi.n 8006b60 + 8006b3c: 2b00 cmp r3, #0 + 8006b3e: d003 beq.n 8006b48 + 8006b40: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 + 8006b44: d006 beq.n 8006b54 + 8006b46: e00b b.n 8006b60 + 8006b48: 2300 movs r3, #0 + 8006b4a: 77fb strb r3, [r7, #31] + 8006b4c: e061 b.n 8006c12 + 8006b4e: 2302 movs r3, #2 + 8006b50: 77fb strb r3, [r7, #31] + 8006b52: e05e b.n 8006c12 + 8006b54: 2304 movs r3, #4 8006b56: 77fb strb r3, [r7, #31] - 8006b58: e00d b.n 8006b76 - 8006b5a: 2302 movs r3, #2 + 8006b58: e05b b.n 8006c12 + 8006b5a: 2308 movs r3, #8 8006b5c: 77fb strb r3, [r7, #31] - 8006b5e: e00a b.n 8006b76 - 8006b60: 2304 movs r3, #4 + 8006b5e: e058 b.n 8006c12 + 8006b60: 2310 movs r3, #16 8006b62: 77fb strb r3, [r7, #31] - 8006b64: e007 b.n 8006b76 - 8006b66: 2308 movs r3, #8 - 8006b68: 77fb strb r3, [r7, #31] - 8006b6a: e004 b.n 8006b76 - 8006b6c: 2310 movs r3, #16 - 8006b6e: 77fb strb r3, [r7, #31] - 8006b70: e001 b.n 8006b76 - 8006b72: 2310 movs r3, #16 - 8006b74: 77fb strb r3, [r7, #31] + 8006b64: e055 b.n 8006c12 + 8006b66: 687b ldr r3, [r7, #4] + 8006b68: 681b ldr r3, [r3, #0] + 8006b6a: 4a6e ldr r2, [pc, #440] @ (8006d24 ) + 8006b6c: 4293 cmp r3, r2 + 8006b6e: d124 bne.n 8006bba + 8006b70: 4b69 ldr r3, [pc, #420] @ (8006d18 ) + 8006b72: 6b1b ldr r3, [r3, #48] @ 0x30 + 8006b74: f403 1340 and.w r3, r3, #3145728 @ 0x300000 + 8006b78: f5b3 1f40 cmp.w r3, #3145728 @ 0x300000 + 8006b7c: d011 beq.n 8006ba2 + 8006b7e: f5b3 1f40 cmp.w r3, #3145728 @ 0x300000 + 8006b82: d817 bhi.n 8006bb4 + 8006b84: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 + 8006b88: d011 beq.n 8006bae + 8006b8a: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 + 8006b8e: d811 bhi.n 8006bb4 + 8006b90: 2b00 cmp r3, #0 + 8006b92: d003 beq.n 8006b9c + 8006b94: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 + 8006b98: d006 beq.n 8006ba8 + 8006b9a: e00b b.n 8006bb4 + 8006b9c: 2300 movs r3, #0 + 8006b9e: 77fb strb r3, [r7, #31] + 8006ba0: e037 b.n 8006c12 + 8006ba2: 2302 movs r3, #2 + 8006ba4: 77fb strb r3, [r7, #31] + 8006ba6: e034 b.n 8006c12 + 8006ba8: 2304 movs r3, #4 + 8006baa: 77fb strb r3, [r7, #31] + 8006bac: e031 b.n 8006c12 + 8006bae: 2308 movs r3, #8 + 8006bb0: 77fb strb r3, [r7, #31] + 8006bb2: e02e b.n 8006c12 + 8006bb4: 2310 movs r3, #16 + 8006bb6: 77fb strb r3, [r7, #31] + 8006bb8: e02b b.n 8006c12 + 8006bba: 687b ldr r3, [r7, #4] + 8006bbc: 681b ldr r3, [r3, #0] + 8006bbe: 4a5a ldr r2, [pc, #360] @ (8006d28 ) + 8006bc0: 4293 cmp r3, r2 + 8006bc2: d124 bne.n 8006c0e + 8006bc4: 4b54 ldr r3, [pc, #336] @ (8006d18 ) + 8006bc6: 6b1b ldr r3, [r3, #48] @ 0x30 + 8006bc8: f403 0340 and.w r3, r3, #12582912 @ 0xc00000 + 8006bcc: f5b3 0f40 cmp.w r3, #12582912 @ 0xc00000 + 8006bd0: d011 beq.n 8006bf6 + 8006bd2: f5b3 0f40 cmp.w r3, #12582912 @ 0xc00000 + 8006bd6: d817 bhi.n 8006c08 + 8006bd8: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 + 8006bdc: d011 beq.n 8006c02 + 8006bde: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 + 8006be2: d811 bhi.n 8006c08 + 8006be4: 2b00 cmp r3, #0 + 8006be6: d003 beq.n 8006bf0 + 8006be8: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 + 8006bec: d006 beq.n 8006bfc + 8006bee: e00b b.n 8006c08 + 8006bf0: 2300 movs r3, #0 + 8006bf2: 77fb strb r3, [r7, #31] + 8006bf4: e00d b.n 8006c12 + 8006bf6: 2302 movs r3, #2 + 8006bf8: 77fb strb r3, [r7, #31] + 8006bfa: e00a b.n 8006c12 + 8006bfc: 2304 movs r3, #4 + 8006bfe: 77fb strb r3, [r7, #31] + 8006c00: e007 b.n 8006c12 + 8006c02: 2308 movs r3, #8 + 8006c04: 77fb strb r3, [r7, #31] + 8006c06: e004 b.n 8006c12 + 8006c08: 2310 movs r3, #16 + 8006c0a: 77fb strb r3, [r7, #31] + 8006c0c: e001 b.n 8006c12 + 8006c0e: 2310 movs r3, #16 + 8006c10: 77fb strb r3, [r7, #31] if (huart->Init.OverSampling == UART_OVERSAMPLING_8) - 8006b76: 687b ldr r3, [r7, #4] - 8006b78: 69db ldr r3, [r3, #28] - 8006b7a: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 - 8006b7e: d15b bne.n 8006c38 + 8006c12: 687b ldr r3, [r7, #4] + 8006c14: 69db ldr r3, [r3, #28] + 8006c16: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 + 8006c1a: d15b bne.n 8006cd4 { switch (clocksource) - 8006b80: 7ffb ldrb r3, [r7, #31] - 8006b82: 2b08 cmp r3, #8 - 8006b84: d827 bhi.n 8006bd6 - 8006b86: a201 add r2, pc, #4 @ (adr r2, 8006b8c ) - 8006b88: f852 f023 ldr.w pc, [r2, r3, lsl #2] - 8006b8c: 08006bb1 .word 0x08006bb1 - 8006b90: 08006bb9 .word 0x08006bb9 - 8006b94: 08006bc1 .word 0x08006bc1 - 8006b98: 08006bd7 .word 0x08006bd7 - 8006b9c: 08006bc7 .word 0x08006bc7 - 8006ba0: 08006bd7 .word 0x08006bd7 - 8006ba4: 08006bd7 .word 0x08006bd7 - 8006ba8: 08006bd7 .word 0x08006bd7 - 8006bac: 08006bcf .word 0x08006bcf + 8006c1c: 7ffb ldrb r3, [r7, #31] + 8006c1e: 2b08 cmp r3, #8 + 8006c20: d827 bhi.n 8006c72 + 8006c22: a201 add r2, pc, #4 @ (adr r2, 8006c28 ) + 8006c24: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8006c28: 08006c4d .word 0x08006c4d + 8006c2c: 08006c55 .word 0x08006c55 + 8006c30: 08006c5d .word 0x08006c5d + 8006c34: 08006c73 .word 0x08006c73 + 8006c38: 08006c63 .word 0x08006c63 + 8006c3c: 08006c73 .word 0x08006c73 + 8006c40: 08006c73 .word 0x08006c73 + 8006c44: 08006c73 .word 0x08006c73 + 8006c48: 08006c6b .word 0x08006c6b { case UART_CLOCKSOURCE_PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); - 8006bb0: f7ff f9ac bl 8005f0c - 8006bb4: 61b8 str r0, [r7, #24] + 8006c4c: f7ff f9ac bl 8005fa8 + 8006c50: 61b8 str r0, [r7, #24] break; - 8006bb6: e013 b.n 8006be0 + 8006c52: e013 b.n 8006c7c case UART_CLOCKSOURCE_PCLK2: pclk = HAL_RCC_GetPCLK2Freq(); - 8006bb8: f7ff f9ca bl 8005f50 - 8006bbc: 61b8 str r0, [r7, #24] + 8006c54: f7ff f9ca bl 8005fec + 8006c58: 61b8 str r0, [r7, #24] break; - 8006bbe: e00f b.n 8006be0 + 8006c5a: e00f b.n 8006c7c case UART_CLOCKSOURCE_HSI: pclk = (uint32_t) HSI_VALUE; - 8006bc0: 4b33 ldr r3, [pc, #204] @ (8006c90 ) - 8006bc2: 61bb str r3, [r7, #24] + 8006c5c: 4b33 ldr r3, [pc, #204] @ (8006d2c ) + 8006c5e: 61bb str r3, [r7, #24] break; - 8006bc4: e00c b.n 8006be0 + 8006c60: e00c b.n 8006c7c case UART_CLOCKSOURCE_SYSCLK: pclk = HAL_RCC_GetSysClockFreq(); - 8006bc6: f7ff f93f bl 8005e48 - 8006bca: 61b8 str r0, [r7, #24] + 8006c62: f7ff f93f bl 8005ee4 + 8006c66: 61b8 str r0, [r7, #24] break; - 8006bcc: e008 b.n 8006be0 + 8006c68: e008 b.n 8006c7c case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; - 8006bce: f44f 4300 mov.w r3, #32768 @ 0x8000 - 8006bd2: 61bb str r3, [r7, #24] + 8006c6a: f44f 4300 mov.w r3, #32768 @ 0x8000 + 8006c6e: 61bb str r3, [r7, #24] break; - 8006bd4: e004 b.n 8006be0 + 8006c70: e004 b.n 8006c7c default: pclk = 0U; - 8006bd6: 2300 movs r3, #0 - 8006bd8: 61bb str r3, [r7, #24] + 8006c72: 2300 movs r3, #0 + 8006c74: 61bb str r3, [r7, #24] ret = HAL_ERROR; - 8006bda: 2301 movs r3, #1 - 8006bdc: 77bb strb r3, [r7, #30] + 8006c76: 2301 movs r3, #1 + 8006c78: 77bb strb r3, [r7, #30] break; - 8006bde: bf00 nop + 8006c7a: bf00 nop } /* USARTDIV must be greater than or equal to 0d16 */ if (pclk != 0U) - 8006be0: 69bb ldr r3, [r7, #24] - 8006be2: 2b00 cmp r3, #0 - 8006be4: f000 8082 beq.w 8006cec + 8006c7c: 69bb ldr r3, [r7, #24] + 8006c7e: 2b00 cmp r3, #0 + 8006c80: f000 8082 beq.w 8006d88 { usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate)); - 8006be8: 69bb ldr r3, [r7, #24] - 8006bea: 005a lsls r2, r3, #1 - 8006bec: 687b ldr r3, [r7, #4] - 8006bee: 685b ldr r3, [r3, #4] - 8006bf0: 085b lsrs r3, r3, #1 - 8006bf2: 441a add r2, r3 - 8006bf4: 687b ldr r3, [r7, #4] - 8006bf6: 685b ldr r3, [r3, #4] - 8006bf8: fbb2 f3f3 udiv r3, r2, r3 - 8006bfc: 613b str r3, [r7, #16] + 8006c84: 69bb ldr r3, [r7, #24] + 8006c86: 005a lsls r2, r3, #1 + 8006c88: 687b ldr r3, [r7, #4] + 8006c8a: 685b ldr r3, [r3, #4] + 8006c8c: 085b lsrs r3, r3, #1 + 8006c8e: 441a add r2, r3 + 8006c90: 687b ldr r3, [r7, #4] + 8006c92: 685b ldr r3, [r3, #4] + 8006c94: fbb2 f3f3 udiv r3, r2, r3 + 8006c98: 613b str r3, [r7, #16] if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) - 8006bfe: 693b ldr r3, [r7, #16] - 8006c00: 2b0f cmp r3, #15 - 8006c02: d916 bls.n 8006c32 - 8006c04: 693b ldr r3, [r7, #16] - 8006c06: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 - 8006c0a: d212 bcs.n 8006c32 + 8006c9a: 693b ldr r3, [r7, #16] + 8006c9c: 2b0f cmp r3, #15 + 8006c9e: d916 bls.n 8006cce + 8006ca0: 693b ldr r3, [r7, #16] + 8006ca2: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 + 8006ca6: d212 bcs.n 8006cce { brrtemp = (uint16_t)(usartdiv & 0xFFF0U); - 8006c0c: 693b ldr r3, [r7, #16] - 8006c0e: b29b uxth r3, r3 - 8006c10: f023 030f bic.w r3, r3, #15 - 8006c14: 81fb strh r3, [r7, #14] + 8006ca8: 693b ldr r3, [r7, #16] + 8006caa: b29b uxth r3, r3 + 8006cac: f023 030f bic.w r3, r3, #15 + 8006cb0: 81fb strh r3, [r7, #14] brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); - 8006c16: 693b ldr r3, [r7, #16] - 8006c18: 085b lsrs r3, r3, #1 - 8006c1a: b29b uxth r3, r3 - 8006c1c: f003 0307 and.w r3, r3, #7 - 8006c20: b29a uxth r2, r3 - 8006c22: 89fb ldrh r3, [r7, #14] - 8006c24: 4313 orrs r3, r2 - 8006c26: 81fb strh r3, [r7, #14] + 8006cb2: 693b ldr r3, [r7, #16] + 8006cb4: 085b lsrs r3, r3, #1 + 8006cb6: b29b uxth r3, r3 + 8006cb8: f003 0307 and.w r3, r3, #7 + 8006cbc: b29a uxth r2, r3 + 8006cbe: 89fb ldrh r3, [r7, #14] + 8006cc0: 4313 orrs r3, r2 + 8006cc2: 81fb strh r3, [r7, #14] huart->Instance->BRR = brrtemp; - 8006c28: 687b ldr r3, [r7, #4] - 8006c2a: 681b ldr r3, [r3, #0] - 8006c2c: 89fa ldrh r2, [r7, #14] - 8006c2e: 60da str r2, [r3, #12] - 8006c30: e05c b.n 8006cec + 8006cc4: 687b ldr r3, [r7, #4] + 8006cc6: 681b ldr r3, [r3, #0] + 8006cc8: 89fa ldrh r2, [r7, #14] + 8006cca: 60da str r2, [r3, #12] + 8006ccc: e05c b.n 8006d88 } else { ret = HAL_ERROR; - 8006c32: 2301 movs r3, #1 - 8006c34: 77bb strb r3, [r7, #30] - 8006c36: e059 b.n 8006cec + 8006cce: 2301 movs r3, #1 + 8006cd0: 77bb strb r3, [r7, #30] + 8006cd2: e059 b.n 8006d88 } } } else { switch (clocksource) - 8006c38: 7ffb ldrb r3, [r7, #31] - 8006c3a: 2b08 cmp r3, #8 - 8006c3c: d835 bhi.n 8006caa - 8006c3e: a201 add r2, pc, #4 @ (adr r2, 8006c44 ) - 8006c40: f852 f023 ldr.w pc, [r2, r3, lsl #2] - 8006c44: 08006c69 .word 0x08006c69 - 8006c48: 08006c71 .word 0x08006c71 - 8006c4c: 08006c95 .word 0x08006c95 - 8006c50: 08006cab .word 0x08006cab - 8006c54: 08006c9b .word 0x08006c9b - 8006c58: 08006cab .word 0x08006cab - 8006c5c: 08006cab .word 0x08006cab - 8006c60: 08006cab .word 0x08006cab - 8006c64: 08006ca3 .word 0x08006ca3 + 8006cd4: 7ffb ldrb r3, [r7, #31] + 8006cd6: 2b08 cmp r3, #8 + 8006cd8: d835 bhi.n 8006d46 + 8006cda: a201 add r2, pc, #4 @ (adr r2, 8006ce0 ) + 8006cdc: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8006ce0: 08006d05 .word 0x08006d05 + 8006ce4: 08006d0d .word 0x08006d0d + 8006ce8: 08006d31 .word 0x08006d31 + 8006cec: 08006d47 .word 0x08006d47 + 8006cf0: 08006d37 .word 0x08006d37 + 8006cf4: 08006d47 .word 0x08006d47 + 8006cf8: 08006d47 .word 0x08006d47 + 8006cfc: 08006d47 .word 0x08006d47 + 8006d00: 08006d3f .word 0x08006d3f { case UART_CLOCKSOURCE_PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); - 8006c68: f7ff f950 bl 8005f0c - 8006c6c: 61b8 str r0, [r7, #24] + 8006d04: f7ff f950 bl 8005fa8 + 8006d08: 61b8 str r0, [r7, #24] break; - 8006c6e: e021 b.n 8006cb4 + 8006d0a: e021 b.n 8006d50 case UART_CLOCKSOURCE_PCLK2: pclk = HAL_RCC_GetPCLK2Freq(); - 8006c70: f7ff f96e bl 8005f50 - 8006c74: 61b8 str r0, [r7, #24] + 8006d0c: f7ff f96e bl 8005fec + 8006d10: 61b8 str r0, [r7, #24] break; - 8006c76: e01d b.n 8006cb4 - 8006c78: 40013800 .word 0x40013800 - 8006c7c: 40021000 .word 0x40021000 - 8006c80: 40004400 .word 0x40004400 - 8006c84: 40004800 .word 0x40004800 - 8006c88: 40004c00 .word 0x40004c00 - 8006c8c: 40005000 .word 0x40005000 - 8006c90: 007a1200 .word 0x007a1200 + 8006d12: e01d b.n 8006d50 + 8006d14: 40013800 .word 0x40013800 + 8006d18: 40021000 .word 0x40021000 + 8006d1c: 40004400 .word 0x40004400 + 8006d20: 40004800 .word 0x40004800 + 8006d24: 40004c00 .word 0x40004c00 + 8006d28: 40005000 .word 0x40005000 + 8006d2c: 007a1200 .word 0x007a1200 case UART_CLOCKSOURCE_HSI: pclk = (uint32_t) HSI_VALUE; - 8006c94: 4b1b ldr r3, [pc, #108] @ (8006d04 ) - 8006c96: 61bb str r3, [r7, #24] + 8006d30: 4b1b ldr r3, [pc, #108] @ (8006da0 ) + 8006d32: 61bb str r3, [r7, #24] break; - 8006c98: e00c b.n 8006cb4 + 8006d34: e00c b.n 8006d50 case UART_CLOCKSOURCE_SYSCLK: pclk = HAL_RCC_GetSysClockFreq(); - 8006c9a: f7ff f8d5 bl 8005e48 - 8006c9e: 61b8 str r0, [r7, #24] + 8006d36: f7ff f8d5 bl 8005ee4 + 8006d3a: 61b8 str r0, [r7, #24] break; - 8006ca0: e008 b.n 8006cb4 + 8006d3c: e008 b.n 8006d50 case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; - 8006ca2: f44f 4300 mov.w r3, #32768 @ 0x8000 - 8006ca6: 61bb str r3, [r7, #24] + 8006d3e: f44f 4300 mov.w r3, #32768 @ 0x8000 + 8006d42: 61bb str r3, [r7, #24] break; - 8006ca8: e004 b.n 8006cb4 + 8006d44: e004 b.n 8006d50 default: pclk = 0U; - 8006caa: 2300 movs r3, #0 - 8006cac: 61bb str r3, [r7, #24] + 8006d46: 2300 movs r3, #0 + 8006d48: 61bb str r3, [r7, #24] ret = HAL_ERROR; - 8006cae: 2301 movs r3, #1 - 8006cb0: 77bb strb r3, [r7, #30] + 8006d4a: 2301 movs r3, #1 + 8006d4c: 77bb strb r3, [r7, #30] break; - 8006cb2: bf00 nop + 8006d4e: bf00 nop } if (pclk != 0U) - 8006cb4: 69bb ldr r3, [r7, #24] - 8006cb6: 2b00 cmp r3, #0 - 8006cb8: d018 beq.n 8006cec + 8006d50: 69bb ldr r3, [r7, #24] + 8006d52: 2b00 cmp r3, #0 + 8006d54: d018 beq.n 8006d88 { /* USARTDIV must be greater than or equal to 0d16 */ usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate)); - 8006cba: 687b ldr r3, [r7, #4] - 8006cbc: 685b ldr r3, [r3, #4] - 8006cbe: 085a lsrs r2, r3, #1 - 8006cc0: 69bb ldr r3, [r7, #24] - 8006cc2: 441a add r2, r3 - 8006cc4: 687b ldr r3, [r7, #4] - 8006cc6: 685b ldr r3, [r3, #4] - 8006cc8: fbb2 f3f3 udiv r3, r2, r3 - 8006ccc: 613b str r3, [r7, #16] + 8006d56: 687b ldr r3, [r7, #4] + 8006d58: 685b ldr r3, [r3, #4] + 8006d5a: 085a lsrs r2, r3, #1 + 8006d5c: 69bb ldr r3, [r7, #24] + 8006d5e: 441a add r2, r3 + 8006d60: 687b ldr r3, [r7, #4] + 8006d62: 685b ldr r3, [r3, #4] + 8006d64: fbb2 f3f3 udiv r3, r2, r3 + 8006d68: 613b str r3, [r7, #16] if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) - 8006cce: 693b ldr r3, [r7, #16] - 8006cd0: 2b0f cmp r3, #15 - 8006cd2: d909 bls.n 8006ce8 - 8006cd4: 693b ldr r3, [r7, #16] - 8006cd6: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 - 8006cda: d205 bcs.n 8006ce8 + 8006d6a: 693b ldr r3, [r7, #16] + 8006d6c: 2b0f cmp r3, #15 + 8006d6e: d909 bls.n 8006d84 + 8006d70: 693b ldr r3, [r7, #16] + 8006d72: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 + 8006d76: d205 bcs.n 8006d84 { huart->Instance->BRR = (uint16_t)usartdiv; - 8006cdc: 693b ldr r3, [r7, #16] - 8006cde: b29a uxth r2, r3 - 8006ce0: 687b ldr r3, [r7, #4] - 8006ce2: 681b ldr r3, [r3, #0] - 8006ce4: 60da str r2, [r3, #12] - 8006ce6: e001 b.n 8006cec + 8006d78: 693b ldr r3, [r7, #16] + 8006d7a: b29a uxth r2, r3 + 8006d7c: 687b ldr r3, [r7, #4] + 8006d7e: 681b ldr r3, [r3, #0] + 8006d80: 60da str r2, [r3, #12] + 8006d82: e001 b.n 8006d88 } else { ret = HAL_ERROR; - 8006ce8: 2301 movs r3, #1 - 8006cea: 77bb strb r3, [r7, #30] + 8006d84: 2301 movs r3, #1 + 8006d86: 77bb strb r3, [r7, #30] } } /* Clear ISR function pointers */ huart->RxISR = NULL; - 8006cec: 687b ldr r3, [r7, #4] - 8006cee: 2200 movs r2, #0 - 8006cf0: 669a str r2, [r3, #104] @ 0x68 + 8006d88: 687b ldr r3, [r7, #4] + 8006d8a: 2200 movs r2, #0 + 8006d8c: 669a str r2, [r3, #104] @ 0x68 huart->TxISR = NULL; - 8006cf2: 687b ldr r3, [r7, #4] - 8006cf4: 2200 movs r2, #0 - 8006cf6: 66da str r2, [r3, #108] @ 0x6c + 8006d8e: 687b ldr r3, [r7, #4] + 8006d90: 2200 movs r2, #0 + 8006d92: 66da str r2, [r3, #108] @ 0x6c return ret; - 8006cf8: 7fbb ldrb r3, [r7, #30] + 8006d94: 7fbb ldrb r3, [r7, #30] } - 8006cfa: 4618 mov r0, r3 - 8006cfc: 3720 adds r7, #32 - 8006cfe: 46bd mov sp, r7 - 8006d00: bd80 pop {r7, pc} - 8006d02: bf00 nop - 8006d04: 007a1200 .word 0x007a1200 + 8006d96: 4618 mov r0, r3 + 8006d98: 3720 adds r7, #32 + 8006d9a: 46bd mov sp, r7 + 8006d9c: bd80 pop {r7, pc} + 8006d9e: bf00 nop + 8006da0: 007a1200 .word 0x007a1200 -08006d08 : +08006da4 : * @brief Configure the UART peripheral advanced features. * @param huart UART handle. * @retval None */ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) { - 8006d08: b480 push {r7} - 8006d0a: b083 sub sp, #12 - 8006d0c: af00 add r7, sp, #0 - 8006d0e: 6078 str r0, [r7, #4] + 8006da4: b480 push {r7} + 8006da6: b083 sub sp, #12 + 8006da8: af00 add r7, sp, #0 + 8006daa: 6078 str r0, [r7, #4] /* Check whether the set of advanced features to configure is properly set */ assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); /* if required, configure RX/TX pins swap */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) - 8006d10: 687b ldr r3, [r7, #4] - 8006d12: 6a5b ldr r3, [r3, #36] @ 0x24 - 8006d14: f003 0308 and.w r3, r3, #8 - 8006d18: 2b00 cmp r3, #0 - 8006d1a: d00a beq.n 8006d32 + 8006dac: 687b ldr r3, [r7, #4] + 8006dae: 6a5b ldr r3, [r3, #36] @ 0x24 + 8006db0: f003 0308 and.w r3, r3, #8 + 8006db4: 2b00 cmp r3, #0 + 8006db6: d00a beq.n 8006dce { assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); - 8006d1c: 687b ldr r3, [r7, #4] - 8006d1e: 681b ldr r3, [r3, #0] - 8006d20: 685b ldr r3, [r3, #4] - 8006d22: f423 4100 bic.w r1, r3, #32768 @ 0x8000 - 8006d26: 687b ldr r3, [r7, #4] - 8006d28: 6b5a ldr r2, [r3, #52] @ 0x34 - 8006d2a: 687b ldr r3, [r7, #4] - 8006d2c: 681b ldr r3, [r3, #0] - 8006d2e: 430a orrs r2, r1 - 8006d30: 605a str r2, [r3, #4] + 8006db8: 687b ldr r3, [r7, #4] + 8006dba: 681b ldr r3, [r3, #0] + 8006dbc: 685b ldr r3, [r3, #4] + 8006dbe: f423 4100 bic.w r1, r3, #32768 @ 0x8000 + 8006dc2: 687b ldr r3, [r7, #4] + 8006dc4: 6b5a ldr r2, [r3, #52] @ 0x34 + 8006dc6: 687b ldr r3, [r7, #4] + 8006dc8: 681b ldr r3, [r3, #0] + 8006dca: 430a orrs r2, r1 + 8006dcc: 605a str r2, [r3, #4] } /* if required, configure TX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) - 8006d32: 687b ldr r3, [r7, #4] - 8006d34: 6a5b ldr r3, [r3, #36] @ 0x24 - 8006d36: f003 0301 and.w r3, r3, #1 - 8006d3a: 2b00 cmp r3, #0 - 8006d3c: d00a beq.n 8006d54 + 8006dce: 687b ldr r3, [r7, #4] + 8006dd0: 6a5b ldr r3, [r3, #36] @ 0x24 + 8006dd2: f003 0301 and.w r3, r3, #1 + 8006dd6: 2b00 cmp r3, #0 + 8006dd8: d00a beq.n 8006df0 { assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); - 8006d3e: 687b ldr r3, [r7, #4] - 8006d40: 681b ldr r3, [r3, #0] - 8006d42: 685b ldr r3, [r3, #4] - 8006d44: f423 3100 bic.w r1, r3, #131072 @ 0x20000 - 8006d48: 687b ldr r3, [r7, #4] - 8006d4a: 6a9a ldr r2, [r3, #40] @ 0x28 - 8006d4c: 687b ldr r3, [r7, #4] - 8006d4e: 681b ldr r3, [r3, #0] - 8006d50: 430a orrs r2, r1 - 8006d52: 605a str r2, [r3, #4] + 8006dda: 687b ldr r3, [r7, #4] + 8006ddc: 681b ldr r3, [r3, #0] + 8006dde: 685b ldr r3, [r3, #4] + 8006de0: f423 3100 bic.w r1, r3, #131072 @ 0x20000 + 8006de4: 687b ldr r3, [r7, #4] + 8006de6: 6a9a ldr r2, [r3, #40] @ 0x28 + 8006de8: 687b ldr r3, [r7, #4] + 8006dea: 681b ldr r3, [r3, #0] + 8006dec: 430a orrs r2, r1 + 8006dee: 605a str r2, [r3, #4] } /* if required, configure RX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) - 8006d54: 687b ldr r3, [r7, #4] - 8006d56: 6a5b ldr r3, [r3, #36] @ 0x24 - 8006d58: f003 0302 and.w r3, r3, #2 - 8006d5c: 2b00 cmp r3, #0 - 8006d5e: d00a beq.n 8006d76 + 8006df0: 687b ldr r3, [r7, #4] + 8006df2: 6a5b ldr r3, [r3, #36] @ 0x24 + 8006df4: f003 0302 and.w r3, r3, #2 + 8006df8: 2b00 cmp r3, #0 + 8006dfa: d00a beq.n 8006e12 { assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); - 8006d60: 687b ldr r3, [r7, #4] - 8006d62: 681b ldr r3, [r3, #0] - 8006d64: 685b ldr r3, [r3, #4] - 8006d66: f423 3180 bic.w r1, r3, #65536 @ 0x10000 - 8006d6a: 687b ldr r3, [r7, #4] - 8006d6c: 6ada ldr r2, [r3, #44] @ 0x2c - 8006d6e: 687b ldr r3, [r7, #4] - 8006d70: 681b ldr r3, [r3, #0] - 8006d72: 430a orrs r2, r1 - 8006d74: 605a str r2, [r3, #4] + 8006dfc: 687b ldr r3, [r7, #4] + 8006dfe: 681b ldr r3, [r3, #0] + 8006e00: 685b ldr r3, [r3, #4] + 8006e02: f423 3180 bic.w r1, r3, #65536 @ 0x10000 + 8006e06: 687b ldr r3, [r7, #4] + 8006e08: 6ada ldr r2, [r3, #44] @ 0x2c + 8006e0a: 687b ldr r3, [r7, #4] + 8006e0c: 681b ldr r3, [r3, #0] + 8006e0e: 430a orrs r2, r1 + 8006e10: 605a str r2, [r3, #4] } /* if required, configure data inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) - 8006d76: 687b ldr r3, [r7, #4] - 8006d78: 6a5b ldr r3, [r3, #36] @ 0x24 - 8006d7a: f003 0304 and.w r3, r3, #4 - 8006d7e: 2b00 cmp r3, #0 - 8006d80: d00a beq.n 8006d98 + 8006e12: 687b ldr r3, [r7, #4] + 8006e14: 6a5b ldr r3, [r3, #36] @ 0x24 + 8006e16: f003 0304 and.w r3, r3, #4 + 8006e1a: 2b00 cmp r3, #0 + 8006e1c: d00a beq.n 8006e34 { assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); - 8006d82: 687b ldr r3, [r7, #4] - 8006d84: 681b ldr r3, [r3, #0] - 8006d86: 685b ldr r3, [r3, #4] - 8006d88: f423 2180 bic.w r1, r3, #262144 @ 0x40000 - 8006d8c: 687b ldr r3, [r7, #4] - 8006d8e: 6b1a ldr r2, [r3, #48] @ 0x30 - 8006d90: 687b ldr r3, [r7, #4] - 8006d92: 681b ldr r3, [r3, #0] - 8006d94: 430a orrs r2, r1 - 8006d96: 605a str r2, [r3, #4] + 8006e1e: 687b ldr r3, [r7, #4] + 8006e20: 681b ldr r3, [r3, #0] + 8006e22: 685b ldr r3, [r3, #4] + 8006e24: f423 2180 bic.w r1, r3, #262144 @ 0x40000 + 8006e28: 687b ldr r3, [r7, #4] + 8006e2a: 6b1a ldr r2, [r3, #48] @ 0x30 + 8006e2c: 687b ldr r3, [r7, #4] + 8006e2e: 681b ldr r3, [r3, #0] + 8006e30: 430a orrs r2, r1 + 8006e32: 605a str r2, [r3, #4] } /* if required, configure RX overrun detection disabling */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) - 8006d98: 687b ldr r3, [r7, #4] - 8006d9a: 6a5b ldr r3, [r3, #36] @ 0x24 - 8006d9c: f003 0310 and.w r3, r3, #16 - 8006da0: 2b00 cmp r3, #0 - 8006da2: d00a beq.n 8006dba + 8006e34: 687b ldr r3, [r7, #4] + 8006e36: 6a5b ldr r3, [r3, #36] @ 0x24 + 8006e38: f003 0310 and.w r3, r3, #16 + 8006e3c: 2b00 cmp r3, #0 + 8006e3e: d00a beq.n 8006e56 { assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); - 8006da4: 687b ldr r3, [r7, #4] - 8006da6: 681b ldr r3, [r3, #0] - 8006da8: 689b ldr r3, [r3, #8] - 8006daa: f423 5180 bic.w r1, r3, #4096 @ 0x1000 - 8006dae: 687b ldr r3, [r7, #4] - 8006db0: 6b9a ldr r2, [r3, #56] @ 0x38 - 8006db2: 687b ldr r3, [r7, #4] - 8006db4: 681b ldr r3, [r3, #0] - 8006db6: 430a orrs r2, r1 - 8006db8: 609a str r2, [r3, #8] + 8006e40: 687b ldr r3, [r7, #4] + 8006e42: 681b ldr r3, [r3, #0] + 8006e44: 689b ldr r3, [r3, #8] + 8006e46: f423 5180 bic.w r1, r3, #4096 @ 0x1000 + 8006e4a: 687b ldr r3, [r7, #4] + 8006e4c: 6b9a ldr r2, [r3, #56] @ 0x38 + 8006e4e: 687b ldr r3, [r7, #4] + 8006e50: 681b ldr r3, [r3, #0] + 8006e52: 430a orrs r2, r1 + 8006e54: 609a str r2, [r3, #8] } /* if required, configure DMA disabling on reception error */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) - 8006dba: 687b ldr r3, [r7, #4] - 8006dbc: 6a5b ldr r3, [r3, #36] @ 0x24 - 8006dbe: f003 0320 and.w r3, r3, #32 - 8006dc2: 2b00 cmp r3, #0 - 8006dc4: d00a beq.n 8006ddc + 8006e56: 687b ldr r3, [r7, #4] + 8006e58: 6a5b ldr r3, [r3, #36] @ 0x24 + 8006e5a: f003 0320 and.w r3, r3, #32 + 8006e5e: 2b00 cmp r3, #0 + 8006e60: d00a beq.n 8006e78 { assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); - 8006dc6: 687b ldr r3, [r7, #4] - 8006dc8: 681b ldr r3, [r3, #0] - 8006dca: 689b ldr r3, [r3, #8] - 8006dcc: f423 5100 bic.w r1, r3, #8192 @ 0x2000 - 8006dd0: 687b ldr r3, [r7, #4] - 8006dd2: 6bda ldr r2, [r3, #60] @ 0x3c - 8006dd4: 687b ldr r3, [r7, #4] - 8006dd6: 681b ldr r3, [r3, #0] - 8006dd8: 430a orrs r2, r1 - 8006dda: 609a str r2, [r3, #8] + 8006e62: 687b ldr r3, [r7, #4] + 8006e64: 681b ldr r3, [r3, #0] + 8006e66: 689b ldr r3, [r3, #8] + 8006e68: f423 5100 bic.w r1, r3, #8192 @ 0x2000 + 8006e6c: 687b ldr r3, [r7, #4] + 8006e6e: 6bda ldr r2, [r3, #60] @ 0x3c + 8006e70: 687b ldr r3, [r7, #4] + 8006e72: 681b ldr r3, [r3, #0] + 8006e74: 430a orrs r2, r1 + 8006e76: 609a str r2, [r3, #8] } /* if required, configure auto Baud rate detection scheme */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) - 8006ddc: 687b ldr r3, [r7, #4] - 8006dde: 6a5b ldr r3, [r3, #36] @ 0x24 - 8006de0: f003 0340 and.w r3, r3, #64 @ 0x40 - 8006de4: 2b00 cmp r3, #0 - 8006de6: d01a beq.n 8006e1e + 8006e78: 687b ldr r3, [r7, #4] + 8006e7a: 6a5b ldr r3, [r3, #36] @ 0x24 + 8006e7c: f003 0340 and.w r3, r3, #64 @ 0x40 + 8006e80: 2b00 cmp r3, #0 + 8006e82: d01a beq.n 8006eba { assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance)); assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); - 8006de8: 687b ldr r3, [r7, #4] - 8006dea: 681b ldr r3, [r3, #0] - 8006dec: 685b ldr r3, [r3, #4] - 8006dee: f423 1180 bic.w r1, r3, #1048576 @ 0x100000 - 8006df2: 687b ldr r3, [r7, #4] - 8006df4: 6c1a ldr r2, [r3, #64] @ 0x40 - 8006df6: 687b ldr r3, [r7, #4] - 8006df8: 681b ldr r3, [r3, #0] - 8006dfa: 430a orrs r2, r1 - 8006dfc: 605a str r2, [r3, #4] + 8006e84: 687b ldr r3, [r7, #4] + 8006e86: 681b ldr r3, [r3, #0] + 8006e88: 685b ldr r3, [r3, #4] + 8006e8a: f423 1180 bic.w r1, r3, #1048576 @ 0x100000 + 8006e8e: 687b ldr r3, [r7, #4] + 8006e90: 6c1a ldr r2, [r3, #64] @ 0x40 + 8006e92: 687b ldr r3, [r7, #4] + 8006e94: 681b ldr r3, [r3, #0] + 8006e96: 430a orrs r2, r1 + 8006e98: 605a str r2, [r3, #4] /* set auto Baudrate detection parameters if detection is enabled */ if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) - 8006dfe: 687b ldr r3, [r7, #4] - 8006e00: 6c1b ldr r3, [r3, #64] @ 0x40 - 8006e02: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 - 8006e06: d10a bne.n 8006e1e + 8006e9a: 687b ldr r3, [r7, #4] + 8006e9c: 6c1b ldr r3, [r3, #64] @ 0x40 + 8006e9e: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 + 8006ea2: d10a bne.n 8006eba { assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); - 8006e08: 687b ldr r3, [r7, #4] - 8006e0a: 681b ldr r3, [r3, #0] - 8006e0c: 685b ldr r3, [r3, #4] - 8006e0e: f423 01c0 bic.w r1, r3, #6291456 @ 0x600000 - 8006e12: 687b ldr r3, [r7, #4] - 8006e14: 6c5a ldr r2, [r3, #68] @ 0x44 - 8006e16: 687b ldr r3, [r7, #4] - 8006e18: 681b ldr r3, [r3, #0] - 8006e1a: 430a orrs r2, r1 - 8006e1c: 605a str r2, [r3, #4] + 8006ea4: 687b ldr r3, [r7, #4] + 8006ea6: 681b ldr r3, [r3, #0] + 8006ea8: 685b ldr r3, [r3, #4] + 8006eaa: f423 01c0 bic.w r1, r3, #6291456 @ 0x600000 + 8006eae: 687b ldr r3, [r7, #4] + 8006eb0: 6c5a ldr r2, [r3, #68] @ 0x44 + 8006eb2: 687b ldr r3, [r7, #4] + 8006eb4: 681b ldr r3, [r3, #0] + 8006eb6: 430a orrs r2, r1 + 8006eb8: 605a str r2, [r3, #4] } } /* if required, configure MSB first on communication line */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) - 8006e1e: 687b ldr r3, [r7, #4] - 8006e20: 6a5b ldr r3, [r3, #36] @ 0x24 - 8006e22: f003 0380 and.w r3, r3, #128 @ 0x80 - 8006e26: 2b00 cmp r3, #0 - 8006e28: d00a beq.n 8006e40 + 8006eba: 687b ldr r3, [r7, #4] + 8006ebc: 6a5b ldr r3, [r3, #36] @ 0x24 + 8006ebe: f003 0380 and.w r3, r3, #128 @ 0x80 + 8006ec2: 2b00 cmp r3, #0 + 8006ec4: d00a beq.n 8006edc { assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); - 8006e2a: 687b ldr r3, [r7, #4] - 8006e2c: 681b ldr r3, [r3, #0] - 8006e2e: 685b ldr r3, [r3, #4] - 8006e30: f423 2100 bic.w r1, r3, #524288 @ 0x80000 - 8006e34: 687b ldr r3, [r7, #4] - 8006e36: 6c9a ldr r2, [r3, #72] @ 0x48 - 8006e38: 687b ldr r3, [r7, #4] - 8006e3a: 681b ldr r3, [r3, #0] - 8006e3c: 430a orrs r2, r1 - 8006e3e: 605a str r2, [r3, #4] + 8006ec6: 687b ldr r3, [r7, #4] + 8006ec8: 681b ldr r3, [r3, #0] + 8006eca: 685b ldr r3, [r3, #4] + 8006ecc: f423 2100 bic.w r1, r3, #524288 @ 0x80000 + 8006ed0: 687b ldr r3, [r7, #4] + 8006ed2: 6c9a ldr r2, [r3, #72] @ 0x48 + 8006ed4: 687b ldr r3, [r7, #4] + 8006ed6: 681b ldr r3, [r3, #0] + 8006ed8: 430a orrs r2, r1 + 8006eda: 605a str r2, [r3, #4] } } - 8006e40: bf00 nop - 8006e42: 370c adds r7, #12 - 8006e44: 46bd mov sp, r7 - 8006e46: f85d 7b04 ldr.w r7, [sp], #4 - 8006e4a: 4770 bx lr + 8006edc: bf00 nop + 8006ede: 370c adds r7, #12 + 8006ee0: 46bd mov sp, r7 + 8006ee2: f85d 7b04 ldr.w r7, [sp], #4 + 8006ee6: 4770 bx lr -08006e4c : +08006ee8 : * @brief Check the UART Idle State. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) { - 8006e4c: b580 push {r7, lr} - 8006e4e: b098 sub sp, #96 @ 0x60 - 8006e50: af02 add r7, sp, #8 - 8006e52: 6078 str r0, [r7, #4] + 8006ee8: b580 push {r7, lr} + 8006eea: b098 sub sp, #96 @ 0x60 + 8006eec: af02 add r7, sp, #8 + 8006eee: 6078 str r0, [r7, #4] uint32_t tickstart; /* Initialize the UART ErrorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; - 8006e54: 687b ldr r3, [r7, #4] - 8006e56: 2200 movs r2, #0 - 8006e58: f8c3 2084 str.w r2, [r3, #132] @ 0x84 + 8006ef0: 687b ldr r3, [r7, #4] + 8006ef2: 2200 movs r2, #0 + 8006ef4: f8c3 2084 str.w r2, [r3, #132] @ 0x84 /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); - 8006e5c: f7fb fa04 bl 8002268 - 8006e60: 6578 str r0, [r7, #84] @ 0x54 + 8006ef8: f7fb fa04 bl 8002304 + 8006efc: 6578 str r0, [r7, #84] @ 0x54 /* Check if the Transmitter is enabled */ if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) - 8006e62: 687b ldr r3, [r7, #4] - 8006e64: 681b ldr r3, [r3, #0] - 8006e66: 681b ldr r3, [r3, #0] - 8006e68: f003 0308 and.w r3, r3, #8 - 8006e6c: 2b08 cmp r3, #8 - 8006e6e: d12e bne.n 8006ece + 8006efe: 687b ldr r3, [r7, #4] + 8006f00: 681b ldr r3, [r3, #0] + 8006f02: 681b ldr r3, [r3, #0] + 8006f04: f003 0308 and.w r3, r3, #8 + 8006f08: 2b08 cmp r3, #8 + 8006f0a: d12e bne.n 8006f6a { /* Wait until TEACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) - 8006e70: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000 - 8006e74: 9300 str r3, [sp, #0] - 8006e76: 6d7b ldr r3, [r7, #84] @ 0x54 - 8006e78: 2200 movs r2, #0 - 8006e7a: f44f 1100 mov.w r1, #2097152 @ 0x200000 - 8006e7e: 6878 ldr r0, [r7, #4] - 8006e80: f000 f88c bl 8006f9c - 8006e84: 4603 mov r3, r0 - 8006e86: 2b00 cmp r3, #0 - 8006e88: d021 beq.n 8006ece + 8006f0c: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000 + 8006f10: 9300 str r3, [sp, #0] + 8006f12: 6d7b ldr r3, [r7, #84] @ 0x54 + 8006f14: 2200 movs r2, #0 + 8006f16: f44f 1100 mov.w r1, #2097152 @ 0x200000 + 8006f1a: 6878 ldr r0, [r7, #4] + 8006f1c: f000 f88c bl 8007038 + 8006f20: 4603 mov r3, r0 + 8006f22: 2b00 cmp r3, #0 + 8006f24: d021 beq.n 8006f6a { /* Disable TXE interrupt for the interrupt process */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE)); - 8006e8a: 687b ldr r3, [r7, #4] - 8006e8c: 681b ldr r3, [r3, #0] - 8006e8e: 63bb str r3, [r7, #56] @ 0x38 + 8006f26: 687b ldr r3, [r7, #4] + 8006f28: 681b ldr r3, [r3, #0] + 8006f2a: 63bb str r3, [r7, #56] @ 0x38 */ __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) { uint32_t result; __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 8006e90: 6bbb ldr r3, [r7, #56] @ 0x38 - 8006e92: e853 3f00 ldrex r3, [r3] - 8006e96: 637b str r3, [r7, #52] @ 0x34 + 8006f2c: 6bbb ldr r3, [r7, #56] @ 0x38 + 8006f2e: e853 3f00 ldrex r3, [r3] + 8006f32: 637b str r3, [r7, #52] @ 0x34 return(result); - 8006e98: 6b7b ldr r3, [r7, #52] @ 0x34 - 8006e9a: f023 0380 bic.w r3, r3, #128 @ 0x80 - 8006e9e: 653b str r3, [r7, #80] @ 0x50 - 8006ea0: 687b ldr r3, [r7, #4] - 8006ea2: 681b ldr r3, [r3, #0] - 8006ea4: 461a mov r2, r3 - 8006ea6: 6d3b ldr r3, [r7, #80] @ 0x50 - 8006ea8: 647b str r3, [r7, #68] @ 0x44 - 8006eaa: 643a str r2, [r7, #64] @ 0x40 + 8006f34: 6b7b ldr r3, [r7, #52] @ 0x34 + 8006f36: f023 0380 bic.w r3, r3, #128 @ 0x80 + 8006f3a: 653b str r3, [r7, #80] @ 0x50 + 8006f3c: 687b ldr r3, [r7, #4] + 8006f3e: 681b ldr r3, [r3, #0] + 8006f40: 461a mov r2, r3 + 8006f42: 6d3b ldr r3, [r7, #80] @ 0x50 + 8006f44: 647b str r3, [r7, #68] @ 0x44 + 8006f46: 643a str r2, [r7, #64] @ 0x40 */ __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) { uint32_t result; __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 8006eac: 6c39 ldr r1, [r7, #64] @ 0x40 - 8006eae: 6c7a ldr r2, [r7, #68] @ 0x44 - 8006eb0: e841 2300 strex r3, r2, [r1] - 8006eb4: 63fb str r3, [r7, #60] @ 0x3c + 8006f48: 6c39 ldr r1, [r7, #64] @ 0x40 + 8006f4a: 6c7a ldr r2, [r7, #68] @ 0x44 + 8006f4c: e841 2300 strex r3, r2, [r1] + 8006f50: 63fb str r3, [r7, #60] @ 0x3c return(result); - 8006eb6: 6bfb ldr r3, [r7, #60] @ 0x3c - 8006eb8: 2b00 cmp r3, #0 - 8006eba: d1e6 bne.n 8006e8a + 8006f52: 6bfb ldr r3, [r7, #60] @ 0x3c + 8006f54: 2b00 cmp r3, #0 + 8006f56: d1e6 bne.n 8006f26 huart->gState = HAL_UART_STATE_READY; - 8006ebc: 687b ldr r3, [r7, #4] - 8006ebe: 2220 movs r2, #32 - 8006ec0: 67da str r2, [r3, #124] @ 0x7c + 8006f58: 687b ldr r3, [r7, #4] + 8006f5a: 2220 movs r2, #32 + 8006f5c: 67da str r2, [r3, #124] @ 0x7c __HAL_UNLOCK(huart); - 8006ec2: 687b ldr r3, [r7, #4] - 8006ec4: 2200 movs r2, #0 - 8006ec6: f883 2078 strb.w r2, [r3, #120] @ 0x78 + 8006f5e: 687b ldr r3, [r7, #4] + 8006f60: 2200 movs r2, #0 + 8006f62: f883 2078 strb.w r2, [r3, #120] @ 0x78 /* Timeout occurred */ return HAL_TIMEOUT; - 8006eca: 2303 movs r3, #3 - 8006ecc: e062 b.n 8006f94 + 8006f66: 2303 movs r3, #3 + 8006f68: e062 b.n 8007030 } } /* Check if the Receiver is enabled */ if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) - 8006ece: 687b ldr r3, [r7, #4] - 8006ed0: 681b ldr r3, [r3, #0] - 8006ed2: 681b ldr r3, [r3, #0] - 8006ed4: f003 0304 and.w r3, r3, #4 - 8006ed8: 2b04 cmp r3, #4 - 8006eda: d149 bne.n 8006f70 + 8006f6a: 687b ldr r3, [r7, #4] + 8006f6c: 681b ldr r3, [r3, #0] + 8006f6e: 681b ldr r3, [r3, #0] + 8006f70: f003 0304 and.w r3, r3, #4 + 8006f74: 2b04 cmp r3, #4 + 8006f76: d149 bne.n 800700c { /* Wait until REACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) - 8006edc: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000 - 8006ee0: 9300 str r3, [sp, #0] - 8006ee2: 6d7b ldr r3, [r7, #84] @ 0x54 - 8006ee4: 2200 movs r2, #0 - 8006ee6: f44f 0180 mov.w r1, #4194304 @ 0x400000 - 8006eea: 6878 ldr r0, [r7, #4] - 8006eec: f000 f856 bl 8006f9c - 8006ef0: 4603 mov r3, r0 - 8006ef2: 2b00 cmp r3, #0 - 8006ef4: d03c beq.n 8006f70 + 8006f78: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000 + 8006f7c: 9300 str r3, [sp, #0] + 8006f7e: 6d7b ldr r3, [r7, #84] @ 0x54 + 8006f80: 2200 movs r2, #0 + 8006f82: f44f 0180 mov.w r1, #4194304 @ 0x400000 + 8006f86: 6878 ldr r0, [r7, #4] + 8006f88: f000 f856 bl 8007038 + 8006f8c: 4603 mov r3, r0 + 8006f8e: 2b00 cmp r3, #0 + 8006f90: d03c beq.n 800700c { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); - 8006ef6: 687b ldr r3, [r7, #4] - 8006ef8: 681b ldr r3, [r3, #0] - 8006efa: 627b str r3, [r7, #36] @ 0x24 + 8006f92: 687b ldr r3, [r7, #4] + 8006f94: 681b ldr r3, [r3, #0] + 8006f96: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 8006efc: 6a7b ldr r3, [r7, #36] @ 0x24 - 8006efe: e853 3f00 ldrex r3, [r3] - 8006f02: 623b str r3, [r7, #32] + 8006f98: 6a7b ldr r3, [r7, #36] @ 0x24 + 8006f9a: e853 3f00 ldrex r3, [r3] + 8006f9e: 623b str r3, [r7, #32] return(result); - 8006f04: 6a3b ldr r3, [r7, #32] - 8006f06: f423 7390 bic.w r3, r3, #288 @ 0x120 - 8006f0a: 64fb str r3, [r7, #76] @ 0x4c - 8006f0c: 687b ldr r3, [r7, #4] - 8006f0e: 681b ldr r3, [r3, #0] - 8006f10: 461a mov r2, r3 - 8006f12: 6cfb ldr r3, [r7, #76] @ 0x4c - 8006f14: 633b str r3, [r7, #48] @ 0x30 - 8006f16: 62fa str r2, [r7, #44] @ 0x2c + 8006fa0: 6a3b ldr r3, [r7, #32] + 8006fa2: f423 7390 bic.w r3, r3, #288 @ 0x120 + 8006fa6: 64fb str r3, [r7, #76] @ 0x4c + 8006fa8: 687b ldr r3, [r7, #4] + 8006faa: 681b ldr r3, [r3, #0] + 8006fac: 461a mov r2, r3 + 8006fae: 6cfb ldr r3, [r7, #76] @ 0x4c + 8006fb0: 633b str r3, [r7, #48] @ 0x30 + 8006fb2: 62fa str r2, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 8006f18: 6af9 ldr r1, [r7, #44] @ 0x2c - 8006f1a: 6b3a ldr r2, [r7, #48] @ 0x30 - 8006f1c: e841 2300 strex r3, r2, [r1] - 8006f20: 62bb str r3, [r7, #40] @ 0x28 + 8006fb4: 6af9 ldr r1, [r7, #44] @ 0x2c + 8006fb6: 6b3a ldr r2, [r7, #48] @ 0x30 + 8006fb8: e841 2300 strex r3, r2, [r1] + 8006fbc: 62bb str r3, [r7, #40] @ 0x28 return(result); - 8006f22: 6abb ldr r3, [r7, #40] @ 0x28 - 8006f24: 2b00 cmp r3, #0 - 8006f26: d1e6 bne.n 8006ef6 + 8006fbe: 6abb ldr r3, [r7, #40] @ 0x28 + 8006fc0: 2b00 cmp r3, #0 + 8006fc2: d1e6 bne.n 8006f92 ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - 8006f28: 687b ldr r3, [r7, #4] - 8006f2a: 681b ldr r3, [r3, #0] - 8006f2c: 3308 adds r3, #8 - 8006f2e: 613b str r3, [r7, #16] + 8006fc4: 687b ldr r3, [r7, #4] + 8006fc6: 681b ldr r3, [r3, #0] + 8006fc8: 3308 adds r3, #8 + 8006fca: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 8006f30: 693b ldr r3, [r7, #16] - 8006f32: e853 3f00 ldrex r3, [r3] - 8006f36: 60fb str r3, [r7, #12] + 8006fcc: 693b ldr r3, [r7, #16] + 8006fce: e853 3f00 ldrex r3, [r3] + 8006fd2: 60fb str r3, [r7, #12] return(result); - 8006f38: 68fb ldr r3, [r7, #12] - 8006f3a: f023 0301 bic.w r3, r3, #1 - 8006f3e: 64bb str r3, [r7, #72] @ 0x48 - 8006f40: 687b ldr r3, [r7, #4] - 8006f42: 681b ldr r3, [r3, #0] - 8006f44: 3308 adds r3, #8 - 8006f46: 6cba ldr r2, [r7, #72] @ 0x48 - 8006f48: 61fa str r2, [r7, #28] - 8006f4a: 61bb str r3, [r7, #24] + 8006fd4: 68fb ldr r3, [r7, #12] + 8006fd6: f023 0301 bic.w r3, r3, #1 + 8006fda: 64bb str r3, [r7, #72] @ 0x48 + 8006fdc: 687b ldr r3, [r7, #4] + 8006fde: 681b ldr r3, [r3, #0] + 8006fe0: 3308 adds r3, #8 + 8006fe2: 6cba ldr r2, [r7, #72] @ 0x48 + 8006fe4: 61fa str r2, [r7, #28] + 8006fe6: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 8006f4c: 69b9 ldr r1, [r7, #24] - 8006f4e: 69fa ldr r2, [r7, #28] - 8006f50: e841 2300 strex r3, r2, [r1] - 8006f54: 617b str r3, [r7, #20] + 8006fe8: 69b9 ldr r1, [r7, #24] + 8006fea: 69fa ldr r2, [r7, #28] + 8006fec: e841 2300 strex r3, r2, [r1] + 8006ff0: 617b str r3, [r7, #20] return(result); - 8006f56: 697b ldr r3, [r7, #20] - 8006f58: 2b00 cmp r3, #0 - 8006f5a: d1e5 bne.n 8006f28 + 8006ff2: 697b ldr r3, [r7, #20] + 8006ff4: 2b00 cmp r3, #0 + 8006ff6: d1e5 bne.n 8006fc4 huart->RxState = HAL_UART_STATE_READY; - 8006f5c: 687b ldr r3, [r7, #4] - 8006f5e: 2220 movs r2, #32 - 8006f60: f8c3 2080 str.w r2, [r3, #128] @ 0x80 + 8006ff8: 687b ldr r3, [r7, #4] + 8006ffa: 2220 movs r2, #32 + 8006ffc: f8c3 2080 str.w r2, [r3, #128] @ 0x80 __HAL_UNLOCK(huart); - 8006f64: 687b ldr r3, [r7, #4] - 8006f66: 2200 movs r2, #0 - 8006f68: f883 2078 strb.w r2, [r3, #120] @ 0x78 + 8007000: 687b ldr r3, [r7, #4] + 8007002: 2200 movs r2, #0 + 8007004: f883 2078 strb.w r2, [r3, #120] @ 0x78 /* Timeout occurred */ return HAL_TIMEOUT; - 8006f6c: 2303 movs r3, #3 - 8006f6e: e011 b.n 8006f94 + 8007008: 2303 movs r3, #3 + 800700a: e011 b.n 8007030 } } /* Initialize the UART State */ huart->gState = HAL_UART_STATE_READY; - 8006f70: 687b ldr r3, [r7, #4] - 8006f72: 2220 movs r2, #32 - 8006f74: 67da str r2, [r3, #124] @ 0x7c + 800700c: 687b ldr r3, [r7, #4] + 800700e: 2220 movs r2, #32 + 8007010: 67da str r2, [r3, #124] @ 0x7c huart->RxState = HAL_UART_STATE_READY; - 8006f76: 687b ldr r3, [r7, #4] - 8006f78: 2220 movs r2, #32 - 8006f7a: f8c3 2080 str.w r2, [r3, #128] @ 0x80 + 8007012: 687b ldr r3, [r7, #4] + 8007014: 2220 movs r2, #32 + 8007016: f8c3 2080 str.w r2, [r3, #128] @ 0x80 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - 8006f7e: 687b ldr r3, [r7, #4] - 8006f80: 2200 movs r2, #0 - 8006f82: 661a str r2, [r3, #96] @ 0x60 + 800701a: 687b ldr r3, [r7, #4] + 800701c: 2200 movs r2, #0 + 800701e: 661a str r2, [r3, #96] @ 0x60 huart->RxEventType = HAL_UART_RXEVENT_TC; - 8006f84: 687b ldr r3, [r7, #4] - 8006f86: 2200 movs r2, #0 - 8006f88: 665a str r2, [r3, #100] @ 0x64 + 8007020: 687b ldr r3, [r7, #4] + 8007022: 2200 movs r2, #0 + 8007024: 665a str r2, [r3, #100] @ 0x64 __HAL_UNLOCK(huart); - 8006f8a: 687b ldr r3, [r7, #4] - 8006f8c: 2200 movs r2, #0 - 8006f8e: f883 2078 strb.w r2, [r3, #120] @ 0x78 + 8007026: 687b ldr r3, [r7, #4] + 8007028: 2200 movs r2, #0 + 800702a: f883 2078 strb.w r2, [r3, #120] @ 0x78 return HAL_OK; - 8006f92: 2300 movs r3, #0 + 800702e: 2300 movs r3, #0 } - 8006f94: 4618 mov r0, r3 - 8006f96: 3758 adds r7, #88 @ 0x58 - 8006f98: 46bd mov sp, r7 - 8006f9a: bd80 pop {r7, pc} + 8007030: 4618 mov r0, r3 + 8007032: 3758 adds r7, #88 @ 0x58 + 8007034: 46bd mov sp, r7 + 8007036: bd80 pop {r7, pc} -08006f9c : +08007038 : * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { - 8006f9c: b580 push {r7, lr} - 8006f9e: b084 sub sp, #16 - 8006fa0: af00 add r7, sp, #0 - 8006fa2: 60f8 str r0, [r7, #12] - 8006fa4: 60b9 str r1, [r7, #8] - 8006fa6: 603b str r3, [r7, #0] - 8006fa8: 4613 mov r3, r2 - 8006faa: 71fb strb r3, [r7, #7] + 8007038: b580 push {r7, lr} + 800703a: b084 sub sp, #16 + 800703c: af00 add r7, sp, #0 + 800703e: 60f8 str r0, [r7, #12] + 8007040: 60b9 str r1, [r7, #8] + 8007042: 603b str r3, [r7, #0] + 8007044: 4613 mov r3, r2 + 8007046: 71fb strb r3, [r7, #7] /* Wait until flag is set */ while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) - 8006fac: e04f b.n 800704e + 8007048: e04f b.n 80070ea { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) - 8006fae: 69bb ldr r3, [r7, #24] - 8006fb0: f1b3 3fff cmp.w r3, #4294967295 - 8006fb4: d04b beq.n 800704e + 800704a: 69bb ldr r3, [r7, #24] + 800704c: f1b3 3fff cmp.w r3, #4294967295 + 8007050: d04b beq.n 80070ea { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) - 8006fb6: f7fb f957 bl 8002268 - 8006fba: 4602 mov r2, r0 - 8006fbc: 683b ldr r3, [r7, #0] - 8006fbe: 1ad3 subs r3, r2, r3 - 8006fc0: 69ba ldr r2, [r7, #24] - 8006fc2: 429a cmp r2, r3 - 8006fc4: d302 bcc.n 8006fcc - 8006fc6: 69bb ldr r3, [r7, #24] - 8006fc8: 2b00 cmp r3, #0 - 8006fca: d101 bne.n 8006fd0 + 8007052: f7fb f957 bl 8002304 + 8007056: 4602 mov r2, r0 + 8007058: 683b ldr r3, [r7, #0] + 800705a: 1ad3 subs r3, r2, r3 + 800705c: 69ba ldr r2, [r7, #24] + 800705e: 429a cmp r2, r3 + 8007060: d302 bcc.n 8007068 + 8007062: 69bb ldr r3, [r7, #24] + 8007064: 2b00 cmp r3, #0 + 8007066: d101 bne.n 800706c { return HAL_TIMEOUT; - 8006fcc: 2303 movs r3, #3 - 8006fce: e04e b.n 800706e + 8007068: 2303 movs r3, #3 + 800706a: e04e b.n 800710a } if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC)) - 8006fd0: 68fb ldr r3, [r7, #12] - 8006fd2: 681b ldr r3, [r3, #0] - 8006fd4: 681b ldr r3, [r3, #0] - 8006fd6: f003 0304 and.w r3, r3, #4 - 8006fda: 2b00 cmp r3, #0 - 8006fdc: d037 beq.n 800704e - 8006fde: 68bb ldr r3, [r7, #8] - 8006fe0: 2b80 cmp r3, #128 @ 0x80 - 8006fe2: d034 beq.n 800704e - 8006fe4: 68bb ldr r3, [r7, #8] - 8006fe6: 2b40 cmp r3, #64 @ 0x40 - 8006fe8: d031 beq.n 800704e + 800706c: 68fb ldr r3, [r7, #12] + 800706e: 681b ldr r3, [r3, #0] + 8007070: 681b ldr r3, [r3, #0] + 8007072: f003 0304 and.w r3, r3, #4 + 8007076: 2b00 cmp r3, #0 + 8007078: d037 beq.n 80070ea + 800707a: 68bb ldr r3, [r7, #8] + 800707c: 2b80 cmp r3, #128 @ 0x80 + 800707e: d034 beq.n 80070ea + 8007080: 68bb ldr r3, [r7, #8] + 8007082: 2b40 cmp r3, #64 @ 0x40 + 8007084: d031 beq.n 80070ea { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) - 8006fea: 68fb ldr r3, [r7, #12] - 8006fec: 681b ldr r3, [r3, #0] - 8006fee: 69db ldr r3, [r3, #28] - 8006ff0: f003 0308 and.w r3, r3, #8 - 8006ff4: 2b08 cmp r3, #8 - 8006ff6: d110 bne.n 800701a + 8007086: 68fb ldr r3, [r7, #12] + 8007088: 681b ldr r3, [r3, #0] + 800708a: 69db ldr r3, [r3, #28] + 800708c: f003 0308 and.w r3, r3, #8 + 8007090: 2b08 cmp r3, #8 + 8007092: d110 bne.n 80070b6 { /* Clear Overrun Error flag*/ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); - 8006ff8: 68fb ldr r3, [r7, #12] - 8006ffa: 681b ldr r3, [r3, #0] - 8006ffc: 2208 movs r2, #8 - 8006ffe: 621a str r2, [r3, #32] + 8007094: 68fb ldr r3, [r7, #12] + 8007096: 681b ldr r3, [r3, #0] + 8007098: 2208 movs r2, #8 + 800709a: 621a str r2, [r3, #32] /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts if ongoing */ UART_EndRxTransfer(huart); - 8007000: 68f8 ldr r0, [r7, #12] - 8007002: f000 f838 bl 8007076 + 800709c: 68f8 ldr r0, [r7, #12] + 800709e: f000 f838 bl 8007112 huart->ErrorCode = HAL_UART_ERROR_ORE; - 8007006: 68fb ldr r3, [r7, #12] - 8007008: 2208 movs r2, #8 - 800700a: f8c3 2084 str.w r2, [r3, #132] @ 0x84 + 80070a2: 68fb ldr r3, [r7, #12] + 80070a4: 2208 movs r2, #8 + 80070a6: f8c3 2084 str.w r2, [r3, #132] @ 0x84 /* Process Unlocked */ __HAL_UNLOCK(huart); - 800700e: 68fb ldr r3, [r7, #12] - 8007010: 2200 movs r2, #0 - 8007012: f883 2078 strb.w r2, [r3, #120] @ 0x78 + 80070aa: 68fb ldr r3, [r7, #12] + 80070ac: 2200 movs r2, #0 + 80070ae: f883 2078 strb.w r2, [r3, #120] @ 0x78 return HAL_ERROR; - 8007016: 2301 movs r3, #1 - 8007018: e029 b.n 800706e + 80070b2: 2301 movs r3, #1 + 80070b4: e029 b.n 800710a } if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) - 800701a: 68fb ldr r3, [r7, #12] - 800701c: 681b ldr r3, [r3, #0] - 800701e: 69db ldr r3, [r3, #28] - 8007020: f403 6300 and.w r3, r3, #2048 @ 0x800 - 8007024: f5b3 6f00 cmp.w r3, #2048 @ 0x800 - 8007028: d111 bne.n 800704e + 80070b6: 68fb ldr r3, [r7, #12] + 80070b8: 681b ldr r3, [r3, #0] + 80070ba: 69db ldr r3, [r3, #28] + 80070bc: f403 6300 and.w r3, r3, #2048 @ 0x800 + 80070c0: f5b3 6f00 cmp.w r3, #2048 @ 0x800 + 80070c4: d111 bne.n 80070ea { /* Clear Receiver Timeout flag*/ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); - 800702a: 68fb ldr r3, [r7, #12] - 800702c: 681b ldr r3, [r3, #0] - 800702e: f44f 6200 mov.w r2, #2048 @ 0x800 - 8007032: 621a str r2, [r3, #32] + 80070c6: 68fb ldr r3, [r7, #12] + 80070c8: 681b ldr r3, [r3, #0] + 80070ca: f44f 6200 mov.w r2, #2048 @ 0x800 + 80070ce: 621a str r2, [r3, #32] /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts if ongoing */ UART_EndRxTransfer(huart); - 8007034: 68f8 ldr r0, [r7, #12] - 8007036: f000 f81e bl 8007076 + 80070d0: 68f8 ldr r0, [r7, #12] + 80070d2: f000 f81e bl 8007112 huart->ErrorCode = HAL_UART_ERROR_RTO; - 800703a: 68fb ldr r3, [r7, #12] - 800703c: 2220 movs r2, #32 - 800703e: f8c3 2084 str.w r2, [r3, #132] @ 0x84 + 80070d6: 68fb ldr r3, [r7, #12] + 80070d8: 2220 movs r2, #32 + 80070da: f8c3 2084 str.w r2, [r3, #132] @ 0x84 /* Process Unlocked */ __HAL_UNLOCK(huart); - 8007042: 68fb ldr r3, [r7, #12] - 8007044: 2200 movs r2, #0 - 8007046: f883 2078 strb.w r2, [r3, #120] @ 0x78 + 80070de: 68fb ldr r3, [r7, #12] + 80070e0: 2200 movs r2, #0 + 80070e2: f883 2078 strb.w r2, [r3, #120] @ 0x78 return HAL_TIMEOUT; - 800704a: 2303 movs r3, #3 - 800704c: e00f b.n 800706e + 80070e6: 2303 movs r3, #3 + 80070e8: e00f b.n 800710a while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) - 800704e: 68fb ldr r3, [r7, #12] - 8007050: 681b ldr r3, [r3, #0] - 8007052: 69da ldr r2, [r3, #28] - 8007054: 68bb ldr r3, [r7, #8] - 8007056: 4013 ands r3, r2 - 8007058: 68ba ldr r2, [r7, #8] - 800705a: 429a cmp r2, r3 - 800705c: bf0c ite eq - 800705e: 2301 moveq r3, #1 - 8007060: 2300 movne r3, #0 - 8007062: b2db uxtb r3, r3 - 8007064: 461a mov r2, r3 - 8007066: 79fb ldrb r3, [r7, #7] - 8007068: 429a cmp r2, r3 - 800706a: d0a0 beq.n 8006fae + 80070ea: 68fb ldr r3, [r7, #12] + 80070ec: 681b ldr r3, [r3, #0] + 80070ee: 69da ldr r2, [r3, #28] + 80070f0: 68bb ldr r3, [r7, #8] + 80070f2: 4013 ands r3, r2 + 80070f4: 68ba ldr r2, [r7, #8] + 80070f6: 429a cmp r2, r3 + 80070f8: bf0c ite eq + 80070fa: 2301 moveq r3, #1 + 80070fc: 2300 movne r3, #0 + 80070fe: b2db uxtb r3, r3 + 8007100: 461a mov r2, r3 + 8007102: 79fb ldrb r3, [r7, #7] + 8007104: 429a cmp r2, r3 + 8007106: d0a0 beq.n 800704a } } } } return HAL_OK; - 800706c: 2300 movs r3, #0 + 8007108: 2300 movs r3, #0 } - 800706e: 4618 mov r0, r3 - 8007070: 3710 adds r7, #16 - 8007072: 46bd mov sp, r7 - 8007074: bd80 pop {r7, pc} + 800710a: 4618 mov r0, r3 + 800710c: 3710 adds r7, #16 + 800710e: 46bd mov sp, r7 + 8007110: bd80 pop {r7, pc} -08007076 : +08007112 : * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). * @param huart UART handle. * @retval None */ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) { - 8007076: b480 push {r7} - 8007078: b095 sub sp, #84 @ 0x54 - 800707a: af00 add r7, sp, #0 - 800707c: 6078 str r0, [r7, #4] + 8007112: b480 push {r7} + 8007114: b095 sub sp, #84 @ 0x54 + 8007116: af00 add r7, sp, #0 + 8007118: 6078 str r0, [r7, #4] /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); - 800707e: 687b ldr r3, [r7, #4] - 8007080: 681b ldr r3, [r3, #0] - 8007082: 637b str r3, [r7, #52] @ 0x34 + 800711a: 687b ldr r3, [r7, #4] + 800711c: 681b ldr r3, [r3, #0] + 800711e: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 8007084: 6b7b ldr r3, [r7, #52] @ 0x34 - 8007086: e853 3f00 ldrex r3, [r3] - 800708a: 633b str r3, [r7, #48] @ 0x30 + 8007120: 6b7b ldr r3, [r7, #52] @ 0x34 + 8007122: e853 3f00 ldrex r3, [r3] + 8007126: 633b str r3, [r7, #48] @ 0x30 return(result); - 800708c: 6b3b ldr r3, [r7, #48] @ 0x30 - 800708e: f423 7390 bic.w r3, r3, #288 @ 0x120 - 8007092: 64fb str r3, [r7, #76] @ 0x4c - 8007094: 687b ldr r3, [r7, #4] - 8007096: 681b ldr r3, [r3, #0] - 8007098: 461a mov r2, r3 - 800709a: 6cfb ldr r3, [r7, #76] @ 0x4c - 800709c: 643b str r3, [r7, #64] @ 0x40 - 800709e: 63fa str r2, [r7, #60] @ 0x3c + 8007128: 6b3b ldr r3, [r7, #48] @ 0x30 + 800712a: f423 7390 bic.w r3, r3, #288 @ 0x120 + 800712e: 64fb str r3, [r7, #76] @ 0x4c + 8007130: 687b ldr r3, [r7, #4] + 8007132: 681b ldr r3, [r3, #0] + 8007134: 461a mov r2, r3 + 8007136: 6cfb ldr r3, [r7, #76] @ 0x4c + 8007138: 643b str r3, [r7, #64] @ 0x40 + 800713a: 63fa str r2, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 80070a0: 6bf9 ldr r1, [r7, #60] @ 0x3c - 80070a2: 6c3a ldr r2, [r7, #64] @ 0x40 - 80070a4: e841 2300 strex r3, r2, [r1] - 80070a8: 63bb str r3, [r7, #56] @ 0x38 + 800713c: 6bf9 ldr r1, [r7, #60] @ 0x3c + 800713e: 6c3a ldr r2, [r7, #64] @ 0x40 + 8007140: e841 2300 strex r3, r2, [r1] + 8007144: 63bb str r3, [r7, #56] @ 0x38 return(result); - 80070aa: 6bbb ldr r3, [r7, #56] @ 0x38 - 80070ac: 2b00 cmp r3, #0 - 80070ae: d1e6 bne.n 800707e + 8007146: 6bbb ldr r3, [r7, #56] @ 0x38 + 8007148: 2b00 cmp r3, #0 + 800714a: d1e6 bne.n 800711a ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - 80070b0: 687b ldr r3, [r7, #4] - 80070b2: 681b ldr r3, [r3, #0] - 80070b4: 3308 adds r3, #8 - 80070b6: 623b str r3, [r7, #32] + 800714c: 687b ldr r3, [r7, #4] + 800714e: 681b ldr r3, [r3, #0] + 8007150: 3308 adds r3, #8 + 8007152: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 80070b8: 6a3b ldr r3, [r7, #32] - 80070ba: e853 3f00 ldrex r3, [r3] - 80070be: 61fb str r3, [r7, #28] + 8007154: 6a3b ldr r3, [r7, #32] + 8007156: e853 3f00 ldrex r3, [r3] + 800715a: 61fb str r3, [r7, #28] return(result); - 80070c0: 69fb ldr r3, [r7, #28] - 80070c2: f023 0301 bic.w r3, r3, #1 - 80070c6: 64bb str r3, [r7, #72] @ 0x48 - 80070c8: 687b ldr r3, [r7, #4] - 80070ca: 681b ldr r3, [r3, #0] - 80070cc: 3308 adds r3, #8 - 80070ce: 6cba ldr r2, [r7, #72] @ 0x48 - 80070d0: 62fa str r2, [r7, #44] @ 0x2c - 80070d2: 62bb str r3, [r7, #40] @ 0x28 + 800715c: 69fb ldr r3, [r7, #28] + 800715e: f023 0301 bic.w r3, r3, #1 + 8007162: 64bb str r3, [r7, #72] @ 0x48 + 8007164: 687b ldr r3, [r7, #4] + 8007166: 681b ldr r3, [r3, #0] + 8007168: 3308 adds r3, #8 + 800716a: 6cba ldr r2, [r7, #72] @ 0x48 + 800716c: 62fa str r2, [r7, #44] @ 0x2c + 800716e: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 80070d4: 6ab9 ldr r1, [r7, #40] @ 0x28 - 80070d6: 6afa ldr r2, [r7, #44] @ 0x2c - 80070d8: e841 2300 strex r3, r2, [r1] - 80070dc: 627b str r3, [r7, #36] @ 0x24 + 8007170: 6ab9 ldr r1, [r7, #40] @ 0x28 + 8007172: 6afa ldr r2, [r7, #44] @ 0x2c + 8007174: e841 2300 strex r3, r2, [r1] + 8007178: 627b str r3, [r7, #36] @ 0x24 return(result); - 80070de: 6a7b ldr r3, [r7, #36] @ 0x24 - 80070e0: 2b00 cmp r3, #0 - 80070e2: d1e5 bne.n 80070b0 + 800717a: 6a7b ldr r3, [r7, #36] @ 0x24 + 800717c: 2b00 cmp r3, #0 + 800717e: d1e5 bne.n 800714c /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - 80070e4: 687b ldr r3, [r7, #4] - 80070e6: 6e1b ldr r3, [r3, #96] @ 0x60 - 80070e8: 2b01 cmp r3, #1 - 80070ea: d118 bne.n 800711e + 8007180: 687b ldr r3, [r7, #4] + 8007182: 6e1b ldr r3, [r3, #96] @ 0x60 + 8007184: 2b01 cmp r3, #1 + 8007186: d118 bne.n 80071ba { ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); - 80070ec: 687b ldr r3, [r7, #4] - 80070ee: 681b ldr r3, [r3, #0] - 80070f0: 60fb str r3, [r7, #12] + 8007188: 687b ldr r3, [r7, #4] + 800718a: 681b ldr r3, [r3, #0] + 800718c: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 80070f2: 68fb ldr r3, [r7, #12] - 80070f4: e853 3f00 ldrex r3, [r3] - 80070f8: 60bb str r3, [r7, #8] + 800718e: 68fb ldr r3, [r7, #12] + 8007190: e853 3f00 ldrex r3, [r3] + 8007194: 60bb str r3, [r7, #8] return(result); - 80070fa: 68bb ldr r3, [r7, #8] - 80070fc: f023 0310 bic.w r3, r3, #16 - 8007100: 647b str r3, [r7, #68] @ 0x44 - 8007102: 687b ldr r3, [r7, #4] - 8007104: 681b ldr r3, [r3, #0] - 8007106: 461a mov r2, r3 - 8007108: 6c7b ldr r3, [r7, #68] @ 0x44 - 800710a: 61bb str r3, [r7, #24] - 800710c: 617a str r2, [r7, #20] + 8007196: 68bb ldr r3, [r7, #8] + 8007198: f023 0310 bic.w r3, r3, #16 + 800719c: 647b str r3, [r7, #68] @ 0x44 + 800719e: 687b ldr r3, [r7, #4] + 80071a0: 681b ldr r3, [r3, #0] + 80071a2: 461a mov r2, r3 + 80071a4: 6c7b ldr r3, [r7, #68] @ 0x44 + 80071a6: 61bb str r3, [r7, #24] + 80071a8: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 800710e: 6979 ldr r1, [r7, #20] - 8007110: 69ba ldr r2, [r7, #24] - 8007112: e841 2300 strex r3, r2, [r1] - 8007116: 613b str r3, [r7, #16] + 80071aa: 6979 ldr r1, [r7, #20] + 80071ac: 69ba ldr r2, [r7, #24] + 80071ae: e841 2300 strex r3, r2, [r1] + 80071b2: 613b str r3, [r7, #16] return(result); - 8007118: 693b ldr r3, [r7, #16] - 800711a: 2b00 cmp r3, #0 - 800711c: d1e6 bne.n 80070ec + 80071b4: 693b ldr r3, [r7, #16] + 80071b6: 2b00 cmp r3, #0 + 80071b8: d1e6 bne.n 8007188 } /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; - 800711e: 687b ldr r3, [r7, #4] - 8007120: 2220 movs r2, #32 - 8007122: f8c3 2080 str.w r2, [r3, #128] @ 0x80 + 80071ba: 687b ldr r3, [r7, #4] + 80071bc: 2220 movs r2, #32 + 80071be: f8c3 2080 str.w r2, [r3, #128] @ 0x80 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - 8007126: 687b ldr r3, [r7, #4] - 8007128: 2200 movs r2, #0 - 800712a: 661a str r2, [r3, #96] @ 0x60 + 80071c2: 687b ldr r3, [r7, #4] + 80071c4: 2200 movs r2, #0 + 80071c6: 661a str r2, [r3, #96] @ 0x60 /* Reset RxIsr function pointer */ huart->RxISR = NULL; - 800712c: 687b ldr r3, [r7, #4] - 800712e: 2200 movs r2, #0 - 8007130: 669a str r2, [r3, #104] @ 0x68 + 80071c8: 687b ldr r3, [r7, #4] + 80071ca: 2200 movs r2, #0 + 80071cc: 669a str r2, [r3, #104] @ 0x68 } - 8007132: bf00 nop - 8007134: 3754 adds r7, #84 @ 0x54 - 8007136: 46bd mov sp, r7 - 8007138: f85d 7b04 ldr.w r7, [sp], #4 - 800713c: 4770 bx lr + 80071ce: bf00 nop + 80071d0: 3754 adds r7, #84 @ 0x54 + 80071d2: 46bd mov sp, r7 + 80071d4: f85d 7b04 ldr.w r7, [sp], #4 + 80071d8: 4770 bx lr -0800713e : - 800713e: 4402 add r2, r0 - 8007140: 4603 mov r3, r0 - 8007142: 4293 cmp r3, r2 - 8007144: d100 bne.n 8007148 - 8007146: 4770 bx lr - 8007148: f803 1b01 strb.w r1, [r3], #1 - 800714c: e7f9 b.n 8007142 +080071da : + 80071da: 4402 add r2, r0 + 80071dc: 4603 mov r3, r0 + 80071de: 4293 cmp r3, r2 + 80071e0: d100 bne.n 80071e4 + 80071e2: 4770 bx lr + 80071e4: f803 1b01 strb.w r1, [r3], #1 + 80071e8: e7f9 b.n 80071de ... -08007150 <__libc_init_array>: - 8007150: b570 push {r4, r5, r6, lr} - 8007152: 4d0d ldr r5, [pc, #52] @ (8007188 <__libc_init_array+0x38>) - 8007154: 4c0d ldr r4, [pc, #52] @ (800718c <__libc_init_array+0x3c>) - 8007156: 1b64 subs r4, r4, r5 - 8007158: 10a4 asrs r4, r4, #2 - 800715a: 2600 movs r6, #0 - 800715c: 42a6 cmp r6, r4 - 800715e: d109 bne.n 8007174 <__libc_init_array+0x24> - 8007160: 4d0b ldr r5, [pc, #44] @ (8007190 <__libc_init_array+0x40>) - 8007162: 4c0c ldr r4, [pc, #48] @ (8007194 <__libc_init_array+0x44>) - 8007164: f000 f818 bl 8007198 <_init> - 8007168: 1b64 subs r4, r4, r5 - 800716a: 10a4 asrs r4, r4, #2 - 800716c: 2600 movs r6, #0 - 800716e: 42a6 cmp r6, r4 - 8007170: d105 bne.n 800717e <__libc_init_array+0x2e> - 8007172: bd70 pop {r4, r5, r6, pc} - 8007174: f855 3b04 ldr.w r3, [r5], #4 - 8007178: 4798 blx r3 - 800717a: 3601 adds r6, #1 - 800717c: e7ee b.n 800715c <__libc_init_array+0xc> - 800717e: f855 3b04 ldr.w r3, [r5], #4 - 8007182: 4798 blx r3 - 8007184: 3601 adds r6, #1 - 8007186: e7f2 b.n 800716e <__libc_init_array+0x1e> - 8007188: 080071e8 .word 0x080071e8 - 800718c: 080071e8 .word 0x080071e8 - 8007190: 080071e8 .word 0x080071e8 - 8007194: 080071ec .word 0x080071ec +080071ec <__libc_init_array>: + 80071ec: b570 push {r4, r5, r6, lr} + 80071ee: 4d0d ldr r5, [pc, #52] @ (8007224 <__libc_init_array+0x38>) + 80071f0: 4c0d ldr r4, [pc, #52] @ (8007228 <__libc_init_array+0x3c>) + 80071f2: 1b64 subs r4, r4, r5 + 80071f4: 10a4 asrs r4, r4, #2 + 80071f6: 2600 movs r6, #0 + 80071f8: 42a6 cmp r6, r4 + 80071fa: d109 bne.n 8007210 <__libc_init_array+0x24> + 80071fc: 4d0b ldr r5, [pc, #44] @ (800722c <__libc_init_array+0x40>) + 80071fe: 4c0c ldr r4, [pc, #48] @ (8007230 <__libc_init_array+0x44>) + 8007200: f000 f818 bl 8007234 <_init> + 8007204: 1b64 subs r4, r4, r5 + 8007206: 10a4 asrs r4, r4, #2 + 8007208: 2600 movs r6, #0 + 800720a: 42a6 cmp r6, r4 + 800720c: d105 bne.n 800721a <__libc_init_array+0x2e> + 800720e: bd70 pop {r4, r5, r6, pc} + 8007210: f855 3b04 ldr.w r3, [r5], #4 + 8007214: 4798 blx r3 + 8007216: 3601 adds r6, #1 + 8007218: e7ee b.n 80071f8 <__libc_init_array+0xc> + 800721a: f855 3b04 ldr.w r3, [r5], #4 + 800721e: 4798 blx r3 + 8007220: 3601 adds r6, #1 + 8007222: e7f2 b.n 800720a <__libc_init_array+0x1e> + 8007224: 08007284 .word 0x08007284 + 8007228: 08007284 .word 0x08007284 + 800722c: 08007284 .word 0x08007284 + 8007230: 08007288 .word 0x08007288 -08007198 <_init>: - 8007198: b5f8 push {r3, r4, r5, r6, r7, lr} - 800719a: bf00 nop - 800719c: bcf8 pop {r3, r4, r5, r6, r7} - 800719e: bc08 pop {r3} - 80071a0: 469e mov lr, r3 - 80071a2: 4770 bx lr +08007234 <_init>: + 8007234: b5f8 push {r3, r4, r5, r6, r7, lr} + 8007236: bf00 nop + 8007238: bcf8 pop {r3, r4, r5, r6, r7} + 800723a: bc08 pop {r3} + 800723c: 469e mov lr, r3 + 800723e: 4770 bx lr -080071a4 <_fini>: - 80071a4: b5f8 push {r3, r4, r5, r6, r7, lr} - 80071a6: bf00 nop - 80071a8: bcf8 pop {r3, r4, r5, r6, r7} - 80071aa: bc08 pop {r3} - 80071ac: 469e mov lr, r3 - 80071ae: 4770 bx lr +08007240 <_fini>: + 8007240: b5f8 push {r3, r4, r5, r6, r7, lr} + 8007242: bf00 nop + 8007244: bcf8 pop {r3, r4, r5, r6, r7} + 8007246: bc08 pop {r3} + 8007248: 469e mov lr, r3 + 800724a: 4770 bx lr diff --git a/Software/Code/Debug/PDU_FT25.map b/Software/Code/Debug/PDU_FT25.map index eaf7b26..0c7a4ab 100644 --- a/Software/Code/Debug/PDU_FT25.map +++ b/Software/Code/Debug/PDU_FT25.map @@ -109,10 +109,6 @@ Discarded input sections .text 0x00000000 0x0 ./Core/Src/can_communication.o .data 0x00000000 0x0 ./Core/Src/can_communication.o .bss 0x00000000 0x0 ./Core/Src/can_communication.o - .text.can_error_report - 0x00000000 0xb4 ./Core/Src/can_communication.o - .bss.error_loop.0 - 0x00000000 0x4 ./Core/Src/can_communication.o .group 0x00000000 0xc ./Core/Src/can_halal.o .group 0x00000000 0xc ./Core/Src/can_halal.o .group 0x00000000 0xc ./Core/Src/can_halal.o @@ -4342,7 +4338,7 @@ LOAD C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.ext 0x08000000 g_pfnVectors 0x08000188 . = ALIGN (0x4) -.text 0x08000188 0x7028 +.text 0x08000188 0x70c4 0x08000188 . = ALIGN (0x4) *(.text) .text 0x08000188 0x40 C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.1.0.202410251130/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+fp/hard/crtbegin.o @@ -4376,516 +4372,519 @@ LOAD C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.ext .text.can_sendloop 0x080007f4 0x1fc ./Core/Src/can_communication.o 0x080007f4 can_sendloop + .text.can_error_report + 0x080009f0 0x2c ./Core/Src/can_communication.o + 0x080009f0 can_error_report .text.ftcan_msg_received_cb - 0x080009f0 0x6c ./Core/Src/can_communication.o - 0x080009f0 ftcan_msg_received_cb + 0x08000a1c 0x6c ./Core/Src/can_communication.o + 0x08000a1c ftcan_msg_received_cb .text.ftcan_init - 0x08000a5c 0x40 ./Core/Src/can_halal.o - 0x08000a5c ftcan_init + 0x08000a88 0x40 ./Core/Src/can_halal.o + 0x08000a88 ftcan_init .text.ftcan_transmit - 0x08000a9c 0x48 ./Core/Src/can_halal.o - 0x08000a9c ftcan_transmit + 0x08000ac8 0x48 ./Core/Src/can_halal.o + 0x08000ac8 ftcan_transmit .text.ftcan_add_filter - 0x08000ae4 0xb8 ./Core/Src/can_halal.o - 0x08000ae4 ftcan_add_filter + 0x08000b10 0xb8 ./Core/Src/can_halal.o + 0x08000b10 ftcan_add_filter .text.HAL_CAN_RxFifo0MsgPendingCallback - 0x08000b9c 0x58 ./Core/Src/can_halal.o - 0x08000b9c HAL_CAN_RxFifo0MsgPendingCallback + 0x08000bc8 0x58 ./Core/Src/can_halal.o + 0x08000bc8 HAL_CAN_RxFifo0MsgPendingCallback .text.ChannelControl_init - 0x08000bf4 0x34 ./Core/Src/channel_control.o - 0x08000bf4 ChannelControl_init + 0x08000c20 0x34 ./Core/Src/channel_control.o + 0x08000c20 ChannelControl_init .text.ChannelControl_UpdateGPIOs - 0x08000c28 0x218 ./Core/Src/channel_control.o - 0x08000c28 ChannelControl_UpdateGPIOs + 0x08000c54 0x204 ./Core/Src/channel_control.o + 0x08000c54 ChannelControl_UpdateGPIOs .text.current_monitor_init - 0x08000e40 0x74 ./Core/Src/current_monitoring.o - 0x08000e40 current_monitor_init + 0x08000e58 0x74 ./Core/Src/current_monitoring.o + 0x08000e58 current_monitor_init .text.current_monitor_checklimits - 0x08000eb4 0x10 ./Core/Src/current_monitoring.o - 0x08000eb4 current_monitor_checklimits - *fill* 0x08000ec4 0x4 + 0x08000ecc 0x10 ./Core/Src/current_monitoring.o + 0x08000ecc current_monitor_checklimits + *fill* 0x08000edc 0x4 .text.HAL_ADC_ConvCpltCallback - 0x08000ec8 0x32c ./Core/Src/current_monitoring.o - 0x08000ec8 HAL_ADC_ConvCpltCallback - .text.main 0x080011f4 0x1d0 ./Core/Src/main.o - 0x080011f4 main + 0x08000ee0 0x32c ./Core/Src/current_monitoring.o + 0x08000ee0 HAL_ADC_ConvCpltCallback + .text.main 0x0800120c 0x1d8 ./Core/Src/main.o + 0x0800120c main .text.SystemClock_Config - 0x080013c4 0xb8 ./Core/Src/main.o - 0x080013c4 SystemClock_Config + 0x080013e4 0xb8 ./Core/Src/main.o + 0x080013e4 SystemClock_Config .text.MX_ADC1_Init - 0x0800147c 0x1a8 ./Core/Src/main.o + 0x0800149c 0x1a8 ./Core/Src/main.o .text.MX_ADC2_Init - 0x08001624 0x14c ./Core/Src/main.o + 0x08001644 0x14c ./Core/Src/main.o .text.MX_CAN_Init - 0x08001770 0x6c ./Core/Src/main.o + 0x08001790 0x6c ./Core/Src/main.o .text.MX_TIM6_Init - 0x080017dc 0x70 ./Core/Src/main.o + 0x080017fc 0x70 ./Core/Src/main.o .text.MX_UART4_Init - 0x0800184c 0x60 ./Core/Src/main.o + 0x0800186c 0x60 ./Core/Src/main.o .text.MX_DMA_Init - 0x080018ac 0x64 ./Core/Src/main.o + 0x080018cc 0x64 ./Core/Src/main.o .text.MX_GPIO_Init - 0x08001910 0x10c ./Core/Src/main.o + 0x08001930 0x10c ./Core/Src/main.o .text.Error_Handler - 0x08001a1c 0xc ./Core/Src/main.o - 0x08001a1c Error_Handler + 0x08001a3c 0xc ./Core/Src/main.o + 0x08001a3c Error_Handler .text.check_plausibility - 0x08001a28 0x20c ./Core/Src/plausibility_check.o - 0x08001a28 check_plausibility + 0x08001a48 0x288 ./Core/Src/plausibility_check.o + 0x08001a48 check_plausibility .text.HAL_MspInit - 0x08001c34 0x48 ./Core/Src/stm32f3xx_hal_msp.o - 0x08001c34 HAL_MspInit + 0x08001cd0 0x48 ./Core/Src/stm32f3xx_hal_msp.o + 0x08001cd0 HAL_MspInit .text.HAL_ADC_MspInit - 0x08001c7c 0x264 ./Core/Src/stm32f3xx_hal_msp.o - 0x08001c7c HAL_ADC_MspInit + 0x08001d18 0x264 ./Core/Src/stm32f3xx_hal_msp.o + 0x08001d18 HAL_ADC_MspInit .text.HAL_CAN_MspInit - 0x08001ee0 0xa8 ./Core/Src/stm32f3xx_hal_msp.o - 0x08001ee0 HAL_CAN_MspInit + 0x08001f7c 0xa8 ./Core/Src/stm32f3xx_hal_msp.o + 0x08001f7c HAL_CAN_MspInit .text.HAL_TIM_Base_MspInit - 0x08001f88 0x4c ./Core/Src/stm32f3xx_hal_msp.o - 0x08001f88 HAL_TIM_Base_MspInit + 0x08002024 0x4c ./Core/Src/stm32f3xx_hal_msp.o + 0x08002024 HAL_TIM_Base_MspInit .text.HAL_UART_MspInit - 0x08001fd4 0x88 ./Core/Src/stm32f3xx_hal_msp.o - 0x08001fd4 HAL_UART_MspInit + 0x08002070 0x88 ./Core/Src/stm32f3xx_hal_msp.o + 0x08002070 HAL_UART_MspInit .text.NMI_Handler - 0x0800205c 0x8 ./Core/Src/stm32f3xx_it.o - 0x0800205c NMI_Handler + 0x080020f8 0x8 ./Core/Src/stm32f3xx_it.o + 0x080020f8 NMI_Handler .text.HardFault_Handler - 0x08002064 0x8 ./Core/Src/stm32f3xx_it.o - 0x08002064 HardFault_Handler + 0x08002100 0x8 ./Core/Src/stm32f3xx_it.o + 0x08002100 HardFault_Handler .text.MemManage_Handler - 0x0800206c 0x8 ./Core/Src/stm32f3xx_it.o - 0x0800206c MemManage_Handler + 0x08002108 0x8 ./Core/Src/stm32f3xx_it.o + 0x08002108 MemManage_Handler .text.BusFault_Handler - 0x08002074 0x8 ./Core/Src/stm32f3xx_it.o - 0x08002074 BusFault_Handler + 0x08002110 0x8 ./Core/Src/stm32f3xx_it.o + 0x08002110 BusFault_Handler .text.UsageFault_Handler - 0x0800207c 0x8 ./Core/Src/stm32f3xx_it.o - 0x0800207c UsageFault_Handler + 0x08002118 0x8 ./Core/Src/stm32f3xx_it.o + 0x08002118 UsageFault_Handler .text.SVC_Handler - 0x08002084 0xe ./Core/Src/stm32f3xx_it.o - 0x08002084 SVC_Handler + 0x08002120 0xe ./Core/Src/stm32f3xx_it.o + 0x08002120 SVC_Handler .text.DebugMon_Handler - 0x08002092 0xe ./Core/Src/stm32f3xx_it.o - 0x08002092 DebugMon_Handler + 0x0800212e 0xe ./Core/Src/stm32f3xx_it.o + 0x0800212e DebugMon_Handler .text.PendSV_Handler - 0x080020a0 0xe ./Core/Src/stm32f3xx_it.o - 0x080020a0 PendSV_Handler + 0x0800213c 0xe ./Core/Src/stm32f3xx_it.o + 0x0800213c PendSV_Handler .text.SysTick_Handler - 0x080020ae 0xc ./Core/Src/stm32f3xx_it.o - 0x080020ae SysTick_Handler - *fill* 0x080020ba 0x2 + 0x0800214a 0xc ./Core/Src/stm32f3xx_it.o + 0x0800214a SysTick_Handler + *fill* 0x08002156 0x2 .text.DMA1_Channel1_IRQHandler - 0x080020bc 0x14 ./Core/Src/stm32f3xx_it.o - 0x080020bc DMA1_Channel1_IRQHandler + 0x08002158 0x14 ./Core/Src/stm32f3xx_it.o + 0x08002158 DMA1_Channel1_IRQHandler .text.ADC1_2_IRQHandler - 0x080020d0 0x1c ./Core/Src/stm32f3xx_it.o - 0x080020d0 ADC1_2_IRQHandler + 0x0800216c 0x1c ./Core/Src/stm32f3xx_it.o + 0x0800216c ADC1_2_IRQHandler .text.USB_LP_CAN_RX0_IRQHandler - 0x080020ec 0x14 ./Core/Src/stm32f3xx_it.o - 0x080020ec USB_LP_CAN_RX0_IRQHandler + 0x08002188 0x14 ./Core/Src/stm32f3xx_it.o + 0x08002188 USB_LP_CAN_RX0_IRQHandler .text.CAN_RX1_IRQHandler - 0x08002100 0x14 ./Core/Src/stm32f3xx_it.o - 0x08002100 CAN_RX1_IRQHandler + 0x0800219c 0x14 ./Core/Src/stm32f3xx_it.o + 0x0800219c CAN_RX1_IRQHandler .text.TIM6_DAC_IRQHandler - 0x08002114 0x14 ./Core/Src/stm32f3xx_it.o - 0x08002114 TIM6_DAC_IRQHandler + 0x080021b0 0x14 ./Core/Src/stm32f3xx_it.o + 0x080021b0 TIM6_DAC_IRQHandler .text.DMA2_Channel1_IRQHandler - 0x08002128 0x14 ./Core/Src/stm32f3xx_it.o - 0x08002128 DMA2_Channel1_IRQHandler + 0x080021c4 0x14 ./Core/Src/stm32f3xx_it.o + 0x080021c4 DMA2_Channel1_IRQHandler .text.SystemInit - 0x0800213c 0x24 ./Core/Src/system_stm32f3xx.o - 0x0800213c SystemInit + 0x080021d8 0x24 ./Core/Src/system_stm32f3xx.o + 0x080021d8 SystemInit .text.Reset_Handler - 0x08002160 0x50 ./Core/Startup/startup_stm32f302rbtx.o - 0x08002160 Reset_Handler + 0x080021fc 0x50 ./Core/Startup/startup_stm32f302rbtx.o + 0x080021fc Reset_Handler .text.Default_Handler - 0x080021b0 0x2 ./Core/Startup/startup_stm32f302rbtx.o - 0x080021b0 RTC_Alarm_IRQHandler - 0x080021b0 TIM1_CC_IRQHandler - 0x080021b0 USB_HP_IRQHandler - 0x080021b0 PVD_IRQHandler - 0x080021b0 TAMP_STAMP_IRQHandler - 0x080021b0 EXTI3_IRQHandler - 0x080021b0 USB_HP_CAN_TX_IRQHandler - 0x080021b0 EXTI0_IRQHandler - 0x080021b0 I2C2_EV_IRQHandler - 0x080021b0 FPU_IRQHandler - 0x080021b0 TIM1_UP_TIM16_IRQHandler - 0x080021b0 SPI1_IRQHandler - 0x080021b0 CAN_SCE_IRQHandler - 0x080021b0 DMA2_Channel2_IRQHandler - 0x080021b0 DMA1_Channel4_IRQHandler - 0x080021b0 USART3_IRQHandler - 0x080021b0 DMA1_Channel7_IRQHandler - 0x080021b0 UART5_IRQHandler - 0x080021b0 TIM4_IRQHandler - 0x080021b0 I2C1_EV_IRQHandler - 0x080021b0 DMA1_Channel6_IRQHandler - 0x080021b0 UART4_IRQHandler - 0x080021b0 DMA2_Channel4_IRQHandler - 0x080021b0 TIM3_IRQHandler - 0x080021b0 RCC_IRQHandler - 0x080021b0 Default_Handler - 0x080021b0 USBWakeUp_RMP_IRQHandler - 0x080021b0 EXTI15_10_IRQHandler - 0x080021b0 EXTI9_5_IRQHandler - 0x080021b0 RTC_WKUP_IRQHandler - 0x080021b0 SPI2_IRQHandler - 0x080021b0 DMA2_Channel5_IRQHandler - 0x080021b0 DMA1_Channel5_IRQHandler - 0x080021b0 USB_LP_IRQHandler - 0x080021b0 EXTI4_IRQHandler - 0x080021b0 COMP1_2_IRQHandler - 0x080021b0 TIM1_TRG_COM_TIM17_IRQHandler - 0x080021b0 DMA1_Channel3_IRQHandler - 0x080021b0 WWDG_IRQHandler - 0x080021b0 TIM2_IRQHandler - 0x080021b0 EXTI1_IRQHandler - 0x080021b0 COMP4_6_IRQHandler - 0x080021b0 USART2_IRQHandler - 0x080021b0 I2C2_ER_IRQHandler - 0x080021b0 DMA1_Channel2_IRQHandler - 0x080021b0 FLASH_IRQHandler - 0x080021b0 USART1_IRQHandler - 0x080021b0 SPI3_IRQHandler - 0x080021b0 I2C1_ER_IRQHandler - 0x080021b0 USBWakeUp_IRQHandler - 0x080021b0 DMA2_Channel3_IRQHandler - 0x080021b0 EXTI2_TSC_IRQHandler - 0x080021b0 TIM1_BRK_TIM15_IRQHandler - *fill* 0x080021b2 0x2 + 0x0800224c 0x2 ./Core/Startup/startup_stm32f302rbtx.o + 0x0800224c RTC_Alarm_IRQHandler + 0x0800224c TIM1_CC_IRQHandler + 0x0800224c USB_HP_IRQHandler + 0x0800224c PVD_IRQHandler + 0x0800224c TAMP_STAMP_IRQHandler + 0x0800224c EXTI3_IRQHandler + 0x0800224c USB_HP_CAN_TX_IRQHandler + 0x0800224c EXTI0_IRQHandler + 0x0800224c I2C2_EV_IRQHandler + 0x0800224c FPU_IRQHandler + 0x0800224c TIM1_UP_TIM16_IRQHandler + 0x0800224c SPI1_IRQHandler + 0x0800224c CAN_SCE_IRQHandler + 0x0800224c DMA2_Channel2_IRQHandler + 0x0800224c DMA1_Channel4_IRQHandler + 0x0800224c USART3_IRQHandler + 0x0800224c DMA1_Channel7_IRQHandler + 0x0800224c UART5_IRQHandler + 0x0800224c TIM4_IRQHandler + 0x0800224c I2C1_EV_IRQHandler + 0x0800224c DMA1_Channel6_IRQHandler + 0x0800224c UART4_IRQHandler + 0x0800224c DMA2_Channel4_IRQHandler + 0x0800224c TIM3_IRQHandler + 0x0800224c RCC_IRQHandler + 0x0800224c Default_Handler + 0x0800224c USBWakeUp_RMP_IRQHandler + 0x0800224c EXTI15_10_IRQHandler + 0x0800224c EXTI9_5_IRQHandler + 0x0800224c RTC_WKUP_IRQHandler + 0x0800224c SPI2_IRQHandler + 0x0800224c DMA2_Channel5_IRQHandler + 0x0800224c DMA1_Channel5_IRQHandler + 0x0800224c USB_LP_IRQHandler + 0x0800224c EXTI4_IRQHandler + 0x0800224c COMP1_2_IRQHandler + 0x0800224c TIM1_TRG_COM_TIM17_IRQHandler + 0x0800224c DMA1_Channel3_IRQHandler + 0x0800224c WWDG_IRQHandler + 0x0800224c TIM2_IRQHandler + 0x0800224c EXTI1_IRQHandler + 0x0800224c COMP4_6_IRQHandler + 0x0800224c USART2_IRQHandler + 0x0800224c I2C2_ER_IRQHandler + 0x0800224c DMA1_Channel2_IRQHandler + 0x0800224c FLASH_IRQHandler + 0x0800224c USART1_IRQHandler + 0x0800224c SPI3_IRQHandler + 0x0800224c I2C1_ER_IRQHandler + 0x0800224c USBWakeUp_IRQHandler + 0x0800224c DMA2_Channel3_IRQHandler + 0x0800224c EXTI2_TSC_IRQHandler + 0x0800224c TIM1_BRK_TIM15_IRQHandler + *fill* 0x0800224e 0x2 .text.HAL_Init - 0x080021b4 0x2c ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.o - 0x080021b4 HAL_Init + 0x08002250 0x2c ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.o + 0x08002250 HAL_Init .text.HAL_InitTick - 0x080021e0 0x60 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.o - 0x080021e0 HAL_InitTick + 0x0800227c 0x60 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.o + 0x0800227c HAL_InitTick .text.HAL_IncTick - 0x08002240 0x28 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.o - 0x08002240 HAL_IncTick + 0x080022dc 0x28 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.o + 0x080022dc HAL_IncTick .text.HAL_GetTick - 0x08002268 0x18 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.o - 0x08002268 HAL_GetTick + 0x08002304 0x18 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.o + 0x08002304 HAL_GetTick .text.HAL_Delay - 0x08002280 0x48 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.o - 0x08002280 HAL_Delay + 0x0800231c 0x48 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.o + 0x0800231c HAL_Delay .text.HAL_ADC_ConvHalfCpltCallback - 0x080022c8 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.o - 0x080022c8 HAL_ADC_ConvHalfCpltCallback + 0x08002364 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.o + 0x08002364 HAL_ADC_ConvHalfCpltCallback .text.HAL_ADC_LevelOutOfWindowCallback - 0x080022dc 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.o - 0x080022dc HAL_ADC_LevelOutOfWindowCallback + 0x08002378 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.o + 0x08002378 HAL_ADC_LevelOutOfWindowCallback .text.HAL_ADC_ErrorCallback - 0x080022f0 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.o - 0x080022f0 HAL_ADC_ErrorCallback + 0x0800238c 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.o + 0x0800238c HAL_ADC_ErrorCallback .text.HAL_ADC_Init - 0x08002304 0x324 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.o - 0x08002304 HAL_ADC_Init + 0x080023a0 0x324 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.o + 0x080023a0 HAL_ADC_Init .text.HAL_ADC_Start_DMA - 0x08002628 0x1b4 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.o - 0x08002628 HAL_ADC_Start_DMA + 0x080026c4 0x1b4 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.o + 0x080026c4 HAL_ADC_Start_DMA .text.HAL_ADC_IRQHandler - 0x080027dc 0x3f4 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.o - 0x080027dc HAL_ADC_IRQHandler + 0x08002878 0x3f4 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.o + 0x08002878 HAL_ADC_IRQHandler .text.HAL_ADCEx_InjectedConvCpltCallback - 0x08002bd0 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.o - 0x08002bd0 HAL_ADCEx_InjectedConvCpltCallback + 0x08002c6c 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.o + 0x08002c6c HAL_ADCEx_InjectedConvCpltCallback .text.HAL_ADCEx_InjectedQueueOverflowCallback - 0x08002be4 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.o - 0x08002be4 HAL_ADCEx_InjectedQueueOverflowCallback + 0x08002c80 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.o + 0x08002c80 HAL_ADCEx_InjectedQueueOverflowCallback .text.HAL_ADCEx_LevelOutOfWindow2Callback - 0x08002bf8 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.o - 0x08002bf8 HAL_ADCEx_LevelOutOfWindow2Callback + 0x08002c94 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.o + 0x08002c94 HAL_ADCEx_LevelOutOfWindow2Callback .text.HAL_ADCEx_LevelOutOfWindow3Callback - 0x08002c0c 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.o - 0x08002c0c HAL_ADCEx_LevelOutOfWindow3Callback + 0x08002ca8 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.o + 0x08002ca8 HAL_ADCEx_LevelOutOfWindow3Callback .text.HAL_ADC_ConfigChannel - 0x08002c20 0x57c ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.o - 0x08002c20 HAL_ADC_ConfigChannel + 0x08002cbc 0x57c ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.o + 0x08002cbc HAL_ADC_ConfigChannel .text.HAL_ADCEx_MultiModeConfigChannel - 0x0800319c 0x18c ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.o - 0x0800319c HAL_ADCEx_MultiModeConfigChannel + 0x08003238 0x18c ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.o + 0x08003238 HAL_ADCEx_MultiModeConfigChannel .text.ADC_DMAConvCplt - 0x08003328 0x7a ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.o + 0x080033c4 0x7a ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.o .text.ADC_DMAHalfConvCplt - 0x080033a2 0x1c ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.o + 0x0800343e 0x1c ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.o .text.ADC_DMAError - 0x080033be 0x34 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.o - *fill* 0x080033f2 0x2 + 0x0800345a 0x34 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.o + *fill* 0x0800348e 0x2 .text.ADC_Enable - 0x080033f4 0xc8 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.o + 0x08003490 0xc8 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.o .text.ADC_Disable - 0x080034bc 0xcc ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.o + 0x08003558 0xcc ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.o .text.HAL_CAN_Init - 0x08003588 0x1f6 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o - 0x08003588 HAL_CAN_Init + 0x08003624 0x1f6 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o + 0x08003624 HAL_CAN_Init .text.HAL_CAN_ConfigFilter - 0x0800377e 0x194 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o - 0x0800377e HAL_CAN_ConfigFilter + 0x0800381a 0x194 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o + 0x0800381a HAL_CAN_ConfigFilter .text.HAL_CAN_Start - 0x08003912 0x88 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o - 0x08003912 HAL_CAN_Start + 0x080039ae 0x88 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o + 0x080039ae HAL_CAN_Start .text.HAL_CAN_AddTxMessage - 0x0800399a 0x1a0 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o - 0x0800399a HAL_CAN_AddTxMessage + 0x08003a36 0x1a0 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o + 0x08003a36 HAL_CAN_AddTxMessage .text.HAL_CAN_GetRxMessage - 0x08003b3a 0x244 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o - 0x08003b3a HAL_CAN_GetRxMessage + 0x08003bd6 0x244 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o + 0x08003bd6 HAL_CAN_GetRxMessage .text.HAL_CAN_ActivateNotification - 0x08003d7e 0x4c ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o - 0x08003d7e HAL_CAN_ActivateNotification + 0x08003e1a 0x4c ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o + 0x08003e1a HAL_CAN_ActivateNotification .text.HAL_CAN_IRQHandler - 0x08003dca 0x36e ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o - 0x08003dca HAL_CAN_IRQHandler + 0x08003e66 0x36e ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o + 0x08003e66 HAL_CAN_IRQHandler .text.HAL_CAN_TxMailbox0CompleteCallback - 0x08004138 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o - 0x08004138 HAL_CAN_TxMailbox0CompleteCallback + 0x080041d4 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o + 0x080041d4 HAL_CAN_TxMailbox0CompleteCallback .text.HAL_CAN_TxMailbox1CompleteCallback - 0x0800414c 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o - 0x0800414c HAL_CAN_TxMailbox1CompleteCallback + 0x080041e8 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o + 0x080041e8 HAL_CAN_TxMailbox1CompleteCallback .text.HAL_CAN_TxMailbox2CompleteCallback - 0x08004160 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o - 0x08004160 HAL_CAN_TxMailbox2CompleteCallback + 0x080041fc 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o + 0x080041fc HAL_CAN_TxMailbox2CompleteCallback .text.HAL_CAN_TxMailbox0AbortCallback - 0x08004174 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o - 0x08004174 HAL_CAN_TxMailbox0AbortCallback + 0x08004210 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o + 0x08004210 HAL_CAN_TxMailbox0AbortCallback .text.HAL_CAN_TxMailbox1AbortCallback - 0x08004188 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o - 0x08004188 HAL_CAN_TxMailbox1AbortCallback + 0x08004224 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o + 0x08004224 HAL_CAN_TxMailbox1AbortCallback .text.HAL_CAN_TxMailbox2AbortCallback - 0x0800419c 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o - 0x0800419c HAL_CAN_TxMailbox2AbortCallback + 0x08004238 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o + 0x08004238 HAL_CAN_TxMailbox2AbortCallback .text.HAL_CAN_RxFifo0FullCallback - 0x080041b0 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o - 0x080041b0 HAL_CAN_RxFifo0FullCallback + 0x0800424c 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o + 0x0800424c HAL_CAN_RxFifo0FullCallback .text.HAL_CAN_RxFifo1MsgPendingCallback - 0x080041c4 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o - 0x080041c4 HAL_CAN_RxFifo1MsgPendingCallback + 0x08004260 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o + 0x08004260 HAL_CAN_RxFifo1MsgPendingCallback .text.HAL_CAN_RxFifo1FullCallback - 0x080041d8 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o - 0x080041d8 HAL_CAN_RxFifo1FullCallback + 0x08004274 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o + 0x08004274 HAL_CAN_RxFifo1FullCallback .text.HAL_CAN_SleepCallback - 0x080041ec 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o - 0x080041ec HAL_CAN_SleepCallback + 0x08004288 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o + 0x08004288 HAL_CAN_SleepCallback .text.HAL_CAN_WakeUpFromRxMsgCallback - 0x08004200 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o - 0x08004200 HAL_CAN_WakeUpFromRxMsgCallback + 0x0800429c 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o + 0x0800429c HAL_CAN_WakeUpFromRxMsgCallback .text.HAL_CAN_ErrorCallback - 0x08004214 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o - 0x08004214 HAL_CAN_ErrorCallback + 0x080042b0 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o + 0x080042b0 HAL_CAN_ErrorCallback .text.__NVIC_SetPriorityGrouping - 0x08004228 0x48 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.o + 0x080042c4 0x48 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.o .text.__NVIC_GetPriorityGrouping - 0x08004270 0x1c ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.o + 0x0800430c 0x1c ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.o .text.__NVIC_EnableIRQ - 0x0800428c 0x3c ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.o + 0x08004328 0x3c ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.o .text.__NVIC_SetPriority - 0x080042c8 0x54 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.o + 0x08004364 0x54 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.o .text.NVIC_EncodePriority - 0x0800431c 0x66 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.o - *fill* 0x08004382 0x2 + 0x080043b8 0x66 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.o + *fill* 0x0800441e 0x2 .text.SysTick_Config - 0x08004384 0x44 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.o + 0x08004420 0x44 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.o .text.HAL_NVIC_SetPriorityGrouping - 0x080043c8 0x16 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.o - 0x080043c8 HAL_NVIC_SetPriorityGrouping + 0x08004464 0x16 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.o + 0x08004464 HAL_NVIC_SetPriorityGrouping .text.HAL_NVIC_SetPriority - 0x080043de 0x38 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.o - 0x080043de HAL_NVIC_SetPriority + 0x0800447a 0x38 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.o + 0x0800447a HAL_NVIC_SetPriority .text.HAL_NVIC_EnableIRQ - 0x08004416 0x1c ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.o - 0x08004416 HAL_NVIC_EnableIRQ + 0x080044b2 0x1c ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.o + 0x080044b2 HAL_NVIC_EnableIRQ .text.HAL_SYSTICK_Config - 0x08004432 0x18 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.o - 0x08004432 HAL_SYSTICK_Config + 0x080044ce 0x18 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.o + 0x080044ce HAL_SYSTICK_Config .text.HAL_DMA_Init - 0x0800444a 0x8e ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.o - 0x0800444a HAL_DMA_Init + 0x080044e6 0x8e ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.o + 0x080044e6 HAL_DMA_Init .text.HAL_DMA_Start_IT - 0x080044d8 0xbe ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.o - 0x080044d8 HAL_DMA_Start_IT + 0x08004574 0xbe ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.o + 0x08004574 HAL_DMA_Start_IT .text.HAL_DMA_IRQHandler - 0x08004596 0x146 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.o - 0x08004596 HAL_DMA_IRQHandler + 0x08004632 0x146 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.o + 0x08004632 HAL_DMA_IRQHandler .text.DMA_SetConfig - 0x080046dc 0x5c ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.o + 0x08004778 0x5c ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.o .text.DMA_CalcBaseAndBitshift - 0x08004738 0x78 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.o + 0x080047d4 0x78 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.o .text.HAL_GPIO_Init - 0x080047b0 0x2f4 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.o - 0x080047b0 HAL_GPIO_Init + 0x0800484c 0x2f4 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.o + 0x0800484c HAL_GPIO_Init .text.HAL_GPIO_WritePin - 0x08004aa4 0x30 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.o - 0x08004aa4 HAL_GPIO_WritePin + 0x08004b40 0x30 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.o + 0x08004b40 HAL_GPIO_WritePin .text.HAL_RCC_OscConfig - 0x08004ad4 0x107c ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.o - 0x08004ad4 HAL_RCC_OscConfig + 0x08004b70 0x107c ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.o + 0x08004b70 HAL_RCC_OscConfig .text.HAL_RCC_ClockConfig - 0x08005b50 0x2f8 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.o - 0x08005b50 HAL_RCC_ClockConfig + 0x08005bec 0x2f8 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.o + 0x08005bec HAL_RCC_ClockConfig .text.HAL_RCC_GetSysClockFreq - 0x08005e48 0xac ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.o - 0x08005e48 HAL_RCC_GetSysClockFreq + 0x08005ee4 0xac ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.o + 0x08005ee4 HAL_RCC_GetSysClockFreq .text.HAL_RCC_GetHCLKFreq - 0x08005ef4 0x18 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.o - 0x08005ef4 HAL_RCC_GetHCLKFreq + 0x08005f90 0x18 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.o + 0x08005f90 HAL_RCC_GetHCLKFreq .text.HAL_RCC_GetPCLK1Freq - 0x08005f0c 0x44 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.o - 0x08005f0c HAL_RCC_GetPCLK1Freq + 0x08005fa8 0x44 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.o + 0x08005fa8 HAL_RCC_GetPCLK1Freq .text.HAL_RCC_GetPCLK2Freq - 0x08005f50 0x44 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.o - 0x08005f50 HAL_RCC_GetPCLK2Freq + 0x08005fec 0x44 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.o + 0x08005fec HAL_RCC_GetPCLK2Freq .text.HAL_RCCEx_PeriphCLKConfig - 0x08005f94 0x324 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.o - 0x08005f94 HAL_RCCEx_PeriphCLKConfig + 0x08006030 0x324 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.o + 0x08006030 HAL_RCCEx_PeriphCLKConfig .text.HAL_TIM_Base_Init - 0x080062b8 0xae ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.o - 0x080062b8 HAL_TIM_Base_Init - *fill* 0x08006366 0x2 + 0x08006354 0xae ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.o + 0x08006354 HAL_TIM_Base_Init + *fill* 0x08006402 0x2 .text.HAL_TIM_Base_Start - 0x08006368 0xb4 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.o - 0x08006368 HAL_TIM_Base_Start + 0x08006404 0xb4 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.o + 0x08006404 HAL_TIM_Base_Start .text.HAL_TIM_IRQHandler - 0x0800641c 0x204 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.o - 0x0800641c HAL_TIM_IRQHandler + 0x080064b8 0x204 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.o + 0x080064b8 HAL_TIM_IRQHandler .text.HAL_TIM_PeriodElapsedCallback - 0x08006620 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.o - 0x08006620 HAL_TIM_PeriodElapsedCallback + 0x080066bc 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.o + 0x080066bc HAL_TIM_PeriodElapsedCallback .text.HAL_TIM_OC_DelayElapsedCallback - 0x08006634 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.o - 0x08006634 HAL_TIM_OC_DelayElapsedCallback + 0x080066d0 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.o + 0x080066d0 HAL_TIM_OC_DelayElapsedCallback .text.HAL_TIM_IC_CaptureCallback - 0x08006648 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.o - 0x08006648 HAL_TIM_IC_CaptureCallback + 0x080066e4 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.o + 0x080066e4 HAL_TIM_IC_CaptureCallback .text.HAL_TIM_PWM_PulseFinishedCallback - 0x0800665c 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.o - 0x0800665c HAL_TIM_PWM_PulseFinishedCallback + 0x080066f8 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.o + 0x080066f8 HAL_TIM_PWM_PulseFinishedCallback .text.HAL_TIM_TriggerCallback - 0x08006670 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.o - 0x08006670 HAL_TIM_TriggerCallback + 0x0800670c 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.o + 0x0800670c HAL_TIM_TriggerCallback .text.TIM_Base_SetConfig - 0x08006684 0x11c ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.o - 0x08006684 TIM_Base_SetConfig + 0x08006720 0x11c ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.o + 0x08006720 TIM_Base_SetConfig .text.HAL_TIMEx_MasterConfigSynchronization - 0x080067a0 0xe8 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.o - 0x080067a0 HAL_TIMEx_MasterConfigSynchronization + 0x0800683c 0xe8 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.o + 0x0800683c HAL_TIMEx_MasterConfigSynchronization .text.HAL_TIMEx_CommutCallback - 0x08006888 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.o - 0x08006888 HAL_TIMEx_CommutCallback + 0x08006924 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.o + 0x08006924 HAL_TIMEx_CommutCallback .text.HAL_TIMEx_BreakCallback - 0x0800689c 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.o - 0x0800689c HAL_TIMEx_BreakCallback + 0x08006938 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.o + 0x08006938 HAL_TIMEx_BreakCallback .text.HAL_TIMEx_Break2Callback - 0x080068b0 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.o - 0x080068b0 HAL_TIMEx_Break2Callback + 0x0800694c 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.o + 0x0800694c HAL_TIMEx_Break2Callback .text.HAL_UART_Init - 0x080068c4 0x9c ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.o - 0x080068c4 HAL_UART_Init + 0x08006960 0x9c ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.o + 0x08006960 HAL_UART_Init .text.UART_SetConfig - 0x08006960 0x3a8 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.o - 0x08006960 UART_SetConfig + 0x080069fc 0x3a8 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.o + 0x080069fc UART_SetConfig .text.UART_AdvFeatureConfig - 0x08006d08 0x144 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.o - 0x08006d08 UART_AdvFeatureConfig + 0x08006da4 0x144 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.o + 0x08006da4 UART_AdvFeatureConfig .text.UART_CheckIdleState - 0x08006e4c 0x150 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.o - 0x08006e4c UART_CheckIdleState + 0x08006ee8 0x150 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.o + 0x08006ee8 UART_CheckIdleState .text.UART_WaitOnFlagUntilTimeout - 0x08006f9c 0xda ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.o - 0x08006f9c UART_WaitOnFlagUntilTimeout + 0x08007038 0xda ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.o + 0x08007038 UART_WaitOnFlagUntilTimeout .text.UART_EndRxTransfer - 0x08007076 0xc8 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.o - .text.memset 0x0800713e 0x10 C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.1.0.202410251130/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-memset.o) - 0x0800713e memset - *fill* 0x0800714e 0x2 + 0x08007112 0xc8 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.o + .text.memset 0x080071da 0x10 C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.1.0.202410251130/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-memset.o) + 0x080071da memset + *fill* 0x080071ea 0x2 .text.__libc_init_array - 0x08007150 0x48 C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.1.0.202410251130/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-init.o) - 0x08007150 __libc_init_array + 0x080071ec 0x48 C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.1.0.202410251130/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-init.o) + 0x080071ec __libc_init_array *(.glue_7) - .glue_7 0x08007198 0x0 linker stubs + .glue_7 0x08007234 0x0 linker stubs *(.glue_7t) - .glue_7t 0x08007198 0x0 linker stubs + .glue_7t 0x08007234 0x0 linker stubs *(.eh_frame) - .eh_frame 0x08007198 0x0 C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.1.0.202410251130/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+fp/hard/crtbegin.o + .eh_frame 0x08007234 0x0 C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.1.0.202410251130/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+fp/hard/crtbegin.o *(.init) - .init 0x08007198 0x4 C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.1.0.202410251130/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+fp/hard/crti.o - 0x08007198 _init - .init 0x0800719c 0x8 C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.1.0.202410251130/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+fp/hard/crtn.o + .init 0x08007234 0x4 C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.1.0.202410251130/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+fp/hard/crti.o + 0x08007234 _init + .init 0x08007238 0x8 C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.1.0.202410251130/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+fp/hard/crtn.o *(.fini) - .fini 0x080071a4 0x4 C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.1.0.202410251130/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+fp/hard/crti.o - 0x080071a4 _fini - .fini 0x080071a8 0x8 C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.1.0.202410251130/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+fp/hard/crtn.o - 0x080071b0 . = ALIGN (0x4) - 0x080071b0 _etext = . + .fini 0x08007240 0x4 C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.1.0.202410251130/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+fp/hard/crti.o + 0x08007240 _fini + .fini 0x08007244 0x8 C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.1.0.202410251130/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+fp/hard/crtn.o + 0x0800724c . = ALIGN (0x4) + 0x0800724c _etext = . -.vfp11_veneer 0x080071b0 0x0 - .vfp11_veneer 0x080071b0 0x0 linker stubs +.vfp11_veneer 0x0800724c 0x0 + .vfp11_veneer 0x0800724c 0x0 linker stubs -.v4_bx 0x080071b0 0x0 - .v4_bx 0x080071b0 0x0 linker stubs +.v4_bx 0x0800724c 0x0 + .v4_bx 0x0800724c 0x0 linker stubs -.iplt 0x080071b0 0x0 - .iplt 0x080071b0 0x0 C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.1.0.202410251130/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+fp/hard/crtbegin.o +.iplt 0x0800724c 0x0 + .iplt 0x0800724c 0x0 C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.1.0.202410251130/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+fp/hard/crtbegin.o -.rodata 0x080071b0 0x38 - 0x080071b0 . = ALIGN (0x4) +.rodata 0x0800724c 0x38 + 0x0800724c . = ALIGN (0x4) *(.rodata) *(.rodata*) .rodata.AHBPrescTable - 0x080071b0 0x10 ./Core/Src/system_stm32f3xx.o - 0x080071b0 AHBPrescTable + 0x0800724c 0x10 ./Core/Src/system_stm32f3xx.o + 0x0800724c AHBPrescTable .rodata.APBPrescTable - 0x080071c0 0x8 ./Core/Src/system_stm32f3xx.o - 0x080071c0 APBPrescTable + 0x0800725c 0x8 ./Core/Src/system_stm32f3xx.o + 0x0800725c APBPrescTable .rodata.aPLLMULFactorTable - 0x080071c8 0x10 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.o + 0x08007264 0x10 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.o .rodata.aPredivFactorTable - 0x080071d8 0x10 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.o - 0x080071e8 . = ALIGN (0x4) + 0x08007274 0x10 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.o + 0x08007284 . = ALIGN (0x4) -.ARM.extab 0x080071e8 0x0 - 0x080071e8 . = ALIGN (0x4) +.ARM.extab 0x08007284 0x0 + 0x08007284 . = ALIGN (0x4) *(.ARM.extab* .gnu.linkonce.armextab.*) - 0x080071e8 . = ALIGN (0x4) + 0x08007284 . = ALIGN (0x4) -.ARM 0x080071e8 0x0 - 0x080071e8 . = ALIGN (0x4) - 0x080071e8 __exidx_start = . +.ARM 0x08007284 0x0 + 0x08007284 . = ALIGN (0x4) + 0x08007284 __exidx_start = . *(.ARM.exidx*) - 0x080071e8 __exidx_end = . - 0x080071e8 . = ALIGN (0x4) + 0x08007284 __exidx_end = . + 0x08007284 . = ALIGN (0x4) -.preinit_array 0x080071e8 0x0 - 0x080071e8 . = ALIGN (0x4) - 0x080071e8 PROVIDE (__preinit_array_start = .) +.preinit_array 0x08007284 0x0 + 0x08007284 . = ALIGN (0x4) + 0x08007284 PROVIDE (__preinit_array_start = .) *(.preinit_array*) - 0x080071e8 PROVIDE (__preinit_array_end = .) - 0x080071e8 . = ALIGN (0x4) + 0x08007284 PROVIDE (__preinit_array_end = .) + 0x08007284 . = ALIGN (0x4) -.init_array 0x080071e8 0x4 - 0x080071e8 . = ALIGN (0x4) - 0x080071e8 PROVIDE (__init_array_start = .) +.init_array 0x08007284 0x4 + 0x08007284 . = ALIGN (0x4) + 0x08007284 PROVIDE (__init_array_start = .) *(SORT_BY_NAME(.init_array.*)) *(.init_array*) - .init_array 0x080071e8 0x4 C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.1.0.202410251130/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+fp/hard/crtbegin.o - 0x080071ec PROVIDE (__init_array_end = .) - 0x080071ec . = ALIGN (0x4) + .init_array 0x08007284 0x4 C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.1.0.202410251130/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+fp/hard/crtbegin.o + 0x08007288 PROVIDE (__init_array_end = .) + 0x08007288 . = ALIGN (0x4) -.fini_array 0x080071ec 0x4 - 0x080071ec . = ALIGN (0x4) +.fini_array 0x08007288 0x4 + 0x08007288 . = ALIGN (0x4) [!provide] PROVIDE (__fini_array_start = .) *(SORT_BY_NAME(.fini_array.*)) *(.fini_array*) - .fini_array 0x080071ec 0x4 C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.1.0.202410251130/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+fp/hard/crtbegin.o + .fini_array 0x08007288 0x4 C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.1.0.202410251130/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+fp/hard/crtbegin.o [!provide] PROVIDE (__fini_array_end = .) - 0x080071f0 . = ALIGN (0x4) - 0x080071f0 _sidata = LOADADDR (.data) + 0x0800728c . = ALIGN (0x4) + 0x0800728c _sidata = LOADADDR (.data) -.rel.dyn 0x080071f0 0x0 - .rel.iplt 0x080071f0 0x0 C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.1.0.202410251130/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+fp/hard/crtbegin.o +.rel.dyn 0x0800728c 0x0 + .rel.iplt 0x0800728c 0x0 C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.1.0.202410251130/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+fp/hard/crtbegin.o -.data 0x20000000 0xc load address 0x080071f0 +.data 0x20000000 0xc load address 0x0800728c 0x20000000 . = ALIGN (0x4) 0x20000000 _sdata = . *(.data) @@ -4905,11 +4904,11 @@ LOAD C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.ext *fill* 0x20000009 0x3 0x2000000c _edata = . -.igot.plt 0x2000000c 0x0 load address 0x080071fc +.igot.plt 0x2000000c 0x0 load address 0x08007298 .igot.plt 0x2000000c 0x0 C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.1.0.202410251130/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+fp/hard/crtbegin.o 0x2000000c . = ALIGN (0x4) -.bss 0x2000000c 0x300 load address 0x080071fc +.bss 0x2000000c 0x2f4 load address 0x08007298 0x2000000c _sbss = . 0x2000000c __bss_start__ = _sbss *(.bss) @@ -4920,7 +4919,7 @@ LOAD C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.ext .bss.canmsg_received 0x2000002c 0x1 ./Core/Src/can_communication.o 0x2000002c canmsg_received - .bss.additionaltxcounter.1 + .bss.additionaltxcounter.0 0x2000002d 0x1 ./Core/Src/can_communication.o *fill* 0x2000002e 0x2 .bss.hcan 0x20000030 0x4 ./Core/Src/can_halal.o @@ -4975,29 +4974,28 @@ LOAD C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.ext .bss.inhibit_SDC 0x200002f0 0x4 ./Core/Src/main.o 0x200002f0 inhibit_SDC - .bss.error_data - 0x200002f4 0x10 ./Core/Src/plausibility_check.o - 0x200002f4 error_data + .bss.error 0x200002f4 0x2 ./Core/Src/plausibility_check.o + 0x200002f4 error + *fill* 0x200002f6 0x2 .bss.HAL_RCC_ADC12_CLK_ENABLED - 0x20000304 0x4 ./Core/Src/stm32f3xx_hal_msp.o - .bss.uwTick 0x20000308 0x4 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.o - 0x20000308 uwTick + 0x200002f8 0x4 ./Core/Src/stm32f3xx_hal_msp.o + .bss.uwTick 0x200002fc 0x4 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.o + 0x200002fc uwTick *(COMMON) - 0x2000030c . = ALIGN (0x4) - 0x2000030c _ebss = . - 0x2000030c __bss_end__ = _ebss + 0x20000300 . = ALIGN (0x4) + 0x20000300 _ebss = . + 0x20000300 __bss_end__ = _ebss ._user_heap_stack - 0x2000030c 0x604 load address 0x080071fc - 0x20000310 . = ALIGN (0x8) - *fill* 0x2000030c 0x4 + 0x20000300 0x600 load address 0x08007298 + 0x20000300 . = ALIGN (0x8) [!provide] PROVIDE (end = .) - 0x20000310 PROVIDE (_end = .) - 0x20000510 . = (. + _Min_Heap_Size) - *fill* 0x20000310 0x200 - 0x20000910 . = (. + _Min_Stack_Size) - *fill* 0x20000510 0x400 - 0x20000910 . = ALIGN (0x8) + 0x20000300 PROVIDE (_end = .) + 0x20000500 . = (. + _Min_Heap_Size) + *fill* 0x20000300 0x200 + 0x20000900 . = (. + _Min_Stack_Size) + *fill* 0x20000500 0x400 + 0x20000900 . = ALIGN (0x8) /DISCARD/ libc.a(*) @@ -5073,53 +5071,53 @@ LOAD C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.ext LOAD C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.1.0.202410251130/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libm.a LOAD C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.1.0.202410251130/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+fp/hard\libgcc.a -.debug_info 0x00000000 0x15769 - .debug_info 0x00000000 0x8e7 ./Core/Src/can_communication.o - .debug_info 0x000008e7 0xa24 ./Core/Src/can_halal.o - .debug_info 0x0000130b 0x458 ./Core/Src/channel_control.o - .debug_info 0x00001763 0xe73 ./Core/Src/current_monitoring.o - .debug_info 0x000025d6 0x1e74 ./Core/Src/main.o - .debug_info 0x0000444a 0x330 ./Core/Src/plausibility_check.o - .debug_info 0x0000477a 0x182c ./Core/Src/stm32f3xx_hal_msp.o - .debug_info 0x00005fa6 0xebb ./Core/Src/stm32f3xx_it.o - .debug_info 0x00006e61 0x407 ./Core/Src/system_stm32f3xx.o - .debug_info 0x00007268 0x30 ./Core/Startup/startup_stm32f302rbtx.o - .debug_info 0x00007298 0x7a4 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.o - .debug_info 0x00007a3c 0xb32 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.o - .debug_info 0x0000856e 0x15b2 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.o - .debug_info 0x00009b20 0xf0a ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o - .debug_info 0x0000aa2a 0xcb4 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.o - .debug_info 0x0000b6de 0x6e1 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.o - .debug_info 0x0000bdbf 0x5fe ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.o - .debug_info 0x0000c3bd 0x148a ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.o - .debug_info 0x0000d847 0x59d ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.o - .debug_info 0x0000dde4 0x2a70 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.o - .debug_info 0x00010854 0x156d ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.o - .debug_info 0x00011dc1 0x39a8 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.o +.debug_info 0x00000000 0x15a5c + .debug_info 0x00000000 0xa50 ./Core/Src/can_communication.o + .debug_info 0x00000a50 0xa24 ./Core/Src/can_halal.o + .debug_info 0x00001474 0x458 ./Core/Src/channel_control.o + .debug_info 0x000018cc 0xe73 ./Core/Src/current_monitoring.o + .debug_info 0x0000273f 0x1e8e ./Core/Src/main.o + .debug_info 0x000045cd 0x4a0 ./Core/Src/plausibility_check.o + .debug_info 0x00004a6d 0x182c ./Core/Src/stm32f3xx_hal_msp.o + .debug_info 0x00006299 0xebb ./Core/Src/stm32f3xx_it.o + .debug_info 0x00007154 0x407 ./Core/Src/system_stm32f3xx.o + .debug_info 0x0000755b 0x30 ./Core/Startup/startup_stm32f302rbtx.o + .debug_info 0x0000758b 0x7a4 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.o + .debug_info 0x00007d2f 0xb32 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.o + .debug_info 0x00008861 0x15b2 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.o + .debug_info 0x00009e13 0xf0a ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o + .debug_info 0x0000ad1d 0xcb4 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.o + .debug_info 0x0000b9d1 0x6e1 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.o + .debug_info 0x0000c0b2 0x5fe ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.o + .debug_info 0x0000c6b0 0x148a ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.o + .debug_info 0x0000db3a 0x59d ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.o + .debug_info 0x0000e0d7 0x2a70 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.o + .debug_info 0x00010b47 0x156d ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.o + .debug_info 0x000120b4 0x39a8 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.o -.debug_abbrev 0x00000000 0x2f63 - .debug_abbrev 0x00000000 0x23f ./Core/Src/can_communication.o - .debug_abbrev 0x0000023f 0x276 ./Core/Src/can_halal.o - .debug_abbrev 0x000004b5 0x1ca ./Core/Src/channel_control.o - .debug_abbrev 0x0000067f 0x222 ./Core/Src/current_monitoring.o - .debug_abbrev 0x000008a1 0x399 ./Core/Src/main.o - .debug_abbrev 0x00000c3a 0x119 ./Core/Src/plausibility_check.o - .debug_abbrev 0x00000d53 0x28c ./Core/Src/stm32f3xx_hal_msp.o - .debug_abbrev 0x00000fdf 0x21d ./Core/Src/stm32f3xx_it.o - .debug_abbrev 0x000011fc 0x11a ./Core/Src/system_stm32f3xx.o - .debug_abbrev 0x00001316 0x24 ./Core/Startup/startup_stm32f302rbtx.o - .debug_abbrev 0x0000133a 0x215 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.o - .debug_abbrev 0x0000154f 0x186 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.o - .debug_abbrev 0x000016d5 0x28e ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.o - .debug_abbrev 0x00001963 0x21e ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o - .debug_abbrev 0x00001b81 0x31e ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.o - .debug_abbrev 0x00001e9f 0x20d ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.o - .debug_abbrev 0x000020ac 0x1ca ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.o - .debug_abbrev 0x00002276 0x300 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.o - .debug_abbrev 0x00002576 0x221 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.o - .debug_abbrev 0x00002797 0x278 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.o - .debug_abbrev 0x00002a0f 0x283 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.o - .debug_abbrev 0x00002c92 0x2d1 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.o +.debug_abbrev 0x00000000 0x2f4b + .debug_abbrev 0x00000000 0x23c ./Core/Src/can_communication.o + .debug_abbrev 0x0000023c 0x276 ./Core/Src/can_halal.o + .debug_abbrev 0x000004b2 0x1ca ./Core/Src/channel_control.o + .debug_abbrev 0x0000067c 0x222 ./Core/Src/current_monitoring.o + .debug_abbrev 0x0000089e 0x399 ./Core/Src/main.o + .debug_abbrev 0x00000c37 0x104 ./Core/Src/plausibility_check.o + .debug_abbrev 0x00000d3b 0x28c ./Core/Src/stm32f3xx_hal_msp.o + .debug_abbrev 0x00000fc7 0x21d ./Core/Src/stm32f3xx_it.o + .debug_abbrev 0x000011e4 0x11a ./Core/Src/system_stm32f3xx.o + .debug_abbrev 0x000012fe 0x24 ./Core/Startup/startup_stm32f302rbtx.o + .debug_abbrev 0x00001322 0x215 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.o + .debug_abbrev 0x00001537 0x186 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.o + .debug_abbrev 0x000016bd 0x28e ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.o + .debug_abbrev 0x0000194b 0x21e ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o + .debug_abbrev 0x00001b69 0x31e ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.o + .debug_abbrev 0x00001e87 0x20d ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.o + .debug_abbrev 0x00002094 0x1ca ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.o + .debug_abbrev 0x0000225e 0x300 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.o + .debug_abbrev 0x0000255e 0x221 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.o + .debug_abbrev 0x0000277f 0x278 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.o + .debug_abbrev 0x000029f7 0x283 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.o + .debug_abbrev 0x00002c7a 0x2d1 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.o .debug_aranges 0x00000000 0x1148 .debug_aranges @@ -5168,53 +5166,53 @@ LOAD C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.ext 0x00000f20 0x228 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.o .debug_rnglists - 0x00000000 0xd75 + 0x00000000 0xd74 .debug_rnglists - 0x00000000 0x27 ./Core/Src/can_communication.o + 0x00000000 0x26 ./Core/Src/can_communication.o .debug_rnglists - 0x00000027 0x46 ./Core/Src/can_halal.o + 0x00000026 0x46 ./Core/Src/can_halal.o .debug_rnglists - 0x0000006d 0x1a ./Core/Src/channel_control.o + 0x0000006c 0x1a ./Core/Src/channel_control.o .debug_rnglists - 0x00000087 0x20 ./Core/Src/current_monitoring.o + 0x00000086 0x20 ./Core/Src/current_monitoring.o .debug_rnglists - 0x000000a7 0x4e ./Core/Src/main.o + 0x000000a6 0x4e ./Core/Src/main.o .debug_rnglists - 0x000000f5 0x14 ./Core/Src/plausibility_check.o + 0x000000f4 0x14 ./Core/Src/plausibility_check.o .debug_rnglists - 0x00000109 0x47 ./Core/Src/stm32f3xx_hal_msp.o + 0x00000108 0x47 ./Core/Src/stm32f3xx_hal_msp.o .debug_rnglists - 0x00000150 0x67 ./Core/Src/stm32f3xx_it.o + 0x0000014f 0x67 ./Core/Src/stm32f3xx_it.o .debug_rnglists - 0x000001b7 0x1a ./Core/Src/system_stm32f3xx.o + 0x000001b6 0x1a ./Core/Src/system_stm32f3xx.o .debug_rnglists - 0x000001d1 0x19 ./Core/Startup/startup_stm32f302rbtx.o + 0x000001d0 0x19 ./Core/Startup/startup_stm32f302rbtx.o .debug_rnglists - 0x000001ea 0xa3 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.o + 0x000001e9 0xa3 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.o .debug_rnglists - 0x0000028d 0x91 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.o + 0x0000028c 0x91 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.o .debug_rnglists - 0x0000031e 0x126 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.o + 0x0000031d 0x126 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.o .debug_rnglists - 0x00000444 0xee ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o + 0x00000443 0xee ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o .debug_rnglists - 0x00000532 0xda ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.o + 0x00000531 0xda ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.o .debug_rnglists - 0x0000060c 0x69 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.o + 0x0000060b 0x69 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.o .debug_rnglists - 0x00000675 0x3f ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.o + 0x00000674 0x3f ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.o .debug_rnglists - 0x000006b4 0x66 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.o + 0x000006b3 0x66 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.o .debug_rnglists - 0x0000071a 0x28 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.o + 0x00000719 0x28 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.o .debug_rnglists - 0x00000742 0x328 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.o + 0x00000741 0x328 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.o .debug_rnglists - 0x00000a6a 0x131 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.o + 0x00000a69 0x131 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.o .debug_rnglists - 0x00000b9b 0x1da ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.o + 0x00000b9a 0x1da ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.o -.debug_macro 0x00000000 0x1ea20 +.debug_macro 0x00000000 0x1ea2e .debug_macro 0x00000000 0x23b ./Core/Src/can_communication.o .debug_macro 0x0000023b 0xab4 ./Core/Src/can_communication.o .debug_macro 0x00000cef 0x16a ./Core/Src/can_communication.o @@ -5287,93 +5285,93 @@ LOAD C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.ext .debug_macro 0x0001c18a 0x1a2 ./Core/Src/channel_control.o .debug_macro 0x0001c32c 0x242 ./Core/Src/current_monitoring.o .debug_macro 0x0001c56e 0x34 ./Core/Src/current_monitoring.o - .debug_macro 0x0001c5a2 0x238 ./Core/Src/main.o - .debug_macro 0x0001c7da 0x19c ./Core/Src/main.o - .debug_macro 0x0001c976 0x235 ./Core/Src/plausibility_check.o - .debug_macro 0x0001cbab 0x209 ./Core/Src/stm32f3xx_hal_msp.o - .debug_macro 0x0001cdb4 0x213 ./Core/Src/stm32f3xx_it.o - .debug_macro 0x0001cfc7 0x1fa ./Core/Src/system_stm32f3xx.o - .debug_macro 0x0001d1c1 0x21e ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.o - .debug_macro 0x0001d3df 0x1fb ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.o - .debug_macro 0x0001d5da 0x224 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.o - .debug_macro 0x0001d7fe 0x209 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o - .debug_macro 0x0001da07 0x1fa ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.o - .debug_macro 0x0001dc01 0x1fa ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.o - .debug_macro 0x0001ddfb 0x201 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.o - .debug_macro 0x0001dffc 0x21e ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.o - .debug_macro 0x0001e21a 0x1fa ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.o - .debug_macro 0x0001e414 0x1fb ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.o - .debug_macro 0x0001e60f 0x1fa ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.o - .debug_macro 0x0001e809 0x217 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.o + .debug_macro 0x0001c5a2 0x246 ./Core/Src/main.o + .debug_macro 0x0001c7e8 0x19c ./Core/Src/main.o + .debug_macro 0x0001c984 0x235 ./Core/Src/plausibility_check.o + .debug_macro 0x0001cbb9 0x209 ./Core/Src/stm32f3xx_hal_msp.o + .debug_macro 0x0001cdc2 0x213 ./Core/Src/stm32f3xx_it.o + .debug_macro 0x0001cfd5 0x1fa ./Core/Src/system_stm32f3xx.o + .debug_macro 0x0001d1cf 0x21e ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.o + .debug_macro 0x0001d3ed 0x1fb ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.o + .debug_macro 0x0001d5e8 0x224 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.o + .debug_macro 0x0001d80c 0x209 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o + .debug_macro 0x0001da15 0x1fa ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.o + .debug_macro 0x0001dc0f 0x1fa ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.o + .debug_macro 0x0001de09 0x201 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.o + .debug_macro 0x0001e00a 0x21e ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.o + .debug_macro 0x0001e228 0x1fa ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.o + .debug_macro 0x0001e422 0x1fb ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.o + .debug_macro 0x0001e61d 0x1fa ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.o + .debug_macro 0x0001e817 0x217 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.o -.debug_line 0x00000000 0x170ef - .debug_line 0x00000000 0x9ee ./Core/Src/can_communication.o - .debug_line 0x000009ee 0xadb ./Core/Src/can_halal.o - .debug_line 0x000014c9 0x8c3 ./Core/Src/channel_control.o - .debug_line 0x00001d8c 0x942 ./Core/Src/current_monitoring.o - .debug_line 0x000026ce 0xba0 ./Core/Src/main.o - .debug_line 0x0000326e 0x95f ./Core/Src/plausibility_check.o - .debug_line 0x00003bcd 0x9a8 ./Core/Src/stm32f3xx_hal_msp.o - .debug_line 0x00004575 0x90d ./Core/Src/stm32f3xx_it.o - .debug_line 0x00004e82 0x833 ./Core/Src/system_stm32f3xx.o - .debug_line 0x000056b5 0x7a ./Core/Startup/startup_stm32f302rbtx.o - .debug_line 0x0000572f 0xa6b ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.o - .debug_line 0x0000619a 0x9a9 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.o - .debug_line 0x00006b43 0x2149 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.o - .debug_line 0x00008c8c 0x1245 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o - .debug_line 0x00009ed1 0xd58 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.o - .debug_line 0x0000ac29 0xd79 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.o - .debug_line 0x0000b9a2 0xbe2 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.o - .debug_line 0x0000c584 0x1400 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.o - .debug_line 0x0000d984 0xd2d ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.o - .debug_line 0x0000e6b1 0x3d97 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.o - .debug_line 0x00012448 0x1b09 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.o - .debug_line 0x00013f51 0x319e ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.o +.debug_line 0x00000000 0x170a9 + .debug_line 0x00000000 0x982 ./Core/Src/can_communication.o + .debug_line 0x00000982 0xadb ./Core/Src/can_halal.o + .debug_line 0x0000145d 0x8c1 ./Core/Src/channel_control.o + .debug_line 0x00001d1e 0x942 ./Core/Src/current_monitoring.o + .debug_line 0x00002660 0xbba ./Core/Src/main.o + .debug_line 0x0000321a 0x96d ./Core/Src/plausibility_check.o + .debug_line 0x00003b87 0x9a8 ./Core/Src/stm32f3xx_hal_msp.o + .debug_line 0x0000452f 0x90d ./Core/Src/stm32f3xx_it.o + .debug_line 0x00004e3c 0x833 ./Core/Src/system_stm32f3xx.o + .debug_line 0x0000566f 0x7a ./Core/Startup/startup_stm32f302rbtx.o + .debug_line 0x000056e9 0xa6b ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.o + .debug_line 0x00006154 0x9a9 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.o + .debug_line 0x00006afd 0x2149 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.o + .debug_line 0x00008c46 0x1245 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o + .debug_line 0x00009e8b 0xd58 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.o + .debug_line 0x0000abe3 0xd79 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.o + .debug_line 0x0000b95c 0xbe2 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.o + .debug_line 0x0000c53e 0x1400 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.o + .debug_line 0x0000d93e 0xd2d ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.o + .debug_line 0x0000e66b 0x3d97 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.o + .debug_line 0x00012402 0x1b09 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.o + .debug_line 0x00013f0b 0x319e ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.o -.debug_str 0x00000000 0xb7d41 - .debug_str 0x00000000 0xaf7d0 ./Core/Src/can_communication.o - 0xafebf (size before relaxing) - .debug_str 0x000af7d0 0x33ac ./Core/Src/can_halal.o +.debug_str 0x00000000 0xb7e00 + .debug_str 0x00000000 0xaf88f ./Core/Src/can_communication.o + 0xaffda (size before relaxing) + .debug_str 0x000af88f 0x33ac ./Core/Src/can_halal.o 0xb2e52 (size before relaxing) - .debug_str 0x000b2b7c 0x65e ./Core/Src/channel_control.o - 0xb001e (size before relaxing) - .debug_str 0x000b31da 0x770 ./Core/Src/current_monitoring.o - 0xb09a7 (size before relaxing) - .debug_str 0x000b394a 0xa9d ./Core/Src/main.o - 0xb167b (size before relaxing) - .debug_str 0x000b43e7 0x21 ./Core/Src/plausibility_check.o - 0xafaf5 (size before relaxing) - .debug_str 0x000b4408 0x12a ./Core/Src/stm32f3xx_hal_msp.o + .debug_str 0x000b2c3b 0x65e ./Core/Src/channel_control.o + 0xb0031 (size before relaxing) + .debug_str 0x000b3299 0x770 ./Core/Src/current_monitoring.o + 0xb09ba (size before relaxing) + .debug_str 0x000b3a09 0xa9d ./Core/Src/main.o + 0xb16cd (size before relaxing) + .debug_str 0x000b44a6 0x21 ./Core/Src/plausibility_check.o + 0xafc1c (size before relaxing) + .debug_str 0x000b44c7 0x12a ./Core/Src/stm32f3xx_hal_msp.o 0xb0e72 (size before relaxing) - .debug_str 0x000b4532 0x15a ./Core/Src/stm32f3xx_it.o + .debug_str 0x000b45f1 0x15a ./Core/Src/stm32f3xx_it.o 0xb0792 (size before relaxing) - .debug_str 0x000b468c 0xdf ./Core/Src/system_stm32f3xx.o + .debug_str 0x000b474b 0xdf ./Core/Src/system_stm32f3xx.o 0xaf83c (size before relaxing) - .debug_str 0x000b476b 0x44 ./Core/Startup/startup_stm32f302rbtx.o + .debug_str 0x000b482a 0x44 ./Core/Startup/startup_stm32f302rbtx.o 0x8d (size before relaxing) - .debug_str 0x000b47af 0x38b ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.o + .debug_str 0x000b486e 0x38b ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.o 0xb0013 (size before relaxing) - .debug_str 0x000b4b3a 0x1bf ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.o + .debug_str 0x000b4bf9 0x1bf ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.o 0xafe29 (size before relaxing) - .debug_str 0x000b4cf9 0x6c8 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.o + .debug_str 0x000b4db8 0x6c8 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.o 0xb0542 (size before relaxing) - .debug_str 0x000b53c1 0x3ee ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o + .debug_str 0x000b5480 0x3ee ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o 0xaffcb (size before relaxing) - .debug_str 0x000b57af 0x358 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.o + .debug_str 0x000b586e 0x358 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.o 0xb0097 (size before relaxing) - .debug_str 0x000b5b07 0x1fa ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.o + .debug_str 0x000b5bc6 0x1fa ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.o 0xafb84 (size before relaxing) - .debug_str 0x000b5d01 0x12b ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.o + .debug_str 0x000b5dc0 0x12b ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.o 0xaf9b2 (size before relaxing) - .debug_str 0x000b5e2c 0x2b8 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.o + .debug_str 0x000b5eeb 0x2b8 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.o 0xafcdc (size before relaxing) - .debug_str 0x000b60e4 0xbe ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.o + .debug_str 0x000b61a3 0xbe ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.o 0xafa79 (size before relaxing) - .debug_str 0x000b61a2 0xe66 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.o + .debug_str 0x000b6261 0xe66 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.o 0xb0c73 (size before relaxing) - .debug_str 0x000b7008 0x4dc ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.o + .debug_str 0x000b70c7 0x4dc ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.o 0xb04b9 (size before relaxing) - .debug_str 0x000b74e4 0x85d ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.o + .debug_str 0x000b75a3 0x85d ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.o 0xb055f (size before relaxing) .comment 0x00000000 0x43 @@ -5400,33 +5398,33 @@ LOAD C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.ext .comment 0x00000043 0x44 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.o .comment 0x00000043 0x44 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.o -.debug_frame 0x00000000 0x4948 +.debug_frame 0x00000000 0x494c .debug_frame 0x00000000 0xa0 ./Core/Src/can_communication.o .debug_frame 0x000000a0 0x178 ./Core/Src/can_halal.o .debug_frame 0x00000218 0x50 ./Core/Src/channel_control.o .debug_frame 0x00000268 0x7c ./Core/Src/current_monitoring.o .debug_frame 0x000002e4 0x158 ./Core/Src/main.o - .debug_frame 0x0000043c 0x30 ./Core/Src/plausibility_check.o - .debug_frame 0x0000046c 0x15c ./Core/Src/stm32f3xx_hal_msp.o - .debug_frame 0x000005c8 0x1ac ./Core/Src/stm32f3xx_it.o - .debug_frame 0x00000774 0x58 ./Core/Src/system_stm32f3xx.o - .debug_frame 0x000007cc 0x334 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.o - .debug_frame 0x00000b00 0x380 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.o - .debug_frame 0x00000e80 0x638 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.o - .debug_frame 0x000014b8 0x5a0 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o - .debug_frame 0x00001a58 0x4e8 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.o - .debug_frame 0x00001f40 0x224 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.o - .debug_frame 0x00002164 0x14c ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.o - .debug_frame 0x000022b0 0x214 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.o - .debug_frame 0x000024c4 0xb0 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.o - .debug_frame 0x00002574 0x1218 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.o - .debug_frame 0x0000378c 0x688 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.o - .debug_frame 0x00003e14 0x9e8 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.o - .debug_frame 0x000047fc 0x20 C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.1.0.202410251130/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-memset.o) - .debug_frame 0x0000481c 0x2c C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.1.0.202410251130/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-init.o) - .debug_frame 0x00004848 0x30 C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.1.0.202410251130/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+fp/hard\libgcc.a(_arm_muldf3.o) - .debug_frame 0x00004878 0xac C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.1.0.202410251130/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+fp/hard\libgcc.a(_arm_addsubdf3.o) - .debug_frame 0x00004924 0x24 C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.1.0.202410251130/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+fp/hard\libgcc.a(_arm_fixunsdfsi.o) + .debug_frame 0x0000043c 0x34 ./Core/Src/plausibility_check.o + .debug_frame 0x00000470 0x15c ./Core/Src/stm32f3xx_hal_msp.o + .debug_frame 0x000005cc 0x1ac ./Core/Src/stm32f3xx_it.o + .debug_frame 0x00000778 0x58 ./Core/Src/system_stm32f3xx.o + .debug_frame 0x000007d0 0x334 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.o + .debug_frame 0x00000b04 0x380 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.o + .debug_frame 0x00000e84 0x638 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.o + .debug_frame 0x000014bc 0x5a0 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o + .debug_frame 0x00001a5c 0x4e8 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.o + .debug_frame 0x00001f44 0x224 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.o + .debug_frame 0x00002168 0x14c ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.o + .debug_frame 0x000022b4 0x214 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.o + .debug_frame 0x000024c8 0xb0 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.o + .debug_frame 0x00002578 0x1218 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.o + .debug_frame 0x00003790 0x688 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.o + .debug_frame 0x00003e18 0x9e8 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.o + .debug_frame 0x00004800 0x20 C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.1.0.202410251130/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-memset.o) + .debug_frame 0x00004820 0x2c C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.1.0.202410251130/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-init.o) + .debug_frame 0x0000484c 0x30 C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.1.0.202410251130/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+fp/hard\libgcc.a(_arm_muldf3.o) + .debug_frame 0x0000487c 0xac C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.1.0.202410251130/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+fp/hard\libgcc.a(_arm_addsubdf3.o) + .debug_frame 0x00004928 0x24 C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.1.0.202410251130/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+fp/hard\libgcc.a(_arm_fixunsdfsi.o) .debug_line_str 0x00000000 0x71