From 26aa408e960233b7e59ab7d67784347a16d0a107 Mon Sep 17 00:00:00 2001 From: Janek Date: Thu, 13 Mar 2025 21:08:45 +0100 Subject: [PATCH] implemented current and voltage monitoring (currently NOT tested) --- Software/Code/Core/Inc/can_communication.h | 6 +- Software/Code/Core/Inc/current_monitoring.h | 51 + Software/Code/Core/Src/can_communication.c | 61 +- Software/Code/Core/Src/current_monitoring.c | 94 + Software/Code/Core/Src/main.c | 12 +- Software/Code/Debug/Core/Src/main.cyclo | 20 +- Software/Code/Debug/Core/Src/main.o | Bin 1002680 -> 1002796 bytes Software/Code/Debug/Core/Src/main.su | 18 +- Software/Code/Debug/PDU_FT25.elf | Bin 1128200 -> 1128228 bytes Software/Code/Debug/PDU_FT25.list | 18787 +++++++++--------- Software/Code/Debug/PDU_FT25.map | 674 +- 11 files changed, 9977 insertions(+), 9746 deletions(-) create mode 100644 Software/Code/Core/Inc/current_monitoring.h create mode 100644 Software/Code/Core/Src/current_monitoring.c diff --git a/Software/Code/Core/Inc/can_communication.h b/Software/Code/Core/Inc/can_communication.h index 161223b..3b144f0 100644 --- a/Software/Code/Core/Inc/can_communication.h +++ b/Software/Code/Core/Inc/can_communication.h @@ -10,16 +10,16 @@ #include "channel_control.h" #include "can_halal.h" -//#include "current_monitoring.h" +#include "current_monitoring.h" #define RX_STATUS_HEARTBEAT 0xC7 // IDs of all CAN-packages (may be other IDs next year) -#define RX_STATUS_MSG_ID 0xC8 // TODO: check new IDs +#define RX_STATUS_MSG_ID 0xC8 #define TX_STATUS_MSG_ID 0xC9 #define CUR_CHANNELS_1_ID 0xCA #define CUR_CHANNELS_2_ID 0xCB #define CUR_CHANNELS_3_ID 0xCC #define CUR_CHANNELS_4_ID 0xCD -#define LV_SENS_ID 0xCE +//#define LV_SENS_ID 0xCE // not used typedef struct { // TODO: add error-codes enable_gpios iostatus; diff --git a/Software/Code/Core/Inc/current_monitoring.h b/Software/Code/Core/Inc/current_monitoring.h new file mode 100644 index 0000000..fce8f65 --- /dev/null +++ b/Software/Code/Core/Inc/current_monitoring.h @@ -0,0 +1,51 @@ +/* + * current_monitoring.h + * + * Created on: Mar 13, 2025 + * Author: janek + */ + +#ifndef INC_CURRENT_MONITORING_H_ +#define INC_CURRENT_MONITORING_H_ + +#include "stm32f3xx_hal.h" + +// convert ADC quants to V +#define ADC_V_FACTOR (3.3f / 4096) // 3.3V / 12bit +// scale to LV by divider to mV +#define LV_SENSE_FACTOR (1e3 * (ADC_V_FACTOR * ((12.f + 1.8f) / 1.8f))) +#define PC_VSENSE_FACTOR (1e3 * (ADC_V_FACTOR * ((100.f + 10.f) / 10.f))); + +// convert ADC quants to I_S in mA +#define CURR_SENSE_IS_FACTOR_9A (ADC_V_FACTOR / 1.2f) // 3.3V / 12bit / 1.2kOhm +#define CURR_SENSE_IS_FACTOR_4_5A (ADC_V_FACTOR / 1.f) +#define CURR_SENSE_IS_FACTOR_1A (ADC_V_FACTOR / 4.f) +// convert ADC quants to I_L in mA +#define CURR_SENSE_FACTOR_1A (300 * CURR_SENSE_IS_FACTOR) // typical current sense ratio (datasheet PROFET) +#define CURR_SENSE_FACTOR_4_5A (1500 * CURR_SENSE_IS_FACTOR) +#define CURR_SENSE_FACTOR_9A (3900 * CURR_SENSE_IS_FACTOR) + +typedef struct { + uint16_t acc_cooling; + uint16_t ts_cooling; + uint16_t drs; + uint16_t acu; + uint16_t epsc; + uint16_t inverter; + uint16_t lidar; + uint16_t misc; + uint16_t alwayson; + uint16_t sdc; + uint16_t ebs1; + uint16_t ebs2; + uint16_t ebs3; + uint16_t epsc_precharge; + uint16_t lvms_v; + uint16_t asms_v; +} current_measurements; + +void current_monitor_init(ADC_HandleTypeDef* hadc1, ADC_HandleTypeDef* hadc2, TIM_HandleTypeDef* trigtim); + +uint8_t current_monitor_checklimits(); + +#endif /* INC_CURRENT_MONITORING_H_ */ diff --git a/Software/Code/Core/Src/can_communication.c b/Software/Code/Core/Src/can_communication.c index e862821..d76aab7 100644 --- a/Software/Code/Core/Src/can_communication.c +++ b/Software/Code/Core/Src/can_communication.c @@ -7,7 +7,7 @@ #include "can_communication.h" #include "channel_control.h" -//#include "current_monitoring.h" +#include "current_monitoring.h" rx_status_frame rxstate = {}; volatile uint8_t canmsg_received = 0; @@ -23,14 +23,69 @@ void can_init(CAN_HandleTypeDef* hcan){ } void can_sendloop(){ - //static uint8_t additionaltxcounter = 0; + static uint8_t additionaltxcounter = 0; uint8_t status_data[3]; status_data[0] = update_ports.porta.porta; status_data[1] = update_ports.portb.portb; status_data[2] = !inhibit_SDC; ftcan_transmit(TX_STATUS_MSG_ID, status_data, 3); - // TODO: implement transmission of current and voltage measurements + + uint8_t data[8]; + + switch (additionaltxcounter) { + case 0: + data[0] = current_measurements_adc_val.alwayson >> 8; + data[1] = current_measurements_adc_val.alwayson & 0xFF; + data[2] = current_measurements_adc_val.misc >> 8; + data[3] = current_measurements_adc_val.misc & 0xFF; + data[4] = current_measurements_adc_val.inverter >> 8; + data[5] = current_measurements_adc_val.inverter & 0xFF; + data[6] = current_measurements_adc_val.sdc >> 8; + data[7] = current_measurements_adc_val.sdc & 0xFF; + ftcan_transmit(CUR_CHANNELS_1_ID, data, 8); + break; + + case 1: + data[0] = current_measurements_adc_val.acc_cooling >> 8; + data[1] = current_measurements_adc_val.acc_cooling & 0xFF; + data[2] = current_measurements_adc_val.ts_cooling >> 8; + data[3] = current_measurements_adc_val.ts_cooling & 0xFF; + data[4] = current_measurements_adc_val.acu >> 8; + data[5] = current_measurements_adc_val.acu & 0xFF; + data[6] = current_measurements_adc_val.epsc >> 8; + data[7] = current_measurements_adc_val.epsc & 0xFF; + ftcan_transmit(CUR_CHANNELS_2_ID, data, 8); + break; + + case 2: + data[0] = current_measurements_adc_val.ebs1 >> 8; + data[1] = current_measurements_adc_val.ebs1 & 0xFF; + data[2] = current_measurements_adc_val.ebs2 >> 8; + data[3] = current_measurements_adc_val.ebs2 & 0xFF; + data[4] = current_measurements_adc_val.ebs3 >> 8; + data[5] = current_measurements_adc_val.ebs3 & 0xFF; + data[6] = current_measurements_adc_val.drs >> 8; + data[7] = current_measurements_adc_val.drs & 0xFF; + ftcan_transmit(CUR_CHANNLES_3_ID, data, 8); + break; + + case 3: + data[0] = current_measurements_adc_val.lidar >> 8; + data[1] = current_measurements_adc_val.lidar & 0xFF; + data[2] = current_measurements_adc_val.lvms_v >> 8; + data[3] = current_measurements_adc_val.lvms_v & 0xFF; + data[4] = current_measurements_adc_val.asms_v >> 8; + data[5] = current_measurements_adc_val.asms_v & 0xFF; + data[6] = 0x01; // not used (transmits 313) + data[7] = 0x39; // not used (transmits 313) + ftcan_transmit(CUR_CHANNELS_4_ID, data, 8); + break; + + default: + break; + } + additionaltxcounter = (additionaltxcounter + 1) % 4; } void ftcan_msg_received_cb(uint16_t id, size_t datalen, const uint8_t* data){ diff --git a/Software/Code/Core/Src/current_monitoring.c b/Software/Code/Core/Src/current_monitoring.c new file mode 100644 index 0000000..fae46e6 --- /dev/null +++ b/Software/Code/Core/Src/current_monitoring.c @@ -0,0 +1,94 @@ +/* + * current_monitoring.c + * + * Created on: Mar 13, 2025 + * Author: janek + */ + +#include "current_monitoring.h" +#include "main.h" + +volatile union adc1_channels { + struct { + uint16_t lvms_vsense; // LVMS-Vsense + uint16_t isense1; // acc-cooling + uint16_t isense2; // ts-cooling + uint16_t isense9; // always on + uint16_t isense11; // ebs1, ebs2, ebs3 (DSEL0, DSEL1) + uint16_t asms_vsense; // ASMS-Vsense + uint16_t isense10; // sdc + uint16_t isense6; // inverter + } adcbank1; + uint16_t adcbuffer[8]; +} adc_channels1; + +volatile union adc2_channels { + struct { + uint16_t isense3; // drs + uint16_t isense8; // misc + uint16_t isense4; // acu + uint16_t isense5; // epsc + uint16_t pc_read; // precharge voltage epsc + uint16_t isense7; // lidar + } adcbank2; + uint16_t adcbuffer[6]; +} adc_channels2; + +current_measurements current_measurements_adc_val; + +GPIO_PinState valve2 = GPIO_PIN_RESET; +GPIO_PinState valve3 = GPIO_PIN_RESET; + +ADC_HandleTypeDef* adc1; +ADC_HandleTypeDef* adc2; + +void current_monitor_init(ADC_HandleTypeDef* hadc1, ADC_HandleTypeDef* hadc2, TIM_HandleTypeDef* trigtim) { + HAL_GPIO_WritePin(DSEL0_GPIO_Port, DSEL0_Pin, valve3); + HAL_GPIO_WritePin(DSEL1_GPIO_Port, DSEL1_Pin, valve2); + adc1 = hadc1; + adc2 = hadc2; + HAL_TIM_Base_Start(trigtim); + HAL_ADC_Start_DMA(hadc1, (uint32_t*)adc_channels1.adcbuffer, 6); + HAL_ADC_Start_DMA(hadc2, (uint32_t*)adc_channels2.adcbuffer, 5); +} + +uint8_t current_monitor_checklimits() {return 0;} // TODO: implement properly + +void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) { + if (hadc == adc1){ + if (valve2 == GPIO_PIN_RESET && valve3 == GPIO_PIN_RESET){ + current_measurement_adc_val.ebs1 = adc_channels1.adcbank1.isense11 * CURR_SENSE_FACTOR_1A; + valve2 = GPIO_PIN_SET; + } + if (valve2 == GPIO_PIN_SET && valve3 == GPIO_PIN_RESET){ + current_measurement_adc_val.ebs2 = adc_channels1.adcbank1.isense11 * CURR_SENSE_FACTOR_1A; + valve2 = GPIO_PIN_RESET; + valve3 = GPIO_PIN_SET; + } + if (valve2 == GPIO_PIN_RESET && valve3 == GPIO_PIN_SET){ + current_measurement_adc_val.ebs3 = adc_channels1.adcbank1.isense11 * CURR_SENSE_FACTOR_1A; + valve3 = GPIO_PIN_RESET; + } + } + else { + current_measurement_adc_val.lvms_v = adc_channels1.adcbank1.lvms_vsense * LV_SENSE_FACTOR; + current_measurement_adc_val.acc_cooling = adc_channels1.adcbank1.isense1 * CURR_SENSE_FACTOR_9A; + current_measurement_adc_val.ts_cooling = adc_channels1.adcbank1.isense2 * CURR_SENSE_FACTOR_9A; + current_measurement_adc_val.alwayson = adc_channels1.adcbank1.isense9 * CURR_SENSE_FACTOR_9A; + current_measurement_adc_val.asms_v = adc_channels1.adcbank1.asms_vsense * LV_SENSE_FACTOR; + current_measurement_adc_val.sdc = adc_channels1.adcbank1.isense10 * CURR_SENSE_FACTOR_4_5A; + current_measurement_adc_val.inverter = adc_channels1.adcbank1.isense6 * CURR_SENSE_FACTOR_9A; + + HAL_GPIO_WritePin(DSEL0_GPIO_Port, DSEL0_Pin, valve3); + HAL_GPIO_WritePin(DSEL1_GPIO_Port, DSEL1_Pin, valve2); + } + if (hadc == adc2){ + current_measurement_adc_val.drs = adc_channels2.adcbank2.isense3 * CURR_SENSE_FACTOR_4_5A; + current_measurement_adc_val.misc = adc_channels2.adcbank2.isense8 * CURR_SENSE_FACTOR_4_5A; + current_measurement_adc_val.acu = adc_channels2.adcbank2.isense4 * CURR_SENSE_FACTOR_9A; + current_measurement_adc_val.epsc = adc_channels2.adcbank2.isense5 * CURR_SENSE_FACTOR_9A; + current_measurement_adc_val.epsc_precharge = adc_channels2.adcbank2.pc_read * PC_VSENSE_FACTOR; + current_measurement_adc_val.lidar = adc_channels2.adcbank2.isense7 * CURR_SENSE_FACTOR_4_5A; + } +} + diff --git a/Software/Code/Core/Src/main.c b/Software/Code/Core/Src/main.c index af73eb0..69a2053 100644 --- a/Software/Code/Core/Src/main.c +++ b/Software/Code/Core/Src/main.c @@ -71,7 +71,8 @@ static void MX_TIM6_Init(void); /* Private user code ---------------------------------------------------------*/ /* USER CODE BEGIN 0 */ -// adc buffer +uint16_t adc1_buffer[7]; +uint16_t adc2_buffer[7]; extern rx_status_frame rxstate; extern volatile uint8_t canmsg_received; @@ -145,7 +146,7 @@ int main(void) ChannelControl_init(); can_init(&hcan); - // currentMonitor initialisieren + current_monitor_init(&hadc1, &hadc2, &htim6); uint32_t lasttick = HAL_GetTick(); // Zeit in ms seit Start @@ -168,10 +169,15 @@ int main(void) lasttick = HAL_GetTick(); can_sendloop(); } - //watchdog (auch Status-LED an schalten) + if (((HAL_GetTick() - lastheartbeat) > 125U) && (HAL_GetTick() > 1000U)) { + inhibit_SDC = 1; + } HAL_GPIO_WritePin(LED1_GPIO_Port, LED1_Pin, (GPIO_PinState)!update_ports.portb.sdc); // indicates open SDC + HAL_GPIO_WritePin(LED2_GPIO_Port, LED2_Pin, (GPIO_PinState)inhibit_SDC); // indicates watchdog-status // overcurrent check (wenn funktioniert, LED schalten) ChannelControl_UpdateGPIOs(update_ports); + + current_monitor_checklimits(); // currently not implemented } /* USER CODE END 3 */ } diff --git a/Software/Code/Debug/Core/Src/main.cyclo b/Software/Code/Debug/Core/Src/main.cyclo index 4baa8ed..19201e7 100644 --- a/Software/Code/Debug/Core/Src/main.cyclo +++ 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b/Software/Code/Debug/PDU_FT25.list index 31b1d64..ffbdea2 100644 --- a/Software/Code/Debug/PDU_FT25.list +++ b/Software/Code/Debug/PDU_FT25.list @@ -5,25 +5,25 @@ Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 00000188 08000000 08000000 00001000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA - 1 .text 00005ce4 08000188 08000188 00001188 2**2 + 1 .text 00005d1c 08000188 08000188 00001188 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE - 2 .rodata 00000038 08005e6c 08005e6c 00006e6c 2**2 + 2 .rodata 00000038 08005ea4 08005ea4 00006ea4 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA - 3 .ARM.extab 00000000 08005ea4 08005ea4 0000700c 2**0 + 3 .ARM.extab 00000000 08005edc 08005edc 0000700c 2**0 CONTENTS - 4 .ARM 00000000 08005ea4 08005ea4 0000700c 2**0 + 4 .ARM 00000000 08005edc 08005edc 0000700c 2**0 CONTENTS - 5 .preinit_array 00000000 08005ea4 08005ea4 0000700c 2**0 + 5 .preinit_array 00000000 08005edc 08005edc 0000700c 2**0 CONTENTS, ALLOC, LOAD, DATA - 6 .init_array 00000004 08005ea4 08005ea4 00006ea4 2**2 + 6 .init_array 00000004 08005edc 08005edc 00006edc 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA - 7 .fini_array 00000004 08005ea8 08005ea8 00006ea8 2**2 + 7 .fini_array 00000004 08005ee0 08005ee0 00006ee0 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA - 8 .data 0000000c 20000000 08005eac 00007000 2**2 + 8 .data 0000000c 20000000 08005ee4 00007000 2**2 CONTENTS, ALLOC, LOAD, DATA - 9 .bss 000002ac 2000000c 08005eb8 0000700c 2**2 + 9 .bss 000002ac 2000000c 08005ef0 0000700c 2**2 ALLOC - 10 ._user_heap_stack 00000600 200002b8 08005eb8 000072b8 2**0 + 10 ._user_heap_stack 00000600 200002b8 08005ef0 000072b8 2**0 ALLOC 11 .ARM.attributes 00000030 00000000 00000000 0000700c 2**0 CONTENTS, READONLY @@ -37,15 +37,15 @@ Idx Name Size VMA LMA File off Algn CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_macro 0001e4dd 00000000 00000000 0001fe1d 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS - 17 .debug_line 00015c26 00000000 00000000 0003e2fa 2**0 + 17 .debug_line 00015c41 00000000 00000000 0003e2fa 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS - 18 .debug_str 000b7783 00000000 00000000 00053f20 2**0 + 18 .debug_str 000b7783 00000000 00000000 00053f3b 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS - 19 .comment 00000043 00000000 00000000 0010b6a3 2**0 + 19 .comment 00000043 00000000 00000000 0010b6be 2**0 CONTENTS, READONLY - 20 .debug_frame 0000472c 00000000 00000000 0010b6e8 2**2 + 20 .debug_frame 0000472c 00000000 00000000 0010b704 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS - 21 .debug_line_str 00000071 00000000 00000000 0010fe14 2**0 + 21 .debug_line_str 00000071 00000000 00000000 0010fe30 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: @@ -64,7 +64,7 @@ Disassembly of section .text: 800019e: bd10 pop {r4, pc} 80001a0: 2000000c .word 0x2000000c 80001a4: 00000000 .word 0x00000000 - 80001a8: 08005e54 .word 0x08005e54 + 80001a8: 08005e8c .word 0x08005e8c 080001ac : 80001ac: b508 push {r3, lr} @@ -76,7 +76,7 @@ Disassembly of section .text: 80001ba: bd08 pop {r3, pc} 80001bc: 00000000 .word 0x00000000 80001c0: 20000010 .word 0x20000010 - 80001c4: 08005e54 .word 0x08005e54 + 80001c4: 08005e8c .word 0x08005e8c 080001c8 : @@ -190,7 +190,7 @@ void ftcan_msg_received_cb(uint16_t id, size_t datalen, const uint8_t* data){ 8000266: 2bc7 cmp r3, #199 @ 0xc7 8000268: d107 bne.n 800027a lastheartbeat = HAL_GetTick(); - 800026a: f001 f8c5 bl 80013f8 + 800026a: f001 f8e1 bl 8001430 800026e: 4603 mov r3, r0 8000270: 4a06 ldr r2, [pc, #24] @ (800028c ) 8000272: 6013 str r3, [r2, #0] @@ -232,7 +232,7 @@ HAL_StatusTypeDef ftcan_init(CAN_HandleTypeDef *handle) { 80002a4: 681b ldr r3, [r3, #0] 80002a6: 2102 movs r1, #2 80002a8: 4618 mov r0, r3 - 80002aa: f002 fc8c bl 8002bc6 + 80002aa: f002 fca8 bl 8002bfe 80002ae: 4603 mov r3, r0 80002b0: 73fb strb r3, [r7, #15] if (status != HAL_OK) { @@ -248,7 +248,7 @@ HAL_StatusTypeDef ftcan_init(CAN_HandleTypeDef *handle) { 80002bc: 4b04 ldr r3, [pc, #16] @ (80002d0 ) 80002be: 681b ldr r3, [r3, #0] 80002c0: 4618 mov r0, r3 - 80002c2: f002 fa4a bl 800275a + 80002c2: f002 fa66 bl 8002792 80002c6: 4603 mov r3, r0 } 80002c8: 4618 mov r0, r3 @@ -292,7 +292,7 @@ HAL_StatusTypeDef ftcan_transmit(uint16_t id, const uint8_t *data, 80002fe: f107 0314 add.w r3, r7, #20 8000302: 68ba ldr r2, [r7, #8] 8000304: 4903 ldr r1, [pc, #12] @ (8000314 ) - 8000306: f002 fa6c bl 80027e2 + 8000306: f002 fa88 bl 800281a 800030a: 4603 mov r3, r0 } 800030c: 4618 mov r0, r3 @@ -400,7 +400,7 @@ HAL_StatusTypeDef ftcan_add_filter(uint16_t id, uint16_t mask) { 80003a0: 681b ldr r3, [r3, #0] 80003a2: 490a ldr r1, [pc, #40] @ (80003cc ) 80003a4: 4618 mov r0, r3 - 80003a6: f002 f90e bl 80025c6 + 80003a6: f002 f92a bl 80025fe 80003aa: 4603 mov r3, r0 80003ac: 73fb strb r3, [r7, #15] if (status == HAL_OK) { @@ -448,7 +448,7 @@ void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *handle) { 80003ea: f107 030c add.w r3, r7, #12 80003ee: f107 0214 add.w r2, r7, #20 80003f2: 2100 movs r1, #0 - 80003f4: f002 fac5 bl 8002982 + 80003f4: f002 fae1 bl 80029ba 80003f8: 4603 mov r3, r0 80003fa: 2b00 cmp r3, #0 80003fc: d10d bne.n 800041a @@ -541,7 +541,7 @@ void ChannelControl_UpdateGPIOs(enable_gpios UpdatePorts){ 8000478: 2201 movs r2, #1 800047a: f44f 7100 mov.w r1, #512 @ 0x200 800047e: 4860 ldr r0, [pc, #384] @ (8000600 ) - 8000480: f003 f9a8 bl 80037d4 + 8000480: f003 f9c4 bl 800380c } HAL_GPIO_WritePin(IN1_GPIO_Port, IN1_Pin, (GPIO_PinState)UpdatePorts.porta.acc_cooling); // Acc-Cooling 8000484: 793b ldrb r3, [r7, #4] @@ -550,7 +550,7 @@ void ChannelControl_UpdateGPIOs(enable_gpios UpdatePorts){ 800048c: 461a mov r2, r3 800048e: f44f 7100 mov.w r1, #512 @ 0x200 8000492: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 - 8000496: f003 f99d bl 80037d4 + 8000496: f003 f9b9 bl 800380c HAL_GPIO_WritePin(IN2_GPIO_Port, IN2_Pin, (GPIO_PinState)UpdatePorts.porta.ts_cooling); // TS-Cooling 800049a: 793b ldrb r3, [r7, #4] 800049c: f3c3 0340 ubfx r3, r3, #1, #1 @@ -558,7 +558,7 @@ void ChannelControl_UpdateGPIOs(enable_gpios UpdatePorts){ 80004a2: 461a mov r2, r3 80004a4: f44f 7180 mov.w r1, #256 @ 0x100 80004a8: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 - 80004ac: f003 f992 bl 80037d4 + 80004ac: f003 f9ae bl 800380c HAL_GPIO_WritePin(IN3_GPIO_Port, IN3_Pin, (GPIO_PinState)UpdatePorts.porta.drs); // DRS 80004b0: 793b ldrb r3, [r7, #4] 80004b2: f3c3 0380 ubfx r3, r3, #2, #1 @@ -566,7 +566,7 @@ void ChannelControl_UpdateGPIOs(enable_gpios UpdatePorts){ 80004b8: 461a mov r2, r3 80004ba: f44f 5180 mov.w r1, #4096 @ 0x1000 80004be: 4851 ldr r0, [pc, #324] @ (8000604 ) - 80004c0: f003 f988 bl 80037d4 + 80004c0: f003 f9a4 bl 800380c HAL_GPIO_WritePin(IN4_GPIO_Port, IN4_Pin, (GPIO_PinState)UpdatePorts.porta.acu); // ACU 80004c4: 793b ldrb r3, [r7, #4] 80004c6: f3c3 03c0 ubfx r3, r3, #3, #1 @@ -574,7 +574,7 @@ void ChannelControl_UpdateGPIOs(enable_gpios UpdatePorts){ 80004cc: 461a mov r2, r3 80004ce: f44f 4100 mov.w r1, #32768 @ 0x8000 80004d2: 484c ldr r0, [pc, #304] @ (8000604 ) - 80004d4: f003 f97e bl 80037d4 + 80004d4: f003 f99a bl 800380c if (prev_epsc_state == 0 && ((UpdatePorts.porta.porta >> 4) & 1) == 1){ // will be replaced by precharge 80004d8: 4b4b ldr r3, [pc, #300] @ (8000608 ) 80004da: 681b ldr r3, [r3, #0] @@ -590,10 +590,10 @@ void ChannelControl_UpdateGPIOs(enable_gpios UpdatePorts){ 80004ee: 2201 movs r2, #1 80004f0: 2180 movs r1, #128 @ 0x80 80004f2: 4843 ldr r0, [pc, #268] @ (8000600 ) - 80004f4: f003 f96e bl 80037d4 + 80004f4: f003 f98a bl 800380c HAL_Delay(2000); // contiuosly read precharge voltage 80004f8: f44f 60fa mov.w r0, #2000 @ 0x7d0 - 80004fc: f000 ff88 bl 8001410 + 80004fc: f000 ffa4 bl 8001448 HAL_GPIO_WritePin(IN5_GPIO_Port, IN5_Pin, (GPIO_PinState)UpdatePorts.porta.epsc); // if precharge voltage > 95% 24V enable PROFET 8000500: 793b ldrb r3, [r7, #4] 8000502: f3c3 1300 ubfx r3, r3, #4, #1 @@ -601,15 +601,15 @@ void ChannelControl_UpdateGPIOs(enable_gpios UpdatePorts){ 8000508: 461a mov r2, r3 800050a: f44f 4180 mov.w r1, #16384 @ 0x4000 800050e: 483d ldr r0, [pc, #244] @ (8000604 ) - 8000510: f003 f960 bl 80037d4 + 8000510: f003 f97c bl 800380c HAL_Delay(100); // after few ms disengage precharge 8000514: 2064 movs r0, #100 @ 0x64 - 8000516: f000 ff7b bl 8001410 + 8000516: f000 ff97 bl 8001448 HAL_GPIO_WritePin(LED3_GPIO_Port, LED3_Pin, 0); 800051a: 2200 movs r2, #0 800051c: 2180 movs r1, #128 @ 0x80 800051e: 4838 ldr r0, [pc, #224] @ (8000600 ) - 8000520: f003 f958 bl 80037d4 + 8000520: f003 f974 bl 800380c prev_epsc_state = UpdatePorts.porta.epsc; 8000524: 793b ldrb r3, [r7, #4] 8000526: f3c3 1300 ubfx r3, r3, #4, #1 @@ -627,7 +627,7 @@ void ChannelControl_UpdateGPIOs(enable_gpios UpdatePorts){ 800053c: 461a mov r2, r3 800053e: f44f 4180 mov.w r1, #16384 @ 0x4000 8000542: 4830 ldr r0, [pc, #192] @ (8000604 ) - 8000544: f003 f946 bl 80037d4 + 8000544: f003 f962 bl 800380c prev_epsc_state = UpdatePorts.porta.epsc; 8000548: 793b ldrb r3, [r7, #4] 800054a: f3c3 1300 ubfx r3, r3, #4, #1 @@ -643,7 +643,7 @@ void ChannelControl_UpdateGPIOs(enable_gpios UpdatePorts){ 800055e: 461a mov r2, r3 8000560: f44f 6180 mov.w r1, #1024 @ 0x400 8000564: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 - 8000568: f003 f934 bl 80037d4 + 8000568: f003 f950 bl 800380c HAL_GPIO_WritePin(IN7_GPIO_Port, IN7_Pin, (GPIO_PinState)UpdatePorts.porta.lidar); // lidar 800056c: 793b ldrb r3, [r7, #4] 800056e: f3c3 1380 ubfx r3, r3, #6, #1 @@ -651,7 +651,7 @@ void ChannelControl_UpdateGPIOs(enable_gpios UpdatePorts){ 8000574: 461a mov r2, r3 8000576: f44f 7180 mov.w r1, #256 @ 0x100 800057a: 4822 ldr r0, [pc, #136] @ (8000604 ) - 800057c: f003 f92a bl 80037d4 + 800057c: f003 f946 bl 800380c HAL_GPIO_WritePin(IN8_GPIO_Port, IN8_Pin, (GPIO_PinState)UpdatePorts.porta.misc); // MISC 8000580: 793b ldrb r3, [r7, #4] 8000582: f3c3 13c0 ubfx r3, r3, #7, #1 @@ -659,7 +659,7 @@ void ChannelControl_UpdateGPIOs(enable_gpios UpdatePorts){ 8000588: 461a mov r2, r3 800058a: f44f 5100 mov.w r1, #8192 @ 0x2000 800058e: 481d ldr r0, [pc, #116] @ (8000604 ) - 8000590: f003 f920 bl 80037d4 + 8000590: f003 f93c bl 800380c HAL_GPIO_WritePin(IN9_GPIO_Port, IN9_Pin, (GPIO_PinState)UpdatePorts.portb.alwayson); // always on -> standardmäßig auf HIGH forcen 8000594: 797b ldrb r3, [r7, #5] 8000596: f3c3 0300 ubfx r3, r3, #0, #1 @@ -667,7 +667,7 @@ void ChannelControl_UpdateGPIOs(enable_gpios UpdatePorts){ 800059c: 461a mov r2, r3 800059e: f44f 6100 mov.w r1, #2048 @ 0x800 80005a2: 4818 ldr r0, [pc, #96] @ (8000604 ) - 80005a4: f003 f916 bl 80037d4 + 80005a4: f003 f932 bl 800380c HAL_GPIO_WritePin(IN10_GPIO_Port, IN10_Pin, (GPIO_PinState)UpdatePorts.portb.sdc); // SDC -> muss anders controlled werden 80005a8: 797b ldrb r3, [r7, #5] 80005aa: f3c3 0340 ubfx r3, r3, #1, #1 @@ -675,7 +675,7 @@ void ChannelControl_UpdateGPIOs(enable_gpios UpdatePorts){ 80005b0: 461a mov r2, r3 80005b2: f44f 7100 mov.w r1, #512 @ 0x200 80005b6: 4813 ldr r0, [pc, #76] @ (8000604 ) - 80005b8: f003 f90c bl 80037d4 + 80005b8: f003 f928 bl 800380c HAL_GPIO_WritePin(IN11_GPIO_Port, IN11_Pin, (GPIO_PinState)UpdatePorts.portb.ebs1); // EBS 1 80005bc: 797b ldrb r3, [r7, #5] 80005be: f3c3 0380 ubfx r3, r3, #2, #1 @@ -683,7 +683,7 @@ void ChannelControl_UpdateGPIOs(enable_gpios UpdatePorts){ 80005c4: 461a mov r2, r3 80005c6: 2104 movs r1, #4 80005c8: 480e ldr r0, [pc, #56] @ (8000604 ) - 80005ca: f003 f903 bl 80037d4 + 80005ca: f003 f91f bl 800380c HAL_GPIO_WritePin(IN12_GPIO_Port, IN12_Pin, (GPIO_PinState)UpdatePorts.portb.ebs2); // EBS 2 80005ce: 797b ldrb r3, [r7, #5] 80005d0: f3c3 03c0 ubfx r3, r3, #3, #1 @@ -691,7 +691,7 @@ void ChannelControl_UpdateGPIOs(enable_gpios UpdatePorts){ 80005d6: 461a mov r2, r3 80005d8: 2102 movs r1, #2 80005da: 480a ldr r0, [pc, #40] @ (8000604 ) - 80005dc: f003 f8fa bl 80037d4 + 80005dc: f003 f916 bl 800380c HAL_GPIO_WritePin(IN13_GPIO_Port, IN13_Pin, (GPIO_PinState)UpdatePorts.portb.ebs3); // EBS 3 80005e0: 797b ldrb r3, [r7, #5] 80005e2: f3c3 1300 ubfx r3, r3, #4, #1 @@ -699,7 +699,7 @@ void ChannelControl_UpdateGPIOs(enable_gpios UpdatePorts){ 80005e8: 461a mov r2, r3 80005ea: f44f 6180 mov.w r1, #1024 @ 0x400 80005ee: 4805 ldr r0, [pc, #20] @ (8000604 ) - 80005f0: f003 f8f0 bl 80037d4 + 80005f0: f003 f90c bl 800380c } 80005f4: bf00 nop 80005f6: 3708 adds r7, #8 @@ -726,146 +726,146 @@ int main(void) /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); - 8000612: f000 fe97 bl 8001344 + 8000612: f000 feb3 bl 800137c /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); - 8000616: f000 f8b9 bl 800078c + 8000616: f000 f8d5 bl 80007c4 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); - 800061a: f000 fb47 bl 8000cac + 800061a: f000 fb63 bl 8000ce4 MX_DMA_Init(); - 800061e: f000 fb13 bl 8000c48 + 800061e: f000 fb2f bl 8000c80 MX_ADC1_Init(); - 8000622: f000 f90f bl 8000844 + 8000622: f000 f92b bl 800087c MX_ADC2_Init(); - 8000626: f000 f9d5 bl 80009d4 + 8000626: f000 f9f1 bl 8000a0c MX_CAN_Init(); - 800062a: f000 fa6f bl 8000b0c + 800062a: f000 fa8b bl 8000b44 MX_UART4_Init(); - 800062e: f000 fadb bl 8000be8 + 800062e: f000 faf7 bl 8000c20 MX_TIM6_Init(); - 8000632: f000 faa1 bl 8000b78 + 8000632: f000 fabd bl 8000bb0 /* USER CODE BEGIN 2 */ // begin start-up animation HAL_GPIO_WritePin(LED1_GPIO_Port, LED1_Pin, GPIO_PIN_SET); 8000636: 2201 movs r2, #1 8000638: f44f 7100 mov.w r1, #512 @ 0x200 - 800063c: 484d ldr r0, [pc, #308] @ (8000774 ) - 800063e: f003 f8c9 bl 80037d4 + 800063c: 485a ldr r0, [pc, #360] @ (80007a8 ) + 800063e: f003 f8e5 bl 800380c HAL_Delay(100); 8000642: 2064 movs r0, #100 @ 0x64 - 8000644: f000 fee4 bl 8001410 + 8000644: f000 ff00 bl 8001448 HAL_GPIO_WritePin(LED1_GPIO_Port, LED1_Pin, GPIO_PIN_RESET); 8000648: 2200 movs r2, #0 800064a: f44f 7100 mov.w r1, #512 @ 0x200 - 800064e: 4849 ldr r0, [pc, #292] @ (8000774 ) - 8000650: f003 f8c0 bl 80037d4 + 800064e: 4856 ldr r0, [pc, #344] @ (80007a8 ) + 8000650: f003 f8dc bl 800380c HAL_GPIO_WritePin(LED2_GPIO_Port, LED2_Pin, GPIO_PIN_SET); 8000654: 2201 movs r2, #1 8000656: f44f 7180 mov.w r1, #256 @ 0x100 - 800065a: 4846 ldr r0, [pc, #280] @ (8000774 ) - 800065c: f003 f8ba bl 80037d4 + 800065a: 4853 ldr r0, [pc, #332] @ (80007a8 ) + 800065c: f003 f8d6 bl 800380c HAL_Delay(100); 8000660: 2064 movs r0, #100 @ 0x64 - 8000662: f000 fed5 bl 8001410 + 8000662: f000 fef1 bl 8001448 HAL_GPIO_WritePin(LED2_GPIO_Port, LED2_Pin, GPIO_PIN_RESET); 8000666: 2200 movs r2, #0 8000668: f44f 7180 mov.w r1, #256 @ 0x100 - 800066c: 4841 ldr r0, [pc, #260] @ (8000774 ) - 800066e: f003 f8b1 bl 80037d4 + 800066c: 484e ldr r0, [pc, #312] @ (80007a8 ) + 800066e: f003 f8cd bl 800380c HAL_GPIO_WritePin(LED3_GPIO_Port, LED3_Pin, GPIO_PIN_SET); 8000672: 2201 movs r2, #1 8000674: 2180 movs r1, #128 @ 0x80 - 8000676: 483f ldr r0, [pc, #252] @ (8000774 ) - 8000678: f003 f8ac bl 80037d4 + 8000676: 484c ldr r0, [pc, #304] @ (80007a8 ) + 8000678: f003 f8c8 bl 800380c HAL_Delay(100); 800067c: 2064 movs r0, #100 @ 0x64 - 800067e: f000 fec7 bl 8001410 + 800067e: f000 fee3 bl 8001448 HAL_GPIO_WritePin(LED3_GPIO_Port, LED3_Pin, GPIO_PIN_RESET); 8000682: 2200 movs r2, #0 8000684: 2180 movs r1, #128 @ 0x80 - 8000686: 483b ldr r0, [pc, #236] @ (8000774 ) - 8000688: f003 f8a4 bl 80037d4 + 8000686: 4848 ldr r0, [pc, #288] @ (80007a8 ) + 8000688: f003 f8c0 bl 800380c HAL_GPIO_WritePin(LED4_GPIO_Port, LED4_Pin, GPIO_PIN_SET); 800068c: 2201 movs r2, #1 800068e: 2140 movs r1, #64 @ 0x40 - 8000690: 4838 ldr r0, [pc, #224] @ (8000774 ) - 8000692: f003 f89f bl 80037d4 + 8000690: 4845 ldr r0, [pc, #276] @ (80007a8 ) + 8000692: f003 f8bb bl 800380c HAL_Delay(100); 8000696: 2064 movs r0, #100 @ 0x64 - 8000698: f000 feba bl 8001410 + 8000698: f000 fed6 bl 8001448 HAL_GPIO_WritePin(LED4_GPIO_Port, LED3_Pin, GPIO_PIN_SET); 800069c: 2201 movs r2, #1 800069e: 2180 movs r1, #128 @ 0x80 - 80006a0: 4834 ldr r0, [pc, #208] @ (8000774 ) - 80006a2: f003 f897 bl 80037d4 + 80006a0: 4841 ldr r0, [pc, #260] @ (80007a8 ) + 80006a2: f003 f8b3 bl 800380c HAL_Delay(100); 80006a6: 2064 movs r0, #100 @ 0x64 - 80006a8: f000 feb2 bl 8001410 + 80006a8: f000 fece bl 8001448 HAL_GPIO_WritePin(LED2_GPIO_Port, LED2_Pin, GPIO_PIN_SET); 80006ac: 2201 movs r2, #1 80006ae: f44f 7180 mov.w r1, #256 @ 0x100 - 80006b2: 4830 ldr r0, [pc, #192] @ (8000774 ) - 80006b4: f003 f88e bl 80037d4 + 80006b2: 483d ldr r0, [pc, #244] @ (80007a8 ) + 80006b4: f003 f8aa bl 800380c HAL_Delay(100); 80006b8: 2064 movs r0, #100 @ 0x64 - 80006ba: f000 fea9 bl 8001410 + 80006ba: f000 fec5 bl 8001448 HAL_GPIO_WritePin(LED1_GPIO_Port, LED1_Pin, GPIO_PIN_SET); 80006be: 2201 movs r2, #1 80006c0: f44f 7100 mov.w r1, #512 @ 0x200 - 80006c4: 482b ldr r0, [pc, #172] @ (8000774 ) - 80006c6: f003 f885 bl 80037d4 + 80006c4: 4838 ldr r0, [pc, #224] @ (80007a8 ) + 80006c6: f003 f8a1 bl 800380c HAL_Delay(100); 80006ca: 2064 movs r0, #100 @ 0x64 - 80006cc: f000 fea0 bl 8001410 + 80006cc: f000 febc bl 8001448 HAL_GPIO_WritePin(LED1_GPIO_Port, LED1_Pin, GPIO_PIN_RESET); 80006d0: 2200 movs r2, #0 80006d2: f44f 7100 mov.w r1, #512 @ 0x200 - 80006d6: 4827 ldr r0, [pc, #156] @ (8000774 ) - 80006d8: f003 f87c bl 80037d4 + 80006d6: 4834 ldr r0, [pc, #208] @ (80007a8 ) + 80006d8: f003 f898 bl 800380c HAL_GPIO_WritePin(LED2_GPIO_Port, LED2_Pin, GPIO_PIN_RESET); 80006dc: 2200 movs r2, #0 80006de: f44f 7180 mov.w r1, #256 @ 0x100 - 80006e2: 4824 ldr r0, [pc, #144] @ (8000774 ) - 80006e4: f003 f876 bl 80037d4 + 80006e2: 4831 ldr r0, [pc, #196] @ (80007a8 ) + 80006e4: f003 f892 bl 800380c HAL_GPIO_WritePin(LED3_GPIO_Port, LED3_Pin, GPIO_PIN_RESET); 80006e8: 2200 movs r2, #0 80006ea: 2180 movs r1, #128 @ 0x80 - 80006ec: 4821 ldr r0, [pc, #132] @ (8000774 ) - 80006ee: f003 f871 bl 80037d4 + 80006ec: 482e ldr r0, [pc, #184] @ (80007a8 ) + 80006ee: f003 f88d bl 800380c HAL_GPIO_WritePin(LED4_GPIO_Port, LED4_Pin, GPIO_PIN_RESET); 80006f2: 2200 movs r2, #0 80006f4: 2140 movs r1, #64 @ 0x40 - 80006f6: 481f ldr r0, [pc, #124] @ (8000774 ) - 80006f8: f003 f86c bl 80037d4 + 80006f6: 482c ldr r0, [pc, #176] @ (80007a8 ) + 80006f8: f003 f888 bl 800380c // end start-up animation HAL_GPIO_WritePin(LED4_GPIO_Port, LED4_Pin, GPIO_PIN_SET); // indicates running STM 80006fc: 2201 movs r2, #1 80006fe: 2140 movs r1, #64 @ 0x40 - 8000700: 481c ldr r0, [pc, #112] @ (8000774 ) - 8000702: f003 f867 bl 80037d4 + 8000700: 4829 ldr r0, [pc, #164] @ (80007a8 ) + 8000702: f003 f883 bl 800380c ChannelControl_init(); 8000706: f7ff fe91 bl 800042c can_init(&hcan); - 800070a: 481b ldr r0, [pc, #108] @ (8000778 ) + 800070a: 4828 ldr r0, [pc, #160] @ (80007ac ) 800070c: f7ff fd5c bl 80001c8 // currentMonitor initialisieren uint32_t lasttick = HAL_GetTick(); // Zeit in ms seit Start - 8000710: f000 fe72 bl 80013f8 + 8000710: f000 fe8e bl 8001430 8000714: 6078 str r0, [r7, #4] inhibit_SDC = 0; - 8000716: 4b19 ldr r3, [pc, #100] @ (800077c ) + 8000716: 4b26 ldr r3, [pc, #152] @ (80007b0 ) 8000718: 2200 movs r2, #0 800071a: 601a str r2, [r3, #0] while (1) @@ -874,4235 +874,4228 @@ int main(void) /* USER CODE BEGIN 3 */ if (canmsg_received){ - 800071c: 4b18 ldr r3, [pc, #96] @ (8000780 ) + 800071c: 4b25 ldr r3, [pc, #148] @ (80007b4 ) 800071e: 781b ldrb r3, [r3, #0] 8000720: b2db uxtb r3, r3 8000722: 2b00 cmp r3, #0 8000724: d006 beq.n 8000734 canmsg_received = 0; - 8000726: 4b16 ldr r3, [pc, #88] @ (8000780 ) + 8000726: 4b23 ldr r3, [pc, #140] @ (80007b4 ) 8000728: 2200 movs r2, #0 800072a: 701a strb r2, [r3, #0] update_ports = rxstate.iostatus; - 800072c: 4a15 ldr r2, [pc, #84] @ (8000784 ) - 800072e: 4b16 ldr r3, [pc, #88] @ (8000788 ) + 800072c: 4a22 ldr r2, [pc, #136] @ (80007b8 ) + 800072e: 4b23 ldr r3, [pc, #140] @ (80007bc ) 8000730: 881b ldrh r3, [r3, #0] 8000732: 8013 strh r3, [r2, #0] } if ((HAL_GetTick() - lasttick) > 100u){ - 8000734: f000 fe60 bl 80013f8 + 8000734: f000 fe7c bl 8001430 8000738: 4602 mov r2, r0 800073a: 687b ldr r3, [r7, #4] 800073c: 1ad3 subs r3, r2, r3 800073e: 2b64 cmp r3, #100 @ 0x64 8000740: d904 bls.n 800074c lasttick = HAL_GetTick(); - 8000742: f000 fe59 bl 80013f8 + 8000742: f000 fe75 bl 8001430 8000746: 6078 str r0, [r7, #4] can_sendloop(); 8000748: f7ff fd4e bl 80001e8 } - //watchdog (auch Status-LED an schalten) + if (((HAL_GetTick() - lastheartbeat) > 125U) && (HAL_GetTick() > 1000U)) { + 800074c: f000 fe70 bl 8001430 + 8000750: 4602 mov r2, r0 + 8000752: 4b1b ldr r3, [pc, #108] @ (80007c0 ) + 8000754: 681b ldr r3, [r3, #0] + 8000756: 1ad3 subs r3, r2, r3 + 8000758: 2b7d cmp r3, #125 @ 0x7d + 800075a: d908 bls.n 800076e + 800075c: f000 fe68 bl 8001430 + 8000760: 4603 mov r3, r0 + 8000762: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 + 8000766: d902 bls.n 800076e + inhibit_SDC = 1; + 8000768: 4b11 ldr r3, [pc, #68] @ (80007b0 ) + 800076a: 2201 movs r2, #1 + 800076c: 601a str r2, [r3, #0] + } HAL_GPIO_WritePin(LED1_GPIO_Port, LED1_Pin, (GPIO_PinState)!update_ports.portb.sdc); // indicates open SDC - 800074c: 4b0d ldr r3, [pc, #52] @ (8000784 ) - 800074e: 785b ldrb r3, [r3, #1] - 8000750: f3c3 0340 ubfx r3, r3, #1, #1 - 8000754: b2db uxtb r3, r3 - 8000756: f083 0301 eor.w r3, r3, #1 - 800075a: b2db uxtb r3, r3 - 800075c: 461a mov r2, r3 - 800075e: f44f 7100 mov.w r1, #512 @ 0x200 - 8000762: 4804 ldr r0, [pc, #16] @ (8000774 ) - 8000764: f003 f836 bl 80037d4 + 800076e: 4b12 ldr r3, [pc, #72] @ (80007b8 ) + 8000770: 785b ldrb r3, [r3, #1] + 8000772: f3c3 0340 ubfx r3, r3, #1, #1 + 8000776: b2db uxtb r3, r3 + 8000778: f083 0301 eor.w r3, r3, #1 + 800077c: b2db uxtb r3, r3 + 800077e: 461a mov r2, r3 + 8000780: f44f 7100 mov.w r1, #512 @ 0x200 + 8000784: 4808 ldr r0, [pc, #32] @ (80007a8 ) + 8000786: f003 f841 bl 800380c + HAL_GPIO_WritePin(LED2_GPIO_Port, LED2_Pin, (GPIO_PinState)inhibit_SDC); // indicates watchdog-status + 800078a: 4b09 ldr r3, [pc, #36] @ (80007b0 ) + 800078c: 681b ldr r3, [r3, #0] + 800078e: b2db uxtb r3, r3 + 8000790: 461a mov r2, r3 + 8000792: f44f 7180 mov.w r1, #256 @ 0x100 + 8000796: 4804 ldr r0, [pc, #16] @ (80007a8 ) + 8000798: f003 f838 bl 800380c // overcurrent check (wenn funktioniert, LED schalten) ChannelControl_UpdateGPIOs(update_ports); - 8000768: 4b06 ldr r3, [pc, #24] @ (8000784 ) - 800076a: 8818 ldrh r0, [r3, #0] - 800076c: f7ff fe74 bl 8000458 + 800079c: 4b06 ldr r3, [pc, #24] @ (80007b8 ) + 800079e: 8818 ldrh r0, [r3, #0] + 80007a0: f7ff fe5a bl 8000458 if (canmsg_received){ - 8000770: e7d4 b.n 800071c - 8000772: bf00 nop - 8000774: 48000800 .word 0x48000800 - 8000778: 200001a4 .word 0x200001a4 - 800077c: 200002a8 .word 0x200002a8 - 8000780: 2000002c .word 0x2000002c - 8000784: 200002a0 .word 0x200002a0 - 8000788: 20000028 .word 0x20000028 + 80007a4: e7ba b.n 800071c + 80007a6: bf00 nop + 80007a8: 48000800 .word 0x48000800 + 80007ac: 200001a4 .word 0x200001a4 + 80007b0: 200002a8 .word 0x200002a8 + 80007b4: 2000002c .word 0x2000002c + 80007b8: 200002a0 .word 0x200002a0 + 80007bc: 20000028 .word 0x20000028 + 80007c0: 200002a4 .word 0x200002a4 -0800078c : +080007c4 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { - 800078c: b580 push {r7, lr} - 800078e: b09c sub sp, #112 @ 0x70 - 8000790: af00 add r7, sp, #0 + 80007c4: b580 push {r7, lr} + 80007c6: b09c sub sp, #112 @ 0x70 + 80007c8: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; - 8000792: f107 0348 add.w r3, r7, #72 @ 0x48 - 8000796: 2228 movs r2, #40 @ 0x28 - 8000798: 2100 movs r1, #0 - 800079a: 4618 mov r0, r3 - 800079c: f005 fb2d bl 8005dfa + 80007ca: f107 0348 add.w r3, r7, #72 @ 0x48 + 80007ce: 2228 movs r2, #40 @ 0x28 + 80007d0: 2100 movs r1, #0 + 80007d2: 4618 mov r0, r3 + 80007d4: f005 fb2d bl 8005e32 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - 80007a0: f107 0334 add.w r3, r7, #52 @ 0x34 - 80007a4: 2200 movs r2, #0 - 80007a6: 601a str r2, [r3, #0] - 80007a8: 605a str r2, [r3, #4] - 80007aa: 609a str r2, [r3, #8] - 80007ac: 60da str r2, [r3, #12] - 80007ae: 611a str r2, [r3, #16] + 80007d8: f107 0334 add.w r3, r7, #52 @ 0x34 + 80007dc: 2200 movs r2, #0 + 80007de: 601a str r2, [r3, #0] + 80007e0: 605a str r2, [r3, #4] + 80007e2: 609a str r2, [r3, #8] + 80007e4: 60da str r2, [r3, #12] + 80007e6: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - 80007b0: 463b mov r3, r7 - 80007b2: 2234 movs r2, #52 @ 0x34 - 80007b4: 2100 movs r1, #0 - 80007b6: 4618 mov r0, r3 - 80007b8: f005 fb1f bl 8005dfa + 80007e8: 463b mov r3, r7 + 80007ea: 2234 movs r2, #52 @ 0x34 + 80007ec: 2100 movs r1, #0 + 80007ee: 4618 mov r0, r3 + 80007f0: f005 fb1f bl 8005e32 /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; - 80007bc: 2301 movs r3, #1 - 80007be: 64bb str r3, [r7, #72] @ 0x48 + 80007f4: 2301 movs r3, #1 + 80007f6: 64bb str r3, [r7, #72] @ 0x48 RCC_OscInitStruct.HSEState = RCC_HSE_ON; - 80007c0: f44f 3380 mov.w r3, #65536 @ 0x10000 - 80007c4: 64fb str r3, [r7, #76] @ 0x4c + 80007f8: f44f 3380 mov.w r3, #65536 @ 0x10000 + 80007fc: 64fb str r3, [r7, #76] @ 0x4c RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1; - 80007c6: 2300 movs r3, #0 - 80007c8: 653b str r3, [r7, #80] @ 0x50 + 80007fe: 2300 movs r3, #0 + 8000800: 653b str r3, [r7, #80] @ 0x50 RCC_OscInitStruct.HSIState = RCC_HSI_ON; - 80007ca: 2301 movs r3, #1 - 80007cc: 65bb str r3, [r7, #88] @ 0x58 + 8000802: 2301 movs r3, #1 + 8000804: 65bb str r3, [r7, #88] @ 0x58 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - 80007ce: 2302 movs r3, #2 - 80007d0: 667b str r3, [r7, #100] @ 0x64 + 8000806: 2302 movs r3, #2 + 8000808: 667b str r3, [r7, #100] @ 0x64 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - 80007d2: f44f 3380 mov.w r3, #65536 @ 0x10000 - 80007d6: 66bb str r3, [r7, #104] @ 0x68 + 800080a: f44f 3380 mov.w r3, #65536 @ 0x10000 + 800080e: 66bb str r3, [r7, #104] @ 0x68 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL4; - 80007d8: f44f 2300 mov.w r3, #524288 @ 0x80000 - 80007dc: 66fb str r3, [r7, #108] @ 0x6c + 8000810: f44f 2300 mov.w r3, #524288 @ 0x80000 + 8000814: 66fb str r3, [r7, #108] @ 0x6c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) - 80007de: f107 0348 add.w r3, r7, #72 @ 0x48 - 80007e2: 4618 mov r0, r3 - 80007e4: f003 f80e bl 8003804 - 80007e8: 4603 mov r3, r0 - 80007ea: 2b00 cmp r3, #0 - 80007ec: d001 beq.n 80007f2 + 8000816: f107 0348 add.w r3, r7, #72 @ 0x48 + 800081a: 4618 mov r0, r3 + 800081c: f003 f80e bl 800383c + 8000820: 4603 mov r3, r0 + 8000822: 2b00 cmp r3, #0 + 8000824: d001 beq.n 800082a { Error_Handler(); - 80007ee: f000 fae3 bl 8000db8 + 8000826: f000 fae3 bl 8000df0 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK - 80007f2: 230f movs r3, #15 - 80007f4: 637b str r3, [r7, #52] @ 0x34 + 800082a: 230f movs r3, #15 + 800082c: 637b str r3, [r7, #52] @ 0x34 |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE; - 80007f6: 2301 movs r3, #1 - 80007f8: 63bb str r3, [r7, #56] @ 0x38 + 800082e: 2301 movs r3, #1 + 8000830: 63bb str r3, [r7, #56] @ 0x38 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - 80007fa: 2300 movs r3, #0 - 80007fc: 63fb str r3, [r7, #60] @ 0x3c + 8000832: 2300 movs r3, #0 + 8000834: 63fb str r3, [r7, #60] @ 0x3c RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; - 80007fe: 2300 movs r3, #0 - 8000800: 643b str r3, [r7, #64] @ 0x40 + 8000836: 2300 movs r3, #0 + 8000838: 643b str r3, [r7, #64] @ 0x40 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; - 8000802: 2300 movs r3, #0 - 8000804: 647b str r3, [r7, #68] @ 0x44 + 800083a: 2300 movs r3, #0 + 800083c: 647b str r3, [r7, #68] @ 0x44 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) - 8000806: f107 0334 add.w r3, r7, #52 @ 0x34 - 800080a: 2100 movs r1, #0 - 800080c: 4618 mov r0, r3 - 800080e: f004 f837 bl 8004880 - 8000812: 4603 mov r3, r0 - 8000814: 2b00 cmp r3, #0 - 8000816: d001 beq.n 800081c + 800083e: f107 0334 add.w r3, r7, #52 @ 0x34 + 8000842: 2100 movs r1, #0 + 8000844: 4618 mov r0, r3 + 8000846: f004 f837 bl 80048b8 + 800084a: 4603 mov r3, r0 + 800084c: 2b00 cmp r3, #0 + 800084e: d001 beq.n 8000854 { Error_Handler(); - 8000818: f000 face bl 8000db8 + 8000850: f000 face bl 8000df0 } PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_UART4|RCC_PERIPHCLK_ADC12; - 800081c: 2388 movs r3, #136 @ 0x88 - 800081e: 603b str r3, [r7, #0] + 8000854: 2388 movs r3, #136 @ 0x88 + 8000856: 603b str r3, [r7, #0] PeriphClkInit.Uart4ClockSelection = RCC_UART4CLKSOURCE_PCLK1; - 8000820: 2300 movs r3, #0 - 8000822: 617b str r3, [r7, #20] + 8000858: 2300 movs r3, #0 + 800085a: 617b str r3, [r7, #20] PeriphClkInit.Adc12ClockSelection = RCC_ADC12PLLCLK_DIV1; - 8000824: f44f 7380 mov.w r3, #256 @ 0x100 - 8000828: 627b str r3, [r7, #36] @ 0x24 + 800085c: f44f 7380 mov.w r3, #256 @ 0x100 + 8000860: 627b str r3, [r7, #36] @ 0x24 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) - 800082a: 463b mov r3, r7 - 800082c: 4618 mov r0, r3 - 800082e: f004 fa5f bl 8004cf0 - 8000832: 4603 mov r3, r0 - 8000834: 2b00 cmp r3, #0 - 8000836: d001 beq.n 800083c + 8000862: 463b mov r3, r7 + 8000864: 4618 mov r0, r3 + 8000866: f004 fa5f bl 8004d28 + 800086a: 4603 mov r3, r0 + 800086c: 2b00 cmp r3, #0 + 800086e: d001 beq.n 8000874 { Error_Handler(); - 8000838: f000 fabe bl 8000db8 + 8000870: f000 fabe bl 8000df0 } } - 800083c: bf00 nop - 800083e: 3770 adds r7, #112 @ 0x70 - 8000840: 46bd mov sp, r7 - 8000842: bd80 pop {r7, pc} + 8000874: bf00 nop + 8000876: 3770 adds r7, #112 @ 0x70 + 8000878: 46bd mov sp, r7 + 800087a: bd80 pop {r7, pc} -08000844 : +0800087c : * @brief ADC1 Initialization Function * @param None * @retval None */ static void MX_ADC1_Init(void) { - 8000844: b580 push {r7, lr} - 8000846: b08a sub sp, #40 @ 0x28 - 8000848: af00 add r7, sp, #0 + 800087c: b580 push {r7, lr} + 800087e: b08a sub sp, #40 @ 0x28 + 8000880: af00 add r7, sp, #0 /* USER CODE BEGIN ADC1_Init 0 */ /* USER CODE END ADC1_Init 0 */ ADC_MultiModeTypeDef multimode = {0}; - 800084a: f107 031c add.w r3, r7, #28 - 800084e: 2200 movs r2, #0 - 8000850: 601a str r2, [r3, #0] - 8000852: 605a str r2, [r3, #4] - 8000854: 609a str r2, [r3, #8] + 8000882: f107 031c add.w r3, r7, #28 + 8000886: 2200 movs r2, #0 + 8000888: 601a str r2, [r3, #0] + 800088a: 605a str r2, [r3, #4] + 800088c: 609a str r2, [r3, #8] ADC_ChannelConfTypeDef sConfig = {0}; - 8000856: 1d3b adds r3, r7, #4 - 8000858: 2200 movs r2, #0 - 800085a: 601a str r2, [r3, #0] - 800085c: 605a str r2, [r3, #4] - 800085e: 609a str r2, [r3, #8] - 8000860: 60da str r2, [r3, #12] - 8000862: 611a str r2, [r3, #16] - 8000864: 615a str r2, [r3, #20] + 800088e: 1d3b adds r3, r7, #4 + 8000890: 2200 movs r2, #0 + 8000892: 601a str r2, [r3, #0] + 8000894: 605a str r2, [r3, #4] + 8000896: 609a str r2, [r3, #8] + 8000898: 60da str r2, [r3, #12] + 800089a: 611a str r2, [r3, #16] + 800089c: 615a str r2, [r3, #20] /* USER CODE END ADC1_Init 1 */ /** Common config */ hadc1.Instance = ADC1; - 8000866: 4b5a ldr r3, [pc, #360] @ (80009d0 ) - 8000868: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 - 800086c: 601a str r2, [r3, #0] + 800089e: 4b5a ldr r3, [pc, #360] @ (8000a08 ) + 80008a0: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 + 80008a4: 601a str r2, [r3, #0] hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1; - 800086e: 4b58 ldr r3, [pc, #352] @ (80009d0 ) - 8000870: 2200 movs r2, #0 - 8000872: 605a str r2, [r3, #4] + 80008a6: 4b58 ldr r3, [pc, #352] @ (8000a08 ) + 80008a8: 2200 movs r2, #0 + 80008aa: 605a str r2, [r3, #4] hadc1.Init.Resolution = ADC_RESOLUTION_12B; - 8000874: 4b56 ldr r3, [pc, #344] @ (80009d0 ) - 8000876: 2200 movs r2, #0 - 8000878: 609a str r2, [r3, #8] + 80008ac: 4b56 ldr r3, [pc, #344] @ (8000a08 ) + 80008ae: 2200 movs r2, #0 + 80008b0: 609a str r2, [r3, #8] hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE; - 800087a: 4b55 ldr r3, [pc, #340] @ (80009d0 ) - 800087c: 2201 movs r2, #1 - 800087e: 611a str r2, [r3, #16] + 80008b2: 4b55 ldr r3, [pc, #340] @ (8000a08 ) + 80008b4: 2201 movs r2, #1 + 80008b6: 611a str r2, [r3, #16] hadc1.Init.ContinuousConvMode = DISABLE; - 8000880: 4b53 ldr r3, [pc, #332] @ (80009d0 ) - 8000882: 2200 movs r2, #0 - 8000884: 765a strb r2, [r3, #25] - hadc1.Init.DiscontinuousConvMode = DISABLE; - 8000886: 4b52 ldr r3, [pc, #328] @ (80009d0 ) - 8000888: 2200 movs r2, #0 - 800088a: f883 2020 strb.w r2, [r3, #32] - hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; - 800088e: 4b50 ldr r3, [pc, #320] @ (80009d0 ) - 8000890: f44f 6280 mov.w r2, #1024 @ 0x400 - 8000894: 62da str r2, [r3, #44] @ 0x2c - hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_T6_TRGO; - 8000896: 4b4e ldr r3, [pc, #312] @ (80009d0 ) - 8000898: f44f 7250 mov.w r2, #832 @ 0x340 - 800089c: 629a str r2, [r3, #40] @ 0x28 - hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; - 800089e: 4b4c ldr r3, [pc, #304] @ (80009d0 ) - 80008a0: 2200 movs r2, #0 - 80008a2: 60da str r2, [r3, #12] - hadc1.Init.NbrOfConversion = 8; - 80008a4: 4b4a ldr r3, [pc, #296] @ (80009d0 ) - 80008a6: 2208 movs r2, #8 - 80008a8: 61da str r2, [r3, #28] - hadc1.Init.DMAContinuousRequests = ENABLE; - 80008aa: 4b49 ldr r3, [pc, #292] @ (80009d0 ) - 80008ac: 2201 movs r2, #1 - 80008ae: f883 2030 strb.w r2, [r3, #48] @ 0x30 - hadc1.Init.EOCSelection = ADC_EOC_SEQ_CONV; - 80008b2: 4b47 ldr r3, [pc, #284] @ (80009d0 ) - 80008b4: 2208 movs r2, #8 - 80008b6: 615a str r2, [r3, #20] - hadc1.Init.LowPowerAutoWait = DISABLE; - 80008b8: 4b45 ldr r3, [pc, #276] @ (80009d0 ) + 80008b8: 4b53 ldr r3, [pc, #332] @ (8000a08 ) 80008ba: 2200 movs r2, #0 - 80008bc: 761a strb r2, [r3, #24] - hadc1.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN; - 80008be: 4b44 ldr r3, [pc, #272] @ (80009d0 ) + 80008bc: 765a strb r2, [r3, #25] + hadc1.Init.DiscontinuousConvMode = DISABLE; + 80008be: 4b52 ldr r3, [pc, #328] @ (8000a08 ) 80008c0: 2200 movs r2, #0 - 80008c2: 635a str r2, [r3, #52] @ 0x34 + 80008c2: f883 2020 strb.w r2, [r3, #32] + hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; + 80008c6: 4b50 ldr r3, [pc, #320] @ (8000a08 ) + 80008c8: f44f 6280 mov.w r2, #1024 @ 0x400 + 80008cc: 62da str r2, [r3, #44] @ 0x2c + hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_T6_TRGO; + 80008ce: 4b4e ldr r3, [pc, #312] @ (8000a08 ) + 80008d0: f44f 7250 mov.w r2, #832 @ 0x340 + 80008d4: 629a str r2, [r3, #40] @ 0x28 + hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; + 80008d6: 4b4c ldr r3, [pc, #304] @ (8000a08 ) + 80008d8: 2200 movs r2, #0 + 80008da: 60da str r2, [r3, #12] + hadc1.Init.NbrOfConversion = 8; + 80008dc: 4b4a ldr r3, [pc, #296] @ (8000a08 ) + 80008de: 2208 movs r2, #8 + 80008e0: 61da str r2, [r3, #28] + hadc1.Init.DMAContinuousRequests = ENABLE; + 80008e2: 4b49 ldr r3, [pc, #292] @ (8000a08 ) + 80008e4: 2201 movs r2, #1 + 80008e6: f883 2030 strb.w r2, [r3, #48] @ 0x30 + hadc1.Init.EOCSelection = ADC_EOC_SEQ_CONV; + 80008ea: 4b47 ldr r3, [pc, #284] @ (8000a08 ) + 80008ec: 2208 movs r2, #8 + 80008ee: 615a str r2, [r3, #20] + hadc1.Init.LowPowerAutoWait = DISABLE; + 80008f0: 4b45 ldr r3, [pc, #276] @ (8000a08 ) + 80008f2: 2200 movs r2, #0 + 80008f4: 761a strb r2, [r3, #24] + hadc1.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN; + 80008f6: 4b44 ldr r3, [pc, #272] @ (8000a08 ) + 80008f8: 2200 movs r2, #0 + 80008fa: 635a str r2, [r3, #52] @ 0x34 if (HAL_ADC_Init(&hadc1) != HAL_OK) - 80008c4: 4842 ldr r0, [pc, #264] @ (80009d0 ) - 80008c6: f000 fde5 bl 8001494 - 80008ca: 4603 mov r3, r0 - 80008cc: 2b00 cmp r3, #0 - 80008ce: d001 beq.n 80008d4 + 80008fc: 4842 ldr r0, [pc, #264] @ (8000a08 ) + 80008fe: f000 fde5 bl 80014cc + 8000902: 4603 mov r3, r0 + 8000904: 2b00 cmp r3, #0 + 8000906: d001 beq.n 800090c { Error_Handler(); - 80008d0: f000 fa72 bl 8000db8 + 8000908: f000 fa72 bl 8000df0 } /** Configure the ADC multi-mode */ multimode.Mode = ADC_MODE_INDEPENDENT; - 80008d4: 2300 movs r3, #0 - 80008d6: 61fb str r3, [r7, #28] + 800090c: 2300 movs r3, #0 + 800090e: 61fb str r3, [r7, #28] if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK) - 80008d8: f107 031c add.w r3, r7, #28 - 80008dc: 4619 mov r1, r3 - 80008de: 483c ldr r0, [pc, #240] @ (80009d0 ) - 80008e0: f001 fc4a bl 8002178 - 80008e4: 4603 mov r3, r0 - 80008e6: 2b00 cmp r3, #0 - 80008e8: d001 beq.n 80008ee + 8000910: f107 031c add.w r3, r7, #28 + 8000914: 4619 mov r1, r3 + 8000916: 483c ldr r0, [pc, #240] @ (8000a08 ) + 8000918: f001 fc4a bl 80021b0 + 800091c: 4603 mov r3, r0 + 800091e: 2b00 cmp r3, #0 + 8000920: d001 beq.n 8000926 { Error_Handler(); - 80008ea: f000 fa65 bl 8000db8 + 8000922: f000 fa65 bl 8000df0 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_2; - 80008ee: 2302 movs r3, #2 - 80008f0: 607b str r3, [r7, #4] + 8000926: 2302 movs r3, #2 + 8000928: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_1; - 80008f2: 2301 movs r3, #1 - 80008f4: 60bb str r3, [r7, #8] + 800092a: 2301 movs r3, #1 + 800092c: 60bb str r3, [r7, #8] sConfig.SingleDiff = ADC_SINGLE_ENDED; - 80008f6: 2300 movs r3, #0 - 80008f8: 613b str r3, [r7, #16] + 800092e: 2300 movs r3, #0 + 8000930: 613b str r3, [r7, #16] sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5; - 80008fa: 2300 movs r3, #0 - 80008fc: 60fb str r3, [r7, #12] + 8000932: 2300 movs r3, #0 + 8000934: 60fb str r3, [r7, #12] sConfig.OffsetNumber = ADC_OFFSET_NONE; - 80008fe: 2300 movs r3, #0 - 8000900: 617b str r3, [r7, #20] + 8000936: 2300 movs r3, #0 + 8000938: 617b str r3, [r7, #20] sConfig.Offset = 0; - 8000902: 2300 movs r3, #0 - 8000904: 61bb str r3, [r7, #24] + 800093a: 2300 movs r3, #0 + 800093c: 61bb str r3, [r7, #24] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) - 8000906: 1d3b adds r3, r7, #4 - 8000908: 4619 mov r1, r3 - 800090a: 4831 ldr r0, [pc, #196] @ (80009d0 ) - 800090c: f001 f976 bl 8001bfc - 8000910: 4603 mov r3, r0 - 8000912: 2b00 cmp r3, #0 - 8000914: d001 beq.n 800091a + 800093e: 1d3b adds r3, r7, #4 + 8000940: 4619 mov r1, r3 + 8000942: 4831 ldr r0, [pc, #196] @ (8000a08 ) + 8000944: f001 f976 bl 8001c34 + 8000948: 4603 mov r3, r0 + 800094a: 2b00 cmp r3, #0 + 800094c: d001 beq.n 8000952 { Error_Handler(); - 8000916: f000 fa4f bl 8000db8 + 800094e: f000 fa4f bl 8000df0 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_1; - 800091a: 2301 movs r3, #1 - 800091c: 607b str r3, [r7, #4] + 8000952: 2301 movs r3, #1 + 8000954: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_2; - 800091e: 2302 movs r3, #2 - 8000920: 60bb str r3, [r7, #8] + 8000956: 2302 movs r3, #2 + 8000958: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) - 8000922: 1d3b adds r3, r7, #4 - 8000924: 4619 mov r1, r3 - 8000926: 482a ldr r0, [pc, #168] @ (80009d0 ) - 8000928: f001 f968 bl 8001bfc - 800092c: 4603 mov r3, r0 - 800092e: 2b00 cmp r3, #0 - 8000930: d001 beq.n 8000936 + 800095a: 1d3b adds r3, r7, #4 + 800095c: 4619 mov r1, r3 + 800095e: 482a ldr r0, [pc, #168] @ (8000a08 ) + 8000960: f001 f968 bl 8001c34 + 8000964: 4603 mov r3, r0 + 8000966: 2b00 cmp r3, #0 + 8000968: d001 beq.n 800096e { Error_Handler(); - 8000932: f000 fa41 bl 8000db8 + 800096a: f000 fa41 bl 8000df0 } /** Configure Regular Channel */ sConfig.Rank = ADC_REGULAR_RANK_3; - 8000936: 2303 movs r3, #3 - 8000938: 60bb str r3, [r7, #8] + 800096e: 2303 movs r3, #3 + 8000970: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) - 800093a: 1d3b adds r3, r7, #4 - 800093c: 4619 mov r1, r3 - 800093e: 4824 ldr r0, [pc, #144] @ (80009d0 ) - 8000940: f001 f95c bl 8001bfc - 8000944: 4603 mov r3, r0 - 8000946: 2b00 cmp r3, #0 - 8000948: d001 beq.n 800094e + 8000972: 1d3b adds r3, r7, #4 + 8000974: 4619 mov r1, r3 + 8000976: 4824 ldr r0, [pc, #144] @ (8000a08 ) + 8000978: f001 f95c bl 8001c34 + 800097c: 4603 mov r3, r0 + 800097e: 2b00 cmp r3, #0 + 8000980: d001 beq.n 8000986 { Error_Handler(); - 800094a: f000 fa35 bl 8000db8 + 8000982: f000 fa35 bl 8000df0 } /** Configure Regular Channel */ sConfig.Rank = ADC_REGULAR_RANK_4; - 800094e: 2304 movs r3, #4 - 8000950: 60bb str r3, [r7, #8] + 8000986: 2304 movs r3, #4 + 8000988: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) - 8000952: 1d3b adds r3, r7, #4 - 8000954: 4619 mov r1, r3 - 8000956: 481e ldr r0, [pc, #120] @ (80009d0 ) - 8000958: f001 f950 bl 8001bfc - 800095c: 4603 mov r3, r0 - 800095e: 2b00 cmp r3, #0 - 8000960: d001 beq.n 8000966 + 800098a: 1d3b adds r3, r7, #4 + 800098c: 4619 mov r1, r3 + 800098e: 481e ldr r0, [pc, #120] @ (8000a08 ) + 8000990: f001 f950 bl 8001c34 + 8000994: 4603 mov r3, r0 + 8000996: 2b00 cmp r3, #0 + 8000998: d001 beq.n 800099e { Error_Handler(); - 8000962: f000 fa29 bl 8000db8 + 800099a: f000 fa29 bl 8000df0 } /** Configure Regular Channel */ sConfig.Rank = ADC_REGULAR_RANK_5; - 8000966: 2305 movs r3, #5 - 8000968: 60bb str r3, [r7, #8] + 800099e: 2305 movs r3, #5 + 80009a0: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) - 800096a: 1d3b adds r3, r7, #4 - 800096c: 4619 mov r1, r3 - 800096e: 4818 ldr r0, [pc, #96] @ (80009d0 ) - 8000970: f001 f944 bl 8001bfc - 8000974: 4603 mov r3, r0 - 8000976: 2b00 cmp r3, #0 - 8000978: d001 beq.n 800097e + 80009a2: 1d3b adds r3, r7, #4 + 80009a4: 4619 mov r1, r3 + 80009a6: 4818 ldr r0, [pc, #96] @ (8000a08 ) + 80009a8: f001 f944 bl 8001c34 + 80009ac: 4603 mov r3, r0 + 80009ae: 2b00 cmp r3, #0 + 80009b0: d001 beq.n 80009b6 { Error_Handler(); - 800097a: f000 fa1d bl 8000db8 + 80009b2: f000 fa1d bl 8000df0 } /** Configure Regular Channel */ sConfig.Rank = ADC_REGULAR_RANK_6; - 800097e: 2306 movs r3, #6 - 8000980: 60bb str r3, [r7, #8] + 80009b6: 2306 movs r3, #6 + 80009b8: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) - 8000982: 1d3b adds r3, r7, #4 - 8000984: 4619 mov r1, r3 - 8000986: 4812 ldr r0, [pc, #72] @ (80009d0 ) - 8000988: f001 f938 bl 8001bfc - 800098c: 4603 mov r3, r0 - 800098e: 2b00 cmp r3, #0 - 8000990: d001 beq.n 8000996 + 80009ba: 1d3b adds r3, r7, #4 + 80009bc: 4619 mov r1, r3 + 80009be: 4812 ldr r0, [pc, #72] @ (8000a08 ) + 80009c0: f001 f938 bl 8001c34 + 80009c4: 4603 mov r3, r0 + 80009c6: 2b00 cmp r3, #0 + 80009c8: d001 beq.n 80009ce { Error_Handler(); - 8000992: f000 fa11 bl 8000db8 + 80009ca: f000 fa11 bl 8000df0 } /** Configure Regular Channel */ sConfig.Rank = ADC_REGULAR_RANK_7; - 8000996: 2307 movs r3, #7 - 8000998: 60bb str r3, [r7, #8] + 80009ce: 2307 movs r3, #7 + 80009d0: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) - 800099a: 1d3b adds r3, r7, #4 - 800099c: 4619 mov r1, r3 - 800099e: 480c ldr r0, [pc, #48] @ (80009d0 ) - 80009a0: f001 f92c bl 8001bfc - 80009a4: 4603 mov r3, r0 - 80009a6: 2b00 cmp r3, #0 - 80009a8: d001 beq.n 80009ae + 80009d2: 1d3b adds r3, r7, #4 + 80009d4: 4619 mov r1, r3 + 80009d6: 480c ldr r0, [pc, #48] @ (8000a08 ) + 80009d8: f001 f92c bl 8001c34 + 80009dc: 4603 mov r3, r0 + 80009de: 2b00 cmp r3, #0 + 80009e0: d001 beq.n 80009e6 { Error_Handler(); - 80009aa: f000 fa05 bl 8000db8 + 80009e2: f000 fa05 bl 8000df0 } /** Configure Regular Channel */ sConfig.Rank = ADC_REGULAR_RANK_8; - 80009ae: 2308 movs r3, #8 - 80009b0: 60bb str r3, [r7, #8] + 80009e6: 2308 movs r3, #8 + 80009e8: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) - 80009b2: 1d3b adds r3, r7, #4 - 80009b4: 4619 mov r1, r3 - 80009b6: 4806 ldr r0, [pc, #24] @ (80009d0 ) - 80009b8: f001 f920 bl 8001bfc - 80009bc: 4603 mov r3, r0 - 80009be: 2b00 cmp r3, #0 - 80009c0: d001 beq.n 80009c6 + 80009ea: 1d3b adds r3, r7, #4 + 80009ec: 4619 mov r1, r3 + 80009ee: 4806 ldr r0, [pc, #24] @ (8000a08 ) + 80009f0: f001 f920 bl 8001c34 + 80009f4: 4603 mov r3, r0 + 80009f6: 2b00 cmp r3, #0 + 80009f8: d001 beq.n 80009fe { Error_Handler(); - 80009c2: f000 f9f9 bl 8000db8 + 80009fa: f000 f9f9 bl 8000df0 } /* USER CODE BEGIN ADC1_Init 2 */ /* USER CODE END ADC1_Init 2 */ } - 80009c6: bf00 nop - 80009c8: 3728 adds r7, #40 @ 0x28 - 80009ca: 46bd mov sp, r7 - 80009cc: bd80 pop {r7, pc} - 80009ce: bf00 nop - 80009d0: 2000007c .word 0x2000007c + 80009fe: bf00 nop + 8000a00: 3728 adds r7, #40 @ 0x28 + 8000a02: 46bd mov sp, r7 + 8000a04: bd80 pop {r7, pc} + 8000a06: bf00 nop + 8000a08: 2000007c .word 0x2000007c -080009d4 : +08000a0c : * @brief ADC2 Initialization Function * @param None * @retval None */ static void MX_ADC2_Init(void) { - 80009d4: b580 push {r7, lr} - 80009d6: b086 sub sp, #24 - 80009d8: af00 add r7, sp, #0 + 8000a0c: b580 push {r7, lr} + 8000a0e: b086 sub sp, #24 + 8000a10: af00 add r7, sp, #0 /* USER CODE BEGIN ADC2_Init 0 */ /* USER CODE END ADC2_Init 0 */ ADC_ChannelConfTypeDef sConfig = {0}; - 80009da: 463b mov r3, r7 - 80009dc: 2200 movs r2, #0 - 80009de: 601a str r2, [r3, #0] - 80009e0: 605a str r2, [r3, #4] - 80009e2: 609a str r2, [r3, #8] - 80009e4: 60da str r2, [r3, #12] - 80009e6: 611a str r2, [r3, #16] - 80009e8: 615a str r2, [r3, #20] + 8000a12: 463b mov r3, r7 + 8000a14: 2200 movs r2, #0 + 8000a16: 601a str r2, [r3, #0] + 8000a18: 605a str r2, [r3, #4] + 8000a1a: 609a str r2, [r3, #8] + 8000a1c: 60da str r2, [r3, #12] + 8000a1e: 611a str r2, [r3, #16] + 8000a20: 615a str r2, [r3, #20] /* USER CODE END ADC2_Init 1 */ /** Common config */ hadc2.Instance = ADC2; - 80009ea: 4b46 ldr r3, [pc, #280] @ (8000b04 ) - 80009ec: 4a46 ldr r2, [pc, #280] @ (8000b08 ) - 80009ee: 601a str r2, [r3, #0] + 8000a22: 4b46 ldr r3, [pc, #280] @ (8000b3c ) + 8000a24: 4a46 ldr r2, [pc, #280] @ (8000b40 ) + 8000a26: 601a str r2, [r3, #0] hadc2.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1; - 80009f0: 4b44 ldr r3, [pc, #272] @ (8000b04 ) - 80009f2: 2200 movs r2, #0 - 80009f4: 605a str r2, [r3, #4] + 8000a28: 4b44 ldr r3, [pc, #272] @ (8000b3c ) + 8000a2a: 2200 movs r2, #0 + 8000a2c: 605a str r2, [r3, #4] hadc2.Init.Resolution = ADC_RESOLUTION_12B; - 80009f6: 4b43 ldr r3, [pc, #268] @ (8000b04 ) - 80009f8: 2200 movs r2, #0 - 80009fa: 609a str r2, [r3, #8] + 8000a2e: 4b43 ldr r3, [pc, #268] @ (8000b3c ) + 8000a30: 2200 movs r2, #0 + 8000a32: 609a str r2, [r3, #8] hadc2.Init.ScanConvMode = ADC_SCAN_ENABLE; - 80009fc: 4b41 ldr r3, [pc, #260] @ (8000b04 ) - 80009fe: 2201 movs r2, #1 - 8000a00: 611a str r2, [r3, #16] + 8000a34: 4b41 ldr r3, [pc, #260] @ (8000b3c ) + 8000a36: 2201 movs r2, #1 + 8000a38: 611a str r2, [r3, #16] hadc2.Init.ContinuousConvMode = DISABLE; - 8000a02: 4b40 ldr r3, [pc, #256] @ (8000b04 ) - 8000a04: 2200 movs r2, #0 - 8000a06: 765a strb r2, [r3, #25] - hadc2.Init.DiscontinuousConvMode = DISABLE; - 8000a08: 4b3e ldr r3, [pc, #248] @ (8000b04 ) - 8000a0a: 2200 movs r2, #0 - 8000a0c: f883 2020 strb.w r2, [r3, #32] - hadc2.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; - 8000a10: 4b3c ldr r3, [pc, #240] @ (8000b04 ) - 8000a12: f44f 6280 mov.w r2, #1024 @ 0x400 - 8000a16: 62da str r2, [r3, #44] @ 0x2c - hadc2.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_T6_TRGO; - 8000a18: 4b3a ldr r3, [pc, #232] @ (8000b04 ) - 8000a1a: f44f 7250 mov.w r2, #832 @ 0x340 - 8000a1e: 629a str r2, [r3, #40] @ 0x28 - hadc2.Init.DataAlign = ADC_DATAALIGN_RIGHT; - 8000a20: 4b38 ldr r3, [pc, #224] @ (8000b04 ) - 8000a22: 2200 movs r2, #0 - 8000a24: 60da str r2, [r3, #12] - hadc2.Init.NbrOfConversion = 6; - 8000a26: 4b37 ldr r3, [pc, #220] @ (8000b04 ) - 8000a28: 2206 movs r2, #6 - 8000a2a: 61da str r2, [r3, #28] - hadc2.Init.DMAContinuousRequests = ENABLE; - 8000a2c: 4b35 ldr r3, [pc, #212] @ (8000b04 ) - 8000a2e: 2201 movs r2, #1 - 8000a30: f883 2030 strb.w r2, [r3, #48] @ 0x30 - hadc2.Init.EOCSelection = ADC_EOC_SEQ_CONV; - 8000a34: 4b33 ldr r3, [pc, #204] @ (8000b04 ) - 8000a36: 2208 movs r2, #8 - 8000a38: 615a str r2, [r3, #20] - hadc2.Init.LowPowerAutoWait = DISABLE; - 8000a3a: 4b32 ldr r3, [pc, #200] @ (8000b04 ) + 8000a3a: 4b40 ldr r3, [pc, #256] @ (8000b3c ) 8000a3c: 2200 movs r2, #0 - 8000a3e: 761a strb r2, [r3, #24] - hadc2.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN; - 8000a40: 4b30 ldr r3, [pc, #192] @ (8000b04 ) + 8000a3e: 765a strb r2, [r3, #25] + hadc2.Init.DiscontinuousConvMode = DISABLE; + 8000a40: 4b3e ldr r3, [pc, #248] @ (8000b3c ) 8000a42: 2200 movs r2, #0 - 8000a44: 635a str r2, [r3, #52] @ 0x34 + 8000a44: f883 2020 strb.w r2, [r3, #32] + hadc2.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; + 8000a48: 4b3c ldr r3, [pc, #240] @ (8000b3c ) + 8000a4a: f44f 6280 mov.w r2, #1024 @ 0x400 + 8000a4e: 62da str r2, [r3, #44] @ 0x2c + hadc2.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_T6_TRGO; + 8000a50: 4b3a ldr r3, [pc, #232] @ (8000b3c ) + 8000a52: f44f 7250 mov.w r2, #832 @ 0x340 + 8000a56: 629a str r2, [r3, #40] @ 0x28 + hadc2.Init.DataAlign = ADC_DATAALIGN_RIGHT; + 8000a58: 4b38 ldr r3, [pc, #224] @ (8000b3c ) + 8000a5a: 2200 movs r2, #0 + 8000a5c: 60da str r2, [r3, #12] + hadc2.Init.NbrOfConversion = 6; + 8000a5e: 4b37 ldr r3, [pc, #220] @ (8000b3c ) + 8000a60: 2206 movs r2, #6 + 8000a62: 61da str r2, [r3, #28] + hadc2.Init.DMAContinuousRequests = ENABLE; + 8000a64: 4b35 ldr r3, [pc, #212] @ (8000b3c ) + 8000a66: 2201 movs r2, #1 + 8000a68: f883 2030 strb.w r2, [r3, #48] @ 0x30 + hadc2.Init.EOCSelection = ADC_EOC_SEQ_CONV; + 8000a6c: 4b33 ldr r3, [pc, #204] @ (8000b3c ) + 8000a6e: 2208 movs r2, #8 + 8000a70: 615a str r2, [r3, #20] + hadc2.Init.LowPowerAutoWait = DISABLE; + 8000a72: 4b32 ldr r3, [pc, #200] @ (8000b3c ) + 8000a74: 2200 movs r2, #0 + 8000a76: 761a strb r2, [r3, #24] + hadc2.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN; + 8000a78: 4b30 ldr r3, [pc, #192] @ (8000b3c ) + 8000a7a: 2200 movs r2, #0 + 8000a7c: 635a str r2, [r3, #52] @ 0x34 if (HAL_ADC_Init(&hadc2) != HAL_OK) - 8000a46: 482f ldr r0, [pc, #188] @ (8000b04 ) - 8000a48: f000 fd24 bl 8001494 - 8000a4c: 4603 mov r3, r0 - 8000a4e: 2b00 cmp r3, #0 - 8000a50: d001 beq.n 8000a56 + 8000a7e: 482f ldr r0, [pc, #188] @ (8000b3c ) + 8000a80: f000 fd24 bl 80014cc + 8000a84: 4603 mov r3, r0 + 8000a86: 2b00 cmp r3, #0 + 8000a88: d001 beq.n 8000a8e { Error_Handler(); - 8000a52: f000 f9b1 bl 8000db8 + 8000a8a: f000 f9b1 bl 8000df0 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_1; - 8000a56: 2301 movs r3, #1 - 8000a58: 603b str r3, [r7, #0] + 8000a8e: 2301 movs r3, #1 + 8000a90: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_1; - 8000a5a: 2301 movs r3, #1 - 8000a5c: 607b str r3, [r7, #4] + 8000a92: 2301 movs r3, #1 + 8000a94: 607b str r3, [r7, #4] sConfig.SingleDiff = ADC_SINGLE_ENDED; - 8000a5e: 2300 movs r3, #0 - 8000a60: 60fb str r3, [r7, #12] + 8000a96: 2300 movs r3, #0 + 8000a98: 60fb str r3, [r7, #12] sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5; - 8000a62: 2300 movs r3, #0 - 8000a64: 60bb str r3, [r7, #8] + 8000a9a: 2300 movs r3, #0 + 8000a9c: 60bb str r3, [r7, #8] sConfig.OffsetNumber = ADC_OFFSET_NONE; - 8000a66: 2300 movs r3, #0 - 8000a68: 613b str r3, [r7, #16] + 8000a9e: 2300 movs r3, #0 + 8000aa0: 613b str r3, [r7, #16] sConfig.Offset = 0; - 8000a6a: 2300 movs r3, #0 - 8000a6c: 617b str r3, [r7, #20] + 8000aa2: 2300 movs r3, #0 + 8000aa4: 617b str r3, [r7, #20] if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) - 8000a6e: 463b mov r3, r7 - 8000a70: 4619 mov r1, r3 - 8000a72: 4824 ldr r0, [pc, #144] @ (8000b04 ) - 8000a74: f001 f8c2 bl 8001bfc - 8000a78: 4603 mov r3, r0 - 8000a7a: 2b00 cmp r3, #0 - 8000a7c: d001 beq.n 8000a82 + 8000aa6: 463b mov r3, r7 + 8000aa8: 4619 mov r1, r3 + 8000aaa: 4824 ldr r0, [pc, #144] @ (8000b3c ) + 8000aac: f001 f8c2 bl 8001c34 + 8000ab0: 4603 mov r3, r0 + 8000ab2: 2b00 cmp r3, #0 + 8000ab4: d001 beq.n 8000aba { Error_Handler(); - 8000a7e: f000 f99b bl 8000db8 + 8000ab6: f000 f99b bl 8000df0 } /** Configure Regular Channel */ sConfig.Rank = ADC_REGULAR_RANK_2; - 8000a82: 2302 movs r3, #2 - 8000a84: 607b str r3, [r7, #4] + 8000aba: 2302 movs r3, #2 + 8000abc: 607b str r3, [r7, #4] if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) - 8000a86: 463b mov r3, r7 - 8000a88: 4619 mov r1, r3 - 8000a8a: 481e ldr r0, [pc, #120] @ (8000b04 ) - 8000a8c: f001 f8b6 bl 8001bfc - 8000a90: 4603 mov r3, r0 - 8000a92: 2b00 cmp r3, #0 - 8000a94: d001 beq.n 8000a9a + 8000abe: 463b mov r3, r7 + 8000ac0: 4619 mov r1, r3 + 8000ac2: 481e ldr r0, [pc, #120] @ (8000b3c ) + 8000ac4: f001 f8b6 bl 8001c34 + 8000ac8: 4603 mov r3, r0 + 8000aca: 2b00 cmp r3, #0 + 8000acc: d001 beq.n 8000ad2 { Error_Handler(); - 8000a96: f000 f98f bl 8000db8 + 8000ace: f000 f98f bl 8000df0 } /** Configure Regular Channel */ sConfig.Rank = ADC_REGULAR_RANK_3; - 8000a9a: 2303 movs r3, #3 - 8000a9c: 607b str r3, [r7, #4] + 8000ad2: 2303 movs r3, #3 + 8000ad4: 607b str r3, [r7, #4] if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) - 8000a9e: 463b mov r3, r7 - 8000aa0: 4619 mov r1, r3 - 8000aa2: 4818 ldr r0, [pc, #96] @ (8000b04 ) - 8000aa4: f001 f8aa bl 8001bfc - 8000aa8: 4603 mov r3, r0 - 8000aaa: 2b00 cmp r3, #0 - 8000aac: d001 beq.n 8000ab2 + 8000ad6: 463b mov r3, r7 + 8000ad8: 4619 mov r1, r3 + 8000ada: 4818 ldr r0, [pc, #96] @ (8000b3c ) + 8000adc: f001 f8aa bl 8001c34 + 8000ae0: 4603 mov r3, r0 + 8000ae2: 2b00 cmp r3, #0 + 8000ae4: d001 beq.n 8000aea { Error_Handler(); - 8000aae: f000 f983 bl 8000db8 + 8000ae6: f000 f983 bl 8000df0 } /** Configure Regular Channel */ sConfig.Rank = ADC_REGULAR_RANK_4; - 8000ab2: 2304 movs r3, #4 - 8000ab4: 607b str r3, [r7, #4] + 8000aea: 2304 movs r3, #4 + 8000aec: 607b str r3, [r7, #4] if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) - 8000ab6: 463b mov r3, r7 - 8000ab8: 4619 mov r1, r3 - 8000aba: 4812 ldr r0, [pc, #72] @ (8000b04 ) - 8000abc: f001 f89e bl 8001bfc - 8000ac0: 4603 mov r3, r0 - 8000ac2: 2b00 cmp r3, #0 - 8000ac4: d001 beq.n 8000aca + 8000aee: 463b mov r3, r7 + 8000af0: 4619 mov r1, r3 + 8000af2: 4812 ldr r0, [pc, #72] @ (8000b3c ) + 8000af4: f001 f89e bl 8001c34 + 8000af8: 4603 mov r3, r0 + 8000afa: 2b00 cmp r3, #0 + 8000afc: d001 beq.n 8000b02 { Error_Handler(); - 8000ac6: f000 f977 bl 8000db8 + 8000afe: f000 f977 bl 8000df0 } /** Configure Regular Channel */ sConfig.Rank = ADC_REGULAR_RANK_5; - 8000aca: 2305 movs r3, #5 - 8000acc: 607b str r3, [r7, #4] + 8000b02: 2305 movs r3, #5 + 8000b04: 607b str r3, [r7, #4] if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) - 8000ace: 463b mov r3, r7 - 8000ad0: 4619 mov r1, r3 - 8000ad2: 480c ldr r0, [pc, #48] @ (8000b04 ) - 8000ad4: f001 f892 bl 8001bfc - 8000ad8: 4603 mov r3, r0 - 8000ada: 2b00 cmp r3, #0 - 8000adc: d001 beq.n 8000ae2 + 8000b06: 463b mov r3, r7 + 8000b08: 4619 mov r1, r3 + 8000b0a: 480c ldr r0, [pc, #48] @ (8000b3c ) + 8000b0c: f001 f892 bl 8001c34 + 8000b10: 4603 mov r3, r0 + 8000b12: 2b00 cmp r3, #0 + 8000b14: d001 beq.n 8000b1a { Error_Handler(); - 8000ade: f000 f96b bl 8000db8 + 8000b16: f000 f96b bl 8000df0 } /** Configure Regular Channel */ sConfig.Rank = ADC_REGULAR_RANK_6; - 8000ae2: 2306 movs r3, #6 - 8000ae4: 607b str r3, [r7, #4] + 8000b1a: 2306 movs r3, #6 + 8000b1c: 607b str r3, [r7, #4] if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) - 8000ae6: 463b mov r3, r7 - 8000ae8: 4619 mov r1, r3 - 8000aea: 4806 ldr r0, [pc, #24] @ (8000b04 ) - 8000aec: f001 f886 bl 8001bfc - 8000af0: 4603 mov r3, r0 - 8000af2: 2b00 cmp r3, #0 - 8000af4: d001 beq.n 8000afa + 8000b1e: 463b mov r3, r7 + 8000b20: 4619 mov r1, r3 + 8000b22: 4806 ldr r0, [pc, #24] @ (8000b3c ) + 8000b24: f001 f886 bl 8001c34 + 8000b28: 4603 mov r3, r0 + 8000b2a: 2b00 cmp r3, #0 + 8000b2c: d001 beq.n 8000b32 { Error_Handler(); - 8000af6: f000 f95f bl 8000db8 + 8000b2e: f000 f95f bl 8000df0 } /* USER CODE BEGIN ADC2_Init 2 */ /* USER CODE END ADC2_Init 2 */ } - 8000afa: bf00 nop - 8000afc: 3718 adds r7, #24 - 8000afe: 46bd mov sp, r7 - 8000b00: bd80 pop {r7, pc} - 8000b02: bf00 nop - 8000b04: 200000cc .word 0x200000cc - 8000b08: 50000100 .word 0x50000100 + 8000b32: bf00 nop + 8000b34: 3718 adds r7, #24 + 8000b36: 46bd mov sp, r7 + 8000b38: bd80 pop {r7, pc} + 8000b3a: bf00 nop + 8000b3c: 200000cc .word 0x200000cc + 8000b40: 50000100 .word 0x50000100 -08000b0c : +08000b44 : * @brief CAN Initialization Function * @param None * @retval None */ static void MX_CAN_Init(void) { - 8000b0c: b580 push {r7, lr} - 8000b0e: af00 add r7, sp, #0 + 8000b44: b580 push {r7, lr} + 8000b46: af00 add r7, sp, #0 /* USER CODE END CAN_Init 0 */ /* USER CODE BEGIN CAN_Init 1 */ /* USER CODE END CAN_Init 1 */ hcan.Instance = CAN; - 8000b10: 4b17 ldr r3, [pc, #92] @ (8000b70 ) - 8000b12: 4a18 ldr r2, [pc, #96] @ (8000b74 ) - 8000b14: 601a str r2, [r3, #0] + 8000b48: 4b17 ldr r3, [pc, #92] @ (8000ba8 ) + 8000b4a: 4a18 ldr r2, [pc, #96] @ (8000bac ) + 8000b4c: 601a str r2, [r3, #0] hcan.Init.Prescaler = 2; - 8000b16: 4b16 ldr r3, [pc, #88] @ (8000b70 ) - 8000b18: 2202 movs r2, #2 - 8000b1a: 605a str r2, [r3, #4] + 8000b4e: 4b16 ldr r3, [pc, #88] @ (8000ba8 ) + 8000b50: 2202 movs r2, #2 + 8000b52: 605a str r2, [r3, #4] hcan.Init.Mode = CAN_MODE_NORMAL; - 8000b1c: 4b14 ldr r3, [pc, #80] @ (8000b70 ) - 8000b1e: 2200 movs r2, #0 - 8000b20: 609a str r2, [r3, #8] + 8000b54: 4b14 ldr r3, [pc, #80] @ (8000ba8 ) + 8000b56: 2200 movs r2, #0 + 8000b58: 609a str r2, [r3, #8] hcan.Init.SyncJumpWidth = CAN_SJW_1TQ; - 8000b22: 4b13 ldr r3, [pc, #76] @ (8000b70 ) - 8000b24: 2200 movs r2, #0 - 8000b26: 60da str r2, [r3, #12] + 8000b5a: 4b13 ldr r3, [pc, #76] @ (8000ba8 ) + 8000b5c: 2200 movs r2, #0 + 8000b5e: 60da str r2, [r3, #12] hcan.Init.TimeSeg1 = CAN_BS1_13TQ; - 8000b28: 4b11 ldr r3, [pc, #68] @ (8000b70 ) - 8000b2a: f44f 2240 mov.w r2, #786432 @ 0xc0000 - 8000b2e: 611a str r2, [r3, #16] + 8000b60: 4b11 ldr r3, [pc, #68] @ (8000ba8 ) + 8000b62: f44f 2240 mov.w r2, #786432 @ 0xc0000 + 8000b66: 611a str r2, [r3, #16] hcan.Init.TimeSeg2 = CAN_BS2_2TQ; - 8000b30: 4b0f ldr r3, [pc, #60] @ (8000b70 ) - 8000b32: f44f 1280 mov.w r2, #1048576 @ 0x100000 - 8000b36: 615a str r2, [r3, #20] + 8000b68: 4b0f ldr r3, [pc, #60] @ (8000ba8 ) + 8000b6a: f44f 1280 mov.w r2, #1048576 @ 0x100000 + 8000b6e: 615a str r2, [r3, #20] hcan.Init.TimeTriggeredMode = DISABLE; - 8000b38: 4b0d ldr r3, [pc, #52] @ (8000b70 ) - 8000b3a: 2200 movs r2, #0 - 8000b3c: 761a strb r2, [r3, #24] + 8000b70: 4b0d ldr r3, [pc, #52] @ (8000ba8 ) + 8000b72: 2200 movs r2, #0 + 8000b74: 761a strb r2, [r3, #24] hcan.Init.AutoBusOff = DISABLE; - 8000b3e: 4b0c ldr r3, [pc, #48] @ (8000b70 ) - 8000b40: 2200 movs r2, #0 - 8000b42: 765a strb r2, [r3, #25] + 8000b76: 4b0c ldr r3, [pc, #48] @ (8000ba8 ) + 8000b78: 2200 movs r2, #0 + 8000b7a: 765a strb r2, [r3, #25] hcan.Init.AutoWakeUp = DISABLE; - 8000b44: 4b0a ldr r3, [pc, #40] @ (8000b70 ) - 8000b46: 2200 movs r2, #0 - 8000b48: 769a strb r2, [r3, #26] + 8000b7c: 4b0a ldr r3, [pc, #40] @ (8000ba8 ) + 8000b7e: 2200 movs r2, #0 + 8000b80: 769a strb r2, [r3, #26] hcan.Init.AutoRetransmission = DISABLE; - 8000b4a: 4b09 ldr r3, [pc, #36] @ (8000b70 ) - 8000b4c: 2200 movs r2, #0 - 8000b4e: 76da strb r2, [r3, #27] + 8000b82: 4b09 ldr r3, [pc, #36] @ (8000ba8 ) + 8000b84: 2200 movs r2, #0 + 8000b86: 76da strb r2, [r3, #27] hcan.Init.ReceiveFifoLocked = DISABLE; - 8000b50: 4b07 ldr r3, [pc, #28] @ (8000b70 ) - 8000b52: 2200 movs r2, #0 - 8000b54: 771a strb r2, [r3, #28] + 8000b88: 4b07 ldr r3, [pc, #28] @ (8000ba8 ) + 8000b8a: 2200 movs r2, #0 + 8000b8c: 771a strb r2, [r3, #28] hcan.Init.TransmitFifoPriority = DISABLE; - 8000b56: 4b06 ldr r3, [pc, #24] @ (8000b70 ) - 8000b58: 2200 movs r2, #0 - 8000b5a: 775a strb r2, [r3, #29] + 8000b8e: 4b06 ldr r3, [pc, #24] @ (8000ba8 ) + 8000b90: 2200 movs r2, #0 + 8000b92: 775a strb r2, [r3, #29] if (HAL_CAN_Init(&hcan) != HAL_OK) - 8000b5c: 4804 ldr r0, [pc, #16] @ (8000b70 ) - 8000b5e: f001 fc37 bl 80023d0 - 8000b62: 4603 mov r3, r0 - 8000b64: 2b00 cmp r3, #0 - 8000b66: d001 beq.n 8000b6c + 8000b94: 4804 ldr r0, [pc, #16] @ (8000ba8 ) + 8000b96: f001 fc37 bl 8002408 + 8000b9a: 4603 mov r3, r0 + 8000b9c: 2b00 cmp r3, #0 + 8000b9e: d001 beq.n 8000ba4 { Error_Handler(); - 8000b68: f000 f926 bl 8000db8 + 8000ba0: f000 f926 bl 8000df0 } /* USER CODE BEGIN CAN_Init 2 */ /* USER CODE END CAN_Init 2 */ } - 8000b6c: bf00 nop - 8000b6e: bd80 pop {r7, pc} - 8000b70: 200001a4 .word 0x200001a4 - 8000b74: 40006400 .word 0x40006400 + 8000ba4: bf00 nop + 8000ba6: bd80 pop {r7, pc} + 8000ba8: 200001a4 .word 0x200001a4 + 8000bac: 40006400 .word 0x40006400 -08000b78 : +08000bb0 : * @brief TIM6 Initialization Function * @param None * @retval None */ static void MX_TIM6_Init(void) { - 8000b78: b580 push {r7, lr} - 8000b7a: b084 sub sp, #16 - 8000b7c: af00 add r7, sp, #0 + 8000bb0: b580 push {r7, lr} + 8000bb2: b084 sub sp, #16 + 8000bb4: af00 add r7, sp, #0 /* USER CODE BEGIN TIM6_Init 0 */ /* USER CODE END TIM6_Init 0 */ TIM_MasterConfigTypeDef sMasterConfig = {0}; - 8000b7e: 1d3b adds r3, r7, #4 - 8000b80: 2200 movs r2, #0 - 8000b82: 601a str r2, [r3, #0] - 8000b84: 605a str r2, [r3, #4] - 8000b86: 609a str r2, [r3, #8] + 8000bb6: 1d3b adds r3, r7, #4 + 8000bb8: 2200 movs r2, #0 + 8000bba: 601a str r2, [r3, #0] + 8000bbc: 605a str r2, [r3, #4] + 8000bbe: 609a str r2, [r3, #8] /* USER CODE BEGIN TIM6_Init 1 */ /* USER CODE END TIM6_Init 1 */ htim6.Instance = TIM6; - 8000b88: 4b15 ldr r3, [pc, #84] @ (8000be0 ) - 8000b8a: 4a16 ldr r2, [pc, #88] @ (8000be4 ) - 8000b8c: 601a str r2, [r3, #0] + 8000bc0: 4b15 ldr r3, [pc, #84] @ (8000c18 ) + 8000bc2: 4a16 ldr r2, [pc, #88] @ (8000c1c ) + 8000bc4: 601a str r2, [r3, #0] htim6.Init.Prescaler = 400; - 8000b8e: 4b14 ldr r3, [pc, #80] @ (8000be0 ) - 8000b90: f44f 72c8 mov.w r2, #400 @ 0x190 - 8000b94: 605a str r2, [r3, #4] + 8000bc6: 4b14 ldr r3, [pc, #80] @ (8000c18 ) + 8000bc8: f44f 72c8 mov.w r2, #400 @ 0x190 + 8000bcc: 605a str r2, [r3, #4] htim6.Init.CounterMode = TIM_COUNTERMODE_UP; - 8000b96: 4b12 ldr r3, [pc, #72] @ (8000be0 ) - 8000b98: 2200 movs r2, #0 - 8000b9a: 609a str r2, [r3, #8] + 8000bce: 4b12 ldr r3, [pc, #72] @ (8000c18 ) + 8000bd0: 2200 movs r2, #0 + 8000bd2: 609a str r2, [r3, #8] htim6.Init.Period = 8000-1; - 8000b9c: 4b10 ldr r3, [pc, #64] @ (8000be0 ) - 8000b9e: f641 723f movw r2, #7999 @ 0x1f3f - 8000ba2: 60da str r2, [r3, #12] + 8000bd4: 4b10 ldr r3, [pc, #64] @ (8000c18 ) + 8000bd6: f641 723f movw r2, #7999 @ 0x1f3f + 8000bda: 60da str r2, [r3, #12] htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; - 8000ba4: 4b0e ldr r3, [pc, #56] @ (8000be0 ) - 8000ba6: 2200 movs r2, #0 - 8000ba8: 619a str r2, [r3, #24] + 8000bdc: 4b0e ldr r3, [pc, #56] @ (8000c18 ) + 8000bde: 2200 movs r2, #0 + 8000be0: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim6) != HAL_OK) - 8000baa: 480d ldr r0, [pc, #52] @ (8000be0 ) - 8000bac: f004 fa32 bl 8005014 - 8000bb0: 4603 mov r3, r0 - 8000bb2: 2b00 cmp r3, #0 - 8000bb4: d001 beq.n 8000bba + 8000be2: 480d ldr r0, [pc, #52] @ (8000c18 ) + 8000be4: f004 fa32 bl 800504c + 8000be8: 4603 mov r3, r0 + 8000bea: 2b00 cmp r3, #0 + 8000bec: d001 beq.n 8000bf2 { Error_Handler(); - 8000bb6: f000 f8ff bl 8000db8 + 8000bee: f000 f8ff bl 8000df0 } sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE; - 8000bba: 2320 movs r3, #32 - 8000bbc: 607b str r3, [r7, #4] + 8000bf2: 2320 movs r3, #32 + 8000bf4: 607b str r3, [r7, #4] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; - 8000bbe: 2300 movs r3, #0 - 8000bc0: 60fb str r3, [r7, #12] + 8000bf6: 2300 movs r3, #0 + 8000bf8: 60fb str r3, [r7, #12] if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig) != HAL_OK) - 8000bc2: 1d3b adds r3, r7, #4 - 8000bc4: 4619 mov r1, r3 - 8000bc6: 4806 ldr r0, [pc, #24] @ (8000be0 ) - 8000bc8: f004 fc4e bl 8005468 - 8000bcc: 4603 mov r3, r0 - 8000bce: 2b00 cmp r3, #0 - 8000bd0: d001 beq.n 8000bd6 + 8000bfa: 1d3b adds r3, r7, #4 + 8000bfc: 4619 mov r1, r3 + 8000bfe: 4806 ldr r0, [pc, #24] @ (8000c18 ) + 8000c00: f004 fc4e bl 80054a0 + 8000c04: 4603 mov r3, r0 + 8000c06: 2b00 cmp r3, #0 + 8000c08: d001 beq.n 8000c0e { Error_Handler(); - 8000bd2: f000 f8f1 bl 8000db8 + 8000c0a: f000 f8f1 bl 8000df0 } /* USER CODE BEGIN TIM6_Init 2 */ /* USER CODE END TIM6_Init 2 */ } - 8000bd6: bf00 nop - 8000bd8: 3710 adds r7, #16 - 8000bda: 46bd mov sp, r7 - 8000bdc: bd80 pop {r7, pc} - 8000bde: bf00 nop - 8000be0: 200001cc .word 0x200001cc - 8000be4: 40001000 .word 0x40001000 + 8000c0e: bf00 nop + 8000c10: 3710 adds r7, #16 + 8000c12: 46bd mov sp, r7 + 8000c14: bd80 pop {r7, pc} + 8000c16: bf00 nop + 8000c18: 200001cc .word 0x200001cc + 8000c1c: 40001000 .word 0x40001000 -08000be8 : +08000c20 : * @brief UART4 Initialization Function * @param None * @retval None */ static void MX_UART4_Init(void) { - 8000be8: b580 push {r7, lr} - 8000bea: af00 add r7, sp, #0 + 8000c20: b580 push {r7, lr} + 8000c22: af00 add r7, sp, #0 /* USER CODE END UART4_Init 0 */ /* USER CODE BEGIN UART4_Init 1 */ /* USER CODE END UART4_Init 1 */ huart4.Instance = UART4; - 8000bec: 4b14 ldr r3, [pc, #80] @ (8000c40 ) - 8000bee: 4a15 ldr r2, [pc, #84] @ (8000c44 ) - 8000bf0: 601a str r2, [r3, #0] + 8000c24: 4b14 ldr r3, [pc, #80] @ (8000c78 ) + 8000c26: 4a15 ldr r2, [pc, #84] @ (8000c7c ) + 8000c28: 601a str r2, [r3, #0] huart4.Init.BaudRate = 115200; - 8000bf2: 4b13 ldr r3, [pc, #76] @ (8000c40 ) - 8000bf4: f44f 32e1 mov.w r2, #115200 @ 0x1c200 - 8000bf8: 605a str r2, [r3, #4] + 8000c2a: 4b13 ldr r3, [pc, #76] @ (8000c78 ) + 8000c2c: f44f 32e1 mov.w r2, #115200 @ 0x1c200 + 8000c30: 605a str r2, [r3, #4] huart4.Init.WordLength = UART_WORDLENGTH_8B; - 8000bfa: 4b11 ldr r3, [pc, #68] @ (8000c40 ) - 8000bfc: 2200 movs r2, #0 - 8000bfe: 609a str r2, [r3, #8] + 8000c32: 4b11 ldr r3, [pc, #68] @ (8000c78 ) + 8000c34: 2200 movs r2, #0 + 8000c36: 609a str r2, [r3, #8] huart4.Init.StopBits = UART_STOPBITS_1; - 8000c00: 4b0f ldr r3, [pc, #60] @ (8000c40 ) - 8000c02: 2200 movs r2, #0 - 8000c04: 60da str r2, [r3, #12] + 8000c38: 4b0f ldr r3, [pc, #60] @ (8000c78 ) + 8000c3a: 2200 movs r2, #0 + 8000c3c: 60da str r2, [r3, #12] huart4.Init.Parity = UART_PARITY_NONE; - 8000c06: 4b0e ldr r3, [pc, #56] @ (8000c40 ) - 8000c08: 2200 movs r2, #0 - 8000c0a: 611a str r2, [r3, #16] + 8000c3e: 4b0e ldr r3, [pc, #56] @ (8000c78 ) + 8000c40: 2200 movs r2, #0 + 8000c42: 611a str r2, [r3, #16] huart4.Init.Mode = UART_MODE_TX_RX; - 8000c0c: 4b0c ldr r3, [pc, #48] @ (8000c40 ) - 8000c0e: 220c movs r2, #12 - 8000c10: 615a str r2, [r3, #20] + 8000c44: 4b0c ldr r3, [pc, #48] @ (8000c78 ) + 8000c46: 220c movs r2, #12 + 8000c48: 615a str r2, [r3, #20] huart4.Init.HwFlowCtl = UART_HWCONTROL_NONE; - 8000c12: 4b0b ldr r3, [pc, #44] @ (8000c40 ) - 8000c14: 2200 movs r2, #0 - 8000c16: 619a str r2, [r3, #24] + 8000c4a: 4b0b ldr r3, [pc, #44] @ (8000c78 ) + 8000c4c: 2200 movs r2, #0 + 8000c4e: 619a str r2, [r3, #24] huart4.Init.OverSampling = UART_OVERSAMPLING_16; - 8000c18: 4b09 ldr r3, [pc, #36] @ (8000c40 ) - 8000c1a: 2200 movs r2, #0 - 8000c1c: 61da str r2, [r3, #28] + 8000c50: 4b09 ldr r3, [pc, #36] @ (8000c78 ) + 8000c52: 2200 movs r2, #0 + 8000c54: 61da str r2, [r3, #28] huart4.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; - 8000c1e: 4b08 ldr r3, [pc, #32] @ (8000c40 ) - 8000c20: 2200 movs r2, #0 - 8000c22: 621a str r2, [r3, #32] + 8000c56: 4b08 ldr r3, [pc, #32] @ (8000c78 ) + 8000c58: 2200 movs r2, #0 + 8000c5a: 621a str r2, [r3, #32] huart4.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; - 8000c24: 4b06 ldr r3, [pc, #24] @ (8000c40 ) - 8000c26: 2200 movs r2, #0 - 8000c28: 625a str r2, [r3, #36] @ 0x24 + 8000c5c: 4b06 ldr r3, [pc, #24] @ (8000c78 ) + 8000c5e: 2200 movs r2, #0 + 8000c60: 625a str r2, [r3, #36] @ 0x24 if (HAL_UART_Init(&huart4) != HAL_OK) - 8000c2a: 4805 ldr r0, [pc, #20] @ (8000c40 ) - 8000c2c: f004 fcae bl 800558c - 8000c30: 4603 mov r3, r0 - 8000c32: 2b00 cmp r3, #0 - 8000c34: d001 beq.n 8000c3a + 8000c62: 4805 ldr r0, [pc, #20] @ (8000c78 ) + 8000c64: f004 fcae bl 80055c4 + 8000c68: 4603 mov r3, r0 + 8000c6a: 2b00 cmp r3, #0 + 8000c6c: d001 beq.n 8000c72 { Error_Handler(); - 8000c36: f000 f8bf bl 8000db8 + 8000c6e: f000 f8bf bl 8000df0 } /* USER CODE BEGIN UART4_Init 2 */ /* USER CODE END UART4_Init 2 */ } - 8000c3a: bf00 nop - 8000c3c: bd80 pop {r7, pc} - 8000c3e: bf00 nop - 8000c40: 20000218 .word 0x20000218 - 8000c44: 40004c00 .word 0x40004c00 + 8000c72: bf00 nop + 8000c74: bd80 pop {r7, pc} + 8000c76: bf00 nop + 8000c78: 20000218 .word 0x20000218 + 8000c7c: 40004c00 .word 0x40004c00 -08000c48 : +08000c80 : /** * Enable DMA controller clock */ static void MX_DMA_Init(void) { - 8000c48: b580 push {r7, lr} - 8000c4a: b082 sub sp, #8 - 8000c4c: af00 add r7, sp, #0 + 8000c80: b580 push {r7, lr} + 8000c82: b082 sub sp, #8 + 8000c84: af00 add r7, sp, #0 /* DMA controller clock enable */ __HAL_RCC_DMA1_CLK_ENABLE(); - 8000c4e: 4b16 ldr r3, [pc, #88] @ (8000ca8 ) - 8000c50: 695b ldr r3, [r3, #20] - 8000c52: 4a15 ldr r2, [pc, #84] @ (8000ca8 ) - 8000c54: f043 0301 orr.w r3, r3, #1 - 8000c58: 6153 str r3, [r2, #20] - 8000c5a: 4b13 ldr r3, [pc, #76] @ (8000ca8 ) - 8000c5c: 695b ldr r3, [r3, #20] - 8000c5e: f003 0301 and.w r3, r3, #1 - 8000c62: 607b str r3, [r7, #4] - 8000c64: 687b ldr r3, [r7, #4] + 8000c86: 4b16 ldr r3, [pc, #88] @ (8000ce0 ) + 8000c88: 695b ldr r3, [r3, #20] + 8000c8a: 4a15 ldr r2, [pc, #84] @ (8000ce0 ) + 8000c8c: f043 0301 orr.w r3, r3, #1 + 8000c90: 6153 str r3, [r2, #20] + 8000c92: 4b13 ldr r3, [pc, #76] @ (8000ce0 ) + 8000c94: 695b ldr r3, [r3, #20] + 8000c96: f003 0301 and.w r3, r3, #1 + 8000c9a: 607b str r3, [r7, #4] + 8000c9c: 687b ldr r3, [r7, #4] __HAL_RCC_DMA2_CLK_ENABLE(); - 8000c66: 4b10 ldr r3, [pc, #64] @ (8000ca8 ) - 8000c68: 695b ldr r3, [r3, #20] - 8000c6a: 4a0f ldr r2, [pc, #60] @ (8000ca8 ) - 8000c6c: f043 0302 orr.w r3, r3, #2 - 8000c70: 6153 str r3, [r2, #20] - 8000c72: 4b0d ldr r3, [pc, #52] @ (8000ca8 ) - 8000c74: 695b ldr r3, [r3, #20] - 8000c76: f003 0302 and.w r3, r3, #2 - 8000c7a: 603b str r3, [r7, #0] - 8000c7c: 683b ldr r3, [r7, #0] + 8000c9e: 4b10 ldr r3, [pc, #64] @ (8000ce0 ) + 8000ca0: 695b ldr r3, [r3, #20] + 8000ca2: 4a0f ldr r2, [pc, #60] @ (8000ce0 ) + 8000ca4: f043 0302 orr.w r3, r3, #2 + 8000ca8: 6153 str r3, [r2, #20] + 8000caa: 4b0d ldr r3, [pc, #52] @ (8000ce0 ) + 8000cac: 695b ldr r3, [r3, #20] + 8000cae: f003 0302 and.w r3, r3, #2 + 8000cb2: 603b str r3, [r7, #0] + 8000cb4: 683b ldr r3, [r7, #0] /* DMA interrupt init */ /* DMA1_Channel1_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0); - 8000c7e: 2200 movs r2, #0 - 8000c80: 2100 movs r1, #0 - 8000c82: 200b movs r0, #11 - 8000c84: f002 facf bl 8003226 + 8000cb6: 2200 movs r2, #0 + 8000cb8: 2100 movs r1, #0 + 8000cba: 200b movs r0, #11 + 8000cbc: f002 facf bl 800325e HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn); - 8000c88: 200b movs r0, #11 - 8000c8a: f002 fae8 bl 800325e + 8000cc0: 200b movs r0, #11 + 8000cc2: f002 fae8 bl 8003296 /* DMA2_Channel1_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA2_Channel1_IRQn, 0, 0); - 8000c8e: 2200 movs r2, #0 - 8000c90: 2100 movs r1, #0 - 8000c92: 2038 movs r0, #56 @ 0x38 - 8000c94: f002 fac7 bl 8003226 + 8000cc6: 2200 movs r2, #0 + 8000cc8: 2100 movs r1, #0 + 8000cca: 2038 movs r0, #56 @ 0x38 + 8000ccc: f002 fac7 bl 800325e HAL_NVIC_EnableIRQ(DMA2_Channel1_IRQn); - 8000c98: 2038 movs r0, #56 @ 0x38 - 8000c9a: f002 fae0 bl 800325e + 8000cd0: 2038 movs r0, #56 @ 0x38 + 8000cd2: f002 fae0 bl 8003296 } - 8000c9e: bf00 nop - 8000ca0: 3708 adds r7, #8 - 8000ca2: 46bd mov sp, r7 - 8000ca4: bd80 pop {r7, pc} - 8000ca6: bf00 nop - 8000ca8: 40021000 .word 0x40021000 + 8000cd6: bf00 nop + 8000cd8: 3708 adds r7, #8 + 8000cda: 46bd mov sp, r7 + 8000cdc: bd80 pop {r7, pc} + 8000cde: bf00 nop + 8000ce0: 40021000 .word 0x40021000 -08000cac : +08000ce4 : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { - 8000cac: b580 push {r7, lr} - 8000cae: b08a sub sp, #40 @ 0x28 - 8000cb0: af00 add r7, sp, #0 + 8000ce4: b580 push {r7, lr} + 8000ce6: b08a sub sp, #40 @ 0x28 + 8000ce8: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; - 8000cb2: f107 0314 add.w r3, r7, #20 - 8000cb6: 2200 movs r2, #0 - 8000cb8: 601a str r2, [r3, #0] - 8000cba: 605a str r2, [r3, #4] - 8000cbc: 609a str r2, [r3, #8] - 8000cbe: 60da str r2, [r3, #12] - 8000cc0: 611a str r2, [r3, #16] + 8000cea: f107 0314 add.w r3, r7, #20 + 8000cee: 2200 movs r2, #0 + 8000cf0: 601a str r2, [r3, #0] + 8000cf2: 605a str r2, [r3, #4] + 8000cf4: 609a str r2, [r3, #8] + 8000cf6: 60da str r2, [r3, #12] + 8000cf8: 611a str r2, [r3, #16] /* USER CODE BEGIN MX_GPIO_Init_1 */ /* USER CODE END MX_GPIO_Init_1 */ /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOF_CLK_ENABLE(); - 8000cc2: 4b3a ldr r3, [pc, #232] @ (8000dac ) - 8000cc4: 695b ldr r3, [r3, #20] - 8000cc6: 4a39 ldr r2, [pc, #228] @ (8000dac ) - 8000cc8: f443 0380 orr.w r3, r3, #4194304 @ 0x400000 - 8000ccc: 6153 str r3, [r2, #20] - 8000cce: 4b37 ldr r3, [pc, #220] @ (8000dac ) - 8000cd0: 695b ldr r3, [r3, #20] - 8000cd2: f403 0380 and.w r3, r3, #4194304 @ 0x400000 - 8000cd6: 613b str r3, [r7, #16] - 8000cd8: 693b ldr r3, [r7, #16] + 8000cfa: 4b3a ldr r3, [pc, #232] @ (8000de4 ) + 8000cfc: 695b ldr r3, [r3, #20] + 8000cfe: 4a39 ldr r2, [pc, #228] @ (8000de4 ) + 8000d00: f443 0380 orr.w r3, r3, #4194304 @ 0x400000 + 8000d04: 6153 str r3, [r2, #20] + 8000d06: 4b37 ldr r3, [pc, #220] @ (8000de4 ) + 8000d08: 695b ldr r3, [r3, #20] + 8000d0a: f403 0380 and.w r3, r3, #4194304 @ 0x400000 + 8000d0e: 613b str r3, [r7, #16] + 8000d10: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOC_CLK_ENABLE(); - 8000cda: 4b34 ldr r3, [pc, #208] @ (8000dac ) - 8000cdc: 695b ldr r3, [r3, #20] - 8000cde: 4a33 ldr r2, [pc, #204] @ (8000dac ) - 8000ce0: f443 2300 orr.w r3, r3, #524288 @ 0x80000 - 8000ce4: 6153 str r3, [r2, #20] - 8000ce6: 4b31 ldr r3, [pc, #196] @ (8000dac ) - 8000ce8: 695b ldr r3, [r3, #20] - 8000cea: f403 2300 and.w r3, r3, #524288 @ 0x80000 - 8000cee: 60fb str r3, [r7, #12] - 8000cf0: 68fb ldr r3, [r7, #12] + 8000d12: 4b34 ldr r3, [pc, #208] @ (8000de4 ) + 8000d14: 695b ldr r3, [r3, #20] + 8000d16: 4a33 ldr r2, [pc, #204] @ (8000de4 ) + 8000d18: f443 2300 orr.w r3, r3, #524288 @ 0x80000 + 8000d1c: 6153 str r3, [r2, #20] + 8000d1e: 4b31 ldr r3, [pc, #196] @ (8000de4 ) + 8000d20: 695b ldr r3, [r3, #20] + 8000d22: f403 2300 and.w r3, r3, #524288 @ 0x80000 + 8000d26: 60fb str r3, [r7, #12] + 8000d28: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOA_CLK_ENABLE(); - 8000cf2: 4b2e ldr r3, [pc, #184] @ (8000dac ) - 8000cf4: 695b ldr r3, [r3, #20] - 8000cf6: 4a2d ldr r2, [pc, #180] @ (8000dac ) - 8000cf8: f443 3300 orr.w r3, r3, #131072 @ 0x20000 - 8000cfc: 6153 str r3, [r2, #20] - 8000cfe: 4b2b ldr r3, [pc, #172] @ (8000dac ) - 8000d00: 695b ldr r3, [r3, #20] - 8000d02: f403 3300 and.w r3, r3, #131072 @ 0x20000 - 8000d06: 60bb str r3, [r7, #8] - 8000d08: 68bb ldr r3, [r7, #8] + 8000d2a: 4b2e ldr r3, [pc, #184] @ (8000de4 ) + 8000d2c: 695b ldr r3, [r3, #20] + 8000d2e: 4a2d ldr r2, [pc, #180] @ (8000de4 ) + 8000d30: f443 3300 orr.w r3, r3, #131072 @ 0x20000 + 8000d34: 6153 str r3, [r2, #20] + 8000d36: 4b2b ldr r3, [pc, #172] @ (8000de4 ) + 8000d38: 695b ldr r3, [r3, #20] + 8000d3a: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 8000d3e: 60bb str r3, [r7, #8] + 8000d40: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOB_CLK_ENABLE(); - 8000d0a: 4b28 ldr r3, [pc, #160] @ (8000dac ) - 8000d0c: 695b ldr r3, [r3, #20] - 8000d0e: 4a27 ldr r2, [pc, #156] @ (8000dac ) - 8000d10: f443 2380 orr.w r3, r3, #262144 @ 0x40000 - 8000d14: 6153 str r3, [r2, #20] - 8000d16: 4b25 ldr r3, [pc, #148] @ (8000dac ) - 8000d18: 695b ldr r3, [r3, #20] - 8000d1a: f403 2380 and.w r3, r3, #262144 @ 0x40000 - 8000d1e: 607b str r3, [r7, #4] - 8000d20: 687b ldr r3, [r7, #4] + 8000d42: 4b28 ldr r3, [pc, #160] @ (8000de4 ) + 8000d44: 695b ldr r3, [r3, #20] + 8000d46: 4a27 ldr r2, [pc, #156] @ (8000de4 ) + 8000d48: f443 2380 orr.w r3, r3, #262144 @ 0x40000 + 8000d4c: 6153 str r3, [r2, #20] + 8000d4e: 4b25 ldr r3, [pc, #148] @ (8000de4 ) + 8000d50: 695b ldr r3, [r3, #20] + 8000d52: f403 2380 and.w r3, r3, #262144 @ 0x40000 + 8000d56: 607b str r3, [r7, #4] + 8000d58: 687b ldr r3, [r7, #4] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOB, IN12_Pin|IN11_Pin|IN13_Pin|IN9_Pin - 8000d22: 2200 movs r2, #0 - 8000d24: f64f 7176 movw r1, #65398 @ 0xff76 - 8000d28: 4821 ldr r0, [pc, #132] @ (8000db0 ) - 8000d2a: f002 fd53 bl 80037d4 + 8000d5a: 2200 movs r2, #0 + 8000d5c: f64f 7176 movw r1, #65398 @ 0xff76 + 8000d60: 4821 ldr r0, [pc, #132] @ (8000de8 ) + 8000d62: f002 fd53 bl 800380c |IN3_Pin|IN8_Pin|IN5_Pin|IN4_Pin |DSEL0_Pin|DSEL1_Pin|PC_EN_Pin|IN7_Pin |IN10_Pin, GPIO_PIN_RESET); /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOC, LED4_Pin|LED3_Pin|LED2_Pin|LED1_Pin, GPIO_PIN_RESET); - 8000d2e: 2200 movs r2, #0 - 8000d30: f44f 7170 mov.w r1, #960 @ 0x3c0 - 8000d34: 481f ldr r0, [pc, #124] @ (8000db4 ) - 8000d36: f002 fd4d bl 80037d4 + 8000d66: 2200 movs r2, #0 + 8000d68: f44f 7170 mov.w r1, #960 @ 0x3c0 + 8000d6c: 481f ldr r0, [pc, #124] @ (8000dec ) + 8000d6e: f002 fd4d bl 800380c /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOA, IN2_Pin|IN1_Pin|IN6_Pin, GPIO_PIN_RESET); - 8000d3a: 2200 movs r2, #0 - 8000d3c: f44f 61e0 mov.w r1, #1792 @ 0x700 - 8000d40: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 - 8000d44: f002 fd46 bl 80037d4 + 8000d72: 2200 movs r2, #0 + 8000d74: f44f 61e0 mov.w r1, #1792 @ 0x700 + 8000d78: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 + 8000d7c: f002 fd46 bl 800380c /*Configure GPIO pins : IN12_Pin IN11_Pin IN13_Pin IN9_Pin IN3_Pin IN8_Pin IN5_Pin IN4_Pin DSEL0_Pin DSEL1_Pin PC_EN_Pin IN7_Pin IN10_Pin */ GPIO_InitStruct.Pin = IN12_Pin|IN11_Pin|IN13_Pin|IN9_Pin - 8000d48: f64f 7376 movw r3, #65398 @ 0xff76 - 8000d4c: 617b str r3, [r7, #20] + 8000d80: f64f 7376 movw r3, #65398 @ 0xff76 + 8000d84: 617b str r3, [r7, #20] |IN3_Pin|IN8_Pin|IN5_Pin|IN4_Pin |DSEL0_Pin|DSEL1_Pin|PC_EN_Pin|IN7_Pin |IN10_Pin; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; - 8000d4e: 2301 movs r3, #1 - 8000d50: 61bb str r3, [r7, #24] + 8000d86: 2301 movs r3, #1 + 8000d88: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; - 8000d52: 2300 movs r3, #0 - 8000d54: 61fb str r3, [r7, #28] + 8000d8a: 2300 movs r3, #0 + 8000d8c: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - 8000d56: 2300 movs r3, #0 - 8000d58: 623b str r3, [r7, #32] + 8000d8e: 2300 movs r3, #0 + 8000d90: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); - 8000d5a: f107 0314 add.w r3, r7, #20 - 8000d5e: 4619 mov r1, r3 - 8000d60: 4813 ldr r0, [pc, #76] @ (8000db0 ) - 8000d62: f002 fbbd bl 80034e0 + 8000d92: f107 0314 add.w r3, r7, #20 + 8000d96: 4619 mov r1, r3 + 8000d98: 4813 ldr r0, [pc, #76] @ (8000de8 ) + 8000d9a: f002 fbbd bl 8003518 /*Configure GPIO pins : LED4_Pin LED3_Pin LED2_Pin LED1_Pin */ GPIO_InitStruct.Pin = LED4_Pin|LED3_Pin|LED2_Pin|LED1_Pin; - 8000d66: f44f 7370 mov.w r3, #960 @ 0x3c0 - 8000d6a: 617b str r3, [r7, #20] + 8000d9e: f44f 7370 mov.w r3, #960 @ 0x3c0 + 8000da2: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; - 8000d6c: 2301 movs r3, #1 - 8000d6e: 61bb str r3, [r7, #24] + 8000da4: 2301 movs r3, #1 + 8000da6: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; - 8000d70: 2300 movs r3, #0 - 8000d72: 61fb str r3, [r7, #28] + 8000da8: 2300 movs r3, #0 + 8000daa: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - 8000d74: 2300 movs r3, #0 - 8000d76: 623b str r3, [r7, #32] + 8000dac: 2300 movs r3, #0 + 8000dae: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); - 8000d78: f107 0314 add.w r3, r7, #20 - 8000d7c: 4619 mov r1, r3 - 8000d7e: 480d ldr r0, [pc, #52] @ (8000db4 ) - 8000d80: f002 fbae bl 80034e0 + 8000db0: f107 0314 add.w r3, r7, #20 + 8000db4: 4619 mov r1, r3 + 8000db6: 480d ldr r0, [pc, #52] @ (8000dec ) + 8000db8: f002 fbae bl 8003518 /*Configure GPIO pins : IN2_Pin IN1_Pin IN6_Pin */ GPIO_InitStruct.Pin = IN2_Pin|IN1_Pin|IN6_Pin; - 8000d84: f44f 63e0 mov.w r3, #1792 @ 0x700 - 8000d88: 617b str r3, [r7, #20] + 8000dbc: f44f 63e0 mov.w r3, #1792 @ 0x700 + 8000dc0: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; - 8000d8a: 2301 movs r3, #1 - 8000d8c: 61bb str r3, [r7, #24] + 8000dc2: 2301 movs r3, #1 + 8000dc4: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; - 8000d8e: 2300 movs r3, #0 - 8000d90: 61fb str r3, [r7, #28] + 8000dc6: 2300 movs r3, #0 + 8000dc8: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - 8000d92: 2300 movs r3, #0 - 8000d94: 623b str r3, [r7, #32] + 8000dca: 2300 movs r3, #0 + 8000dcc: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - 8000d96: f107 0314 add.w r3, r7, #20 - 8000d9a: 4619 mov r1, r3 - 8000d9c: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 - 8000da0: f002 fb9e bl 80034e0 + 8000dce: f107 0314 add.w r3, r7, #20 + 8000dd2: 4619 mov r1, r3 + 8000dd4: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 + 8000dd8: f002 fb9e bl 8003518 /* USER CODE BEGIN MX_GPIO_Init_2 */ /* USER CODE END MX_GPIO_Init_2 */ } - 8000da4: bf00 nop - 8000da6: 3728 adds r7, #40 @ 0x28 - 8000da8: 46bd mov sp, r7 - 8000daa: bd80 pop {r7, pc} - 8000dac: 40021000 .word 0x40021000 - 8000db0: 48000400 .word 0x48000400 - 8000db4: 48000800 .word 0x48000800 + 8000ddc: bf00 nop + 8000dde: 3728 adds r7, #40 @ 0x28 + 8000de0: 46bd mov sp, r7 + 8000de2: bd80 pop {r7, pc} + 8000de4: 40021000 .word 0x40021000 + 8000de8: 48000400 .word 0x48000400 + 8000dec: 48000800 .word 0x48000800 -08000db8 : +08000df0 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { - 8000db8: b480 push {r7} - 8000dba: af00 add r7, sp, #0 + 8000df0: b480 push {r7} + 8000df2: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); - 8000dbc: b672 cpsid i + 8000df4: b672 cpsid i } - 8000dbe: bf00 nop + 8000df6: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) - 8000dc0: bf00 nop - 8000dc2: e7fd b.n 8000dc0 + 8000df8: bf00 nop + 8000dfa: e7fd b.n 8000df8 -08000dc4 : +08000dfc : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { - 8000dc4: b480 push {r7} - 8000dc6: b083 sub sp, #12 - 8000dc8: af00 add r7, sp, #0 + 8000dfc: b480 push {r7} + 8000dfe: b083 sub sp, #12 + 8000e00: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_SYSCFG_CLK_ENABLE(); - 8000dca: 4b0f ldr r3, [pc, #60] @ (8000e08 ) - 8000dcc: 699b ldr r3, [r3, #24] - 8000dce: 4a0e ldr r2, [pc, #56] @ (8000e08 ) - 8000dd0: f043 0301 orr.w r3, r3, #1 - 8000dd4: 6193 str r3, [r2, #24] - 8000dd6: 4b0c ldr r3, [pc, #48] @ (8000e08 ) - 8000dd8: 699b ldr r3, [r3, #24] - 8000dda: f003 0301 and.w r3, r3, #1 - 8000dde: 607b str r3, [r7, #4] - 8000de0: 687b ldr r3, [r7, #4] + 8000e02: 4b0f ldr r3, [pc, #60] @ (8000e40 ) + 8000e04: 699b ldr r3, [r3, #24] + 8000e06: 4a0e ldr r2, [pc, #56] @ (8000e40 ) + 8000e08: f043 0301 orr.w r3, r3, #1 + 8000e0c: 6193 str r3, [r2, #24] + 8000e0e: 4b0c ldr r3, [pc, #48] @ (8000e40 ) + 8000e10: 699b ldr r3, [r3, #24] + 8000e12: f003 0301 and.w r3, r3, #1 + 8000e16: 607b str r3, [r7, #4] + 8000e18: 687b ldr r3, [r7, #4] __HAL_RCC_PWR_CLK_ENABLE(); - 8000de2: 4b09 ldr r3, [pc, #36] @ (8000e08 ) - 8000de4: 69db ldr r3, [r3, #28] - 8000de6: 4a08 ldr r2, [pc, #32] @ (8000e08 ) - 8000de8: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 - 8000dec: 61d3 str r3, [r2, #28] - 8000dee: 4b06 ldr r3, [pc, #24] @ (8000e08 ) - 8000df0: 69db ldr r3, [r3, #28] - 8000df2: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 - 8000df6: 603b str r3, [r7, #0] - 8000df8: 683b ldr r3, [r7, #0] + 8000e1a: 4b09 ldr r3, [pc, #36] @ (8000e40 ) + 8000e1c: 69db ldr r3, [r3, #28] + 8000e1e: 4a08 ldr r2, [pc, #32] @ (8000e40 ) + 8000e20: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 8000e24: 61d3 str r3, [r2, #28] + 8000e26: 4b06 ldr r3, [pc, #24] @ (8000e40 ) + 8000e28: 69db ldr r3, [r3, #28] + 8000e2a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 8000e2e: 603b str r3, [r7, #0] + 8000e30: 683b ldr r3, [r7, #0] /* System interrupt init*/ /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } - 8000dfa: bf00 nop - 8000dfc: 370c adds r7, #12 - 8000dfe: 46bd mov sp, r7 - 8000e00: f85d 7b04 ldr.w r7, [sp], #4 - 8000e04: 4770 bx lr - 8000e06: bf00 nop - 8000e08: 40021000 .word 0x40021000 + 8000e32: bf00 nop + 8000e34: 370c adds r7, #12 + 8000e36: 46bd mov sp, r7 + 8000e38: f85d 7b04 ldr.w r7, [sp], #4 + 8000e3c: 4770 bx lr + 8000e3e: bf00 nop + 8000e40: 40021000 .word 0x40021000 -08000e0c : +08000e44 : * This function configures the hardware resources used in this example * @param hadc: ADC handle pointer * @retval None */ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) { - 8000e0c: b580 push {r7, lr} - 8000e0e: b08e sub sp, #56 @ 0x38 - 8000e10: af00 add r7, sp, #0 - 8000e12: 6078 str r0, [r7, #4] + 8000e44: b580 push {r7, lr} + 8000e46: b08e sub sp, #56 @ 0x38 + 8000e48: af00 add r7, sp, #0 + 8000e4a: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; - 8000e14: f107 0324 add.w r3, r7, #36 @ 0x24 - 8000e18: 2200 movs r2, #0 - 8000e1a: 601a str r2, [r3, #0] - 8000e1c: 605a str r2, [r3, #4] - 8000e1e: 609a str r2, [r3, #8] - 8000e20: 60da str r2, [r3, #12] - 8000e22: 611a str r2, [r3, #16] + 8000e4c: f107 0324 add.w r3, r7, #36 @ 0x24 + 8000e50: 2200 movs r2, #0 + 8000e52: 601a str r2, [r3, #0] + 8000e54: 605a str r2, [r3, #4] + 8000e56: 609a str r2, [r3, #8] + 8000e58: 60da str r2, [r3, #12] + 8000e5a: 611a str r2, [r3, #16] if(hadc->Instance==ADC1) - 8000e24: 687b ldr r3, [r7, #4] - 8000e26: 681b ldr r3, [r3, #0] - 8000e28: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 - 8000e2c: f040 808f bne.w 8000f4e + 8000e5c: 687b ldr r3, [r7, #4] + 8000e5e: 681b ldr r3, [r3, #0] + 8000e60: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 + 8000e64: f040 808f bne.w 8000f86 { /* USER CODE BEGIN ADC1_MspInit 0 */ /* USER CODE END ADC1_MspInit 0 */ /* Peripheral clock enable */ HAL_RCC_ADC12_CLK_ENABLED++; - 8000e30: 4b86 ldr r3, [pc, #536] @ (800104c ) - 8000e32: 681b ldr r3, [r3, #0] - 8000e34: 3301 adds r3, #1 - 8000e36: 4a85 ldr r2, [pc, #532] @ (800104c ) - 8000e38: 6013 str r3, [r2, #0] + 8000e68: 4b86 ldr r3, [pc, #536] @ (8001084 ) + 8000e6a: 681b ldr r3, [r3, #0] + 8000e6c: 3301 adds r3, #1 + 8000e6e: 4a85 ldr r2, [pc, #532] @ (8001084 ) + 8000e70: 6013 str r3, [r2, #0] if(HAL_RCC_ADC12_CLK_ENABLED==1){ - 8000e3a: 4b84 ldr r3, [pc, #528] @ (800104c ) - 8000e3c: 681b ldr r3, [r3, #0] - 8000e3e: 2b01 cmp r3, #1 - 8000e40: d10b bne.n 8000e5a + 8000e72: 4b84 ldr r3, [pc, #528] @ (8001084 ) + 8000e74: 681b ldr r3, [r3, #0] + 8000e76: 2b01 cmp r3, #1 + 8000e78: d10b bne.n 8000e92 __HAL_RCC_ADC12_CLK_ENABLE(); - 8000e42: 4b83 ldr r3, [pc, #524] @ (8001050 ) - 8000e44: 695b ldr r3, [r3, #20] - 8000e46: 4a82 ldr r2, [pc, #520] @ (8001050 ) - 8000e48: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 - 8000e4c: 6153 str r3, [r2, #20] - 8000e4e: 4b80 ldr r3, [pc, #512] @ (8001050 ) - 8000e50: 695b ldr r3, [r3, #20] - 8000e52: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 - 8000e56: 623b str r3, [r7, #32] - 8000e58: 6a3b ldr r3, [r7, #32] + 8000e7a: 4b83 ldr r3, [pc, #524] @ (8001088 ) + 8000e7c: 695b ldr r3, [r3, #20] + 8000e7e: 4a82 ldr r2, [pc, #520] @ (8001088 ) + 8000e80: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 8000e84: 6153 str r3, [r2, #20] + 8000e86: 4b80 ldr r3, [pc, #512] @ (8001088 ) + 8000e88: 695b ldr r3, [r3, #20] + 8000e8a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 8000e8e: 623b str r3, [r7, #32] + 8000e90: 6a3b ldr r3, [r7, #32] } __HAL_RCC_GPIOC_CLK_ENABLE(); - 8000e5a: 4b7d ldr r3, [pc, #500] @ (8001050 ) - 8000e5c: 695b ldr r3, [r3, #20] - 8000e5e: 4a7c ldr r2, [pc, #496] @ (8001050 ) - 8000e60: f443 2300 orr.w r3, r3, #524288 @ 0x80000 - 8000e64: 6153 str r3, [r2, #20] - 8000e66: 4b7a ldr r3, [pc, #488] @ (8001050 ) - 8000e68: 695b ldr r3, [r3, #20] - 8000e6a: f403 2300 and.w r3, r3, #524288 @ 0x80000 - 8000e6e: 61fb str r3, [r7, #28] - 8000e70: 69fb ldr r3, [r7, #28] + 8000e92: 4b7d ldr r3, [pc, #500] @ (8001088 ) + 8000e94: 695b ldr r3, [r3, #20] + 8000e96: 4a7c ldr r2, [pc, #496] @ (8001088 ) + 8000e98: f443 2300 orr.w r3, r3, #524288 @ 0x80000 + 8000e9c: 6153 str r3, [r2, #20] + 8000e9e: 4b7a ldr r3, [pc, #488] @ (8001088 ) + 8000ea0: 695b ldr r3, [r3, #20] + 8000ea2: f403 2300 and.w r3, r3, #524288 @ 0x80000 + 8000ea6: 61fb str r3, [r7, #28] + 8000ea8: 69fb ldr r3, [r7, #28] __HAL_RCC_GPIOA_CLK_ENABLE(); - 8000e72: 4b77 ldr r3, [pc, #476] @ (8001050 ) - 8000e74: 695b ldr r3, [r3, #20] - 8000e76: 4a76 ldr r2, [pc, #472] @ (8001050 ) - 8000e78: f443 3300 orr.w r3, r3, #131072 @ 0x20000 - 8000e7c: 6153 str r3, [r2, #20] - 8000e7e: 4b74 ldr r3, [pc, #464] @ (8001050 ) - 8000e80: 695b ldr r3, [r3, #20] - 8000e82: f403 3300 and.w r3, r3, #131072 @ 0x20000 - 8000e86: 61bb str r3, [r7, #24] - 8000e88: 69bb ldr r3, [r7, #24] + 8000eaa: 4b77 ldr r3, [pc, #476] @ (8001088 ) + 8000eac: 695b ldr r3, [r3, #20] + 8000eae: 4a76 ldr r2, [pc, #472] @ (8001088 ) + 8000eb0: f443 3300 orr.w r3, r3, #131072 @ 0x20000 + 8000eb4: 6153 str r3, [r2, #20] + 8000eb6: 4b74 ldr r3, [pc, #464] @ (8001088 ) + 8000eb8: 695b ldr r3, [r3, #20] + 8000eba: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 8000ebe: 61bb str r3, [r7, #24] + 8000ec0: 69bb ldr r3, [r7, #24] __HAL_RCC_GPIOF_CLK_ENABLE(); - 8000e8a: 4b71 ldr r3, [pc, #452] @ (8001050 ) - 8000e8c: 695b ldr r3, [r3, #20] - 8000e8e: 4a70 ldr r2, [pc, #448] @ (8001050 ) - 8000e90: f443 0380 orr.w r3, r3, #4194304 @ 0x400000 - 8000e94: 6153 str r3, [r2, #20] - 8000e96: 4b6e ldr r3, [pc, #440] @ (8001050 ) - 8000e98: 695b ldr r3, [r3, #20] - 8000e9a: f403 0380 and.w r3, r3, #4194304 @ 0x400000 - 8000e9e: 617b str r3, [r7, #20] - 8000ea0: 697b ldr r3, [r7, #20] + 8000ec2: 4b71 ldr r3, [pc, #452] @ (8001088 ) + 8000ec4: 695b ldr r3, [r3, #20] + 8000ec6: 4a70 ldr r2, [pc, #448] @ (8001088 ) + 8000ec8: f443 0380 orr.w r3, r3, #4194304 @ 0x400000 + 8000ecc: 6153 str r3, [r2, #20] + 8000ece: 4b6e ldr r3, [pc, #440] @ (8001088 ) + 8000ed0: 695b ldr r3, [r3, #20] + 8000ed2: f403 0380 and.w r3, r3, #4194304 @ 0x400000 + 8000ed6: 617b str r3, [r7, #20] + 8000ed8: 697b ldr r3, [r7, #20] PA1 ------> ADC1_IN2 PA2 ------> ADC1_IN3 PA3 ------> ADC1_IN4 PF4 ------> ADC1_IN5 */ GPIO_InitStruct.Pin = LVMS_Vsense_Pin|IS10_Pin|IS6_Pin; - 8000ea2: 2307 movs r3, #7 - 8000ea4: 627b str r3, [r7, #36] @ 0x24 + 8000eda: 2307 movs r3, #7 + 8000edc: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; - 8000ea6: 2303 movs r3, #3 - 8000ea8: 62bb str r3, [r7, #40] @ 0x28 + 8000ede: 2303 movs r3, #3 + 8000ee0: 62bb str r3, [r7, #40] @ 0x28 GPIO_InitStruct.Pull = GPIO_NOPULL; - 8000eaa: 2300 movs r3, #0 - 8000eac: 62fb str r3, [r7, #44] @ 0x2c + 8000ee2: 2300 movs r3, #0 + 8000ee4: 62fb str r3, [r7, #44] @ 0x2c HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); - 8000eae: f107 0324 add.w r3, r7, #36 @ 0x24 - 8000eb2: 4619 mov r1, r3 - 8000eb4: 4867 ldr r0, [pc, #412] @ (8001054 ) - 8000eb6: f002 fb13 bl 80034e0 + 8000ee6: f107 0324 add.w r3, r7, #36 @ 0x24 + 8000eea: 4619 mov r1, r3 + 8000eec: 4867 ldr r0, [pc, #412] @ (800108c ) + 8000eee: f002 fb13 bl 8003518 GPIO_InitStruct.Pin = ASMS_Vsense_Pin|IS1_Pin|IS2_Pin|IS9_Pin; - 8000eba: 230f movs r3, #15 - 8000ebc: 627b str r3, [r7, #36] @ 0x24 + 8000ef2: 230f movs r3, #15 + 8000ef4: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; - 8000ebe: 2303 movs r3, #3 - 8000ec0: 62bb str r3, [r7, #40] @ 0x28 + 8000ef6: 2303 movs r3, #3 + 8000ef8: 62bb str r3, [r7, #40] @ 0x28 GPIO_InitStruct.Pull = GPIO_NOPULL; - 8000ec2: 2300 movs r3, #0 - 8000ec4: 62fb str r3, [r7, #44] @ 0x2c + 8000efa: 2300 movs r3, #0 + 8000efc: 62fb str r3, [r7, #44] @ 0x2c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - 8000ec6: f107 0324 add.w r3, r7, #36 @ 0x24 - 8000eca: 4619 mov r1, r3 - 8000ecc: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 - 8000ed0: f002 fb06 bl 80034e0 + 8000efe: f107 0324 add.w r3, r7, #36 @ 0x24 + 8000f02: 4619 mov r1, r3 + 8000f04: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 + 8000f08: f002 fb06 bl 8003518 GPIO_InitStruct.Pin = IS11_Pin; - 8000ed4: 2310 movs r3, #16 - 8000ed6: 627b str r3, [r7, #36] @ 0x24 + 8000f0c: 2310 movs r3, #16 + 8000f0e: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; - 8000ed8: 2303 movs r3, #3 - 8000eda: 62bb str r3, [r7, #40] @ 0x28 + 8000f10: 2303 movs r3, #3 + 8000f12: 62bb str r3, [r7, #40] @ 0x28 GPIO_InitStruct.Pull = GPIO_NOPULL; - 8000edc: 2300 movs r3, #0 - 8000ede: 62fb str r3, [r7, #44] @ 0x2c + 8000f14: 2300 movs r3, #0 + 8000f16: 62fb str r3, [r7, #44] @ 0x2c HAL_GPIO_Init(IS11_GPIO_Port, &GPIO_InitStruct); - 8000ee0: f107 0324 add.w r3, r7, #36 @ 0x24 - 8000ee4: 4619 mov r1, r3 - 8000ee6: 485c ldr r0, [pc, #368] @ (8001058 ) - 8000ee8: f002 fafa bl 80034e0 + 8000f18: f107 0324 add.w r3, r7, #36 @ 0x24 + 8000f1c: 4619 mov r1, r3 + 8000f1e: 485c ldr r0, [pc, #368] @ (8001090 ) + 8000f20: f002 fafa bl 8003518 /* ADC1 DMA Init */ /* ADC1 Init */ hdma_adc1.Instance = DMA1_Channel1; - 8000eec: 4b5b ldr r3, [pc, #364] @ (800105c ) - 8000eee: 4a5c ldr r2, [pc, #368] @ (8001060 ) - 8000ef0: 601a str r2, [r3, #0] + 8000f24: 4b5b ldr r3, [pc, #364] @ (8001094 ) + 8000f26: 4a5c ldr r2, [pc, #368] @ (8001098 ) + 8000f28: 601a str r2, [r3, #0] hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY; - 8000ef2: 4b5a ldr r3, [pc, #360] @ (800105c ) - 8000ef4: 2200 movs r2, #0 - 8000ef6: 605a str r2, [r3, #4] + 8000f2a: 4b5a ldr r3, [pc, #360] @ (8001094 ) + 8000f2c: 2200 movs r2, #0 + 8000f2e: 605a str r2, [r3, #4] hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE; - 8000ef8: 4b58 ldr r3, [pc, #352] @ (800105c ) - 8000efa: 2200 movs r2, #0 - 8000efc: 609a str r2, [r3, #8] + 8000f30: 4b58 ldr r3, [pc, #352] @ (8001094 ) + 8000f32: 2200 movs r2, #0 + 8000f34: 609a str r2, [r3, #8] hdma_adc1.Init.MemInc = DMA_MINC_ENABLE; - 8000efe: 4b57 ldr r3, [pc, #348] @ (800105c ) - 8000f00: 2280 movs r2, #128 @ 0x80 - 8000f02: 60da str r2, [r3, #12] + 8000f36: 4b57 ldr r3, [pc, #348] @ (8001094 ) + 8000f38: 2280 movs r2, #128 @ 0x80 + 8000f3a: 60da str r2, [r3, #12] hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; - 8000f04: 4b55 ldr r3, [pc, #340] @ (800105c ) - 8000f06: f44f 7280 mov.w r2, #256 @ 0x100 - 8000f0a: 611a str r2, [r3, #16] + 8000f3c: 4b55 ldr r3, [pc, #340] @ (8001094 ) + 8000f3e: f44f 7280 mov.w r2, #256 @ 0x100 + 8000f42: 611a str r2, [r3, #16] hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; - 8000f0c: 4b53 ldr r3, [pc, #332] @ (800105c ) - 8000f0e: f44f 6280 mov.w r2, #1024 @ 0x400 - 8000f12: 615a str r2, [r3, #20] + 8000f44: 4b53 ldr r3, [pc, #332] @ (8001094 ) + 8000f46: f44f 6280 mov.w r2, #1024 @ 0x400 + 8000f4a: 615a str r2, [r3, #20] hdma_adc1.Init.Mode = DMA_CIRCULAR; - 8000f14: 4b51 ldr r3, [pc, #324] @ (800105c ) - 8000f16: 2220 movs r2, #32 - 8000f18: 619a str r2, [r3, #24] + 8000f4c: 4b51 ldr r3, [pc, #324] @ (8001094 ) + 8000f4e: 2220 movs r2, #32 + 8000f50: 619a str r2, [r3, #24] hdma_adc1.Init.Priority = DMA_PRIORITY_LOW; - 8000f1a: 4b50 ldr r3, [pc, #320] @ (800105c ) - 8000f1c: 2200 movs r2, #0 - 8000f1e: 61da str r2, [r3, #28] + 8000f52: 4b50 ldr r3, [pc, #320] @ (8001094 ) + 8000f54: 2200 movs r2, #0 + 8000f56: 61da str r2, [r3, #28] if (HAL_DMA_Init(&hdma_adc1) != HAL_OK) - 8000f20: 484e ldr r0, [pc, #312] @ (800105c ) - 8000f22: f002 f9b6 bl 8003292 - 8000f26: 4603 mov r3, r0 - 8000f28: 2b00 cmp r3, #0 - 8000f2a: d001 beq.n 8000f30 + 8000f58: 484e ldr r0, [pc, #312] @ (8001094 ) + 8000f5a: f002 f9b6 bl 80032ca + 8000f5e: 4603 mov r3, r0 + 8000f60: 2b00 cmp r3, #0 + 8000f62: d001 beq.n 8000f68 { Error_Handler(); - 8000f2c: f7ff ff44 bl 8000db8 + 8000f64: f7ff ff44 bl 8000df0 } __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc1); - 8000f30: 687b ldr r3, [r7, #4] - 8000f32: 4a4a ldr r2, [pc, #296] @ (800105c ) - 8000f34: 639a str r2, [r3, #56] @ 0x38 - 8000f36: 4a49 ldr r2, [pc, #292] @ (800105c ) - 8000f38: 687b ldr r3, [r7, #4] - 8000f3a: 6253 str r3, [r2, #36] @ 0x24 + 8000f68: 687b ldr r3, [r7, #4] + 8000f6a: 4a4a ldr r2, [pc, #296] @ (8001094 ) + 8000f6c: 639a str r2, [r3, #56] @ 0x38 + 8000f6e: 4a49 ldr r2, [pc, #292] @ (8001094 ) + 8000f70: 687b ldr r3, [r7, #4] + 8000f72: 6253 str r3, [r2, #36] @ 0x24 /* ADC1 interrupt Init */ HAL_NVIC_SetPriority(ADC1_2_IRQn, 0, 0); - 8000f3c: 2200 movs r2, #0 - 8000f3e: 2100 movs r1, #0 - 8000f40: 2012 movs r0, #18 - 8000f42: f002 f970 bl 8003226 + 8000f74: 2200 movs r2, #0 + 8000f76: 2100 movs r1, #0 + 8000f78: 2012 movs r0, #18 + 8000f7a: f002 f970 bl 800325e HAL_NVIC_EnableIRQ(ADC1_2_IRQn); - 8000f46: 2012 movs r0, #18 - 8000f48: f002 f989 bl 800325e + 8000f7e: 2012 movs r0, #18 + 8000f80: f002 f989 bl 8003296 /* USER CODE BEGIN ADC2_MspInit 1 */ /* USER CODE END ADC2_MspInit 1 */ } } - 8000f4c: e07a b.n 8001044 + 8000f84: e07a b.n 800107c else if(hadc->Instance==ADC2) - 8000f4e: 687b ldr r3, [r7, #4] - 8000f50: 681b ldr r3, [r3, #0] - 8000f52: 4a44 ldr r2, [pc, #272] @ (8001064 ) - 8000f54: 4293 cmp r3, r2 - 8000f56: d175 bne.n 8001044 + 8000f86: 687b ldr r3, [r7, #4] + 8000f88: 681b ldr r3, [r3, #0] + 8000f8a: 4a44 ldr r2, [pc, #272] @ (800109c ) + 8000f8c: 4293 cmp r3, r2 + 8000f8e: d175 bne.n 800107c HAL_RCC_ADC12_CLK_ENABLED++; - 8000f58: 4b3c ldr r3, [pc, #240] @ (800104c ) - 8000f5a: 681b ldr r3, [r3, #0] - 8000f5c: 3301 adds r3, #1 - 8000f5e: 4a3b ldr r2, [pc, #236] @ (800104c ) - 8000f60: 6013 str r3, [r2, #0] + 8000f90: 4b3c ldr r3, [pc, #240] @ (8001084 ) + 8000f92: 681b ldr r3, [r3, #0] + 8000f94: 3301 adds r3, #1 + 8000f96: 4a3b ldr r2, [pc, #236] @ (8001084 ) + 8000f98: 6013 str r3, [r2, #0] if(HAL_RCC_ADC12_CLK_ENABLED==1){ - 8000f62: 4b3a ldr r3, [pc, #232] @ (800104c ) - 8000f64: 681b ldr r3, [r3, #0] - 8000f66: 2b01 cmp r3, #1 - 8000f68: d10b bne.n 8000f82 + 8000f9a: 4b3a ldr r3, [pc, #232] @ (8001084 ) + 8000f9c: 681b ldr r3, [r3, #0] + 8000f9e: 2b01 cmp r3, #1 + 8000fa0: d10b bne.n 8000fba __HAL_RCC_ADC12_CLK_ENABLE(); - 8000f6a: 4b39 ldr r3, [pc, #228] @ (8001050 ) - 8000f6c: 695b ldr r3, [r3, #20] - 8000f6e: 4a38 ldr r2, [pc, #224] @ (8001050 ) - 8000f70: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 - 8000f74: 6153 str r3, [r2, #20] - 8000f76: 4b36 ldr r3, [pc, #216] @ (8001050 ) - 8000f78: 695b ldr r3, [r3, #20] - 8000f7a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 - 8000f7e: 613b str r3, [r7, #16] - 8000f80: 693b ldr r3, [r7, #16] + 8000fa2: 4b39 ldr r3, [pc, #228] @ (8001088 ) + 8000fa4: 695b ldr r3, [r3, #20] + 8000fa6: 4a38 ldr r2, [pc, #224] @ (8001088 ) + 8000fa8: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 8000fac: 6153 str r3, [r2, #20] + 8000fae: 4b36 ldr r3, [pc, #216] @ (8001088 ) + 8000fb0: 695b ldr r3, [r3, #20] + 8000fb2: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 8000fb6: 613b str r3, [r7, #16] + 8000fb8: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOC_CLK_ENABLE(); - 8000f82: 4b33 ldr r3, [pc, #204] @ (8001050 ) - 8000f84: 695b ldr r3, [r3, #20] - 8000f86: 4a32 ldr r2, [pc, #200] @ (8001050 ) - 8000f88: f443 2300 orr.w r3, r3, #524288 @ 0x80000 - 8000f8c: 6153 str r3, [r2, #20] - 8000f8e: 4b30 ldr r3, [pc, #192] @ (8001050 ) - 8000f90: 695b ldr r3, [r3, #20] - 8000f92: f403 2300 and.w r3, r3, #524288 @ 0x80000 - 8000f96: 60fb str r3, [r7, #12] - 8000f98: 68fb ldr r3, [r7, #12] + 8000fba: 4b33 ldr r3, [pc, #204] @ (8001088 ) + 8000fbc: 695b ldr r3, [r3, #20] + 8000fbe: 4a32 ldr r2, [pc, #200] @ (8001088 ) + 8000fc0: f443 2300 orr.w r3, r3, #524288 @ 0x80000 + 8000fc4: 6153 str r3, [r2, #20] + 8000fc6: 4b30 ldr r3, [pc, #192] @ (8001088 ) + 8000fc8: 695b ldr r3, [r3, #20] + 8000fca: f403 2300 and.w r3, r3, #524288 @ 0x80000 + 8000fce: 60fb str r3, [r7, #12] + 8000fd0: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOA_CLK_ENABLE(); - 8000f9a: 4b2d ldr r3, [pc, #180] @ (8001050 ) - 8000f9c: 695b ldr r3, [r3, #20] - 8000f9e: 4a2c ldr r2, [pc, #176] @ (8001050 ) - 8000fa0: f443 3300 orr.w r3, r3, #131072 @ 0x20000 - 8000fa4: 6153 str r3, [r2, #20] - 8000fa6: 4b2a ldr r3, [pc, #168] @ (8001050 ) - 8000fa8: 695b ldr r3, [r3, #20] - 8000faa: f403 3300 and.w r3, r3, #131072 @ 0x20000 - 8000fae: 60bb str r3, [r7, #8] - 8000fb0: 68bb ldr r3, [r7, #8] + 8000fd2: 4b2d ldr r3, [pc, #180] @ (8001088 ) + 8000fd4: 695b ldr r3, [r3, #20] + 8000fd6: 4a2c ldr r2, [pc, #176] @ (8001088 ) + 8000fd8: f443 3300 orr.w r3, r3, #131072 @ 0x20000 + 8000fdc: 6153 str r3, [r2, #20] + 8000fde: 4b2a ldr r3, [pc, #168] @ (8001088 ) + 8000fe0: 695b ldr r3, [r3, #20] + 8000fe2: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 8000fe6: 60bb str r3, [r7, #8] + 8000fe8: 68bb ldr r3, [r7, #8] GPIO_InitStruct.Pin = IS7_Pin|PC_Read_Pin; - 8000fb2: 2318 movs r3, #24 - 8000fb4: 627b str r3, [r7, #36] @ 0x24 + 8000fea: 2318 movs r3, #24 + 8000fec: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; - 8000fb6: 2303 movs r3, #3 - 8000fb8: 62bb str r3, [r7, #40] @ 0x28 + 8000fee: 2303 movs r3, #3 + 8000ff0: 62bb str r3, [r7, #40] @ 0x28 GPIO_InitStruct.Pull = GPIO_NOPULL; - 8000fba: 2300 movs r3, #0 - 8000fbc: 62fb str r3, [r7, #44] @ 0x2c + 8000ff2: 2300 movs r3, #0 + 8000ff4: 62fb str r3, [r7, #44] @ 0x2c HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); - 8000fbe: f107 0324 add.w r3, r7, #36 @ 0x24 - 8000fc2: 4619 mov r1, r3 - 8000fc4: 4823 ldr r0, [pc, #140] @ (8001054 ) - 8000fc6: f002 fa8b bl 80034e0 + 8000ff6: f107 0324 add.w r3, r7, #36 @ 0x24 + 8000ffa: 4619 mov r1, r3 + 8000ffc: 4823 ldr r0, [pc, #140] @ (800108c ) + 8000ffe: f002 fa8b bl 8003518 GPIO_InitStruct.Pin = IS3_Pin|IS8_Pin|IS4_Pin|IS5_Pin; - 8000fca: 23f0 movs r3, #240 @ 0xf0 - 8000fcc: 627b str r3, [r7, #36] @ 0x24 + 8001002: 23f0 movs r3, #240 @ 0xf0 + 8001004: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; - 8000fce: 2303 movs r3, #3 - 8000fd0: 62bb str r3, [r7, #40] @ 0x28 + 8001006: 2303 movs r3, #3 + 8001008: 62bb str r3, [r7, #40] @ 0x28 GPIO_InitStruct.Pull = GPIO_NOPULL; - 8000fd2: 2300 movs r3, #0 - 8000fd4: 62fb str r3, [r7, #44] @ 0x2c + 800100a: 2300 movs r3, #0 + 800100c: 62fb str r3, [r7, #44] @ 0x2c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - 8000fd6: f107 0324 add.w r3, r7, #36 @ 0x24 - 8000fda: 4619 mov r1, r3 - 8000fdc: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 - 8000fe0: f002 fa7e bl 80034e0 + 800100e: f107 0324 add.w r3, r7, #36 @ 0x24 + 8001012: 4619 mov r1, r3 + 8001014: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 + 8001018: f002 fa7e bl 8003518 hdma_adc2.Instance = DMA2_Channel1; - 8000fe4: 4b20 ldr r3, [pc, #128] @ (8001068 ) - 8000fe6: 4a21 ldr r2, [pc, #132] @ (800106c ) - 8000fe8: 601a str r2, [r3, #0] + 800101c: 4b20 ldr r3, [pc, #128] @ (80010a0 ) + 800101e: 4a21 ldr r2, [pc, #132] @ (80010a4 ) + 8001020: 601a str r2, [r3, #0] hdma_adc2.Init.Direction = DMA_PERIPH_TO_MEMORY; - 8000fea: 4b1f ldr r3, [pc, #124] @ (8001068 ) - 8000fec: 2200 movs r2, #0 - 8000fee: 605a str r2, [r3, #4] + 8001022: 4b1f ldr r3, [pc, #124] @ (80010a0 ) + 8001024: 2200 movs r2, #0 + 8001026: 605a str r2, [r3, #4] hdma_adc2.Init.PeriphInc = DMA_PINC_DISABLE; - 8000ff0: 4b1d ldr r3, [pc, #116] @ (8001068 ) - 8000ff2: 2200 movs r2, #0 - 8000ff4: 609a str r2, [r3, #8] + 8001028: 4b1d ldr r3, [pc, #116] @ (80010a0 ) + 800102a: 2200 movs r2, #0 + 800102c: 609a str r2, [r3, #8] hdma_adc2.Init.MemInc = DMA_MINC_ENABLE; - 8000ff6: 4b1c ldr r3, [pc, #112] @ (8001068 ) - 8000ff8: 2280 movs r2, #128 @ 0x80 - 8000ffa: 60da str r2, [r3, #12] + 800102e: 4b1c ldr r3, [pc, #112] @ (80010a0 ) + 8001030: 2280 movs r2, #128 @ 0x80 + 8001032: 60da str r2, [r3, #12] hdma_adc2.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; - 8000ffc: 4b1a ldr r3, [pc, #104] @ (8001068 ) - 8000ffe: f44f 7280 mov.w r2, #256 @ 0x100 - 8001002: 611a str r2, [r3, #16] + 8001034: 4b1a ldr r3, [pc, #104] @ (80010a0 ) + 8001036: f44f 7280 mov.w r2, #256 @ 0x100 + 800103a: 611a str r2, [r3, #16] hdma_adc2.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; - 8001004: 4b18 ldr r3, [pc, #96] @ (8001068 ) - 8001006: f44f 6280 mov.w r2, #1024 @ 0x400 - 800100a: 615a str r2, [r3, #20] + 800103c: 4b18 ldr r3, [pc, #96] @ (80010a0 ) + 800103e: f44f 6280 mov.w r2, #1024 @ 0x400 + 8001042: 615a str r2, [r3, #20] hdma_adc2.Init.Mode = DMA_CIRCULAR; - 800100c: 4b16 ldr r3, [pc, #88] @ (8001068 ) - 800100e: 2220 movs r2, #32 - 8001010: 619a str r2, [r3, #24] + 8001044: 4b16 ldr r3, [pc, #88] @ (80010a0 ) + 8001046: 2220 movs r2, #32 + 8001048: 619a str r2, [r3, #24] hdma_adc2.Init.Priority = DMA_PRIORITY_LOW; - 8001012: 4b15 ldr r3, [pc, #84] @ (8001068 ) - 8001014: 2200 movs r2, #0 - 8001016: 61da str r2, [r3, #28] + 800104a: 4b15 ldr r3, [pc, #84] @ (80010a0 ) + 800104c: 2200 movs r2, #0 + 800104e: 61da str r2, [r3, #28] if (HAL_DMA_Init(&hdma_adc2) != HAL_OK) - 8001018: 4813 ldr r0, [pc, #76] @ (8001068 ) - 800101a: f002 f93a bl 8003292 - 800101e: 4603 mov r3, r0 - 8001020: 2b00 cmp r3, #0 - 8001022: d001 beq.n 8001028 + 8001050: 4813 ldr r0, [pc, #76] @ (80010a0 ) + 8001052: f002 f93a bl 80032ca + 8001056: 4603 mov r3, r0 + 8001058: 2b00 cmp r3, #0 + 800105a: d001 beq.n 8001060 Error_Handler(); - 8001024: f7ff fec8 bl 8000db8 + 800105c: f7ff fec8 bl 8000df0 __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc2); - 8001028: 687b ldr r3, [r7, #4] - 800102a: 4a0f ldr r2, [pc, #60] @ (8001068 ) - 800102c: 639a str r2, [r3, #56] @ 0x38 - 800102e: 4a0e ldr r2, [pc, #56] @ (8001068 ) - 8001030: 687b ldr r3, [r7, #4] - 8001032: 6253 str r3, [r2, #36] @ 0x24 + 8001060: 687b ldr r3, [r7, #4] + 8001062: 4a0f ldr r2, [pc, #60] @ (80010a0 ) + 8001064: 639a str r2, [r3, #56] @ 0x38 + 8001066: 4a0e ldr r2, [pc, #56] @ (80010a0 ) + 8001068: 687b ldr r3, [r7, #4] + 800106a: 6253 str r3, [r2, #36] @ 0x24 HAL_NVIC_SetPriority(ADC1_2_IRQn, 0, 0); - 8001034: 2200 movs r2, #0 - 8001036: 2100 movs r1, #0 - 8001038: 2012 movs r0, #18 - 800103a: f002 f8f4 bl 8003226 + 800106c: 2200 movs r2, #0 + 800106e: 2100 movs r1, #0 + 8001070: 2012 movs r0, #18 + 8001072: f002 f8f4 bl 800325e HAL_NVIC_EnableIRQ(ADC1_2_IRQn); - 800103e: 2012 movs r0, #18 - 8001040: f002 f90d bl 800325e + 8001076: 2012 movs r0, #18 + 8001078: f002 f90d bl 8003296 } - 8001044: bf00 nop - 8001046: 3738 adds r7, #56 @ 0x38 - 8001048: 46bd mov sp, r7 - 800104a: bd80 pop {r7, pc} - 800104c: 200002b0 .word 0x200002b0 - 8001050: 40021000 .word 0x40021000 - 8001054: 48000800 .word 0x48000800 - 8001058: 48001400 .word 0x48001400 - 800105c: 2000011c .word 0x2000011c - 8001060: 40020008 .word 0x40020008 - 8001064: 50000100 .word 0x50000100 - 8001068: 20000160 .word 0x20000160 - 800106c: 40020408 .word 0x40020408 + 800107c: bf00 nop + 800107e: 3738 adds r7, #56 @ 0x38 + 8001080: 46bd mov sp, r7 + 8001082: bd80 pop {r7, pc} + 8001084: 200002b0 .word 0x200002b0 + 8001088: 40021000 .word 0x40021000 + 800108c: 48000800 .word 0x48000800 + 8001090: 48001400 .word 0x48001400 + 8001094: 2000011c .word 0x2000011c + 8001098: 40020008 .word 0x40020008 + 800109c: 50000100 .word 0x50000100 + 80010a0: 20000160 .word 0x20000160 + 80010a4: 40020408 .word 0x40020408 -08001070 : +080010a8 : * This function configures the hardware resources used in this example * @param hcan: CAN handle pointer * @retval None */ void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan) { - 8001070: b580 push {r7, lr} - 8001072: b08a sub sp, #40 @ 0x28 - 8001074: af00 add r7, sp, #0 - 8001076: 6078 str r0, [r7, #4] + 80010a8: b580 push {r7, lr} + 80010aa: b08a sub sp, #40 @ 0x28 + 80010ac: af00 add r7, sp, #0 + 80010ae: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; - 8001078: f107 0314 add.w r3, r7, #20 - 800107c: 2200 movs r2, #0 - 800107e: 601a str r2, [r3, #0] - 8001080: 605a str r2, [r3, #4] - 8001082: 609a str r2, [r3, #8] - 8001084: 60da str r2, [r3, #12] - 8001086: 611a str r2, [r3, #16] + 80010b0: f107 0314 add.w r3, r7, #20 + 80010b4: 2200 movs r2, #0 + 80010b6: 601a str r2, [r3, #0] + 80010b8: 605a str r2, [r3, #4] + 80010ba: 609a str r2, [r3, #8] + 80010bc: 60da str r2, [r3, #12] + 80010be: 611a str r2, [r3, #16] if(hcan->Instance==CAN) - 8001088: 687b ldr r3, [r7, #4] - 800108a: 681b ldr r3, [r3, #0] - 800108c: 4a20 ldr r2, [pc, #128] @ (8001110 ) - 800108e: 4293 cmp r3, r2 - 8001090: d139 bne.n 8001106 + 80010c0: 687b ldr r3, [r7, #4] + 80010c2: 681b ldr r3, [r3, #0] + 80010c4: 4a20 ldr r2, [pc, #128] @ (8001148 ) + 80010c6: 4293 cmp r3, r2 + 80010c8: d139 bne.n 800113e { /* USER CODE BEGIN CAN_MspInit 0 */ /* USER CODE END CAN_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_CAN1_CLK_ENABLE(); - 8001092: 4b20 ldr r3, [pc, #128] @ (8001114 ) - 8001094: 69db ldr r3, [r3, #28] - 8001096: 4a1f ldr r2, [pc, #124] @ (8001114 ) - 8001098: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 - 800109c: 61d3 str r3, [r2, #28] - 800109e: 4b1d ldr r3, [pc, #116] @ (8001114 ) - 80010a0: 69db ldr r3, [r3, #28] - 80010a2: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 - 80010a6: 613b str r3, [r7, #16] - 80010a8: 693b ldr r3, [r7, #16] + 80010ca: 4b20 ldr r3, [pc, #128] @ (800114c ) + 80010cc: 69db ldr r3, [r3, #28] + 80010ce: 4a1f ldr r2, [pc, #124] @ (800114c ) + 80010d0: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 + 80010d4: 61d3 str r3, [r2, #28] + 80010d6: 4b1d ldr r3, [pc, #116] @ (800114c ) + 80010d8: 69db ldr r3, [r3, #28] + 80010da: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 80010de: 613b str r3, [r7, #16] + 80010e0: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); - 80010aa: 4b1a ldr r3, [pc, #104] @ (8001114 ) - 80010ac: 695b ldr r3, [r3, #20] - 80010ae: 4a19 ldr r2, [pc, #100] @ (8001114 ) - 80010b0: f443 3300 orr.w r3, r3, #131072 @ 0x20000 - 80010b4: 6153 str r3, [r2, #20] - 80010b6: 4b17 ldr r3, [pc, #92] @ (8001114 ) - 80010b8: 695b ldr r3, [r3, #20] - 80010ba: f403 3300 and.w r3, r3, #131072 @ 0x20000 - 80010be: 60fb str r3, [r7, #12] - 80010c0: 68fb ldr r3, [r7, #12] + 80010e2: 4b1a ldr r3, [pc, #104] @ (800114c ) + 80010e4: 695b ldr r3, [r3, #20] + 80010e6: 4a19 ldr r2, [pc, #100] @ (800114c ) + 80010e8: f443 3300 orr.w r3, r3, #131072 @ 0x20000 + 80010ec: 6153 str r3, [r2, #20] + 80010ee: 4b17 ldr r3, [pc, #92] @ (800114c ) + 80010f0: 695b ldr r3, [r3, #20] + 80010f2: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 80010f6: 60fb str r3, [r7, #12] + 80010f8: 68fb ldr r3, [r7, #12] /**CAN GPIO Configuration PA11 ------> CAN_RX PA12 ------> CAN_TX */ GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12; - 80010c2: f44f 53c0 mov.w r3, #6144 @ 0x1800 - 80010c6: 617b str r3, [r7, #20] + 80010fa: f44f 53c0 mov.w r3, #6144 @ 0x1800 + 80010fe: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - 80010c8: 2302 movs r3, #2 - 80010ca: 61bb str r3, [r7, #24] + 8001100: 2302 movs r3, #2 + 8001102: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; - 80010cc: 2300 movs r3, #0 - 80010ce: 61fb str r3, [r7, #28] + 8001104: 2300 movs r3, #0 + 8001106: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; - 80010d0: 2303 movs r3, #3 - 80010d2: 623b str r3, [r7, #32] + 8001108: 2303 movs r3, #3 + 800110a: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF9_CAN; - 80010d4: 2309 movs r3, #9 - 80010d6: 627b str r3, [r7, #36] @ 0x24 + 800110c: 2309 movs r3, #9 + 800110e: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - 80010d8: f107 0314 add.w r3, r7, #20 - 80010dc: 4619 mov r1, r3 - 80010de: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 - 80010e2: f002 f9fd bl 80034e0 + 8001110: f107 0314 add.w r3, r7, #20 + 8001114: 4619 mov r1, r3 + 8001116: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 + 800111a: f002 f9fd bl 8003518 /* CAN interrupt Init */ HAL_NVIC_SetPriority(USB_LP_CAN_RX0_IRQn, 0, 0); - 80010e6: 2200 movs r2, #0 - 80010e8: 2100 movs r1, #0 - 80010ea: 2014 movs r0, #20 - 80010ec: f002 f89b bl 8003226 + 800111e: 2200 movs r2, #0 + 8001120: 2100 movs r1, #0 + 8001122: 2014 movs r0, #20 + 8001124: f002 f89b bl 800325e HAL_NVIC_EnableIRQ(USB_LP_CAN_RX0_IRQn); - 80010f0: 2014 movs r0, #20 - 80010f2: f002 f8b4 bl 800325e + 8001128: 2014 movs r0, #20 + 800112a: f002 f8b4 bl 8003296 HAL_NVIC_SetPriority(CAN_RX1_IRQn, 0, 0); - 80010f6: 2200 movs r2, #0 - 80010f8: 2100 movs r1, #0 - 80010fa: 2015 movs r0, #21 - 80010fc: f002 f893 bl 8003226 + 800112e: 2200 movs r2, #0 + 8001130: 2100 movs r1, #0 + 8001132: 2015 movs r0, #21 + 8001134: f002 f893 bl 800325e HAL_NVIC_EnableIRQ(CAN_RX1_IRQn); - 8001100: 2015 movs r0, #21 - 8001102: f002 f8ac bl 800325e + 8001138: 2015 movs r0, #21 + 800113a: f002 f8ac bl 8003296 /* USER CODE BEGIN CAN_MspInit 1 */ /* USER CODE END CAN_MspInit 1 */ } } - 8001106: bf00 nop - 8001108: 3728 adds r7, #40 @ 0x28 - 800110a: 46bd mov sp, r7 - 800110c: bd80 pop {r7, pc} - 800110e: bf00 nop - 8001110: 40006400 .word 0x40006400 - 8001114: 40021000 .word 0x40021000 + 800113e: bf00 nop + 8001140: 3728 adds r7, #40 @ 0x28 + 8001142: 46bd mov sp, r7 + 8001144: bd80 pop {r7, pc} + 8001146: bf00 nop + 8001148: 40006400 .word 0x40006400 + 800114c: 40021000 .word 0x40021000 -08001118 : +08001150 : * This function configures the hardware resources used in this example * @param htim_base: TIM_Base handle pointer * @retval None */ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) { - 8001118: b580 push {r7, lr} - 800111a: b084 sub sp, #16 - 800111c: af00 add r7, sp, #0 - 800111e: 6078 str r0, [r7, #4] + 8001150: b580 push {r7, lr} + 8001152: b084 sub sp, #16 + 8001154: af00 add r7, sp, #0 + 8001156: 6078 str r0, [r7, #4] if(htim_base->Instance==TIM6) - 8001120: 687b ldr r3, [r7, #4] - 8001122: 681b ldr r3, [r3, #0] - 8001124: 4a0d ldr r2, [pc, #52] @ (800115c ) - 8001126: 4293 cmp r3, r2 - 8001128: d113 bne.n 8001152 + 8001158: 687b ldr r3, [r7, #4] + 800115a: 681b ldr r3, [r3, #0] + 800115c: 4a0d ldr r2, [pc, #52] @ (8001194 ) + 800115e: 4293 cmp r3, r2 + 8001160: d113 bne.n 800118a { /* USER CODE BEGIN TIM6_MspInit 0 */ /* USER CODE END TIM6_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_TIM6_CLK_ENABLE(); - 800112a: 4b0d ldr r3, [pc, #52] @ (8001160 ) - 800112c: 69db ldr r3, [r3, #28] - 800112e: 4a0c ldr r2, [pc, #48] @ (8001160 ) - 8001130: f043 0310 orr.w r3, r3, #16 - 8001134: 61d3 str r3, [r2, #28] - 8001136: 4b0a ldr r3, [pc, #40] @ (8001160 ) - 8001138: 69db ldr r3, [r3, #28] - 800113a: f003 0310 and.w r3, r3, #16 - 800113e: 60fb str r3, [r7, #12] - 8001140: 68fb ldr r3, [r7, #12] + 8001162: 4b0d ldr r3, [pc, #52] @ (8001198 ) + 8001164: 69db ldr r3, [r3, #28] + 8001166: 4a0c ldr r2, [pc, #48] @ (8001198 ) + 8001168: f043 0310 orr.w r3, r3, #16 + 800116c: 61d3 str r3, [r2, #28] + 800116e: 4b0a ldr r3, [pc, #40] @ (8001198 ) + 8001170: 69db ldr r3, [r3, #28] + 8001172: f003 0310 and.w r3, r3, #16 + 8001176: 60fb str r3, [r7, #12] + 8001178: 68fb ldr r3, [r7, #12] /* TIM6 interrupt Init */ HAL_NVIC_SetPriority(TIM6_DAC_IRQn, 0, 0); - 8001142: 2200 movs r2, #0 - 8001144: 2100 movs r1, #0 - 8001146: 2036 movs r0, #54 @ 0x36 - 8001148: f002 f86d bl 8003226 + 800117a: 2200 movs r2, #0 + 800117c: 2100 movs r1, #0 + 800117e: 2036 movs r0, #54 @ 0x36 + 8001180: f002 f86d bl 800325e HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn); - 800114c: 2036 movs r0, #54 @ 0x36 - 800114e: f002 f886 bl 800325e + 8001184: 2036 movs r0, #54 @ 0x36 + 8001186: f002 f886 bl 8003296 /* USER CODE BEGIN TIM6_MspInit 1 */ /* USER CODE END TIM6_MspInit 1 */ } } - 8001152: bf00 nop - 8001154: 3710 adds r7, #16 - 8001156: 46bd mov sp, r7 - 8001158: bd80 pop {r7, pc} - 800115a: bf00 nop - 800115c: 40001000 .word 0x40001000 - 8001160: 40021000 .word 0x40021000 + 800118a: bf00 nop + 800118c: 3710 adds r7, #16 + 800118e: 46bd mov sp, r7 + 8001190: bd80 pop {r7, pc} + 8001192: bf00 nop + 8001194: 40001000 .word 0x40001000 + 8001198: 40021000 .word 0x40021000 -08001164 : +0800119c : * This function configures the hardware resources used in this example * @param huart: UART handle pointer * @retval None */ void HAL_UART_MspInit(UART_HandleTypeDef* huart) { - 8001164: b580 push {r7, lr} - 8001166: b08a sub sp, #40 @ 0x28 - 8001168: af00 add r7, sp, #0 - 800116a: 6078 str r0, [r7, #4] + 800119c: b580 push {r7, lr} + 800119e: b08a sub sp, #40 @ 0x28 + 80011a0: af00 add r7, sp, #0 + 80011a2: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; - 800116c: f107 0314 add.w r3, r7, #20 - 8001170: 2200 movs r2, #0 - 8001172: 601a str r2, [r3, #0] - 8001174: 605a str r2, [r3, #4] - 8001176: 609a str r2, [r3, #8] - 8001178: 60da str r2, [r3, #12] - 800117a: 611a str r2, [r3, #16] + 80011a4: f107 0314 add.w r3, r7, #20 + 80011a8: 2200 movs r2, #0 + 80011aa: 601a str r2, [r3, #0] + 80011ac: 605a str r2, [r3, #4] + 80011ae: 609a str r2, [r3, #8] + 80011b0: 60da str r2, [r3, #12] + 80011b2: 611a str r2, [r3, #16] if(huart->Instance==UART4) - 800117c: 687b ldr r3, [r7, #4] - 800117e: 681b ldr r3, [r3, #0] - 8001180: 4a17 ldr r2, [pc, #92] @ (80011e0 ) - 8001182: 4293 cmp r3, r2 - 8001184: d128 bne.n 80011d8 + 80011b4: 687b ldr r3, [r7, #4] + 80011b6: 681b ldr r3, [r3, #0] + 80011b8: 4a17 ldr r2, [pc, #92] @ (8001218 ) + 80011ba: 4293 cmp r3, r2 + 80011bc: d128 bne.n 8001210 { /* USER CODE BEGIN UART4_MspInit 0 */ /* USER CODE END UART4_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_UART4_CLK_ENABLE(); - 8001186: 4b17 ldr r3, [pc, #92] @ (80011e4 ) - 8001188: 69db ldr r3, [r3, #28] - 800118a: 4a16 ldr r2, [pc, #88] @ (80011e4 ) - 800118c: f443 2300 orr.w r3, r3, #524288 @ 0x80000 - 8001190: 61d3 str r3, [r2, #28] - 8001192: 4b14 ldr r3, [pc, #80] @ (80011e4 ) - 8001194: 69db ldr r3, [r3, #28] - 8001196: f403 2300 and.w r3, r3, #524288 @ 0x80000 - 800119a: 613b str r3, [r7, #16] - 800119c: 693b ldr r3, [r7, #16] + 80011be: 4b17 ldr r3, [pc, #92] @ (800121c ) + 80011c0: 69db ldr r3, [r3, #28] + 80011c2: 4a16 ldr r2, [pc, #88] @ (800121c ) + 80011c4: f443 2300 orr.w r3, r3, #524288 @ 0x80000 + 80011c8: 61d3 str r3, [r2, #28] + 80011ca: 4b14 ldr r3, [pc, #80] @ (800121c ) + 80011cc: 69db ldr r3, [r3, #28] + 80011ce: f403 2300 and.w r3, r3, #524288 @ 0x80000 + 80011d2: 613b str r3, [r7, #16] + 80011d4: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOC_CLK_ENABLE(); - 800119e: 4b11 ldr r3, [pc, #68] @ (80011e4 ) - 80011a0: 695b ldr r3, [r3, #20] - 80011a2: 4a10 ldr r2, [pc, #64] @ (80011e4 ) - 80011a4: f443 2300 orr.w r3, r3, #524288 @ 0x80000 - 80011a8: 6153 str r3, [r2, #20] - 80011aa: 4b0e ldr r3, [pc, #56] @ (80011e4 ) - 80011ac: 695b ldr r3, [r3, #20] - 80011ae: f403 2300 and.w r3, r3, #524288 @ 0x80000 - 80011b2: 60fb str r3, [r7, #12] - 80011b4: 68fb ldr r3, [r7, #12] + 80011d6: 4b11 ldr r3, [pc, #68] @ (800121c ) + 80011d8: 695b ldr r3, [r3, #20] + 80011da: 4a10 ldr r2, [pc, #64] @ (800121c ) + 80011dc: f443 2300 orr.w r3, r3, #524288 @ 0x80000 + 80011e0: 6153 str r3, [r2, #20] + 80011e2: 4b0e ldr r3, [pc, #56] @ (800121c ) + 80011e4: 695b ldr r3, [r3, #20] + 80011e6: f403 2300 and.w r3, r3, #524288 @ 0x80000 + 80011ea: 60fb str r3, [r7, #12] + 80011ec: 68fb ldr r3, [r7, #12] /**UART4 GPIO Configuration PC10 ------> UART4_TX PC11 ------> UART4_RX */ GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11; - 80011b6: f44f 6340 mov.w r3, #3072 @ 0xc00 - 80011ba: 617b str r3, [r7, #20] + 80011ee: f44f 6340 mov.w r3, #3072 @ 0xc00 + 80011f2: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - 80011bc: 2302 movs r3, #2 - 80011be: 61bb str r3, [r7, #24] + 80011f4: 2302 movs r3, #2 + 80011f6: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; - 80011c0: 2300 movs r3, #0 - 80011c2: 61fb str r3, [r7, #28] + 80011f8: 2300 movs r3, #0 + 80011fa: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; - 80011c4: 2303 movs r3, #3 - 80011c6: 623b str r3, [r7, #32] + 80011fc: 2303 movs r3, #3 + 80011fe: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF5_UART4; - 80011c8: 2305 movs r3, #5 - 80011ca: 627b str r3, [r7, #36] @ 0x24 + 8001200: 2305 movs r3, #5 + 8001202: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); - 80011cc: f107 0314 add.w r3, r7, #20 - 80011d0: 4619 mov r1, r3 - 80011d2: 4805 ldr r0, [pc, #20] @ (80011e8 ) - 80011d4: f002 f984 bl 80034e0 + 8001204: f107 0314 add.w r3, r7, #20 + 8001208: 4619 mov r1, r3 + 800120a: 4805 ldr r0, [pc, #20] @ (8001220 ) + 800120c: f002 f984 bl 8003518 /* USER CODE BEGIN UART4_MspInit 1 */ /* USER CODE END UART4_MspInit 1 */ } } - 80011d8: bf00 nop - 80011da: 3728 adds r7, #40 @ 0x28 - 80011dc: 46bd mov sp, r7 - 80011de: bd80 pop {r7, pc} - 80011e0: 40004c00 .word 0x40004c00 - 80011e4: 40021000 .word 0x40021000 - 80011e8: 48000800 .word 0x48000800 + 8001210: bf00 nop + 8001212: 3728 adds r7, #40 @ 0x28 + 8001214: 46bd mov sp, r7 + 8001216: bd80 pop {r7, pc} + 8001218: 40004c00 .word 0x40004c00 + 800121c: 40021000 .word 0x40021000 + 8001220: 48000800 .word 0x48000800 -080011ec : +08001224 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { - 80011ec: b480 push {r7} - 80011ee: af00 add r7, sp, #0 + 8001224: b480 push {r7} + 8001226: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) - 80011f0: bf00 nop - 80011f2: e7fd b.n 80011f0 + 8001228: bf00 nop + 800122a: e7fd b.n 8001228 -080011f4 : +0800122c : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { - 80011f4: b480 push {r7} - 80011f6: af00 add r7, sp, #0 + 800122c: b480 push {r7} + 800122e: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) - 80011f8: bf00 nop - 80011fa: e7fd b.n 80011f8 + 8001230: bf00 nop + 8001232: e7fd b.n 8001230 -080011fc : +08001234 : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { - 80011fc: b480 push {r7} - 80011fe: af00 add r7, sp, #0 + 8001234: b480 push {r7} + 8001236: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) - 8001200: bf00 nop - 8001202: e7fd b.n 8001200 + 8001238: bf00 nop + 800123a: e7fd b.n 8001238 -08001204 : +0800123c : /** * @brief This function handles Pre-fetch fault, memory access fault. */ void BusFault_Handler(void) { - 8001204: b480 push {r7} - 8001206: af00 add r7, sp, #0 + 800123c: b480 push {r7} + 800123e: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) - 8001208: bf00 nop - 800120a: e7fd b.n 8001208 + 8001240: bf00 nop + 8001242: e7fd b.n 8001240 -0800120c : +08001244 : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { - 800120c: b480 push {r7} - 800120e: af00 add r7, sp, #0 + 8001244: b480 push {r7} + 8001246: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) - 8001210: bf00 nop - 8001212: e7fd b.n 8001210 + 8001248: bf00 nop + 800124a: e7fd b.n 8001248 -08001214 : +0800124c : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { - 8001214: b480 push {r7} - 8001216: af00 add r7, sp, #0 + 800124c: b480 push {r7} + 800124e: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } - 8001218: bf00 nop - 800121a: 46bd mov sp, r7 - 800121c: f85d 7b04 ldr.w r7, [sp], #4 - 8001220: 4770 bx lr + 8001250: bf00 nop + 8001252: 46bd mov sp, r7 + 8001254: f85d 7b04 ldr.w r7, [sp], #4 + 8001258: 4770 bx lr -08001222 : +0800125a : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { - 8001222: b480 push {r7} - 8001224: af00 add r7, sp, #0 + 800125a: b480 push {r7} + 800125c: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } - 8001226: bf00 nop - 8001228: 46bd mov sp, r7 - 800122a: f85d 7b04 ldr.w r7, [sp], #4 - 800122e: 4770 bx lr + 800125e: bf00 nop + 8001260: 46bd mov sp, r7 + 8001262: f85d 7b04 ldr.w r7, [sp], #4 + 8001266: 4770 bx lr -08001230 : +08001268 : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { - 8001230: b480 push {r7} - 8001232: af00 add r7, sp, #0 + 8001268: b480 push {r7} + 800126a: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } - 8001234: bf00 nop - 8001236: 46bd mov sp, r7 - 8001238: f85d 7b04 ldr.w r7, [sp], #4 - 800123c: 4770 bx lr + 800126c: bf00 nop + 800126e: 46bd mov sp, r7 + 8001270: f85d 7b04 ldr.w r7, [sp], #4 + 8001274: 4770 bx lr -0800123e : +08001276 : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { - 800123e: b580 push {r7, lr} - 8001240: af00 add r7, sp, #0 + 8001276: b580 push {r7, lr} + 8001278: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); - 8001242: f000 f8c5 bl 80013d0 + 800127a: f000 f8c5 bl 8001408 /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } - 8001246: bf00 nop - 8001248: bd80 pop {r7, pc} + 800127e: bf00 nop + 8001280: bd80 pop {r7, pc} ... -0800124c : +08001284 : /** * @brief This function handles DMA1 channel1 global interrupt. */ void DMA1_Channel1_IRQHandler(void) { - 800124c: b580 push {r7, lr} - 800124e: af00 add r7, sp, #0 + 8001284: b580 push {r7, lr} + 8001286: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Channel1_IRQn 0 */ /* USER CODE END DMA1_Channel1_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_adc1); - 8001250: 4802 ldr r0, [pc, #8] @ (800125c ) - 8001252: f002 f865 bl 8003320 + 8001288: 4802 ldr r0, [pc, #8] @ (8001294 ) + 800128a: f002 f865 bl 8003358 /* USER CODE BEGIN DMA1_Channel1_IRQn 1 */ /* USER CODE END DMA1_Channel1_IRQn 1 */ } - 8001256: bf00 nop - 8001258: bd80 pop {r7, pc} - 800125a: bf00 nop - 800125c: 2000011c .word 0x2000011c + 800128e: bf00 nop + 8001290: bd80 pop {r7, pc} + 8001292: bf00 nop + 8001294: 2000011c .word 0x2000011c -08001260 : +08001298 : /** * @brief This function handles ADC1 and ADC2 interrupts. */ void ADC1_2_IRQHandler(void) { - 8001260: b580 push {r7, lr} - 8001262: af00 add r7, sp, #0 + 8001298: b580 push {r7, lr} + 800129a: af00 add r7, sp, #0 /* USER CODE BEGIN ADC1_2_IRQn 0 */ /* USER CODE END ADC1_2_IRQn 0 */ HAL_ADC_IRQHandler(&hadc1); - 8001264: 4803 ldr r0, [pc, #12] @ (8001274 ) - 8001266: f000 faa7 bl 80017b8 + 800129c: 4803 ldr r0, [pc, #12] @ (80012ac ) + 800129e: f000 faa7 bl 80017f0 HAL_ADC_IRQHandler(&hadc2); - 800126a: 4803 ldr r0, [pc, #12] @ (8001278 ) - 800126c: f000 faa4 bl 80017b8 + 80012a2: 4803 ldr r0, [pc, #12] @ (80012b0 ) + 80012a4: f000 faa4 bl 80017f0 /* USER CODE BEGIN ADC1_2_IRQn 1 */ /* USER CODE END ADC1_2_IRQn 1 */ } - 8001270: bf00 nop - 8001272: bd80 pop {r7, pc} - 8001274: 2000007c .word 0x2000007c - 8001278: 200000cc .word 0x200000cc + 80012a8: bf00 nop + 80012aa: bd80 pop {r7, pc} + 80012ac: 2000007c .word 0x2000007c + 80012b0: 200000cc .word 0x200000cc -0800127c : +080012b4 : /** * @brief This function handles USB low priority or CAN_RX0 interrupts. */ void USB_LP_CAN_RX0_IRQHandler(void) { - 800127c: b580 push {r7, lr} - 800127e: af00 add r7, sp, #0 + 80012b4: b580 push {r7, lr} + 80012b6: af00 add r7, sp, #0 /* USER CODE BEGIN USB_LP_CAN_RX0_IRQn 0 */ /* USER CODE END USB_LP_CAN_RX0_IRQn 0 */ HAL_CAN_IRQHandler(&hcan); - 8001280: 4802 ldr r0, [pc, #8] @ (800128c ) - 8001282: f001 fcc6 bl 8002c12 + 80012b8: 4802 ldr r0, [pc, #8] @ (80012c4 ) + 80012ba: f001 fcc6 bl 8002c4a /* USER CODE BEGIN USB_LP_CAN_RX0_IRQn 1 */ /* USER CODE END USB_LP_CAN_RX0_IRQn 1 */ } - 8001286: bf00 nop - 8001288: bd80 pop {r7, pc} - 800128a: bf00 nop - 800128c: 200001a4 .word 0x200001a4 + 80012be: bf00 nop + 80012c0: bd80 pop {r7, pc} + 80012c2: bf00 nop + 80012c4: 200001a4 .word 0x200001a4 -08001290 : +080012c8 : /** * @brief This function handles CAN RX1 interrupt. */ void CAN_RX1_IRQHandler(void) { - 8001290: b580 push {r7, lr} - 8001292: af00 add r7, sp, #0 + 80012c8: b580 push {r7, lr} + 80012ca: af00 add r7, sp, #0 /* USER CODE BEGIN CAN_RX1_IRQn 0 */ /* USER CODE END CAN_RX1_IRQn 0 */ HAL_CAN_IRQHandler(&hcan); - 8001294: 4802 ldr r0, [pc, #8] @ (80012a0 ) - 8001296: f001 fcbc bl 8002c12 + 80012cc: 4802 ldr r0, [pc, #8] @ (80012d8 ) + 80012ce: f001 fcbc bl 8002c4a /* USER CODE BEGIN CAN_RX1_IRQn 1 */ /* USER CODE END CAN_RX1_IRQn 1 */ } - 800129a: bf00 nop - 800129c: bd80 pop {r7, pc} - 800129e: bf00 nop - 80012a0: 200001a4 .word 0x200001a4 + 80012d2: bf00 nop + 80012d4: bd80 pop {r7, pc} + 80012d6: bf00 nop + 80012d8: 200001a4 .word 0x200001a4 -080012a4 : +080012dc : /** * @brief This function handles Timer 6 interrupt and DAC underrun interrupts. */ void TIM6_DAC_IRQHandler(void) { - 80012a4: b580 push {r7, lr} - 80012a6: af00 add r7, sp, #0 + 80012dc: b580 push {r7, lr} + 80012de: af00 add r7, sp, #0 /* USER CODE BEGIN TIM6_DAC_IRQn 0 */ /* USER CODE END TIM6_DAC_IRQn 0 */ HAL_TIM_IRQHandler(&htim6); - 80012a8: 4802 ldr r0, [pc, #8] @ (80012b4 ) - 80012aa: f003 ff0a bl 80050c2 + 80012e0: 4802 ldr r0, [pc, #8] @ (80012ec ) + 80012e2: f003 ff0a bl 80050fa /* USER CODE BEGIN TIM6_DAC_IRQn 1 */ /* USER CODE END TIM6_DAC_IRQn 1 */ } - 80012ae: bf00 nop - 80012b0: bd80 pop {r7, pc} - 80012b2: bf00 nop - 80012b4: 200001cc .word 0x200001cc + 80012e6: bf00 nop + 80012e8: bd80 pop {r7, pc} + 80012ea: bf00 nop + 80012ec: 200001cc .word 0x200001cc -080012b8 : +080012f0 : /** * @brief This function handles DMA2 channel1 global interrupt. */ void DMA2_Channel1_IRQHandler(void) { - 80012b8: b580 push {r7, lr} - 80012ba: af00 add r7, sp, #0 + 80012f0: b580 push {r7, lr} + 80012f2: af00 add r7, sp, #0 /* USER CODE BEGIN DMA2_Channel1_IRQn 0 */ /* USER CODE END DMA2_Channel1_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_adc2); - 80012bc: 4802 ldr r0, [pc, #8] @ (80012c8 ) - 80012be: f002 f82f bl 8003320 + 80012f4: 4802 ldr r0, [pc, #8] @ (8001300 ) + 80012f6: f002 f82f bl 8003358 /* USER CODE BEGIN DMA2_Channel1_IRQn 1 */ /* USER CODE END DMA2_Channel1_IRQn 1 */ } - 80012c2: bf00 nop - 80012c4: bd80 pop {r7, pc} - 80012c6: bf00 nop - 80012c8: 20000160 .word 0x20000160 + 80012fa: bf00 nop + 80012fc: bd80 pop {r7, pc} + 80012fe: bf00 nop + 8001300: 20000160 .word 0x20000160 -080012cc : +08001304 : * @brief Setup the microcontroller system * @param None * @retval None */ void SystemInit(void) { - 80012cc: b480 push {r7} - 80012ce: af00 add r7, sp, #0 + 8001304: b480 push {r7} + 8001306: af00 add r7, sp, #0 /* FPU settings --------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ - 80012d0: 4b06 ldr r3, [pc, #24] @ (80012ec ) - 80012d2: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 - 80012d6: 4a05 ldr r2, [pc, #20] @ (80012ec ) - 80012d8: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000 - 80012dc: f8c2 3088 str.w r3, [r2, #136] @ 0x88 + 8001308: 4b06 ldr r3, [pc, #24] @ (8001324 ) + 800130a: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 + 800130e: 4a05 ldr r2, [pc, #20] @ (8001324 ) + 8001310: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000 + 8001314: f8c2 3088 str.w r3, [r2, #136] @ 0x88 /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ #endif /* USER_VECT_TAB_ADDRESS */ } - 80012e0: bf00 nop - 80012e2: 46bd mov sp, r7 - 80012e4: f85d 7b04 ldr.w r7, [sp], #4 - 80012e8: 4770 bx lr - 80012ea: bf00 nop - 80012ec: e000ed00 .word 0xe000ed00 + 8001318: bf00 nop + 800131a: 46bd mov sp, r7 + 800131c: f85d 7b04 ldr.w r7, [sp], #4 + 8001320: 4770 bx lr + 8001322: bf00 nop + 8001324: e000ed00 .word 0xe000ed00 -080012f0 : +08001328 : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr sp, =_estack /* Atollic update: set stack pointer */ - 80012f0: f8df d034 ldr.w sp, [pc, #52] @ 8001328 + 8001328: f8df d034 ldr.w sp, [pc, #52] @ 8001360 /* Call the clock system initialization function.*/ bl SystemInit - 80012f4: f7ff ffea bl 80012cc + 800132c: f7ff ffea bl 8001304 /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata - 80012f8: 480c ldr r0, [pc, #48] @ (800132c ) + 8001330: 480c ldr r0, [pc, #48] @ (8001364 ) ldr r1, =_edata - 80012fa: 490d ldr r1, [pc, #52] @ (8001330 ) + 8001332: 490d ldr r1, [pc, #52] @ (8001368 ) ldr r2, =_sidata - 80012fc: 4a0d ldr r2, [pc, #52] @ (8001334 ) + 8001334: 4a0d ldr r2, [pc, #52] @ (800136c ) movs r3, #0 - 80012fe: 2300 movs r3, #0 + 8001336: 2300 movs r3, #0 b LoopCopyDataInit - 8001300: e002 b.n 8001308 + 8001338: e002 b.n 8001340 -08001302 : +0800133a : CopyDataInit: ldr r4, [r2, r3] - 8001302: 58d4 ldr r4, [r2, r3] + 800133a: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] - 8001304: 50c4 str r4, [r0, r3] + 800133c: 50c4 str r4, [r0, r3] adds r3, r3, #4 - 8001306: 3304 adds r3, #4 + 800133e: 3304 adds r3, #4 -08001308 : +08001340 : LoopCopyDataInit: adds r4, r0, r3 - 8001308: 18c4 adds r4, r0, r3 + 8001340: 18c4 adds r4, r0, r3 cmp r4, r1 - 800130a: 428c cmp r4, r1 + 8001342: 428c cmp r4, r1 bcc CopyDataInit - 800130c: d3f9 bcc.n 8001302 + 8001344: d3f9 bcc.n 800133a /* Zero fill the bss segment. */ ldr r2, =_sbss - 800130e: 4a0a ldr r2, [pc, #40] @ (8001338 ) + 8001346: 4a0a ldr r2, [pc, #40] @ (8001370 ) ldr r4, =_ebss - 8001310: 4c0a ldr r4, [pc, #40] @ (800133c ) + 8001348: 4c0a ldr r4, [pc, #40] @ (8001374 ) movs r3, #0 - 8001312: 2300 movs r3, #0 + 800134a: 2300 movs r3, #0 b LoopFillZerobss - 8001314: e001 b.n 800131a + 800134c: e001 b.n 8001352 -08001316 : +0800134e : FillZerobss: str r3, [r2] - 8001316: 6013 str r3, [r2, #0] + 800134e: 6013 str r3, [r2, #0] adds r2, r2, #4 - 8001318: 3204 adds r2, #4 + 8001350: 3204 adds r2, #4 -0800131a : +08001352 : LoopFillZerobss: cmp r2, r4 - 800131a: 42a2 cmp r2, r4 + 8001352: 42a2 cmp r2, r4 bcc FillZerobss - 800131c: d3fb bcc.n 8001316 + 8001354: d3fb bcc.n 800134e /* Call static constructors */ bl __libc_init_array - 800131e: f004 fd75 bl 8005e0c <__libc_init_array> + 8001356: f004 fd75 bl 8005e44 <__libc_init_array> /* Call the application's entry point.*/ bl main - 8001322: f7ff f973 bl 800060c
+ 800135a: f7ff f957 bl 800060c
-08001326 : +0800135e : LoopForever: b LoopForever - 8001326: e7fe b.n 8001326 + 800135e: e7fe b.n 800135e ldr sp, =_estack /* Atollic update: set stack pointer */ - 8001328: 20008000 .word 0x20008000 + 8001360: 20008000 .word 0x20008000 ldr r0, =_sdata - 800132c: 20000000 .word 0x20000000 + 8001364: 20000000 .word 0x20000000 ldr r1, =_edata - 8001330: 2000000c .word 0x2000000c + 8001368: 2000000c .word 0x2000000c ldr r2, =_sidata - 8001334: 08005eac .word 0x08005eac + 800136c: 08005ee4 .word 0x08005ee4 ldr r2, =_sbss - 8001338: 2000000c .word 0x2000000c + 8001370: 2000000c .word 0x2000000c ldr r4, =_ebss - 800133c: 200002b8 .word 0x200002b8 + 8001374: 200002b8 .word 0x200002b8 -08001340 : +08001378 : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop - 8001340: e7fe b.n 8001340 + 8001378: e7fe b.n 8001378 ... -08001344 : +0800137c : * In the default implementation,Systick is used as source of time base. * The tick variable is incremented each 1ms in its ISR. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { - 8001344: b580 push {r7, lr} - 8001346: af00 add r7, sp, #0 + 800137c: b580 push {r7, lr} + 800137e: af00 add r7, sp, #0 /* Configure Flash prefetch */ #if (PREFETCH_ENABLE != 0U) __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); - 8001348: 4b08 ldr r3, [pc, #32] @ (800136c ) - 800134a: 681b ldr r3, [r3, #0] - 800134c: 4a07 ldr r2, [pc, #28] @ (800136c ) - 800134e: f043 0310 orr.w r3, r3, #16 - 8001352: 6013 str r3, [r2, #0] + 8001380: 4b08 ldr r3, [pc, #32] @ (80013a4 ) + 8001382: 681b ldr r3, [r3, #0] + 8001384: 4a07 ldr r2, [pc, #28] @ (80013a4 ) + 8001386: f043 0310 orr.w r3, r3, #16 + 800138a: 6013 str r3, [r2, #0] #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); - 8001354: 2003 movs r0, #3 - 8001356: f001 ff5b bl 8003210 + 800138c: 2003 movs r0, #3 + 800138e: f001 ff5b bl 8003248 /* Enable systick and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); - 800135a: 200f movs r0, #15 - 800135c: f000 f808 bl 8001370 + 8001392: 200f movs r0, #15 + 8001394: f000 f808 bl 80013a8 /* Init the low level hardware */ HAL_MspInit(); - 8001360: f7ff fd30 bl 8000dc4 + 8001398: f7ff fd30 bl 8000dfc /* Return function status */ return HAL_OK; - 8001364: 2300 movs r3, #0 + 800139c: 2300 movs r3, #0 } - 8001366: 4618 mov r0, r3 - 8001368: bd80 pop {r7, pc} - 800136a: bf00 nop - 800136c: 40022000 .word 0x40022000 + 800139e: 4618 mov r0, r3 + 80013a0: bd80 pop {r7, pc} + 80013a2: bf00 nop + 80013a4: 40022000 .word 0x40022000 -08001370 : +080013a8 : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { - 8001370: b580 push {r7, lr} - 8001372: b082 sub sp, #8 - 8001374: af00 add r7, sp, #0 - 8001376: 6078 str r0, [r7, #4] + 80013a8: b580 push {r7, lr} + 80013aa: b082 sub sp, #8 + 80013ac: af00 add r7, sp, #0 + 80013ae: 6078 str r0, [r7, #4] /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) - 8001378: 4b12 ldr r3, [pc, #72] @ (80013c4 ) - 800137a: 681a ldr r2, [r3, #0] - 800137c: 4b12 ldr r3, [pc, #72] @ (80013c8 ) - 800137e: 781b ldrb r3, [r3, #0] - 8001380: 4619 mov r1, r3 - 8001382: f44f 737a mov.w r3, #1000 @ 0x3e8 - 8001386: fbb3 f3f1 udiv r3, r3, r1 - 800138a: fbb2 f3f3 udiv r3, r2, r3 - 800138e: 4618 mov r0, r3 - 8001390: f001 ff73 bl 800327a - 8001394: 4603 mov r3, r0 - 8001396: 2b00 cmp r3, #0 - 8001398: d001 beq.n 800139e + 80013b0: 4b12 ldr r3, [pc, #72] @ (80013fc ) + 80013b2: 681a ldr r2, [r3, #0] + 80013b4: 4b12 ldr r3, [pc, #72] @ (8001400 ) + 80013b6: 781b ldrb r3, [r3, #0] + 80013b8: 4619 mov r1, r3 + 80013ba: f44f 737a mov.w r3, #1000 @ 0x3e8 + 80013be: fbb3 f3f1 udiv r3, r3, r1 + 80013c2: fbb2 f3f3 udiv r3, r2, r3 + 80013c6: 4618 mov r0, r3 + 80013c8: f001 ff73 bl 80032b2 + 80013cc: 4603 mov r3, r0 + 80013ce: 2b00 cmp r3, #0 + 80013d0: d001 beq.n 80013d6 { return HAL_ERROR; - 800139a: 2301 movs r3, #1 - 800139c: e00e b.n 80013bc + 80013d2: 2301 movs r3, #1 + 80013d4: e00e b.n 80013f4 } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) - 800139e: 687b ldr r3, [r7, #4] - 80013a0: 2b0f cmp r3, #15 - 80013a2: d80a bhi.n 80013ba + 80013d6: 687b ldr r3, [r7, #4] + 80013d8: 2b0f cmp r3, #15 + 80013da: d80a bhi.n 80013f2 { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); - 80013a4: 2200 movs r2, #0 - 80013a6: 6879 ldr r1, [r7, #4] - 80013a8: f04f 30ff mov.w r0, #4294967295 - 80013ac: f001 ff3b bl 8003226 + 80013dc: 2200 movs r2, #0 + 80013de: 6879 ldr r1, [r7, #4] + 80013e0: f04f 30ff mov.w r0, #4294967295 + 80013e4: f001 ff3b bl 800325e uwTickPrio = TickPriority; - 80013b0: 4a06 ldr r2, [pc, #24] @ (80013cc ) - 80013b2: 687b ldr r3, [r7, #4] - 80013b4: 6013 str r3, [r2, #0] + 80013e8: 4a06 ldr r2, [pc, #24] @ (8001404 ) + 80013ea: 687b ldr r3, [r7, #4] + 80013ec: 6013 str r3, [r2, #0] else { return HAL_ERROR; } /* Return function status */ return HAL_OK; - 80013b6: 2300 movs r3, #0 - 80013b8: e000 b.n 80013bc + 80013ee: 2300 movs r3, #0 + 80013f0: e000 b.n 80013f4 return HAL_ERROR; - 80013ba: 2301 movs r3, #1 + 80013f2: 2301 movs r3, #1 } - 80013bc: 4618 mov r0, r3 - 80013be: 3708 adds r7, #8 - 80013c0: 46bd mov sp, r7 - 80013c2: bd80 pop {r7, pc} - 80013c4: 20000000 .word 0x20000000 - 80013c8: 20000008 .word 0x20000008 - 80013cc: 20000004 .word 0x20000004 + 80013f4: 4618 mov r0, r3 + 80013f6: 3708 adds r7, #8 + 80013f8: 46bd mov sp, r7 + 80013fa: bd80 pop {r7, pc} + 80013fc: 20000000 .word 0x20000000 + 8001400: 20000008 .word 0x20000008 + 8001404: 20000004 .word 0x20000004 -080013d0 : +08001408 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { - 80013d0: b480 push {r7} - 80013d2: af00 add r7, sp, #0 + 8001408: b480 push {r7} + 800140a: af00 add r7, sp, #0 uwTick += uwTickFreq; - 80013d4: 4b06 ldr r3, [pc, #24] @ (80013f0 ) - 80013d6: 781b ldrb r3, [r3, #0] - 80013d8: 461a mov r2, r3 - 80013da: 4b06 ldr r3, [pc, #24] @ (80013f4 ) - 80013dc: 681b ldr r3, [r3, #0] - 80013de: 4413 add r3, r2 - 80013e0: 4a04 ldr r2, [pc, #16] @ (80013f4 ) - 80013e2: 6013 str r3, [r2, #0] + 800140c: 4b06 ldr r3, [pc, #24] @ (8001428 ) + 800140e: 781b ldrb r3, [r3, #0] + 8001410: 461a mov r2, r3 + 8001412: 4b06 ldr r3, [pc, #24] @ (800142c ) + 8001414: 681b ldr r3, [r3, #0] + 8001416: 4413 add r3, r2 + 8001418: 4a04 ldr r2, [pc, #16] @ (800142c ) + 800141a: 6013 str r3, [r2, #0] } - 80013e4: bf00 nop - 80013e6: 46bd mov sp, r7 - 80013e8: f85d 7b04 ldr.w r7, [sp], #4 - 80013ec: 4770 bx lr - 80013ee: bf00 nop - 80013f0: 20000008 .word 0x20000008 - 80013f4: 200002b4 .word 0x200002b4 + 800141c: bf00 nop + 800141e: 46bd mov sp, r7 + 8001420: f85d 7b04 ldr.w r7, [sp], #4 + 8001424: 4770 bx lr + 8001426: bf00 nop + 8001428: 20000008 .word 0x20000008 + 800142c: 200002b4 .word 0x200002b4 -080013f8 : +08001430 : * @note The function is declared as __Weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { - 80013f8: b480 push {r7} - 80013fa: af00 add r7, sp, #0 + 8001430: b480 push {r7} + 8001432: af00 add r7, sp, #0 return uwTick; - 80013fc: 4b03 ldr r3, [pc, #12] @ (800140c ) - 80013fe: 681b ldr r3, [r3, #0] + 8001434: 4b03 ldr r3, [pc, #12] @ (8001444 ) + 8001436: 681b ldr r3, [r3, #0] } - 8001400: 4618 mov r0, r3 - 8001402: 46bd mov sp, r7 - 8001404: f85d 7b04 ldr.w r7, [sp], #4 - 8001408: 4770 bx lr - 800140a: bf00 nop - 800140c: 200002b4 .word 0x200002b4 + 8001438: 4618 mov r0, r3 + 800143a: 46bd mov sp, r7 + 800143c: f85d 7b04 ldr.w r7, [sp], #4 + 8001440: 4770 bx lr + 8001442: bf00 nop + 8001444: 200002b4 .word 0x200002b4 -08001410 : +08001448 : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { - 8001410: b580 push {r7, lr} - 8001412: b084 sub sp, #16 - 8001414: af00 add r7, sp, #0 - 8001416: 6078 str r0, [r7, #4] + 8001448: b580 push {r7, lr} + 800144a: b084 sub sp, #16 + 800144c: af00 add r7, sp, #0 + 800144e: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); - 8001418: f7ff ffee bl 80013f8 - 800141c: 60b8 str r0, [r7, #8] + 8001450: f7ff ffee bl 8001430 + 8001454: 60b8 str r0, [r7, #8] uint32_t wait = Delay; - 800141e: 687b ldr r3, [r7, #4] - 8001420: 60fb str r3, [r7, #12] + 8001456: 687b ldr r3, [r7, #4] + 8001458: 60fb str r3, [r7, #12] /* Add freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) - 8001422: 68fb ldr r3, [r7, #12] - 8001424: f1b3 3fff cmp.w r3, #4294967295 - 8001428: d005 beq.n 8001436 + 800145a: 68fb ldr r3, [r7, #12] + 800145c: f1b3 3fff cmp.w r3, #4294967295 + 8001460: d005 beq.n 800146e { wait += (uint32_t)(uwTickFreq); - 800142a: 4b0a ldr r3, [pc, #40] @ (8001454 ) - 800142c: 781b ldrb r3, [r3, #0] - 800142e: 461a mov r2, r3 - 8001430: 68fb ldr r3, [r7, #12] - 8001432: 4413 add r3, r2 - 8001434: 60fb str r3, [r7, #12] + 8001462: 4b0a ldr r3, [pc, #40] @ (800148c ) + 8001464: 781b ldrb r3, [r3, #0] + 8001466: 461a mov r2, r3 + 8001468: 68fb ldr r3, [r7, #12] + 800146a: 4413 add r3, r2 + 800146c: 60fb str r3, [r7, #12] } while((HAL_GetTick() - tickstart) < wait) - 8001436: bf00 nop - 8001438: f7ff ffde bl 80013f8 - 800143c: 4602 mov r2, r0 - 800143e: 68bb ldr r3, [r7, #8] - 8001440: 1ad3 subs r3, r2, r3 - 8001442: 68fa ldr r2, [r7, #12] - 8001444: 429a cmp r2, r3 - 8001446: d8f7 bhi.n 8001438 + 800146e: bf00 nop + 8001470: f7ff ffde bl 8001430 + 8001474: 4602 mov r2, r0 + 8001476: 68bb ldr r3, [r7, #8] + 8001478: 1ad3 subs r3, r2, r3 + 800147a: 68fa ldr r2, [r7, #12] + 800147c: 429a cmp r2, r3 + 800147e: d8f7 bhi.n 8001470 { } } - 8001448: bf00 nop - 800144a: bf00 nop - 800144c: 3710 adds r7, #16 - 800144e: 46bd mov sp, r7 - 8001450: bd80 pop {r7, pc} - 8001452: bf00 nop - 8001454: 20000008 .word 0x20000008 + 8001480: bf00 nop + 8001482: bf00 nop + 8001484: 3710 adds r7, #16 + 8001486: 46bd mov sp, r7 + 8001488: bd80 pop {r7, pc} + 800148a: bf00 nop + 800148c: 20000008 .word 0x20000008 -08001458 : +08001490 : * @brief Conversion complete callback in non blocking mode * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) { - 8001458: b480 push {r7} - 800145a: b083 sub sp, #12 - 800145c: af00 add r7, sp, #0 - 800145e: 6078 str r0, [r7, #4] + 8001490: b480 push {r7} + 8001492: b083 sub sp, #12 + 8001494: af00 add r7, sp, #0 + 8001496: 6078 str r0, [r7, #4] UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ConvCpltCallback must be implemented in the user file. */ } - 8001460: bf00 nop - 8001462: 370c adds r7, #12 - 8001464: 46bd mov sp, r7 - 8001466: f85d 7b04 ldr.w r7, [sp], #4 - 800146a: 4770 bx lr + 8001498: bf00 nop + 800149a: 370c adds r7, #12 + 800149c: 46bd mov sp, r7 + 800149e: f85d 7b04 ldr.w r7, [sp], #4 + 80014a2: 4770 bx lr -0800146c : +080014a4 : * @brief Analog watchdog callback in non blocking mode. * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) { - 800146c: b480 push {r7} - 800146e: b083 sub sp, #12 - 8001470: af00 add r7, sp, #0 - 8001472: 6078 str r0, [r7, #4] + 80014a4: b480 push {r7} + 80014a6: b083 sub sp, #12 + 80014a8: af00 add r7, sp, #0 + 80014aa: 6078 str r0, [r7, #4] UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_LevelOoutOfWindowCallback must be implemented in the user file. */ } - 8001474: bf00 nop - 8001476: 370c adds r7, #12 - 8001478: 46bd mov sp, r7 - 800147a: f85d 7b04 ldr.w r7, [sp], #4 - 800147e: 4770 bx lr + 80014ac: bf00 nop + 80014ae: 370c adds r7, #12 + 80014b0: 46bd mov sp, r7 + 80014b2: f85d 7b04 ldr.w r7, [sp], #4 + 80014b6: 4770 bx lr -08001480 : +080014b8 : * (ADC conversion with interruption or transfer by DMA) * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) { - 8001480: b480 push {r7} - 8001482: b083 sub sp, #12 - 8001484: af00 add r7, sp, #0 - 8001486: 6078 str r0, [r7, #4] + 80014b8: b480 push {r7} + 80014ba: b083 sub sp, #12 + 80014bc: af00 add r7, sp, #0 + 80014be: 6078 str r0, [r7, #4] UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ErrorCallback must be implemented in the user file. */ } - 8001488: bf00 nop - 800148a: 370c adds r7, #12 - 800148c: 46bd mov sp, r7 - 800148e: f85d 7b04 ldr.w r7, [sp], #4 - 8001492: 4770 bx lr + 80014c0: bf00 nop + 80014c2: 370c adds r7, #12 + 80014c4: 46bd mov sp, r7 + 80014c6: f85d 7b04 ldr.w r7, [sp], #4 + 80014ca: 4770 bx lr -08001494 : +080014cc : * without disabling the other ADCs sharing the same common group. * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) { - 8001494: b580 push {r7, lr} - 8001496: b09a sub sp, #104 @ 0x68 - 8001498: af00 add r7, sp, #0 - 800149a: 6078 str r0, [r7, #4] + 80014cc: b580 push {r7, lr} + 80014ce: b09a sub sp, #104 @ 0x68 + 80014d0: af00 add r7, sp, #0 + 80014d2: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; - 800149c: 2300 movs r3, #0 - 800149e: f887 3067 strb.w r3, [r7, #103] @ 0x67 + 80014d4: 2300 movs r3, #0 + 80014d6: f887 3067 strb.w r3, [r7, #103] @ 0x67 ADC_Common_TypeDef *tmpADC_Common; ADC_HandleTypeDef tmphadcSharingSameCommonRegister; uint32_t tmpCFGR = 0U; - 80014a2: 2300 movs r3, #0 - 80014a4: 663b str r3, [r7, #96] @ 0x60 + 80014da: 2300 movs r3, #0 + 80014dc: 663b str r3, [r7, #96] @ 0x60 __IO uint32_t wait_loop_index = 0U; - 80014a6: 2300 movs r3, #0 - 80014a8: 60bb str r3, [r7, #8] + 80014de: 2300 movs r3, #0 + 80014e0: 60bb str r3, [r7, #8] /* Check ADC handle */ if(hadc == NULL) - 80014aa: 687b ldr r3, [r7, #4] - 80014ac: 2b00 cmp r3, #0 - 80014ae: d101 bne.n 80014b4 + 80014e2: 687b ldr r3, [r7, #4] + 80014e4: 2b00 cmp r3, #0 + 80014e6: d101 bne.n 80014ec { return HAL_ERROR; - 80014b0: 2301 movs r3, #1 - 80014b2: e172 b.n 800179a + 80014e8: 2301 movs r3, #1 + 80014ea: e172 b.n 80017d2 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests)); assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait)); if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) - 80014b4: 687b ldr r3, [r7, #4] - 80014b6: 691b ldr r3, [r3, #16] - 80014b8: 2b00 cmp r3, #0 + 80014ec: 687b ldr r3, [r7, #4] + 80014ee: 691b ldr r3, [r3, #16] + 80014f0: 2b00 cmp r3, #0 assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion)); } } /* Configuration of ADC core parameters and ADC MSP related parameters */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) - 80014ba: 687b ldr r3, [r7, #4] - 80014bc: 6c1b ldr r3, [r3, #64] @ 0x40 - 80014be: f003 0310 and.w r3, r3, #16 - 80014c2: 2b00 cmp r3, #0 - 80014c4: d176 bne.n 80015b4 + 80014f2: 687b ldr r3, [r7, #4] + 80014f4: 6c1b ldr r3, [r3, #64] @ 0x40 + 80014f6: f003 0310 and.w r3, r3, #16 + 80014fa: 2b00 cmp r3, #0 + 80014fc: d176 bne.n 80015ec /* procedure. */ /* Actions performed only if ADC is coming from state reset: */ /* - Initialization of ADC MSP */ /* - ADC voltage regulator enable */ if (hadc->State == HAL_ADC_STATE_RESET) - 80014c6: 687b ldr r3, [r7, #4] - 80014c8: 6c1b ldr r3, [r3, #64] @ 0x40 - 80014ca: 2b00 cmp r3, #0 - 80014cc: d152 bne.n 8001574 + 80014fe: 687b ldr r3, [r7, #4] + 8001500: 6c1b ldr r3, [r3, #64] @ 0x40 + 8001502: 2b00 cmp r3, #0 + 8001504: d152 bne.n 80015ac { /* Initialize ADC error code */ ADC_CLEAR_ERRORCODE(hadc); - 80014ce: 687b ldr r3, [r7, #4] - 80014d0: 2200 movs r2, #0 - 80014d2: 645a str r2, [r3, #68] @ 0x44 + 8001506: 687b ldr r3, [r7, #4] + 8001508: 2200 movs r2, #0 + 800150a: 645a str r2, [r3, #68] @ 0x44 /* Initialize HAL ADC API internal variables */ hadc->InjectionConfig.ChannelCount = 0U; - 80014d4: 687b ldr r3, [r7, #4] - 80014d6: 2200 movs r2, #0 - 80014d8: 64da str r2, [r3, #76] @ 0x4c + 800150c: 687b ldr r3, [r7, #4] + 800150e: 2200 movs r2, #0 + 8001510: 64da str r2, [r3, #76] @ 0x4c hadc->InjectionConfig.ContextQueue = 0U; - 80014da: 687b ldr r3, [r7, #4] - 80014dc: 2200 movs r2, #0 - 80014de: 649a str r2, [r3, #72] @ 0x48 + 8001512: 687b ldr r3, [r7, #4] + 8001514: 2200 movs r2, #0 + 8001516: 649a str r2, [r3, #72] @ 0x48 /* Allocate lock resource and initialize it */ hadc->Lock = HAL_UNLOCKED; - 80014e0: 687b ldr r3, [r7, #4] - 80014e2: 2200 movs r2, #0 - 80014e4: f883 203c strb.w r2, [r3, #60] @ 0x3c + 8001518: 687b ldr r3, [r7, #4] + 800151a: 2200 movs r2, #0 + 800151c: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Init the low level hardware */ hadc->MspInitCallback(hadc); #else /* Init the low level hardware */ HAL_ADC_MspInit(hadc); - 80014e8: 6878 ldr r0, [r7, #4] - 80014ea: f7ff fc8f bl 8000e0c + 8001520: 6878 ldr r0, [r7, #4] + 8001522: f7ff fc8f bl 8000e44 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Enable voltage regulator (if disabled at this step) */ if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN_0)) - 80014ee: 687b ldr r3, [r7, #4] - 80014f0: 681b ldr r3, [r3, #0] - 80014f2: 689b ldr r3, [r3, #8] - 80014f4: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 - 80014f8: 2b00 cmp r3, #0 - 80014fa: d13b bne.n 8001574 + 8001526: 687b ldr r3, [r7, #4] + 8001528: 681b ldr r3, [r3, #0] + 800152a: 689b ldr r3, [r3, #8] + 800152c: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 8001530: 2b00 cmp r3, #0 + 8001532: d13b bne.n 80015ac /* enabling the ADC. This temporization must be implemented by */ /* software and is equal to 10 us in the worst case */ /* process/temperature/power supply. */ /* Disable the ADC (if not already disabled) */ tmp_hal_status = ADC_Disable(hadc); - 80014fc: 6878 ldr r0, [r7, #4] - 80014fe: f000 ff01 bl 8002304 - 8001502: 4603 mov r3, r0 - 8001504: f887 3067 strb.w r3, [r7, #103] @ 0x67 + 8001534: 6878 ldr r0, [r7, #4] + 8001536: f000 ff01 bl 800233c + 800153a: 4603 mov r3, r0 + 800153c: f887 3067 strb.w r3, [r7, #103] @ 0x67 /* Check if ADC is effectively disabled */ /* Configuration of ADC parameters if previous preliminary actions */ /* are correctly completed. */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && - 8001508: 687b ldr r3, [r7, #4] - 800150a: 6c1b ldr r3, [r3, #64] @ 0x40 - 800150c: f003 0310 and.w r3, r3, #16 - 8001510: 2b00 cmp r3, #0 - 8001512: d12f bne.n 8001574 - 8001514: f897 3067 ldrb.w r3, [r7, #103] @ 0x67 - 8001518: 2b00 cmp r3, #0 - 800151a: d12b bne.n 8001574 + 8001540: 687b ldr r3, [r7, #4] + 8001542: 6c1b ldr r3, [r3, #64] @ 0x40 + 8001544: f003 0310 and.w r3, r3, #16 + 8001548: 2b00 cmp r3, #0 + 800154a: d12f bne.n 80015ac + 800154c: f897 3067 ldrb.w r3, [r7, #103] @ 0x67 + 8001550: 2b00 cmp r3, #0 + 8001552: d12b bne.n 80015ac (tmp_hal_status == HAL_OK) ) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, - 800151c: 687b ldr r3, [r7, #4] - 800151e: 6c1b ldr r3, [r3, #64] @ 0x40 - 8001520: f423 5388 bic.w r3, r3, #4352 @ 0x1100 - 8001524: f023 0302 bic.w r3, r3, #2 - 8001528: f043 0202 orr.w r2, r3, #2 - 800152c: 687b ldr r3, [r7, #4] - 800152e: 641a str r2, [r3, #64] @ 0x40 + 8001554: 687b ldr r3, [r7, #4] + 8001556: 6c1b ldr r3, [r3, #64] @ 0x40 + 8001558: f423 5388 bic.w r3, r3, #4352 @ 0x1100 + 800155c: f023 0302 bic.w r3, r3, #2 + 8001560: f043 0202 orr.w r2, r3, #2 + 8001564: 687b ldr r3, [r7, #4] + 8001566: 641a str r2, [r3, #64] @ 0x40 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_BUSY_INTERNAL); /* Set the intermediate state before moving the ADC voltage */ /* regulator to state enable. */ CLEAR_BIT(hadc->Instance->CR, (ADC_CR_ADVREGEN_1 | ADC_CR_ADVREGEN_0)); - 8001530: 687b ldr r3, [r7, #4] - 8001532: 681b ldr r3, [r3, #0] - 8001534: 689a ldr r2, [r3, #8] - 8001536: 687b ldr r3, [r7, #4] - 8001538: 681b ldr r3, [r3, #0] - 800153a: f022 5240 bic.w r2, r2, #805306368 @ 0x30000000 - 800153e: 609a str r2, [r3, #8] + 8001568: 687b ldr r3, [r7, #4] + 800156a: 681b ldr r3, [r3, #0] + 800156c: 689a ldr r2, [r3, #8] + 800156e: 687b ldr r3, [r7, #4] + 8001570: 681b ldr r3, [r3, #0] + 8001572: f022 5240 bic.w r2, r2, #805306368 @ 0x30000000 + 8001576: 609a str r2, [r3, #8] /* Set ADVREGEN bits to 0x01U */ SET_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN_0); - 8001540: 687b ldr r3, [r7, #4] - 8001542: 681b ldr r3, [r3, #0] - 8001544: 689a ldr r2, [r3, #8] - 8001546: 687b ldr r3, [r7, #4] - 8001548: 681b ldr r3, [r3, #0] - 800154a: f042 5280 orr.w r2, r2, #268435456 @ 0x10000000 - 800154e: 609a str r2, [r3, #8] + 8001578: 687b ldr r3, [r7, #4] + 800157a: 681b ldr r3, [r3, #0] + 800157c: 689a ldr r2, [r3, #8] + 800157e: 687b ldr r3, [r7, #4] + 8001580: 681b ldr r3, [r3, #0] + 8001582: f042 5280 orr.w r2, r2, #268435456 @ 0x10000000 + 8001586: 609a str r2, [r3, #8] /* Delay for ADC stabilization time. */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); - 8001550: 4b94 ldr r3, [pc, #592] @ (80017a4 ) - 8001552: 681b ldr r3, [r3, #0] - 8001554: 4a94 ldr r2, [pc, #592] @ (80017a8 ) - 8001556: fba2 2303 umull r2, r3, r2, r3 - 800155a: 0c9a lsrs r2, r3, #18 - 800155c: 4613 mov r3, r2 - 800155e: 009b lsls r3, r3, #2 - 8001560: 4413 add r3, r2 - 8001562: 005b lsls r3, r3, #1 - 8001564: 60bb str r3, [r7, #8] + 8001588: 4b94 ldr r3, [pc, #592] @ (80017dc ) + 800158a: 681b ldr r3, [r3, #0] + 800158c: 4a94 ldr r2, [pc, #592] @ (80017e0 ) + 800158e: fba2 2303 umull r2, r3, r2, r3 + 8001592: 0c9a lsrs r2, r3, #18 + 8001594: 4613 mov r3, r2 + 8001596: 009b lsls r3, r3, #2 + 8001598: 4413 add r3, r2 + 800159a: 005b lsls r3, r3, #1 + 800159c: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) - 8001566: e002 b.n 800156e + 800159e: e002 b.n 80015a6 { wait_loop_index--; - 8001568: 68bb ldr r3, [r7, #8] - 800156a: 3b01 subs r3, #1 - 800156c: 60bb str r3, [r7, #8] + 80015a0: 68bb ldr r3, [r7, #8] + 80015a2: 3b01 subs r3, #1 + 80015a4: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) - 800156e: 68bb ldr r3, [r7, #8] - 8001570: 2b00 cmp r3, #0 - 8001572: d1f9 bne.n 8001568 + 80015a6: 68bb ldr r3, [r7, #8] + 80015a8: 2b00 cmp r3, #0 + 80015aa: d1f9 bne.n 80015a0 } /* Verification that ADC voltage regulator is correctly enabled, whether */ /* or not ADC is coming from state reset (if any potential problem of */ /* clocking, voltage regulator would not be enabled). */ if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN_0) || - 8001574: 687b ldr r3, [r7, #4] - 8001576: 681b ldr r3, [r3, #0] - 8001578: 689b ldr r3, [r3, #8] - 800157a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 - 800157e: 2b00 cmp r3, #0 - 8001580: d007 beq.n 8001592 + 80015ac: 687b ldr r3, [r7, #4] + 80015ae: 681b ldr r3, [r3, #0] + 80015b0: 689b ldr r3, [r3, #8] + 80015b2: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 80015b6: 2b00 cmp r3, #0 + 80015b8: d007 beq.n 80015ca HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADVREGEN_1) ) - 8001582: 687b ldr r3, [r7, #4] - 8001584: 681b ldr r3, [r3, #0] - 8001586: 689b ldr r3, [r3, #8] - 8001588: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 + 80015ba: 687b ldr r3, [r7, #4] + 80015bc: 681b ldr r3, [r3, #0] + 80015be: 689b ldr r3, [r3, #8] + 80015c0: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN_0) || - 800158c: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 - 8001590: d110 bne.n 80015b4 + 80015c4: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 + 80015c8: d110 bne.n 80015ec { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, - 8001592: 687b ldr r3, [r7, #4] - 8001594: 6c1b ldr r3, [r3, #64] @ 0x40 - 8001596: f023 0312 bic.w r3, r3, #18 - 800159a: f043 0210 orr.w r2, r3, #16 - 800159e: 687b ldr r3, [r7, #4] - 80015a0: 641a str r2, [r3, #64] @ 0x40 + 80015ca: 687b ldr r3, [r7, #4] + 80015cc: 6c1b ldr r3, [r3, #64] @ 0x40 + 80015ce: f023 0312 bic.w r3, r3, #18 + 80015d2: f043 0210 orr.w r2, r3, #16 + 80015d6: 687b ldr r3, [r7, #4] + 80015d8: 641a str r2, [r3, #64] @ 0x40 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - 80015a2: 687b ldr r3, [r7, #4] - 80015a4: 6c5b ldr r3, [r3, #68] @ 0x44 - 80015a6: f043 0201 orr.w r2, r3, #1 - 80015aa: 687b ldr r3, [r7, #4] - 80015ac: 645a str r2, [r3, #68] @ 0x44 + 80015da: 687b ldr r3, [r7, #4] + 80015dc: 6c5b ldr r3, [r3, #68] @ 0x44 + 80015de: f043 0201 orr.w r2, r3, #1 + 80015e2: 687b ldr r3, [r7, #4] + 80015e4: 645a str r2, [r3, #68] @ 0x44 tmp_hal_status = HAL_ERROR; - 80015ae: 2301 movs r3, #1 - 80015b0: f887 3067 strb.w r3, [r7, #103] @ 0x67 + 80015e6: 2301 movs r3, #1 + 80015e8: f887 3067 strb.w r3, [r7, #103] @ 0x67 /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed and if there is no conversion on going on regular */ /* group (ADC may already be enabled at this point if HAL_ADC_Init() is */ /* called to update a parameter on the fly). */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && - 80015b4: 687b ldr r3, [r7, #4] - 80015b6: 6c1b ldr r3, [r3, #64] @ 0x40 - 80015b8: f003 0310 and.w r3, r3, #16 - 80015bc: 2b00 cmp r3, #0 - 80015be: f040 80df bne.w 8001780 - 80015c2: f897 3067 ldrb.w r3, [r7, #103] @ 0x67 - 80015c6: 2b00 cmp r3, #0 - 80015c8: f040 80da bne.w 8001780 + 80015ec: 687b ldr r3, [r7, #4] + 80015ee: 6c1b ldr r3, [r3, #64] @ 0x40 + 80015f0: f003 0310 and.w r3, r3, #16 + 80015f4: 2b00 cmp r3, #0 + 80015f6: f040 80df bne.w 80017b8 + 80015fa: f897 3067 ldrb.w r3, [r7, #103] @ 0x67 + 80015fe: 2b00 cmp r3, #0 + 8001600: f040 80da bne.w 80017b8 (tmp_hal_status == HAL_OK) && (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) ) - 80015cc: 687b ldr r3, [r7, #4] - 80015ce: 681b ldr r3, [r3, #0] - 80015d0: 689b ldr r3, [r3, #8] - 80015d2: f003 0304 and.w r3, r3, #4 + 8001604: 687b ldr r3, [r7, #4] + 8001606: 681b ldr r3, [r3, #0] + 8001608: 689b ldr r3, [r3, #8] + 800160a: f003 0304 and.w r3, r3, #4 (tmp_hal_status == HAL_OK) && - 80015d6: 2b00 cmp r3, #0 - 80015d8: f040 80d2 bne.w 8001780 + 800160e: 2b00 cmp r3, #0 + 8001610: f040 80d2 bne.w 80017b8 { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, - 80015dc: 687b ldr r3, [r7, #4] - 80015de: 6c1b ldr r3, [r3, #64] @ 0x40 - 80015e0: f423 7381 bic.w r3, r3, #258 @ 0x102 - 80015e4: f043 0202 orr.w r2, r3, #2 - 80015e8: 687b ldr r3, [r7, #4] - 80015ea: 641a str r2, [r3, #64] @ 0x40 + 8001614: 687b ldr r3, [r7, #4] + 8001616: 6c1b ldr r3, [r3, #64] @ 0x40 + 8001618: f423 7381 bic.w r3, r3, #258 @ 0x102 + 800161c: f043 0202 orr.w r2, r3, #2 + 8001620: 687b ldr r3, [r7, #4] + 8001622: 641a str r2, [r3, #64] @ 0x40 /* Configuration of common ADC parameters */ /* Pointer to the common control register to which is belonging hadc */ /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */ /* control registers) */ tmpADC_Common = ADC_COMMON_REGISTER(hadc); - 80015ec: 4b6f ldr r3, [pc, #444] @ (80017ac ) - 80015ee: 65fb str r3, [r7, #92] @ 0x5c + 8001624: 4b6f ldr r3, [pc, #444] @ (80017e4 ) + 8001626: 65fb str r3, [r7, #92] @ 0x5c /* Set handle of the other ADC sharing the same common register */ ADC_COMMON_ADC_OTHER(hadc, &tmphadcSharingSameCommonRegister); - 80015f0: 687b ldr r3, [r7, #4] - 80015f2: 681b ldr r3, [r3, #0] - 80015f4: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 - 80015f8: d102 bne.n 8001600 - 80015fa: 4b6d ldr r3, [pc, #436] @ (80017b0 ) - 80015fc: 60fb str r3, [r7, #12] - 80015fe: e002 b.n 8001606 - 8001600: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 - 8001604: 60fb str r3, [r7, #12] + 8001628: 687b ldr r3, [r7, #4] + 800162a: 681b ldr r3, [r3, #0] + 800162c: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 + 8001630: d102 bne.n 8001638 + 8001632: 4b6d ldr r3, [pc, #436] @ (80017e8 ) + 8001634: 60fb str r3, [r7, #12] + 8001636: e002 b.n 800163e + 8001638: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 + 800163c: 60fb str r3, [r7, #12] /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - Multimode clock configuration */ if ((ADC_IS_ENABLE(hadc) == RESET) && - 8001606: 687b ldr r3, [r7, #4] - 8001608: 681b ldr r3, [r3, #0] - 800160a: 689b ldr r3, [r3, #8] - 800160c: f003 0303 and.w r3, r3, #3 - 8001610: 2b01 cmp r3, #1 - 8001612: d108 bne.n 8001626 - 8001614: 687b ldr r3, [r7, #4] - 8001616: 681b ldr r3, [r3, #0] - 8001618: 681b ldr r3, [r3, #0] - 800161a: f003 0301 and.w r3, r3, #1 - 800161e: 2b01 cmp r3, #1 - 8001620: d101 bne.n 8001626 - 8001622: 2301 movs r3, #1 - 8001624: e000 b.n 8001628 - 8001626: 2300 movs r3, #0 - 8001628: 2b00 cmp r3, #0 - 800162a: d11c bne.n 8001666 - ((tmphadcSharingSameCommonRegister.Instance == NULL) || - 800162c: 68fb ldr r3, [r7, #12] - if ((ADC_IS_ENABLE(hadc) == RESET) && - 800162e: 2b00 cmp r3, #0 - 8001630: d010 beq.n 8001654 - (ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) ) ) - 8001632: 68fb ldr r3, [r7, #12] - 8001634: 689b ldr r3, [r3, #8] - 8001636: f003 0303 and.w r3, r3, #3 - 800163a: 2b01 cmp r3, #1 - 800163c: d107 bne.n 800164e - 800163e: 68fb ldr r3, [r7, #12] + 800163e: 687b ldr r3, [r7, #4] 8001640: 681b ldr r3, [r3, #0] - 8001642: f003 0301 and.w r3, r3, #1 - 8001646: 2b01 cmp r3, #1 - 8001648: d101 bne.n 800164e - 800164a: 2301 movs r3, #1 - 800164c: e000 b.n 8001650 - 800164e: 2300 movs r3, #0 + 8001642: 689b ldr r3, [r3, #8] + 8001644: f003 0303 and.w r3, r3, #3 + 8001648: 2b01 cmp r3, #1 + 800164a: d108 bne.n 800165e + 800164c: 687b ldr r3, [r7, #4] + 800164e: 681b ldr r3, [r3, #0] + 8001650: 681b ldr r3, [r3, #0] + 8001652: f003 0301 and.w r3, r3, #1 + 8001656: 2b01 cmp r3, #1 + 8001658: d101 bne.n 800165e + 800165a: 2301 movs r3, #1 + 800165c: e000 b.n 8001660 + 800165e: 2300 movs r3, #0 + 8001660: 2b00 cmp r3, #0 + 8001662: d11c bne.n 800169e ((tmphadcSharingSameCommonRegister.Instance == NULL) || - 8001650: 2b00 cmp r3, #0 - 8001652: d108 bne.n 8001666 + 8001664: 68fb ldr r3, [r7, #12] + if ((ADC_IS_ENABLE(hadc) == RESET) && + 8001666: 2b00 cmp r3, #0 + 8001668: d010 beq.n 800168c + (ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) ) ) + 800166a: 68fb ldr r3, [r7, #12] + 800166c: 689b ldr r3, [r3, #8] + 800166e: f003 0303 and.w r3, r3, #3 + 8001672: 2b01 cmp r3, #1 + 8001674: d107 bne.n 8001686 + 8001676: 68fb ldr r3, [r7, #12] + 8001678: 681b ldr r3, [r3, #0] + 800167a: f003 0301 and.w r3, r3, #1 + 800167e: 2b01 cmp r3, #1 + 8001680: d101 bne.n 8001686 + 8001682: 2301 movs r3, #1 + 8001684: e000 b.n 8001688 + 8001686: 2300 movs r3, #0 + ((tmphadcSharingSameCommonRegister.Instance == NULL) || + 8001688: 2b00 cmp r3, #0 + 800168a: d108 bne.n 800169e /* into HAL_ADCEx_MultiModeConfigChannel() ) */ /* - internal measurement paths: Vbat, temperature sensor, Vref */ /* (set into HAL_ADC_ConfigChannel() or */ /* HAL_ADCEx_InjectedConfigChannel() ) */ MODIFY_REG(tmpADC_Common->CCR , - 8001654: 6dfb ldr r3, [r7, #92] @ 0x5c - 8001656: 689b ldr r3, [r3, #8] - 8001658: f423 3240 bic.w r2, r3, #196608 @ 0x30000 - 800165c: 687b ldr r3, [r7, #4] - 800165e: 685b ldr r3, [r3, #4] - 8001660: 431a orrs r2, r3 - 8001662: 6dfb ldr r3, [r7, #92] @ 0x5c - 8001664: 609a str r2, [r3, #8] + 800168c: 6dfb ldr r3, [r7, #92] @ 0x5c + 800168e: 689b ldr r3, [r3, #8] + 8001690: f423 3240 bic.w r2, r3, #196608 @ 0x30000 + 8001694: 687b ldr r3, [r7, #4] + 8001696: 685b ldr r3, [r3, #4] + 8001698: 431a orrs r2, r3 + 800169a: 6dfb ldr r3, [r7, #92] @ 0x5c + 800169c: 609a str r2, [r3, #8] /* - external trigger to start conversion */ /* - external trigger polarity */ /* - continuous conversion mode */ /* - overrun */ /* - discontinuous mode */ SET_BIT(tmpCFGR, ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | - 8001666: 687b ldr r3, [r7, #4] - 8001668: 7e5b ldrb r3, [r3, #25] - 800166a: 035b lsls r3, r3, #13 - 800166c: 687a ldr r2, [r7, #4] - 800166e: 6b52 ldr r2, [r2, #52] @ 0x34 - 8001670: 2a01 cmp r2, #1 - 8001672: d002 beq.n 800167a - 8001674: f44f 5280 mov.w r2, #4096 @ 0x1000 - 8001678: e000 b.n 800167c - 800167a: 2200 movs r2, #0 - 800167c: 431a orrs r2, r3 - 800167e: 687b ldr r3, [r7, #4] - 8001680: 68db ldr r3, [r3, #12] - 8001682: 431a orrs r2, r3 - 8001684: 687b ldr r3, [r7, #4] - 8001686: 689b ldr r3, [r3, #8] - 8001688: 4313 orrs r3, r2 - 800168a: 6e3a ldr r2, [r7, #96] @ 0x60 - 800168c: 4313 orrs r3, r2 - 800168e: 663b str r3, [r7, #96] @ 0x60 + 800169e: 687b ldr r3, [r7, #4] + 80016a0: 7e5b ldrb r3, [r3, #25] + 80016a2: 035b lsls r3, r3, #13 + 80016a4: 687a ldr r2, [r7, #4] + 80016a6: 6b52 ldr r2, [r2, #52] @ 0x34 + 80016a8: 2a01 cmp r2, #1 + 80016aa: d002 beq.n 80016b2 + 80016ac: f44f 5280 mov.w r2, #4096 @ 0x1000 + 80016b0: e000 b.n 80016b4 + 80016b2: 2200 movs r2, #0 + 80016b4: 431a orrs r2, r3 + 80016b6: 687b ldr r3, [r7, #4] + 80016b8: 68db ldr r3, [r3, #12] + 80016ba: 431a orrs r2, r3 + 80016bc: 687b ldr r3, [r7, #4] + 80016be: 689b ldr r3, [r3, #8] + 80016c0: 4313 orrs r3, r2 + 80016c2: 6e3a ldr r2, [r7, #96] @ 0x60 + 80016c4: 4313 orrs r3, r2 + 80016c6: 663b str r3, [r7, #96] @ 0x60 ADC_CFGR_OVERRUN(hadc->Init.Overrun) | hadc->Init.DataAlign | hadc->Init.Resolution ); /* Enable discontinuous mode only if continuous mode is disabled */ if (hadc->Init.DiscontinuousConvMode == ENABLE) - 8001690: 687b ldr r3, [r7, #4] - 8001692: f893 3020 ldrb.w r3, [r3, #32] - 8001696: 2b01 cmp r3, #1 - 8001698: d11b bne.n 80016d2 + 80016c8: 687b ldr r3, [r7, #4] + 80016ca: f893 3020 ldrb.w r3, [r3, #32] + 80016ce: 2b01 cmp r3, #1 + 80016d0: d11b bne.n 800170a { if (hadc->Init.ContinuousConvMode == DISABLE) - 800169a: 687b ldr r3, [r7, #4] - 800169c: 7e5b ldrb r3, [r3, #25] - 800169e: 2b00 cmp r3, #0 - 80016a0: d109 bne.n 80016b6 + 80016d2: 687b ldr r3, [r7, #4] + 80016d4: 7e5b ldrb r3, [r3, #25] + 80016d6: 2b00 cmp r3, #0 + 80016d8: d109 bne.n 80016ee { /* Enable the selected ADC regular discontinuous mode */ /* Set the number of channels to be converted in discontinuous mode */ SET_BIT(tmpCFGR, ADC_CFGR_DISCEN | - 80016a2: 687b ldr r3, [r7, #4] - 80016a4: 6a5b ldr r3, [r3, #36] @ 0x24 - 80016a6: 3b01 subs r3, #1 - 80016a8: 045a lsls r2, r3, #17 - 80016aa: 6e3b ldr r3, [r7, #96] @ 0x60 - 80016ac: 4313 orrs r3, r2 - 80016ae: f443 3380 orr.w r3, r3, #65536 @ 0x10000 - 80016b2: 663b str r3, [r7, #96] @ 0x60 - 80016b4: e00d b.n 80016d2 + 80016da: 687b ldr r3, [r7, #4] + 80016dc: 6a5b ldr r3, [r3, #36] @ 0x24 + 80016de: 3b01 subs r3, #1 + 80016e0: 045a lsls r2, r3, #17 + 80016e2: 6e3b ldr r3, [r7, #96] @ 0x60 + 80016e4: 4313 orrs r3, r2 + 80016e6: f443 3380 orr.w r3, r3, #65536 @ 0x10000 + 80016ea: 663b str r3, [r7, #96] @ 0x60 + 80016ec: e00d b.n 800170a /* ADC regular group discontinuous was intended to be enabled, */ /* but ADC regular group modes continuous and sequencer discontinuous */ /* cannot be enabled simultaneously. */ /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, - 80016b6: 687b ldr r3, [r7, #4] - 80016b8: 6c1b ldr r3, [r3, #64] @ 0x40 - 80016ba: f023 0322 bic.w r3, r3, #34 @ 0x22 - 80016be: f043 0220 orr.w r2, r3, #32 - 80016c2: 687b ldr r3, [r7, #4] - 80016c4: 641a str r2, [r3, #64] @ 0x40 + 80016ee: 687b ldr r3, [r7, #4] + 80016f0: 6c1b ldr r3, [r3, #64] @ 0x40 + 80016f2: f023 0322 bic.w r3, r3, #34 @ 0x22 + 80016f6: f043 0220 orr.w r2, r3, #32 + 80016fa: 687b ldr r3, [r7, #4] + 80016fc: 641a str r2, [r3, #64] @ 0x40 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_CONFIG); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - 80016c6: 687b ldr r3, [r7, #4] - 80016c8: 6c5b ldr r3, [r3, #68] @ 0x44 - 80016ca: f043 0201 orr.w r2, r3, #1 - 80016ce: 687b ldr r3, [r7, #4] - 80016d0: 645a str r2, [r3, #68] @ 0x44 + 80016fe: 687b ldr r3, [r7, #4] + 8001700: 6c5b ldr r3, [r3, #68] @ 0x44 + 8001702: f043 0201 orr.w r2, r3, #1 + 8001706: 687b ldr r3, [r7, #4] + 8001708: 645a str r2, [r3, #68] @ 0x44 /* Enable external trigger if trigger selection is different of software */ /* start. */ /* Note: This configuration keeps the hardware feature of parameter */ /* ExternalTrigConvEdge "trigger edge none" equivalent to */ /* software start. */ if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) - 80016d2: 687b ldr r3, [r7, #4] - 80016d4: 6a9b ldr r3, [r3, #40] @ 0x28 - 80016d6: 2b01 cmp r3, #1 - 80016d8: d007 beq.n 80016ea + 800170a: 687b ldr r3, [r7, #4] + 800170c: 6a9b ldr r3, [r3, #40] @ 0x28 + 800170e: 2b01 cmp r3, #1 + 8001710: d007 beq.n 8001722 { SET_BIT(tmpCFGR, ADC_CFGR_EXTSEL_SET(hadc, hadc->Init.ExternalTrigConv) | - 80016da: 687b ldr r3, [r7, #4] - 80016dc: 6a9a ldr r2, [r3, #40] @ 0x28 - 80016de: 687b ldr r3, [r7, #4] - 80016e0: 6adb ldr r3, [r3, #44] @ 0x2c - 80016e2: 4313 orrs r3, r2 - 80016e4: 6e3a ldr r2, [r7, #96] @ 0x60 - 80016e6: 4313 orrs r3, r2 - 80016e8: 663b str r3, [r7, #96] @ 0x60 + 8001712: 687b ldr r3, [r7, #4] + 8001714: 6a9a ldr r2, [r3, #40] @ 0x28 + 8001716: 687b ldr r3, [r7, #4] + 8001718: 6adb ldr r3, [r3, #44] @ 0x2c + 800171a: 4313 orrs r3, r2 + 800171c: 6e3a ldr r2, [r7, #96] @ 0x60 + 800171e: 4313 orrs r3, r2 + 8001720: 663b str r3, [r7, #96] @ 0x60 /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular and injected groups: */ /* - DMA continuous request */ /* - LowPowerAutoWait feature */ if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) - 80016ea: 687b ldr r3, [r7, #4] - 80016ec: 681b ldr r3, [r3, #0] - 80016ee: 689b ldr r3, [r3, #8] - 80016f0: f003 030c and.w r3, r3, #12 - 80016f4: 2b00 cmp r3, #0 - 80016f6: d114 bne.n 8001722 + 8001722: 687b ldr r3, [r7, #4] + 8001724: 681b ldr r3, [r3, #0] + 8001726: 689b ldr r3, [r3, #8] + 8001728: f003 030c and.w r3, r3, #12 + 800172c: 2b00 cmp r3, #0 + 800172e: d114 bne.n 800175a { CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_AUTDLY | - 80016f8: 687b ldr r3, [r7, #4] - 80016fa: 681b ldr r3, [r3, #0] - 80016fc: 68db ldr r3, [r3, #12] - 80016fe: 687a ldr r2, [r7, #4] - 8001700: 6812 ldr r2, [r2, #0] - 8001702: f423 4380 bic.w r3, r3, #16384 @ 0x4000 - 8001706: f023 0302 bic.w r3, r3, #2 - 800170a: 60d3 str r3, [r2, #12] + 8001730: 687b ldr r3, [r7, #4] + 8001732: 681b ldr r3, [r3, #0] + 8001734: 68db ldr r3, [r3, #12] + 8001736: 687a ldr r2, [r7, #4] + 8001738: 6812 ldr r2, [r2, #0] + 800173a: f423 4380 bic.w r3, r3, #16384 @ 0x4000 + 800173e: f023 0302 bic.w r3, r3, #2 + 8001742: 60d3 str r3, [r2, #12] ADC_CFGR_DMACFG ); SET_BIT(tmpCFGR, ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | - 800170c: 687b ldr r3, [r7, #4] - 800170e: 7e1b ldrb r3, [r3, #24] - 8001710: 039a lsls r2, r3, #14 - 8001712: 687b ldr r3, [r7, #4] - 8001714: f893 3030 ldrb.w r3, [r3, #48] @ 0x30 - 8001718: 005b lsls r3, r3, #1 - 800171a: 4313 orrs r3, r2 - 800171c: 6e3a ldr r2, [r7, #96] @ 0x60 - 800171e: 4313 orrs r3, r2 - 8001720: 663b str r3, [r7, #96] @ 0x60 + 8001744: 687b ldr r3, [r7, #4] + 8001746: 7e1b ldrb r3, [r3, #24] + 8001748: 039a lsls r2, r3, #14 + 800174a: 687b ldr r3, [r7, #4] + 800174c: f893 3030 ldrb.w r3, [r3, #48] @ 0x30 + 8001750: 005b lsls r3, r3, #1 + 8001752: 4313 orrs r3, r2 + 8001754: 6e3a ldr r2, [r7, #96] @ 0x60 + 8001756: 4313 orrs r3, r2 + 8001758: 663b str r3, [r7, #96] @ 0x60 ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests) ); } /* Update ADC configuration register with previous settings */ MODIFY_REG(hadc->Instance->CFGR, - 8001722: 687b ldr r3, [r7, #4] - 8001724: 681b ldr r3, [r3, #0] - 8001726: 68da ldr r2, [r3, #12] - 8001728: 4b22 ldr r3, [pc, #136] @ (80017b4 ) - 800172a: 4013 ands r3, r2 - 800172c: 687a ldr r2, [r7, #4] - 800172e: 6812 ldr r2, [r2, #0] - 8001730: 6e39 ldr r1, [r7, #96] @ 0x60 - 8001732: 430b orrs r3, r1 - 8001734: 60d3 str r3, [r2, #12] + 800175a: 687b ldr r3, [r7, #4] + 800175c: 681b ldr r3, [r3, #0] + 800175e: 68da ldr r2, [r3, #12] + 8001760: 4b22 ldr r3, [pc, #136] @ (80017ec ) + 8001762: 4013 ands r3, r2 + 8001764: 687a ldr r2, [r7, #4] + 8001766: 6812 ldr r2, [r2, #0] + 8001768: 6e39 ldr r1, [r7, #96] @ 0x60 + 800176a: 430b orrs r3, r1 + 800176c: 60d3 str r3, [r2, #12] /* Parameter "NbrOfConversion" is discarded. */ /* Note: Scan mode is not present by hardware on this device, but */ /* emulated by software for alignment over all STM32 devices. */ /* - if scan mode is enabled, regular channels sequence length is set to */ /* parameter "NbrOfConversion" */ if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE) - 8001736: 687b ldr r3, [r7, #4] - 8001738: 691b ldr r3, [r3, #16] - 800173a: 2b01 cmp r3, #1 - 800173c: d10c bne.n 8001758 + 800176e: 687b ldr r3, [r7, #4] + 8001770: 691b ldr r3, [r3, #16] + 8001772: 2b01 cmp r3, #1 + 8001774: d10c bne.n 8001790 { /* Set number of ranks in regular group sequencer */ MODIFY_REG(hadc->Instance->SQR1 , - 800173e: 687b ldr r3, [r7, #4] - 8001740: 681b ldr r3, [r3, #0] - 8001742: 6b1b ldr r3, [r3, #48] @ 0x30 - 8001744: f023 010f bic.w r1, r3, #15 - 8001748: 687b ldr r3, [r7, #4] - 800174a: 69db ldr r3, [r3, #28] - 800174c: 1e5a subs r2, r3, #1 - 800174e: 687b ldr r3, [r7, #4] - 8001750: 681b ldr r3, [r3, #0] - 8001752: 430a orrs r2, r1 - 8001754: 631a str r2, [r3, #48] @ 0x30 - 8001756: e007 b.n 8001768 + 8001776: 687b ldr r3, [r7, #4] + 8001778: 681b ldr r3, [r3, #0] + 800177a: 6b1b ldr r3, [r3, #48] @ 0x30 + 800177c: f023 010f bic.w r1, r3, #15 + 8001780: 687b ldr r3, [r7, #4] + 8001782: 69db ldr r3, [r3, #28] + 8001784: 1e5a subs r2, r3, #1 + 8001786: 687b ldr r3, [r7, #4] + 8001788: 681b ldr r3, [r3, #0] + 800178a: 430a orrs r2, r1 + 800178c: 631a str r2, [r3, #48] @ 0x30 + 800178e: e007 b.n 80017a0 ADC_SQR1_L , (hadc->Init.NbrOfConversion - (uint8_t)1U) ); } else { CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L); - 8001758: 687b ldr r3, [r7, #4] - 800175a: 681b ldr r3, [r3, #0] - 800175c: 6b1a ldr r2, [r3, #48] @ 0x30 - 800175e: 687b ldr r3, [r7, #4] - 8001760: 681b ldr r3, [r3, #0] - 8001762: f022 020f bic.w r2, r2, #15 - 8001766: 631a str r2, [r3, #48] @ 0x30 + 8001790: 687b ldr r3, [r7, #4] + 8001792: 681b ldr r3, [r3, #0] + 8001794: 6b1a ldr r2, [r3, #48] @ 0x30 + 8001796: 687b ldr r3, [r7, #4] + 8001798: 681b ldr r3, [r3, #0] + 800179a: f022 020f bic.w r2, r2, #15 + 800179e: 631a str r2, [r3, #48] @ 0x30 } /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); - 8001768: 687b ldr r3, [r7, #4] - 800176a: 2200 movs r2, #0 - 800176c: 645a str r2, [r3, #68] @ 0x44 + 80017a0: 687b ldr r3, [r7, #4] + 80017a2: 2200 movs r2, #0 + 80017a4: 645a str r2, [r3, #68] @ 0x44 /* Set the ADC state */ ADC_STATE_CLR_SET(hadc->State, - 800176e: 687b ldr r3, [r7, #4] - 8001770: 6c1b ldr r3, [r3, #64] @ 0x40 - 8001772: f023 0303 bic.w r3, r3, #3 - 8001776: f043 0201 orr.w r2, r3, #1 - 800177a: 687b ldr r3, [r7, #4] - 800177c: 641a str r2, [r3, #64] @ 0x40 - 800177e: e00a b.n 8001796 + 80017a6: 687b ldr r3, [r7, #4] + 80017a8: 6c1b ldr r3, [r3, #64] @ 0x40 + 80017aa: f023 0303 bic.w r3, r3, #3 + 80017ae: f043 0201 orr.w r2, r3, #1 + 80017b2: 687b ldr r3, [r7, #4] + 80017b4: 641a str r2, [r3, #64] @ 0x40 + 80017b6: e00a b.n 80017ce HAL_ADC_STATE_READY); } else { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, - 8001780: 687b ldr r3, [r7, #4] - 8001782: 6c1b ldr r3, [r3, #64] @ 0x40 - 8001784: f023 0312 bic.w r3, r3, #18 - 8001788: f043 0210 orr.w r2, r3, #16 - 800178c: 687b ldr r3, [r7, #4] - 800178e: 641a str r2, [r3, #64] @ 0x40 + 80017b8: 687b ldr r3, [r7, #4] + 80017ba: 6c1b ldr r3, [r3, #64] @ 0x40 + 80017bc: f023 0312 bic.w r3, r3, #18 + 80017c0: f043 0210 orr.w r2, r3, #16 + 80017c4: 687b ldr r3, [r7, #4] + 80017c6: 641a str r2, [r3, #64] @ 0x40 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); tmp_hal_status = HAL_ERROR; - 8001790: 2301 movs r3, #1 - 8001792: f887 3067 strb.w r3, [r7, #103] @ 0x67 + 80017c8: 2301 movs r3, #1 + 80017ca: f887 3067 strb.w r3, [r7, #103] @ 0x67 } /* Return function status */ return tmp_hal_status; - 8001796: f897 3067 ldrb.w r3, [r7, #103] @ 0x67 + 80017ce: f897 3067 ldrb.w r3, [r7, #103] @ 0x67 } - 800179a: 4618 mov r0, r3 - 800179c: 3768 adds r7, #104 @ 0x68 - 800179e: 46bd mov sp, r7 - 80017a0: bd80 pop {r7, pc} - 80017a2: bf00 nop - 80017a4: 20000000 .word 0x20000000 - 80017a8: 431bde83 .word 0x431bde83 - 80017ac: 50000300 .word 0x50000300 - 80017b0: 50000100 .word 0x50000100 - 80017b4: fff0c007 .word 0xfff0c007 + 80017d2: 4618 mov r0, r3 + 80017d4: 3768 adds r7, #104 @ 0x68 + 80017d6: 46bd mov sp, r7 + 80017d8: bd80 pop {r7, pc} + 80017da: bf00 nop + 80017dc: 20000000 .word 0x20000000 + 80017e0: 431bde83 .word 0x431bde83 + 80017e4: 50000300 .word 0x50000300 + 80017e8: 50000100 .word 0x50000100 + 80017ec: fff0c007 .word 0xfff0c007 -080017b8 : +080017f0 : * @brief Handles ADC interrupt request. * @param hadc ADC handle * @retval None */ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) { - 80017b8: b580 push {r7, lr} - 80017ba: b088 sub sp, #32 - 80017bc: af00 add r7, sp, #0 - 80017be: 6078 str r0, [r7, #4] + 80017f0: b580 push {r7, lr} + 80017f2: b088 sub sp, #32 + 80017f4: af00 add r7, sp, #0 + 80017f6: 6078 str r0, [r7, #4] uint32_t overrun_error = 0U; /* flag set if overrun occurrence has to be considered as an error */ - 80017c0: 2300 movs r3, #0 - 80017c2: 61fb str r3, [r7, #28] + 80017f8: 2300 movs r3, #0 + 80017fa: 61fb str r3, [r7, #28] ADC_Common_TypeDef *tmpADC_Common; uint32_t tmp_cfgr = 0x0U; - 80017c4: 2300 movs r3, #0 - 80017c6: 61bb str r3, [r7, #24] + 80017fc: 2300 movs r3, #0 + 80017fe: 61bb str r3, [r7, #24] uint32_t tmp_cfgr_jqm = 0x0U; - 80017c8: 2300 movs r3, #0 - 80017ca: 617b str r3, [r7, #20] + 8001800: 2300 movs r3, #0 + 8001802: 617b str r3, [r7, #20] uint32_t tmp_isr = hadc->Instance->ISR; - 80017cc: 687b ldr r3, [r7, #4] - 80017ce: 681b ldr r3, [r3, #0] - 80017d0: 681b ldr r3, [r3, #0] - 80017d2: 613b str r3, [r7, #16] + 8001804: 687b ldr r3, [r7, #4] + 8001806: 681b ldr r3, [r3, #0] + 8001808: 681b ldr r3, [r3, #0] + 800180a: 613b str r3, [r7, #16] uint32_t tmp_ier = hadc->Instance->IER; - 80017d4: 687b ldr r3, [r7, #4] - 80017d6: 681b ldr r3, [r3, #0] - 80017d8: 685b ldr r3, [r3, #4] - 80017da: 60fb str r3, [r7, #12] + 800180c: 687b ldr r3, [r7, #4] + 800180e: 681b ldr r3, [r3, #0] + 8001810: 685b ldr r3, [r3, #4] + 8001812: 60fb str r3, [r7, #12] assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); /* ========== Check End of Conversion flag for regular group ========== */ if( (((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) || - 80017dc: 693b ldr r3, [r7, #16] - 80017de: f003 0304 and.w r3, r3, #4 - 80017e2: 2b00 cmp r3, #0 - 80017e4: d004 beq.n 80017f0 - 80017e6: 68fb ldr r3, [r7, #12] - 80017e8: f003 0304 and.w r3, r3, #4 - 80017ec: 2b00 cmp r3, #0 - 80017ee: d109 bne.n 8001804 + 8001814: 693b ldr r3, [r7, #16] + 8001816: f003 0304 and.w r3, r3, #4 + 800181a: 2b00 cmp r3, #0 + 800181c: d004 beq.n 8001828 + 800181e: 68fb ldr r3, [r7, #12] + 8001820: f003 0304 and.w r3, r3, #4 + 8001824: 2b00 cmp r3, #0 + 8001826: d109 bne.n 800183c (((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS)) ) - 80017f0: 693b ldr r3, [r7, #16] - 80017f2: f003 0308 and.w r3, r3, #8 + 8001828: 693b ldr r3, [r7, #16] + 800182a: f003 0308 and.w r3, r3, #8 if( (((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) || - 80017f6: 2b00 cmp r3, #0 - 80017f8: d076 beq.n 80018e8 + 800182e: 2b00 cmp r3, #0 + 8001830: d076 beq.n 8001920 (((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS)) ) - 80017fa: 68fb ldr r3, [r7, #12] - 80017fc: f003 0308 and.w r3, r3, #8 - 8001800: 2b00 cmp r3, #0 - 8001802: d071 beq.n 80018e8 + 8001832: 68fb ldr r3, [r7, #12] + 8001834: f003 0308 and.w r3, r3, #8 + 8001838: 2b00 cmp r3, #0 + 800183a: d071 beq.n 8001920 { /* Update state machine on conversion status if not in error state */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) - 8001804: 687b ldr r3, [r7, #4] - 8001806: 6c1b ldr r3, [r3, #64] @ 0x40 - 8001808: f003 0310 and.w r3, r3, #16 - 800180c: 2b00 cmp r3, #0 - 800180e: d105 bne.n 800181c + 800183c: 687b ldr r3, [r7, #4] + 800183e: 6c1b ldr r3, [r3, #64] @ 0x40 + 8001840: f003 0310 and.w r3, r3, #16 + 8001844: 2b00 cmp r3, #0 + 8001846: d105 bne.n 8001854 { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); - 8001810: 687b ldr r3, [r7, #4] - 8001812: 6c1b ldr r3, [r3, #64] @ 0x40 - 8001814: f443 7200 orr.w r2, r3, #512 @ 0x200 - 8001818: 687b ldr r3, [r7, #4] - 800181a: 641a str r2, [r3, #64] @ 0x40 + 8001848: 687b ldr r3, [r7, #4] + 800184a: 6c1b ldr r3, [r3, #64] @ 0x40 + 800184c: f443 7200 orr.w r2, r3, #512 @ 0x200 + 8001850: 687b ldr r3, [r7, #4] + 8001852: 641a str r2, [r3, #64] @ 0x40 } /* Get relevant register CFGR in ADC instance of ADC master or slave */ /* in function of multimode state (for devices with multimode */ /* available). */ if (ADC_NONMULTIMODE_REG_OR_MULTIMODEMASTER(hadc)) - 800181c: 4b82 ldr r3, [pc, #520] @ (8001a28 ) - 800181e: 689b ldr r3, [r3, #8] - 8001820: f003 031f and.w r3, r3, #31 - 8001824: 2b00 cmp r3, #0 - 8001826: d010 beq.n 800184a - 8001828: 4b7f ldr r3, [pc, #508] @ (8001a28 ) - 800182a: 689b ldr r3, [r3, #8] - 800182c: f003 031f and.w r3, r3, #31 - 8001830: 2b05 cmp r3, #5 - 8001832: d00a beq.n 800184a - 8001834: 4b7c ldr r3, [pc, #496] @ (8001a28 ) - 8001836: 689b ldr r3, [r3, #8] - 8001838: f003 031f and.w r3, r3, #31 - 800183c: 2b09 cmp r3, #9 - 800183e: d004 beq.n 800184a - 8001840: 687b ldr r3, [r7, #4] - 8001842: 681b ldr r3, [r3, #0] - 8001844: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 - 8001848: d104 bne.n 8001854 + 8001854: 4b82 ldr r3, [pc, #520] @ (8001a60 ) + 8001856: 689b ldr r3, [r3, #8] + 8001858: f003 031f and.w r3, r3, #31 + 800185c: 2b00 cmp r3, #0 + 800185e: d010 beq.n 8001882 + 8001860: 4b7f ldr r3, [pc, #508] @ (8001a60 ) + 8001862: 689b ldr r3, [r3, #8] + 8001864: f003 031f and.w r3, r3, #31 + 8001868: 2b05 cmp r3, #5 + 800186a: d00a beq.n 8001882 + 800186c: 4b7c ldr r3, [pc, #496] @ (8001a60 ) + 800186e: 689b ldr r3, [r3, #8] + 8001870: f003 031f and.w r3, r3, #31 + 8001874: 2b09 cmp r3, #9 + 8001876: d004 beq.n 8001882 + 8001878: 687b ldr r3, [r7, #4] + 800187a: 681b ldr r3, [r3, #0] + 800187c: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 + 8001880: d104 bne.n 800188c { tmp_cfgr = READ_REG(hadc->Instance->CFGR); - 800184a: 687b ldr r3, [r7, #4] - 800184c: 681b ldr r3, [r3, #0] - 800184e: 68db ldr r3, [r3, #12] - 8001850: 61bb str r3, [r7, #24] - 8001852: e003 b.n 800185c + 8001882: 687b ldr r3, [r7, #4] + 8001884: 681b ldr r3, [r3, #0] + 8001886: 68db ldr r3, [r3, #12] + 8001888: 61bb str r3, [r7, #24] + 800188a: e003 b.n 8001894 } else { tmp_cfgr = READ_REG(ADC_MASTER_INSTANCE(hadc)->CFGR); - 8001854: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 - 8001858: 68db ldr r3, [r3, #12] - 800185a: 61bb str r3, [r7, #24] + 800188c: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 + 8001890: 68db ldr r3, [r3, #12] + 8001892: 61bb str r3, [r7, #24] } /* Disable interruption if no further conversion upcoming by regular */ /* external trigger or by continuous mode, */ /* and if scan sequence if completed. */ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && - 800185c: 687b ldr r3, [r7, #4] - 800185e: 681b ldr r3, [r3, #0] - 8001860: 68db ldr r3, [r3, #12] - 8001862: f403 6340 and.w r3, r3, #3072 @ 0xc00 - 8001866: 2b00 cmp r3, #0 - 8001868: d137 bne.n 80018da + 8001894: 687b ldr r3, [r7, #4] + 8001896: 681b ldr r3, [r3, #0] + 8001898: 68db ldr r3, [r3, #12] + 800189a: f403 6340 and.w r3, r3, #3072 @ 0xc00 + 800189e: 2b00 cmp r3, #0 + 80018a0: d137 bne.n 8001912 (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == RESET) ) - 800186a: 69bb ldr r3, [r7, #24] - 800186c: f403 5300 and.w r3, r3, #8192 @ 0x2000 + 80018a2: 69bb ldr r3, [r7, #24] + 80018a4: f403 5300 and.w r3, r3, #8192 @ 0x2000 if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && - 8001870: 2b00 cmp r3, #0 - 8001872: d132 bne.n 80018da + 80018a8: 2b00 cmp r3, #0 + 80018aa: d132 bne.n 8001912 { /* If End of Sequence is reached, disable interrupts */ if((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) - 8001874: 693b ldr r3, [r7, #16] - 8001876: f003 0308 and.w r3, r3, #8 - 800187a: 2b00 cmp r3, #0 - 800187c: d02d beq.n 80018da + 80018ac: 693b ldr r3, [r7, #16] + 80018ae: f003 0308 and.w r3, r3, #8 + 80018b2: 2b00 cmp r3, #0 + 80018b4: d02d beq.n 8001912 { /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */ /* ADSTART==0 (no conversion on going) */ if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) - 800187e: 687b ldr r3, [r7, #4] - 8001880: 681b ldr r3, [r3, #0] - 8001882: 689b ldr r3, [r3, #8] - 8001884: f003 0304 and.w r3, r3, #4 - 8001888: 2b00 cmp r3, #0 - 800188a: d11a bne.n 80018c2 + 80018b6: 687b ldr r3, [r7, #4] + 80018b8: 681b ldr r3, [r3, #0] + 80018ba: 689b ldr r3, [r3, #8] + 80018bc: f003 0304 and.w r3, r3, #4 + 80018c0: 2b00 cmp r3, #0 + 80018c2: d11a bne.n 80018fa { /* Disable ADC end of sequence conversion interrupt */ /* Note: Overrun interrupt was enabled with EOC interrupt in */ /* HAL_Start_IT(), but is not disabled here because can be used */ /* by overrun IRQ process below. */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS); - 800188c: 687b ldr r3, [r7, #4] - 800188e: 681b ldr r3, [r3, #0] - 8001890: 685a ldr r2, [r3, #4] - 8001892: 687b ldr r3, [r7, #4] - 8001894: 681b ldr r3, [r3, #0] - 8001896: f022 020c bic.w r2, r2, #12 - 800189a: 605a str r2, [r3, #4] + 80018c4: 687b ldr r3, [r7, #4] + 80018c6: 681b ldr r3, [r3, #0] + 80018c8: 685a ldr r2, [r3, #4] + 80018ca: 687b ldr r3, [r7, #4] + 80018cc: 681b ldr r3, [r3, #0] + 80018ce: f022 020c bic.w r2, r2, #12 + 80018d2: 605a str r2, [r3, #4] /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); - 800189c: 687b ldr r3, [r7, #4] - 800189e: 6c1b ldr r3, [r3, #64] @ 0x40 - 80018a0: f423 7280 bic.w r2, r3, #256 @ 0x100 - 80018a4: 687b ldr r3, [r7, #4] - 80018a6: 641a str r2, [r3, #64] @ 0x40 + 80018d4: 687b ldr r3, [r7, #4] + 80018d6: 6c1b ldr r3, [r3, #64] @ 0x40 + 80018d8: f423 7280 bic.w r2, r3, #256 @ 0x100 + 80018dc: 687b ldr r3, [r7, #4] + 80018de: 641a str r2, [r3, #64] @ 0x40 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) - 80018a8: 687b ldr r3, [r7, #4] - 80018aa: 6c1b ldr r3, [r3, #64] @ 0x40 - 80018ac: f403 5380 and.w r3, r3, #4096 @ 0x1000 - 80018b0: 2b00 cmp r3, #0 - 80018b2: d112 bne.n 80018da + 80018e0: 687b ldr r3, [r7, #4] + 80018e2: 6c1b ldr r3, [r3, #64] @ 0x40 + 80018e4: f403 5380 and.w r3, r3, #4096 @ 0x1000 + 80018e8: 2b00 cmp r3, #0 + 80018ea: d112 bne.n 8001912 { SET_BIT(hadc->State, HAL_ADC_STATE_READY); - 80018b4: 687b ldr r3, [r7, #4] - 80018b6: 6c1b ldr r3, [r3, #64] @ 0x40 - 80018b8: f043 0201 orr.w r2, r3, #1 - 80018bc: 687b ldr r3, [r7, #4] - 80018be: 641a str r2, [r3, #64] @ 0x40 - 80018c0: e00b b.n 80018da + 80018ec: 687b ldr r3, [r7, #4] + 80018ee: 6c1b ldr r3, [r3, #64] @ 0x40 + 80018f0: f043 0201 orr.w r2, r3, #1 + 80018f4: 687b ldr r3, [r7, #4] + 80018f6: 641a str r2, [r3, #64] @ 0x40 + 80018f8: e00b b.n 8001912 } } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - 80018c2: 687b ldr r3, [r7, #4] - 80018c4: 6c1b ldr r3, [r3, #64] @ 0x40 - 80018c6: f043 0210 orr.w r2, r3, #16 - 80018ca: 687b ldr r3, [r7, #4] - 80018cc: 641a str r2, [r3, #64] @ 0x40 + 80018fa: 687b ldr r3, [r7, #4] + 80018fc: 6c1b ldr r3, [r3, #64] @ 0x40 + 80018fe: f043 0210 orr.w r2, r3, #16 + 8001902: 687b ldr r3, [r7, #4] + 8001904: 641a str r2, [r3, #64] @ 0x40 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - 80018ce: 687b ldr r3, [r7, #4] - 80018d0: 6c5b ldr r3, [r3, #68] @ 0x44 - 80018d2: f043 0201 orr.w r2, r3, #1 - 80018d6: 687b ldr r3, [r7, #4] - 80018d8: 645a str r2, [r3, #68] @ 0x44 + 8001906: 687b ldr r3, [r7, #4] + 8001908: 6c5b ldr r3, [r3, #68] @ 0x44 + 800190a: f043 0201 orr.w r2, r3, #1 + 800190e: 687b ldr r3, [r7, #4] + 8001910: 645a str r2, [r3, #68] @ 0x44 /* from EOC or EOS, possibility to use: */ /* " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvCpltCallback(hadc); #else HAL_ADC_ConvCpltCallback(hadc); - 80018da: 6878 ldr r0, [r7, #4] - 80018dc: f7ff fdbc bl 8001458 + 8001912: 6878 ldr r0, [r7, #4] + 8001914: f7ff fdbc bl 8001490 /* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of */ /* conversion flags clear induces the release of the preserved */ /* data. */ /* Therefore, if the preserved data value is needed, it must be */ /* read preliminarily into HAL_ADC_ConvCpltCallback(). */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS) ); - 80018e0: 687b ldr r3, [r7, #4] - 80018e2: 681b ldr r3, [r3, #0] - 80018e4: 220c movs r2, #12 - 80018e6: 601a str r2, [r3, #0] + 8001918: 687b ldr r3, [r7, #4] + 800191a: 681b ldr r3, [r3, #0] + 800191c: 220c movs r2, #12 + 800191e: 601a str r2, [r3, #0] } /* ========== Check End of Conversion flag for injected group ========== */ if( (((tmp_isr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) && ((tmp_ier & ADC_IT_JEOC) == ADC_IT_JEOC)) || - 80018e8: 693b ldr r3, [r7, #16] - 80018ea: f003 0320 and.w r3, r3, #32 - 80018ee: 2b00 cmp r3, #0 - 80018f0: d004 beq.n 80018fc - 80018f2: 68fb ldr r3, [r7, #12] - 80018f4: f003 0320 and.w r3, r3, #32 - 80018f8: 2b00 cmp r3, #0 - 80018fa: d10b bne.n 8001914 + 8001920: 693b ldr r3, [r7, #16] + 8001922: f003 0320 and.w r3, r3, #32 + 8001926: 2b00 cmp r3, #0 + 8001928: d004 beq.n 8001934 + 800192a: 68fb ldr r3, [r7, #12] + 800192c: f003 0320 and.w r3, r3, #32 + 8001930: 2b00 cmp r3, #0 + 8001932: d10b bne.n 800194c (((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) && ((tmp_ier & ADC_IT_JEOS) == ADC_IT_JEOS)) ) - 80018fc: 693b ldr r3, [r7, #16] - 80018fe: f003 0340 and.w r3, r3, #64 @ 0x40 + 8001934: 693b ldr r3, [r7, #16] + 8001936: f003 0340 and.w r3, r3, #64 @ 0x40 if( (((tmp_isr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) && ((tmp_ier & ADC_IT_JEOC) == ADC_IT_JEOC)) || - 8001902: 2b00 cmp r3, #0 - 8001904: f000 80a5 beq.w 8001a52 + 800193a: 2b00 cmp r3, #0 + 800193c: f000 80a5 beq.w 8001a8a (((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) && ((tmp_ier & ADC_IT_JEOS) == ADC_IT_JEOS)) ) - 8001908: 68fb ldr r3, [r7, #12] - 800190a: f003 0340 and.w r3, r3, #64 @ 0x40 - 800190e: 2b00 cmp r3, #0 - 8001910: f000 809f beq.w 8001a52 + 8001940: 68fb ldr r3, [r7, #12] + 8001942: f003 0340 and.w r3, r3, #64 @ 0x40 + 8001946: 2b00 cmp r3, #0 + 8001948: f000 809f beq.w 8001a8a { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); - 8001914: 687b ldr r3, [r7, #4] - 8001916: 6c1b ldr r3, [r3, #64] @ 0x40 - 8001918: f443 5200 orr.w r2, r3, #8192 @ 0x2000 - 800191c: 687b ldr r3, [r7, #4] - 800191e: 641a str r2, [r3, #64] @ 0x40 + 800194c: 687b ldr r3, [r7, #4] + 800194e: 6c1b ldr r3, [r3, #64] @ 0x40 + 8001950: f443 5200 orr.w r2, r3, #8192 @ 0x2000 + 8001954: 687b ldr r3, [r7, #4] + 8001956: 641a str r2, [r3, #64] @ 0x40 /* Get relevant register CFGR in ADC instance of ADC master or slave */ /* in function of multimode state (for devices with multimode */ /* available). */ if (ADC_NONMULTIMODE_REG_OR_MULTIMODEMASTER(hadc)) - 8001920: 4b41 ldr r3, [pc, #260] @ (8001a28 ) - 8001922: 689b ldr r3, [r3, #8] - 8001924: f003 031f and.w r3, r3, #31 - 8001928: 2b00 cmp r3, #0 - 800192a: d010 beq.n 800194e - 800192c: 4b3e ldr r3, [pc, #248] @ (8001a28 ) - 800192e: 689b ldr r3, [r3, #8] - 8001930: f003 031f and.w r3, r3, #31 - 8001934: 2b05 cmp r3, #5 - 8001936: d00a beq.n 800194e - 8001938: 4b3b ldr r3, [pc, #236] @ (8001a28 ) - 800193a: 689b ldr r3, [r3, #8] - 800193c: f003 031f and.w r3, r3, #31 - 8001940: 2b09 cmp r3, #9 - 8001942: d004 beq.n 800194e - 8001944: 687b ldr r3, [r7, #4] - 8001946: 681b ldr r3, [r3, #0] - 8001948: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 - 800194c: d104 bne.n 8001958 + 8001958: 4b41 ldr r3, [pc, #260] @ (8001a60 ) + 800195a: 689b ldr r3, [r3, #8] + 800195c: f003 031f and.w r3, r3, #31 + 8001960: 2b00 cmp r3, #0 + 8001962: d010 beq.n 8001986 + 8001964: 4b3e ldr r3, [pc, #248] @ (8001a60 ) + 8001966: 689b ldr r3, [r3, #8] + 8001968: f003 031f and.w r3, r3, #31 + 800196c: 2b05 cmp r3, #5 + 800196e: d00a beq.n 8001986 + 8001970: 4b3b ldr r3, [pc, #236] @ (8001a60 ) + 8001972: 689b ldr r3, [r3, #8] + 8001974: f003 031f and.w r3, r3, #31 + 8001978: 2b09 cmp r3, #9 + 800197a: d004 beq.n 8001986 + 800197c: 687b ldr r3, [r7, #4] + 800197e: 681b ldr r3, [r3, #0] + 8001980: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 + 8001984: d104 bne.n 8001990 { tmp_cfgr = READ_REG(hadc->Instance->CFGR); - 800194e: 687b ldr r3, [r7, #4] - 8001950: 681b ldr r3, [r3, #0] - 8001952: 68db ldr r3, [r3, #12] - 8001954: 61bb str r3, [r7, #24] - 8001956: e003 b.n 8001960 + 8001986: 687b ldr r3, [r7, #4] + 8001988: 681b ldr r3, [r3, #0] + 800198a: 68db ldr r3, [r3, #12] + 800198c: 61bb str r3, [r7, #24] + 800198e: e003 b.n 8001998 } else { tmp_cfgr = READ_REG(ADC_MASTER_INSTANCE(hadc)->CFGR); - 8001958: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 - 800195c: 68db ldr r3, [r3, #12] - 800195e: 61bb str r3, [r7, #24] + 8001990: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 + 8001994: 68db ldr r3, [r3, #12] + 8001996: 61bb str r3, [r7, #24] /* Disable interruption if no further conversion upcoming by injected */ /* external trigger or by automatic injected conversion with regular */ /* group having no further conversion upcoming (same conditions as */ /* regular group interruption disabling above), */ /* and if injected scan sequence is completed. */ if(ADC_IS_SOFTWARE_START_INJECTED(hadc)) - 8001960: 687b ldr r3, [r7, #4] - 8001962: 681b ldr r3, [r3, #0] - 8001964: 6cdb ldr r3, [r3, #76] @ 0x4c - 8001966: f003 03c0 and.w r3, r3, #192 @ 0xc0 - 800196a: 2b00 cmp r3, #0 - 800196c: d16a bne.n 8001a44 + 8001998: 687b ldr r3, [r7, #4] + 800199a: 681b ldr r3, [r3, #0] + 800199c: 6cdb ldr r3, [r3, #76] @ 0x4c + 800199e: f003 03c0 and.w r3, r3, #192 @ 0xc0 + 80019a2: 2b00 cmp r3, #0 + 80019a4: d16a bne.n 8001a7c { if((READ_BIT (tmp_cfgr, ADC_CFGR_JAUTO) == RESET) || - 800196e: 69bb ldr r3, [r7, #24] - 8001970: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 - 8001974: 2b00 cmp r3, #0 - 8001976: d00b beq.n 8001990 + 80019a6: 69bb ldr r3, [r7, #24] + 80019a8: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 80019ac: 2b00 cmp r3, #0 + 80019ae: d00b beq.n 80019c8 (ADC_IS_SOFTWARE_START_REGULAR(hadc) && - 8001978: 687b ldr r3, [r7, #4] - 800197a: 681b ldr r3, [r3, #0] - 800197c: 68db ldr r3, [r3, #12] - 800197e: f403 6340 and.w r3, r3, #3072 @ 0xc00 + 80019b0: 687b ldr r3, [r7, #4] + 80019b2: 681b ldr r3, [r3, #0] + 80019b4: 68db ldr r3, [r3, #12] + 80019b6: f403 6340 and.w r3, r3, #3072 @ 0xc00 if((READ_BIT (tmp_cfgr, ADC_CFGR_JAUTO) == RESET) || - 8001982: 2b00 cmp r3, #0 - 8001984: d15e bne.n 8001a44 + 80019ba: 2b00 cmp r3, #0 + 80019bc: d15e bne.n 8001a7c (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) == RESET) ) ) - 8001986: 69bb ldr r3, [r7, #24] - 8001988: f403 5300 and.w r3, r3, #8192 @ 0x2000 + 80019be: 69bb ldr r3, [r7, #24] + 80019c0: f403 5300 and.w r3, r3, #8192 @ 0x2000 (ADC_IS_SOFTWARE_START_REGULAR(hadc) && - 800198c: 2b00 cmp r3, #0 - 800198e: d159 bne.n 8001a44 + 80019c4: 2b00 cmp r3, #0 + 80019c6: d159 bne.n 8001a7c { /* If End of Sequence is reached, disable interrupts */ if((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) - 8001990: 693b ldr r3, [r7, #16] - 8001992: f003 0340 and.w r3, r3, #64 @ 0x40 - 8001996: 2b00 cmp r3, #0 - 8001998: d054 beq.n 8001a44 + 80019c8: 693b ldr r3, [r7, #16] + 80019ca: f003 0340 and.w r3, r3, #64 @ 0x40 + 80019ce: 2b00 cmp r3, #0 + 80019d0: d054 beq.n 8001a7c { /* Get relevant register CFGR in ADC instance of ADC master or slave */ /* in function of multimode state (for devices with multimode */ /* available). */ if (ADC_NONMULTIMODE_INJ_OR_MULTIMODEMASTER(hadc)) - 800199a: 4b23 ldr r3, [pc, #140] @ (8001a28 ) - 800199c: 689b ldr r3, [r3, #8] - 800199e: f003 031f and.w r3, r3, #31 - 80019a2: 2b00 cmp r3, #0 - 80019a4: d010 beq.n 80019c8 - 80019a6: 4b20 ldr r3, [pc, #128] @ (8001a28 ) - 80019a8: 689b ldr r3, [r3, #8] - 80019aa: f003 031f and.w r3, r3, #31 - 80019ae: 2b06 cmp r3, #6 - 80019b0: d00a beq.n 80019c8 - 80019b2: 4b1d ldr r3, [pc, #116] @ (8001a28 ) - 80019b4: 689b ldr r3, [r3, #8] - 80019b6: f003 031f and.w r3, r3, #31 - 80019ba: 2b07 cmp r3, #7 - 80019bc: d004 beq.n 80019c8 - 80019be: 687b ldr r3, [r7, #4] - 80019c0: 681b ldr r3, [r3, #0] - 80019c2: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 - 80019c6: d104 bne.n 80019d2 + 80019d2: 4b23 ldr r3, [pc, #140] @ (8001a60 ) + 80019d4: 689b ldr r3, [r3, #8] + 80019d6: f003 031f and.w r3, r3, #31 + 80019da: 2b00 cmp r3, #0 + 80019dc: d010 beq.n 8001a00 + 80019de: 4b20 ldr r3, [pc, #128] @ (8001a60 ) + 80019e0: 689b ldr r3, [r3, #8] + 80019e2: f003 031f and.w r3, r3, #31 + 80019e6: 2b06 cmp r3, #6 + 80019e8: d00a beq.n 8001a00 + 80019ea: 4b1d ldr r3, [pc, #116] @ (8001a60 ) + 80019ec: 689b ldr r3, [r3, #8] + 80019ee: f003 031f and.w r3, r3, #31 + 80019f2: 2b07 cmp r3, #7 + 80019f4: d004 beq.n 8001a00 + 80019f6: 687b ldr r3, [r7, #4] + 80019f8: 681b ldr r3, [r3, #0] + 80019fa: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 + 80019fe: d104 bne.n 8001a0a { tmp_cfgr_jqm = READ_REG(hadc->Instance->CFGR); - 80019c8: 687b ldr r3, [r7, #4] - 80019ca: 681b ldr r3, [r3, #0] - 80019cc: 68db ldr r3, [r3, #12] - 80019ce: 617b str r3, [r7, #20] - 80019d0: e003 b.n 80019da + 8001a00: 687b ldr r3, [r7, #4] + 8001a02: 681b ldr r3, [r3, #0] + 8001a04: 68db ldr r3, [r3, #12] + 8001a06: 617b str r3, [r7, #20] + 8001a08: e003 b.n 8001a12 } else { tmp_cfgr_jqm = READ_REG(ADC_MASTER_INSTANCE(hadc)->CFGR); - 80019d2: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 - 80019d6: 68db ldr r3, [r3, #12] - 80019d8: 617b str r3, [r7, #20] + 8001a0a: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 + 8001a0e: 68db ldr r3, [r3, #12] + 8001a10: 617b str r3, [r7, #20] /* when the last context has been fully processed, JSQR is reset */ /* by the hardware. Even if no injected conversion is planned to come */ /* (queue empty, triggers are ignored), it can start again */ /* immediately after setting a new context (JADSTART is still set). */ /* Therefore, state of HAL ADC injected group is kept to busy. */ if(READ_BIT(tmp_cfgr_jqm, ADC_CFGR_JQM) == RESET) - 80019da: 697b ldr r3, [r7, #20] - 80019dc: f403 1300 and.w r3, r3, #2097152 @ 0x200000 - 80019e0: 2b00 cmp r3, #0 - 80019e2: d12f bne.n 8001a44 + 8001a12: 697b ldr r3, [r7, #20] + 8001a14: f403 1300 and.w r3, r3, #2097152 @ 0x200000 + 8001a18: 2b00 cmp r3, #0 + 8001a1a: d12f bne.n 8001a7c { /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */ /* JADSTART==0 (no conversion on going) */ if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET) - 80019e4: 687b ldr r3, [r7, #4] - 80019e6: 681b ldr r3, [r3, #0] - 80019e8: 689b ldr r3, [r3, #8] - 80019ea: f003 0308 and.w r3, r3, #8 - 80019ee: 2b00 cmp r3, #0 - 80019f0: d11c bne.n 8001a2c + 8001a1c: 687b ldr r3, [r7, #4] + 8001a1e: 681b ldr r3, [r3, #0] + 8001a20: 689b ldr r3, [r3, #8] + 8001a22: f003 0308 and.w r3, r3, #8 + 8001a26: 2b00 cmp r3, #0 + 8001a28: d11c bne.n 8001a64 { /* Disable ADC end of sequence conversion interrupt */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS); - 80019f2: 687b ldr r3, [r7, #4] - 80019f4: 681b ldr r3, [r3, #0] - 80019f6: 685a ldr r2, [r3, #4] - 80019f8: 687b ldr r3, [r7, #4] - 80019fa: 681b ldr r3, [r3, #0] - 80019fc: f022 0260 bic.w r2, r2, #96 @ 0x60 - 8001a00: 605a str r2, [r3, #4] + 8001a2a: 687b ldr r3, [r7, #4] + 8001a2c: 681b ldr r3, [r3, #0] + 8001a2e: 685a ldr r2, [r3, #4] + 8001a30: 687b ldr r3, [r7, #4] + 8001a32: 681b ldr r3, [r3, #0] + 8001a34: f022 0260 bic.w r2, r2, #96 @ 0x60 + 8001a38: 605a str r2, [r3, #4] /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); - 8001a02: 687b ldr r3, [r7, #4] - 8001a04: 6c1b ldr r3, [r3, #64] @ 0x40 - 8001a06: f423 5280 bic.w r2, r3, #4096 @ 0x1000 - 8001a0a: 687b ldr r3, [r7, #4] - 8001a0c: 641a str r2, [r3, #64] @ 0x40 + 8001a3a: 687b ldr r3, [r7, #4] + 8001a3c: 6c1b ldr r3, [r3, #64] @ 0x40 + 8001a3e: f423 5280 bic.w r2, r3, #4096 @ 0x1000 + 8001a42: 687b ldr r3, [r7, #4] + 8001a44: 641a str r2, [r3, #64] @ 0x40 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) - 8001a0e: 687b ldr r3, [r7, #4] - 8001a10: 6c1b ldr r3, [r3, #64] @ 0x40 - 8001a12: f403 7380 and.w r3, r3, #256 @ 0x100 - 8001a16: 2b00 cmp r3, #0 - 8001a18: d114 bne.n 8001a44 + 8001a46: 687b ldr r3, [r7, #4] + 8001a48: 6c1b ldr r3, [r3, #64] @ 0x40 + 8001a4a: f403 7380 and.w r3, r3, #256 @ 0x100 + 8001a4e: 2b00 cmp r3, #0 + 8001a50: d114 bne.n 8001a7c { SET_BIT(hadc->State, HAL_ADC_STATE_READY); - 8001a1a: 687b ldr r3, [r7, #4] - 8001a1c: 6c1b ldr r3, [r3, #64] @ 0x40 - 8001a1e: f043 0201 orr.w r2, r3, #1 - 8001a22: 687b ldr r3, [r7, #4] - 8001a24: 641a str r2, [r3, #64] @ 0x40 - 8001a26: e00d b.n 8001a44 - 8001a28: 50000300 .word 0x50000300 + 8001a52: 687b ldr r3, [r7, #4] + 8001a54: 6c1b ldr r3, [r3, #64] @ 0x40 + 8001a56: f043 0201 orr.w r2, r3, #1 + 8001a5a: 687b ldr r3, [r7, #4] + 8001a5c: 641a str r2, [r3, #64] @ 0x40 + 8001a5e: e00d b.n 8001a7c + 8001a60: 50000300 .word 0x50000300 } } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - 8001a2c: 687b ldr r3, [r7, #4] - 8001a2e: 6c1b ldr r3, [r3, #64] @ 0x40 - 8001a30: f043 0210 orr.w r2, r3, #16 - 8001a34: 687b ldr r3, [r7, #4] - 8001a36: 641a str r2, [r3, #64] @ 0x40 + 8001a64: 687b ldr r3, [r7, #4] + 8001a66: 6c1b ldr r3, [r3, #64] @ 0x40 + 8001a68: f043 0210 orr.w r2, r3, #16 + 8001a6c: 687b ldr r3, [r7, #4] + 8001a6e: 641a str r2, [r3, #64] @ 0x40 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - 8001a38: 687b ldr r3, [r7, #4] - 8001a3a: 6c5b ldr r3, [r3, #68] @ 0x44 - 8001a3c: f043 0201 orr.w r2, r3, #1 - 8001a40: 687b ldr r3, [r7, #4] - 8001a42: 645a str r2, [r3, #68] @ 0x44 + 8001a70: 687b ldr r3, [r7, #4] + 8001a72: 6c5b ldr r3, [r3, #68] @ 0x44 + 8001a74: f043 0201 orr.w r2, r3, #1 + 8001a78: 687b ldr r3, [r7, #4] + 8001a7a: 645a str r2, [r3, #68] @ 0x44 /* from JEOC or JEOS, possibility to use: */ /* " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOS)) " */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->InjectedConvCpltCallback(hadc); #else HAL_ADCEx_InjectedConvCpltCallback(hadc); - 8001a44: 6878 ldr r0, [r7, #4] - 8001a46: f000 f8b1 bl 8001bac + 8001a7c: 6878 ldr r0, [r7, #4] + 8001a7e: f000 f8b1 bl 8001be4 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear injected group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC | ADC_FLAG_JEOS); - 8001a4a: 687b ldr r3, [r7, #4] - 8001a4c: 681b ldr r3, [r3, #0] - 8001a4e: 2260 movs r2, #96 @ 0x60 - 8001a50: 601a str r2, [r3, #0] + 8001a82: 687b ldr r3, [r7, #4] + 8001a84: 681b ldr r3, [r3, #0] + 8001a86: 2260 movs r2, #96 @ 0x60 + 8001a88: 601a str r2, [r3, #0] } /* ========== Check analog watchdog 1 flag ========== */ if(((tmp_isr & ADC_FLAG_AWD1) == ADC_FLAG_AWD1) && ((tmp_ier & ADC_IT_AWD1) == ADC_IT_AWD1)) - 8001a52: 693b ldr r3, [r7, #16] - 8001a54: f003 0380 and.w r3, r3, #128 @ 0x80 - 8001a58: 2b00 cmp r3, #0 - 8001a5a: d011 beq.n 8001a80 - 8001a5c: 68fb ldr r3, [r7, #12] - 8001a5e: f003 0380 and.w r3, r3, #128 @ 0x80 - 8001a62: 2b00 cmp r3, #0 - 8001a64: d00c beq.n 8001a80 + 8001a8a: 693b ldr r3, [r7, #16] + 8001a8c: f003 0380 and.w r3, r3, #128 @ 0x80 + 8001a90: 2b00 cmp r3, #0 + 8001a92: d011 beq.n 8001ab8 + 8001a94: 68fb ldr r3, [r7, #12] + 8001a96: f003 0380 and.w r3, r3, #128 @ 0x80 + 8001a9a: 2b00 cmp r3, #0 + 8001a9c: d00c beq.n 8001ab8 { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); - 8001a66: 687b ldr r3, [r7, #4] - 8001a68: 6c1b ldr r3, [r3, #64] @ 0x40 - 8001a6a: f443 3280 orr.w r2, r3, #65536 @ 0x10000 - 8001a6e: 687b ldr r3, [r7, #4] - 8001a70: 641a str r2, [r3, #64] @ 0x40 + 8001a9e: 687b ldr r3, [r7, #4] + 8001aa0: 6c1b ldr r3, [r3, #64] @ 0x40 + 8001aa2: f443 3280 orr.w r2, r3, #65536 @ 0x10000 + 8001aa6: 687b ldr r3, [r7, #4] + 8001aa8: 641a str r2, [r3, #64] @ 0x40 /* Level out of window 1 callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->LevelOutOfWindowCallback(hadc); #else HAL_ADC_LevelOutOfWindowCallback(hadc); - 8001a72: 6878 ldr r0, [r7, #4] - 8001a74: f7ff fcfa bl 800146c + 8001aaa: 6878 ldr r0, [r7, #4] + 8001aac: f7ff fcfa bl 80014a4 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear ADC analog watchdog flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1); - 8001a78: 687b ldr r3, [r7, #4] - 8001a7a: 681b ldr r3, [r3, #0] - 8001a7c: 2280 movs r2, #128 @ 0x80 - 8001a7e: 601a str r2, [r3, #0] + 8001ab0: 687b ldr r3, [r7, #4] + 8001ab2: 681b ldr r3, [r3, #0] + 8001ab4: 2280 movs r2, #128 @ 0x80 + 8001ab6: 601a str r2, [r3, #0] } /* ========== Check analog watchdog 2 flag ========== */ if(((tmp_isr & ADC_FLAG_AWD2) == ADC_FLAG_AWD2) && ((tmp_ier & ADC_IT_AWD2) == ADC_IT_AWD2)) - 8001a80: 693b ldr r3, [r7, #16] - 8001a82: f403 7380 and.w r3, r3, #256 @ 0x100 - 8001a86: 2b00 cmp r3, #0 - 8001a88: d012 beq.n 8001ab0 - 8001a8a: 68fb ldr r3, [r7, #12] - 8001a8c: f403 7380 and.w r3, r3, #256 @ 0x100 - 8001a90: 2b00 cmp r3, #0 - 8001a92: d00d beq.n 8001ab0 + 8001ab8: 693b ldr r3, [r7, #16] + 8001aba: f403 7380 and.w r3, r3, #256 @ 0x100 + 8001abe: 2b00 cmp r3, #0 + 8001ac0: d012 beq.n 8001ae8 + 8001ac2: 68fb ldr r3, [r7, #12] + 8001ac4: f403 7380 and.w r3, r3, #256 @ 0x100 + 8001ac8: 2b00 cmp r3, #0 + 8001aca: d00d beq.n 8001ae8 { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_AWD2); - 8001a94: 687b ldr r3, [r7, #4] - 8001a96: 6c1b ldr r3, [r3, #64] @ 0x40 - 8001a98: f443 3200 orr.w r2, r3, #131072 @ 0x20000 - 8001a9c: 687b ldr r3, [r7, #4] - 8001a9e: 641a str r2, [r3, #64] @ 0x40 + 8001acc: 687b ldr r3, [r7, #4] + 8001ace: 6c1b ldr r3, [r3, #64] @ 0x40 + 8001ad0: f443 3200 orr.w r2, r3, #131072 @ 0x20000 + 8001ad4: 687b ldr r3, [r7, #4] + 8001ad6: 641a str r2, [r3, #64] @ 0x40 /* Level out of window 2 callback */ HAL_ADCEx_LevelOutOfWindow2Callback(hadc); - 8001aa0: 6878 ldr r0, [r7, #4] - 8001aa2: f000 f897 bl 8001bd4 + 8001ad8: 6878 ldr r0, [r7, #4] + 8001ada: f000 f897 bl 8001c0c /* Clear ADC analog watchdog flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2); - 8001aa6: 687b ldr r3, [r7, #4] - 8001aa8: 681b ldr r3, [r3, #0] - 8001aaa: f44f 7280 mov.w r2, #256 @ 0x100 - 8001aae: 601a str r2, [r3, #0] + 8001ade: 687b ldr r3, [r7, #4] + 8001ae0: 681b ldr r3, [r3, #0] + 8001ae2: f44f 7280 mov.w r2, #256 @ 0x100 + 8001ae6: 601a str r2, [r3, #0] } /* ========== Check analog watchdog 3 flag ========== */ if(((tmp_isr & ADC_FLAG_AWD3) == ADC_FLAG_AWD3) && ((tmp_ier & ADC_IT_AWD3) == ADC_IT_AWD3)) - 8001ab0: 693b ldr r3, [r7, #16] - 8001ab2: f403 7300 and.w r3, r3, #512 @ 0x200 - 8001ab6: 2b00 cmp r3, #0 - 8001ab8: d012 beq.n 8001ae0 - 8001aba: 68fb ldr r3, [r7, #12] - 8001abc: f403 7300 and.w r3, r3, #512 @ 0x200 - 8001ac0: 2b00 cmp r3, #0 - 8001ac2: d00d beq.n 8001ae0 + 8001ae8: 693b ldr r3, [r7, #16] + 8001aea: f403 7300 and.w r3, r3, #512 @ 0x200 + 8001aee: 2b00 cmp r3, #0 + 8001af0: d012 beq.n 8001b18 + 8001af2: 68fb ldr r3, [r7, #12] + 8001af4: f403 7300 and.w r3, r3, #512 @ 0x200 + 8001af8: 2b00 cmp r3, #0 + 8001afa: d00d beq.n 8001b18 { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_AWD3); - 8001ac4: 687b ldr r3, [r7, #4] - 8001ac6: 6c1b ldr r3, [r3, #64] @ 0x40 - 8001ac8: f443 2280 orr.w r2, r3, #262144 @ 0x40000 - 8001acc: 687b ldr r3, [r7, #4] - 8001ace: 641a str r2, [r3, #64] @ 0x40 + 8001afc: 687b ldr r3, [r7, #4] + 8001afe: 6c1b ldr r3, [r3, #64] @ 0x40 + 8001b00: f443 2280 orr.w r2, r3, #262144 @ 0x40000 + 8001b04: 687b ldr r3, [r7, #4] + 8001b06: 641a str r2, [r3, #64] @ 0x40 /* Level out of window 3 callback */ HAL_ADCEx_LevelOutOfWindow3Callback(hadc); - 8001ad0: 6878 ldr r0, [r7, #4] - 8001ad2: f000 f889 bl 8001be8 + 8001b08: 6878 ldr r0, [r7, #4] + 8001b0a: f000 f889 bl 8001c20 /* Clear ADC analog watchdog flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3); - 8001ad6: 687b ldr r3, [r7, #4] - 8001ad8: 681b ldr r3, [r3, #0] - 8001ada: f44f 7200 mov.w r2, #512 @ 0x200 - 8001ade: 601a str r2, [r3, #0] + 8001b0e: 687b ldr r3, [r7, #4] + 8001b10: 681b ldr r3, [r3, #0] + 8001b12: f44f 7200 mov.w r2, #512 @ 0x200 + 8001b16: 601a str r2, [r3, #0] } /* ========== Check Overrun flag ========== */ if(((tmp_isr & ADC_FLAG_OVR) == ADC_FLAG_OVR) && ((tmp_ier & ADC_IT_OVR) == ADC_IT_OVR)) - 8001ae0: 693b ldr r3, [r7, #16] - 8001ae2: f003 0310 and.w r3, r3, #16 - 8001ae6: 2b00 cmp r3, #0 - 8001ae8: d03b beq.n 8001b62 - 8001aea: 68fb ldr r3, [r7, #12] - 8001aec: f003 0310 and.w r3, r3, #16 - 8001af0: 2b00 cmp r3, #0 - 8001af2: d036 beq.n 8001b62 + 8001b18: 693b ldr r3, [r7, #16] + 8001b1a: f003 0310 and.w r3, r3, #16 + 8001b1e: 2b00 cmp r3, #0 + 8001b20: d03b beq.n 8001b9a + 8001b22: 68fb ldr r3, [r7, #12] + 8001b24: f003 0310 and.w r3, r3, #16 + 8001b28: 2b00 cmp r3, #0 + 8001b2a: d036 beq.n 8001b9a /* overrun event is not considered as an error. */ /* (cf ref manual "Managing conversions without using the DMA and */ /* without overrun ") */ /* Exception for usage with DMA overrun event always considered as an */ /* error. */ if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) - 8001af4: 687b ldr r3, [r7, #4] - 8001af6: 6b5b ldr r3, [r3, #52] @ 0x34 - 8001af8: 2b01 cmp r3, #1 - 8001afa: d102 bne.n 8001b02 + 8001b2c: 687b ldr r3, [r7, #4] + 8001b2e: 6b5b ldr r3, [r3, #52] @ 0x34 + 8001b30: 2b01 cmp r3, #1 + 8001b32: d102 bne.n 8001b3a { overrun_error = 1U; - 8001afc: 2301 movs r3, #1 - 8001afe: 61fb str r3, [r7, #28] - 8001b00: e019 b.n 8001b36 + 8001b34: 2301 movs r3, #1 + 8001b36: 61fb str r3, [r7, #28] + 8001b38: e019 b.n 8001b6e else { /* Pointer to the common control register to which is belonging hadc */ /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */ /* control registers) */ tmpADC_Common = ADC_COMMON_REGISTER(hadc); - 8001b02: 4b29 ldr r3, [pc, #164] @ (8001ba8 ) - 8001b04: 60bb str r3, [r7, #8] + 8001b3a: 4b29 ldr r3, [pc, #164] @ (8001be0 ) + 8001b3c: 60bb str r3, [r7, #8] /* Check DMA configuration, depending on MultiMode set or not */ if (READ_BIT(tmpADC_Common->CCR, ADC_CCR_MULTI) == ADC_MODE_INDEPENDENT) - 8001b06: 68bb ldr r3, [r7, #8] - 8001b08: 689b ldr r3, [r3, #8] - 8001b0a: f003 031f and.w r3, r3, #31 - 8001b0e: 2b00 cmp r3, #0 - 8001b10: d109 bne.n 8001b26 + 8001b3e: 68bb ldr r3, [r7, #8] + 8001b40: 689b ldr r3, [r3, #8] + 8001b42: f003 031f and.w r3, r3, #31 + 8001b46: 2b00 cmp r3, #0 + 8001b48: d109 bne.n 8001b5e { if (HAL_IS_BIT_SET(hadc->Instance->CFGR, ADC_CFGR_DMAEN)) - 8001b12: 687b ldr r3, [r7, #4] - 8001b14: 681b ldr r3, [r3, #0] - 8001b16: 68db ldr r3, [r3, #12] - 8001b18: f003 0301 and.w r3, r3, #1 - 8001b1c: 2b01 cmp r3, #1 - 8001b1e: d10a bne.n 8001b36 + 8001b4a: 687b ldr r3, [r7, #4] + 8001b4c: 681b ldr r3, [r3, #0] + 8001b4e: 68db ldr r3, [r3, #12] + 8001b50: f003 0301 and.w r3, r3, #1 + 8001b54: 2b01 cmp r3, #1 + 8001b56: d10a bne.n 8001b6e { overrun_error = 1U; - 8001b20: 2301 movs r3, #1 - 8001b22: 61fb str r3, [r7, #28] - 8001b24: e007 b.n 8001b36 + 8001b58: 2301 movs r3, #1 + 8001b5a: 61fb str r3, [r7, #28] + 8001b5c: e007 b.n 8001b6e } } else { /* MultiMode is enabled, Common Control Register MDMA bits must be checked */ if (READ_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA) != RESET) - 8001b26: 68bb ldr r3, [r7, #8] - 8001b28: 689b ldr r3, [r3, #8] - 8001b2a: f403 4340 and.w r3, r3, #49152 @ 0xc000 - 8001b2e: 2b00 cmp r3, #0 - 8001b30: d001 beq.n 8001b36 + 8001b5e: 68bb ldr r3, [r7, #8] + 8001b60: 689b ldr r3, [r3, #8] + 8001b62: f403 4340 and.w r3, r3, #49152 @ 0xc000 + 8001b66: 2b00 cmp r3, #0 + 8001b68: d001 beq.n 8001b6e { overrun_error = 1U; - 8001b32: 2301 movs r3, #1 - 8001b34: 61fb str r3, [r7, #28] + 8001b6a: 2301 movs r3, #1 + 8001b6c: 61fb str r3, [r7, #28] } } } if (overrun_error == 1U) - 8001b36: 69fb ldr r3, [r7, #28] - 8001b38: 2b01 cmp r3, #1 - 8001b3a: d10e bne.n 8001b5a + 8001b6e: 69fb ldr r3, [r7, #28] + 8001b70: 2b01 cmp r3, #1 + 8001b72: d10e bne.n 8001b92 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR); - 8001b3c: 687b ldr r3, [r7, #4] - 8001b3e: 6c1b ldr r3, [r3, #64] @ 0x40 - 8001b40: f443 6280 orr.w r2, r3, #1024 @ 0x400 - 8001b44: 687b ldr r3, [r7, #4] - 8001b46: 641a str r2, [r3, #64] @ 0x40 + 8001b74: 687b ldr r3, [r7, #4] + 8001b76: 6c1b ldr r3, [r3, #64] @ 0x40 + 8001b78: f443 6280 orr.w r2, r3, #1024 @ 0x400 + 8001b7c: 687b ldr r3, [r7, #4] + 8001b7e: 641a str r2, [r3, #64] @ 0x40 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); - 8001b48: 687b ldr r3, [r7, #4] - 8001b4a: 6c5b ldr r3, [r3, #68] @ 0x44 - 8001b4c: f043 0202 orr.w r2, r3, #2 - 8001b50: 687b ldr r3, [r7, #4] - 8001b52: 645a str r2, [r3, #68] @ 0x44 + 8001b80: 687b ldr r3, [r7, #4] + 8001b82: 6c5b ldr r3, [r3, #68] @ 0x44 + 8001b84: f043 0202 orr.w r2, r3, #2 + 8001b88: 687b ldr r3, [r7, #4] + 8001b8a: 645a str r2, [r3, #68] @ 0x44 /* Error callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ErrorCallback(hadc); #else HAL_ADC_ErrorCallback(hadc); - 8001b54: 6878 ldr r0, [r7, #4] - 8001b56: f7ff fc93 bl 8001480 + 8001b8c: 6878 ldr r0, [r7, #4] + 8001b8e: f7ff fc93 bl 80014b8 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } /* Clear the Overrun flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); - 8001b5a: 687b ldr r3, [r7, #4] - 8001b5c: 681b ldr r3, [r3, #0] - 8001b5e: 2210 movs r2, #16 - 8001b60: 601a str r2, [r3, #0] + 8001b92: 687b ldr r3, [r7, #4] + 8001b94: 681b ldr r3, [r3, #0] + 8001b96: 2210 movs r2, #16 + 8001b98: 601a str r2, [r3, #0] } /* ========== Check Injected context queue overflow flag ========== */ if(((tmp_isr & ADC_FLAG_JQOVF) == ADC_FLAG_JQOVF) && ((tmp_ier & ADC_IT_JQOVF) == ADC_IT_JQOVF)) - 8001b62: 693b ldr r3, [r7, #16] - 8001b64: f403 6380 and.w r3, r3, #1024 @ 0x400 - 8001b68: 2b00 cmp r3, #0 - 8001b6a: d018 beq.n 8001b9e - 8001b6c: 68fb ldr r3, [r7, #12] - 8001b6e: f403 6380 and.w r3, r3, #1024 @ 0x400 - 8001b72: 2b00 cmp r3, #0 - 8001b74: d013 beq.n 8001b9e + 8001b9a: 693b ldr r3, [r7, #16] + 8001b9c: f403 6380 and.w r3, r3, #1024 @ 0x400 + 8001ba0: 2b00 cmp r3, #0 + 8001ba2: d018 beq.n 8001bd6 + 8001ba4: 68fb ldr r3, [r7, #12] + 8001ba6: f403 6380 and.w r3, r3, #1024 @ 0x400 + 8001baa: 2b00 cmp r3, #0 + 8001bac: d013 beq.n 8001bd6 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF); - 8001b76: 687b ldr r3, [r7, #4] - 8001b78: 6c1b ldr r3, [r3, #64] @ 0x40 - 8001b7a: f443 4280 orr.w r2, r3, #16384 @ 0x4000 - 8001b7e: 687b ldr r3, [r7, #4] - 8001b80: 641a str r2, [r3, #64] @ 0x40 + 8001bae: 687b ldr r3, [r7, #4] + 8001bb0: 6c1b ldr r3, [r3, #64] @ 0x40 + 8001bb2: f443 4280 orr.w r2, r3, #16384 @ 0x4000 + 8001bb6: 687b ldr r3, [r7, #4] + 8001bb8: 641a str r2, [r3, #64] @ 0x40 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF); - 8001b82: 687b ldr r3, [r7, #4] - 8001b84: 6c5b ldr r3, [r3, #68] @ 0x44 - 8001b86: f043 0208 orr.w r2, r3, #8 - 8001b8a: 687b ldr r3, [r7, #4] - 8001b8c: 645a str r2, [r3, #68] @ 0x44 + 8001bba: 687b ldr r3, [r7, #4] + 8001bbc: 6c5b ldr r3, [r3, #68] @ 0x44 + 8001bbe: f043 0208 orr.w r2, r3, #8 + 8001bc2: 687b ldr r3, [r7, #4] + 8001bc4: 645a str r2, [r3, #68] @ 0x44 /* Clear the Injected context queue overflow flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF); - 8001b8e: 687b ldr r3, [r7, #4] - 8001b90: 681b ldr r3, [r3, #0] - 8001b92: f44f 6280 mov.w r2, #1024 @ 0x400 - 8001b96: 601a str r2, [r3, #0] + 8001bc6: 687b ldr r3, [r7, #4] + 8001bc8: 681b ldr r3, [r3, #0] + 8001bca: f44f 6280 mov.w r2, #1024 @ 0x400 + 8001bce: 601a str r2, [r3, #0] /* Error callback */ HAL_ADCEx_InjectedQueueOverflowCallback(hadc); - 8001b98: 6878 ldr r0, [r7, #4] - 8001b9a: f000 f811 bl 8001bc0 + 8001bd0: 6878 ldr r0, [r7, #4] + 8001bd2: f000 f811 bl 8001bf8 } } - 8001b9e: bf00 nop - 8001ba0: 3720 adds r7, #32 - 8001ba2: 46bd mov sp, r7 - 8001ba4: bd80 pop {r7, pc} - 8001ba6: bf00 nop - 8001ba8: 50000300 .word 0x50000300 + 8001bd6: bf00 nop + 8001bd8: 3720 adds r7, #32 + 8001bda: 46bd mov sp, r7 + 8001bdc: bd80 pop {r7, pc} + 8001bde: bf00 nop + 8001be0: 50000300 .word 0x50000300 -08001bac : +08001be4 : * @brief Injected conversion complete callback in non blocking mode * @param hadc ADC handle * @retval None */ __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc) { - 8001bac: b480 push {r7} - 8001bae: b083 sub sp, #12 - 8001bb0: af00 add r7, sp, #0 - 8001bb2: 6078 str r0, [r7, #4] + 8001be4: b480 push {r7} + 8001be6: b083 sub sp, #12 + 8001be8: af00 add r7, sp, #0 + 8001bea: 6078 str r0, [r7, #4] UNUSED(hadc); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_ADCEx_InjectedConvCpltCallback could be implemented in the user file */ } - 8001bb4: bf00 nop - 8001bb6: 370c adds r7, #12 - 8001bb8: 46bd mov sp, r7 - 8001bba: f85d 7b04 ldr.w r7, [sp], #4 - 8001bbe: 4770 bx lr + 8001bec: bf00 nop + 8001bee: 370c adds r7, #12 + 8001bf0: 46bd mov sp, r7 + 8001bf2: f85d 7b04 ldr.w r7, [sp], #4 + 8001bf6: 4770 bx lr -08001bc0 : +08001bf8 : contexts). * @param hadc ADC handle * @retval None */ __weak void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef* hadc) { - 8001bc0: b480 push {r7} - 8001bc2: b083 sub sp, #12 - 8001bc4: af00 add r7, sp, #0 - 8001bc6: 6078 str r0, [r7, #4] + 8001bf8: b480 push {r7} + 8001bfa: b083 sub sp, #12 + 8001bfc: af00 add r7, sp, #0 + 8001bfe: 6078 str r0, [r7, #4] /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADCEx_InjectedQueueOverflowCallback must be implemented in the user file. */ } - 8001bc8: bf00 nop - 8001bca: 370c adds r7, #12 - 8001bcc: 46bd mov sp, r7 - 8001bce: f85d 7b04 ldr.w r7, [sp], #4 - 8001bd2: 4770 bx lr + 8001c00: bf00 nop + 8001c02: 370c adds r7, #12 + 8001c04: 46bd mov sp, r7 + 8001c06: f85d 7b04 ldr.w r7, [sp], #4 + 8001c0a: 4770 bx lr -08001bd4 : +08001c0c : * @brief Analog watchdog 2 callback in non blocking mode. * @param hadc ADC handle * @retval None */ __weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef* hadc) { - 8001bd4: b480 push {r7} - 8001bd6: b083 sub sp, #12 - 8001bd8: af00 add r7, sp, #0 - 8001bda: 6078 str r0, [r7, #4] + 8001c0c: b480 push {r7} + 8001c0e: b083 sub sp, #12 + 8001c10: af00 add r7, sp, #0 + 8001c12: 6078 str r0, [r7, #4] UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_LevelOoutOfWindow2Callback must be implemented in the user file. */ } - 8001bdc: bf00 nop - 8001bde: 370c adds r7, #12 - 8001be0: 46bd mov sp, r7 - 8001be2: f85d 7b04 ldr.w r7, [sp], #4 - 8001be6: 4770 bx lr + 8001c14: bf00 nop + 8001c16: 370c adds r7, #12 + 8001c18: 46bd mov sp, r7 + 8001c1a: f85d 7b04 ldr.w r7, [sp], #4 + 8001c1e: 4770 bx lr -08001be8 : +08001c20 : * @brief Analog watchdog 3 callback in non blocking mode. * @param hadc ADC handle * @retval None */ __weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef* hadc) { - 8001be8: b480 push {r7} - 8001bea: b083 sub sp, #12 - 8001bec: af00 add r7, sp, #0 - 8001bee: 6078 str r0, [r7, #4] + 8001c20: b480 push {r7} + 8001c22: b083 sub sp, #12 + 8001c24: af00 add r7, sp, #0 + 8001c26: 6078 str r0, [r7, #4] UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_LevelOoutOfWindow3Callback must be implemented in the user file. */ } - 8001bf0: bf00 nop - 8001bf2: 370c adds r7, #12 - 8001bf4: 46bd mov sp, r7 - 8001bf6: f85d 7b04 ldr.w r7, [sp], #4 - 8001bfa: 4770 bx lr + 8001c28: bf00 nop + 8001c2a: 370c adds r7, #12 + 8001c2c: 46bd mov sp, r7 + 8001c2e: f85d 7b04 ldr.w r7, [sp], #4 + 8001c32: 4770 bx lr -08001bfc : +08001c34 : * @param hadc ADC handle * @param sConfig Structure ADC channel for regular group. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) { - 8001bfc: b480 push {r7} - 8001bfe: b09b sub sp, #108 @ 0x6c - 8001c00: af00 add r7, sp, #0 - 8001c02: 6078 str r0, [r7, #4] - 8001c04: 6039 str r1, [r7, #0] + 8001c34: b480 push {r7} + 8001c36: b09b sub sp, #108 @ 0x6c + 8001c38: af00 add r7, sp, #0 + 8001c3a: 6078 str r0, [r7, #4] + 8001c3c: 6039 str r1, [r7, #0] HAL_StatusTypeDef tmp_hal_status = HAL_OK; - 8001c06: 2300 movs r3, #0 - 8001c08: f887 3067 strb.w r3, [r7, #103] @ 0x67 + 8001c3e: 2300 movs r3, #0 + 8001c40: f887 3067 strb.w r3, [r7, #103] @ 0x67 ADC_Common_TypeDef *tmpADC_Common; ADC_HandleTypeDef tmphadcSharingSameCommonRegister; uint32_t tmpOffsetShifted; __IO uint32_t wait_loop_index = 0U; - 8001c0c: 2300 movs r3, #0 - 8001c0e: 60bb str r3, [r7, #8] + 8001c44: 2300 movs r3, #0 + 8001c46: 60bb str r3, [r7, #8] { assert_param(IS_ADC_DIFF_CHANNEL(sConfig->Channel)); } /* Process locked */ __HAL_LOCK(hadc); - 8001c10: 687b ldr r3, [r7, #4] - 8001c12: f893 303c ldrb.w r3, [r3, #60] @ 0x3c - 8001c16: 2b01 cmp r3, #1 - 8001c18: d101 bne.n 8001c1e - 8001c1a: 2302 movs r3, #2 - 8001c1c: e2a1 b.n 8002162 - 8001c1e: 687b ldr r3, [r7, #4] - 8001c20: 2201 movs r2, #1 - 8001c22: f883 203c strb.w r2, [r3, #60] @ 0x3c + 8001c48: 687b ldr r3, [r7, #4] + 8001c4a: f893 303c ldrb.w r3, [r3, #60] @ 0x3c + 8001c4e: 2b01 cmp r3, #1 + 8001c50: d101 bne.n 8001c56 + 8001c52: 2302 movs r3, #2 + 8001c54: e2a1 b.n 800219a + 8001c56: 687b ldr r3, [r7, #4] + 8001c58: 2201 movs r2, #1 + 8001c5a: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - Channel number */ /* - Channel rank */ if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) - 8001c26: 687b ldr r3, [r7, #4] - 8001c28: 681b ldr r3, [r3, #0] - 8001c2a: 689b ldr r3, [r3, #8] - 8001c2c: f003 0304 and.w r3, r3, #4 - 8001c30: 2b00 cmp r3, #0 - 8001c32: f040 8285 bne.w 8002140 + 8001c5e: 687b ldr r3, [r7, #4] + 8001c60: 681b ldr r3, [r3, #0] + 8001c62: 689b ldr r3, [r3, #8] + 8001c64: f003 0304 and.w r3, r3, #4 + 8001c68: 2b00 cmp r3, #0 + 8001c6a: f040 8285 bne.w 8002178 { /* Regular sequence configuration */ /* For Rank 1 to 4U */ if (sConfig->Rank < 5U) - 8001c36: 683b ldr r3, [r7, #0] - 8001c38: 685b ldr r3, [r3, #4] - 8001c3a: 2b04 cmp r3, #4 - 8001c3c: d81c bhi.n 8001c78 + 8001c6e: 683b ldr r3, [r7, #0] + 8001c70: 685b ldr r3, [r3, #4] + 8001c72: 2b04 cmp r3, #4 + 8001c74: d81c bhi.n 8001cb0 { MODIFY_REG(hadc->Instance->SQR1, - 8001c3e: 687b ldr r3, [r7, #4] - 8001c40: 681b ldr r3, [r3, #0] - 8001c42: 6b19 ldr r1, [r3, #48] @ 0x30 - 8001c44: 683b ldr r3, [r7, #0] - 8001c46: 685a ldr r2, [r3, #4] - 8001c48: 4613 mov r3, r2 - 8001c4a: 005b lsls r3, r3, #1 - 8001c4c: 4413 add r3, r2 - 8001c4e: 005b lsls r3, r3, #1 - 8001c50: 461a mov r2, r3 - 8001c52: 231f movs r3, #31 - 8001c54: 4093 lsls r3, r2 - 8001c56: 43db mvns r3, r3 - 8001c58: 4019 ands r1, r3 - 8001c5a: 683b ldr r3, [r7, #0] - 8001c5c: 6818 ldr r0, [r3, #0] - 8001c5e: 683b ldr r3, [r7, #0] - 8001c60: 685a ldr r2, [r3, #4] - 8001c62: 4613 mov r3, r2 - 8001c64: 005b lsls r3, r3, #1 - 8001c66: 4413 add r3, r2 - 8001c68: 005b lsls r3, r3, #1 - 8001c6a: fa00 f203 lsl.w r2, r0, r3 - 8001c6e: 687b ldr r3, [r7, #4] - 8001c70: 681b ldr r3, [r3, #0] - 8001c72: 430a orrs r2, r1 - 8001c74: 631a str r2, [r3, #48] @ 0x30 - 8001c76: e063 b.n 8001d40 + 8001c76: 687b ldr r3, [r7, #4] + 8001c78: 681b ldr r3, [r3, #0] + 8001c7a: 6b19 ldr r1, [r3, #48] @ 0x30 + 8001c7c: 683b ldr r3, [r7, #0] + 8001c7e: 685a ldr r2, [r3, #4] + 8001c80: 4613 mov r3, r2 + 8001c82: 005b lsls r3, r3, #1 + 8001c84: 4413 add r3, r2 + 8001c86: 005b lsls r3, r3, #1 + 8001c88: 461a mov r2, r3 + 8001c8a: 231f movs r3, #31 + 8001c8c: 4093 lsls r3, r2 + 8001c8e: 43db mvns r3, r3 + 8001c90: 4019 ands r1, r3 + 8001c92: 683b ldr r3, [r7, #0] + 8001c94: 6818 ldr r0, [r3, #0] + 8001c96: 683b ldr r3, [r7, #0] + 8001c98: 685a ldr r2, [r3, #4] + 8001c9a: 4613 mov r3, r2 + 8001c9c: 005b lsls r3, r3, #1 + 8001c9e: 4413 add r3, r2 + 8001ca0: 005b lsls r3, r3, #1 + 8001ca2: fa00 f203 lsl.w r2, r0, r3 + 8001ca6: 687b ldr r3, [r7, #4] + 8001ca8: 681b ldr r3, [r3, #0] + 8001caa: 430a orrs r2, r1 + 8001cac: 631a str r2, [r3, #48] @ 0x30 + 8001cae: e063 b.n 8001d78 ADC_SQR1_RK(ADC_SQR2_SQ5, sConfig->Rank) , ADC_SQR1_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 5 to 9U */ else if (sConfig->Rank < 10U) - 8001c78: 683b ldr r3, [r7, #0] - 8001c7a: 685b ldr r3, [r3, #4] - 8001c7c: 2b09 cmp r3, #9 - 8001c7e: d81e bhi.n 8001cbe + 8001cb0: 683b ldr r3, [r7, #0] + 8001cb2: 685b ldr r3, [r3, #4] + 8001cb4: 2b09 cmp r3, #9 + 8001cb6: d81e bhi.n 8001cf6 { MODIFY_REG(hadc->Instance->SQR2, - 8001c80: 687b ldr r3, [r7, #4] - 8001c82: 681b ldr r3, [r3, #0] - 8001c84: 6b59 ldr r1, [r3, #52] @ 0x34 - 8001c86: 683b ldr r3, [r7, #0] - 8001c88: 685a ldr r2, [r3, #4] - 8001c8a: 4613 mov r3, r2 - 8001c8c: 005b lsls r3, r3, #1 - 8001c8e: 4413 add r3, r2 - 8001c90: 005b lsls r3, r3, #1 - 8001c92: 3b1e subs r3, #30 - 8001c94: 221f movs r2, #31 - 8001c96: fa02 f303 lsl.w r3, r2, r3 - 8001c9a: 43db mvns r3, r3 - 8001c9c: 4019 ands r1, r3 - 8001c9e: 683b ldr r3, [r7, #0] - 8001ca0: 6818 ldr r0, [r3, #0] - 8001ca2: 683b ldr r3, [r7, #0] - 8001ca4: 685a ldr r2, [r3, #4] - 8001ca6: 4613 mov r3, r2 - 8001ca8: 005b lsls r3, r3, #1 - 8001caa: 4413 add r3, r2 - 8001cac: 005b lsls r3, r3, #1 - 8001cae: 3b1e subs r3, #30 - 8001cb0: fa00 f203 lsl.w r2, r0, r3 - 8001cb4: 687b ldr r3, [r7, #4] - 8001cb6: 681b ldr r3, [r3, #0] - 8001cb8: 430a orrs r2, r1 - 8001cba: 635a str r2, [r3, #52] @ 0x34 - 8001cbc: e040 b.n 8001d40 + 8001cb8: 687b ldr r3, [r7, #4] + 8001cba: 681b ldr r3, [r3, #0] + 8001cbc: 6b59 ldr r1, [r3, #52] @ 0x34 + 8001cbe: 683b ldr r3, [r7, #0] + 8001cc0: 685a ldr r2, [r3, #4] + 8001cc2: 4613 mov r3, r2 + 8001cc4: 005b lsls r3, r3, #1 + 8001cc6: 4413 add r3, r2 + 8001cc8: 005b lsls r3, r3, #1 + 8001cca: 3b1e subs r3, #30 + 8001ccc: 221f movs r2, #31 + 8001cce: fa02 f303 lsl.w r3, r2, r3 + 8001cd2: 43db mvns r3, r3 + 8001cd4: 4019 ands r1, r3 + 8001cd6: 683b ldr r3, [r7, #0] + 8001cd8: 6818 ldr r0, [r3, #0] + 8001cda: 683b ldr r3, [r7, #0] + 8001cdc: 685a ldr r2, [r3, #4] + 8001cde: 4613 mov r3, r2 + 8001ce0: 005b lsls r3, r3, #1 + 8001ce2: 4413 add r3, r2 + 8001ce4: 005b lsls r3, r3, #1 + 8001ce6: 3b1e subs r3, #30 + 8001ce8: fa00 f203 lsl.w r2, r0, r3 + 8001cec: 687b ldr r3, [r7, #4] + 8001cee: 681b ldr r3, [r3, #0] + 8001cf0: 430a orrs r2, r1 + 8001cf2: 635a str r2, [r3, #52] @ 0x34 + 8001cf4: e040 b.n 8001d78 ADC_SQR2_RK(ADC_SQR2_SQ5, sConfig->Rank) , ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 10 to 14U */ else if (sConfig->Rank < 15U) - 8001cbe: 683b ldr r3, [r7, #0] - 8001cc0: 685b ldr r3, [r3, #4] - 8001cc2: 2b0e cmp r3, #14 - 8001cc4: d81e bhi.n 8001d04 + 8001cf6: 683b ldr r3, [r7, #0] + 8001cf8: 685b ldr r3, [r3, #4] + 8001cfa: 2b0e cmp r3, #14 + 8001cfc: d81e bhi.n 8001d3c { MODIFY_REG(hadc->Instance->SQR3 , - 8001cc6: 687b ldr r3, [r7, #4] - 8001cc8: 681b ldr r3, [r3, #0] - 8001cca: 6b99 ldr r1, [r3, #56] @ 0x38 - 8001ccc: 683b ldr r3, [r7, #0] - 8001cce: 685a ldr r2, [r3, #4] - 8001cd0: 4613 mov r3, r2 - 8001cd2: 005b lsls r3, r3, #1 - 8001cd4: 4413 add r3, r2 - 8001cd6: 005b lsls r3, r3, #1 - 8001cd8: 3b3c subs r3, #60 @ 0x3c - 8001cda: 221f movs r2, #31 - 8001cdc: fa02 f303 lsl.w r3, r2, r3 - 8001ce0: 43db mvns r3, r3 - 8001ce2: 4019 ands r1, r3 - 8001ce4: 683b ldr r3, [r7, #0] - 8001ce6: 6818 ldr r0, [r3, #0] - 8001ce8: 683b ldr r3, [r7, #0] - 8001cea: 685a ldr r2, [r3, #4] - 8001cec: 4613 mov r3, r2 - 8001cee: 005b lsls r3, r3, #1 - 8001cf0: 4413 add r3, r2 - 8001cf2: 005b lsls r3, r3, #1 - 8001cf4: 3b3c subs r3, #60 @ 0x3c - 8001cf6: fa00 f203 lsl.w r2, r0, r3 - 8001cfa: 687b ldr r3, [r7, #4] - 8001cfc: 681b ldr r3, [r3, #0] - 8001cfe: 430a orrs r2, r1 - 8001d00: 639a str r2, [r3, #56] @ 0x38 - 8001d02: e01d b.n 8001d40 + 8001cfe: 687b ldr r3, [r7, #4] + 8001d00: 681b ldr r3, [r3, #0] + 8001d02: 6b99 ldr r1, [r3, #56] @ 0x38 + 8001d04: 683b ldr r3, [r7, #0] + 8001d06: 685a ldr r2, [r3, #4] + 8001d08: 4613 mov r3, r2 + 8001d0a: 005b lsls r3, r3, #1 + 8001d0c: 4413 add r3, r2 + 8001d0e: 005b lsls r3, r3, #1 + 8001d10: 3b3c subs r3, #60 @ 0x3c + 8001d12: 221f movs r2, #31 + 8001d14: fa02 f303 lsl.w r3, r2, r3 + 8001d18: 43db mvns r3, r3 + 8001d1a: 4019 ands r1, r3 + 8001d1c: 683b ldr r3, [r7, #0] + 8001d1e: 6818 ldr r0, [r3, #0] + 8001d20: 683b ldr r3, [r7, #0] + 8001d22: 685a ldr r2, [r3, #4] + 8001d24: 4613 mov r3, r2 + 8001d26: 005b lsls r3, r3, #1 + 8001d28: 4413 add r3, r2 + 8001d2a: 005b lsls r3, r3, #1 + 8001d2c: 3b3c subs r3, #60 @ 0x3c + 8001d2e: fa00 f203 lsl.w r2, r0, r3 + 8001d32: 687b ldr r3, [r7, #4] + 8001d34: 681b ldr r3, [r3, #0] + 8001d36: 430a orrs r2, r1 + 8001d38: 639a str r2, [r3, #56] @ 0x38 + 8001d3a: e01d b.n 8001d78 ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 15 to 16U */ else { MODIFY_REG(hadc->Instance->SQR4 , - 8001d04: 687b ldr r3, [r7, #4] - 8001d06: 681b ldr r3, [r3, #0] - 8001d08: 6bd9 ldr r1, [r3, #60] @ 0x3c - 8001d0a: 683b ldr r3, [r7, #0] - 8001d0c: 685a ldr r2, [r3, #4] - 8001d0e: 4613 mov r3, r2 - 8001d10: 005b lsls r3, r3, #1 - 8001d12: 4413 add r3, r2 - 8001d14: 005b lsls r3, r3, #1 - 8001d16: 3b5a subs r3, #90 @ 0x5a - 8001d18: 221f movs r2, #31 - 8001d1a: fa02 f303 lsl.w r3, r2, r3 - 8001d1e: 43db mvns r3, r3 - 8001d20: 4019 ands r1, r3 - 8001d22: 683b ldr r3, [r7, #0] - 8001d24: 6818 ldr r0, [r3, #0] - 8001d26: 683b ldr r3, [r7, #0] - 8001d28: 685a ldr r2, [r3, #4] - 8001d2a: 4613 mov r3, r2 - 8001d2c: 005b lsls r3, r3, #1 - 8001d2e: 4413 add r3, r2 - 8001d30: 005b lsls r3, r3, #1 - 8001d32: 3b5a subs r3, #90 @ 0x5a - 8001d34: fa00 f203 lsl.w r2, r0, r3 - 8001d38: 687b ldr r3, [r7, #4] - 8001d3a: 681b ldr r3, [r3, #0] - 8001d3c: 430a orrs r2, r1 - 8001d3e: 63da str r2, [r3, #60] @ 0x3c + 8001d3c: 687b ldr r3, [r7, #4] + 8001d3e: 681b ldr r3, [r3, #0] + 8001d40: 6bd9 ldr r1, [r3, #60] @ 0x3c + 8001d42: 683b ldr r3, [r7, #0] + 8001d44: 685a ldr r2, [r3, #4] + 8001d46: 4613 mov r3, r2 + 8001d48: 005b lsls r3, r3, #1 + 8001d4a: 4413 add r3, r2 + 8001d4c: 005b lsls r3, r3, #1 + 8001d4e: 3b5a subs r3, #90 @ 0x5a + 8001d50: 221f movs r2, #31 + 8001d52: fa02 f303 lsl.w r3, r2, r3 + 8001d56: 43db mvns r3, r3 + 8001d58: 4019 ands r1, r3 + 8001d5a: 683b ldr r3, [r7, #0] + 8001d5c: 6818 ldr r0, [r3, #0] + 8001d5e: 683b ldr r3, [r7, #0] + 8001d60: 685a ldr r2, [r3, #4] + 8001d62: 4613 mov r3, r2 + 8001d64: 005b lsls r3, r3, #1 + 8001d66: 4413 add r3, r2 + 8001d68: 005b lsls r3, r3, #1 + 8001d6a: 3b5a subs r3, #90 @ 0x5a + 8001d6c: fa00 f203 lsl.w r2, r0, r3 + 8001d70: 687b ldr r3, [r7, #4] + 8001d72: 681b ldr r3, [r3, #0] + 8001d74: 430a orrs r2, r1 + 8001d76: 63da str r2, [r3, #60] @ 0x3c /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - Channel sampling time */ /* - Channel offset */ if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) - 8001d40: 687b ldr r3, [r7, #4] - 8001d42: 681b ldr r3, [r3, #0] - 8001d44: 689b ldr r3, [r3, #8] - 8001d46: f003 030c and.w r3, r3, #12 - 8001d4a: 2b00 cmp r3, #0 - 8001d4c: f040 80e5 bne.w 8001f1a + 8001d78: 687b ldr r3, [r7, #4] + 8001d7a: 681b ldr r3, [r3, #0] + 8001d7c: 689b ldr r3, [r3, #8] + 8001d7e: f003 030c and.w r3, r3, #12 + 8001d82: 2b00 cmp r3, #0 + 8001d84: f040 80e5 bne.w 8001f52 { /* Channel sampling time configuration */ /* For channels 10 to 18U */ if (sConfig->Channel >= ADC_CHANNEL_10) - 8001d50: 683b ldr r3, [r7, #0] - 8001d52: 681b ldr r3, [r3, #0] - 8001d54: 2b09 cmp r3, #9 - 8001d56: d91c bls.n 8001d92 + 8001d88: 683b ldr r3, [r7, #0] + 8001d8a: 681b ldr r3, [r3, #0] + 8001d8c: 2b09 cmp r3, #9 + 8001d8e: d91c bls.n 8001dca { MODIFY_REG(hadc->Instance->SMPR2 , - 8001d58: 687b ldr r3, [r7, #4] - 8001d5a: 681b ldr r3, [r3, #0] - 8001d5c: 6999 ldr r1, [r3, #24] - 8001d5e: 683b ldr r3, [r7, #0] - 8001d60: 681a ldr r2, [r3, #0] - 8001d62: 4613 mov r3, r2 - 8001d64: 005b lsls r3, r3, #1 - 8001d66: 4413 add r3, r2 - 8001d68: 3b1e subs r3, #30 - 8001d6a: 2207 movs r2, #7 - 8001d6c: fa02 f303 lsl.w r3, r2, r3 - 8001d70: 43db mvns r3, r3 - 8001d72: 4019 ands r1, r3 - 8001d74: 683b ldr r3, [r7, #0] - 8001d76: 6898 ldr r0, [r3, #8] - 8001d78: 683b ldr r3, [r7, #0] - 8001d7a: 681a ldr r2, [r3, #0] - 8001d7c: 4613 mov r3, r2 - 8001d7e: 005b lsls r3, r3, #1 - 8001d80: 4413 add r3, r2 - 8001d82: 3b1e subs r3, #30 - 8001d84: fa00 f203 lsl.w r2, r0, r3 - 8001d88: 687b ldr r3, [r7, #4] - 8001d8a: 681b ldr r3, [r3, #0] - 8001d8c: 430a orrs r2, r1 - 8001d8e: 619a str r2, [r3, #24] - 8001d90: e019 b.n 8001dc6 - ADC_SMPR2(ADC_SMPR2_SMP10, sConfig->Channel) , - ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) ); - } - else /* For channels 1 to 9U */ - { - MODIFY_REG(hadc->Instance->SMPR1 , - 8001d92: 687b ldr r3, [r7, #4] - 8001d94: 681b ldr r3, [r3, #0] - 8001d96: 6959 ldr r1, [r3, #20] - 8001d98: 683b ldr r3, [r7, #0] - 8001d9a: 681a ldr r2, [r3, #0] - 8001d9c: 4613 mov r3, r2 - 8001d9e: 005b lsls r3, r3, #1 - 8001da0: 4413 add r3, r2 + 8001d90: 687b ldr r3, [r7, #4] + 8001d92: 681b ldr r3, [r3, #0] + 8001d94: 6999 ldr r1, [r3, #24] + 8001d96: 683b ldr r3, [r7, #0] + 8001d98: 681a ldr r2, [r3, #0] + 8001d9a: 4613 mov r3, r2 + 8001d9c: 005b lsls r3, r3, #1 + 8001d9e: 4413 add r3, r2 + 8001da0: 3b1e subs r3, #30 8001da2: 2207 movs r2, #7 8001da4: fa02 f303 lsl.w r3, r2, r3 8001da8: 43db mvns r3, r3 @@ -5114,2195 +5107,2193 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf 8001db4: 4613 mov r3, r2 8001db6: 005b lsls r3, r3, #1 8001db8: 4413 add r3, r2 - 8001dba: fa00 f203 lsl.w r2, r0, r3 - 8001dbe: 687b ldr r3, [r7, #4] - 8001dc0: 681b ldr r3, [r3, #0] - 8001dc2: 430a orrs r2, r1 - 8001dc4: 615a str r2, [r3, #20] + 8001dba: 3b1e subs r3, #30 + 8001dbc: fa00 f203 lsl.w r2, r0, r3 + 8001dc0: 687b ldr r3, [r7, #4] + 8001dc2: 681b ldr r3, [r3, #0] + 8001dc4: 430a orrs r2, r1 + 8001dc6: 619a str r2, [r3, #24] + 8001dc8: e019 b.n 8001dfe + ADC_SMPR2(ADC_SMPR2_SMP10, sConfig->Channel) , + ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) ); + } + else /* For channels 1 to 9U */ + { + MODIFY_REG(hadc->Instance->SMPR1 , + 8001dca: 687b ldr r3, [r7, #4] + 8001dcc: 681b ldr r3, [r3, #0] + 8001dce: 6959 ldr r1, [r3, #20] + 8001dd0: 683b ldr r3, [r7, #0] + 8001dd2: 681a ldr r2, [r3, #0] + 8001dd4: 4613 mov r3, r2 + 8001dd6: 005b lsls r3, r3, #1 + 8001dd8: 4413 add r3, r2 + 8001dda: 2207 movs r2, #7 + 8001ddc: fa02 f303 lsl.w r3, r2, r3 + 8001de0: 43db mvns r3, r3 + 8001de2: 4019 ands r1, r3 + 8001de4: 683b ldr r3, [r7, #0] + 8001de6: 6898 ldr r0, [r3, #8] + 8001de8: 683b ldr r3, [r7, #0] + 8001dea: 681a ldr r2, [r3, #0] + 8001dec: 4613 mov r3, r2 + 8001dee: 005b lsls r3, r3, #1 + 8001df0: 4413 add r3, r2 + 8001df2: fa00 f203 lsl.w r2, r0, r3 + 8001df6: 687b ldr r3, [r7, #4] + 8001df8: 681b ldr r3, [r3, #0] + 8001dfa: 430a orrs r2, r1 + 8001dfc: 615a str r2, [r3, #20] /* Configure the offset: offset enable/disable, channel, offset value */ /* Shift the offset in function of the selected ADC resolution. */ /* Offset has to be left-aligned on bit 11U, the LSB (right bits) are set */ /* to 0. */ tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfig->Offset); - 8001dc6: 683b ldr r3, [r7, #0] - 8001dc8: 695a ldr r2, [r3, #20] - 8001dca: 687b ldr r3, [r7, #4] - 8001dcc: 681b ldr r3, [r3, #0] - 8001dce: 68db ldr r3, [r3, #12] - 8001dd0: 08db lsrs r3, r3, #3 - 8001dd2: f003 0303 and.w r3, r3, #3 - 8001dd6: 005b lsls r3, r3, #1 - 8001dd8: fa02 f303 lsl.w r3, r2, r3 - 8001ddc: 663b str r3, [r7, #96] @ 0x60 + 8001dfe: 683b ldr r3, [r7, #0] + 8001e00: 695a ldr r2, [r3, #20] + 8001e02: 687b ldr r3, [r7, #4] + 8001e04: 681b ldr r3, [r3, #0] + 8001e06: 68db ldr r3, [r3, #12] + 8001e08: 08db lsrs r3, r3, #3 + 8001e0a: f003 0303 and.w r3, r3, #3 + 8001e0e: 005b lsls r3, r3, #1 + 8001e10: fa02 f303 lsl.w r3, r2, r3 + 8001e14: 663b str r3, [r7, #96] @ 0x60 /* Configure the selected offset register: */ /* - Enable offset */ /* - Set channel number */ /* - Set offset value */ switch (sConfig->OffsetNumber) - 8001dde: 683b ldr r3, [r7, #0] - 8001de0: 691b ldr r3, [r3, #16] - 8001de2: 3b01 subs r3, #1 - 8001de4: 2b03 cmp r3, #3 - 8001de6: d84f bhi.n 8001e88 - 8001de8: a201 add r2, pc, #4 @ (adr r2, 8001df0 ) - 8001dea: f852 f023 ldr.w pc, [r2, r3, lsl #2] - 8001dee: bf00 nop - 8001df0: 08001e01 .word 0x08001e01 - 8001df4: 08001e23 .word 0x08001e23 - 8001df8: 08001e45 .word 0x08001e45 - 8001dfc: 08001e67 .word 0x08001e67 + 8001e16: 683b ldr r3, [r7, #0] + 8001e18: 691b ldr r3, [r3, #16] + 8001e1a: 3b01 subs r3, #1 + 8001e1c: 2b03 cmp r3, #3 + 8001e1e: d84f bhi.n 8001ec0 + 8001e20: a201 add r2, pc, #4 @ (adr r2, 8001e28 ) + 8001e22: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8001e26: bf00 nop + 8001e28: 08001e39 .word 0x08001e39 + 8001e2c: 08001e5b .word 0x08001e5b + 8001e30: 08001e7d .word 0x08001e7d + 8001e34: 08001e9f .word 0x08001e9f { case ADC_OFFSET_1: /* Configure offset register 1U */ MODIFY_REG(hadc->Instance->OFR1 , - 8001e00: 687b ldr r3, [r7, #4] - 8001e02: 681b ldr r3, [r3, #0] - 8001e04: 6e1a ldr r2, [r3, #96] @ 0x60 - 8001e06: 4b9c ldr r3, [pc, #624] @ (8002078 ) - 8001e08: 4013 ands r3, r2 - 8001e0a: 683a ldr r2, [r7, #0] - 8001e0c: 6812 ldr r2, [r2, #0] - 8001e0e: 0691 lsls r1, r2, #26 - 8001e10: 6e3a ldr r2, [r7, #96] @ 0x60 - 8001e12: 430a orrs r2, r1 - 8001e14: 431a orrs r2, r3 - 8001e16: 687b ldr r3, [r7, #4] - 8001e18: 681b ldr r3, [r3, #0] - 8001e1a: f042 4200 orr.w r2, r2, #2147483648 @ 0x80000000 - 8001e1e: 661a str r2, [r3, #96] @ 0x60 + 8001e38: 687b ldr r3, [r7, #4] + 8001e3a: 681b ldr r3, [r3, #0] + 8001e3c: 6e1a ldr r2, [r3, #96] @ 0x60 + 8001e3e: 4b9c ldr r3, [pc, #624] @ (80020b0 ) + 8001e40: 4013 ands r3, r2 + 8001e42: 683a ldr r2, [r7, #0] + 8001e44: 6812 ldr r2, [r2, #0] + 8001e46: 0691 lsls r1, r2, #26 + 8001e48: 6e3a ldr r2, [r7, #96] @ 0x60 + 8001e4a: 430a orrs r2, r1 + 8001e4c: 431a orrs r2, r3 + 8001e4e: 687b ldr r3, [r7, #4] + 8001e50: 681b ldr r3, [r3, #0] + 8001e52: f042 4200 orr.w r2, r2, #2147483648 @ 0x80000000 + 8001e56: 661a str r2, [r3, #96] @ 0x60 ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1 , ADC_OFR1_OFFSET1_EN | ADC_OFR_CHANNEL(sConfig->Channel) | tmpOffsetShifted ); break; - 8001e20: e07b b.n 8001f1a + 8001e58: e07b b.n 8001f52 case ADC_OFFSET_2: /* Configure offset register 2U */ MODIFY_REG(hadc->Instance->OFR2 , - 8001e22: 687b ldr r3, [r7, #4] - 8001e24: 681b ldr r3, [r3, #0] - 8001e26: 6e5a ldr r2, [r3, #100] @ 0x64 - 8001e28: 4b93 ldr r3, [pc, #588] @ (8002078 ) - 8001e2a: 4013 ands r3, r2 - 8001e2c: 683a ldr r2, [r7, #0] - 8001e2e: 6812 ldr r2, [r2, #0] - 8001e30: 0691 lsls r1, r2, #26 - 8001e32: 6e3a ldr r2, [r7, #96] @ 0x60 - 8001e34: 430a orrs r2, r1 - 8001e36: 431a orrs r2, r3 - 8001e38: 687b ldr r3, [r7, #4] - 8001e3a: 681b ldr r3, [r3, #0] - 8001e3c: f042 4200 orr.w r2, r2, #2147483648 @ 0x80000000 - 8001e40: 665a str r2, [r3, #100] @ 0x64 + 8001e5a: 687b ldr r3, [r7, #4] + 8001e5c: 681b ldr r3, [r3, #0] + 8001e5e: 6e5a ldr r2, [r3, #100] @ 0x64 + 8001e60: 4b93 ldr r3, [pc, #588] @ (80020b0 ) + 8001e62: 4013 ands r3, r2 + 8001e64: 683a ldr r2, [r7, #0] + 8001e66: 6812 ldr r2, [r2, #0] + 8001e68: 0691 lsls r1, r2, #26 + 8001e6a: 6e3a ldr r2, [r7, #96] @ 0x60 + 8001e6c: 430a orrs r2, r1 + 8001e6e: 431a orrs r2, r3 + 8001e70: 687b ldr r3, [r7, #4] + 8001e72: 681b ldr r3, [r3, #0] + 8001e74: f042 4200 orr.w r2, r2, #2147483648 @ 0x80000000 + 8001e78: 665a str r2, [r3, #100] @ 0x64 ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2 , ADC_OFR2_OFFSET2_EN | ADC_OFR_CHANNEL(sConfig->Channel) | tmpOffsetShifted ); break; - 8001e42: e06a b.n 8001f1a + 8001e7a: e06a b.n 8001f52 case ADC_OFFSET_3: /* Configure offset register 3U */ MODIFY_REG(hadc->Instance->OFR3 , - 8001e44: 687b ldr r3, [r7, #4] - 8001e46: 681b ldr r3, [r3, #0] - 8001e48: 6e9a ldr r2, [r3, #104] @ 0x68 - 8001e4a: 4b8b ldr r3, [pc, #556] @ (8002078 ) - 8001e4c: 4013 ands r3, r2 - 8001e4e: 683a ldr r2, [r7, #0] - 8001e50: 6812 ldr r2, [r2, #0] - 8001e52: 0691 lsls r1, r2, #26 - 8001e54: 6e3a ldr r2, [r7, #96] @ 0x60 - 8001e56: 430a orrs r2, r1 - 8001e58: 431a orrs r2, r3 - 8001e5a: 687b ldr r3, [r7, #4] - 8001e5c: 681b ldr r3, [r3, #0] - 8001e5e: f042 4200 orr.w r2, r2, #2147483648 @ 0x80000000 - 8001e62: 669a str r2, [r3, #104] @ 0x68 + 8001e7c: 687b ldr r3, [r7, #4] + 8001e7e: 681b ldr r3, [r3, #0] + 8001e80: 6e9a ldr r2, [r3, #104] @ 0x68 + 8001e82: 4b8b ldr r3, [pc, #556] @ (80020b0 ) + 8001e84: 4013 ands r3, r2 + 8001e86: 683a ldr r2, [r7, #0] + 8001e88: 6812 ldr r2, [r2, #0] + 8001e8a: 0691 lsls r1, r2, #26 + 8001e8c: 6e3a ldr r2, [r7, #96] @ 0x60 + 8001e8e: 430a orrs r2, r1 + 8001e90: 431a orrs r2, r3 + 8001e92: 687b ldr r3, [r7, #4] + 8001e94: 681b ldr r3, [r3, #0] + 8001e96: f042 4200 orr.w r2, r2, #2147483648 @ 0x80000000 + 8001e9a: 669a str r2, [r3, #104] @ 0x68 ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3 , ADC_OFR3_OFFSET3_EN | ADC_OFR_CHANNEL(sConfig->Channel) | tmpOffsetShifted ); break; - 8001e64: e059 b.n 8001f1a + 8001e9c: e059 b.n 8001f52 case ADC_OFFSET_4: /* Configure offset register 4U */ MODIFY_REG(hadc->Instance->OFR4 , - 8001e66: 687b ldr r3, [r7, #4] - 8001e68: 681b ldr r3, [r3, #0] - 8001e6a: 6eda ldr r2, [r3, #108] @ 0x6c - 8001e6c: 4b82 ldr r3, [pc, #520] @ (8002078 ) - 8001e6e: 4013 ands r3, r2 - 8001e70: 683a ldr r2, [r7, #0] - 8001e72: 6812 ldr r2, [r2, #0] - 8001e74: 0691 lsls r1, r2, #26 - 8001e76: 6e3a ldr r2, [r7, #96] @ 0x60 - 8001e78: 430a orrs r2, r1 - 8001e7a: 431a orrs r2, r3 - 8001e7c: 687b ldr r3, [r7, #4] - 8001e7e: 681b ldr r3, [r3, #0] - 8001e80: f042 4200 orr.w r2, r2, #2147483648 @ 0x80000000 - 8001e84: 66da str r2, [r3, #108] @ 0x6c + 8001e9e: 687b ldr r3, [r7, #4] + 8001ea0: 681b ldr r3, [r3, #0] + 8001ea2: 6eda ldr r2, [r3, #108] @ 0x6c + 8001ea4: 4b82 ldr r3, [pc, #520] @ (80020b0 ) + 8001ea6: 4013 ands r3, r2 + 8001ea8: 683a ldr r2, [r7, #0] + 8001eaa: 6812 ldr r2, [r2, #0] + 8001eac: 0691 lsls r1, r2, #26 + 8001eae: 6e3a ldr r2, [r7, #96] @ 0x60 + 8001eb0: 430a orrs r2, r1 + 8001eb2: 431a orrs r2, r3 + 8001eb4: 687b ldr r3, [r7, #4] + 8001eb6: 681b ldr r3, [r3, #0] + 8001eb8: f042 4200 orr.w r2, r2, #2147483648 @ 0x80000000 + 8001ebc: 66da str r2, [r3, #108] @ 0x6c ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4 , ADC_OFR4_OFFSET4_EN | ADC_OFR_CHANNEL(sConfig->Channel) | tmpOffsetShifted ); break; - 8001e86: e048 b.n 8001f1a + 8001ebe: e048 b.n 8001f52 /* Case ADC_OFFSET_NONE */ default : /* Scan OFR1, OFR2, OFR3, OFR4 to check if the selected channel is */ /* enabled. If this is the case, offset OFRx is disabled. */ if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) - 8001e88: 687b ldr r3, [r7, #4] - 8001e8a: 681b ldr r3, [r3, #0] - 8001e8c: 6e1b ldr r3, [r3, #96] @ 0x60 - 8001e8e: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 - 8001e92: 683b ldr r3, [r7, #0] - 8001e94: 681b ldr r3, [r3, #0] - 8001e96: 069b lsls r3, r3, #26 - 8001e98: 429a cmp r2, r3 - 8001e9a: d107 bne.n 8001eac + 8001ec0: 687b ldr r3, [r7, #4] + 8001ec2: 681b ldr r3, [r3, #0] + 8001ec4: 6e1b ldr r3, [r3, #96] @ 0x60 + 8001ec6: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 + 8001eca: 683b ldr r3, [r7, #0] + 8001ecc: 681b ldr r3, [r3, #0] + 8001ece: 069b lsls r3, r3, #26 + 8001ed0: 429a cmp r2, r3 + 8001ed2: d107 bne.n 8001ee4 { /* Disable offset OFR1*/ CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN); - 8001e9c: 687b ldr r3, [r7, #4] - 8001e9e: 681b ldr r3, [r3, #0] - 8001ea0: 6e1a ldr r2, [r3, #96] @ 0x60 - 8001ea2: 687b ldr r3, [r7, #4] - 8001ea4: 681b ldr r3, [r3, #0] - 8001ea6: f022 4200 bic.w r2, r2, #2147483648 @ 0x80000000 - 8001eaa: 661a str r2, [r3, #96] @ 0x60 + 8001ed4: 687b ldr r3, [r7, #4] + 8001ed6: 681b ldr r3, [r3, #0] + 8001ed8: 6e1a ldr r2, [r3, #96] @ 0x60 + 8001eda: 687b ldr r3, [r7, #4] + 8001edc: 681b ldr r3, [r3, #0] + 8001ede: f022 4200 bic.w r2, r2, #2147483648 @ 0x80000000 + 8001ee2: 661a str r2, [r3, #96] @ 0x60 } if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) - 8001eac: 687b ldr r3, [r7, #4] - 8001eae: 681b ldr r3, [r3, #0] - 8001eb0: 6e5b ldr r3, [r3, #100] @ 0x64 - 8001eb2: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 - 8001eb6: 683b ldr r3, [r7, #0] - 8001eb8: 681b ldr r3, [r3, #0] - 8001eba: 069b lsls r3, r3, #26 - 8001ebc: 429a cmp r2, r3 - 8001ebe: d107 bne.n 8001ed0 + 8001ee4: 687b ldr r3, [r7, #4] + 8001ee6: 681b ldr r3, [r3, #0] + 8001ee8: 6e5b ldr r3, [r3, #100] @ 0x64 + 8001eea: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 + 8001eee: 683b ldr r3, [r7, #0] + 8001ef0: 681b ldr r3, [r3, #0] + 8001ef2: 069b lsls r3, r3, #26 + 8001ef4: 429a cmp r2, r3 + 8001ef6: d107 bne.n 8001f08 { /* Disable offset OFR2*/ CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN); - 8001ec0: 687b ldr r3, [r7, #4] - 8001ec2: 681b ldr r3, [r3, #0] - 8001ec4: 6e5a ldr r2, [r3, #100] @ 0x64 - 8001ec6: 687b ldr r3, [r7, #4] - 8001ec8: 681b ldr r3, [r3, #0] - 8001eca: f022 4200 bic.w r2, r2, #2147483648 @ 0x80000000 - 8001ece: 665a str r2, [r3, #100] @ 0x64 + 8001ef8: 687b ldr r3, [r7, #4] + 8001efa: 681b ldr r3, [r3, #0] + 8001efc: 6e5a ldr r2, [r3, #100] @ 0x64 + 8001efe: 687b ldr r3, [r7, #4] + 8001f00: 681b ldr r3, [r3, #0] + 8001f02: f022 4200 bic.w r2, r2, #2147483648 @ 0x80000000 + 8001f06: 665a str r2, [r3, #100] @ 0x64 } if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) - 8001ed0: 687b ldr r3, [r7, #4] - 8001ed2: 681b ldr r3, [r3, #0] - 8001ed4: 6e9b ldr r3, [r3, #104] @ 0x68 - 8001ed6: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 - 8001eda: 683b ldr r3, [r7, #0] - 8001edc: 681b ldr r3, [r3, #0] - 8001ede: 069b lsls r3, r3, #26 - 8001ee0: 429a cmp r2, r3 - 8001ee2: d107 bne.n 8001ef4 + 8001f08: 687b ldr r3, [r7, #4] + 8001f0a: 681b ldr r3, [r3, #0] + 8001f0c: 6e9b ldr r3, [r3, #104] @ 0x68 + 8001f0e: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 + 8001f12: 683b ldr r3, [r7, #0] + 8001f14: 681b ldr r3, [r3, #0] + 8001f16: 069b lsls r3, r3, #26 + 8001f18: 429a cmp r2, r3 + 8001f1a: d107 bne.n 8001f2c { /* Disable offset OFR3*/ CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN); - 8001ee4: 687b ldr r3, [r7, #4] - 8001ee6: 681b ldr r3, [r3, #0] - 8001ee8: 6e9a ldr r2, [r3, #104] @ 0x68 - 8001eea: 687b ldr r3, [r7, #4] - 8001eec: 681b ldr r3, [r3, #0] - 8001eee: f022 4200 bic.w r2, r2, #2147483648 @ 0x80000000 - 8001ef2: 669a str r2, [r3, #104] @ 0x68 + 8001f1c: 687b ldr r3, [r7, #4] + 8001f1e: 681b ldr r3, [r3, #0] + 8001f20: 6e9a ldr r2, [r3, #104] @ 0x68 + 8001f22: 687b ldr r3, [r7, #4] + 8001f24: 681b ldr r3, [r3, #0] + 8001f26: f022 4200 bic.w r2, r2, #2147483648 @ 0x80000000 + 8001f2a: 669a str r2, [r3, #104] @ 0x68 } if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) - 8001ef4: 687b ldr r3, [r7, #4] - 8001ef6: 681b ldr r3, [r3, #0] - 8001ef8: 6edb ldr r3, [r3, #108] @ 0x6c - 8001efa: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 - 8001efe: 683b ldr r3, [r7, #0] - 8001f00: 681b ldr r3, [r3, #0] - 8001f02: 069b lsls r3, r3, #26 - 8001f04: 429a cmp r2, r3 - 8001f06: d107 bne.n 8001f18 + 8001f2c: 687b ldr r3, [r7, #4] + 8001f2e: 681b ldr r3, [r3, #0] + 8001f30: 6edb ldr r3, [r3, #108] @ 0x6c + 8001f32: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 + 8001f36: 683b ldr r3, [r7, #0] + 8001f38: 681b ldr r3, [r3, #0] + 8001f3a: 069b lsls r3, r3, #26 + 8001f3c: 429a cmp r2, r3 + 8001f3e: d107 bne.n 8001f50 { /* Disable offset OFR4*/ CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN); - 8001f08: 687b ldr r3, [r7, #4] - 8001f0a: 681b ldr r3, [r3, #0] - 8001f0c: 6eda ldr r2, [r3, #108] @ 0x6c - 8001f0e: 687b ldr r3, [r7, #4] - 8001f10: 681b ldr r3, [r3, #0] - 8001f12: f022 4200 bic.w r2, r2, #2147483648 @ 0x80000000 - 8001f16: 66da str r2, [r3, #108] @ 0x6c + 8001f40: 687b ldr r3, [r7, #4] + 8001f42: 681b ldr r3, [r3, #0] + 8001f44: 6eda ldr r2, [r3, #108] @ 0x6c + 8001f46: 687b ldr r3, [r7, #4] + 8001f48: 681b ldr r3, [r3, #0] + 8001f4a: f022 4200 bic.w r2, r2, #2147483648 @ 0x80000000 + 8001f4e: 66da str r2, [r3, #108] @ 0x6c } break; - 8001f18: bf00 nop + 8001f50: bf00 nop /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - Single or differential mode */ /* - Internal measurement channels: Vbat/VrefInt/TempSensor */ if (ADC_IS_ENABLE(hadc) == RESET) - 8001f1a: 687b ldr r3, [r7, #4] - 8001f1c: 681b ldr r3, [r3, #0] - 8001f1e: 689b ldr r3, [r3, #8] - 8001f20: f003 0303 and.w r3, r3, #3 - 8001f24: 2b01 cmp r3, #1 - 8001f26: d108 bne.n 8001f3a - 8001f28: 687b ldr r3, [r7, #4] - 8001f2a: 681b ldr r3, [r3, #0] - 8001f2c: 681b ldr r3, [r3, #0] - 8001f2e: f003 0301 and.w r3, r3, #1 - 8001f32: 2b01 cmp r3, #1 - 8001f34: d101 bne.n 8001f3a - 8001f36: 2301 movs r3, #1 - 8001f38: e000 b.n 8001f3c - 8001f3a: 2300 movs r3, #0 - 8001f3c: 2b00 cmp r3, #0 - 8001f3e: f040 810a bne.w 8002156 + 8001f52: 687b ldr r3, [r7, #4] + 8001f54: 681b ldr r3, [r3, #0] + 8001f56: 689b ldr r3, [r3, #8] + 8001f58: f003 0303 and.w r3, r3, #3 + 8001f5c: 2b01 cmp r3, #1 + 8001f5e: d108 bne.n 8001f72 + 8001f60: 687b ldr r3, [r7, #4] + 8001f62: 681b ldr r3, [r3, #0] + 8001f64: 681b ldr r3, [r3, #0] + 8001f66: f003 0301 and.w r3, r3, #1 + 8001f6a: 2b01 cmp r3, #1 + 8001f6c: d101 bne.n 8001f72 + 8001f6e: 2301 movs r3, #1 + 8001f70: e000 b.n 8001f74 + 8001f72: 2300 movs r3, #0 + 8001f74: 2b00 cmp r3, #0 + 8001f76: f040 810a bne.w 800218e { /* Configuration of differential mode */ if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED) - 8001f42: 683b ldr r3, [r7, #0] - 8001f44: 68db ldr r3, [r3, #12] - 8001f46: 2b01 cmp r3, #1 - 8001f48: d00f beq.n 8001f6a + 8001f7a: 683b ldr r3, [r7, #0] + 8001f7c: 68db ldr r3, [r3, #12] + 8001f7e: 2b01 cmp r3, #1 + 8001f80: d00f beq.n 8001fa2 { /* Disable differential mode (default mode: single-ended) */ CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfig->Channel)); - 8001f4a: 687b ldr r3, [r7, #4] - 8001f4c: 681b ldr r3, [r3, #0] - 8001f4e: f8d3 10b0 ldr.w r1, [r3, #176] @ 0xb0 - 8001f52: 683b ldr r3, [r7, #0] - 8001f54: 681b ldr r3, [r3, #0] - 8001f56: 2201 movs r2, #1 - 8001f58: fa02 f303 lsl.w r3, r2, r3 - 8001f5c: 43da mvns r2, r3 - 8001f5e: 687b ldr r3, [r7, #4] - 8001f60: 681b ldr r3, [r3, #0] - 8001f62: 400a ands r2, r1 - 8001f64: f8c3 20b0 str.w r2, [r3, #176] @ 0xb0 - 8001f68: e049 b.n 8001ffe + 8001f82: 687b ldr r3, [r7, #4] + 8001f84: 681b ldr r3, [r3, #0] + 8001f86: f8d3 10b0 ldr.w r1, [r3, #176] @ 0xb0 + 8001f8a: 683b ldr r3, [r7, #0] + 8001f8c: 681b ldr r3, [r3, #0] + 8001f8e: 2201 movs r2, #1 + 8001f90: fa02 f303 lsl.w r3, r2, r3 + 8001f94: 43da mvns r2, r3 + 8001f96: 687b ldr r3, [r7, #4] + 8001f98: 681b ldr r3, [r3, #0] + 8001f9a: 400a ands r2, r1 + 8001f9c: f8c3 20b0 str.w r2, [r3, #176] @ 0xb0 + 8001fa0: e049 b.n 8002036 } else { /* Enable differential mode */ SET_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfig->Channel)); - 8001f6a: 687b ldr r3, [r7, #4] - 8001f6c: 681b ldr r3, [r3, #0] - 8001f6e: f8d3 10b0 ldr.w r1, [r3, #176] @ 0xb0 - 8001f72: 683b ldr r3, [r7, #0] - 8001f74: 681b ldr r3, [r3, #0] - 8001f76: 2201 movs r2, #1 - 8001f78: 409a lsls r2, r3 - 8001f7a: 687b ldr r3, [r7, #4] - 8001f7c: 681b ldr r3, [r3, #0] - 8001f7e: 430a orrs r2, r1 - 8001f80: f8c3 20b0 str.w r2, [r3, #176] @ 0xb0 + 8001fa2: 687b ldr r3, [r7, #4] + 8001fa4: 681b ldr r3, [r3, #0] + 8001fa6: f8d3 10b0 ldr.w r1, [r3, #176] @ 0xb0 + 8001faa: 683b ldr r3, [r7, #0] + 8001fac: 681b ldr r3, [r3, #0] + 8001fae: 2201 movs r2, #1 + 8001fb0: 409a lsls r2, r3 + 8001fb2: 687b ldr r3, [r7, #4] + 8001fb4: 681b ldr r3, [r3, #0] + 8001fb6: 430a orrs r2, r1 + 8001fb8: f8c3 20b0 str.w r2, [r3, #176] @ 0xb0 /* Channel sampling time configuration (channel ADC_INx +1 */ /* corresponding to differential negative input). */ /* For channels 10 to 18U */ if (sConfig->Channel >= ADC_CHANNEL_10) - 8001f84: 683b ldr r3, [r7, #0] - 8001f86: 681b ldr r3, [r3, #0] - 8001f88: 2b09 cmp r3, #9 - 8001f8a: d91c bls.n 8001fc6 + 8001fbc: 683b ldr r3, [r7, #0] + 8001fbe: 681b ldr r3, [r3, #0] + 8001fc0: 2b09 cmp r3, #9 + 8001fc2: d91c bls.n 8001ffe { MODIFY_REG(hadc->Instance->SMPR2, - 8001f8c: 687b ldr r3, [r7, #4] - 8001f8e: 681b ldr r3, [r3, #0] - 8001f90: 6999 ldr r1, [r3, #24] - 8001f92: 683b ldr r3, [r7, #0] - 8001f94: 681a ldr r2, [r3, #0] - 8001f96: 4613 mov r3, r2 - 8001f98: 005b lsls r3, r3, #1 - 8001f9a: 4413 add r3, r2 - 8001f9c: 3b1b subs r3, #27 - 8001f9e: 2207 movs r2, #7 - 8001fa0: fa02 f303 lsl.w r3, r2, r3 - 8001fa4: 43db mvns r3, r3 - 8001fa6: 4019 ands r1, r3 - 8001fa8: 683b ldr r3, [r7, #0] - 8001faa: 6898 ldr r0, [r3, #8] - 8001fac: 683b ldr r3, [r7, #0] - 8001fae: 681a ldr r2, [r3, #0] - 8001fb0: 4613 mov r3, r2 - 8001fb2: 005b lsls r3, r3, #1 - 8001fb4: 4413 add r3, r2 - 8001fb6: 3b1b subs r3, #27 - 8001fb8: fa00 f203 lsl.w r2, r0, r3 - 8001fbc: 687b ldr r3, [r7, #4] - 8001fbe: 681b ldr r3, [r3, #0] - 8001fc0: 430a orrs r2, r1 - 8001fc2: 619a str r2, [r3, #24] - 8001fc4: e01b b.n 8001ffe + 8001fc4: 687b ldr r3, [r7, #4] + 8001fc6: 681b ldr r3, [r3, #0] + 8001fc8: 6999 ldr r1, [r3, #24] + 8001fca: 683b ldr r3, [r7, #0] + 8001fcc: 681a ldr r2, [r3, #0] + 8001fce: 4613 mov r3, r2 + 8001fd0: 005b lsls r3, r3, #1 + 8001fd2: 4413 add r3, r2 + 8001fd4: 3b1b subs r3, #27 + 8001fd6: 2207 movs r2, #7 + 8001fd8: fa02 f303 lsl.w r3, r2, r3 + 8001fdc: 43db mvns r3, r3 + 8001fde: 4019 ands r1, r3 + 8001fe0: 683b ldr r3, [r7, #0] + 8001fe2: 6898 ldr r0, [r3, #8] + 8001fe4: 683b ldr r3, [r7, #0] + 8001fe6: 681a ldr r2, [r3, #0] + 8001fe8: 4613 mov r3, r2 + 8001fea: 005b lsls r3, r3, #1 + 8001fec: 4413 add r3, r2 + 8001fee: 3b1b subs r3, #27 + 8001ff0: fa00 f203 lsl.w r2, r0, r3 + 8001ff4: 687b ldr r3, [r7, #4] + 8001ff6: 681b ldr r3, [r3, #0] + 8001ff8: 430a orrs r2, r1 + 8001ffa: 619a str r2, [r3, #24] + 8001ffc: e01b b.n 8002036 ADC_SMPR2(ADC_SMPR2_SMP10, sConfig->Channel +1U) , ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel +1U) ); } else /* For channels 1 to 9U */ { MODIFY_REG(hadc->Instance->SMPR1, - 8001fc6: 687b ldr r3, [r7, #4] - 8001fc8: 681b ldr r3, [r3, #0] - 8001fca: 6959 ldr r1, [r3, #20] - 8001fcc: 683b ldr r3, [r7, #0] - 8001fce: 681b ldr r3, [r3, #0] - 8001fd0: 1c5a adds r2, r3, #1 - 8001fd2: 4613 mov r3, r2 - 8001fd4: 005b lsls r3, r3, #1 - 8001fd6: 4413 add r3, r2 - 8001fd8: 2207 movs r2, #7 - 8001fda: fa02 f303 lsl.w r3, r2, r3 - 8001fde: 43db mvns r3, r3 - 8001fe0: 4019 ands r1, r3 - 8001fe2: 683b ldr r3, [r7, #0] - 8001fe4: 6898 ldr r0, [r3, #8] - 8001fe6: 683b ldr r3, [r7, #0] - 8001fe8: 681b ldr r3, [r3, #0] - 8001fea: 1c5a adds r2, r3, #1 - 8001fec: 4613 mov r3, r2 - 8001fee: 005b lsls r3, r3, #1 - 8001ff0: 4413 add r3, r2 - 8001ff2: fa00 f203 lsl.w r2, r0, r3 - 8001ff6: 687b ldr r3, [r7, #4] - 8001ff8: 681b ldr r3, [r3, #0] - 8001ffa: 430a orrs r2, r1 - 8001ffc: 615a str r2, [r3, #20] + 8001ffe: 687b ldr r3, [r7, #4] + 8002000: 681b ldr r3, [r3, #0] + 8002002: 6959 ldr r1, [r3, #20] + 8002004: 683b ldr r3, [r7, #0] + 8002006: 681b ldr r3, [r3, #0] + 8002008: 1c5a adds r2, r3, #1 + 800200a: 4613 mov r3, r2 + 800200c: 005b lsls r3, r3, #1 + 800200e: 4413 add r3, r2 + 8002010: 2207 movs r2, #7 + 8002012: fa02 f303 lsl.w r3, r2, r3 + 8002016: 43db mvns r3, r3 + 8002018: 4019 ands r1, r3 + 800201a: 683b ldr r3, [r7, #0] + 800201c: 6898 ldr r0, [r3, #8] + 800201e: 683b ldr r3, [r7, #0] + 8002020: 681b ldr r3, [r3, #0] + 8002022: 1c5a adds r2, r3, #1 + 8002024: 4613 mov r3, r2 + 8002026: 005b lsls r3, r3, #1 + 8002028: 4413 add r3, r2 + 800202a: fa00 f203 lsl.w r2, r0, r3 + 800202e: 687b ldr r3, [r7, #4] + 8002030: 681b ldr r3, [r3, #0] + 8002032: 430a orrs r2, r1 + 8002034: 615a str r2, [r3, #20] /* Configuration of common ADC parameters */ /* Pointer to the common control register to which is belonging hadc */ /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */ /* control registers) */ tmpADC_Common = ADC_COMMON_REGISTER(hadc); - 8001ffe: 4b1f ldr r3, [pc, #124] @ (800207c ) - 8002000: 65fb str r3, [r7, #92] @ 0x5c + 8002036: 4b1f ldr r3, [pc, #124] @ (80020b4 ) + 8002038: 65fb str r3, [r7, #92] @ 0x5c /* If the requested internal measurement path has already been enabled, */ /* bypass the configuration processing. */ if (( (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && - 8002002: 683b ldr r3, [r7, #0] - 8002004: 681b ldr r3, [r3, #0] - 8002006: 2b10 cmp r3, #16 - 8002008: d105 bne.n 8002016 + 800203a: 683b ldr r3, [r7, #0] + 800203c: 681b ldr r3, [r3, #0] + 800203e: 2b10 cmp r3, #16 + 8002040: d105 bne.n 800204e (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_TSEN)) ) || - 800200a: 6dfb ldr r3, [r7, #92] @ 0x5c - 800200c: 689b ldr r3, [r3, #8] - 800200e: f403 0300 and.w r3, r3, #8388608 @ 0x800000 + 8002042: 6dfb ldr r3, [r7, #92] @ 0x5c + 8002044: 689b ldr r3, [r3, #8] + 8002046: f403 0300 and.w r3, r3, #8388608 @ 0x800000 if (( (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && - 8002012: 2b00 cmp r3, #0 - 8002014: d015 beq.n 8002042 + 800204a: 2b00 cmp r3, #0 + 800204c: d015 beq.n 800207a ( (sConfig->Channel == ADC_CHANNEL_VBAT) && - 8002016: 683b ldr r3, [r7, #0] - 8002018: 681b ldr r3, [r3, #0] + 800204e: 683b ldr r3, [r7, #0] + 8002050: 681b ldr r3, [r3, #0] (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_TSEN)) ) || - 800201a: 2b11 cmp r3, #17 - 800201c: d105 bne.n 800202a + 8002052: 2b11 cmp r3, #17 + 8002054: d105 bne.n 8002062 (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VBATEN)) ) || - 800201e: 6dfb ldr r3, [r7, #92] @ 0x5c - 8002020: 689b ldr r3, [r3, #8] - 8002022: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 + 8002056: 6dfb ldr r3, [r7, #92] @ 0x5c + 8002058: 689b ldr r3, [r3, #8] + 800205a: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 ( (sConfig->Channel == ADC_CHANNEL_VBAT) && - 8002026: 2b00 cmp r3, #0 - 8002028: d00b beq.n 8002042 + 800205e: 2b00 cmp r3, #0 + 8002060: d00b beq.n 800207a ( (sConfig->Channel == ADC_CHANNEL_VREFINT) && - 800202a: 683b ldr r3, [r7, #0] - 800202c: 681b ldr r3, [r3, #0] + 8002062: 683b ldr r3, [r7, #0] + 8002064: 681b ldr r3, [r3, #0] (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VBATEN)) ) || - 800202e: 2b12 cmp r3, #18 - 8002030: f040 8091 bne.w 8002156 + 8002066: 2b12 cmp r3, #18 + 8002068: f040 8091 bne.w 800218e (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VREFEN))) - 8002034: 6dfb ldr r3, [r7, #92] @ 0x5c - 8002036: 689b ldr r3, [r3, #8] - 8002038: f403 0380 and.w r3, r3, #4194304 @ 0x400000 + 800206c: 6dfb ldr r3, [r7, #92] @ 0x5c + 800206e: 689b ldr r3, [r3, #8] + 8002070: f403 0380 and.w r3, r3, #4194304 @ 0x400000 ( (sConfig->Channel == ADC_CHANNEL_VREFINT) && - 800203c: 2b00 cmp r3, #0 - 800203e: f040 808a bne.w 8002156 + 8002074: 2b00 cmp r3, #0 + 8002076: f040 808a bne.w 800218e ) { /* Configuration of common ADC parameters (continuation) */ /* Set handle of the other ADC sharing the same common register */ ADC_COMMON_ADC_OTHER(hadc, &tmphadcSharingSameCommonRegister); - 8002042: 687b ldr r3, [r7, #4] - 8002044: 681b ldr r3, [r3, #0] - 8002046: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 - 800204a: d102 bne.n 8002052 - 800204c: 4b0c ldr r3, [pc, #48] @ (8002080 ) - 800204e: 60fb str r3, [r7, #12] - 8002050: e002 b.n 8002058 - 8002052: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 - 8002056: 60fb str r3, [r7, #12] + 800207a: 687b ldr r3, [r7, #4] + 800207c: 681b ldr r3, [r3, #0] + 800207e: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 + 8002082: d102 bne.n 800208a + 8002084: 4b0c ldr r3, [pc, #48] @ (80020b8 ) + 8002086: 60fb str r3, [r7, #12] + 8002088: e002 b.n 8002090 + 800208a: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 + 800208e: 60fb str r3, [r7, #12] /* Software is allowed to change common parameters only when all ADCs */ /* of the common group are disabled. */ if ((ADC_IS_ENABLE(hadc) == RESET) && - 8002058: 687b ldr r3, [r7, #4] - 800205a: 681b ldr r3, [r3, #0] - 800205c: 689b ldr r3, [r3, #8] - 800205e: f003 0303 and.w r3, r3, #3 - 8002062: 2b01 cmp r3, #1 - 8002064: d10e bne.n 8002084 - 8002066: 687b ldr r3, [r7, #4] - 8002068: 681b ldr r3, [r3, #0] - 800206a: 681b ldr r3, [r3, #0] - 800206c: f003 0301 and.w r3, r3, #1 - 8002070: 2b01 cmp r3, #1 - 8002072: d107 bne.n 8002084 - 8002074: 2301 movs r3, #1 - 8002076: e006 b.n 8002086 - 8002078: 83fff000 .word 0x83fff000 - 800207c: 50000300 .word 0x50000300 - 8002080: 50000100 .word 0x50000100 - 8002084: 2300 movs r3, #0 - 8002086: 2b00 cmp r3, #0 - 8002088: d150 bne.n 800212c + 8002090: 687b ldr r3, [r7, #4] + 8002092: 681b ldr r3, [r3, #0] + 8002094: 689b ldr r3, [r3, #8] + 8002096: f003 0303 and.w r3, r3, #3 + 800209a: 2b01 cmp r3, #1 + 800209c: d10e bne.n 80020bc + 800209e: 687b ldr r3, [r7, #4] + 80020a0: 681b ldr r3, [r3, #0] + 80020a2: 681b ldr r3, [r3, #0] + 80020a4: f003 0301 and.w r3, r3, #1 + 80020a8: 2b01 cmp r3, #1 + 80020aa: d107 bne.n 80020bc + 80020ac: 2301 movs r3, #1 + 80020ae: e006 b.n 80020be + 80020b0: 83fff000 .word 0x83fff000 + 80020b4: 50000300 .word 0x50000300 + 80020b8: 50000100 .word 0x50000100 + 80020bc: 2300 movs r3, #0 + 80020be: 2b00 cmp r3, #0 + 80020c0: d150 bne.n 8002164 ( (tmphadcSharingSameCommonRegister.Instance == NULL) || - 800208a: 68fb ldr r3, [r7, #12] + 80020c2: 68fb ldr r3, [r7, #12] if ((ADC_IS_ENABLE(hadc) == RESET) && - 800208c: 2b00 cmp r3, #0 - 800208e: d010 beq.n 80020b2 + 80020c4: 2b00 cmp r3, #0 + 80020c6: d010 beq.n 80020ea (ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) ) ) - 8002090: 68fb ldr r3, [r7, #12] - 8002092: 689b ldr r3, [r3, #8] - 8002094: f003 0303 and.w r3, r3, #3 - 8002098: 2b01 cmp r3, #1 - 800209a: d107 bne.n 80020ac - 800209c: 68fb ldr r3, [r7, #12] - 800209e: 681b ldr r3, [r3, #0] - 80020a0: f003 0301 and.w r3, r3, #1 - 80020a4: 2b01 cmp r3, #1 - 80020a6: d101 bne.n 80020ac - 80020a8: 2301 movs r3, #1 - 80020aa: e000 b.n 80020ae - 80020ac: 2300 movs r3, #0 + 80020c8: 68fb ldr r3, [r7, #12] + 80020ca: 689b ldr r3, [r3, #8] + 80020cc: f003 0303 and.w r3, r3, #3 + 80020d0: 2b01 cmp r3, #1 + 80020d2: d107 bne.n 80020e4 + 80020d4: 68fb ldr r3, [r7, #12] + 80020d6: 681b ldr r3, [r3, #0] + 80020d8: f003 0301 and.w r3, r3, #1 + 80020dc: 2b01 cmp r3, #1 + 80020de: d101 bne.n 80020e4 + 80020e0: 2301 movs r3, #1 + 80020e2: e000 b.n 80020e6 + 80020e4: 2300 movs r3, #0 ( (tmphadcSharingSameCommonRegister.Instance == NULL) || - 80020ae: 2b00 cmp r3, #0 - 80020b0: d13c bne.n 800212c + 80020e6: 2b00 cmp r3, #0 + 80020e8: d13c bne.n 8002164 { /* If Channel_16 is selected, enable Temp. sensor measurement path */ /* Note: Temp. sensor internal channels available on ADC1 only */ if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && (hadc->Instance == ADC1)) - 80020b2: 683b ldr r3, [r7, #0] - 80020b4: 681b ldr r3, [r3, #0] - 80020b6: 2b10 cmp r3, #16 - 80020b8: d11d bne.n 80020f6 - 80020ba: 687b ldr r3, [r7, #4] - 80020bc: 681b ldr r3, [r3, #0] - 80020be: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 - 80020c2: d118 bne.n 80020f6 + 80020ea: 683b ldr r3, [r7, #0] + 80020ec: 681b ldr r3, [r3, #0] + 80020ee: 2b10 cmp r3, #16 + 80020f0: d11d bne.n 800212e + 80020f2: 687b ldr r3, [r7, #4] + 80020f4: 681b ldr r3, [r3, #0] + 80020f6: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 + 80020fa: d118 bne.n 800212e { SET_BIT(tmpADC_Common->CCR, ADC_CCR_TSEN); - 80020c4: 6dfb ldr r3, [r7, #92] @ 0x5c - 80020c6: 689b ldr r3, [r3, #8] - 80020c8: f443 0200 orr.w r2, r3, #8388608 @ 0x800000 - 80020cc: 6dfb ldr r3, [r7, #92] @ 0x5c - 80020ce: 609a str r2, [r3, #8] + 80020fc: 6dfb ldr r3, [r7, #92] @ 0x5c + 80020fe: 689b ldr r3, [r3, #8] + 8002100: f443 0200 orr.w r2, r3, #8388608 @ 0x800000 + 8002104: 6dfb ldr r3, [r7, #92] @ 0x5c + 8002106: 609a str r2, [r3, #8] /* Delay for temperature sensor stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); - 80020d0: 4b27 ldr r3, [pc, #156] @ (8002170 ) - 80020d2: 681b ldr r3, [r3, #0] - 80020d4: 4a27 ldr r2, [pc, #156] @ (8002174 ) - 80020d6: fba2 2303 umull r2, r3, r2, r3 - 80020da: 0c9a lsrs r2, r3, #18 - 80020dc: 4613 mov r3, r2 - 80020de: 009b lsls r3, r3, #2 - 80020e0: 4413 add r3, r2 - 80020e2: 005b lsls r3, r3, #1 - 80020e4: 60bb str r3, [r7, #8] + 8002108: 4b27 ldr r3, [pc, #156] @ (80021a8 ) + 800210a: 681b ldr r3, [r3, #0] + 800210c: 4a27 ldr r2, [pc, #156] @ (80021ac ) + 800210e: fba2 2303 umull r2, r3, r2, r3 + 8002112: 0c9a lsrs r2, r3, #18 + 8002114: 4613 mov r3, r2 + 8002116: 009b lsls r3, r3, #2 + 8002118: 4413 add r3, r2 + 800211a: 005b lsls r3, r3, #1 + 800211c: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) - 80020e6: e002 b.n 80020ee + 800211e: e002 b.n 8002126 { wait_loop_index--; - 80020e8: 68bb ldr r3, [r7, #8] - 80020ea: 3b01 subs r3, #1 - 80020ec: 60bb str r3, [r7, #8] + 8002120: 68bb ldr r3, [r7, #8] + 8002122: 3b01 subs r3, #1 + 8002124: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) - 80020ee: 68bb ldr r3, [r7, #8] - 80020f0: 2b00 cmp r3, #0 - 80020f2: d1f9 bne.n 80020e8 + 8002126: 68bb ldr r3, [r7, #8] + 8002128: 2b00 cmp r3, #0 + 800212a: d1f9 bne.n 8002120 if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && (hadc->Instance == ADC1)) - 80020f4: e02e b.n 8002154 + 800212c: e02e b.n 800218c } } /* If Channel_17 is selected, enable VBAT measurement path */ /* Note: VBAT internal channels available on ADC1 only */ else if ((sConfig->Channel == ADC_CHANNEL_VBAT) && (hadc->Instance == ADC1)) - 80020f6: 683b ldr r3, [r7, #0] - 80020f8: 681b ldr r3, [r3, #0] - 80020fa: 2b11 cmp r3, #17 - 80020fc: d10b bne.n 8002116 - 80020fe: 687b ldr r3, [r7, #4] - 8002100: 681b ldr r3, [r3, #0] - 8002102: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 - 8002106: d106 bne.n 8002116 + 800212e: 683b ldr r3, [r7, #0] + 8002130: 681b ldr r3, [r3, #0] + 8002132: 2b11 cmp r3, #17 + 8002134: d10b bne.n 800214e + 8002136: 687b ldr r3, [r7, #4] + 8002138: 681b ldr r3, [r3, #0] + 800213a: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 + 800213e: d106 bne.n 800214e { SET_BIT(tmpADC_Common->CCR, ADC_CCR_VBATEN); - 8002108: 6dfb ldr r3, [r7, #92] @ 0x5c - 800210a: 689b ldr r3, [r3, #8] - 800210c: f043 7280 orr.w r2, r3, #16777216 @ 0x1000000 - 8002110: 6dfb ldr r3, [r7, #92] @ 0x5c - 8002112: 609a str r2, [r3, #8] + 8002140: 6dfb ldr r3, [r7, #92] @ 0x5c + 8002142: 689b ldr r3, [r3, #8] + 8002144: f043 7280 orr.w r2, r3, #16777216 @ 0x1000000 + 8002148: 6dfb ldr r3, [r7, #92] @ 0x5c + 800214a: 609a str r2, [r3, #8] if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && (hadc->Instance == ADC1)) - 8002114: e01e b.n 8002154 + 800214c: e01e b.n 800218c } /* If Channel_18 is selected, enable VREFINT measurement path */ /* Note: VrefInt internal channels available on all ADCs, but only */ /* one ADC is allowed to be connected to VrefInt at the same */ /* time. */ else if (sConfig->Channel == ADC_CHANNEL_VREFINT) - 8002116: 683b ldr r3, [r7, #0] - 8002118: 681b ldr r3, [r3, #0] - 800211a: 2b12 cmp r3, #18 - 800211c: d11a bne.n 8002154 + 800214e: 683b ldr r3, [r7, #0] + 8002150: 681b ldr r3, [r3, #0] + 8002152: 2b12 cmp r3, #18 + 8002154: d11a bne.n 800218c { SET_BIT(tmpADC_Common->CCR, ADC_CCR_VREFEN); - 800211e: 6dfb ldr r3, [r7, #92] @ 0x5c - 8002120: 689b ldr r3, [r3, #8] - 8002122: f443 0280 orr.w r2, r3, #4194304 @ 0x400000 - 8002126: 6dfb ldr r3, [r7, #92] @ 0x5c - 8002128: 609a str r2, [r3, #8] + 8002156: 6dfb ldr r3, [r7, #92] @ 0x5c + 8002158: 689b ldr r3, [r3, #8] + 800215a: f443 0280 orr.w r2, r3, #4194304 @ 0x400000 + 800215e: 6dfb ldr r3, [r7, #92] @ 0x5c + 8002160: 609a str r2, [r3, #8] if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && (hadc->Instance == ADC1)) - 800212a: e013 b.n 8002154 + 8002162: e013 b.n 800218c /* enabled and other ADC of the common group are enabled, internal */ /* measurement paths cannot be enabled. */ else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - 800212c: 687b ldr r3, [r7, #4] - 800212e: 6c1b ldr r3, [r3, #64] @ 0x40 - 8002130: f043 0220 orr.w r2, r3, #32 - 8002134: 687b ldr r3, [r7, #4] - 8002136: 641a str r2, [r3, #64] @ 0x40 + 8002164: 687b ldr r3, [r7, #4] + 8002166: 6c1b ldr r3, [r3, #64] @ 0x40 + 8002168: f043 0220 orr.w r2, r3, #32 + 800216c: 687b ldr r3, [r7, #4] + 800216e: 641a str r2, [r3, #64] @ 0x40 tmp_hal_status = HAL_ERROR; - 8002138: 2301 movs r3, #1 - 800213a: f887 3067 strb.w r3, [r7, #103] @ 0x67 - 800213e: e00a b.n 8002156 + 8002170: 2301 movs r3, #1 + 8002172: f887 3067 strb.w r3, [r7, #103] @ 0x67 + 8002176: e00a b.n 800218e /* channel could be done on neither of the channel configuration structure */ /* parameters. */ else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - 8002140: 687b ldr r3, [r7, #4] - 8002142: 6c1b ldr r3, [r3, #64] @ 0x40 - 8002144: f043 0220 orr.w r2, r3, #32 - 8002148: 687b ldr r3, [r7, #4] - 800214a: 641a str r2, [r3, #64] @ 0x40 + 8002178: 687b ldr r3, [r7, #4] + 800217a: 6c1b ldr r3, [r3, #64] @ 0x40 + 800217c: f043 0220 orr.w r2, r3, #32 + 8002180: 687b ldr r3, [r7, #4] + 8002182: 641a str r2, [r3, #64] @ 0x40 tmp_hal_status = HAL_ERROR; - 800214c: 2301 movs r3, #1 - 800214e: f887 3067 strb.w r3, [r7, #103] @ 0x67 - 8002152: e000 b.n 8002156 + 8002184: 2301 movs r3, #1 + 8002186: f887 3067 strb.w r3, [r7, #103] @ 0x67 + 800218a: e000 b.n 800218e if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && (hadc->Instance == ADC1)) - 8002154: bf00 nop + 800218c: bf00 nop } /* Process unlocked */ __HAL_UNLOCK(hadc); - 8002156: 687b ldr r3, [r7, #4] - 8002158: 2200 movs r2, #0 - 800215a: f883 203c strb.w r2, [r3, #60] @ 0x3c + 800218e: 687b ldr r3, [r7, #4] + 8002190: 2200 movs r2, #0 + 8002192: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Return function status */ return tmp_hal_status; - 800215e: f897 3067 ldrb.w r3, [r7, #103] @ 0x67 + 8002196: f897 3067 ldrb.w r3, [r7, #103] @ 0x67 } - 8002162: 4618 mov r0, r3 - 8002164: 376c adds r7, #108 @ 0x6c - 8002166: 46bd mov sp, r7 - 8002168: f85d 7b04 ldr.w r7, [sp], #4 - 800216c: 4770 bx lr - 800216e: bf00 nop - 8002170: 20000000 .word 0x20000000 - 8002174: 431bde83 .word 0x431bde83 + 800219a: 4618 mov r0, r3 + 800219c: 376c adds r7, #108 @ 0x6c + 800219e: 46bd mov sp, r7 + 80021a0: f85d 7b04 ldr.w r7, [sp], #4 + 80021a4: 4770 bx lr + 80021a6: bf00 nop + 80021a8: 20000000 .word 0x20000000 + 80021ac: 431bde83 .word 0x431bde83 -08002178 : +080021b0 : * @param hadc ADC handle * @param multimode Structure of ADC multimode configuration * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode) { - 8002178: b480 push {r7} - 800217a: b099 sub sp, #100 @ 0x64 - 800217c: af00 add r7, sp, #0 - 800217e: 6078 str r0, [r7, #4] - 8002180: 6039 str r1, [r7, #0] + 80021b0: b480 push {r7} + 80021b2: b099 sub sp, #100 @ 0x64 + 80021b4: af00 add r7, sp, #0 + 80021b6: 6078 str r0, [r7, #4] + 80021b8: 6039 str r1, [r7, #0] HAL_StatusTypeDef tmp_hal_status = HAL_OK; - 8002182: 2300 movs r3, #0 - 8002184: f887 305f strb.w r3, [r7, #95] @ 0x5f + 80021ba: 2300 movs r3, #0 + 80021bc: f887 305f strb.w r3, [r7, #95] @ 0x5f assert_param(IS_ADC_DMA_ACCESS_MODE(multimode->DMAAccessMode)); assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay)); } /* Set handle of the other ADC sharing the same common register */ ADC_COMMON_ADC_OTHER(hadc, &tmphadcSharingSameCommonRegister); - 8002188: 687b ldr r3, [r7, #4] - 800218a: 681b ldr r3, [r3, #0] - 800218c: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 - 8002190: d102 bne.n 8002198 - 8002192: 4b5a ldr r3, [pc, #360] @ (80022fc ) - 8002194: 60bb str r3, [r7, #8] - 8002196: e002 b.n 800219e - 8002198: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 - 800219c: 60bb str r3, [r7, #8] + 80021c0: 687b ldr r3, [r7, #4] + 80021c2: 681b ldr r3, [r3, #0] + 80021c4: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 + 80021c8: d102 bne.n 80021d0 + 80021ca: 4b5a ldr r3, [pc, #360] @ (8002334 ) + 80021cc: 60bb str r3, [r7, #8] + 80021ce: e002 b.n 80021d6 + 80021d0: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 + 80021d4: 60bb str r3, [r7, #8] if (tmphadcSharingSameCommonRegister.Instance == NULL) - 800219e: 68bb ldr r3, [r7, #8] - 80021a0: 2b00 cmp r3, #0 - 80021a2: d101 bne.n 80021a8 + 80021d6: 68bb ldr r3, [r7, #8] + 80021d8: 2b00 cmp r3, #0 + 80021da: d101 bne.n 80021e0 { /* Return function status */ return HAL_ERROR; - 80021a4: 2301 movs r3, #1 - 80021a6: e0a2 b.n 80022ee + 80021dc: 2301 movs r3, #1 + 80021de: e0a2 b.n 8002326 } /* Process locked */ __HAL_LOCK(hadc); - 80021a8: 687b ldr r3, [r7, #4] - 80021aa: f893 303c ldrb.w r3, [r3, #60] @ 0x3c - 80021ae: 2b01 cmp r3, #1 - 80021b0: d101 bne.n 80021b6 - 80021b2: 2302 movs r3, #2 - 80021b4: e09b b.n 80022ee - 80021b6: 687b ldr r3, [r7, #4] - 80021b8: 2201 movs r2, #1 - 80021ba: f883 203c strb.w r2, [r3, #60] @ 0x3c + 80021e0: 687b ldr r3, [r7, #4] + 80021e2: f893 303c ldrb.w r3, [r3, #60] @ 0x3c + 80021e6: 2b01 cmp r3, #1 + 80021e8: d101 bne.n 80021ee + 80021ea: 2302 movs r3, #2 + 80021ec: e09b b.n 8002326 + 80021ee: 687b ldr r3, [r7, #4] + 80021f0: 2201 movs r2, #1 + 80021f2: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - Multimode DMA configuration */ /* - Multimode DMA mode */ if ( (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) - 80021be: 687b ldr r3, [r7, #4] - 80021c0: 681b ldr r3, [r3, #0] - 80021c2: 689b ldr r3, [r3, #8] - 80021c4: f003 0304 and.w r3, r3, #4 - 80021c8: 2b00 cmp r3, #0 - 80021ca: d17f bne.n 80022cc + 80021f6: 687b ldr r3, [r7, #4] + 80021f8: 681b ldr r3, [r3, #0] + 80021fa: 689b ldr r3, [r3, #8] + 80021fc: f003 0304 and.w r3, r3, #4 + 8002200: 2b00 cmp r3, #0 + 8002202: d17f bne.n 8002304 && (ADC_IS_CONVERSION_ONGOING_REGULAR(&tmphadcSharingSameCommonRegister) == RESET) ) - 80021cc: 68bb ldr r3, [r7, #8] - 80021ce: 689b ldr r3, [r3, #8] - 80021d0: f003 0304 and.w r3, r3, #4 - 80021d4: 2b00 cmp r3, #0 - 80021d6: d179 bne.n 80022cc + 8002204: 68bb ldr r3, [r7, #8] + 8002206: 689b ldr r3, [r3, #8] + 8002208: f003 0304 and.w r3, r3, #4 + 800220c: 2b00 cmp r3, #0 + 800220e: d179 bne.n 8002304 { /* Pointer to the common control register to which is belonging hadc */ /* (Depending on STM32F3 product, there may have up to 4 ADC and 2 common */ /* control registers) */ tmpADC_Common = ADC_COMMON_REGISTER(hadc); - 80021d8: 4b49 ldr r3, [pc, #292] @ (8002300 ) - 80021da: 65bb str r3, [r7, #88] @ 0x58 + 8002210: 4b49 ldr r3, [pc, #292] @ (8002338 ) + 8002212: 65bb str r3, [r7, #88] @ 0x58 /* If multimode is selected, configure all multimode parameters. */ /* Otherwise, reset multimode parameters (can be used in case of */ /* transition from multimode to independent mode). */ if(multimode->Mode != ADC_MODE_INDEPENDENT) - 80021dc: 683b ldr r3, [r7, #0] - 80021de: 681b ldr r3, [r3, #0] - 80021e0: 2b00 cmp r3, #0 - 80021e2: d040 beq.n 8002266 + 8002214: 683b ldr r3, [r7, #0] + 8002216: 681b ldr r3, [r3, #0] + 8002218: 2b00 cmp r3, #0 + 800221a: d040 beq.n 800229e { /* Configuration of ADC common group ADC1&ADC2, ADC3&ADC4 if available */ /* (ADC2, ADC3, ADC4 availability depends on STM32 product) */ /* - DMA access mode */ MODIFY_REG(tmpADC_Common->CCR , - 80021e4: 6dbb ldr r3, [r7, #88] @ 0x58 - 80021e6: 689b ldr r3, [r3, #8] - 80021e8: f423 4260 bic.w r2, r3, #57344 @ 0xe000 - 80021ec: 683b ldr r3, [r7, #0] - 80021ee: 6859 ldr r1, [r3, #4] - 80021f0: 687b ldr r3, [r7, #4] - 80021f2: f893 3030 ldrb.w r3, [r3, #48] @ 0x30 - 80021f6: 035b lsls r3, r3, #13 - 80021f8: 430b orrs r3, r1 - 80021fa: 431a orrs r2, r3 - 80021fc: 6dbb ldr r3, [r7, #88] @ 0x58 - 80021fe: 609a str r2, [r3, #8] + 800221c: 6dbb ldr r3, [r7, #88] @ 0x58 + 800221e: 689b ldr r3, [r3, #8] + 8002220: f423 4260 bic.w r2, r3, #57344 @ 0xe000 + 8002224: 683b ldr r3, [r7, #0] + 8002226: 6859 ldr r1, [r3, #4] + 8002228: 687b ldr r3, [r7, #4] + 800222a: f893 3030 ldrb.w r3, [r3, #48] @ 0x30 + 800222e: 035b lsls r3, r3, #13 + 8002230: 430b orrs r3, r1 + 8002232: 431a orrs r2, r3 + 8002234: 6dbb ldr r3, [r7, #88] @ 0x58 + 8002236: 609a str r2, [r3, #8] /* parameters, their setting is bypassed without error reporting */ /* (as it can be the expected behaviour in case of intended action */ /* to update parameter above (which fulfills the ADC state */ /* condition: no conversion on going on group regular) */ /* on the fly). */ if ((ADC_IS_ENABLE(hadc) == RESET) && - 8002200: 687b ldr r3, [r7, #4] - 8002202: 681b ldr r3, [r3, #0] - 8002204: 689b ldr r3, [r3, #8] - 8002206: f003 0303 and.w r3, r3, #3 - 800220a: 2b01 cmp r3, #1 - 800220c: d108 bne.n 8002220 - 800220e: 687b ldr r3, [r7, #4] - 8002210: 681b ldr r3, [r3, #0] - 8002212: 681b ldr r3, [r3, #0] - 8002214: f003 0301 and.w r3, r3, #1 - 8002218: 2b01 cmp r3, #1 - 800221a: d101 bne.n 8002220 - 800221c: 2301 movs r3, #1 - 800221e: e000 b.n 8002222 - 8002220: 2300 movs r3, #0 - 8002222: 2b00 cmp r3, #0 - 8002224: d15c bne.n 80022e0 + 8002238: 687b ldr r3, [r7, #4] + 800223a: 681b ldr r3, [r3, #0] + 800223c: 689b ldr r3, [r3, #8] + 800223e: f003 0303 and.w r3, r3, #3 + 8002242: 2b01 cmp r3, #1 + 8002244: d108 bne.n 8002258 + 8002246: 687b ldr r3, [r7, #4] + 8002248: 681b ldr r3, [r3, #0] + 800224a: 681b ldr r3, [r3, #0] + 800224c: f003 0301 and.w r3, r3, #1 + 8002250: 2b01 cmp r3, #1 + 8002252: d101 bne.n 8002258 + 8002254: 2301 movs r3, #1 + 8002256: e000 b.n 800225a + 8002258: 2300 movs r3, #0 + 800225a: 2b00 cmp r3, #0 + 800225c: d15c bne.n 8002318 (ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) ) - 8002226: 68bb ldr r3, [r7, #8] - 8002228: 689b ldr r3, [r3, #8] - 800222a: f003 0303 and.w r3, r3, #3 - 800222e: 2b01 cmp r3, #1 - 8002230: d107 bne.n 8002242 - 8002232: 68bb ldr r3, [r7, #8] - 8002234: 681b ldr r3, [r3, #0] - 8002236: f003 0301 and.w r3, r3, #1 - 800223a: 2b01 cmp r3, #1 - 800223c: d101 bne.n 8002242 - 800223e: 2301 movs r3, #1 - 8002240: e000 b.n 8002244 - 8002242: 2300 movs r3, #0 + 800225e: 68bb ldr r3, [r7, #8] + 8002260: 689b ldr r3, [r3, #8] + 8002262: f003 0303 and.w r3, r3, #3 + 8002266: 2b01 cmp r3, #1 + 8002268: d107 bne.n 800227a + 800226a: 68bb ldr r3, [r7, #8] + 800226c: 681b ldr r3, [r3, #0] + 800226e: f003 0301 and.w r3, r3, #1 + 8002272: 2b01 cmp r3, #1 + 8002274: d101 bne.n 800227a + 8002276: 2301 movs r3, #1 + 8002278: e000 b.n 800227c + 800227a: 2300 movs r3, #0 if ((ADC_IS_ENABLE(hadc) == RESET) && - 8002244: 2b00 cmp r3, #0 - 8002246: d14b bne.n 80022e0 + 800227c: 2b00 cmp r3, #0 + 800227e: d14b bne.n 8002318 { MODIFY_REG(tmpADC_Common->CCR , - 8002248: 6dbb ldr r3, [r7, #88] @ 0x58 - 800224a: 689b ldr r3, [r3, #8] - 800224c: f423 6371 bic.w r3, r3, #3856 @ 0xf10 - 8002250: f023 030f bic.w r3, r3, #15 - 8002254: 683a ldr r2, [r7, #0] - 8002256: 6811 ldr r1, [r2, #0] - 8002258: 683a ldr r2, [r7, #0] - 800225a: 6892 ldr r2, [r2, #8] - 800225c: 430a orrs r2, r1 - 800225e: 431a orrs r2, r3 - 8002260: 6dbb ldr r3, [r7, #88] @ 0x58 - 8002262: 609a str r2, [r3, #8] + 8002280: 6dbb ldr r3, [r7, #88] @ 0x58 + 8002282: 689b ldr r3, [r3, #8] + 8002284: f423 6371 bic.w r3, r3, #3856 @ 0xf10 + 8002288: f023 030f bic.w r3, r3, #15 + 800228c: 683a ldr r2, [r7, #0] + 800228e: 6811 ldr r1, [r2, #0] + 8002290: 683a ldr r2, [r7, #0] + 8002292: 6892 ldr r2, [r2, #8] + 8002294: 430a orrs r2, r1 + 8002296: 431a orrs r2, r3 + 8002298: 6dbb ldr r3, [r7, #88] @ 0x58 + 800229a: 609a str r2, [r3, #8] if(multimode->Mode != ADC_MODE_INDEPENDENT) - 8002264: e03c b.n 80022e0 + 800229c: e03c b.n 8002318 multimode->TwoSamplingDelay ); } } else /* ADC_MODE_INDEPENDENT */ { CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG); - 8002266: 6dbb ldr r3, [r7, #88] @ 0x58 - 8002268: 689b ldr r3, [r3, #8] - 800226a: f423 4260 bic.w r2, r3, #57344 @ 0xe000 - 800226e: 6dbb ldr r3, [r7, #88] @ 0x58 - 8002270: 609a str r2, [r3, #8] + 800229e: 6dbb ldr r3, [r7, #88] @ 0x58 + 80022a0: 689b ldr r3, [r3, #8] + 80022a2: f423 4260 bic.w r2, r3, #57344 @ 0xe000 + 80022a6: 6dbb ldr r3, [r7, #88] @ 0x58 + 80022a8: 609a str r2, [r3, #8] /* Parameters that can be updated only when ADC is disabled: */ /* - Multimode mode selection */ /* - Multimode delay */ if ((ADC_IS_ENABLE(hadc) == RESET) && - 8002272: 687b ldr r3, [r7, #4] - 8002274: 681b ldr r3, [r3, #0] - 8002276: 689b ldr r3, [r3, #8] - 8002278: f003 0303 and.w r3, r3, #3 - 800227c: 2b01 cmp r3, #1 - 800227e: d108 bne.n 8002292 - 8002280: 687b ldr r3, [r7, #4] - 8002282: 681b ldr r3, [r3, #0] - 8002284: 681b ldr r3, [r3, #0] - 8002286: f003 0301 and.w r3, r3, #1 - 800228a: 2b01 cmp r3, #1 - 800228c: d101 bne.n 8002292 - 800228e: 2301 movs r3, #1 - 8002290: e000 b.n 8002294 - 8002292: 2300 movs r3, #0 - 8002294: 2b00 cmp r3, #0 - 8002296: d123 bne.n 80022e0 + 80022aa: 687b ldr r3, [r7, #4] + 80022ac: 681b ldr r3, [r3, #0] + 80022ae: 689b ldr r3, [r3, #8] + 80022b0: f003 0303 and.w r3, r3, #3 + 80022b4: 2b01 cmp r3, #1 + 80022b6: d108 bne.n 80022ca + 80022b8: 687b ldr r3, [r7, #4] + 80022ba: 681b ldr r3, [r3, #0] + 80022bc: 681b ldr r3, [r3, #0] + 80022be: f003 0301 and.w r3, r3, #1 + 80022c2: 2b01 cmp r3, #1 + 80022c4: d101 bne.n 80022ca + 80022c6: 2301 movs r3, #1 + 80022c8: e000 b.n 80022cc + 80022ca: 2300 movs r3, #0 + 80022cc: 2b00 cmp r3, #0 + 80022ce: d123 bne.n 8002318 (ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) ) - 8002298: 68bb ldr r3, [r7, #8] - 800229a: 689b ldr r3, [r3, #8] - 800229c: f003 0303 and.w r3, r3, #3 - 80022a0: 2b01 cmp r3, #1 - 80022a2: d107 bne.n 80022b4 - 80022a4: 68bb ldr r3, [r7, #8] - 80022a6: 681b ldr r3, [r3, #0] - 80022a8: f003 0301 and.w r3, r3, #1 - 80022ac: 2b01 cmp r3, #1 - 80022ae: d101 bne.n 80022b4 - 80022b0: 2301 movs r3, #1 - 80022b2: e000 b.n 80022b6 - 80022b4: 2300 movs r3, #0 + 80022d0: 68bb ldr r3, [r7, #8] + 80022d2: 689b ldr r3, [r3, #8] + 80022d4: f003 0303 and.w r3, r3, #3 + 80022d8: 2b01 cmp r3, #1 + 80022da: d107 bne.n 80022ec + 80022dc: 68bb ldr r3, [r7, #8] + 80022de: 681b ldr r3, [r3, #0] + 80022e0: f003 0301 and.w r3, r3, #1 + 80022e4: 2b01 cmp r3, #1 + 80022e6: d101 bne.n 80022ec + 80022e8: 2301 movs r3, #1 + 80022ea: e000 b.n 80022ee + 80022ec: 2300 movs r3, #0 if ((ADC_IS_ENABLE(hadc) == RESET) && - 80022b6: 2b00 cmp r3, #0 - 80022b8: d112 bne.n 80022e0 + 80022ee: 2b00 cmp r3, #0 + 80022f0: d112 bne.n 8002318 { CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_MULTI | ADC_CCR_DELAY); - 80022ba: 6dbb ldr r3, [r7, #88] @ 0x58 - 80022bc: 689b ldr r3, [r3, #8] - 80022be: f423 6371 bic.w r3, r3, #3856 @ 0xf10 - 80022c2: f023 030f bic.w r3, r3, #15 - 80022c6: 6dba ldr r2, [r7, #88] @ 0x58 - 80022c8: 6093 str r3, [r2, #8] + 80022f2: 6dbb ldr r3, [r7, #88] @ 0x58 + 80022f4: 689b ldr r3, [r3, #8] + 80022f6: f423 6371 bic.w r3, r3, #3856 @ 0xf10 + 80022fa: f023 030f bic.w r3, r3, #15 + 80022fe: 6dba ldr r2, [r7, #88] @ 0x58 + 8002300: 6093 str r3, [r2, #8] if(multimode->Mode != ADC_MODE_INDEPENDENT) - 80022ca: e009 b.n 80022e0 + 8002302: e009 b.n 8002318 /* If one of the ADC sharing the same common group is enabled, no update */ /* could be done on neither of the multimode structure parameters. */ else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - 80022cc: 687b ldr r3, [r7, #4] - 80022ce: 6c1b ldr r3, [r3, #64] @ 0x40 - 80022d0: f043 0220 orr.w r2, r3, #32 - 80022d4: 687b ldr r3, [r7, #4] - 80022d6: 641a str r2, [r3, #64] @ 0x40 + 8002304: 687b ldr r3, [r7, #4] + 8002306: 6c1b ldr r3, [r3, #64] @ 0x40 + 8002308: f043 0220 orr.w r2, r3, #32 + 800230c: 687b ldr r3, [r7, #4] + 800230e: 641a str r2, [r3, #64] @ 0x40 tmp_hal_status = HAL_ERROR; - 80022d8: 2301 movs r3, #1 - 80022da: f887 305f strb.w r3, [r7, #95] @ 0x5f - 80022de: e000 b.n 80022e2 + 8002310: 2301 movs r3, #1 + 8002312: f887 305f strb.w r3, [r7, #95] @ 0x5f + 8002316: e000 b.n 800231a if(multimode->Mode != ADC_MODE_INDEPENDENT) - 80022e0: bf00 nop + 8002318: bf00 nop } /* Process unlocked */ __HAL_UNLOCK(hadc); - 80022e2: 687b ldr r3, [r7, #4] - 80022e4: 2200 movs r2, #0 - 80022e6: f883 203c strb.w r2, [r3, #60] @ 0x3c + 800231a: 687b ldr r3, [r7, #4] + 800231c: 2200 movs r2, #0 + 800231e: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Return function status */ return tmp_hal_status; - 80022ea: f897 305f ldrb.w r3, [r7, #95] @ 0x5f + 8002322: f897 305f ldrb.w r3, [r7, #95] @ 0x5f } - 80022ee: 4618 mov r0, r3 - 80022f0: 3764 adds r7, #100 @ 0x64 - 80022f2: 46bd mov sp, r7 - 80022f4: f85d 7b04 ldr.w r7, [sp], #4 - 80022f8: 4770 bx lr - 80022fa: bf00 nop - 80022fc: 50000100 .word 0x50000100 - 8002300: 50000300 .word 0x50000300 + 8002326: 4618 mov r0, r3 + 8002328: 3764 adds r7, #100 @ 0x64 + 800232a: 46bd mov sp, r7 + 800232c: f85d 7b04 ldr.w r7, [sp], #4 + 8002330: 4770 bx lr + 8002332: bf00 nop + 8002334: 50000100 .word 0x50000100 + 8002338: 50000300 .word 0x50000300 -08002304 : +0800233c : * stopped. * @param hadc ADC handle * @retval HAL status. */ static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc) { - 8002304: b580 push {r7, lr} - 8002306: b084 sub sp, #16 - 8002308: af00 add r7, sp, #0 - 800230a: 6078 str r0, [r7, #4] + 800233c: b580 push {r7, lr} + 800233e: b084 sub sp, #16 + 8002340: af00 add r7, sp, #0 + 8002342: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; - 800230c: 2300 movs r3, #0 - 800230e: 60fb str r3, [r7, #12] + 8002344: 2300 movs r3, #0 + 8002346: 60fb str r3, [r7, #12] /* Verification if ADC is not already disabled: */ /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */ /* disabled. */ if (ADC_IS_ENABLE(hadc) != RESET ) - 8002310: 687b ldr r3, [r7, #4] - 8002312: 681b ldr r3, [r3, #0] - 8002314: 689b ldr r3, [r3, #8] - 8002316: f003 0303 and.w r3, r3, #3 - 800231a: 2b01 cmp r3, #1 - 800231c: d108 bne.n 8002330 - 800231e: 687b ldr r3, [r7, #4] - 8002320: 681b ldr r3, [r3, #0] - 8002322: 681b ldr r3, [r3, #0] - 8002324: f003 0301 and.w r3, r3, #1 - 8002328: 2b01 cmp r3, #1 - 800232a: d101 bne.n 8002330 - 800232c: 2301 movs r3, #1 - 800232e: e000 b.n 8002332 - 8002330: 2300 movs r3, #0 - 8002332: 2b00 cmp r3, #0 - 8002334: d047 beq.n 80023c6 + 8002348: 687b ldr r3, [r7, #4] + 800234a: 681b ldr r3, [r3, #0] + 800234c: 689b ldr r3, [r3, #8] + 800234e: f003 0303 and.w r3, r3, #3 + 8002352: 2b01 cmp r3, #1 + 8002354: d108 bne.n 8002368 + 8002356: 687b ldr r3, [r7, #4] + 8002358: 681b ldr r3, [r3, #0] + 800235a: 681b ldr r3, [r3, #0] + 800235c: f003 0301 and.w r3, r3, #1 + 8002360: 2b01 cmp r3, #1 + 8002362: d101 bne.n 8002368 + 8002364: 2301 movs r3, #1 + 8002366: e000 b.n 800236a + 8002368: 2300 movs r3, #0 + 800236a: 2b00 cmp r3, #0 + 800236c: d047 beq.n 80023fe { /* Check if conditions to disable the ADC are fulfilled */ if (ADC_DISABLING_CONDITIONS(hadc) != RESET) - 8002336: 687b ldr r3, [r7, #4] - 8002338: 681b ldr r3, [r3, #0] - 800233a: 689b ldr r3, [r3, #8] - 800233c: f003 030d and.w r3, r3, #13 - 8002340: 2b01 cmp r3, #1 - 8002342: d10f bne.n 8002364 + 800236e: 687b ldr r3, [r7, #4] + 8002370: 681b ldr r3, [r3, #0] + 8002372: 689b ldr r3, [r3, #8] + 8002374: f003 030d and.w r3, r3, #13 + 8002378: 2b01 cmp r3, #1 + 800237a: d10f bne.n 800239c { /* Disable the ADC peripheral */ __HAL_ADC_DISABLE(hadc); - 8002344: 687b ldr r3, [r7, #4] - 8002346: 681b ldr r3, [r3, #0] - 8002348: 689a ldr r2, [r3, #8] - 800234a: 687b ldr r3, [r7, #4] - 800234c: 681b ldr r3, [r3, #0] - 800234e: f042 0202 orr.w r2, r2, #2 - 8002352: 609a str r2, [r3, #8] - 8002354: 687b ldr r3, [r7, #4] - 8002356: 681b ldr r3, [r3, #0] - 8002358: 2203 movs r2, #3 - 800235a: 601a str r2, [r3, #0] + 800237c: 687b ldr r3, [r7, #4] + 800237e: 681b ldr r3, [r3, #0] + 8002380: 689a ldr r2, [r3, #8] + 8002382: 687b ldr r3, [r7, #4] + 8002384: 681b ldr r3, [r3, #0] + 8002386: f042 0202 orr.w r2, r2, #2 + 800238a: 609a str r2, [r3, #8] + 800238c: 687b ldr r3, [r7, #4] + 800238e: 681b ldr r3, [r3, #0] + 8002390: 2203 movs r2, #3 + 8002392: 601a str r2, [r3, #0] return HAL_ERROR; } /* Wait for ADC effectively disabled */ tickstart = HAL_GetTick(); - 800235c: f7ff f84c bl 80013f8 - 8002360: 60f8 str r0, [r7, #12] + 8002394: f7ff f84c bl 8001430 + 8002398: 60f8 str r0, [r7, #12] while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN)) - 8002362: e029 b.n 80023b8 + 800239a: e029 b.n 80023f0 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - 8002364: 687b ldr r3, [r7, #4] - 8002366: 6c1b ldr r3, [r3, #64] @ 0x40 - 8002368: f043 0210 orr.w r2, r3, #16 - 800236c: 687b ldr r3, [r7, #4] - 800236e: 641a str r2, [r3, #64] @ 0x40 - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - 8002370: 687b ldr r3, [r7, #4] - 8002372: 6c5b ldr r3, [r3, #68] @ 0x44 - 8002374: f043 0201 orr.w r2, r3, #1 - 8002378: 687b ldr r3, [r7, #4] - 800237a: 645a str r2, [r3, #68] @ 0x44 - return HAL_ERROR; - 800237c: 2301 movs r3, #1 - 800237e: e023 b.n 80023c8 - { - if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) - 8002380: f7ff f83a bl 80013f8 - 8002384: 4602 mov r2, r0 - 8002386: 68fb ldr r3, [r7, #12] - 8002388: 1ad3 subs r3, r2, r3 - 800238a: 2b02 cmp r3, #2 - 800238c: d914 bls.n 80023b8 - { - /* New check to avoid false timeout detection in case of preemption */ - if(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN)) - 800238e: 687b ldr r3, [r7, #4] - 8002390: 681b ldr r3, [r3, #0] - 8002392: 689b ldr r3, [r3, #8] - 8002394: f003 0301 and.w r3, r3, #1 - 8002398: 2b01 cmp r3, #1 - 800239a: d10d bne.n 80023b8 - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 800239c: 687b ldr r3, [r7, #4] 800239e: 6c1b ldr r3, [r3, #64] @ 0x40 80023a0: f043 0210 orr.w r2, r3, #16 80023a4: 687b ldr r3, [r7, #4] 80023a6: 641a str r2, [r3, #64] @ 0x40 - - /* Set ADC error code to ADC IP internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 80023a8: 687b ldr r3, [r7, #4] 80023aa: 6c5b ldr r3, [r3, #68] @ 0x44 80023ac: f043 0201 orr.w r2, r3, #1 80023b0: 687b ldr r3, [r7, #4] 80023b2: 645a str r2, [r3, #68] @ 0x44 + return HAL_ERROR; + 80023b4: 2301 movs r3, #1 + 80023b6: e023 b.n 8002400 + { + if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) + 80023b8: f7ff f83a bl 8001430 + 80023bc: 4602 mov r2, r0 + 80023be: 68fb ldr r3, [r7, #12] + 80023c0: 1ad3 subs r3, r2, r3 + 80023c2: 2b02 cmp r3, #2 + 80023c4: d914 bls.n 80023f0 + { + /* New check to avoid false timeout detection in case of preemption */ + if(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN)) + 80023c6: 687b ldr r3, [r7, #4] + 80023c8: 681b ldr r3, [r3, #0] + 80023ca: 689b ldr r3, [r3, #8] + 80023cc: f003 0301 and.w r3, r3, #1 + 80023d0: 2b01 cmp r3, #1 + 80023d2: d10d bne.n 80023f0 + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + 80023d4: 687b ldr r3, [r7, #4] + 80023d6: 6c1b ldr r3, [r3, #64] @ 0x40 + 80023d8: f043 0210 orr.w r2, r3, #16 + 80023dc: 687b ldr r3, [r7, #4] + 80023de: 641a str r2, [r3, #64] @ 0x40 + + /* Set ADC error code to ADC IP internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + 80023e0: 687b ldr r3, [r7, #4] + 80023e2: 6c5b ldr r3, [r3, #68] @ 0x44 + 80023e4: f043 0201 orr.w r2, r3, #1 + 80023e8: 687b ldr r3, [r7, #4] + 80023ea: 645a str r2, [r3, #68] @ 0x44 return HAL_ERROR; - 80023b4: 2301 movs r3, #1 - 80023b6: e007 b.n 80023c8 + 80023ec: 2301 movs r3, #1 + 80023ee: e007 b.n 8002400 while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN)) - 80023b8: 687b ldr r3, [r7, #4] - 80023ba: 681b ldr r3, [r3, #0] - 80023bc: 689b ldr r3, [r3, #8] - 80023be: f003 0301 and.w r3, r3, #1 - 80023c2: 2b01 cmp r3, #1 - 80023c4: d0dc beq.n 8002380 + 80023f0: 687b ldr r3, [r7, #4] + 80023f2: 681b ldr r3, [r3, #0] + 80023f4: 689b ldr r3, [r3, #8] + 80023f6: f003 0301 and.w r3, r3, #1 + 80023fa: 2b01 cmp r3, #1 + 80023fc: d0dc beq.n 80023b8 } } } /* Return HAL status */ return HAL_OK; - 80023c6: 2300 movs r3, #0 + 80023fe: 2300 movs r3, #0 } - 80023c8: 4618 mov r0, r3 - 80023ca: 3710 adds r7, #16 - 80023cc: 46bd mov sp, r7 - 80023ce: bd80 pop {r7, pc} + 8002400: 4618 mov r0, r3 + 8002402: 3710 adds r7, #16 + 8002404: 46bd mov sp, r7 + 8002406: bd80 pop {r7, pc} -080023d0 : +08002408 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan) { - 80023d0: b580 push {r7, lr} - 80023d2: b084 sub sp, #16 - 80023d4: af00 add r7, sp, #0 - 80023d6: 6078 str r0, [r7, #4] + 8002408: b580 push {r7, lr} + 800240a: b084 sub sp, #16 + 800240c: af00 add r7, sp, #0 + 800240e: 6078 str r0, [r7, #4] uint32_t tickstart; /* Check CAN handle */ if (hcan == NULL) - 80023d8: 687b ldr r3, [r7, #4] - 80023da: 2b00 cmp r3, #0 - 80023dc: d101 bne.n 80023e2 + 8002410: 687b ldr r3, [r7, #4] + 8002412: 2b00 cmp r3, #0 + 8002414: d101 bne.n 800241a { return HAL_ERROR; - 80023de: 2301 movs r3, #1 - 80023e0: e0ed b.n 80025be + 8002416: 2301 movs r3, #1 + 8002418: e0ed b.n 80025f6 /* Init the low level hardware: CLOCK, NVIC */ hcan->MspInitCallback(hcan); } #else if (hcan->State == HAL_CAN_STATE_RESET) - 80023e2: 687b ldr r3, [r7, #4] - 80023e4: f893 3020 ldrb.w r3, [r3, #32] - 80023e8: b2db uxtb r3, r3 - 80023ea: 2b00 cmp r3, #0 - 80023ec: d102 bne.n 80023f4 + 800241a: 687b ldr r3, [r7, #4] + 800241c: f893 3020 ldrb.w r3, [r3, #32] + 8002420: b2db uxtb r3, r3 + 8002422: 2b00 cmp r3, #0 + 8002424: d102 bne.n 800242c { /* Init the low level hardware: CLOCK, NVIC */ HAL_CAN_MspInit(hcan); - 80023ee: 6878 ldr r0, [r7, #4] - 80023f0: f7fe fe3e bl 8001070 + 8002426: 6878 ldr r0, [r7, #4] + 8002428: f7fe fe3e bl 80010a8 } #endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */ /* Request initialisation */ SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); - 80023f4: 687b ldr r3, [r7, #4] - 80023f6: 681b ldr r3, [r3, #0] - 80023f8: 681a ldr r2, [r3, #0] - 80023fa: 687b ldr r3, [r7, #4] - 80023fc: 681b ldr r3, [r3, #0] - 80023fe: f042 0201 orr.w r2, r2, #1 - 8002402: 601a str r2, [r3, #0] + 800242c: 687b ldr r3, [r7, #4] + 800242e: 681b ldr r3, [r3, #0] + 8002430: 681a ldr r2, [r3, #0] + 8002432: 687b ldr r3, [r7, #4] + 8002434: 681b ldr r3, [r3, #0] + 8002436: f042 0201 orr.w r2, r2, #1 + 800243a: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); - 8002404: f7fe fff8 bl 80013f8 - 8002408: 60f8 str r0, [r7, #12] + 800243c: f7fe fff8 bl 8001430 + 8002440: 60f8 str r0, [r7, #12] /* Wait initialisation acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) - 800240a: e012 b.n 8002432 + 8002442: e012 b.n 800246a { if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) - 800240c: f7fe fff4 bl 80013f8 - 8002410: 4602 mov r2, r0 - 8002412: 68fb ldr r3, [r7, #12] - 8002414: 1ad3 subs r3, r2, r3 - 8002416: 2b0a cmp r3, #10 - 8002418: d90b bls.n 8002432 + 8002444: f7fe fff4 bl 8001430 + 8002448: 4602 mov r2, r0 + 800244a: 68fb ldr r3, [r7, #12] + 800244c: 1ad3 subs r3, r2, r3 + 800244e: 2b0a cmp r3, #10 + 8002450: d90b bls.n 800246a { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; - 800241a: 687b ldr r3, [r7, #4] - 800241c: 6a5b ldr r3, [r3, #36] @ 0x24 - 800241e: f443 3200 orr.w r2, r3, #131072 @ 0x20000 - 8002422: 687b ldr r3, [r7, #4] - 8002424: 625a str r2, [r3, #36] @ 0x24 + 8002452: 687b ldr r3, [r7, #4] + 8002454: 6a5b ldr r3, [r3, #36] @ 0x24 + 8002456: f443 3200 orr.w r2, r3, #131072 @ 0x20000 + 800245a: 687b ldr r3, [r7, #4] + 800245c: 625a str r2, [r3, #36] @ 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; - 8002426: 687b ldr r3, [r7, #4] - 8002428: 2205 movs r2, #5 - 800242a: f883 2020 strb.w r2, [r3, #32] + 800245e: 687b ldr r3, [r7, #4] + 8002460: 2205 movs r2, #5 + 8002462: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; - 800242e: 2301 movs r3, #1 - 8002430: e0c5 b.n 80025be + 8002466: 2301 movs r3, #1 + 8002468: e0c5 b.n 80025f6 while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) - 8002432: 687b ldr r3, [r7, #4] - 8002434: 681b ldr r3, [r3, #0] - 8002436: 685b ldr r3, [r3, #4] - 8002438: f003 0301 and.w r3, r3, #1 - 800243c: 2b00 cmp r3, #0 - 800243e: d0e5 beq.n 800240c + 800246a: 687b ldr r3, [r7, #4] + 800246c: 681b ldr r3, [r3, #0] + 800246e: 685b ldr r3, [r3, #4] + 8002470: f003 0301 and.w r3, r3, #1 + 8002474: 2b00 cmp r3, #0 + 8002476: d0e5 beq.n 8002444 } } /* Exit from sleep mode */ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); - 8002440: 687b ldr r3, [r7, #4] - 8002442: 681b ldr r3, [r3, #0] - 8002444: 681a ldr r2, [r3, #0] - 8002446: 687b ldr r3, [r7, #4] - 8002448: 681b ldr r3, [r3, #0] - 800244a: f022 0202 bic.w r2, r2, #2 - 800244e: 601a str r2, [r3, #0] + 8002478: 687b ldr r3, [r7, #4] + 800247a: 681b ldr r3, [r3, #0] + 800247c: 681a ldr r2, [r3, #0] + 800247e: 687b ldr r3, [r7, #4] + 8002480: 681b ldr r3, [r3, #0] + 8002482: f022 0202 bic.w r2, r2, #2 + 8002486: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); - 8002450: f7fe ffd2 bl 80013f8 - 8002454: 60f8 str r0, [r7, #12] + 8002488: f7fe ffd2 bl 8001430 + 800248c: 60f8 str r0, [r7, #12] /* Check Sleep mode leave acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) - 8002456: e012 b.n 800247e + 800248e: e012 b.n 80024b6 { if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) - 8002458: f7fe ffce bl 80013f8 - 800245c: 4602 mov r2, r0 - 800245e: 68fb ldr r3, [r7, #12] - 8002460: 1ad3 subs r3, r2, r3 - 8002462: 2b0a cmp r3, #10 - 8002464: d90b bls.n 800247e + 8002490: f7fe ffce bl 8001430 + 8002494: 4602 mov r2, r0 + 8002496: 68fb ldr r3, [r7, #12] + 8002498: 1ad3 subs r3, r2, r3 + 800249a: 2b0a cmp r3, #10 + 800249c: d90b bls.n 80024b6 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; - 8002466: 687b ldr r3, [r7, #4] - 8002468: 6a5b ldr r3, [r3, #36] @ 0x24 - 800246a: f443 3200 orr.w r2, r3, #131072 @ 0x20000 - 800246e: 687b ldr r3, [r7, #4] - 8002470: 625a str r2, [r3, #36] @ 0x24 + 800249e: 687b ldr r3, [r7, #4] + 80024a0: 6a5b ldr r3, [r3, #36] @ 0x24 + 80024a2: f443 3200 orr.w r2, r3, #131072 @ 0x20000 + 80024a6: 687b ldr r3, [r7, #4] + 80024a8: 625a str r2, [r3, #36] @ 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; - 8002472: 687b ldr r3, [r7, #4] - 8002474: 2205 movs r2, #5 - 8002476: f883 2020 strb.w r2, [r3, #32] + 80024aa: 687b ldr r3, [r7, #4] + 80024ac: 2205 movs r2, #5 + 80024ae: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; - 800247a: 2301 movs r3, #1 - 800247c: e09f b.n 80025be + 80024b2: 2301 movs r3, #1 + 80024b4: e09f b.n 80025f6 while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) - 800247e: 687b ldr r3, [r7, #4] - 8002480: 681b ldr r3, [r3, #0] - 8002482: 685b ldr r3, [r3, #4] - 8002484: f003 0302 and.w r3, r3, #2 - 8002488: 2b00 cmp r3, #0 - 800248a: d1e5 bne.n 8002458 + 80024b6: 687b ldr r3, [r7, #4] + 80024b8: 681b ldr r3, [r3, #0] + 80024ba: 685b ldr r3, [r3, #4] + 80024bc: f003 0302 and.w r3, r3, #2 + 80024c0: 2b00 cmp r3, #0 + 80024c2: d1e5 bne.n 8002490 } } /* Set the time triggered communication mode */ if (hcan->Init.TimeTriggeredMode == ENABLE) - 800248c: 687b ldr r3, [r7, #4] - 800248e: 7e1b ldrb r3, [r3, #24] - 8002490: 2b01 cmp r3, #1 - 8002492: d108 bne.n 80024a6 + 80024c4: 687b ldr r3, [r7, #4] + 80024c6: 7e1b ldrb r3, [r3, #24] + 80024c8: 2b01 cmp r3, #1 + 80024ca: d108 bne.n 80024de { SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); - 8002494: 687b ldr r3, [r7, #4] - 8002496: 681b ldr r3, [r3, #0] - 8002498: 681a ldr r2, [r3, #0] - 800249a: 687b ldr r3, [r7, #4] - 800249c: 681b ldr r3, [r3, #0] - 800249e: f042 0280 orr.w r2, r2, #128 @ 0x80 - 80024a2: 601a str r2, [r3, #0] - 80024a4: e007 b.n 80024b6 + 80024cc: 687b ldr r3, [r7, #4] + 80024ce: 681b ldr r3, [r3, #0] + 80024d0: 681a ldr r2, [r3, #0] + 80024d2: 687b ldr r3, [r7, #4] + 80024d4: 681b ldr r3, [r3, #0] + 80024d6: f042 0280 orr.w r2, r2, #128 @ 0x80 + 80024da: 601a str r2, [r3, #0] + 80024dc: e007 b.n 80024ee } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); - 80024a6: 687b ldr r3, [r7, #4] - 80024a8: 681b ldr r3, [r3, #0] - 80024aa: 681a ldr r2, [r3, #0] - 80024ac: 687b ldr r3, [r7, #4] - 80024ae: 681b ldr r3, [r3, #0] - 80024b0: f022 0280 bic.w r2, r2, #128 @ 0x80 - 80024b4: 601a str r2, [r3, #0] + 80024de: 687b ldr r3, [r7, #4] + 80024e0: 681b ldr r3, [r3, #0] + 80024e2: 681a ldr r2, [r3, #0] + 80024e4: 687b ldr r3, [r7, #4] + 80024e6: 681b ldr r3, [r3, #0] + 80024e8: f022 0280 bic.w r2, r2, #128 @ 0x80 + 80024ec: 601a str r2, [r3, #0] } /* Set the automatic bus-off management */ if (hcan->Init.AutoBusOff == ENABLE) - 80024b6: 687b ldr r3, [r7, #4] - 80024b8: 7e5b ldrb r3, [r3, #25] - 80024ba: 2b01 cmp r3, #1 - 80024bc: d108 bne.n 80024d0 + 80024ee: 687b ldr r3, [r7, #4] + 80024f0: 7e5b ldrb r3, [r3, #25] + 80024f2: 2b01 cmp r3, #1 + 80024f4: d108 bne.n 8002508 { SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); - 80024be: 687b ldr r3, [r7, #4] - 80024c0: 681b ldr r3, [r3, #0] - 80024c2: 681a ldr r2, [r3, #0] - 80024c4: 687b ldr r3, [r7, #4] - 80024c6: 681b ldr r3, [r3, #0] - 80024c8: f042 0240 orr.w r2, r2, #64 @ 0x40 - 80024cc: 601a str r2, [r3, #0] - 80024ce: e007 b.n 80024e0 + 80024f6: 687b ldr r3, [r7, #4] + 80024f8: 681b ldr r3, [r3, #0] + 80024fa: 681a ldr r2, [r3, #0] + 80024fc: 687b ldr r3, [r7, #4] + 80024fe: 681b ldr r3, [r3, #0] + 8002500: f042 0240 orr.w r2, r2, #64 @ 0x40 + 8002504: 601a str r2, [r3, #0] + 8002506: e007 b.n 8002518 } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); - 80024d0: 687b ldr r3, [r7, #4] - 80024d2: 681b ldr r3, [r3, #0] - 80024d4: 681a ldr r2, [r3, #0] - 80024d6: 687b ldr r3, [r7, #4] - 80024d8: 681b ldr r3, [r3, #0] - 80024da: f022 0240 bic.w r2, r2, #64 @ 0x40 - 80024de: 601a str r2, [r3, #0] + 8002508: 687b ldr r3, [r7, #4] + 800250a: 681b ldr r3, [r3, #0] + 800250c: 681a ldr r2, [r3, #0] + 800250e: 687b ldr r3, [r7, #4] + 8002510: 681b ldr r3, [r3, #0] + 8002512: f022 0240 bic.w r2, r2, #64 @ 0x40 + 8002516: 601a str r2, [r3, #0] } /* Set the automatic wake-up mode */ if (hcan->Init.AutoWakeUp == ENABLE) - 80024e0: 687b ldr r3, [r7, #4] - 80024e2: 7e9b ldrb r3, [r3, #26] - 80024e4: 2b01 cmp r3, #1 - 80024e6: d108 bne.n 80024fa + 8002518: 687b ldr r3, [r7, #4] + 800251a: 7e9b ldrb r3, [r3, #26] + 800251c: 2b01 cmp r3, #1 + 800251e: d108 bne.n 8002532 { SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); - 80024e8: 687b ldr r3, [r7, #4] - 80024ea: 681b ldr r3, [r3, #0] - 80024ec: 681a ldr r2, [r3, #0] - 80024ee: 687b ldr r3, [r7, #4] - 80024f0: 681b ldr r3, [r3, #0] - 80024f2: f042 0220 orr.w r2, r2, #32 - 80024f6: 601a str r2, [r3, #0] - 80024f8: e007 b.n 800250a + 8002520: 687b ldr r3, [r7, #4] + 8002522: 681b ldr r3, [r3, #0] + 8002524: 681a ldr r2, [r3, #0] + 8002526: 687b ldr r3, [r7, #4] + 8002528: 681b ldr r3, [r3, #0] + 800252a: f042 0220 orr.w r2, r2, #32 + 800252e: 601a str r2, [r3, #0] + 8002530: e007 b.n 8002542 } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); - 80024fa: 687b ldr r3, [r7, #4] - 80024fc: 681b ldr r3, [r3, #0] - 80024fe: 681a ldr r2, [r3, #0] - 8002500: 687b ldr r3, [r7, #4] - 8002502: 681b ldr r3, [r3, #0] - 8002504: f022 0220 bic.w r2, r2, #32 - 8002508: 601a str r2, [r3, #0] + 8002532: 687b ldr r3, [r7, #4] + 8002534: 681b ldr r3, [r3, #0] + 8002536: 681a ldr r2, [r3, #0] + 8002538: 687b ldr r3, [r7, #4] + 800253a: 681b ldr r3, [r3, #0] + 800253c: f022 0220 bic.w r2, r2, #32 + 8002540: 601a str r2, [r3, #0] } /* Set the automatic retransmission */ if (hcan->Init.AutoRetransmission == ENABLE) - 800250a: 687b ldr r3, [r7, #4] - 800250c: 7edb ldrb r3, [r3, #27] - 800250e: 2b01 cmp r3, #1 - 8002510: d108 bne.n 8002524 + 8002542: 687b ldr r3, [r7, #4] + 8002544: 7edb ldrb r3, [r3, #27] + 8002546: 2b01 cmp r3, #1 + 8002548: d108 bne.n 800255c { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART); - 8002512: 687b ldr r3, [r7, #4] - 8002514: 681b ldr r3, [r3, #0] - 8002516: 681a ldr r2, [r3, #0] - 8002518: 687b ldr r3, [r7, #4] - 800251a: 681b ldr r3, [r3, #0] - 800251c: f022 0210 bic.w r2, r2, #16 - 8002520: 601a str r2, [r3, #0] - 8002522: e007 b.n 8002534 + 800254a: 687b ldr r3, [r7, #4] + 800254c: 681b ldr r3, [r3, #0] + 800254e: 681a ldr r2, [r3, #0] + 8002550: 687b ldr r3, [r7, #4] + 8002552: 681b ldr r3, [r3, #0] + 8002554: f022 0210 bic.w r2, r2, #16 + 8002558: 601a str r2, [r3, #0] + 800255a: e007 b.n 800256c } else { SET_BIT(hcan->Instance->MCR, CAN_MCR_NART); - 8002524: 687b ldr r3, [r7, #4] - 8002526: 681b ldr r3, [r3, #0] - 8002528: 681a ldr r2, [r3, #0] - 800252a: 687b ldr r3, [r7, #4] - 800252c: 681b ldr r3, [r3, #0] - 800252e: f042 0210 orr.w r2, r2, #16 - 8002532: 601a str r2, [r3, #0] + 800255c: 687b ldr r3, [r7, #4] + 800255e: 681b ldr r3, [r3, #0] + 8002560: 681a ldr r2, [r3, #0] + 8002562: 687b ldr r3, [r7, #4] + 8002564: 681b ldr r3, [r3, #0] + 8002566: f042 0210 orr.w r2, r2, #16 + 800256a: 601a str r2, [r3, #0] } /* Set the receive FIFO locked mode */ if (hcan->Init.ReceiveFifoLocked == ENABLE) - 8002534: 687b ldr r3, [r7, #4] - 8002536: 7f1b ldrb r3, [r3, #28] - 8002538: 2b01 cmp r3, #1 - 800253a: d108 bne.n 800254e + 800256c: 687b ldr r3, [r7, #4] + 800256e: 7f1b ldrb r3, [r3, #28] + 8002570: 2b01 cmp r3, #1 + 8002572: d108 bne.n 8002586 { SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); - 800253c: 687b ldr r3, [r7, #4] - 800253e: 681b ldr r3, [r3, #0] - 8002540: 681a ldr r2, [r3, #0] - 8002542: 687b ldr r3, [r7, #4] - 8002544: 681b ldr r3, [r3, #0] - 8002546: f042 0208 orr.w r2, r2, #8 - 800254a: 601a str r2, [r3, #0] - 800254c: e007 b.n 800255e + 8002574: 687b ldr r3, [r7, #4] + 8002576: 681b ldr r3, [r3, #0] + 8002578: 681a ldr r2, [r3, #0] + 800257a: 687b ldr r3, [r7, #4] + 800257c: 681b ldr r3, [r3, #0] + 800257e: f042 0208 orr.w r2, r2, #8 + 8002582: 601a str r2, [r3, #0] + 8002584: e007 b.n 8002596 } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); - 800254e: 687b ldr r3, [r7, #4] - 8002550: 681b ldr r3, [r3, #0] - 8002552: 681a ldr r2, [r3, #0] - 8002554: 687b ldr r3, [r7, #4] - 8002556: 681b ldr r3, [r3, #0] - 8002558: f022 0208 bic.w r2, r2, #8 - 800255c: 601a str r2, [r3, #0] + 8002586: 687b ldr r3, [r7, #4] + 8002588: 681b ldr r3, [r3, #0] + 800258a: 681a ldr r2, [r3, #0] + 800258c: 687b ldr r3, [r7, #4] + 800258e: 681b ldr r3, [r3, #0] + 8002590: f022 0208 bic.w r2, r2, #8 + 8002594: 601a str r2, [r3, #0] } /* Set the transmit FIFO priority */ if (hcan->Init.TransmitFifoPriority == ENABLE) - 800255e: 687b ldr r3, [r7, #4] - 8002560: 7f5b ldrb r3, [r3, #29] - 8002562: 2b01 cmp r3, #1 - 8002564: d108 bne.n 8002578 + 8002596: 687b ldr r3, [r7, #4] + 8002598: 7f5b ldrb r3, [r3, #29] + 800259a: 2b01 cmp r3, #1 + 800259c: d108 bne.n 80025b0 { SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); - 8002566: 687b ldr r3, [r7, #4] - 8002568: 681b ldr r3, [r3, #0] - 800256a: 681a ldr r2, [r3, #0] - 800256c: 687b ldr r3, [r7, #4] - 800256e: 681b ldr r3, [r3, #0] - 8002570: f042 0204 orr.w r2, r2, #4 - 8002574: 601a str r2, [r3, #0] - 8002576: e007 b.n 8002588 + 800259e: 687b ldr r3, [r7, #4] + 80025a0: 681b ldr r3, [r3, #0] + 80025a2: 681a ldr r2, [r3, #0] + 80025a4: 687b ldr r3, [r7, #4] + 80025a6: 681b ldr r3, [r3, #0] + 80025a8: f042 0204 orr.w r2, r2, #4 + 80025ac: 601a str r2, [r3, #0] + 80025ae: e007 b.n 80025c0 } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); - 8002578: 687b ldr r3, [r7, #4] - 800257a: 681b ldr r3, [r3, #0] - 800257c: 681a ldr r2, [r3, #0] - 800257e: 687b ldr r3, [r7, #4] - 8002580: 681b ldr r3, [r3, #0] - 8002582: f022 0204 bic.w r2, r2, #4 - 8002586: 601a str r2, [r3, #0] + 80025b0: 687b ldr r3, [r7, #4] + 80025b2: 681b ldr r3, [r3, #0] + 80025b4: 681a ldr r2, [r3, #0] + 80025b6: 687b ldr r3, [r7, #4] + 80025b8: 681b ldr r3, [r3, #0] + 80025ba: f022 0204 bic.w r2, r2, #4 + 80025be: 601a str r2, [r3, #0] } /* Set the bit timing register */ WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode | - 8002588: 687b ldr r3, [r7, #4] - 800258a: 689a ldr r2, [r3, #8] - 800258c: 687b ldr r3, [r7, #4] - 800258e: 68db ldr r3, [r3, #12] - 8002590: 431a orrs r2, r3 - 8002592: 687b ldr r3, [r7, #4] - 8002594: 691b ldr r3, [r3, #16] - 8002596: 431a orrs r2, r3 - 8002598: 687b ldr r3, [r7, #4] - 800259a: 695b ldr r3, [r3, #20] - 800259c: ea42 0103 orr.w r1, r2, r3 - 80025a0: 687b ldr r3, [r7, #4] - 80025a2: 685b ldr r3, [r3, #4] - 80025a4: 1e5a subs r2, r3, #1 - 80025a6: 687b ldr r3, [r7, #4] - 80025a8: 681b ldr r3, [r3, #0] - 80025aa: 430a orrs r2, r1 - 80025ac: 61da str r2, [r3, #28] + 80025c0: 687b ldr r3, [r7, #4] + 80025c2: 689a ldr r2, [r3, #8] + 80025c4: 687b ldr r3, [r7, #4] + 80025c6: 68db ldr r3, [r3, #12] + 80025c8: 431a orrs r2, r3 + 80025ca: 687b ldr r3, [r7, #4] + 80025cc: 691b ldr r3, [r3, #16] + 80025ce: 431a orrs r2, r3 + 80025d0: 687b ldr r3, [r7, #4] + 80025d2: 695b ldr r3, [r3, #20] + 80025d4: ea42 0103 orr.w r1, r2, r3 + 80025d8: 687b ldr r3, [r7, #4] + 80025da: 685b ldr r3, [r3, #4] + 80025dc: 1e5a subs r2, r3, #1 + 80025de: 687b ldr r3, [r7, #4] + 80025e0: 681b ldr r3, [r3, #0] + 80025e2: 430a orrs r2, r1 + 80025e4: 61da str r2, [r3, #28] hcan->Init.TimeSeg1 | hcan->Init.TimeSeg2 | (hcan->Init.Prescaler - 1U))); /* Initialize the error code */ hcan->ErrorCode = HAL_CAN_ERROR_NONE; - 80025ae: 687b ldr r3, [r7, #4] - 80025b0: 2200 movs r2, #0 - 80025b2: 625a str r2, [r3, #36] @ 0x24 + 80025e6: 687b ldr r3, [r7, #4] + 80025e8: 2200 movs r2, #0 + 80025ea: 625a str r2, [r3, #36] @ 0x24 /* Initialize the CAN state */ hcan->State = HAL_CAN_STATE_READY; - 80025b4: 687b ldr r3, [r7, #4] - 80025b6: 2201 movs r2, #1 - 80025b8: f883 2020 strb.w r2, [r3, #32] + 80025ec: 687b ldr r3, [r7, #4] + 80025ee: 2201 movs r2, #1 + 80025f0: f883 2020 strb.w r2, [r3, #32] /* Return function status */ return HAL_OK; - 80025bc: 2300 movs r3, #0 + 80025f4: 2300 movs r3, #0 } - 80025be: 4618 mov r0, r3 - 80025c0: 3710 adds r7, #16 - 80025c2: 46bd mov sp, r7 - 80025c4: bd80 pop {r7, pc} + 80025f6: 4618 mov r0, r3 + 80025f8: 3710 adds r7, #16 + 80025fa: 46bd mov sp, r7 + 80025fc: bd80 pop {r7, pc} -080025c6 : +080025fe : * @param sFilterConfig pointer to a CAN_FilterTypeDef structure that * contains the filter configuration information. * @retval None */ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_FilterTypeDef *sFilterConfig) { - 80025c6: b480 push {r7} - 80025c8: b087 sub sp, #28 - 80025ca: af00 add r7, sp, #0 - 80025cc: 6078 str r0, [r7, #4] - 80025ce: 6039 str r1, [r7, #0] + 80025fe: b480 push {r7} + 8002600: b087 sub sp, #28 + 8002602: af00 add r7, sp, #0 + 8002604: 6078 str r0, [r7, #4] + 8002606: 6039 str r1, [r7, #0] uint32_t filternbrbitpos; CAN_TypeDef *can_ip = hcan->Instance; - 80025d0: 687b ldr r3, [r7, #4] - 80025d2: 681b ldr r3, [r3, #0] - 80025d4: 617b str r3, [r7, #20] + 8002608: 687b ldr r3, [r7, #4] + 800260a: 681b ldr r3, [r3, #0] + 800260c: 617b str r3, [r7, #20] HAL_CAN_StateTypeDef state = hcan->State; - 80025d6: 687b ldr r3, [r7, #4] - 80025d8: f893 3020 ldrb.w r3, [r3, #32] - 80025dc: 74fb strb r3, [r7, #19] + 800260e: 687b ldr r3, [r7, #4] + 8002610: f893 3020 ldrb.w r3, [r3, #32] + 8002614: 74fb strb r3, [r7, #19] if ((state == HAL_CAN_STATE_READY) || - 80025de: 7cfb ldrb r3, [r7, #19] - 80025e0: 2b01 cmp r3, #1 - 80025e2: d003 beq.n 80025ec - 80025e4: 7cfb ldrb r3, [r7, #19] - 80025e6: 2b02 cmp r3, #2 - 80025e8: f040 80aa bne.w 8002740 + 8002616: 7cfb ldrb r3, [r7, #19] + 8002618: 2b01 cmp r3, #1 + 800261a: d003 beq.n 8002624 + 800261c: 7cfb ldrb r3, [r7, #19] + 800261e: 2b02 cmp r3, #2 + 8002620: f040 80aa bne.w 8002778 /* Check the parameters */ assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank)); /* Initialisation mode for the filter */ SET_BIT(can_ip->FMR, CAN_FMR_FINIT); - 80025ec: 697b ldr r3, [r7, #20] - 80025ee: f8d3 3200 ldr.w r3, [r3, #512] @ 0x200 - 80025f2: f043 0201 orr.w r2, r3, #1 - 80025f6: 697b ldr r3, [r7, #20] - 80025f8: f8c3 2200 str.w r2, [r3, #512] @ 0x200 + 8002624: 697b ldr r3, [r7, #20] + 8002626: f8d3 3200 ldr.w r3, [r3, #512] @ 0x200 + 800262a: f043 0201 orr.w r2, r3, #1 + 800262e: 697b ldr r3, [r7, #20] + 8002630: f8c3 2200 str.w r2, [r3, #512] @ 0x200 /* Convert filter number into bit position */ filternbrbitpos = (uint32_t)1 << (sFilterConfig->FilterBank & 0x1FU); - 80025fc: 683b ldr r3, [r7, #0] - 80025fe: 695b ldr r3, [r3, #20] - 8002600: f003 031f and.w r3, r3, #31 - 8002604: 2201 movs r2, #1 - 8002606: fa02 f303 lsl.w r3, r2, r3 - 800260a: 60fb str r3, [r7, #12] + 8002634: 683b ldr r3, [r7, #0] + 8002636: 695b ldr r3, [r3, #20] + 8002638: f003 031f and.w r3, r3, #31 + 800263c: 2201 movs r2, #1 + 800263e: fa02 f303 lsl.w r3, r2, r3 + 8002642: 60fb str r3, [r7, #12] /* Filter Deactivation */ CLEAR_BIT(can_ip->FA1R, filternbrbitpos); - 800260c: 697b ldr r3, [r7, #20] - 800260e: f8d3 221c ldr.w r2, [r3, #540] @ 0x21c - 8002612: 68fb ldr r3, [r7, #12] - 8002614: 43db mvns r3, r3 - 8002616: 401a ands r2, r3 - 8002618: 697b ldr r3, [r7, #20] - 800261a: f8c3 221c str.w r2, [r3, #540] @ 0x21c + 8002644: 697b ldr r3, [r7, #20] + 8002646: f8d3 221c ldr.w r2, [r3, #540] @ 0x21c + 800264a: 68fb ldr r3, [r7, #12] + 800264c: 43db mvns r3, r3 + 800264e: 401a ands r2, r3 + 8002650: 697b ldr r3, [r7, #20] + 8002652: f8c3 221c str.w r2, [r3, #540] @ 0x21c /* Filter Scale */ if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT) - 800261e: 683b ldr r3, [r7, #0] - 8002620: 69db ldr r3, [r3, #28] - 8002622: 2b00 cmp r3, #0 - 8002624: d123 bne.n 800266e + 8002656: 683b ldr r3, [r7, #0] + 8002658: 69db ldr r3, [r3, #28] + 800265a: 2b00 cmp r3, #0 + 800265c: d123 bne.n 80026a6 { /* 16-bit scale for the filter */ CLEAR_BIT(can_ip->FS1R, filternbrbitpos); - 8002626: 697b ldr r3, [r7, #20] - 8002628: f8d3 220c ldr.w r2, [r3, #524] @ 0x20c - 800262c: 68fb ldr r3, [r7, #12] - 800262e: 43db mvns r3, r3 - 8002630: 401a ands r2, r3 - 8002632: 697b ldr r3, [r7, #20] - 8002634: f8c3 220c str.w r2, [r3, #524] @ 0x20c + 800265e: 697b ldr r3, [r7, #20] + 8002660: f8d3 220c ldr.w r2, [r3, #524] @ 0x20c + 8002664: 68fb ldr r3, [r7, #12] + 8002666: 43db mvns r3, r3 + 8002668: 401a ands r2, r3 + 800266a: 697b ldr r3, [r7, #20] + 800266c: f8c3 220c str.w r2, [r3, #524] @ 0x20c /* First 16-bit identifier and First 16-bit mask */ /* Or First 16-bit identifier and Second 16-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | - 8002638: 683b ldr r3, [r7, #0] - 800263a: 68db ldr r3, [r3, #12] - 800263c: 0419 lsls r1, r3, #16 + 8002670: 683b ldr r3, [r7, #0] + 8002672: 68db ldr r3, [r3, #12] + 8002674: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); - 800263e: 683b ldr r3, [r7, #0] - 8002640: 685b ldr r3, [r3, #4] - 8002642: b29b uxth r3, r3 + 8002676: 683b ldr r3, [r7, #0] + 8002678: 685b ldr r3, [r3, #4] + 800267a: b29b uxth r3, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = - 8002644: 683a ldr r2, [r7, #0] - 8002646: 6952 ldr r2, [r2, #20] + 800267c: 683a ldr r2, [r7, #0] + 800267e: 6952 ldr r2, [r2, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | - 8002648: 4319 orrs r1, r3 + 8002680: 4319 orrs r1, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = - 800264a: 697b ldr r3, [r7, #20] - 800264c: 3248 adds r2, #72 @ 0x48 - 800264e: f843 1032 str.w r1, [r3, r2, lsl #3] + 8002682: 697b ldr r3, [r7, #20] + 8002684: 3248 adds r2, #72 @ 0x48 + 8002686: f843 1032 str.w r1, [r3, r2, lsl #3] /* Second 16-bit identifier and Second 16-bit mask */ /* Or Third 16-bit identifier and Fourth 16-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | - 8002652: 683b ldr r3, [r7, #0] - 8002654: 689b ldr r3, [r3, #8] - 8002656: 0419 lsls r1, r3, #16 + 800268a: 683b ldr r3, [r7, #0] + 800268c: 689b ldr r3, [r3, #8] + 800268e: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh); - 8002658: 683b ldr r3, [r7, #0] - 800265a: 681b ldr r3, [r3, #0] - 800265c: b29a uxth r2, r3 + 8002690: 683b ldr r3, [r7, #0] + 8002692: 681b ldr r3, [r3, #0] + 8002694: b29a uxth r2, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = - 800265e: 683b ldr r3, [r7, #0] - 8002660: 695b ldr r3, [r3, #20] + 8002696: 683b ldr r3, [r7, #0] + 8002698: 695b ldr r3, [r3, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | - 8002662: 430a orrs r2, r1 + 800269a: 430a orrs r2, r1 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = - 8002664: 6979 ldr r1, [r7, #20] - 8002666: 3348 adds r3, #72 @ 0x48 - 8002668: 00db lsls r3, r3, #3 - 800266a: 440b add r3, r1 - 800266c: 605a str r2, [r3, #4] + 800269c: 6979 ldr r1, [r7, #20] + 800269e: 3348 adds r3, #72 @ 0x48 + 80026a0: 00db lsls r3, r3, #3 + 80026a2: 440b add r3, r1 + 80026a4: 605a str r2, [r3, #4] } if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT) - 800266e: 683b ldr r3, [r7, #0] - 8002670: 69db ldr r3, [r3, #28] - 8002672: 2b01 cmp r3, #1 - 8002674: d122 bne.n 80026bc + 80026a6: 683b ldr r3, [r7, #0] + 80026a8: 69db ldr r3, [r3, #28] + 80026aa: 2b01 cmp r3, #1 + 80026ac: d122 bne.n 80026f4 { /* 32-bit scale for the filter */ SET_BIT(can_ip->FS1R, filternbrbitpos); - 8002676: 697b ldr r3, [r7, #20] - 8002678: f8d3 220c ldr.w r2, [r3, #524] @ 0x20c - 800267c: 68fb ldr r3, [r7, #12] - 800267e: 431a orrs r2, r3 - 8002680: 697b ldr r3, [r7, #20] - 8002682: f8c3 220c str.w r2, [r3, #524] @ 0x20c + 80026ae: 697b ldr r3, [r7, #20] + 80026b0: f8d3 220c ldr.w r2, [r3, #524] @ 0x20c + 80026b4: 68fb ldr r3, [r7, #12] + 80026b6: 431a orrs r2, r3 + 80026b8: 697b ldr r3, [r7, #20] + 80026ba: f8c3 220c str.w r2, [r3, #524] @ 0x20c /* 32-bit identifier or First 32-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | - 8002686: 683b ldr r3, [r7, #0] - 8002688: 681b ldr r3, [r3, #0] - 800268a: 0419 lsls r1, r3, #16 + 80026be: 683b ldr r3, [r7, #0] + 80026c0: 681b ldr r3, [r3, #0] + 80026c2: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); - 800268c: 683b ldr r3, [r7, #0] - 800268e: 685b ldr r3, [r3, #4] - 8002690: b29b uxth r3, r3 + 80026c4: 683b ldr r3, [r7, #0] + 80026c6: 685b ldr r3, [r3, #4] + 80026c8: b29b uxth r3, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = - 8002692: 683a ldr r2, [r7, #0] - 8002694: 6952 ldr r2, [r2, #20] + 80026ca: 683a ldr r2, [r7, #0] + 80026cc: 6952 ldr r2, [r2, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | - 8002696: 4319 orrs r1, r3 + 80026ce: 4319 orrs r1, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = - 8002698: 697b ldr r3, [r7, #20] - 800269a: 3248 adds r2, #72 @ 0x48 - 800269c: f843 1032 str.w r1, [r3, r2, lsl #3] + 80026d0: 697b ldr r3, [r7, #20] + 80026d2: 3248 adds r2, #72 @ 0x48 + 80026d4: f843 1032 str.w r1, [r3, r2, lsl #3] /* 32-bit mask or Second 32-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | - 80026a0: 683b ldr r3, [r7, #0] - 80026a2: 689b ldr r3, [r3, #8] - 80026a4: 0419 lsls r1, r3, #16 + 80026d8: 683b ldr r3, [r7, #0] + 80026da: 689b ldr r3, [r3, #8] + 80026dc: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow); - 80026a6: 683b ldr r3, [r7, #0] - 80026a8: 68db ldr r3, [r3, #12] - 80026aa: b29a uxth r2, r3 + 80026de: 683b ldr r3, [r7, #0] + 80026e0: 68db ldr r3, [r3, #12] + 80026e2: b29a uxth r2, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = - 80026ac: 683b ldr r3, [r7, #0] - 80026ae: 695b ldr r3, [r3, #20] + 80026e4: 683b ldr r3, [r7, #0] + 80026e6: 695b ldr r3, [r3, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | - 80026b0: 430a orrs r2, r1 + 80026e8: 430a orrs r2, r1 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = - 80026b2: 6979 ldr r1, [r7, #20] - 80026b4: 3348 adds r3, #72 @ 0x48 - 80026b6: 00db lsls r3, r3, #3 - 80026b8: 440b add r3, r1 - 80026ba: 605a str r2, [r3, #4] + 80026ea: 6979 ldr r1, [r7, #20] + 80026ec: 3348 adds r3, #72 @ 0x48 + 80026ee: 00db lsls r3, r3, #3 + 80026f0: 440b add r3, r1 + 80026f2: 605a str r2, [r3, #4] } /* Filter Mode */ if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK) - 80026bc: 683b ldr r3, [r7, #0] - 80026be: 699b ldr r3, [r3, #24] - 80026c0: 2b00 cmp r3, #0 - 80026c2: d109 bne.n 80026d8 + 80026f4: 683b ldr r3, [r7, #0] + 80026f6: 699b ldr r3, [r3, #24] + 80026f8: 2b00 cmp r3, #0 + 80026fa: d109 bne.n 8002710 { /* Id/Mask mode for the filter*/ CLEAR_BIT(can_ip->FM1R, filternbrbitpos); - 80026c4: 697b ldr r3, [r7, #20] - 80026c6: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204 - 80026ca: 68fb ldr r3, [r7, #12] - 80026cc: 43db mvns r3, r3 - 80026ce: 401a ands r2, r3 - 80026d0: 697b ldr r3, [r7, #20] - 80026d2: f8c3 2204 str.w r2, [r3, #516] @ 0x204 - 80026d6: e007 b.n 80026e8 + 80026fc: 697b ldr r3, [r7, #20] + 80026fe: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204 + 8002702: 68fb ldr r3, [r7, #12] + 8002704: 43db mvns r3, r3 + 8002706: 401a ands r2, r3 + 8002708: 697b ldr r3, [r7, #20] + 800270a: f8c3 2204 str.w r2, [r3, #516] @ 0x204 + 800270e: e007 b.n 8002720 } else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ { /* Identifier list mode for the filter*/ SET_BIT(can_ip->FM1R, filternbrbitpos); - 80026d8: 697b ldr r3, [r7, #20] - 80026da: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204 - 80026de: 68fb ldr r3, [r7, #12] - 80026e0: 431a orrs r2, r3 - 80026e2: 697b ldr r3, [r7, #20] - 80026e4: f8c3 2204 str.w r2, [r3, #516] @ 0x204 + 8002710: 697b ldr r3, [r7, #20] + 8002712: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204 + 8002716: 68fb ldr r3, [r7, #12] + 8002718: 431a orrs r2, r3 + 800271a: 697b ldr r3, [r7, #20] + 800271c: f8c3 2204 str.w r2, [r3, #516] @ 0x204 } /* Filter FIFO assignment */ if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0) - 80026e8: 683b ldr r3, [r7, #0] - 80026ea: 691b ldr r3, [r3, #16] - 80026ec: 2b00 cmp r3, #0 - 80026ee: d109 bne.n 8002704 + 8002720: 683b ldr r3, [r7, #0] + 8002722: 691b ldr r3, [r3, #16] + 8002724: 2b00 cmp r3, #0 + 8002726: d109 bne.n 800273c { /* FIFO 0 assignation for the filter */ CLEAR_BIT(can_ip->FFA1R, filternbrbitpos); - 80026f0: 697b ldr r3, [r7, #20] - 80026f2: f8d3 2214 ldr.w r2, [r3, #532] @ 0x214 - 80026f6: 68fb ldr r3, [r7, #12] - 80026f8: 43db mvns r3, r3 - 80026fa: 401a ands r2, r3 - 80026fc: 697b ldr r3, [r7, #20] - 80026fe: f8c3 2214 str.w r2, [r3, #532] @ 0x214 - 8002702: e007 b.n 8002714 + 8002728: 697b ldr r3, [r7, #20] + 800272a: f8d3 2214 ldr.w r2, [r3, #532] @ 0x214 + 800272e: 68fb ldr r3, [r7, #12] + 8002730: 43db mvns r3, r3 + 8002732: 401a ands r2, r3 + 8002734: 697b ldr r3, [r7, #20] + 8002736: f8c3 2214 str.w r2, [r3, #532] @ 0x214 + 800273a: e007 b.n 800274c } else { /* FIFO 1 assignation for the filter */ SET_BIT(can_ip->FFA1R, filternbrbitpos); - 8002704: 697b ldr r3, [r7, #20] - 8002706: f8d3 2214 ldr.w r2, [r3, #532] @ 0x214 - 800270a: 68fb ldr r3, [r7, #12] - 800270c: 431a orrs r2, r3 - 800270e: 697b ldr r3, [r7, #20] - 8002710: f8c3 2214 str.w r2, [r3, #532] @ 0x214 + 800273c: 697b ldr r3, [r7, #20] + 800273e: f8d3 2214 ldr.w r2, [r3, #532] @ 0x214 + 8002742: 68fb ldr r3, [r7, #12] + 8002744: 431a orrs r2, r3 + 8002746: 697b ldr r3, [r7, #20] + 8002748: f8c3 2214 str.w r2, [r3, #532] @ 0x214 } /* Filter activation */ if (sFilterConfig->FilterActivation == CAN_FILTER_ENABLE) - 8002714: 683b ldr r3, [r7, #0] - 8002716: 6a1b ldr r3, [r3, #32] - 8002718: 2b01 cmp r3, #1 - 800271a: d107 bne.n 800272c + 800274c: 683b ldr r3, [r7, #0] + 800274e: 6a1b ldr r3, [r3, #32] + 8002750: 2b01 cmp r3, #1 + 8002752: d107 bne.n 8002764 { SET_BIT(can_ip->FA1R, filternbrbitpos); - 800271c: 697b ldr r3, [r7, #20] - 800271e: f8d3 221c ldr.w r2, [r3, #540] @ 0x21c - 8002722: 68fb ldr r3, [r7, #12] - 8002724: 431a orrs r2, r3 - 8002726: 697b ldr r3, [r7, #20] - 8002728: f8c3 221c str.w r2, [r3, #540] @ 0x21c + 8002754: 697b ldr r3, [r7, #20] + 8002756: f8d3 221c ldr.w r2, [r3, #540] @ 0x21c + 800275a: 68fb ldr r3, [r7, #12] + 800275c: 431a orrs r2, r3 + 800275e: 697b ldr r3, [r7, #20] + 8002760: f8c3 221c str.w r2, [r3, #540] @ 0x21c } /* Leave the initialisation mode for the filter */ CLEAR_BIT(can_ip->FMR, CAN_FMR_FINIT); - 800272c: 697b ldr r3, [r7, #20] - 800272e: f8d3 3200 ldr.w r3, [r3, #512] @ 0x200 - 8002732: f023 0201 bic.w r2, r3, #1 - 8002736: 697b ldr r3, [r7, #20] - 8002738: f8c3 2200 str.w r2, [r3, #512] @ 0x200 + 8002764: 697b ldr r3, [r7, #20] + 8002766: f8d3 3200 ldr.w r3, [r3, #512] @ 0x200 + 800276a: f023 0201 bic.w r2, r3, #1 + 800276e: 697b ldr r3, [r7, #20] + 8002770: f8c3 2200 str.w r2, [r3, #512] @ 0x200 /* Return function status */ return HAL_OK; - 800273c: 2300 movs r3, #0 - 800273e: e006 b.n 800274e + 8002774: 2300 movs r3, #0 + 8002776: e006 b.n 8002786 } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; - 8002740: 687b ldr r3, [r7, #4] - 8002742: 6a5b ldr r3, [r3, #36] @ 0x24 - 8002744: f443 2280 orr.w r2, r3, #262144 @ 0x40000 - 8002748: 687b ldr r3, [r7, #4] - 800274a: 625a str r2, [r3, #36] @ 0x24 + 8002778: 687b ldr r3, [r7, #4] + 800277a: 6a5b ldr r3, [r3, #36] @ 0x24 + 800277c: f443 2280 orr.w r2, r3, #262144 @ 0x40000 + 8002780: 687b ldr r3, [r7, #4] + 8002782: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; - 800274c: 2301 movs r3, #1 + 8002784: 2301 movs r3, #1 } } - 800274e: 4618 mov r0, r3 - 8002750: 371c adds r7, #28 - 8002752: 46bd mov sp, r7 - 8002754: f85d 7b04 ldr.w r7, [sp], #4 - 8002758: 4770 bx lr + 8002786: 4618 mov r0, r3 + 8002788: 371c adds r7, #28 + 800278a: 46bd mov sp, r7 + 800278c: f85d 7b04 ldr.w r7, [sp], #4 + 8002790: 4770 bx lr -0800275a : +08002792 : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan) { - 800275a: b580 push {r7, lr} - 800275c: b084 sub sp, #16 - 800275e: af00 add r7, sp, #0 - 8002760: 6078 str r0, [r7, #4] + 8002792: b580 push {r7, lr} + 8002794: b084 sub sp, #16 + 8002796: af00 add r7, sp, #0 + 8002798: 6078 str r0, [r7, #4] uint32_t tickstart; if (hcan->State == HAL_CAN_STATE_READY) - 8002762: 687b ldr r3, [r7, #4] - 8002764: f893 3020 ldrb.w r3, [r3, #32] - 8002768: b2db uxtb r3, r3 - 800276a: 2b01 cmp r3, #1 - 800276c: d12e bne.n 80027cc + 800279a: 687b ldr r3, [r7, #4] + 800279c: f893 3020 ldrb.w r3, [r3, #32] + 80027a0: b2db uxtb r3, r3 + 80027a2: 2b01 cmp r3, #1 + 80027a4: d12e bne.n 8002804 { /* Change CAN peripheral state */ hcan->State = HAL_CAN_STATE_LISTENING; - 800276e: 687b ldr r3, [r7, #4] - 8002770: 2202 movs r2, #2 - 8002772: f883 2020 strb.w r2, [r3, #32] + 80027a6: 687b ldr r3, [r7, #4] + 80027a8: 2202 movs r2, #2 + 80027aa: f883 2020 strb.w r2, [r3, #32] /* Request leave initialisation */ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); - 8002776: 687b ldr r3, [r7, #4] - 8002778: 681b ldr r3, [r3, #0] - 800277a: 681a ldr r2, [r3, #0] - 800277c: 687b ldr r3, [r7, #4] - 800277e: 681b ldr r3, [r3, #0] - 8002780: f022 0201 bic.w r2, r2, #1 - 8002784: 601a str r2, [r3, #0] + 80027ae: 687b ldr r3, [r7, #4] + 80027b0: 681b ldr r3, [r3, #0] + 80027b2: 681a ldr r2, [r3, #0] + 80027b4: 687b ldr r3, [r7, #4] + 80027b6: 681b ldr r3, [r3, #0] + 80027b8: f022 0201 bic.w r2, r2, #1 + 80027bc: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); - 8002786: f7fe fe37 bl 80013f8 - 800278a: 60f8 str r0, [r7, #12] + 80027be: f7fe fe37 bl 8001430 + 80027c2: 60f8 str r0, [r7, #12] /* Wait the acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U) - 800278c: e012 b.n 80027b4 + 80027c4: e012 b.n 80027ec { /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) - 800278e: f7fe fe33 bl 80013f8 - 8002792: 4602 mov r2, r0 - 8002794: 68fb ldr r3, [r7, #12] - 8002796: 1ad3 subs r3, r2, r3 - 8002798: 2b0a cmp r3, #10 - 800279a: d90b bls.n 80027b4 + 80027c6: f7fe fe33 bl 8001430 + 80027ca: 4602 mov r2, r0 + 80027cc: 68fb ldr r3, [r7, #12] + 80027ce: 1ad3 subs r3, r2, r3 + 80027d0: 2b0a cmp r3, #10 + 80027d2: d90b bls.n 80027ec { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; - 800279c: 687b ldr r3, [r7, #4] - 800279e: 6a5b ldr r3, [r3, #36] @ 0x24 - 80027a0: f443 3200 orr.w r2, r3, #131072 @ 0x20000 - 80027a4: 687b ldr r3, [r7, #4] - 80027a6: 625a str r2, [r3, #36] @ 0x24 + 80027d4: 687b ldr r3, [r7, #4] + 80027d6: 6a5b ldr r3, [r3, #36] @ 0x24 + 80027d8: f443 3200 orr.w r2, r3, #131072 @ 0x20000 + 80027dc: 687b ldr r3, [r7, #4] + 80027de: 625a str r2, [r3, #36] @ 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; - 80027a8: 687b ldr r3, [r7, #4] - 80027aa: 2205 movs r2, #5 - 80027ac: f883 2020 strb.w r2, [r3, #32] + 80027e0: 687b ldr r3, [r7, #4] + 80027e2: 2205 movs r2, #5 + 80027e4: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; - 80027b0: 2301 movs r3, #1 - 80027b2: e012 b.n 80027da + 80027e8: 2301 movs r3, #1 + 80027ea: e012 b.n 8002812 while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U) - 80027b4: 687b ldr r3, [r7, #4] - 80027b6: 681b ldr r3, [r3, #0] - 80027b8: 685b ldr r3, [r3, #4] - 80027ba: f003 0301 and.w r3, r3, #1 - 80027be: 2b00 cmp r3, #0 - 80027c0: d1e5 bne.n 800278e + 80027ec: 687b ldr r3, [r7, #4] + 80027ee: 681b ldr r3, [r3, #0] + 80027f0: 685b ldr r3, [r3, #4] + 80027f2: f003 0301 and.w r3, r3, #1 + 80027f6: 2b00 cmp r3, #0 + 80027f8: d1e5 bne.n 80027c6 } } /* Reset the CAN ErrorCode */ hcan->ErrorCode = HAL_CAN_ERROR_NONE; - 80027c2: 687b ldr r3, [r7, #4] - 80027c4: 2200 movs r2, #0 - 80027c6: 625a str r2, [r3, #36] @ 0x24 + 80027fa: 687b ldr r3, [r7, #4] + 80027fc: 2200 movs r2, #0 + 80027fe: 625a str r2, [r3, #36] @ 0x24 /* Return function status */ return HAL_OK; - 80027c8: 2300 movs r3, #0 - 80027ca: e006 b.n 80027da + 8002800: 2300 movs r3, #0 + 8002802: e006 b.n 8002812 } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_READY; - 80027cc: 687b ldr r3, [r7, #4] - 80027ce: 6a5b ldr r3, [r3, #36] @ 0x24 - 80027d0: f443 2200 orr.w r2, r3, #524288 @ 0x80000 - 80027d4: 687b ldr r3, [r7, #4] - 80027d6: 625a str r2, [r3, #36] @ 0x24 + 8002804: 687b ldr r3, [r7, #4] + 8002806: 6a5b ldr r3, [r3, #36] @ 0x24 + 8002808: f443 2200 orr.w r2, r3, #524288 @ 0x80000 + 800280c: 687b ldr r3, [r7, #4] + 800280e: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; - 80027d8: 2301 movs r3, #1 + 8002810: 2301 movs r3, #1 } } - 80027da: 4618 mov r0, r3 - 80027dc: 3710 adds r7, #16 - 80027de: 46bd mov sp, r7 - 80027e0: bd80 pop {r7, pc} + 8002812: 4618 mov r0, r3 + 8002814: 3710 adds r7, #16 + 8002816: 46bd mov sp, r7 + 8002818: bd80 pop {r7, pc} -080027e2 : +0800281a : * This parameter can be a value of @arg CAN_Tx_Mailboxes. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, const CAN_TxHeaderTypeDef *pHeader, const uint8_t aData[], uint32_t *pTxMailbox) { - 80027e2: b480 push {r7} - 80027e4: b089 sub sp, #36 @ 0x24 - 80027e6: af00 add r7, sp, #0 - 80027e8: 60f8 str r0, [r7, #12] - 80027ea: 60b9 str r1, [r7, #8] - 80027ec: 607a str r2, [r7, #4] - 80027ee: 603b str r3, [r7, #0] + 800281a: b480 push {r7} + 800281c: b089 sub sp, #36 @ 0x24 + 800281e: af00 add r7, sp, #0 + 8002820: 60f8 str r0, [r7, #12] + 8002822: 60b9 str r1, [r7, #8] + 8002824: 607a str r2, [r7, #4] + 8002826: 603b str r3, [r7, #0] uint32_t transmitmailbox; HAL_CAN_StateTypeDef state = hcan->State; - 80027f0: 68fb ldr r3, [r7, #12] - 80027f2: f893 3020 ldrb.w r3, [r3, #32] - 80027f6: 77fb strb r3, [r7, #31] + 8002828: 68fb ldr r3, [r7, #12] + 800282a: f893 3020 ldrb.w r3, [r3, #32] + 800282e: 77fb strb r3, [r7, #31] uint32_t tsr = READ_REG(hcan->Instance->TSR); - 80027f8: 68fb ldr r3, [r7, #12] - 80027fa: 681b ldr r3, [r3, #0] - 80027fc: 689b ldr r3, [r3, #8] - 80027fe: 61bb str r3, [r7, #24] + 8002830: 68fb ldr r3, [r7, #12] + 8002832: 681b ldr r3, [r3, #0] + 8002834: 689b ldr r3, [r3, #8] + 8002836: 61bb str r3, [r7, #24] { assert_param(IS_CAN_EXTID(pHeader->ExtId)); } assert_param(IS_FUNCTIONAL_STATE(pHeader->TransmitGlobalTime)); if ((state == HAL_CAN_STATE_READY) || - 8002800: 7ffb ldrb r3, [r7, #31] - 8002802: 2b01 cmp r3, #1 - 8002804: d003 beq.n 800280e - 8002806: 7ffb ldrb r3, [r7, #31] - 8002808: 2b02 cmp r3, #2 - 800280a: f040 80ad bne.w 8002968 + 8002838: 7ffb ldrb r3, [r7, #31] + 800283a: 2b01 cmp r3, #1 + 800283c: d003 beq.n 8002846 + 800283e: 7ffb ldrb r3, [r7, #31] + 8002840: 2b02 cmp r3, #2 + 8002842: f040 80ad bne.w 80029a0 (state == HAL_CAN_STATE_LISTENING)) { /* Check that all the Tx mailboxes are not full */ if (((tsr & CAN_TSR_TME0) != 0U) || - 800280e: 69bb ldr r3, [r7, #24] - 8002810: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 - 8002814: 2b00 cmp r3, #0 - 8002816: d10a bne.n 800282e + 8002846: 69bb ldr r3, [r7, #24] + 8002848: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 + 800284c: 2b00 cmp r3, #0 + 800284e: d10a bne.n 8002866 ((tsr & CAN_TSR_TME1) != 0U) || - 8002818: 69bb ldr r3, [r7, #24] - 800281a: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 + 8002850: 69bb ldr r3, [r7, #24] + 8002852: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 if (((tsr & CAN_TSR_TME0) != 0U) || - 800281e: 2b00 cmp r3, #0 - 8002820: d105 bne.n 800282e + 8002856: 2b00 cmp r3, #0 + 8002858: d105 bne.n 8002866 ((tsr & CAN_TSR_TME2) != 0U)) - 8002822: 69bb ldr r3, [r7, #24] - 8002824: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 800285a: 69bb ldr r3, [r7, #24] + 800285c: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 ((tsr & CAN_TSR_TME1) != 0U) || - 8002828: 2b00 cmp r3, #0 - 800282a: f000 8095 beq.w 8002958 + 8002860: 2b00 cmp r3, #0 + 8002862: f000 8095 beq.w 8002990 { /* Select an empty transmit mailbox */ transmitmailbox = (tsr & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos; - 800282e: 69bb ldr r3, [r7, #24] - 8002830: 0e1b lsrs r3, r3, #24 - 8002832: f003 0303 and.w r3, r3, #3 - 8002836: 617b str r3, [r7, #20] + 8002866: 69bb ldr r3, [r7, #24] + 8002868: 0e1b lsrs r3, r3, #24 + 800286a: f003 0303 and.w r3, r3, #3 + 800286e: 617b str r3, [r7, #20] /* Store the Tx mailbox */ *pTxMailbox = (uint32_t)1 << transmitmailbox; - 8002838: 2201 movs r2, #1 - 800283a: 697b ldr r3, [r7, #20] - 800283c: 409a lsls r2, r3 - 800283e: 683b ldr r3, [r7, #0] - 8002840: 601a str r2, [r3, #0] + 8002870: 2201 movs r2, #1 + 8002872: 697b ldr r3, [r7, #20] + 8002874: 409a lsls r2, r3 + 8002876: 683b ldr r3, [r7, #0] + 8002878: 601a str r2, [r3, #0] /* Set up the Id */ if (pHeader->IDE == CAN_ID_STD) - 8002842: 68bb ldr r3, [r7, #8] - 8002844: 689b ldr r3, [r3, #8] - 8002846: 2b00 cmp r3, #0 - 8002848: d10d bne.n 8002866 + 800287a: 68bb ldr r3, [r7, #8] + 800287c: 689b ldr r3, [r3, #8] + 800287e: 2b00 cmp r3, #0 + 8002880: d10d bne.n 800289e { hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) | - 800284a: 68bb ldr r3, [r7, #8] - 800284c: 681b ldr r3, [r3, #0] - 800284e: 055a lsls r2, r3, #21 + 8002882: 68bb ldr r3, [r7, #8] + 8002884: 681b ldr r3, [r3, #0] + 8002886: 055a lsls r2, r3, #21 pHeader->RTR); - 8002850: 68bb ldr r3, [r7, #8] - 8002852: 68db ldr r3, [r3, #12] + 8002888: 68bb ldr r3, [r7, #8] + 800288a: 68db ldr r3, [r3, #12] hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) | - 8002854: 68f9 ldr r1, [r7, #12] - 8002856: 6809 ldr r1, [r1, #0] - 8002858: 431a orrs r2, r3 - 800285a: 697b ldr r3, [r7, #20] - 800285c: 3318 adds r3, #24 - 800285e: 011b lsls r3, r3, #4 - 8002860: 440b add r3, r1 - 8002862: 601a str r2, [r3, #0] - 8002864: e00f b.n 8002886 + 800288c: 68f9 ldr r1, [r7, #12] + 800288e: 6809 ldr r1, [r1, #0] + 8002890: 431a orrs r2, r3 + 8002892: 697b ldr r3, [r7, #20] + 8002894: 3318 adds r3, #24 + 8002896: 011b lsls r3, r3, #4 + 8002898: 440b add r3, r1 + 800289a: 601a str r2, [r3, #0] + 800289c: e00f b.n 80028be } else { hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | - 8002866: 68bb ldr r3, [r7, #8] - 8002868: 685b ldr r3, [r3, #4] - 800286a: 00da lsls r2, r3, #3 + 800289e: 68bb ldr r3, [r7, #8] + 80028a0: 685b ldr r3, [r3, #4] + 80028a2: 00da lsls r2, r3, #3 pHeader->IDE | - 800286c: 68bb ldr r3, [r7, #8] - 800286e: 689b ldr r3, [r3, #8] + 80028a4: 68bb ldr r3, [r7, #8] + 80028a6: 689b ldr r3, [r3, #8] hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | - 8002870: 431a orrs r2, r3 + 80028a8: 431a orrs r2, r3 pHeader->RTR); - 8002872: 68bb ldr r3, [r7, #8] - 8002874: 68db ldr r3, [r3, #12] + 80028aa: 68bb ldr r3, [r7, #8] + 80028ac: 68db ldr r3, [r3, #12] hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | - 8002876: 68f9 ldr r1, [r7, #12] - 8002878: 6809 ldr r1, [r1, #0] + 80028ae: 68f9 ldr r1, [r7, #12] + 80028b0: 6809 ldr r1, [r1, #0] pHeader->IDE | - 800287a: 431a orrs r2, r3 + 80028b2: 431a orrs r2, r3 hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | - 800287c: 697b ldr r3, [r7, #20] - 800287e: 3318 adds r3, #24 - 8002880: 011b lsls r3, r3, #4 - 8002882: 440b add r3, r1 - 8002884: 601a str r2, [r3, #0] + 80028b4: 697b ldr r3, [r7, #20] + 80028b6: 3318 adds r3, #24 + 80028b8: 011b lsls r3, r3, #4 + 80028ba: 440b add r3, r1 + 80028bc: 601a str r2, [r3, #0] } /* Set up the DLC */ hcan->Instance->sTxMailBox[transmitmailbox].TDTR = (pHeader->DLC); - 8002886: 68fb ldr r3, [r7, #12] - 8002888: 6819 ldr r1, [r3, #0] - 800288a: 68bb ldr r3, [r7, #8] - 800288c: 691a ldr r2, [r3, #16] - 800288e: 697b ldr r3, [r7, #20] - 8002890: 3318 adds r3, #24 - 8002892: 011b lsls r3, r3, #4 - 8002894: 440b add r3, r1 - 8002896: 3304 adds r3, #4 - 8002898: 601a str r2, [r3, #0] + 80028be: 68fb ldr r3, [r7, #12] + 80028c0: 6819 ldr r1, [r3, #0] + 80028c2: 68bb ldr r3, [r7, #8] + 80028c4: 691a ldr r2, [r3, #16] + 80028c6: 697b ldr r3, [r7, #20] + 80028c8: 3318 adds r3, #24 + 80028ca: 011b lsls r3, r3, #4 + 80028cc: 440b add r3, r1 + 80028ce: 3304 adds r3, #4 + 80028d0: 601a str r2, [r3, #0] /* Set up the Transmit Global Time mode */ if (pHeader->TransmitGlobalTime == ENABLE) - 800289a: 68bb ldr r3, [r7, #8] - 800289c: 7d1b ldrb r3, [r3, #20] - 800289e: 2b01 cmp r3, #1 - 80028a0: d111 bne.n 80028c6 + 80028d2: 68bb ldr r3, [r7, #8] + 80028d4: 7d1b ldrb r3, [r3, #20] + 80028d6: 2b01 cmp r3, #1 + 80028d8: d111 bne.n 80028fe { SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TDTR, CAN_TDT0R_TGT); - 80028a2: 68fb ldr r3, [r7, #12] - 80028a4: 681a ldr r2, [r3, #0] - 80028a6: 697b ldr r3, [r7, #20] - 80028a8: 3318 adds r3, #24 - 80028aa: 011b lsls r3, r3, #4 - 80028ac: 4413 add r3, r2 - 80028ae: 3304 adds r3, #4 - 80028b0: 681b ldr r3, [r3, #0] - 80028b2: 68fa ldr r2, [r7, #12] - 80028b4: 6811 ldr r1, [r2, #0] - 80028b6: f443 7280 orr.w r2, r3, #256 @ 0x100 - 80028ba: 697b ldr r3, [r7, #20] - 80028bc: 3318 adds r3, #24 - 80028be: 011b lsls r3, r3, #4 - 80028c0: 440b add r3, r1 - 80028c2: 3304 adds r3, #4 - 80028c4: 601a str r2, [r3, #0] + 80028da: 68fb ldr r3, [r7, #12] + 80028dc: 681a ldr r2, [r3, #0] + 80028de: 697b ldr r3, [r7, #20] + 80028e0: 3318 adds r3, #24 + 80028e2: 011b lsls r3, r3, #4 + 80028e4: 4413 add r3, r2 + 80028e6: 3304 adds r3, #4 + 80028e8: 681b ldr r3, [r3, #0] + 80028ea: 68fa ldr r2, [r7, #12] + 80028ec: 6811 ldr r1, [r2, #0] + 80028ee: f443 7280 orr.w r2, r3, #256 @ 0x100 + 80028f2: 697b ldr r3, [r7, #20] + 80028f4: 3318 adds r3, #24 + 80028f6: 011b lsls r3, r3, #4 + 80028f8: 440b add r3, r1 + 80028fa: 3304 adds r3, #4 + 80028fc: 601a str r2, [r3, #0] } /* Set up the data field */ WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, - 80028c6: 687b ldr r3, [r7, #4] - 80028c8: 3307 adds r3, #7 - 80028ca: 781b ldrb r3, [r3, #0] - 80028cc: 061a lsls r2, r3, #24 - 80028ce: 687b ldr r3, [r7, #4] - 80028d0: 3306 adds r3, #6 - 80028d2: 781b ldrb r3, [r3, #0] - 80028d4: 041b lsls r3, r3, #16 - 80028d6: 431a orrs r2, r3 - 80028d8: 687b ldr r3, [r7, #4] - 80028da: 3305 adds r3, #5 - 80028dc: 781b ldrb r3, [r3, #0] - 80028de: 021b lsls r3, r3, #8 - 80028e0: 4313 orrs r3, r2 - 80028e2: 687a ldr r2, [r7, #4] - 80028e4: 3204 adds r2, #4 - 80028e6: 7812 ldrb r2, [r2, #0] - 80028e8: 4610 mov r0, r2 - 80028ea: 68fa ldr r2, [r7, #12] - 80028ec: 6811 ldr r1, [r2, #0] - 80028ee: ea43 0200 orr.w r2, r3, r0 - 80028f2: 697b ldr r3, [r7, #20] - 80028f4: 011b lsls r3, r3, #4 - 80028f6: 440b add r3, r1 - 80028f8: f503 73c6 add.w r3, r3, #396 @ 0x18c - 80028fc: 601a str r2, [r3, #0] + 80028fe: 687b ldr r3, [r7, #4] + 8002900: 3307 adds r3, #7 + 8002902: 781b ldrb r3, [r3, #0] + 8002904: 061a lsls r2, r3, #24 + 8002906: 687b ldr r3, [r7, #4] + 8002908: 3306 adds r3, #6 + 800290a: 781b ldrb r3, [r3, #0] + 800290c: 041b lsls r3, r3, #16 + 800290e: 431a orrs r2, r3 + 8002910: 687b ldr r3, [r7, #4] + 8002912: 3305 adds r3, #5 + 8002914: 781b ldrb r3, [r3, #0] + 8002916: 021b lsls r3, r3, #8 + 8002918: 4313 orrs r3, r2 + 800291a: 687a ldr r2, [r7, #4] + 800291c: 3204 adds r2, #4 + 800291e: 7812 ldrb r2, [r2, #0] + 8002920: 4610 mov r0, r2 + 8002922: 68fa ldr r2, [r7, #12] + 8002924: 6811 ldr r1, [r2, #0] + 8002926: ea43 0200 orr.w r2, r3, r0 + 800292a: 697b ldr r3, [r7, #20] + 800292c: 011b lsls r3, r3, #4 + 800292e: 440b add r3, r1 + 8002930: f503 73c6 add.w r3, r3, #396 @ 0x18c + 8002934: 601a str r2, [r3, #0] ((uint32_t)aData[7] << CAN_TDH0R_DATA7_Pos) | ((uint32_t)aData[6] << CAN_TDH0R_DATA6_Pos) | ((uint32_t)aData[5] << CAN_TDH0R_DATA5_Pos) | ((uint32_t)aData[4] << CAN_TDH0R_DATA4_Pos)); WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, - 80028fe: 687b ldr r3, [r7, #4] - 8002900: 3303 adds r3, #3 - 8002902: 781b ldrb r3, [r3, #0] - 8002904: 061a lsls r2, r3, #24 - 8002906: 687b ldr r3, [r7, #4] - 8002908: 3302 adds r3, #2 - 800290a: 781b ldrb r3, [r3, #0] - 800290c: 041b lsls r3, r3, #16 - 800290e: 431a orrs r2, r3 - 8002910: 687b ldr r3, [r7, #4] - 8002912: 3301 adds r3, #1 - 8002914: 781b ldrb r3, [r3, #0] - 8002916: 021b lsls r3, r3, #8 - 8002918: 4313 orrs r3, r2 - 800291a: 687a ldr r2, [r7, #4] - 800291c: 7812 ldrb r2, [r2, #0] - 800291e: 4610 mov r0, r2 - 8002920: 68fa ldr r2, [r7, #12] - 8002922: 6811 ldr r1, [r2, #0] - 8002924: ea43 0200 orr.w r2, r3, r0 - 8002928: 697b ldr r3, [r7, #20] - 800292a: 011b lsls r3, r3, #4 - 800292c: 440b add r3, r1 - 800292e: f503 73c4 add.w r3, r3, #392 @ 0x188 - 8002932: 601a str r2, [r3, #0] + 8002936: 687b ldr r3, [r7, #4] + 8002938: 3303 adds r3, #3 + 800293a: 781b ldrb r3, [r3, #0] + 800293c: 061a lsls r2, r3, #24 + 800293e: 687b ldr r3, [r7, #4] + 8002940: 3302 adds r3, #2 + 8002942: 781b ldrb r3, [r3, #0] + 8002944: 041b lsls r3, r3, #16 + 8002946: 431a orrs r2, r3 + 8002948: 687b ldr r3, [r7, #4] + 800294a: 3301 adds r3, #1 + 800294c: 781b ldrb r3, [r3, #0] + 800294e: 021b lsls r3, r3, #8 + 8002950: 4313 orrs r3, r2 + 8002952: 687a ldr r2, [r7, #4] + 8002954: 7812 ldrb r2, [r2, #0] + 8002956: 4610 mov r0, r2 + 8002958: 68fa ldr r2, [r7, #12] + 800295a: 6811 ldr r1, [r2, #0] + 800295c: ea43 0200 orr.w r2, r3, r0 + 8002960: 697b ldr r3, [r7, #20] + 8002962: 011b lsls r3, r3, #4 + 8002964: 440b add r3, r1 + 8002966: f503 73c4 add.w r3, r3, #392 @ 0x188 + 800296a: 601a str r2, [r3, #0] ((uint32_t)aData[2] << CAN_TDL0R_DATA2_Pos) | ((uint32_t)aData[1] << CAN_TDL0R_DATA1_Pos) | ((uint32_t)aData[0] << CAN_TDL0R_DATA0_Pos)); /* Request transmission */ SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ); - 8002934: 68fb ldr r3, [r7, #12] - 8002936: 681a ldr r2, [r3, #0] - 8002938: 697b ldr r3, [r7, #20] - 800293a: 3318 adds r3, #24 - 800293c: 011b lsls r3, r3, #4 - 800293e: 4413 add r3, r2 - 8002940: 681b ldr r3, [r3, #0] - 8002942: 68fa ldr r2, [r7, #12] - 8002944: 6811 ldr r1, [r2, #0] - 8002946: f043 0201 orr.w r2, r3, #1 - 800294a: 697b ldr r3, [r7, #20] - 800294c: 3318 adds r3, #24 - 800294e: 011b lsls r3, r3, #4 - 8002950: 440b add r3, r1 - 8002952: 601a str r2, [r3, #0] + 800296c: 68fb ldr r3, [r7, #12] + 800296e: 681a ldr r2, [r3, #0] + 8002970: 697b ldr r3, [r7, #20] + 8002972: 3318 adds r3, #24 + 8002974: 011b lsls r3, r3, #4 + 8002976: 4413 add r3, r2 + 8002978: 681b ldr r3, [r3, #0] + 800297a: 68fa ldr r2, [r7, #12] + 800297c: 6811 ldr r1, [r2, #0] + 800297e: f043 0201 orr.w r2, r3, #1 + 8002982: 697b ldr r3, [r7, #20] + 8002984: 3318 adds r3, #24 + 8002986: 011b lsls r3, r3, #4 + 8002988: 440b add r3, r1 + 800298a: 601a str r2, [r3, #0] /* Return function status */ return HAL_OK; - 8002954: 2300 movs r3, #0 - 8002956: e00e b.n 8002976 + 800298c: 2300 movs r3, #0 + 800298e: e00e b.n 80029ae } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; - 8002958: 68fb ldr r3, [r7, #12] - 800295a: 6a5b ldr r3, [r3, #36] @ 0x24 - 800295c: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 - 8002960: 68fb ldr r3, [r7, #12] - 8002962: 625a str r2, [r3, #36] @ 0x24 + 8002990: 68fb ldr r3, [r7, #12] + 8002992: 6a5b ldr r3, [r3, #36] @ 0x24 + 8002994: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 + 8002998: 68fb ldr r3, [r7, #12] + 800299a: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; - 8002964: 2301 movs r3, #1 - 8002966: e006 b.n 8002976 + 800299c: 2301 movs r3, #1 + 800299e: e006 b.n 80029ae } } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; - 8002968: 68fb ldr r3, [r7, #12] - 800296a: 6a5b ldr r3, [r3, #36] @ 0x24 - 800296c: f443 2280 orr.w r2, r3, #262144 @ 0x40000 - 8002970: 68fb ldr r3, [r7, #12] - 8002972: 625a str r2, [r3, #36] @ 0x24 + 80029a0: 68fb ldr r3, [r7, #12] + 80029a2: 6a5b ldr r3, [r3, #36] @ 0x24 + 80029a4: f443 2280 orr.w r2, r3, #262144 @ 0x40000 + 80029a8: 68fb ldr r3, [r7, #12] + 80029aa: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; - 8002974: 2301 movs r3, #1 + 80029ac: 2301 movs r3, #1 } } - 8002976: 4618 mov r0, r3 - 8002978: 3724 adds r7, #36 @ 0x24 - 800297a: 46bd mov sp, r7 - 800297c: f85d 7b04 ldr.w r7, [sp], #4 - 8002980: 4770 bx lr + 80029ae: 4618 mov r0, r3 + 80029b0: 3724 adds r7, #36 @ 0x24 + 80029b2: 46bd mov sp, r7 + 80029b4: f85d 7b04 ldr.w r7, [sp], #4 + 80029b8: 4770 bx lr -08002982 : +080029ba : * @param aData array where the payload of the Rx frame will be stored. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]) { - 8002982: b480 push {r7} - 8002984: b087 sub sp, #28 - 8002986: af00 add r7, sp, #0 - 8002988: 60f8 str r0, [r7, #12] - 800298a: 60b9 str r1, [r7, #8] - 800298c: 607a str r2, [r7, #4] - 800298e: 603b str r3, [r7, #0] + 80029ba: b480 push {r7} + 80029bc: b087 sub sp, #28 + 80029be: af00 add r7, sp, #0 + 80029c0: 60f8 str r0, [r7, #12] + 80029c2: 60b9 str r1, [r7, #8] + 80029c4: 607a str r2, [r7, #4] + 80029c6: 603b str r3, [r7, #0] HAL_CAN_StateTypeDef state = hcan->State; - 8002990: 68fb ldr r3, [r7, #12] - 8002992: f893 3020 ldrb.w r3, [r3, #32] - 8002996: 75fb strb r3, [r7, #23] + 80029c8: 68fb ldr r3, [r7, #12] + 80029ca: f893 3020 ldrb.w r3, [r3, #32] + 80029ce: 75fb strb r3, [r7, #23] assert_param(IS_CAN_RX_FIFO(RxFifo)); if ((state == HAL_CAN_STATE_READY) || - 8002998: 7dfb ldrb r3, [r7, #23] - 800299a: 2b01 cmp r3, #1 - 800299c: d003 beq.n 80029a6 - 800299e: 7dfb ldrb r3, [r7, #23] - 80029a0: 2b02 cmp r3, #2 - 80029a2: f040 8103 bne.w 8002bac + 80029d0: 7dfb ldrb r3, [r7, #23] + 80029d2: 2b01 cmp r3, #1 + 80029d4: d003 beq.n 80029de + 80029d6: 7dfb ldrb r3, [r7, #23] + 80029d8: 2b02 cmp r3, #2 + 80029da: f040 8103 bne.w 8002be4 (state == HAL_CAN_STATE_LISTENING)) { /* Check the Rx FIFO */ if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ - 80029a6: 68bb ldr r3, [r7, #8] - 80029a8: 2b00 cmp r3, #0 - 80029aa: d10e bne.n 80029ca + 80029de: 68bb ldr r3, [r7, #8] + 80029e0: 2b00 cmp r3, #0 + 80029e2: d10e bne.n 8002a02 { /* Check that the Rx FIFO 0 is not empty */ if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == 0U) - 80029ac: 68fb ldr r3, [r7, #12] - 80029ae: 681b ldr r3, [r3, #0] - 80029b0: 68db ldr r3, [r3, #12] - 80029b2: f003 0303 and.w r3, r3, #3 - 80029b6: 2b00 cmp r3, #0 - 80029b8: d116 bne.n 80029e8 + 80029e4: 68fb ldr r3, [r7, #12] + 80029e6: 681b ldr r3, [r3, #0] + 80029e8: 68db ldr r3, [r3, #12] + 80029ea: f003 0303 and.w r3, r3, #3 + 80029ee: 2b00 cmp r3, #0 + 80029f0: d116 bne.n 8002a20 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; - 80029ba: 68fb ldr r3, [r7, #12] - 80029bc: 6a5b ldr r3, [r3, #36] @ 0x24 - 80029be: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 - 80029c2: 68fb ldr r3, [r7, #12] - 80029c4: 625a str r2, [r3, #36] @ 0x24 + 80029f2: 68fb ldr r3, [r7, #12] + 80029f4: 6a5b ldr r3, [r3, #36] @ 0x24 + 80029f6: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 + 80029fa: 68fb ldr r3, [r7, #12] + 80029fc: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; - 80029c6: 2301 movs r3, #1 - 80029c8: e0f7 b.n 8002bba + 80029fe: 2301 movs r3, #1 + 8002a00: e0f7 b.n 8002bf2 } } else /* Rx element is assigned to Rx FIFO 1 */ { /* Check that the Rx FIFO 1 is not empty */ if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == 0U) - 80029ca: 68fb ldr r3, [r7, #12] - 80029cc: 681b ldr r3, [r3, #0] - 80029ce: 691b ldr r3, [r3, #16] - 80029d0: f003 0303 and.w r3, r3, #3 - 80029d4: 2b00 cmp r3, #0 - 80029d6: d107 bne.n 80029e8 + 8002a02: 68fb ldr r3, [r7, #12] + 8002a04: 681b ldr r3, [r3, #0] + 8002a06: 691b ldr r3, [r3, #16] + 8002a08: f003 0303 and.w r3, r3, #3 + 8002a0c: 2b00 cmp r3, #0 + 8002a0e: d107 bne.n 8002a20 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; - 80029d8: 68fb ldr r3, [r7, #12] - 80029da: 6a5b ldr r3, [r3, #36] @ 0x24 - 80029dc: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 - 80029e0: 68fb ldr r3, [r7, #12] - 80029e2: 625a str r2, [r3, #36] @ 0x24 + 8002a10: 68fb ldr r3, [r7, #12] + 8002a12: 6a5b ldr r3, [r3, #36] @ 0x24 + 8002a14: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 + 8002a18: 68fb ldr r3, [r7, #12] + 8002a1a: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; - 80029e4: 2301 movs r3, #1 - 80029e6: e0e8 b.n 8002bba + 8002a1c: 2301 movs r3, #1 + 8002a1e: e0e8 b.n 8002bf2 } } /* Get the header */ pHeader->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[RxFifo].RIR; - 80029e8: 68fb ldr r3, [r7, #12] - 80029ea: 681a ldr r2, [r3, #0] - 80029ec: 68bb ldr r3, [r7, #8] - 80029ee: 331b adds r3, #27 - 80029f0: 011b lsls r3, r3, #4 - 80029f2: 4413 add r3, r2 - 80029f4: 681b ldr r3, [r3, #0] - 80029f6: f003 0204 and.w r2, r3, #4 - 80029fa: 687b ldr r3, [r7, #4] - 80029fc: 609a str r2, [r3, #8] - if (pHeader->IDE == CAN_ID_STD) - 80029fe: 687b ldr r3, [r7, #4] - 8002a00: 689b ldr r3, [r3, #8] - 8002a02: 2b00 cmp r3, #0 - 8002a04: d10c bne.n 8002a20 - { - pHeader->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_TI0R_STID_Pos; - 8002a06: 68fb ldr r3, [r7, #12] - 8002a08: 681a ldr r2, [r3, #0] - 8002a0a: 68bb ldr r3, [r7, #8] - 8002a0c: 331b adds r3, #27 - 8002a0e: 011b lsls r3, r3, #4 - 8002a10: 4413 add r3, r2 - 8002a12: 681b ldr r3, [r3, #0] - 8002a14: 0d5b lsrs r3, r3, #21 - 8002a16: f3c3 020a ubfx r2, r3, #0, #11 - 8002a1a: 687b ldr r3, [r7, #4] - 8002a1c: 601a str r2, [r3, #0] - 8002a1e: e00b b.n 8002a38 - } - else - { - pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & - hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos; 8002a20: 68fb ldr r3, [r7, #12] 8002a22: 681a ldr r2, [r3, #0] 8002a24: 68bb ldr r3, [r7, #8] @@ -7310,59 +7301,58 @@ HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, 8002a28: 011b lsls r3, r3, #4 8002a2a: 4413 add r3, r2 8002a2c: 681b ldr r3, [r3, #0] - 8002a2e: 08db lsrs r3, r3, #3 - 8002a30: f023 4260 bic.w r2, r3, #3758096384 @ 0xe0000000 - pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & - 8002a34: 687b ldr r3, [r7, #4] - 8002a36: 605a str r2, [r3, #4] - } - pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR); - 8002a38: 68fb ldr r3, [r7, #12] - 8002a3a: 681a ldr r2, [r3, #0] - 8002a3c: 68bb ldr r3, [r7, #8] - 8002a3e: 331b adds r3, #27 - 8002a40: 011b lsls r3, r3, #4 - 8002a42: 4413 add r3, r2 - 8002a44: 681b ldr r3, [r3, #0] - 8002a46: f003 0202 and.w r2, r3, #2 - 8002a4a: 687b ldr r3, [r7, #4] - 8002a4c: 60da str r2, [r3, #12] - if (((CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos) >= 8U) - 8002a4e: 68fb ldr r3, [r7, #12] - 8002a50: 681a ldr r2, [r3, #0] - 8002a52: 68bb ldr r3, [r7, #8] - 8002a54: 331b adds r3, #27 - 8002a56: 011b lsls r3, r3, #4 - 8002a58: 4413 add r3, r2 - 8002a5a: 3304 adds r3, #4 - 8002a5c: 681b ldr r3, [r3, #0] - 8002a5e: f003 0308 and.w r3, r3, #8 - 8002a62: 2b00 cmp r3, #0 - 8002a64: d003 beq.n 8002a6e + 8002a2e: f003 0204 and.w r2, r3, #4 + 8002a32: 687b ldr r3, [r7, #4] + 8002a34: 609a str r2, [r3, #8] + if (pHeader->IDE == CAN_ID_STD) + 8002a36: 687b ldr r3, [r7, #4] + 8002a38: 689b ldr r3, [r3, #8] + 8002a3a: 2b00 cmp r3, #0 + 8002a3c: d10c bne.n 8002a58 { - /* Truncate DLC to 8 if received field is over range */ - pHeader->DLC = 8U; - 8002a66: 687b ldr r3, [r7, #4] - 8002a68: 2208 movs r2, #8 - 8002a6a: 611a str r2, [r3, #16] - 8002a6c: e00b b.n 8002a86 + pHeader->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_TI0R_STID_Pos; + 8002a3e: 68fb ldr r3, [r7, #12] + 8002a40: 681a ldr r2, [r3, #0] + 8002a42: 68bb ldr r3, [r7, #8] + 8002a44: 331b adds r3, #27 + 8002a46: 011b lsls r3, r3, #4 + 8002a48: 4413 add r3, r2 + 8002a4a: 681b ldr r3, [r3, #0] + 8002a4c: 0d5b lsrs r3, r3, #21 + 8002a4e: f3c3 020a ubfx r2, r3, #0, #11 + 8002a52: 687b ldr r3, [r7, #4] + 8002a54: 601a str r2, [r3, #0] + 8002a56: e00b b.n 8002a70 } else { - pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos; - 8002a6e: 68fb ldr r3, [r7, #12] - 8002a70: 681a ldr r2, [r3, #0] - 8002a72: 68bb ldr r3, [r7, #8] - 8002a74: 331b adds r3, #27 - 8002a76: 011b lsls r3, r3, #4 - 8002a78: 4413 add r3, r2 - 8002a7a: 3304 adds r3, #4 - 8002a7c: 681b ldr r3, [r3, #0] - 8002a7e: f003 020f and.w r2, r3, #15 - 8002a82: 687b ldr r3, [r7, #4] - 8002a84: 611a str r2, [r3, #16] + pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & + hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos; + 8002a58: 68fb ldr r3, [r7, #12] + 8002a5a: 681a ldr r2, [r3, #0] + 8002a5c: 68bb ldr r3, [r7, #8] + 8002a5e: 331b adds r3, #27 + 8002a60: 011b lsls r3, r3, #4 + 8002a62: 4413 add r3, r2 + 8002a64: 681b ldr r3, [r3, #0] + 8002a66: 08db lsrs r3, r3, #3 + 8002a68: f023 4260 bic.w r2, r3, #3758096384 @ 0xe0000000 + pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & + 8002a6c: 687b ldr r3, [r7, #4] + 8002a6e: 605a str r2, [r3, #4] } - pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos; + pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR); + 8002a70: 68fb ldr r3, [r7, #12] + 8002a72: 681a ldr r2, [r3, #0] + 8002a74: 68bb ldr r3, [r7, #8] + 8002a76: 331b adds r3, #27 + 8002a78: 011b lsls r3, r3, #4 + 8002a7a: 4413 add r3, r2 + 8002a7c: 681b ldr r3, [r3, #0] + 8002a7e: f003 0202 and.w r2, r3, #2 + 8002a82: 687b ldr r3, [r7, #4] + 8002a84: 60da str r2, [r3, #12] + if (((CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos) >= 8U) 8002a86: 68fb ldr r3, [r7, #12] 8002a88: 681a ldr r2, [r3, #0] 8002a8a: 68bb ldr r3, [r7, #8] @@ -7371,8127 +7361,8162 @@ HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, 8002a90: 4413 add r3, r2 8002a92: 3304 adds r3, #4 8002a94: 681b ldr r3, [r3, #0] - 8002a96: 0a1b lsrs r3, r3, #8 - 8002a98: b2da uxtb r2, r3 - 8002a9a: 687b ldr r3, [r7, #4] - 8002a9c: 619a str r2, [r3, #24] + 8002a96: f003 0308 and.w r3, r3, #8 + 8002a9a: 2b00 cmp r3, #0 + 8002a9c: d003 beq.n 8002aa6 + { + /* Truncate DLC to 8 if received field is over range */ + pHeader->DLC = 8U; + 8002a9e: 687b ldr r3, [r7, #4] + 8002aa0: 2208 movs r2, #8 + 8002aa2: 611a str r2, [r3, #16] + 8002aa4: e00b b.n 8002abe + } + else + { + pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos; + 8002aa6: 68fb ldr r3, [r7, #12] + 8002aa8: 681a ldr r2, [r3, #0] + 8002aaa: 68bb ldr r3, [r7, #8] + 8002aac: 331b adds r3, #27 + 8002aae: 011b lsls r3, r3, #4 + 8002ab0: 4413 add r3, r2 + 8002ab2: 3304 adds r3, #4 + 8002ab4: 681b ldr r3, [r3, #0] + 8002ab6: f003 020f and.w r2, r3, #15 + 8002aba: 687b ldr r3, [r7, #4] + 8002abc: 611a str r2, [r3, #16] + } + pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos; + 8002abe: 68fb ldr r3, [r7, #12] + 8002ac0: 681a ldr r2, [r3, #0] + 8002ac2: 68bb ldr r3, [r7, #8] + 8002ac4: 331b adds r3, #27 + 8002ac6: 011b lsls r3, r3, #4 + 8002ac8: 4413 add r3, r2 + 8002aca: 3304 adds r3, #4 + 8002acc: 681b ldr r3, [r3, #0] + 8002ace: 0a1b lsrs r3, r3, #8 + 8002ad0: b2da uxtb r2, r3 + 8002ad2: 687b ldr r3, [r7, #4] + 8002ad4: 619a str r2, [r3, #24] pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos; - 8002a9e: 68fb ldr r3, [r7, #12] - 8002aa0: 681a ldr r2, [r3, #0] - 8002aa2: 68bb ldr r3, [r7, #8] - 8002aa4: 331b adds r3, #27 - 8002aa6: 011b lsls r3, r3, #4 - 8002aa8: 4413 add r3, r2 - 8002aaa: 3304 adds r3, #4 - 8002aac: 681b ldr r3, [r3, #0] - 8002aae: 0c1b lsrs r3, r3, #16 - 8002ab0: b29a uxth r2, r3 - 8002ab2: 687b ldr r3, [r7, #4] - 8002ab4: 615a str r2, [r3, #20] + 8002ad6: 68fb ldr r3, [r7, #12] + 8002ad8: 681a ldr r2, [r3, #0] + 8002ada: 68bb ldr r3, [r7, #8] + 8002adc: 331b adds r3, #27 + 8002ade: 011b lsls r3, r3, #4 + 8002ae0: 4413 add r3, r2 + 8002ae2: 3304 adds r3, #4 + 8002ae4: 681b ldr r3, [r3, #0] + 8002ae6: 0c1b lsrs r3, r3, #16 + 8002ae8: b29a uxth r2, r3 + 8002aea: 687b ldr r3, [r7, #4] + 8002aec: 615a str r2, [r3, #20] /* Get the data */ aData[0] = (uint8_t)((CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos); - 8002ab6: 68fb ldr r3, [r7, #12] - 8002ab8: 681a ldr r2, [r3, #0] - 8002aba: 68bb ldr r3, [r7, #8] - 8002abc: 011b lsls r3, r3, #4 - 8002abe: 4413 add r3, r2 - 8002ac0: f503 73dc add.w r3, r3, #440 @ 0x1b8 - 8002ac4: 681b ldr r3, [r3, #0] - 8002ac6: b2da uxtb r2, r3 - 8002ac8: 683b ldr r3, [r7, #0] - 8002aca: 701a strb r2, [r3, #0] + 8002aee: 68fb ldr r3, [r7, #12] + 8002af0: 681a ldr r2, [r3, #0] + 8002af2: 68bb ldr r3, [r7, #8] + 8002af4: 011b lsls r3, r3, #4 + 8002af6: 4413 add r3, r2 + 8002af8: f503 73dc add.w r3, r3, #440 @ 0x1b8 + 8002afc: 681b ldr r3, [r3, #0] + 8002afe: b2da uxtb r2, r3 + 8002b00: 683b ldr r3, [r7, #0] + 8002b02: 701a strb r2, [r3, #0] aData[1] = (uint8_t)((CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos); - 8002acc: 68fb ldr r3, [r7, #12] - 8002ace: 681a ldr r2, [r3, #0] - 8002ad0: 68bb ldr r3, [r7, #8] - 8002ad2: 011b lsls r3, r3, #4 - 8002ad4: 4413 add r3, r2 - 8002ad6: f503 73dc add.w r3, r3, #440 @ 0x1b8 - 8002ada: 681b ldr r3, [r3, #0] - 8002adc: 0a1a lsrs r2, r3, #8 - 8002ade: 683b ldr r3, [r7, #0] - 8002ae0: 3301 adds r3, #1 - 8002ae2: b2d2 uxtb r2, r2 - 8002ae4: 701a strb r2, [r3, #0] + 8002b04: 68fb ldr r3, [r7, #12] + 8002b06: 681a ldr r2, [r3, #0] + 8002b08: 68bb ldr r3, [r7, #8] + 8002b0a: 011b lsls r3, r3, #4 + 8002b0c: 4413 add r3, r2 + 8002b0e: f503 73dc add.w r3, r3, #440 @ 0x1b8 + 8002b12: 681b ldr r3, [r3, #0] + 8002b14: 0a1a lsrs r2, r3, #8 + 8002b16: 683b ldr r3, [r7, #0] + 8002b18: 3301 adds r3, #1 + 8002b1a: b2d2 uxtb r2, r2 + 8002b1c: 701a strb r2, [r3, #0] aData[2] = (uint8_t)((CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos); - 8002ae6: 68fb ldr r3, [r7, #12] - 8002ae8: 681a ldr r2, [r3, #0] - 8002aea: 68bb ldr r3, [r7, #8] - 8002aec: 011b lsls r3, r3, #4 - 8002aee: 4413 add r3, r2 - 8002af0: f503 73dc add.w r3, r3, #440 @ 0x1b8 - 8002af4: 681b ldr r3, [r3, #0] - 8002af6: 0c1a lsrs r2, r3, #16 - 8002af8: 683b ldr r3, [r7, #0] - 8002afa: 3302 adds r3, #2 - 8002afc: b2d2 uxtb r2, r2 - 8002afe: 701a strb r2, [r3, #0] + 8002b1e: 68fb ldr r3, [r7, #12] + 8002b20: 681a ldr r2, [r3, #0] + 8002b22: 68bb ldr r3, [r7, #8] + 8002b24: 011b lsls r3, r3, #4 + 8002b26: 4413 add r3, r2 + 8002b28: f503 73dc add.w r3, r3, #440 @ 0x1b8 + 8002b2c: 681b ldr r3, [r3, #0] + 8002b2e: 0c1a lsrs r2, r3, #16 + 8002b30: 683b ldr r3, [r7, #0] + 8002b32: 3302 adds r3, #2 + 8002b34: b2d2 uxtb r2, r2 + 8002b36: 701a strb r2, [r3, #0] aData[3] = (uint8_t)((CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos); - 8002b00: 68fb ldr r3, [r7, #12] - 8002b02: 681a ldr r2, [r3, #0] - 8002b04: 68bb ldr r3, [r7, #8] - 8002b06: 011b lsls r3, r3, #4 - 8002b08: 4413 add r3, r2 - 8002b0a: f503 73dc add.w r3, r3, #440 @ 0x1b8 - 8002b0e: 681b ldr r3, [r3, #0] - 8002b10: 0e1a lsrs r2, r3, #24 - 8002b12: 683b ldr r3, [r7, #0] - 8002b14: 3303 adds r3, #3 - 8002b16: b2d2 uxtb r2, r2 - 8002b18: 701a strb r2, [r3, #0] + 8002b38: 68fb ldr r3, [r7, #12] + 8002b3a: 681a ldr r2, [r3, #0] + 8002b3c: 68bb ldr r3, [r7, #8] + 8002b3e: 011b lsls r3, r3, #4 + 8002b40: 4413 add r3, r2 + 8002b42: f503 73dc add.w r3, r3, #440 @ 0x1b8 + 8002b46: 681b ldr r3, [r3, #0] + 8002b48: 0e1a lsrs r2, r3, #24 + 8002b4a: 683b ldr r3, [r7, #0] + 8002b4c: 3303 adds r3, #3 + 8002b4e: b2d2 uxtb r2, r2 + 8002b50: 701a strb r2, [r3, #0] aData[4] = (uint8_t)((CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos); - 8002b1a: 68fb ldr r3, [r7, #12] - 8002b1c: 681a ldr r2, [r3, #0] - 8002b1e: 68bb ldr r3, [r7, #8] - 8002b20: 011b lsls r3, r3, #4 - 8002b22: 4413 add r3, r2 - 8002b24: f503 73de add.w r3, r3, #444 @ 0x1bc - 8002b28: 681a ldr r2, [r3, #0] - 8002b2a: 683b ldr r3, [r7, #0] - 8002b2c: 3304 adds r3, #4 - 8002b2e: b2d2 uxtb r2, r2 - 8002b30: 701a strb r2, [r3, #0] + 8002b52: 68fb ldr r3, [r7, #12] + 8002b54: 681a ldr r2, [r3, #0] + 8002b56: 68bb ldr r3, [r7, #8] + 8002b58: 011b lsls r3, r3, #4 + 8002b5a: 4413 add r3, r2 + 8002b5c: f503 73de add.w r3, r3, #444 @ 0x1bc + 8002b60: 681a ldr r2, [r3, #0] + 8002b62: 683b ldr r3, [r7, #0] + 8002b64: 3304 adds r3, #4 + 8002b66: b2d2 uxtb r2, r2 + 8002b68: 701a strb r2, [r3, #0] aData[5] = (uint8_t)((CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos); - 8002b32: 68fb ldr r3, [r7, #12] - 8002b34: 681a ldr r2, [r3, #0] - 8002b36: 68bb ldr r3, [r7, #8] - 8002b38: 011b lsls r3, r3, #4 - 8002b3a: 4413 add r3, r2 - 8002b3c: f503 73de add.w r3, r3, #444 @ 0x1bc - 8002b40: 681b ldr r3, [r3, #0] - 8002b42: 0a1a lsrs r2, r3, #8 - 8002b44: 683b ldr r3, [r7, #0] - 8002b46: 3305 adds r3, #5 - 8002b48: b2d2 uxtb r2, r2 - 8002b4a: 701a strb r2, [r3, #0] + 8002b6a: 68fb ldr r3, [r7, #12] + 8002b6c: 681a ldr r2, [r3, #0] + 8002b6e: 68bb ldr r3, [r7, #8] + 8002b70: 011b lsls r3, r3, #4 + 8002b72: 4413 add r3, r2 + 8002b74: f503 73de add.w r3, r3, #444 @ 0x1bc + 8002b78: 681b ldr r3, [r3, #0] + 8002b7a: 0a1a lsrs r2, r3, #8 + 8002b7c: 683b ldr r3, [r7, #0] + 8002b7e: 3305 adds r3, #5 + 8002b80: b2d2 uxtb r2, r2 + 8002b82: 701a strb r2, [r3, #0] aData[6] = (uint8_t)((CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos); - 8002b4c: 68fb ldr r3, [r7, #12] - 8002b4e: 681a ldr r2, [r3, #0] - 8002b50: 68bb ldr r3, [r7, #8] - 8002b52: 011b lsls r3, r3, #4 - 8002b54: 4413 add r3, r2 - 8002b56: f503 73de add.w r3, r3, #444 @ 0x1bc - 8002b5a: 681b ldr r3, [r3, #0] - 8002b5c: 0c1a lsrs r2, r3, #16 - 8002b5e: 683b ldr r3, [r7, #0] - 8002b60: 3306 adds r3, #6 - 8002b62: b2d2 uxtb r2, r2 - 8002b64: 701a strb r2, [r3, #0] + 8002b84: 68fb ldr r3, [r7, #12] + 8002b86: 681a ldr r2, [r3, #0] + 8002b88: 68bb ldr r3, [r7, #8] + 8002b8a: 011b lsls r3, r3, #4 + 8002b8c: 4413 add r3, r2 + 8002b8e: f503 73de add.w r3, r3, #444 @ 0x1bc + 8002b92: 681b ldr r3, [r3, #0] + 8002b94: 0c1a lsrs r2, r3, #16 + 8002b96: 683b ldr r3, [r7, #0] + 8002b98: 3306 adds r3, #6 + 8002b9a: b2d2 uxtb r2, r2 + 8002b9c: 701a strb r2, [r3, #0] aData[7] = (uint8_t)((CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos); - 8002b66: 68fb ldr r3, [r7, #12] - 8002b68: 681a ldr r2, [r3, #0] - 8002b6a: 68bb ldr r3, [r7, #8] - 8002b6c: 011b lsls r3, r3, #4 - 8002b6e: 4413 add r3, r2 - 8002b70: f503 73de add.w r3, r3, #444 @ 0x1bc - 8002b74: 681b ldr r3, [r3, #0] - 8002b76: 0e1a lsrs r2, r3, #24 - 8002b78: 683b ldr r3, [r7, #0] - 8002b7a: 3307 adds r3, #7 - 8002b7c: b2d2 uxtb r2, r2 - 8002b7e: 701a strb r2, [r3, #0] + 8002b9e: 68fb ldr r3, [r7, #12] + 8002ba0: 681a ldr r2, [r3, #0] + 8002ba2: 68bb ldr r3, [r7, #8] + 8002ba4: 011b lsls r3, r3, #4 + 8002ba6: 4413 add r3, r2 + 8002ba8: f503 73de add.w r3, r3, #444 @ 0x1bc + 8002bac: 681b ldr r3, [r3, #0] + 8002bae: 0e1a lsrs r2, r3, #24 + 8002bb0: 683b ldr r3, [r7, #0] + 8002bb2: 3307 adds r3, #7 + 8002bb4: b2d2 uxtb r2, r2 + 8002bb6: 701a strb r2, [r3, #0] /* Release the FIFO */ if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ - 8002b80: 68bb ldr r3, [r7, #8] - 8002b82: 2b00 cmp r3, #0 - 8002b84: d108 bne.n 8002b98 + 8002bb8: 68bb ldr r3, [r7, #8] + 8002bba: 2b00 cmp r3, #0 + 8002bbc: d108 bne.n 8002bd0 { /* Release RX FIFO 0 */ SET_BIT(hcan->Instance->RF0R, CAN_RF0R_RFOM0); - 8002b86: 68fb ldr r3, [r7, #12] - 8002b88: 681b ldr r3, [r3, #0] - 8002b8a: 68da ldr r2, [r3, #12] - 8002b8c: 68fb ldr r3, [r7, #12] - 8002b8e: 681b ldr r3, [r3, #0] - 8002b90: f042 0220 orr.w r2, r2, #32 - 8002b94: 60da str r2, [r3, #12] - 8002b96: e007 b.n 8002ba8 + 8002bbe: 68fb ldr r3, [r7, #12] + 8002bc0: 681b ldr r3, [r3, #0] + 8002bc2: 68da ldr r2, [r3, #12] + 8002bc4: 68fb ldr r3, [r7, #12] + 8002bc6: 681b ldr r3, [r3, #0] + 8002bc8: f042 0220 orr.w r2, r2, #32 + 8002bcc: 60da str r2, [r3, #12] + 8002bce: e007 b.n 8002be0 } else /* Rx element is assigned to Rx FIFO 1 */ { /* Release RX FIFO 1 */ SET_BIT(hcan->Instance->RF1R, CAN_RF1R_RFOM1); - 8002b98: 68fb ldr r3, [r7, #12] - 8002b9a: 681b ldr r3, [r3, #0] - 8002b9c: 691a ldr r2, [r3, #16] - 8002b9e: 68fb ldr r3, [r7, #12] - 8002ba0: 681b ldr r3, [r3, #0] - 8002ba2: f042 0220 orr.w r2, r2, #32 - 8002ba6: 611a str r2, [r3, #16] + 8002bd0: 68fb ldr r3, [r7, #12] + 8002bd2: 681b ldr r3, [r3, #0] + 8002bd4: 691a ldr r2, [r3, #16] + 8002bd6: 68fb ldr r3, [r7, #12] + 8002bd8: 681b ldr r3, [r3, #0] + 8002bda: f042 0220 orr.w r2, r2, #32 + 8002bde: 611a str r2, [r3, #16] } /* Return function status */ return HAL_OK; - 8002ba8: 2300 movs r3, #0 - 8002baa: e006 b.n 8002bba + 8002be0: 2300 movs r3, #0 + 8002be2: e006 b.n 8002bf2 } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; - 8002bac: 68fb ldr r3, [r7, #12] - 8002bae: 6a5b ldr r3, [r3, #36] @ 0x24 - 8002bb0: f443 2280 orr.w r2, r3, #262144 @ 0x40000 - 8002bb4: 68fb ldr r3, [r7, #12] - 8002bb6: 625a str r2, [r3, #36] @ 0x24 + 8002be4: 68fb ldr r3, [r7, #12] + 8002be6: 6a5b ldr r3, [r3, #36] @ 0x24 + 8002be8: f443 2280 orr.w r2, r3, #262144 @ 0x40000 + 8002bec: 68fb ldr r3, [r7, #12] + 8002bee: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; - 8002bb8: 2301 movs r3, #1 + 8002bf0: 2301 movs r3, #1 } } - 8002bba: 4618 mov r0, r3 - 8002bbc: 371c adds r7, #28 - 8002bbe: 46bd mov sp, r7 - 8002bc0: f85d 7b04 ldr.w r7, [sp], #4 - 8002bc4: 4770 bx lr + 8002bf2: 4618 mov r0, r3 + 8002bf4: 371c adds r7, #28 + 8002bf6: 46bd mov sp, r7 + 8002bf8: f85d 7b04 ldr.w r7, [sp], #4 + 8002bfc: 4770 bx lr -08002bc6 : +08002bfe : * @param ActiveITs indicates which interrupts will be enabled. * This parameter can be any combination of @arg CAN_Interrupts. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs) { - 8002bc6: b480 push {r7} - 8002bc8: b085 sub sp, #20 - 8002bca: af00 add r7, sp, #0 - 8002bcc: 6078 str r0, [r7, #4] - 8002bce: 6039 str r1, [r7, #0] + 8002bfe: b480 push {r7} + 8002c00: b085 sub sp, #20 + 8002c02: af00 add r7, sp, #0 + 8002c04: 6078 str r0, [r7, #4] + 8002c06: 6039 str r1, [r7, #0] HAL_CAN_StateTypeDef state = hcan->State; - 8002bd0: 687b ldr r3, [r7, #4] - 8002bd2: f893 3020 ldrb.w r3, [r3, #32] - 8002bd6: 73fb strb r3, [r7, #15] + 8002c08: 687b ldr r3, [r7, #4] + 8002c0a: f893 3020 ldrb.w r3, [r3, #32] + 8002c0e: 73fb strb r3, [r7, #15] /* Check function parameters */ assert_param(IS_CAN_IT(ActiveITs)); if ((state == HAL_CAN_STATE_READY) || - 8002bd8: 7bfb ldrb r3, [r7, #15] - 8002bda: 2b01 cmp r3, #1 - 8002bdc: d002 beq.n 8002be4 - 8002bde: 7bfb ldrb r3, [r7, #15] - 8002be0: 2b02 cmp r3, #2 - 8002be2: d109 bne.n 8002bf8 + 8002c10: 7bfb ldrb r3, [r7, #15] + 8002c12: 2b01 cmp r3, #1 + 8002c14: d002 beq.n 8002c1c + 8002c16: 7bfb ldrb r3, [r7, #15] + 8002c18: 2b02 cmp r3, #2 + 8002c1a: d109 bne.n 8002c30 (state == HAL_CAN_STATE_LISTENING)) { /* Enable the selected interrupts */ __HAL_CAN_ENABLE_IT(hcan, ActiveITs); - 8002be4: 687b ldr r3, [r7, #4] - 8002be6: 681b ldr r3, [r3, #0] - 8002be8: 6959 ldr r1, [r3, #20] - 8002bea: 687b ldr r3, [r7, #4] - 8002bec: 681b ldr r3, [r3, #0] - 8002bee: 683a ldr r2, [r7, #0] - 8002bf0: 430a orrs r2, r1 - 8002bf2: 615a str r2, [r3, #20] + 8002c1c: 687b ldr r3, [r7, #4] + 8002c1e: 681b ldr r3, [r3, #0] + 8002c20: 6959 ldr r1, [r3, #20] + 8002c22: 687b ldr r3, [r7, #4] + 8002c24: 681b ldr r3, [r3, #0] + 8002c26: 683a ldr r2, [r7, #0] + 8002c28: 430a orrs r2, r1 + 8002c2a: 615a str r2, [r3, #20] /* Return function status */ return HAL_OK; - 8002bf4: 2300 movs r3, #0 - 8002bf6: e006 b.n 8002c06 + 8002c2c: 2300 movs r3, #0 + 8002c2e: e006 b.n 8002c3e } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; - 8002bf8: 687b ldr r3, [r7, #4] - 8002bfa: 6a5b ldr r3, [r3, #36] @ 0x24 - 8002bfc: f443 2280 orr.w r2, r3, #262144 @ 0x40000 - 8002c00: 687b ldr r3, [r7, #4] - 8002c02: 625a str r2, [r3, #36] @ 0x24 + 8002c30: 687b ldr r3, [r7, #4] + 8002c32: 6a5b ldr r3, [r3, #36] @ 0x24 + 8002c34: f443 2280 orr.w r2, r3, #262144 @ 0x40000 + 8002c38: 687b ldr r3, [r7, #4] + 8002c3a: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; - 8002c04: 2301 movs r3, #1 + 8002c3c: 2301 movs r3, #1 } } - 8002c06: 4618 mov r0, r3 - 8002c08: 3714 adds r7, #20 - 8002c0a: 46bd mov sp, r7 - 8002c0c: f85d 7b04 ldr.w r7, [sp], #4 - 8002c10: 4770 bx lr + 8002c3e: 4618 mov r0, r3 + 8002c40: 3714 adds r7, #20 + 8002c42: 46bd mov sp, r7 + 8002c44: f85d 7b04 ldr.w r7, [sp], #4 + 8002c48: 4770 bx lr -08002c12 : +08002c4a : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan) { - 8002c12: b580 push {r7, lr} - 8002c14: b08a sub sp, #40 @ 0x28 - 8002c16: af00 add r7, sp, #0 - 8002c18: 6078 str r0, [r7, #4] + 8002c4a: b580 push {r7, lr} + 8002c4c: b08a sub sp, #40 @ 0x28 + 8002c4e: af00 add r7, sp, #0 + 8002c50: 6078 str r0, [r7, #4] uint32_t errorcode = HAL_CAN_ERROR_NONE; - 8002c1a: 2300 movs r3, #0 - 8002c1c: 627b str r3, [r7, #36] @ 0x24 + 8002c52: 2300 movs r3, #0 + 8002c54: 627b str r3, [r7, #36] @ 0x24 uint32_t interrupts = READ_REG(hcan->Instance->IER); - 8002c1e: 687b ldr r3, [r7, #4] - 8002c20: 681b ldr r3, [r3, #0] - 8002c22: 695b ldr r3, [r3, #20] - 8002c24: 623b str r3, [r7, #32] + 8002c56: 687b ldr r3, [r7, #4] + 8002c58: 681b ldr r3, [r3, #0] + 8002c5a: 695b ldr r3, [r3, #20] + 8002c5c: 623b str r3, [r7, #32] uint32_t msrflags = READ_REG(hcan->Instance->MSR); - 8002c26: 687b ldr r3, [r7, #4] - 8002c28: 681b ldr r3, [r3, #0] - 8002c2a: 685b ldr r3, [r3, #4] - 8002c2c: 61fb str r3, [r7, #28] + 8002c5e: 687b ldr r3, [r7, #4] + 8002c60: 681b ldr r3, [r3, #0] + 8002c62: 685b ldr r3, [r3, #4] + 8002c64: 61fb str r3, [r7, #28] uint32_t tsrflags = READ_REG(hcan->Instance->TSR); - 8002c2e: 687b ldr r3, [r7, #4] - 8002c30: 681b ldr r3, [r3, #0] - 8002c32: 689b ldr r3, [r3, #8] - 8002c34: 61bb str r3, [r7, #24] + 8002c66: 687b ldr r3, [r7, #4] + 8002c68: 681b ldr r3, [r3, #0] + 8002c6a: 689b ldr r3, [r3, #8] + 8002c6c: 61bb str r3, [r7, #24] uint32_t rf0rflags = READ_REG(hcan->Instance->RF0R); - 8002c36: 687b ldr r3, [r7, #4] - 8002c38: 681b ldr r3, [r3, #0] - 8002c3a: 68db ldr r3, [r3, #12] - 8002c3c: 617b str r3, [r7, #20] + 8002c6e: 687b ldr r3, [r7, #4] + 8002c70: 681b ldr r3, [r3, #0] + 8002c72: 68db ldr r3, [r3, #12] + 8002c74: 617b str r3, [r7, #20] uint32_t rf1rflags = READ_REG(hcan->Instance->RF1R); - 8002c3e: 687b ldr r3, [r7, #4] - 8002c40: 681b ldr r3, [r3, #0] - 8002c42: 691b ldr r3, [r3, #16] - 8002c44: 613b str r3, [r7, #16] + 8002c76: 687b ldr r3, [r7, #4] + 8002c78: 681b ldr r3, [r3, #0] + 8002c7a: 691b ldr r3, [r3, #16] + 8002c7c: 613b str r3, [r7, #16] uint32_t esrflags = READ_REG(hcan->Instance->ESR); - 8002c46: 687b ldr r3, [r7, #4] - 8002c48: 681b ldr r3, [r3, #0] - 8002c4a: 699b ldr r3, [r3, #24] - 8002c4c: 60fb str r3, [r7, #12] + 8002c7e: 687b ldr r3, [r7, #4] + 8002c80: 681b ldr r3, [r3, #0] + 8002c82: 699b ldr r3, [r3, #24] + 8002c84: 60fb str r3, [r7, #12] /* Transmit Mailbox empty interrupt management *****************************/ if ((interrupts & CAN_IT_TX_MAILBOX_EMPTY) != 0U) - 8002c4e: 6a3b ldr r3, [r7, #32] - 8002c50: f003 0301 and.w r3, r3, #1 - 8002c54: 2b00 cmp r3, #0 - 8002c56: d07c beq.n 8002d52 + 8002c86: 6a3b ldr r3, [r7, #32] + 8002c88: f003 0301 and.w r3, r3, #1 + 8002c8c: 2b00 cmp r3, #0 + 8002c8e: d07c beq.n 8002d8a { /* Transmit Mailbox 0 management *****************************************/ if ((tsrflags & CAN_TSR_RQCP0) != 0U) - 8002c58: 69bb ldr r3, [r7, #24] - 8002c5a: f003 0301 and.w r3, r3, #1 - 8002c5e: 2b00 cmp r3, #0 - 8002c60: d023 beq.n 8002caa + 8002c90: 69bb ldr r3, [r7, #24] + 8002c92: f003 0301 and.w r3, r3, #1 + 8002c96: 2b00 cmp r3, #0 + 8002c98: d023 beq.n 8002ce2 { /* Clear the Transmission Complete flag (and TXOK0,ALST0,TERR0 bits) */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP0); - 8002c62: 687b ldr r3, [r7, #4] - 8002c64: 681b ldr r3, [r3, #0] - 8002c66: 2201 movs r2, #1 - 8002c68: 609a str r2, [r3, #8] + 8002c9a: 687b ldr r3, [r7, #4] + 8002c9c: 681b ldr r3, [r3, #0] + 8002c9e: 2201 movs r2, #1 + 8002ca0: 609a str r2, [r3, #8] if ((tsrflags & CAN_TSR_TXOK0) != 0U) - 8002c6a: 69bb ldr r3, [r7, #24] - 8002c6c: f003 0302 and.w r3, r3, #2 - 8002c70: 2b00 cmp r3, #0 - 8002c72: d003 beq.n 8002c7c + 8002ca2: 69bb ldr r3, [r7, #24] + 8002ca4: f003 0302 and.w r3, r3, #2 + 8002ca8: 2b00 cmp r3, #0 + 8002caa: d003 beq.n 8002cb4 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox0CompleteCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox0CompleteCallback(hcan); - 8002c74: 6878 ldr r0, [r7, #4] - 8002c76: f000 f983 bl 8002f80 - 8002c7a: e016 b.n 8002caa + 8002cac: 6878 ldr r0, [r7, #4] + 8002cae: f000 f983 bl 8002fb8 + 8002cb2: e016 b.n 8002ce2 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } else { if ((tsrflags & CAN_TSR_ALST0) != 0U) - 8002c7c: 69bb ldr r3, [r7, #24] - 8002c7e: f003 0304 and.w r3, r3, #4 - 8002c82: 2b00 cmp r3, #0 - 8002c84: d004 beq.n 8002c90 + 8002cb4: 69bb ldr r3, [r7, #24] + 8002cb6: f003 0304 and.w r3, r3, #4 + 8002cba: 2b00 cmp r3, #0 + 8002cbc: d004 beq.n 8002cc8 { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_ALST0; - 8002c86: 6a7b ldr r3, [r7, #36] @ 0x24 - 8002c88: f443 6300 orr.w r3, r3, #2048 @ 0x800 - 8002c8c: 627b str r3, [r7, #36] @ 0x24 - 8002c8e: e00c b.n 8002caa + 8002cbe: 6a7b ldr r3, [r7, #36] @ 0x24 + 8002cc0: f443 6300 orr.w r3, r3, #2048 @ 0x800 + 8002cc4: 627b str r3, [r7, #36] @ 0x24 + 8002cc6: e00c b.n 8002ce2 } else if ((tsrflags & CAN_TSR_TERR0) != 0U) - 8002c90: 69bb ldr r3, [r7, #24] - 8002c92: f003 0308 and.w r3, r3, #8 - 8002c96: 2b00 cmp r3, #0 - 8002c98: d004 beq.n 8002ca4 + 8002cc8: 69bb ldr r3, [r7, #24] + 8002cca: f003 0308 and.w r3, r3, #8 + 8002cce: 2b00 cmp r3, #0 + 8002cd0: d004 beq.n 8002cdc { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_TERR0; - 8002c9a: 6a7b ldr r3, [r7, #36] @ 0x24 - 8002c9c: f443 5380 orr.w r3, r3, #4096 @ 0x1000 - 8002ca0: 627b str r3, [r7, #36] @ 0x24 - 8002ca2: e002 b.n 8002caa + 8002cd2: 6a7b ldr r3, [r7, #36] @ 0x24 + 8002cd4: f443 5380 orr.w r3, r3, #4096 @ 0x1000 + 8002cd8: 627b str r3, [r7, #36] @ 0x24 + 8002cda: e002 b.n 8002ce2 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox0AbortCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox0AbortCallback(hcan); - 8002ca4: 6878 ldr r0, [r7, #4] - 8002ca6: f000 f989 bl 8002fbc + 8002cdc: 6878 ldr r0, [r7, #4] + 8002cde: f000 f989 bl 8002ff4 } } } /* Transmit Mailbox 1 management *****************************************/ if ((tsrflags & CAN_TSR_RQCP1) != 0U) - 8002caa: 69bb ldr r3, [r7, #24] - 8002cac: f403 7380 and.w r3, r3, #256 @ 0x100 - 8002cb0: 2b00 cmp r3, #0 - 8002cb2: d024 beq.n 8002cfe + 8002ce2: 69bb ldr r3, [r7, #24] + 8002ce4: f403 7380 and.w r3, r3, #256 @ 0x100 + 8002ce8: 2b00 cmp r3, #0 + 8002cea: d024 beq.n 8002d36 { /* Clear the Transmission Complete flag (and TXOK1,ALST1,TERR1 bits) */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP1); - 8002cb4: 687b ldr r3, [r7, #4] - 8002cb6: 681b ldr r3, [r3, #0] - 8002cb8: f44f 7280 mov.w r2, #256 @ 0x100 - 8002cbc: 609a str r2, [r3, #8] + 8002cec: 687b ldr r3, [r7, #4] + 8002cee: 681b ldr r3, [r3, #0] + 8002cf0: f44f 7280 mov.w r2, #256 @ 0x100 + 8002cf4: 609a str r2, [r3, #8] if ((tsrflags & CAN_TSR_TXOK1) != 0U) - 8002cbe: 69bb ldr r3, [r7, #24] - 8002cc0: f403 7300 and.w r3, r3, #512 @ 0x200 - 8002cc4: 2b00 cmp r3, #0 - 8002cc6: d003 beq.n 8002cd0 + 8002cf6: 69bb ldr r3, [r7, #24] + 8002cf8: f403 7300 and.w r3, r3, #512 @ 0x200 + 8002cfc: 2b00 cmp r3, #0 + 8002cfe: d003 beq.n 8002d08 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox1CompleteCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox1CompleteCallback(hcan); - 8002cc8: 6878 ldr r0, [r7, #4] - 8002cca: f000 f963 bl 8002f94 - 8002cce: e016 b.n 8002cfe + 8002d00: 6878 ldr r0, [r7, #4] + 8002d02: f000 f963 bl 8002fcc + 8002d06: e016 b.n 8002d36 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } else { if ((tsrflags & CAN_TSR_ALST1) != 0U) - 8002cd0: 69bb ldr r3, [r7, #24] - 8002cd2: f403 6380 and.w r3, r3, #1024 @ 0x400 - 8002cd6: 2b00 cmp r3, #0 - 8002cd8: d004 beq.n 8002ce4 + 8002d08: 69bb ldr r3, [r7, #24] + 8002d0a: f403 6380 and.w r3, r3, #1024 @ 0x400 + 8002d0e: 2b00 cmp r3, #0 + 8002d10: d004 beq.n 8002d1c { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_ALST1; - 8002cda: 6a7b ldr r3, [r7, #36] @ 0x24 - 8002cdc: f443 5300 orr.w r3, r3, #8192 @ 0x2000 - 8002ce0: 627b str r3, [r7, #36] @ 0x24 - 8002ce2: e00c b.n 8002cfe + 8002d12: 6a7b ldr r3, [r7, #36] @ 0x24 + 8002d14: f443 5300 orr.w r3, r3, #8192 @ 0x2000 + 8002d18: 627b str r3, [r7, #36] @ 0x24 + 8002d1a: e00c b.n 8002d36 } else if ((tsrflags & CAN_TSR_TERR1) != 0U) - 8002ce4: 69bb ldr r3, [r7, #24] - 8002ce6: f403 6300 and.w r3, r3, #2048 @ 0x800 - 8002cea: 2b00 cmp r3, #0 - 8002cec: d004 beq.n 8002cf8 + 8002d1c: 69bb ldr r3, [r7, #24] + 8002d1e: f403 6300 and.w r3, r3, #2048 @ 0x800 + 8002d22: 2b00 cmp r3, #0 + 8002d24: d004 beq.n 8002d30 { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_TERR1; - 8002cee: 6a7b ldr r3, [r7, #36] @ 0x24 - 8002cf0: f443 4380 orr.w r3, r3, #16384 @ 0x4000 - 8002cf4: 627b str r3, [r7, #36] @ 0x24 - 8002cf6: e002 b.n 8002cfe + 8002d26: 6a7b ldr r3, [r7, #36] @ 0x24 + 8002d28: f443 4380 orr.w r3, r3, #16384 @ 0x4000 + 8002d2c: 627b str r3, [r7, #36] @ 0x24 + 8002d2e: e002 b.n 8002d36 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox1AbortCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox1AbortCallback(hcan); - 8002cf8: 6878 ldr r0, [r7, #4] - 8002cfa: f000 f969 bl 8002fd0 + 8002d30: 6878 ldr r0, [r7, #4] + 8002d32: f000 f969 bl 8003008 } } } /* Transmit Mailbox 2 management *****************************************/ if ((tsrflags & CAN_TSR_RQCP2) != 0U) - 8002cfe: 69bb ldr r3, [r7, #24] - 8002d00: f403 3380 and.w r3, r3, #65536 @ 0x10000 - 8002d04: 2b00 cmp r3, #0 - 8002d06: d024 beq.n 8002d52 + 8002d36: 69bb ldr r3, [r7, #24] + 8002d38: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 8002d3c: 2b00 cmp r3, #0 + 8002d3e: d024 beq.n 8002d8a { /* Clear the Transmission Complete flag (and TXOK2,ALST2,TERR2 bits) */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP2); - 8002d08: 687b ldr r3, [r7, #4] - 8002d0a: 681b ldr r3, [r3, #0] - 8002d0c: f44f 3280 mov.w r2, #65536 @ 0x10000 - 8002d10: 609a str r2, [r3, #8] + 8002d40: 687b ldr r3, [r7, #4] + 8002d42: 681b ldr r3, [r3, #0] + 8002d44: f44f 3280 mov.w r2, #65536 @ 0x10000 + 8002d48: 609a str r2, [r3, #8] if ((tsrflags & CAN_TSR_TXOK2) != 0U) - 8002d12: 69bb ldr r3, [r7, #24] - 8002d14: f403 3300 and.w r3, r3, #131072 @ 0x20000 - 8002d18: 2b00 cmp r3, #0 - 8002d1a: d003 beq.n 8002d24 + 8002d4a: 69bb ldr r3, [r7, #24] + 8002d4c: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 8002d50: 2b00 cmp r3, #0 + 8002d52: d003 beq.n 8002d5c #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox2CompleteCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox2CompleteCallback(hcan); - 8002d1c: 6878 ldr r0, [r7, #4] - 8002d1e: f000 f943 bl 8002fa8 - 8002d22: e016 b.n 8002d52 + 8002d54: 6878 ldr r0, [r7, #4] + 8002d56: f000 f943 bl 8002fe0 + 8002d5a: e016 b.n 8002d8a #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } else { if ((tsrflags & CAN_TSR_ALST2) != 0U) - 8002d24: 69bb ldr r3, [r7, #24] - 8002d26: f403 2380 and.w r3, r3, #262144 @ 0x40000 - 8002d2a: 2b00 cmp r3, #0 - 8002d2c: d004 beq.n 8002d38 + 8002d5c: 69bb ldr r3, [r7, #24] + 8002d5e: f403 2380 and.w r3, r3, #262144 @ 0x40000 + 8002d62: 2b00 cmp r3, #0 + 8002d64: d004 beq.n 8002d70 { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_ALST2; - 8002d2e: 6a7b ldr r3, [r7, #36] @ 0x24 - 8002d30: f443 4300 orr.w r3, r3, #32768 @ 0x8000 - 8002d34: 627b str r3, [r7, #36] @ 0x24 - 8002d36: e00c b.n 8002d52 + 8002d66: 6a7b ldr r3, [r7, #36] @ 0x24 + 8002d68: f443 4300 orr.w r3, r3, #32768 @ 0x8000 + 8002d6c: 627b str r3, [r7, #36] @ 0x24 + 8002d6e: e00c b.n 8002d8a } else if ((tsrflags & CAN_TSR_TERR2) != 0U) - 8002d38: 69bb ldr r3, [r7, #24] - 8002d3a: f403 2300 and.w r3, r3, #524288 @ 0x80000 - 8002d3e: 2b00 cmp r3, #0 - 8002d40: d004 beq.n 8002d4c + 8002d70: 69bb ldr r3, [r7, #24] + 8002d72: f403 2300 and.w r3, r3, #524288 @ 0x80000 + 8002d76: 2b00 cmp r3, #0 + 8002d78: d004 beq.n 8002d84 { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_TERR2; - 8002d42: 6a7b ldr r3, [r7, #36] @ 0x24 - 8002d44: f443 3380 orr.w r3, r3, #65536 @ 0x10000 - 8002d48: 627b str r3, [r7, #36] @ 0x24 - 8002d4a: e002 b.n 8002d52 + 8002d7a: 6a7b ldr r3, [r7, #36] @ 0x24 + 8002d7c: f443 3380 orr.w r3, r3, #65536 @ 0x10000 + 8002d80: 627b str r3, [r7, #36] @ 0x24 + 8002d82: e002 b.n 8002d8a #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox2AbortCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox2AbortCallback(hcan); - 8002d4c: 6878 ldr r0, [r7, #4] - 8002d4e: f000 f949 bl 8002fe4 + 8002d84: 6878 ldr r0, [r7, #4] + 8002d86: f000 f949 bl 800301c } } } /* Receive FIFO 0 overrun interrupt management *****************************/ if ((interrupts & CAN_IT_RX_FIFO0_OVERRUN) != 0U) - 8002d52: 6a3b ldr r3, [r7, #32] - 8002d54: f003 0308 and.w r3, r3, #8 - 8002d58: 2b00 cmp r3, #0 - 8002d5a: d00c beq.n 8002d76 + 8002d8a: 6a3b ldr r3, [r7, #32] + 8002d8c: f003 0308 and.w r3, r3, #8 + 8002d90: 2b00 cmp r3, #0 + 8002d92: d00c beq.n 8002dae { if ((rf0rflags & CAN_RF0R_FOVR0) != 0U) - 8002d5c: 697b ldr r3, [r7, #20] - 8002d5e: f003 0310 and.w r3, r3, #16 - 8002d62: 2b00 cmp r3, #0 - 8002d64: d007 beq.n 8002d76 + 8002d94: 697b ldr r3, [r7, #20] + 8002d96: f003 0310 and.w r3, r3, #16 + 8002d9a: 2b00 cmp r3, #0 + 8002d9c: d007 beq.n 8002dae { /* Set CAN error code to Rx Fifo 0 overrun error */ errorcode |= HAL_CAN_ERROR_RX_FOV0; - 8002d66: 6a7b ldr r3, [r7, #36] @ 0x24 - 8002d68: f443 7300 orr.w r3, r3, #512 @ 0x200 - 8002d6c: 627b str r3, [r7, #36] @ 0x24 + 8002d9e: 6a7b ldr r3, [r7, #36] @ 0x24 + 8002da0: f443 7300 orr.w r3, r3, #512 @ 0x200 + 8002da4: 627b str r3, [r7, #36] @ 0x24 /* Clear FIFO0 Overrun Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0); - 8002d6e: 687b ldr r3, [r7, #4] - 8002d70: 681b ldr r3, [r3, #0] - 8002d72: 2210 movs r2, #16 - 8002d74: 60da str r2, [r3, #12] + 8002da6: 687b ldr r3, [r7, #4] + 8002da8: 681b ldr r3, [r3, #0] + 8002daa: 2210 movs r2, #16 + 8002dac: 60da str r2, [r3, #12] } } /* Receive FIFO 0 full interrupt management ********************************/ if ((interrupts & CAN_IT_RX_FIFO0_FULL) != 0U) - 8002d76: 6a3b ldr r3, [r7, #32] - 8002d78: f003 0304 and.w r3, r3, #4 - 8002d7c: 2b00 cmp r3, #0 - 8002d7e: d00b beq.n 8002d98 + 8002dae: 6a3b ldr r3, [r7, #32] + 8002db0: f003 0304 and.w r3, r3, #4 + 8002db4: 2b00 cmp r3, #0 + 8002db6: d00b beq.n 8002dd0 { if ((rf0rflags & CAN_RF0R_FULL0) != 0U) - 8002d80: 697b ldr r3, [r7, #20] - 8002d82: f003 0308 and.w r3, r3, #8 - 8002d86: 2b00 cmp r3, #0 - 8002d88: d006 beq.n 8002d98 + 8002db8: 697b ldr r3, [r7, #20] + 8002dba: f003 0308 and.w r3, r3, #8 + 8002dbe: 2b00 cmp r3, #0 + 8002dc0: d006 beq.n 8002dd0 { /* Clear FIFO 0 full Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0); - 8002d8a: 687b ldr r3, [r7, #4] - 8002d8c: 681b ldr r3, [r3, #0] - 8002d8e: 2208 movs r2, #8 - 8002d90: 60da str r2, [r3, #12] + 8002dc2: 687b ldr r3, [r7, #4] + 8002dc4: 681b ldr r3, [r3, #0] + 8002dc6: 2208 movs r2, #8 + 8002dc8: 60da str r2, [r3, #12] #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo0FullCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo0FullCallback(hcan); - 8002d92: 6878 ldr r0, [r7, #4] - 8002d94: f000 f930 bl 8002ff8 + 8002dca: 6878 ldr r0, [r7, #4] + 8002dcc: f000 f930 bl 8003030 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Receive FIFO 0 message pending interrupt management *********************/ if ((interrupts & CAN_IT_RX_FIFO0_MSG_PENDING) != 0U) - 8002d98: 6a3b ldr r3, [r7, #32] - 8002d9a: f003 0302 and.w r3, r3, #2 - 8002d9e: 2b00 cmp r3, #0 - 8002da0: d009 beq.n 8002db6 + 8002dd0: 6a3b ldr r3, [r7, #32] + 8002dd2: f003 0302 and.w r3, r3, #2 + 8002dd6: 2b00 cmp r3, #0 + 8002dd8: d009 beq.n 8002dee { /* Check if message is still pending */ if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != 0U) - 8002da2: 687b ldr r3, [r7, #4] - 8002da4: 681b ldr r3, [r3, #0] - 8002da6: 68db ldr r3, [r3, #12] - 8002da8: f003 0303 and.w r3, r3, #3 - 8002dac: 2b00 cmp r3, #0 - 8002dae: d002 beq.n 8002db6 + 8002dda: 687b ldr r3, [r7, #4] + 8002ddc: 681b ldr r3, [r3, #0] + 8002dde: 68db ldr r3, [r3, #12] + 8002de0: f003 0303 and.w r3, r3, #3 + 8002de4: 2b00 cmp r3, #0 + 8002de6: d002 beq.n 8002dee #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo0MsgPendingCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo0MsgPendingCallback(hcan); - 8002db0: 6878 ldr r0, [r7, #4] - 8002db2: f7fd fb0f bl 80003d4 + 8002de8: 6878 ldr r0, [r7, #4] + 8002dea: f7fd faf3 bl 80003d4 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Receive FIFO 1 overrun interrupt management *****************************/ if ((interrupts & CAN_IT_RX_FIFO1_OVERRUN) != 0U) - 8002db6: 6a3b ldr r3, [r7, #32] - 8002db8: f003 0340 and.w r3, r3, #64 @ 0x40 - 8002dbc: 2b00 cmp r3, #0 - 8002dbe: d00c beq.n 8002dda + 8002dee: 6a3b ldr r3, [r7, #32] + 8002df0: f003 0340 and.w r3, r3, #64 @ 0x40 + 8002df4: 2b00 cmp r3, #0 + 8002df6: d00c beq.n 8002e12 { if ((rf1rflags & CAN_RF1R_FOVR1) != 0U) - 8002dc0: 693b ldr r3, [r7, #16] - 8002dc2: f003 0310 and.w r3, r3, #16 - 8002dc6: 2b00 cmp r3, #0 - 8002dc8: d007 beq.n 8002dda + 8002df8: 693b ldr r3, [r7, #16] + 8002dfa: f003 0310 and.w r3, r3, #16 + 8002dfe: 2b00 cmp r3, #0 + 8002e00: d007 beq.n 8002e12 { /* Set CAN error code to Rx Fifo 1 overrun error */ errorcode |= HAL_CAN_ERROR_RX_FOV1; - 8002dca: 6a7b ldr r3, [r7, #36] @ 0x24 - 8002dcc: f443 6380 orr.w r3, r3, #1024 @ 0x400 - 8002dd0: 627b str r3, [r7, #36] @ 0x24 + 8002e02: 6a7b ldr r3, [r7, #36] @ 0x24 + 8002e04: f443 6380 orr.w r3, r3, #1024 @ 0x400 + 8002e08: 627b str r3, [r7, #36] @ 0x24 /* Clear FIFO1 Overrun Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1); - 8002dd2: 687b ldr r3, [r7, #4] - 8002dd4: 681b ldr r3, [r3, #0] - 8002dd6: 2210 movs r2, #16 - 8002dd8: 611a str r2, [r3, #16] + 8002e0a: 687b ldr r3, [r7, #4] + 8002e0c: 681b ldr r3, [r3, #0] + 8002e0e: 2210 movs r2, #16 + 8002e10: 611a str r2, [r3, #16] } } /* Receive FIFO 1 full interrupt management ********************************/ if ((interrupts & CAN_IT_RX_FIFO1_FULL) != 0U) - 8002dda: 6a3b ldr r3, [r7, #32] - 8002ddc: f003 0320 and.w r3, r3, #32 - 8002de0: 2b00 cmp r3, #0 - 8002de2: d00b beq.n 8002dfc + 8002e12: 6a3b ldr r3, [r7, #32] + 8002e14: f003 0320 and.w r3, r3, #32 + 8002e18: 2b00 cmp r3, #0 + 8002e1a: d00b beq.n 8002e34 { if ((rf1rflags & CAN_RF1R_FULL1) != 0U) - 8002de4: 693b ldr r3, [r7, #16] - 8002de6: f003 0308 and.w r3, r3, #8 - 8002dea: 2b00 cmp r3, #0 - 8002dec: d006 beq.n 8002dfc + 8002e1c: 693b ldr r3, [r7, #16] + 8002e1e: f003 0308 and.w r3, r3, #8 + 8002e22: 2b00 cmp r3, #0 + 8002e24: d006 beq.n 8002e34 { /* Clear FIFO 1 full Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1); - 8002dee: 687b ldr r3, [r7, #4] - 8002df0: 681b ldr r3, [r3, #0] - 8002df2: 2208 movs r2, #8 - 8002df4: 611a str r2, [r3, #16] + 8002e26: 687b ldr r3, [r7, #4] + 8002e28: 681b ldr r3, [r3, #0] + 8002e2a: 2208 movs r2, #8 + 8002e2c: 611a str r2, [r3, #16] #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo1FullCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo1FullCallback(hcan); - 8002df6: 6878 ldr r0, [r7, #4] - 8002df8: f000 f912 bl 8003020 + 8002e2e: 6878 ldr r0, [r7, #4] + 8002e30: f000 f912 bl 8003058 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Receive FIFO 1 message pending interrupt management *********************/ if ((interrupts & CAN_IT_RX_FIFO1_MSG_PENDING) != 0U) - 8002dfc: 6a3b ldr r3, [r7, #32] - 8002dfe: f003 0310 and.w r3, r3, #16 - 8002e02: 2b00 cmp r3, #0 - 8002e04: d009 beq.n 8002e1a + 8002e34: 6a3b ldr r3, [r7, #32] + 8002e36: f003 0310 and.w r3, r3, #16 + 8002e3a: 2b00 cmp r3, #0 + 8002e3c: d009 beq.n 8002e52 { /* Check if message is still pending */ if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != 0U) - 8002e06: 687b ldr r3, [r7, #4] - 8002e08: 681b ldr r3, [r3, #0] - 8002e0a: 691b ldr r3, [r3, #16] - 8002e0c: f003 0303 and.w r3, r3, #3 - 8002e10: 2b00 cmp r3, #0 - 8002e12: d002 beq.n 8002e1a + 8002e3e: 687b ldr r3, [r7, #4] + 8002e40: 681b ldr r3, [r3, #0] + 8002e42: 691b ldr r3, [r3, #16] + 8002e44: f003 0303 and.w r3, r3, #3 + 8002e48: 2b00 cmp r3, #0 + 8002e4a: d002 beq.n 8002e52 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo1MsgPendingCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo1MsgPendingCallback(hcan); - 8002e14: 6878 ldr r0, [r7, #4] - 8002e16: f000 f8f9 bl 800300c + 8002e4c: 6878 ldr r0, [r7, #4] + 8002e4e: f000 f8f9 bl 8003044 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Sleep interrupt management *********************************************/ if ((interrupts & CAN_IT_SLEEP_ACK) != 0U) - 8002e1a: 6a3b ldr r3, [r7, #32] - 8002e1c: f403 3300 and.w r3, r3, #131072 @ 0x20000 - 8002e20: 2b00 cmp r3, #0 - 8002e22: d00b beq.n 8002e3c + 8002e52: 6a3b ldr r3, [r7, #32] + 8002e54: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 8002e58: 2b00 cmp r3, #0 + 8002e5a: d00b beq.n 8002e74 { if ((msrflags & CAN_MSR_SLAKI) != 0U) - 8002e24: 69fb ldr r3, [r7, #28] - 8002e26: f003 0310 and.w r3, r3, #16 - 8002e2a: 2b00 cmp r3, #0 - 8002e2c: d006 beq.n 8002e3c + 8002e5c: 69fb ldr r3, [r7, #28] + 8002e5e: f003 0310 and.w r3, r3, #16 + 8002e62: 2b00 cmp r3, #0 + 8002e64: d006 beq.n 8002e74 { /* Clear Sleep interrupt Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_SLAKI); - 8002e2e: 687b ldr r3, [r7, #4] - 8002e30: 681b ldr r3, [r3, #0] - 8002e32: 2210 movs r2, #16 - 8002e34: 605a str r2, [r3, #4] + 8002e66: 687b ldr r3, [r7, #4] + 8002e68: 681b ldr r3, [r3, #0] + 8002e6a: 2210 movs r2, #16 + 8002e6c: 605a str r2, [r3, #4] #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->SleepCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_SleepCallback(hcan); - 8002e36: 6878 ldr r0, [r7, #4] - 8002e38: f000 f8fc bl 8003034 + 8002e6e: 6878 ldr r0, [r7, #4] + 8002e70: f000 f8fc bl 800306c #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* WakeUp interrupt management *********************************************/ if ((interrupts & CAN_IT_WAKEUP) != 0U) - 8002e3c: 6a3b ldr r3, [r7, #32] - 8002e3e: f403 3380 and.w r3, r3, #65536 @ 0x10000 - 8002e42: 2b00 cmp r3, #0 - 8002e44: d00b beq.n 8002e5e + 8002e74: 6a3b ldr r3, [r7, #32] + 8002e76: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 8002e7a: 2b00 cmp r3, #0 + 8002e7c: d00b beq.n 8002e96 { if ((msrflags & CAN_MSR_WKUI) != 0U) - 8002e46: 69fb ldr r3, [r7, #28] - 8002e48: f003 0308 and.w r3, r3, #8 - 8002e4c: 2b00 cmp r3, #0 - 8002e4e: d006 beq.n 8002e5e + 8002e7e: 69fb ldr r3, [r7, #28] + 8002e80: f003 0308 and.w r3, r3, #8 + 8002e84: 2b00 cmp r3, #0 + 8002e86: d006 beq.n 8002e96 { /* Clear WakeUp Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_WKU); - 8002e50: 687b ldr r3, [r7, #4] - 8002e52: 681b ldr r3, [r3, #0] - 8002e54: 2208 movs r2, #8 - 8002e56: 605a str r2, [r3, #4] + 8002e88: 687b ldr r3, [r7, #4] + 8002e8a: 681b ldr r3, [r3, #0] + 8002e8c: 2208 movs r2, #8 + 8002e8e: 605a str r2, [r3, #4] #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->WakeUpFromRxMsgCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_WakeUpFromRxMsgCallback(hcan); - 8002e58: 6878 ldr r0, [r7, #4] - 8002e5a: f000 f8f5 bl 8003048 + 8002e90: 6878 ldr r0, [r7, #4] + 8002e92: f000 f8f5 bl 8003080 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Error interrupts management *********************************************/ if ((interrupts & CAN_IT_ERROR) != 0U) - 8002e5e: 6a3b ldr r3, [r7, #32] - 8002e60: f403 4300 and.w r3, r3, #32768 @ 0x8000 - 8002e64: 2b00 cmp r3, #0 - 8002e66: d07b beq.n 8002f60 + 8002e96: 6a3b ldr r3, [r7, #32] + 8002e98: f403 4300 and.w r3, r3, #32768 @ 0x8000 + 8002e9c: 2b00 cmp r3, #0 + 8002e9e: d07b beq.n 8002f98 { if ((msrflags & CAN_MSR_ERRI) != 0U) - 8002e68: 69fb ldr r3, [r7, #28] - 8002e6a: f003 0304 and.w r3, r3, #4 - 8002e6e: 2b00 cmp r3, #0 - 8002e70: d072 beq.n 8002f58 + 8002ea0: 69fb ldr r3, [r7, #28] + 8002ea2: f003 0304 and.w r3, r3, #4 + 8002ea6: 2b00 cmp r3, #0 + 8002ea8: d072 beq.n 8002f90 { /* Check Error Warning Flag */ if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) && - 8002e72: 6a3b ldr r3, [r7, #32] - 8002e74: f403 7380 and.w r3, r3, #256 @ 0x100 - 8002e78: 2b00 cmp r3, #0 - 8002e7a: d008 beq.n 8002e8e + 8002eaa: 6a3b ldr r3, [r7, #32] + 8002eac: f403 7380 and.w r3, r3, #256 @ 0x100 + 8002eb0: 2b00 cmp r3, #0 + 8002eb2: d008 beq.n 8002ec6 ((esrflags & CAN_ESR_EWGF) != 0U)) - 8002e7c: 68fb ldr r3, [r7, #12] - 8002e7e: f003 0301 and.w r3, r3, #1 + 8002eb4: 68fb ldr r3, [r7, #12] + 8002eb6: f003 0301 and.w r3, r3, #1 if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) && - 8002e82: 2b00 cmp r3, #0 - 8002e84: d003 beq.n 8002e8e + 8002eba: 2b00 cmp r3, #0 + 8002ebc: d003 beq.n 8002ec6 { /* Set CAN error code to Error Warning */ errorcode |= HAL_CAN_ERROR_EWG; - 8002e86: 6a7b ldr r3, [r7, #36] @ 0x24 - 8002e88: f043 0301 orr.w r3, r3, #1 - 8002e8c: 627b str r3, [r7, #36] @ 0x24 + 8002ebe: 6a7b ldr r3, [r7, #36] @ 0x24 + 8002ec0: f043 0301 orr.w r3, r3, #1 + 8002ec4: 627b str r3, [r7, #36] @ 0x24 /* No need for clear of Error Warning Flag as read-only */ } /* Check Error Passive Flag */ if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) && - 8002e8e: 6a3b ldr r3, [r7, #32] - 8002e90: f403 7300 and.w r3, r3, #512 @ 0x200 - 8002e94: 2b00 cmp r3, #0 - 8002e96: d008 beq.n 8002eaa + 8002ec6: 6a3b ldr r3, [r7, #32] + 8002ec8: f403 7300 and.w r3, r3, #512 @ 0x200 + 8002ecc: 2b00 cmp r3, #0 + 8002ece: d008 beq.n 8002ee2 ((esrflags & CAN_ESR_EPVF) != 0U)) - 8002e98: 68fb ldr r3, [r7, #12] - 8002e9a: f003 0302 and.w r3, r3, #2 + 8002ed0: 68fb ldr r3, [r7, #12] + 8002ed2: f003 0302 and.w r3, r3, #2 if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) && - 8002e9e: 2b00 cmp r3, #0 - 8002ea0: d003 beq.n 8002eaa + 8002ed6: 2b00 cmp r3, #0 + 8002ed8: d003 beq.n 8002ee2 { /* Set CAN error code to Error Passive */ errorcode |= HAL_CAN_ERROR_EPV; - 8002ea2: 6a7b ldr r3, [r7, #36] @ 0x24 - 8002ea4: f043 0302 orr.w r3, r3, #2 - 8002ea8: 627b str r3, [r7, #36] @ 0x24 + 8002eda: 6a7b ldr r3, [r7, #36] @ 0x24 + 8002edc: f043 0302 orr.w r3, r3, #2 + 8002ee0: 627b str r3, [r7, #36] @ 0x24 /* No need for clear of Error Passive Flag as read-only */ } /* Check Bus-off Flag */ if (((interrupts & CAN_IT_BUSOFF) != 0U) && - 8002eaa: 6a3b ldr r3, [r7, #32] - 8002eac: f403 6380 and.w r3, r3, #1024 @ 0x400 - 8002eb0: 2b00 cmp r3, #0 - 8002eb2: d008 beq.n 8002ec6 + 8002ee2: 6a3b ldr r3, [r7, #32] + 8002ee4: f403 6380 and.w r3, r3, #1024 @ 0x400 + 8002ee8: 2b00 cmp r3, #0 + 8002eea: d008 beq.n 8002efe ((esrflags & CAN_ESR_BOFF) != 0U)) - 8002eb4: 68fb ldr r3, [r7, #12] - 8002eb6: f003 0304 and.w r3, r3, #4 + 8002eec: 68fb ldr r3, [r7, #12] + 8002eee: f003 0304 and.w r3, r3, #4 if (((interrupts & CAN_IT_BUSOFF) != 0U) && - 8002eba: 2b00 cmp r3, #0 - 8002ebc: d003 beq.n 8002ec6 + 8002ef2: 2b00 cmp r3, #0 + 8002ef4: d003 beq.n 8002efe { /* Set CAN error code to Bus-Off */ errorcode |= HAL_CAN_ERROR_BOF; - 8002ebe: 6a7b ldr r3, [r7, #36] @ 0x24 - 8002ec0: f043 0304 orr.w r3, r3, #4 - 8002ec4: 627b str r3, [r7, #36] @ 0x24 + 8002ef6: 6a7b ldr r3, [r7, #36] @ 0x24 + 8002ef8: f043 0304 orr.w r3, r3, #4 + 8002efc: 627b str r3, [r7, #36] @ 0x24 /* No need for clear of Error Bus-Off as read-only */ } /* Check Last Error Code Flag */ if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) && - 8002ec6: 6a3b ldr r3, [r7, #32] - 8002ec8: f403 6300 and.w r3, r3, #2048 @ 0x800 - 8002ecc: 2b00 cmp r3, #0 - 8002ece: d043 beq.n 8002f58 + 8002efe: 6a3b ldr r3, [r7, #32] + 8002f00: f403 6300 and.w r3, r3, #2048 @ 0x800 + 8002f04: 2b00 cmp r3, #0 + 8002f06: d043 beq.n 8002f90 ((esrflags & CAN_ESR_LEC) != 0U)) - 8002ed0: 68fb ldr r3, [r7, #12] - 8002ed2: f003 0370 and.w r3, r3, #112 @ 0x70 + 8002f08: 68fb ldr r3, [r7, #12] + 8002f0a: f003 0370 and.w r3, r3, #112 @ 0x70 if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) && - 8002ed6: 2b00 cmp r3, #0 - 8002ed8: d03e beq.n 8002f58 + 8002f0e: 2b00 cmp r3, #0 + 8002f10: d03e beq.n 8002f90 { switch (esrflags & CAN_ESR_LEC) - 8002eda: 68fb ldr r3, [r7, #12] - 8002edc: f003 0370 and.w r3, r3, #112 @ 0x70 - 8002ee0: 2b60 cmp r3, #96 @ 0x60 - 8002ee2: d02b beq.n 8002f3c - 8002ee4: 2b60 cmp r3, #96 @ 0x60 - 8002ee6: d82e bhi.n 8002f46 - 8002ee8: 2b50 cmp r3, #80 @ 0x50 - 8002eea: d022 beq.n 8002f32 - 8002eec: 2b50 cmp r3, #80 @ 0x50 - 8002eee: d82a bhi.n 8002f46 - 8002ef0: 2b40 cmp r3, #64 @ 0x40 - 8002ef2: d019 beq.n 8002f28 - 8002ef4: 2b40 cmp r3, #64 @ 0x40 - 8002ef6: d826 bhi.n 8002f46 - 8002ef8: 2b30 cmp r3, #48 @ 0x30 - 8002efa: d010 beq.n 8002f1e - 8002efc: 2b30 cmp r3, #48 @ 0x30 - 8002efe: d822 bhi.n 8002f46 - 8002f00: 2b10 cmp r3, #16 - 8002f02: d002 beq.n 8002f0a - 8002f04: 2b20 cmp r3, #32 - 8002f06: d005 beq.n 8002f14 + 8002f12: 68fb ldr r3, [r7, #12] + 8002f14: f003 0370 and.w r3, r3, #112 @ 0x70 + 8002f18: 2b60 cmp r3, #96 @ 0x60 + 8002f1a: d02b beq.n 8002f74 + 8002f1c: 2b60 cmp r3, #96 @ 0x60 + 8002f1e: d82e bhi.n 8002f7e + 8002f20: 2b50 cmp r3, #80 @ 0x50 + 8002f22: d022 beq.n 8002f6a + 8002f24: 2b50 cmp r3, #80 @ 0x50 + 8002f26: d82a bhi.n 8002f7e + 8002f28: 2b40 cmp r3, #64 @ 0x40 + 8002f2a: d019 beq.n 8002f60 + 8002f2c: 2b40 cmp r3, #64 @ 0x40 + 8002f2e: d826 bhi.n 8002f7e + 8002f30: 2b30 cmp r3, #48 @ 0x30 + 8002f32: d010 beq.n 8002f56 + 8002f34: 2b30 cmp r3, #48 @ 0x30 + 8002f36: d822 bhi.n 8002f7e + 8002f38: 2b10 cmp r3, #16 + 8002f3a: d002 beq.n 8002f42 + 8002f3c: 2b20 cmp r3, #32 + 8002f3e: d005 beq.n 8002f4c case (CAN_ESR_LEC_2 | CAN_ESR_LEC_1): /* Set CAN error code to CRC error */ errorcode |= HAL_CAN_ERROR_CRC; break; default: break; - 8002f08: e01d b.n 8002f46 + 8002f40: e01d b.n 8002f7e errorcode |= HAL_CAN_ERROR_STF; - 8002f0a: 6a7b ldr r3, [r7, #36] @ 0x24 - 8002f0c: f043 0308 orr.w r3, r3, #8 - 8002f10: 627b str r3, [r7, #36] @ 0x24 + 8002f42: 6a7b ldr r3, [r7, #36] @ 0x24 + 8002f44: f043 0308 orr.w r3, r3, #8 + 8002f48: 627b str r3, [r7, #36] @ 0x24 break; - 8002f12: e019 b.n 8002f48 + 8002f4a: e019 b.n 8002f80 errorcode |= HAL_CAN_ERROR_FOR; - 8002f14: 6a7b ldr r3, [r7, #36] @ 0x24 - 8002f16: f043 0310 orr.w r3, r3, #16 - 8002f1a: 627b str r3, [r7, #36] @ 0x24 + 8002f4c: 6a7b ldr r3, [r7, #36] @ 0x24 + 8002f4e: f043 0310 orr.w r3, r3, #16 + 8002f52: 627b str r3, [r7, #36] @ 0x24 break; - 8002f1c: e014 b.n 8002f48 + 8002f54: e014 b.n 8002f80 errorcode |= HAL_CAN_ERROR_ACK; - 8002f1e: 6a7b ldr r3, [r7, #36] @ 0x24 - 8002f20: f043 0320 orr.w r3, r3, #32 - 8002f24: 627b str r3, [r7, #36] @ 0x24 + 8002f56: 6a7b ldr r3, [r7, #36] @ 0x24 + 8002f58: f043 0320 orr.w r3, r3, #32 + 8002f5c: 627b str r3, [r7, #36] @ 0x24 break; - 8002f26: e00f b.n 8002f48 + 8002f5e: e00f b.n 8002f80 errorcode |= HAL_CAN_ERROR_BR; - 8002f28: 6a7b ldr r3, [r7, #36] @ 0x24 - 8002f2a: f043 0340 orr.w r3, r3, #64 @ 0x40 - 8002f2e: 627b str r3, [r7, #36] @ 0x24 + 8002f60: 6a7b ldr r3, [r7, #36] @ 0x24 + 8002f62: f043 0340 orr.w r3, r3, #64 @ 0x40 + 8002f66: 627b str r3, [r7, #36] @ 0x24 break; - 8002f30: e00a b.n 8002f48 + 8002f68: e00a b.n 8002f80 errorcode |= HAL_CAN_ERROR_BD; - 8002f32: 6a7b ldr r3, [r7, #36] @ 0x24 - 8002f34: f043 0380 orr.w r3, r3, #128 @ 0x80 - 8002f38: 627b str r3, [r7, #36] @ 0x24 + 8002f6a: 6a7b ldr r3, [r7, #36] @ 0x24 + 8002f6c: f043 0380 orr.w r3, r3, #128 @ 0x80 + 8002f70: 627b str r3, [r7, #36] @ 0x24 break; - 8002f3a: e005 b.n 8002f48 + 8002f72: e005 b.n 8002f80 errorcode |= HAL_CAN_ERROR_CRC; - 8002f3c: 6a7b ldr r3, [r7, #36] @ 0x24 - 8002f3e: f443 7380 orr.w r3, r3, #256 @ 0x100 - 8002f42: 627b str r3, [r7, #36] @ 0x24 + 8002f74: 6a7b ldr r3, [r7, #36] @ 0x24 + 8002f76: f443 7380 orr.w r3, r3, #256 @ 0x100 + 8002f7a: 627b str r3, [r7, #36] @ 0x24 break; - 8002f44: e000 b.n 8002f48 + 8002f7c: e000 b.n 8002f80 break; - 8002f46: bf00 nop + 8002f7e: bf00 nop } /* Clear Last error code Flag */ CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC); - 8002f48: 687b ldr r3, [r7, #4] - 8002f4a: 681b ldr r3, [r3, #0] - 8002f4c: 699a ldr r2, [r3, #24] - 8002f4e: 687b ldr r3, [r7, #4] - 8002f50: 681b ldr r3, [r3, #0] - 8002f52: f022 0270 bic.w r2, r2, #112 @ 0x70 - 8002f56: 619a str r2, [r3, #24] + 8002f80: 687b ldr r3, [r7, #4] + 8002f82: 681b ldr r3, [r3, #0] + 8002f84: 699a ldr r2, [r3, #24] + 8002f86: 687b ldr r3, [r7, #4] + 8002f88: 681b ldr r3, [r3, #0] + 8002f8a: f022 0270 bic.w r2, r2, #112 @ 0x70 + 8002f8e: 619a str r2, [r3, #24] } } /* Clear ERRI Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_ERRI); - 8002f58: 687b ldr r3, [r7, #4] - 8002f5a: 681b ldr r3, [r3, #0] - 8002f5c: 2204 movs r2, #4 - 8002f5e: 605a str r2, [r3, #4] + 8002f90: 687b ldr r3, [r7, #4] + 8002f92: 681b ldr r3, [r3, #0] + 8002f94: 2204 movs r2, #4 + 8002f96: 605a str r2, [r3, #4] } /* Call the Error call Back in case of Errors */ if (errorcode != HAL_CAN_ERROR_NONE) - 8002f60: 6a7b ldr r3, [r7, #36] @ 0x24 - 8002f62: 2b00 cmp r3, #0 - 8002f64: d008 beq.n 8002f78 + 8002f98: 6a7b ldr r3, [r7, #36] @ 0x24 + 8002f9a: 2b00 cmp r3, #0 + 8002f9c: d008 beq.n 8002fb0 { /* Update error code in handle */ hcan->ErrorCode |= errorcode; - 8002f66: 687b ldr r3, [r7, #4] - 8002f68: 6a5a ldr r2, [r3, #36] @ 0x24 - 8002f6a: 6a7b ldr r3, [r7, #36] @ 0x24 - 8002f6c: 431a orrs r2, r3 - 8002f6e: 687b ldr r3, [r7, #4] - 8002f70: 625a str r2, [r3, #36] @ 0x24 + 8002f9e: 687b ldr r3, [r7, #4] + 8002fa0: 6a5a ldr r2, [r3, #36] @ 0x24 + 8002fa2: 6a7b ldr r3, [r7, #36] @ 0x24 + 8002fa4: 431a orrs r2, r3 + 8002fa6: 687b ldr r3, [r7, #4] + 8002fa8: 625a str r2, [r3, #36] @ 0x24 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->ErrorCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_ErrorCallback(hcan); - 8002f72: 6878 ldr r0, [r7, #4] - 8002f74: f000 f872 bl 800305c + 8002faa: 6878 ldr r0, [r7, #4] + 8002fac: f000 f872 bl 8003094 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } - 8002f78: bf00 nop - 8002f7a: 3728 adds r7, #40 @ 0x28 - 8002f7c: 46bd mov sp, r7 - 8002f7e: bd80 pop {r7, pc} + 8002fb0: bf00 nop + 8002fb2: 3728 adds r7, #40 @ 0x28 + 8002fb4: 46bd mov sp, r7 + 8002fb6: bd80 pop {r7, pc} -08002f80 : +08002fb8 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan) { - 8002f80: b480 push {r7} - 8002f82: b083 sub sp, #12 - 8002f84: af00 add r7, sp, #0 - 8002f86: 6078 str r0, [r7, #4] + 8002fb8: b480 push {r7} + 8002fba: b083 sub sp, #12 + 8002fbc: af00 add r7, sp, #0 + 8002fbe: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox0CompleteCallback could be implemented in the user file */ } - 8002f88: bf00 nop - 8002f8a: 370c adds r7, #12 - 8002f8c: 46bd mov sp, r7 - 8002f8e: f85d 7b04 ldr.w r7, [sp], #4 - 8002f92: 4770 bx lr + 8002fc0: bf00 nop + 8002fc2: 370c adds r7, #12 + 8002fc4: 46bd mov sp, r7 + 8002fc6: f85d 7b04 ldr.w r7, [sp], #4 + 8002fca: 4770 bx lr -08002f94 : +08002fcc : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan) { - 8002f94: b480 push {r7} - 8002f96: b083 sub sp, #12 - 8002f98: af00 add r7, sp, #0 - 8002f9a: 6078 str r0, [r7, #4] + 8002fcc: b480 push {r7} + 8002fce: b083 sub sp, #12 + 8002fd0: af00 add r7, sp, #0 + 8002fd2: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox1CompleteCallback could be implemented in the user file */ } - 8002f9c: bf00 nop - 8002f9e: 370c adds r7, #12 - 8002fa0: 46bd mov sp, r7 - 8002fa2: f85d 7b04 ldr.w r7, [sp], #4 - 8002fa6: 4770 bx lr + 8002fd4: bf00 nop + 8002fd6: 370c adds r7, #12 + 8002fd8: 46bd mov sp, r7 + 8002fda: f85d 7b04 ldr.w r7, [sp], #4 + 8002fde: 4770 bx lr -08002fa8 : +08002fe0 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan) { - 8002fa8: b480 push {r7} - 8002faa: b083 sub sp, #12 - 8002fac: af00 add r7, sp, #0 - 8002fae: 6078 str r0, [r7, #4] + 8002fe0: b480 push {r7} + 8002fe2: b083 sub sp, #12 + 8002fe4: af00 add r7, sp, #0 + 8002fe6: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox2CompleteCallback could be implemented in the user file */ } - 8002fb0: bf00 nop - 8002fb2: 370c adds r7, #12 - 8002fb4: 46bd mov sp, r7 - 8002fb6: f85d 7b04 ldr.w r7, [sp], #4 - 8002fba: 4770 bx lr + 8002fe8: bf00 nop + 8002fea: 370c adds r7, #12 + 8002fec: 46bd mov sp, r7 + 8002fee: f85d 7b04 ldr.w r7, [sp], #4 + 8002ff2: 4770 bx lr -08002fbc : +08002ff4 : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan) { - 8002fbc: b480 push {r7} - 8002fbe: b083 sub sp, #12 - 8002fc0: af00 add r7, sp, #0 - 8002fc2: 6078 str r0, [r7, #4] + 8002ff4: b480 push {r7} + 8002ff6: b083 sub sp, #12 + 8002ff8: af00 add r7, sp, #0 + 8002ffa: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox0AbortCallback could be implemented in the user file */ } - 8002fc4: bf00 nop - 8002fc6: 370c adds r7, #12 - 8002fc8: 46bd mov sp, r7 - 8002fca: f85d 7b04 ldr.w r7, [sp], #4 - 8002fce: 4770 bx lr + 8002ffc: bf00 nop + 8002ffe: 370c adds r7, #12 + 8003000: 46bd mov sp, r7 + 8003002: f85d 7b04 ldr.w r7, [sp], #4 + 8003006: 4770 bx lr -08002fd0 : +08003008 : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan) { - 8002fd0: b480 push {r7} - 8002fd2: b083 sub sp, #12 - 8002fd4: af00 add r7, sp, #0 - 8002fd6: 6078 str r0, [r7, #4] + 8003008: b480 push {r7} + 800300a: b083 sub sp, #12 + 800300c: af00 add r7, sp, #0 + 800300e: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox1AbortCallback could be implemented in the user file */ } - 8002fd8: bf00 nop - 8002fda: 370c adds r7, #12 - 8002fdc: 46bd mov sp, r7 - 8002fde: f85d 7b04 ldr.w r7, [sp], #4 - 8002fe2: 4770 bx lr + 8003010: bf00 nop + 8003012: 370c adds r7, #12 + 8003014: 46bd mov sp, r7 + 8003016: f85d 7b04 ldr.w r7, [sp], #4 + 800301a: 4770 bx lr -08002fe4 : +0800301c : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan) { - 8002fe4: b480 push {r7} - 8002fe6: b083 sub sp, #12 - 8002fe8: af00 add r7, sp, #0 - 8002fea: 6078 str r0, [r7, #4] + 800301c: b480 push {r7} + 800301e: b083 sub sp, #12 + 8003020: af00 add r7, sp, #0 + 8003022: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox2AbortCallback could be implemented in the user file */ } - 8002fec: bf00 nop - 8002fee: 370c adds r7, #12 - 8002ff0: 46bd mov sp, r7 - 8002ff2: f85d 7b04 ldr.w r7, [sp], #4 - 8002ff6: 4770 bx lr + 8003024: bf00 nop + 8003026: 370c adds r7, #12 + 8003028: 46bd mov sp, r7 + 800302a: f85d 7b04 ldr.w r7, [sp], #4 + 800302e: 4770 bx lr -08002ff8 : +08003030 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan) { - 8002ff8: b480 push {r7} - 8002ffa: b083 sub sp, #12 - 8002ffc: af00 add r7, sp, #0 - 8002ffe: 6078 str r0, [r7, #4] + 8003030: b480 push {r7} + 8003032: b083 sub sp, #12 + 8003034: af00 add r7, sp, #0 + 8003036: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_RxFifo0FullCallback could be implemented in the user file */ } - 8003000: bf00 nop - 8003002: 370c adds r7, #12 - 8003004: 46bd mov sp, r7 - 8003006: f85d 7b04 ldr.w r7, [sp], #4 - 800300a: 4770 bx lr + 8003038: bf00 nop + 800303a: 370c adds r7, #12 + 800303c: 46bd mov sp, r7 + 800303e: f85d 7b04 ldr.w r7, [sp], #4 + 8003042: 4770 bx lr -0800300c : +08003044 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan) { - 800300c: b480 push {r7} - 800300e: b083 sub sp, #12 - 8003010: af00 add r7, sp, #0 - 8003012: 6078 str r0, [r7, #4] + 8003044: b480 push {r7} + 8003046: b083 sub sp, #12 + 8003048: af00 add r7, sp, #0 + 800304a: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_RxFifo1MsgPendingCallback could be implemented in the user file */ } - 8003014: bf00 nop - 8003016: 370c adds r7, #12 - 8003018: 46bd mov sp, r7 - 800301a: f85d 7b04 ldr.w r7, [sp], #4 - 800301e: 4770 bx lr + 800304c: bf00 nop + 800304e: 370c adds r7, #12 + 8003050: 46bd mov sp, r7 + 8003052: f85d 7b04 ldr.w r7, [sp], #4 + 8003056: 4770 bx lr -08003020 : +08003058 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan) { - 8003020: b480 push {r7} - 8003022: b083 sub sp, #12 - 8003024: af00 add r7, sp, #0 - 8003026: 6078 str r0, [r7, #4] + 8003058: b480 push {r7} + 800305a: b083 sub sp, #12 + 800305c: af00 add r7, sp, #0 + 800305e: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_RxFifo1FullCallback could be implemented in the user file */ } - 8003028: bf00 nop - 800302a: 370c adds r7, #12 - 800302c: 46bd mov sp, r7 - 800302e: f85d 7b04 ldr.w r7, [sp], #4 - 8003032: 4770 bx lr + 8003060: bf00 nop + 8003062: 370c adds r7, #12 + 8003064: 46bd mov sp, r7 + 8003066: f85d 7b04 ldr.w r7, [sp], #4 + 800306a: 4770 bx lr -08003034 : +0800306c : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan) { - 8003034: b480 push {r7} - 8003036: b083 sub sp, #12 - 8003038: af00 add r7, sp, #0 - 800303a: 6078 str r0, [r7, #4] + 800306c: b480 push {r7} + 800306e: b083 sub sp, #12 + 8003070: af00 add r7, sp, #0 + 8003072: 6078 str r0, [r7, #4] UNUSED(hcan); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_SleepCallback could be implemented in the user file */ } - 800303c: bf00 nop - 800303e: 370c adds r7, #12 - 8003040: 46bd mov sp, r7 - 8003042: f85d 7b04 ldr.w r7, [sp], #4 - 8003046: 4770 bx lr + 8003074: bf00 nop + 8003076: 370c adds r7, #12 + 8003078: 46bd mov sp, r7 + 800307a: f85d 7b04 ldr.w r7, [sp], #4 + 800307e: 4770 bx lr -08003048 : +08003080 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan) { - 8003048: b480 push {r7} - 800304a: b083 sub sp, #12 - 800304c: af00 add r7, sp, #0 - 800304e: 6078 str r0, [r7, #4] + 8003080: b480 push {r7} + 8003082: b083 sub sp, #12 + 8003084: af00 add r7, sp, #0 + 8003086: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_WakeUpFromRxMsgCallback could be implemented in the user file */ } - 8003050: bf00 nop - 8003052: 370c adds r7, #12 - 8003054: 46bd mov sp, r7 - 8003056: f85d 7b04 ldr.w r7, [sp], #4 - 800305a: 4770 bx lr + 8003088: bf00 nop + 800308a: 370c adds r7, #12 + 800308c: 46bd mov sp, r7 + 800308e: f85d 7b04 ldr.w r7, [sp], #4 + 8003092: 4770 bx lr -0800305c : +08003094 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) { - 800305c: b480 push {r7} - 800305e: b083 sub sp, #12 - 8003060: af00 add r7, sp, #0 - 8003062: 6078 str r0, [r7, #4] + 8003094: b480 push {r7} + 8003096: b083 sub sp, #12 + 8003098: af00 add r7, sp, #0 + 800309a: 6078 str r0, [r7, #4] UNUSED(hcan); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_ErrorCallback could be implemented in the user file */ } - 8003064: bf00 nop - 8003066: 370c adds r7, #12 - 8003068: 46bd mov sp, r7 - 800306a: f85d 7b04 ldr.w r7, [sp], #4 - 800306e: 4770 bx lr + 800309c: bf00 nop + 800309e: 370c adds r7, #12 + 80030a0: 46bd mov sp, r7 + 80030a2: f85d 7b04 ldr.w r7, [sp], #4 + 80030a6: 4770 bx lr -08003070 <__NVIC_SetPriorityGrouping>: +080030a8 <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { - 8003070: b480 push {r7} - 8003072: b085 sub sp, #20 - 8003074: af00 add r7, sp, #0 - 8003076: 6078 str r0, [r7, #4] + 80030a8: b480 push {r7} + 80030aa: b085 sub sp, #20 + 80030ac: af00 add r7, sp, #0 + 80030ae: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - 8003078: 687b ldr r3, [r7, #4] - 800307a: f003 0307 and.w r3, r3, #7 - 800307e: 60fb str r3, [r7, #12] + 80030b0: 687b ldr r3, [r7, #4] + 80030b2: f003 0307 and.w r3, r3, #7 + 80030b6: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ - 8003080: 4b0c ldr r3, [pc, #48] @ (80030b4 <__NVIC_SetPriorityGrouping+0x44>) - 8003082: 68db ldr r3, [r3, #12] - 8003084: 60bb str r3, [r7, #8] + 80030b8: 4b0c ldr r3, [pc, #48] @ (80030ec <__NVIC_SetPriorityGrouping+0x44>) + 80030ba: 68db ldr r3, [r3, #12] + 80030bc: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - 8003086: 68ba ldr r2, [r7, #8] - 8003088: f64f 03ff movw r3, #63743 @ 0xf8ff - 800308c: 4013 ands r3, r2 - 800308e: 60bb str r3, [r7, #8] + 80030be: 68ba ldr r2, [r7, #8] + 80030c0: f64f 03ff movw r3, #63743 @ 0xf8ff + 80030c4: 4013 ands r3, r2 + 80030c6: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - 8003090: 68fb ldr r3, [r7, #12] - 8003092: 021a lsls r2, r3, #8 + 80030c8: 68fb ldr r3, [r7, #12] + 80030ca: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - 8003094: 68bb ldr r3, [r7, #8] - 8003096: 4313 orrs r3, r2 + 80030cc: 68bb ldr r3, [r7, #8] + 80030ce: 4313 orrs r3, r2 reg_value = (reg_value | - 8003098: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 - 800309c: f443 3300 orr.w r3, r3, #131072 @ 0x20000 - 80030a0: 60bb str r3, [r7, #8] + 80030d0: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 + 80030d4: f443 3300 orr.w r3, r3, #131072 @ 0x20000 + 80030d8: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; - 80030a2: 4a04 ldr r2, [pc, #16] @ (80030b4 <__NVIC_SetPriorityGrouping+0x44>) - 80030a4: 68bb ldr r3, [r7, #8] - 80030a6: 60d3 str r3, [r2, #12] + 80030da: 4a04 ldr r2, [pc, #16] @ (80030ec <__NVIC_SetPriorityGrouping+0x44>) + 80030dc: 68bb ldr r3, [r7, #8] + 80030de: 60d3 str r3, [r2, #12] } - 80030a8: bf00 nop - 80030aa: 3714 adds r7, #20 - 80030ac: 46bd mov sp, r7 - 80030ae: f85d 7b04 ldr.w r7, [sp], #4 - 80030b2: 4770 bx lr - 80030b4: e000ed00 .word 0xe000ed00 + 80030e0: bf00 nop + 80030e2: 3714 adds r7, #20 + 80030e4: 46bd mov sp, r7 + 80030e6: f85d 7b04 ldr.w r7, [sp], #4 + 80030ea: 4770 bx lr + 80030ec: e000ed00 .word 0xe000ed00 -080030b8 <__NVIC_GetPriorityGrouping>: +080030f0 <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { - 80030b8: b480 push {r7} - 80030ba: af00 add r7, sp, #0 + 80030f0: b480 push {r7} + 80030f2: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); - 80030bc: 4b04 ldr r3, [pc, #16] @ (80030d0 <__NVIC_GetPriorityGrouping+0x18>) - 80030be: 68db ldr r3, [r3, #12] - 80030c0: 0a1b lsrs r3, r3, #8 - 80030c2: f003 0307 and.w r3, r3, #7 + 80030f4: 4b04 ldr r3, [pc, #16] @ (8003108 <__NVIC_GetPriorityGrouping+0x18>) + 80030f6: 68db ldr r3, [r3, #12] + 80030f8: 0a1b lsrs r3, r3, #8 + 80030fa: f003 0307 and.w r3, r3, #7 } - 80030c6: 4618 mov r0, r3 - 80030c8: 46bd mov sp, r7 - 80030ca: f85d 7b04 ldr.w r7, [sp], #4 - 80030ce: 4770 bx lr - 80030d0: e000ed00 .word 0xe000ed00 + 80030fe: 4618 mov r0, r3 + 8003100: 46bd mov sp, r7 + 8003102: f85d 7b04 ldr.w r7, [sp], #4 + 8003106: 4770 bx lr + 8003108: e000ed00 .word 0xe000ed00 -080030d4 <__NVIC_EnableIRQ>: +0800310c <__NVIC_EnableIRQ>: \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { - 80030d4: b480 push {r7} - 80030d6: b083 sub sp, #12 - 80030d8: af00 add r7, sp, #0 - 80030da: 4603 mov r3, r0 - 80030dc: 71fb strb r3, [r7, #7] + 800310c: b480 push {r7} + 800310e: b083 sub sp, #12 + 8003110: af00 add r7, sp, #0 + 8003112: 4603 mov r3, r0 + 8003114: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) - 80030de: f997 3007 ldrsb.w r3, [r7, #7] - 80030e2: 2b00 cmp r3, #0 - 80030e4: db0b blt.n 80030fe <__NVIC_EnableIRQ+0x2a> + 8003116: f997 3007 ldrsb.w r3, [r7, #7] + 800311a: 2b00 cmp r3, #0 + 800311c: db0b blt.n 8003136 <__NVIC_EnableIRQ+0x2a> { NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - 80030e6: 79fb ldrb r3, [r7, #7] - 80030e8: f003 021f and.w r2, r3, #31 - 80030ec: 4907 ldr r1, [pc, #28] @ (800310c <__NVIC_EnableIRQ+0x38>) - 80030ee: f997 3007 ldrsb.w r3, [r7, #7] - 80030f2: 095b lsrs r3, r3, #5 - 80030f4: 2001 movs r0, #1 - 80030f6: fa00 f202 lsl.w r2, r0, r2 - 80030fa: f841 2023 str.w r2, [r1, r3, lsl #2] + 800311e: 79fb ldrb r3, [r7, #7] + 8003120: f003 021f and.w r2, r3, #31 + 8003124: 4907 ldr r1, [pc, #28] @ (8003144 <__NVIC_EnableIRQ+0x38>) + 8003126: f997 3007 ldrsb.w r3, [r7, #7] + 800312a: 095b lsrs r3, r3, #5 + 800312c: 2001 movs r0, #1 + 800312e: fa00 f202 lsl.w r2, r0, r2 + 8003132: f841 2023 str.w r2, [r1, r3, lsl #2] } } - 80030fe: bf00 nop - 8003100: 370c adds r7, #12 - 8003102: 46bd mov sp, r7 - 8003104: f85d 7b04 ldr.w r7, [sp], #4 - 8003108: 4770 bx lr - 800310a: bf00 nop - 800310c: e000e100 .word 0xe000e100 + 8003136: bf00 nop + 8003138: 370c adds r7, #12 + 800313a: 46bd mov sp, r7 + 800313c: f85d 7b04 ldr.w r7, [sp], #4 + 8003140: 4770 bx lr + 8003142: bf00 nop + 8003144: e000e100 .word 0xe000e100 -08003110 <__NVIC_SetPriority>: +08003148 <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { - 8003110: b480 push {r7} - 8003112: b083 sub sp, #12 - 8003114: af00 add r7, sp, #0 - 8003116: 4603 mov r3, r0 - 8003118: 6039 str r1, [r7, #0] - 800311a: 71fb strb r3, [r7, #7] + 8003148: b480 push {r7} + 800314a: b083 sub sp, #12 + 800314c: af00 add r7, sp, #0 + 800314e: 4603 mov r3, r0 + 8003150: 6039 str r1, [r7, #0] + 8003152: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) - 800311c: f997 3007 ldrsb.w r3, [r7, #7] - 8003120: 2b00 cmp r3, #0 - 8003122: db0a blt.n 800313a <__NVIC_SetPriority+0x2a> + 8003154: f997 3007 ldrsb.w r3, [r7, #7] + 8003158: 2b00 cmp r3, #0 + 800315a: db0a blt.n 8003172 <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - 8003124: 683b ldr r3, [r7, #0] - 8003126: b2da uxtb r2, r3 - 8003128: 490c ldr r1, [pc, #48] @ (800315c <__NVIC_SetPriority+0x4c>) - 800312a: f997 3007 ldrsb.w r3, [r7, #7] - 800312e: 0112 lsls r2, r2, #4 - 8003130: b2d2 uxtb r2, r2 - 8003132: 440b add r3, r1 - 8003134: f883 2300 strb.w r2, [r3, #768] @ 0x300 + 800315c: 683b ldr r3, [r7, #0] + 800315e: b2da uxtb r2, r3 + 8003160: 490c ldr r1, [pc, #48] @ (8003194 <__NVIC_SetPriority+0x4c>) + 8003162: f997 3007 ldrsb.w r3, [r7, #7] + 8003166: 0112 lsls r2, r2, #4 + 8003168: b2d2 uxtb r2, r2 + 800316a: 440b add r3, r1 + 800316c: f883 2300 strb.w r2, [r3, #768] @ 0x300 } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } - 8003138: e00a b.n 8003150 <__NVIC_SetPriority+0x40> + 8003170: e00a b.n 8003188 <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - 800313a: 683b ldr r3, [r7, #0] - 800313c: b2da uxtb r2, r3 - 800313e: 4908 ldr r1, [pc, #32] @ (8003160 <__NVIC_SetPriority+0x50>) - 8003140: 79fb ldrb r3, [r7, #7] - 8003142: f003 030f and.w r3, r3, #15 - 8003146: 3b04 subs r3, #4 - 8003148: 0112 lsls r2, r2, #4 - 800314a: b2d2 uxtb r2, r2 - 800314c: 440b add r3, r1 - 800314e: 761a strb r2, [r3, #24] + 8003172: 683b ldr r3, [r7, #0] + 8003174: b2da uxtb r2, r3 + 8003176: 4908 ldr r1, [pc, #32] @ (8003198 <__NVIC_SetPriority+0x50>) + 8003178: 79fb ldrb r3, [r7, #7] + 800317a: f003 030f and.w r3, r3, #15 + 800317e: 3b04 subs r3, #4 + 8003180: 0112 lsls r2, r2, #4 + 8003182: b2d2 uxtb r2, r2 + 8003184: 440b add r3, r1 + 8003186: 761a strb r2, [r3, #24] } - 8003150: bf00 nop - 8003152: 370c adds r7, #12 - 8003154: 46bd mov sp, r7 - 8003156: f85d 7b04 ldr.w r7, [sp], #4 - 800315a: 4770 bx lr - 800315c: e000e100 .word 0xe000e100 - 8003160: e000ed00 .word 0xe000ed00 + 8003188: bf00 nop + 800318a: 370c adds r7, #12 + 800318c: 46bd mov sp, r7 + 800318e: f85d 7b04 ldr.w r7, [sp], #4 + 8003192: 4770 bx lr + 8003194: e000e100 .word 0xe000e100 + 8003198: e000ed00 .word 0xe000ed00 -08003164 : +0800319c : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { - 8003164: b480 push {r7} - 8003166: b089 sub sp, #36 @ 0x24 - 8003168: af00 add r7, sp, #0 - 800316a: 60f8 str r0, [r7, #12] - 800316c: 60b9 str r1, [r7, #8] - 800316e: 607a str r2, [r7, #4] + 800319c: b480 push {r7} + 800319e: b089 sub sp, #36 @ 0x24 + 80031a0: af00 add r7, sp, #0 + 80031a2: 60f8 str r0, [r7, #12] + 80031a4: 60b9 str r1, [r7, #8] + 80031a6: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - 8003170: 68fb ldr r3, [r7, #12] - 8003172: f003 0307 and.w r3, r3, #7 - 8003176: 61fb str r3, [r7, #28] + 80031a8: 68fb ldr r3, [r7, #12] + 80031aa: f003 0307 and.w r3, r3, #7 + 80031ae: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - 8003178: 69fb ldr r3, [r7, #28] - 800317a: f1c3 0307 rsb r3, r3, #7 - 800317e: 2b04 cmp r3, #4 - 8003180: bf28 it cs - 8003182: 2304 movcs r3, #4 - 8003184: 61bb str r3, [r7, #24] + 80031b0: 69fb ldr r3, [r7, #28] + 80031b2: f1c3 0307 rsb r3, r3, #7 + 80031b6: 2b04 cmp r3, #4 + 80031b8: bf28 it cs + 80031ba: 2304 movcs r3, #4 + 80031bc: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - 8003186: 69fb ldr r3, [r7, #28] - 8003188: 3304 adds r3, #4 - 800318a: 2b06 cmp r3, #6 - 800318c: d902 bls.n 8003194 - 800318e: 69fb ldr r3, [r7, #28] - 8003190: 3b03 subs r3, #3 - 8003192: e000 b.n 8003196 - 8003194: 2300 movs r3, #0 - 8003196: 617b str r3, [r7, #20] + 80031be: 69fb ldr r3, [r7, #28] + 80031c0: 3304 adds r3, #4 + 80031c2: 2b06 cmp r3, #6 + 80031c4: d902 bls.n 80031cc + 80031c6: 69fb ldr r3, [r7, #28] + 80031c8: 3b03 subs r3, #3 + 80031ca: e000 b.n 80031ce + 80031cc: 2300 movs r3, #0 + 80031ce: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - 8003198: f04f 32ff mov.w r2, #4294967295 - 800319c: 69bb ldr r3, [r7, #24] - 800319e: fa02 f303 lsl.w r3, r2, r3 - 80031a2: 43da mvns r2, r3 - 80031a4: 68bb ldr r3, [r7, #8] - 80031a6: 401a ands r2, r3 - 80031a8: 697b ldr r3, [r7, #20] - 80031aa: 409a lsls r2, r3 + 80031d0: f04f 32ff mov.w r2, #4294967295 + 80031d4: 69bb ldr r3, [r7, #24] + 80031d6: fa02 f303 lsl.w r3, r2, r3 + 80031da: 43da mvns r2, r3 + 80031dc: 68bb ldr r3, [r7, #8] + 80031de: 401a ands r2, r3 + 80031e0: 697b ldr r3, [r7, #20] + 80031e2: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - 80031ac: f04f 31ff mov.w r1, #4294967295 - 80031b0: 697b ldr r3, [r7, #20] - 80031b2: fa01 f303 lsl.w r3, r1, r3 - 80031b6: 43d9 mvns r1, r3 - 80031b8: 687b ldr r3, [r7, #4] - 80031ba: 400b ands r3, r1 + 80031e4: f04f 31ff mov.w r1, #4294967295 + 80031e8: 697b ldr r3, [r7, #20] + 80031ea: fa01 f303 lsl.w r3, r1, r3 + 80031ee: 43d9 mvns r1, r3 + 80031f0: 687b ldr r3, [r7, #4] + 80031f2: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - 80031bc: 4313 orrs r3, r2 + 80031f4: 4313 orrs r3, r2 ); } - 80031be: 4618 mov r0, r3 - 80031c0: 3724 adds r7, #36 @ 0x24 - 80031c2: 46bd mov sp, r7 - 80031c4: f85d 7b04 ldr.w r7, [sp], #4 - 80031c8: 4770 bx lr + 80031f6: 4618 mov r0, r3 + 80031f8: 3724 adds r7, #36 @ 0x24 + 80031fa: 46bd mov sp, r7 + 80031fc: f85d 7b04 ldr.w r7, [sp], #4 + 8003200: 4770 bx lr ... -080031cc : +08003204 : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { - 80031cc: b580 push {r7, lr} - 80031ce: b082 sub sp, #8 - 80031d0: af00 add r7, sp, #0 - 80031d2: 6078 str r0, [r7, #4] + 8003204: b580 push {r7, lr} + 8003206: b082 sub sp, #8 + 8003208: af00 add r7, sp, #0 + 800320a: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - 80031d4: 687b ldr r3, [r7, #4] - 80031d6: 3b01 subs r3, #1 - 80031d8: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 - 80031dc: d301 bcc.n 80031e2 + 800320c: 687b ldr r3, [r7, #4] + 800320e: 3b01 subs r3, #1 + 8003210: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 + 8003214: d301 bcc.n 800321a { return (1UL); /* Reload value impossible */ - 80031de: 2301 movs r3, #1 - 80031e0: e00f b.n 8003202 + 8003216: 2301 movs r3, #1 + 8003218: e00f b.n 800323a } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - 80031e2: 4a0a ldr r2, [pc, #40] @ (800320c ) - 80031e4: 687b ldr r3, [r7, #4] - 80031e6: 3b01 subs r3, #1 - 80031e8: 6053 str r3, [r2, #4] + 800321a: 4a0a ldr r2, [pc, #40] @ (8003244 ) + 800321c: 687b ldr r3, [r7, #4] + 800321e: 3b01 subs r3, #1 + 8003220: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - 80031ea: 210f movs r1, #15 - 80031ec: f04f 30ff mov.w r0, #4294967295 - 80031f0: f7ff ff8e bl 8003110 <__NVIC_SetPriority> + 8003222: 210f movs r1, #15 + 8003224: f04f 30ff mov.w r0, #4294967295 + 8003228: f7ff ff8e bl 8003148 <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - 80031f4: 4b05 ldr r3, [pc, #20] @ (800320c ) - 80031f6: 2200 movs r2, #0 - 80031f8: 609a str r2, [r3, #8] + 800322c: 4b05 ldr r3, [pc, #20] @ (8003244 ) + 800322e: 2200 movs r2, #0 + 8003230: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - 80031fa: 4b04 ldr r3, [pc, #16] @ (800320c ) - 80031fc: 2207 movs r2, #7 - 80031fe: 601a str r2, [r3, #0] + 8003232: 4b04 ldr r3, [pc, #16] @ (8003244 ) + 8003234: 2207 movs r2, #7 + 8003236: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ - 8003200: 2300 movs r3, #0 + 8003238: 2300 movs r3, #0 } - 8003202: 4618 mov r0, r3 - 8003204: 3708 adds r7, #8 - 8003206: 46bd mov sp, r7 - 8003208: bd80 pop {r7, pc} - 800320a: bf00 nop - 800320c: e000e010 .word 0xe000e010 + 800323a: 4618 mov r0, r3 + 800323c: 3708 adds r7, #8 + 800323e: 46bd mov sp, r7 + 8003240: bd80 pop {r7, pc} + 8003242: bf00 nop + 8003244: e000e010 .word 0xe000e010 -08003210 : +08003248 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { - 8003210: b580 push {r7, lr} - 8003212: b082 sub sp, #8 - 8003214: af00 add r7, sp, #0 - 8003216: 6078 str r0, [r7, #4] + 8003248: b580 push {r7, lr} + 800324a: b082 sub sp, #8 + 800324c: af00 add r7, sp, #0 + 800324e: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); - 8003218: 6878 ldr r0, [r7, #4] - 800321a: f7ff ff29 bl 8003070 <__NVIC_SetPriorityGrouping> + 8003250: 6878 ldr r0, [r7, #4] + 8003252: f7ff ff29 bl 80030a8 <__NVIC_SetPriorityGrouping> } - 800321e: bf00 nop - 8003220: 3708 adds r7, #8 - 8003222: 46bd mov sp, r7 - 8003224: bd80 pop {r7, pc} + 8003256: bf00 nop + 8003258: 3708 adds r7, #8 + 800325a: 46bd mov sp, r7 + 800325c: bd80 pop {r7, pc} -08003226 : +0800325e : * This parameter can be a value between 0 and 15 as described in the table CORTEX_NVIC_Priority_Table * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { - 8003226: b580 push {r7, lr} - 8003228: b086 sub sp, #24 - 800322a: af00 add r7, sp, #0 - 800322c: 4603 mov r3, r0 - 800322e: 60b9 str r1, [r7, #8] - 8003230: 607a str r2, [r7, #4] - 8003232: 73fb strb r3, [r7, #15] + 800325e: b580 push {r7, lr} + 8003260: b086 sub sp, #24 + 8003262: af00 add r7, sp, #0 + 8003264: 4603 mov r3, r0 + 8003266: 60b9 str r1, [r7, #8] + 8003268: 607a str r2, [r7, #4] + 800326a: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00U; - 8003234: 2300 movs r3, #0 - 8003236: 617b str r3, [r7, #20] + 800326c: 2300 movs r3, #0 + 800326e: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); - 8003238: f7ff ff3e bl 80030b8 <__NVIC_GetPriorityGrouping> - 800323c: 6178 str r0, [r7, #20] + 8003270: f7ff ff3e bl 80030f0 <__NVIC_GetPriorityGrouping> + 8003274: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); - 800323e: 687a ldr r2, [r7, #4] - 8003240: 68b9 ldr r1, [r7, #8] - 8003242: 6978 ldr r0, [r7, #20] - 8003244: f7ff ff8e bl 8003164 - 8003248: 4602 mov r2, r0 - 800324a: f997 300f ldrsb.w r3, [r7, #15] - 800324e: 4611 mov r1, r2 - 8003250: 4618 mov r0, r3 - 8003252: f7ff ff5d bl 8003110 <__NVIC_SetPriority> + 8003276: 687a ldr r2, [r7, #4] + 8003278: 68b9 ldr r1, [r7, #8] + 800327a: 6978 ldr r0, [r7, #20] + 800327c: f7ff ff8e bl 800319c + 8003280: 4602 mov r2, r0 + 8003282: f997 300f ldrsb.w r3, [r7, #15] + 8003286: 4611 mov r1, r2 + 8003288: 4618 mov r0, r3 + 800328a: f7ff ff5d bl 8003148 <__NVIC_SetPriority> } - 8003256: bf00 nop - 8003258: 3718 adds r7, #24 - 800325a: 46bd mov sp, r7 - 800325c: bd80 pop {r7, pc} + 800328e: bf00 nop + 8003290: 3718 adds r7, #24 + 8003292: 46bd mov sp, r7 + 8003294: bd80 pop {r7, pc} -0800325e : +08003296 : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { - 800325e: b580 push {r7, lr} - 8003260: b082 sub sp, #8 - 8003262: af00 add r7, sp, #0 - 8003264: 4603 mov r3, r0 - 8003266: 71fb strb r3, [r7, #7] + 8003296: b580 push {r7, lr} + 8003298: b082 sub sp, #8 + 800329a: af00 add r7, sp, #0 + 800329c: 4603 mov r3, r0 + 800329e: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); - 8003268: f997 3007 ldrsb.w r3, [r7, #7] - 800326c: 4618 mov r0, r3 - 800326e: f7ff ff31 bl 80030d4 <__NVIC_EnableIRQ> + 80032a0: f997 3007 ldrsb.w r3, [r7, #7] + 80032a4: 4618 mov r0, r3 + 80032a6: f7ff ff31 bl 800310c <__NVIC_EnableIRQ> } - 8003272: bf00 nop - 8003274: 3708 adds r7, #8 - 8003276: 46bd mov sp, r7 - 8003278: bd80 pop {r7, pc} + 80032aa: bf00 nop + 80032ac: 3708 adds r7, #8 + 80032ae: 46bd mov sp, r7 + 80032b0: bd80 pop {r7, pc} -0800327a : +080032b2 : * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { - 800327a: b580 push {r7, lr} - 800327c: b082 sub sp, #8 - 800327e: af00 add r7, sp, #0 - 8003280: 6078 str r0, [r7, #4] + 80032b2: b580 push {r7, lr} + 80032b4: b082 sub sp, #8 + 80032b6: af00 add r7, sp, #0 + 80032b8: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); - 8003282: 6878 ldr r0, [r7, #4] - 8003284: f7ff ffa2 bl 80031cc - 8003288: 4603 mov r3, r0 + 80032ba: 6878 ldr r0, [r7, #4] + 80032bc: f7ff ffa2 bl 8003204 + 80032c0: 4603 mov r3, r0 } - 800328a: 4618 mov r0, r3 - 800328c: 3708 adds r7, #8 - 800328e: 46bd mov sp, r7 - 8003290: bd80 pop {r7, pc} + 80032c2: 4618 mov r0, r3 + 80032c4: 3708 adds r7, #8 + 80032c6: 46bd mov sp, r7 + 80032c8: bd80 pop {r7, pc} -08003292 : +080032ca : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) { - 8003292: b580 push {r7, lr} - 8003294: b084 sub sp, #16 - 8003296: af00 add r7, sp, #0 - 8003298: 6078 str r0, [r7, #4] + 80032ca: b580 push {r7, lr} + 80032cc: b084 sub sp, #16 + 80032ce: af00 add r7, sp, #0 + 80032d0: 6078 str r0, [r7, #4] uint32_t tmp = 0U; - 800329a: 2300 movs r3, #0 - 800329c: 60fb str r3, [r7, #12] + 80032d2: 2300 movs r3, #0 + 80032d4: 60fb str r3, [r7, #12] /* Check the DMA handle allocation */ if(NULL == hdma) - 800329e: 687b ldr r3, [r7, #4] - 80032a0: 2b00 cmp r3, #0 - 80032a2: d101 bne.n 80032a8 + 80032d6: 687b ldr r3, [r7, #4] + 80032d8: 2b00 cmp r3, #0 + 80032da: d101 bne.n 80032e0 { return HAL_ERROR; - 80032a4: 2301 movs r3, #1 - 80032a6: e037 b.n 8003318 + 80032dc: 2301 movs r3, #1 + 80032de: e037 b.n 8003350 assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); assert_param(IS_DMA_MODE(hdma->Init.Mode)); assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; - 80032a8: 687b ldr r3, [r7, #4] - 80032aa: 2202 movs r2, #2 - 80032ac: f883 2021 strb.w r2, [r3, #33] @ 0x21 + 80032e0: 687b ldr r3, [r7, #4] + 80032e2: 2202 movs r2, #2 + 80032e4: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Get the CR register value */ tmp = hdma->Instance->CCR; - 80032b0: 687b ldr r3, [r7, #4] - 80032b2: 681b ldr r3, [r3, #0] - 80032b4: 681b ldr r3, [r3, #0] - 80032b6: 60fb str r3, [r7, #12] + 80032e8: 687b ldr r3, [r7, #4] + 80032ea: 681b ldr r3, [r3, #0] + 80032ec: 681b ldr r3, [r3, #0] + 80032ee: 60fb str r3, [r7, #12] /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR bits */ tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \ - 80032b8: 68fb ldr r3, [r7, #12] - 80032ba: f423 537f bic.w r3, r3, #16320 @ 0x3fc0 - 80032be: f023 0330 bic.w r3, r3, #48 @ 0x30 - 80032c2: 60fb str r3, [r7, #12] + 80032f0: 68fb ldr r3, [r7, #12] + 80032f2: f423 537f bic.w r3, r3, #16320 @ 0x3fc0 + 80032f6: f023 0330 bic.w r3, r3, #48 @ 0x30 + 80032fa: 60fb str r3, [r7, #12] DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \ DMA_CCR_DIR)); /* Prepare the DMA Channel configuration */ tmp |= hdma->Init.Direction | - 80032c4: 687b ldr r3, [r7, #4] - 80032c6: 685a ldr r2, [r3, #4] + 80032fc: 687b ldr r3, [r7, #4] + 80032fe: 685a ldr r2, [r3, #4] hdma->Init.PeriphInc | hdma->Init.MemInc | - 80032c8: 687b ldr r3, [r7, #4] - 80032ca: 689b ldr r3, [r3, #8] + 8003300: 687b ldr r3, [r7, #4] + 8003302: 689b ldr r3, [r3, #8] tmp |= hdma->Init.Direction | - 80032cc: 431a orrs r2, r3 + 8003304: 431a orrs r2, r3 hdma->Init.PeriphInc | hdma->Init.MemInc | - 80032ce: 687b ldr r3, [r7, #4] - 80032d0: 68db ldr r3, [r3, #12] - 80032d2: 431a orrs r2, r3 + 8003306: 687b ldr r3, [r7, #4] + 8003308: 68db ldr r3, [r3, #12] + 800330a: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | - 80032d4: 687b ldr r3, [r7, #4] - 80032d6: 691b ldr r3, [r3, #16] + 800330c: 687b ldr r3, [r7, #4] + 800330e: 691b ldr r3, [r3, #16] hdma->Init.PeriphInc | hdma->Init.MemInc | - 80032d8: 431a orrs r2, r3 + 8003310: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | - 80032da: 687b ldr r3, [r7, #4] - 80032dc: 695b ldr r3, [r3, #20] - 80032de: 431a orrs r2, r3 + 8003312: 687b ldr r3, [r7, #4] + 8003314: 695b ldr r3, [r3, #20] + 8003316: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; - 80032e0: 687b ldr r3, [r7, #4] - 80032e2: 699b ldr r3, [r3, #24] + 8003318: 687b ldr r3, [r7, #4] + 800331a: 699b ldr r3, [r3, #24] hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | - 80032e4: 431a orrs r2, r3 + 800331c: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; - 80032e6: 687b ldr r3, [r7, #4] - 80032e8: 69db ldr r3, [r3, #28] - 80032ea: 4313 orrs r3, r2 + 800331e: 687b ldr r3, [r7, #4] + 8003320: 69db ldr r3, [r3, #28] + 8003322: 4313 orrs r3, r2 tmp |= hdma->Init.Direction | - 80032ec: 68fa ldr r2, [r7, #12] - 80032ee: 4313 orrs r3, r2 - 80032f0: 60fb str r3, [r7, #12] + 8003324: 68fa ldr r2, [r7, #12] + 8003326: 4313 orrs r3, r2 + 8003328: 60fb str r3, [r7, #12] /* Write to DMA Channel CR register */ hdma->Instance->CCR = tmp; - 80032f2: 687b ldr r3, [r7, #4] - 80032f4: 681b ldr r3, [r3, #0] - 80032f6: 68fa ldr r2, [r7, #12] - 80032f8: 601a str r2, [r3, #0] + 800332a: 687b ldr r3, [r7, #4] + 800332c: 681b ldr r3, [r3, #0] + 800332e: 68fa ldr r2, [r7, #12] + 8003330: 601a str r2, [r3, #0] /* Initialize DmaBaseAddress and ChannelIndex parameters used by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ DMA_CalcBaseAndBitshift(hdma); - 80032fa: 6878 ldr r0, [r7, #4] - 80032fc: f000 f8b4 bl 8003468 + 8003332: 6878 ldr r0, [r7, #4] + 8003334: f000 f8b4 bl 80034a0 /* Initialise the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; - 8003300: 687b ldr r3, [r7, #4] - 8003302: 2200 movs r2, #0 - 8003304: 639a str r2, [r3, #56] @ 0x38 + 8003338: 687b ldr r3, [r7, #4] + 800333a: 2200 movs r2, #0 + 800333c: 639a str r2, [r3, #56] @ 0x38 /* Initialize the DMA state*/ hdma->State = HAL_DMA_STATE_READY; - 8003306: 687b ldr r3, [r7, #4] - 8003308: 2201 movs r2, #1 - 800330a: f883 2021 strb.w r2, [r3, #33] @ 0x21 + 800333e: 687b ldr r3, [r7, #4] + 8003340: 2201 movs r2, #1 + 8003342: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Allocate lock resource and initialize it */ hdma->Lock = HAL_UNLOCKED; - 800330e: 687b ldr r3, [r7, #4] - 8003310: 2200 movs r2, #0 - 8003312: f883 2020 strb.w r2, [r3, #32] + 8003346: 687b ldr r3, [r7, #4] + 8003348: 2200 movs r2, #0 + 800334a: f883 2020 strb.w r2, [r3, #32] return HAL_OK; - 8003316: 2300 movs r3, #0 + 800334e: 2300 movs r3, #0 } - 8003318: 4618 mov r0, r3 - 800331a: 3710 adds r7, #16 - 800331c: 46bd mov sp, r7 - 800331e: bd80 pop {r7, pc} + 8003350: 4618 mov r0, r3 + 8003352: 3710 adds r7, #16 + 8003354: 46bd mov sp, r7 + 8003356: bd80 pop {r7, pc} -08003320 : +08003358 : * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval None */ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) { - 8003320: b580 push {r7, lr} - 8003322: b084 sub sp, #16 - 8003324: af00 add r7, sp, #0 - 8003326: 6078 str r0, [r7, #4] + 8003358: b580 push {r7, lr} + 800335a: b084 sub sp, #16 + 800335c: af00 add r7, sp, #0 + 800335e: 6078 str r0, [r7, #4] uint32_t flag_it = hdma->DmaBaseAddress->ISR; - 8003328: 687b ldr r3, [r7, #4] - 800332a: 6bdb ldr r3, [r3, #60] @ 0x3c - 800332c: 681b ldr r3, [r3, #0] - 800332e: 60fb str r3, [r7, #12] + 8003360: 687b ldr r3, [r7, #4] + 8003362: 6bdb ldr r3, [r3, #60] @ 0x3c + 8003364: 681b ldr r3, [r3, #0] + 8003366: 60fb str r3, [r7, #12] uint32_t source_it = hdma->Instance->CCR; - 8003330: 687b ldr r3, [r7, #4] - 8003332: 681b ldr r3, [r3, #0] - 8003334: 681b ldr r3, [r3, #0] - 8003336: 60bb str r3, [r7, #8] + 8003368: 687b ldr r3, [r7, #4] + 800336a: 681b ldr r3, [r3, #0] + 800336c: 681b ldr r3, [r3, #0] + 800336e: 60bb str r3, [r7, #8] /* Half Transfer Complete Interrupt management ******************************/ if ((RESET != (flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_HT))) - 8003338: 687b ldr r3, [r7, #4] - 800333a: 6c1b ldr r3, [r3, #64] @ 0x40 - 800333c: 2204 movs r2, #4 - 800333e: 409a lsls r2, r3 - 8003340: 68fb ldr r3, [r7, #12] - 8003342: 4013 ands r3, r2 - 8003344: 2b00 cmp r3, #0 - 8003346: d024 beq.n 8003392 - 8003348: 68bb ldr r3, [r7, #8] - 800334a: f003 0304 and.w r3, r3, #4 - 800334e: 2b00 cmp r3, #0 - 8003350: d01f beq.n 8003392 + 8003370: 687b ldr r3, [r7, #4] + 8003372: 6c1b ldr r3, [r3, #64] @ 0x40 + 8003374: 2204 movs r2, #4 + 8003376: 409a lsls r2, r3 + 8003378: 68fb ldr r3, [r7, #12] + 800337a: 4013 ands r3, r2 + 800337c: 2b00 cmp r3, #0 + 800337e: d024 beq.n 80033ca + 8003380: 68bb ldr r3, [r7, #8] + 8003382: f003 0304 and.w r3, r3, #4 + 8003386: 2b00 cmp r3, #0 + 8003388: d01f beq.n 80033ca { /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) - 8003352: 687b ldr r3, [r7, #4] - 8003354: 681b ldr r3, [r3, #0] - 8003356: 681b ldr r3, [r3, #0] - 8003358: f003 0320 and.w r3, r3, #32 - 800335c: 2b00 cmp r3, #0 - 800335e: d107 bne.n 8003370 + 800338a: 687b ldr r3, [r7, #4] + 800338c: 681b ldr r3, [r3, #0] + 800338e: 681b ldr r3, [r3, #0] + 8003390: f003 0320 and.w r3, r3, #32 + 8003394: 2b00 cmp r3, #0 + 8003396: d107 bne.n 80033a8 { /* Disable the half transfer interrupt */ hdma->Instance->CCR &= ~DMA_IT_HT; - 8003360: 687b ldr r3, [r7, #4] - 8003362: 681b ldr r3, [r3, #0] - 8003364: 681a ldr r2, [r3, #0] - 8003366: 687b ldr r3, [r7, #4] - 8003368: 681b ldr r3, [r3, #0] - 800336a: f022 0204 bic.w r2, r2, #4 - 800336e: 601a str r2, [r3, #0] + 8003398: 687b ldr r3, [r7, #4] + 800339a: 681b ldr r3, [r3, #0] + 800339c: 681a ldr r2, [r3, #0] + 800339e: 687b ldr r3, [r7, #4] + 80033a0: 681b ldr r3, [r3, #0] + 80033a2: f022 0204 bic.w r2, r2, #4 + 80033a6: 601a str r2, [r3, #0] } /* Clear the half transfer complete flag */ hdma->DmaBaseAddress->IFCR = DMA_FLAG_HT1 << hdma->ChannelIndex; - 8003370: 687b ldr r3, [r7, #4] - 8003372: 6c1a ldr r2, [r3, #64] @ 0x40 - 8003374: 687b ldr r3, [r7, #4] - 8003376: 6bdb ldr r3, [r3, #60] @ 0x3c - 8003378: 2104 movs r1, #4 - 800337a: fa01 f202 lsl.w r2, r1, r2 - 800337e: 605a str r2, [r3, #4] + 80033a8: 687b ldr r3, [r7, #4] + 80033aa: 6c1a ldr r2, [r3, #64] @ 0x40 + 80033ac: 687b ldr r3, [r7, #4] + 80033ae: 6bdb ldr r3, [r3, #60] @ 0x3c + 80033b0: 2104 movs r1, #4 + 80033b2: fa01 f202 lsl.w r2, r1, r2 + 80033b6: 605a str r2, [r3, #4] /* DMA peripheral state is not updated in Half Transfer */ /* State is updated only in Transfer Complete case */ if(hdma->XferHalfCpltCallback != NULL) - 8003380: 687b ldr r3, [r7, #4] - 8003382: 6adb ldr r3, [r3, #44] @ 0x2c - 8003384: 2b00 cmp r3, #0 - 8003386: d06a beq.n 800345e + 80033b8: 687b ldr r3, [r7, #4] + 80033ba: 6adb ldr r3, [r3, #44] @ 0x2c + 80033bc: 2b00 cmp r3, #0 + 80033be: d06a beq.n 8003496 { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); - 8003388: 687b ldr r3, [r7, #4] - 800338a: 6adb ldr r3, [r3, #44] @ 0x2c - 800338c: 6878 ldr r0, [r7, #4] - 800338e: 4798 blx r3 + 80033c0: 687b ldr r3, [r7, #4] + 80033c2: 6adb ldr r3, [r3, #44] @ 0x2c + 80033c4: 6878 ldr r0, [r7, #4] + 80033c6: 4798 blx r3 if(hdma->XferHalfCpltCallback != NULL) - 8003390: e065 b.n 800345e + 80033c8: e065 b.n 8003496 } } /* Transfer Complete Interrupt management ***********************************/ else if ((RESET != (flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TC))) - 8003392: 687b ldr r3, [r7, #4] - 8003394: 6c1b ldr r3, [r3, #64] @ 0x40 - 8003396: 2202 movs r2, #2 - 8003398: 409a lsls r2, r3 - 800339a: 68fb ldr r3, [r7, #12] - 800339c: 4013 ands r3, r2 - 800339e: 2b00 cmp r3, #0 - 80033a0: d02c beq.n 80033fc - 80033a2: 68bb ldr r3, [r7, #8] - 80033a4: f003 0302 and.w r3, r3, #2 - 80033a8: 2b00 cmp r3, #0 - 80033aa: d027 beq.n 80033fc + 80033ca: 687b ldr r3, [r7, #4] + 80033cc: 6c1b ldr r3, [r3, #64] @ 0x40 + 80033ce: 2202 movs r2, #2 + 80033d0: 409a lsls r2, r3 + 80033d2: 68fb ldr r3, [r7, #12] + 80033d4: 4013 ands r3, r2 + 80033d6: 2b00 cmp r3, #0 + 80033d8: d02c beq.n 8003434 + 80033da: 68bb ldr r3, [r7, #8] + 80033dc: f003 0302 and.w r3, r3, #2 + 80033e0: 2b00 cmp r3, #0 + 80033e2: d027 beq.n 8003434 { if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) - 80033ac: 687b ldr r3, [r7, #4] - 80033ae: 681b ldr r3, [r3, #0] - 80033b0: 681b ldr r3, [r3, #0] - 80033b2: f003 0320 and.w r3, r3, #32 - 80033b6: 2b00 cmp r3, #0 - 80033b8: d10b bne.n 80033d2 + 80033e4: 687b ldr r3, [r7, #4] + 80033e6: 681b ldr r3, [r3, #0] + 80033e8: 681b ldr r3, [r3, #0] + 80033ea: f003 0320 and.w r3, r3, #32 + 80033ee: 2b00 cmp r3, #0 + 80033f0: d10b bne.n 800340a { /* Disable the transfer complete & transfer error interrupts */ /* if the DMA mode is not CIRCULAR */ hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_TE); - 80033ba: 687b ldr r3, [r7, #4] - 80033bc: 681b ldr r3, [r3, #0] - 80033be: 681a ldr r2, [r3, #0] - 80033c0: 687b ldr r3, [r7, #4] - 80033c2: 681b ldr r3, [r3, #0] - 80033c4: f022 020a bic.w r2, r2, #10 - 80033c8: 601a str r2, [r3, #0] + 80033f2: 687b ldr r3, [r7, #4] + 80033f4: 681b ldr r3, [r3, #0] + 80033f6: 681a ldr r2, [r3, #0] + 80033f8: 687b ldr r3, [r7, #4] + 80033fa: 681b ldr r3, [r3, #0] + 80033fc: f022 020a bic.w r2, r2, #10 + 8003400: 601a str r2, [r3, #0] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; - 80033ca: 687b ldr r3, [r7, #4] - 80033cc: 2201 movs r2, #1 - 80033ce: f883 2021 strb.w r2, [r3, #33] @ 0x21 + 8003402: 687b ldr r3, [r7, #4] + 8003404: 2201 movs r2, #1 + 8003406: f883 2021 strb.w r2, [r3, #33] @ 0x21 } /* Clear the transfer complete flag */ hdma->DmaBaseAddress->IFCR = DMA_FLAG_TC1 << hdma->ChannelIndex; - 80033d2: 687b ldr r3, [r7, #4] - 80033d4: 6c1a ldr r2, [r3, #64] @ 0x40 - 80033d6: 687b ldr r3, [r7, #4] - 80033d8: 6bdb ldr r3, [r3, #60] @ 0x3c - 80033da: 2102 movs r1, #2 - 80033dc: fa01 f202 lsl.w r2, r1, r2 - 80033e0: 605a str r2, [r3, #4] + 800340a: 687b ldr r3, [r7, #4] + 800340c: 6c1a ldr r2, [r3, #64] @ 0x40 + 800340e: 687b ldr r3, [r7, #4] + 8003410: 6bdb ldr r3, [r3, #60] @ 0x3c + 8003412: 2102 movs r1, #2 + 8003414: fa01 f202 lsl.w r2, r1, r2 + 8003418: 605a str r2, [r3, #4] /* Process Unlocked */ __HAL_UNLOCK(hdma); - 80033e2: 687b ldr r3, [r7, #4] - 80033e4: 2200 movs r2, #0 - 80033e6: f883 2020 strb.w r2, [r3, #32] + 800341a: 687b ldr r3, [r7, #4] + 800341c: 2200 movs r2, #0 + 800341e: f883 2020 strb.w r2, [r3, #32] if(hdma->XferCpltCallback != NULL) - 80033ea: 687b ldr r3, [r7, #4] - 80033ec: 6a9b ldr r3, [r3, #40] @ 0x28 - 80033ee: 2b00 cmp r3, #0 - 80033f0: d035 beq.n 800345e + 8003422: 687b ldr r3, [r7, #4] + 8003424: 6a9b ldr r3, [r3, #40] @ 0x28 + 8003426: 2b00 cmp r3, #0 + 8003428: d035 beq.n 8003496 { /* Transfer complete callback */ hdma->XferCpltCallback(hdma); - 80033f2: 687b ldr r3, [r7, #4] - 80033f4: 6a9b ldr r3, [r3, #40] @ 0x28 - 80033f6: 6878 ldr r0, [r7, #4] - 80033f8: 4798 blx r3 + 800342a: 687b ldr r3, [r7, #4] + 800342c: 6a9b ldr r3, [r3, #40] @ 0x28 + 800342e: 6878 ldr r0, [r7, #4] + 8003430: 4798 blx r3 if(hdma->XferCpltCallback != NULL) - 80033fa: e030 b.n 800345e + 8003432: e030 b.n 8003496 } } /* Transfer Error Interrupt management ***************************************/ else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE))) - 80033fc: 687b ldr r3, [r7, #4] - 80033fe: 6c1b ldr r3, [r3, #64] @ 0x40 - 8003400: 2208 movs r2, #8 - 8003402: 409a lsls r2, r3 - 8003404: 68fb ldr r3, [r7, #12] - 8003406: 4013 ands r3, r2 - 8003408: 2b00 cmp r3, #0 - 800340a: d028 beq.n 800345e - 800340c: 68bb ldr r3, [r7, #8] - 800340e: f003 0308 and.w r3, r3, #8 - 8003412: 2b00 cmp r3, #0 - 8003414: d023 beq.n 800345e + 8003434: 687b ldr r3, [r7, #4] + 8003436: 6c1b ldr r3, [r3, #64] @ 0x40 + 8003438: 2208 movs r2, #8 + 800343a: 409a lsls r2, r3 + 800343c: 68fb ldr r3, [r7, #12] + 800343e: 4013 ands r3, r2 + 8003440: 2b00 cmp r3, #0 + 8003442: d028 beq.n 8003496 + 8003444: 68bb ldr r3, [r7, #8] + 8003446: f003 0308 and.w r3, r3, #8 + 800344a: 2b00 cmp r3, #0 + 800344c: d023 beq.n 8003496 { /* When a DMA transfer error occurs */ /* A hardware clear of its EN bits is performed */ /* Then, disable all DMA interrupts */ hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE); - 8003416: 687b ldr r3, [r7, #4] - 8003418: 681b ldr r3, [r3, #0] - 800341a: 681a ldr r2, [r3, #0] - 800341c: 687b ldr r3, [r7, #4] - 800341e: 681b ldr r3, [r3, #0] - 8003420: f022 020e bic.w r2, r2, #14 - 8003424: 601a str r2, [r3, #0] + 800344e: 687b ldr r3, [r7, #4] + 8003450: 681b ldr r3, [r3, #0] + 8003452: 681a ldr r2, [r3, #0] + 8003454: 687b ldr r3, [r7, #4] + 8003456: 681b ldr r3, [r3, #0] + 8003458: f022 020e bic.w r2, r2, #14 + 800345c: 601a str r2, [r3, #0] /* Clear all flags */ hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex; - 8003426: 687b ldr r3, [r7, #4] - 8003428: 6c1a ldr r2, [r3, #64] @ 0x40 - 800342a: 687b ldr r3, [r7, #4] - 800342c: 6bdb ldr r3, [r3, #60] @ 0x3c - 800342e: 2101 movs r1, #1 - 8003430: fa01 f202 lsl.w r2, r1, r2 - 8003434: 605a str r2, [r3, #4] + 800345e: 687b ldr r3, [r7, #4] + 8003460: 6c1a ldr r2, [r3, #64] @ 0x40 + 8003462: 687b ldr r3, [r7, #4] + 8003464: 6bdb ldr r3, [r3, #60] @ 0x3c + 8003466: 2101 movs r1, #1 + 8003468: fa01 f202 lsl.w r2, r1, r2 + 800346c: 605a str r2, [r3, #4] /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TE; - 8003436: 687b ldr r3, [r7, #4] - 8003438: 2201 movs r2, #1 - 800343a: 639a str r2, [r3, #56] @ 0x38 + 800346e: 687b ldr r3, [r7, #4] + 8003470: 2201 movs r2, #1 + 8003472: 639a str r2, [r3, #56] @ 0x38 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; - 800343c: 687b ldr r3, [r7, #4] - 800343e: 2201 movs r2, #1 - 8003440: f883 2021 strb.w r2, [r3, #33] @ 0x21 + 8003474: 687b ldr r3, [r7, #4] + 8003476: 2201 movs r2, #1 + 8003478: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Process Unlocked */ __HAL_UNLOCK(hdma); - 8003444: 687b ldr r3, [r7, #4] - 8003446: 2200 movs r2, #0 - 8003448: f883 2020 strb.w r2, [r3, #32] + 800347c: 687b ldr r3, [r7, #4] + 800347e: 2200 movs r2, #0 + 8003480: f883 2020 strb.w r2, [r3, #32] if(hdma->XferErrorCallback != NULL) - 800344c: 687b ldr r3, [r7, #4] - 800344e: 6b1b ldr r3, [r3, #48] @ 0x30 - 8003450: 2b00 cmp r3, #0 - 8003452: d004 beq.n 800345e + 8003484: 687b ldr r3, [r7, #4] + 8003486: 6b1b ldr r3, [r3, #48] @ 0x30 + 8003488: 2b00 cmp r3, #0 + 800348a: d004 beq.n 8003496 { /* Transfer error callback */ hdma->XferErrorCallback(hdma); - 8003454: 687b ldr r3, [r7, #4] - 8003456: 6b1b ldr r3, [r3, #48] @ 0x30 - 8003458: 6878 ldr r0, [r7, #4] - 800345a: 4798 blx r3 + 800348c: 687b ldr r3, [r7, #4] + 800348e: 6b1b ldr r3, [r3, #48] @ 0x30 + 8003490: 6878 ldr r0, [r7, #4] + 8003492: 4798 blx r3 } } } - 800345c: e7ff b.n 800345e - 800345e: bf00 nop - 8003460: 3710 adds r7, #16 - 8003462: 46bd mov sp, r7 - 8003464: bd80 pop {r7, pc} + 8003494: e7ff b.n 8003496 + 8003496: bf00 nop + 8003498: 3710 adds r7, #16 + 800349a: 46bd mov sp, r7 + 800349c: bd80 pop {r7, pc} ... -08003468 : +080034a0 : * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval None */ static void DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) { - 8003468: b480 push {r7} - 800346a: b083 sub sp, #12 - 800346c: af00 add r7, sp, #0 - 800346e: 6078 str r0, [r7, #4] + 80034a0: b480 push {r7} + 80034a2: b083 sub sp, #12 + 80034a4: af00 add r7, sp, #0 + 80034a6: 6078 str r0, [r7, #4] #if defined (DMA2) /* calculation of the channel index */ if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) - 8003470: 687b ldr r3, [r7, #4] - 8003472: 681b ldr r3, [r3, #0] - 8003474: 461a mov r2, r3 - 8003476: 4b14 ldr r3, [pc, #80] @ (80034c8 ) - 8003478: 429a cmp r2, r3 - 800347a: d80f bhi.n 800349c + 80034a8: 687b ldr r3, [r7, #4] + 80034aa: 681b ldr r3, [r3, #0] + 80034ac: 461a mov r2, r3 + 80034ae: 4b14 ldr r3, [pc, #80] @ (8003500 ) + 80034b0: 429a cmp r2, r3 + 80034b2: d80f bhi.n 80034d4 { /* DMA1 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; - 800347c: 687b ldr r3, [r7, #4] - 800347e: 681b ldr r3, [r3, #0] - 8003480: 461a mov r2, r3 - 8003482: 4b12 ldr r3, [pc, #72] @ (80034cc ) - 8003484: 4413 add r3, r2 - 8003486: 4a12 ldr r2, [pc, #72] @ (80034d0 ) - 8003488: fba2 2303 umull r2, r3, r2, r3 - 800348c: 091b lsrs r3, r3, #4 - 800348e: 009a lsls r2, r3, #2 - 8003490: 687b ldr r3, [r7, #4] - 8003492: 641a str r2, [r3, #64] @ 0x40 + 80034b4: 687b ldr r3, [r7, #4] + 80034b6: 681b ldr r3, [r3, #0] + 80034b8: 461a mov r2, r3 + 80034ba: 4b12 ldr r3, [pc, #72] @ (8003504 ) + 80034bc: 4413 add r3, r2 + 80034be: 4a12 ldr r2, [pc, #72] @ (8003508 ) + 80034c0: fba2 2303 umull r2, r3, r2, r3 + 80034c4: 091b lsrs r3, r3, #4 + 80034c6: 009a lsls r2, r3, #2 + 80034c8: 687b ldr r3, [r7, #4] + 80034ca: 641a str r2, [r3, #64] @ 0x40 hdma->DmaBaseAddress = DMA1; - 8003494: 687b ldr r3, [r7, #4] - 8003496: 4a0f ldr r2, [pc, #60] @ (80034d4 ) - 8003498: 63da str r2, [r3, #60] @ 0x3c + 80034cc: 687b ldr r3, [r7, #4] + 80034ce: 4a0f ldr r2, [pc, #60] @ (800350c ) + 80034d0: 63da str r2, [r3, #60] @ 0x3c /* calculation of the channel index */ /* DMA1 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; hdma->DmaBaseAddress = DMA1; #endif } - 800349a: e00e b.n 80034ba + 80034d2: e00e b.n 80034f2 hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U; - 800349c: 687b ldr r3, [r7, #4] - 800349e: 681b ldr r3, [r3, #0] - 80034a0: 461a mov r2, r3 - 80034a2: 4b0d ldr r3, [pc, #52] @ (80034d8 ) - 80034a4: 4413 add r3, r2 - 80034a6: 4a0a ldr r2, [pc, #40] @ (80034d0 ) - 80034a8: fba2 2303 umull r2, r3, r2, r3 - 80034ac: 091b lsrs r3, r3, #4 - 80034ae: 009a lsls r2, r3, #2 - 80034b0: 687b ldr r3, [r7, #4] - 80034b2: 641a str r2, [r3, #64] @ 0x40 + 80034d4: 687b ldr r3, [r7, #4] + 80034d6: 681b ldr r3, [r3, #0] + 80034d8: 461a mov r2, r3 + 80034da: 4b0d ldr r3, [pc, #52] @ (8003510 ) + 80034dc: 4413 add r3, r2 + 80034de: 4a0a ldr r2, [pc, #40] @ (8003508 ) + 80034e0: fba2 2303 umull r2, r3, r2, r3 + 80034e4: 091b lsrs r3, r3, #4 + 80034e6: 009a lsls r2, r3, #2 + 80034e8: 687b ldr r3, [r7, #4] + 80034ea: 641a str r2, [r3, #64] @ 0x40 hdma->DmaBaseAddress = DMA2; - 80034b4: 687b ldr r3, [r7, #4] - 80034b6: 4a09 ldr r2, [pc, #36] @ (80034dc ) - 80034b8: 63da str r2, [r3, #60] @ 0x3c + 80034ec: 687b ldr r3, [r7, #4] + 80034ee: 4a09 ldr r2, [pc, #36] @ (8003514 ) + 80034f0: 63da str r2, [r3, #60] @ 0x3c } - 80034ba: bf00 nop - 80034bc: 370c adds r7, #12 - 80034be: 46bd mov sp, r7 - 80034c0: f85d 7b04 ldr.w r7, [sp], #4 - 80034c4: 4770 bx lr - 80034c6: bf00 nop - 80034c8: 40020407 .word 0x40020407 - 80034cc: bffdfff8 .word 0xbffdfff8 - 80034d0: cccccccd .word 0xcccccccd - 80034d4: 40020000 .word 0x40020000 - 80034d8: bffdfbf8 .word 0xbffdfbf8 - 80034dc: 40020400 .word 0x40020400 + 80034f2: bf00 nop + 80034f4: 370c adds r7, #12 + 80034f6: 46bd mov sp, r7 + 80034f8: f85d 7b04 ldr.w r7, [sp], #4 + 80034fc: 4770 bx lr + 80034fe: bf00 nop + 8003500: 40020407 .word 0x40020407 + 8003504: bffdfff8 .word 0xbffdfff8 + 8003508: cccccccd .word 0xcccccccd + 800350c: 40020000 .word 0x40020000 + 8003510: bffdfbf8 .word 0xbffdfbf8 + 8003514: 40020400 .word 0x40020400 -080034e0 : +08003518 : * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { - 80034e0: b480 push {r7} - 80034e2: b087 sub sp, #28 - 80034e4: af00 add r7, sp, #0 - 80034e6: 6078 str r0, [r7, #4] - 80034e8: 6039 str r1, [r7, #0] + 8003518: b480 push {r7} + 800351a: b087 sub sp, #28 + 800351c: af00 add r7, sp, #0 + 800351e: 6078 str r0, [r7, #4] + 8003520: 6039 str r1, [r7, #0] uint32_t position = 0x00u; - 80034ea: 2300 movs r3, #0 - 80034ec: 617b str r3, [r7, #20] + 8003522: 2300 movs r3, #0 + 8003524: 617b str r3, [r7, #20] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00u) - 80034ee: e154 b.n 800379a + 8003526: e154 b.n 80037d2 { /* Get current io position */ iocurrent = (GPIO_Init->Pin) & (1uL << position); - 80034f0: 683b ldr r3, [r7, #0] - 80034f2: 681a ldr r2, [r3, #0] - 80034f4: 2101 movs r1, #1 - 80034f6: 697b ldr r3, [r7, #20] - 80034f8: fa01 f303 lsl.w r3, r1, r3 - 80034fc: 4013 ands r3, r2 - 80034fe: 60fb str r3, [r7, #12] + 8003528: 683b ldr r3, [r7, #0] + 800352a: 681a ldr r2, [r3, #0] + 800352c: 2101 movs r1, #1 + 800352e: 697b ldr r3, [r7, #20] + 8003530: fa01 f303 lsl.w r3, r1, r3 + 8003534: 4013 ands r3, r2 + 8003536: 60fb str r3, [r7, #12] if (iocurrent != 0x00u) - 8003500: 68fb ldr r3, [r7, #12] - 8003502: 2b00 cmp r3, #0 - 8003504: f000 8146 beq.w 8003794 + 8003538: 68fb ldr r3, [r7, #12] + 800353a: 2b00 cmp r3, #0 + 800353c: f000 8146 beq.w 80037cc { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) - 8003508: 683b ldr r3, [r7, #0] - 800350a: 685b ldr r3, [r3, #4] - 800350c: f003 0303 and.w r3, r3, #3 - 8003510: 2b01 cmp r3, #1 - 8003512: d005 beq.n 8003520 - 8003514: 683b ldr r3, [r7, #0] - 8003516: 685b ldr r3, [r3, #4] - 8003518: f003 0303 and.w r3, r3, #3 - 800351c: 2b02 cmp r3, #2 - 800351e: d130 bne.n 8003582 + 8003540: 683b ldr r3, [r7, #0] + 8003542: 685b ldr r3, [r3, #4] + 8003544: f003 0303 and.w r3, r3, #3 + 8003548: 2b01 cmp r3, #1 + 800354a: d005 beq.n 8003558 + 800354c: 683b ldr r3, [r7, #0] + 800354e: 685b ldr r3, [r3, #4] + 8003550: f003 0303 and.w r3, r3, #3 + 8003554: 2b02 cmp r3, #2 + 8003556: d130 bne.n 80035ba { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; - 8003520: 687b ldr r3, [r7, #4] - 8003522: 689b ldr r3, [r3, #8] - 8003524: 613b str r3, [r7, #16] + 8003558: 687b ldr r3, [r7, #4] + 800355a: 689b ldr r3, [r3, #8] + 800355c: 613b str r3, [r7, #16] temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2u)); - 8003526: 697b ldr r3, [r7, #20] - 8003528: 005b lsls r3, r3, #1 - 800352a: 2203 movs r2, #3 - 800352c: fa02 f303 lsl.w r3, r2, r3 - 8003530: 43db mvns r3, r3 - 8003532: 693a ldr r2, [r7, #16] - 8003534: 4013 ands r3, r2 - 8003536: 613b str r3, [r7, #16] + 800355e: 697b ldr r3, [r7, #20] + 8003560: 005b lsls r3, r3, #1 + 8003562: 2203 movs r2, #3 + 8003564: fa02 f303 lsl.w r3, r2, r3 + 8003568: 43db mvns r3, r3 + 800356a: 693a ldr r2, [r7, #16] + 800356c: 4013 ands r3, r2 + 800356e: 613b str r3, [r7, #16] temp |= (GPIO_Init->Speed << (position * 2u)); - 8003538: 683b ldr r3, [r7, #0] - 800353a: 68da ldr r2, [r3, #12] - 800353c: 697b ldr r3, [r7, #20] - 800353e: 005b lsls r3, r3, #1 - 8003540: fa02 f303 lsl.w r3, r2, r3 - 8003544: 693a ldr r2, [r7, #16] - 8003546: 4313 orrs r3, r2 - 8003548: 613b str r3, [r7, #16] + 8003570: 683b ldr r3, [r7, #0] + 8003572: 68da ldr r2, [r3, #12] + 8003574: 697b ldr r3, [r7, #20] + 8003576: 005b lsls r3, r3, #1 + 8003578: fa02 f303 lsl.w r3, r2, r3 + 800357c: 693a ldr r2, [r7, #16] + 800357e: 4313 orrs r3, r2 + 8003580: 613b str r3, [r7, #16] GPIOx->OSPEEDR = temp; - 800354a: 687b ldr r3, [r7, #4] - 800354c: 693a ldr r2, [r7, #16] - 800354e: 609a str r2, [r3, #8] + 8003582: 687b ldr r3, [r7, #4] + 8003584: 693a ldr r2, [r7, #16] + 8003586: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; - 8003550: 687b ldr r3, [r7, #4] - 8003552: 685b ldr r3, [r3, #4] - 8003554: 613b str r3, [r7, #16] + 8003588: 687b ldr r3, [r7, #4] + 800358a: 685b ldr r3, [r3, #4] + 800358c: 613b str r3, [r7, #16] temp &= ~(GPIO_OTYPER_OT_0 << position) ; - 8003556: 2201 movs r2, #1 - 8003558: 697b ldr r3, [r7, #20] - 800355a: fa02 f303 lsl.w r3, r2, r3 - 800355e: 43db mvns r3, r3 - 8003560: 693a ldr r2, [r7, #16] - 8003562: 4013 ands r3, r2 - 8003564: 613b str r3, [r7, #16] + 800358e: 2201 movs r2, #1 + 8003590: 697b ldr r3, [r7, #20] + 8003592: fa02 f303 lsl.w r3, r2, r3 + 8003596: 43db mvns r3, r3 + 8003598: 693a ldr r2, [r7, #16] + 800359a: 4013 ands r3, r2 + 800359c: 613b str r3, [r7, #16] temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); - 8003566: 683b ldr r3, [r7, #0] - 8003568: 685b ldr r3, [r3, #4] - 800356a: 091b lsrs r3, r3, #4 - 800356c: f003 0201 and.w r2, r3, #1 - 8003570: 697b ldr r3, [r7, #20] - 8003572: fa02 f303 lsl.w r3, r2, r3 - 8003576: 693a ldr r2, [r7, #16] - 8003578: 4313 orrs r3, r2 - 800357a: 613b str r3, [r7, #16] + 800359e: 683b ldr r3, [r7, #0] + 80035a0: 685b ldr r3, [r3, #4] + 80035a2: 091b lsrs r3, r3, #4 + 80035a4: f003 0201 and.w r2, r3, #1 + 80035a8: 697b ldr r3, [r7, #20] + 80035aa: fa02 f303 lsl.w r3, r2, r3 + 80035ae: 693a ldr r2, [r7, #16] + 80035b0: 4313 orrs r3, r2 + 80035b2: 613b str r3, [r7, #16] GPIOx->OTYPER = temp; - 800357c: 687b ldr r3, [r7, #4] - 800357e: 693a ldr r2, [r7, #16] - 8003580: 605a str r2, [r3, #4] + 80035b4: 687b ldr r3, [r7, #4] + 80035b6: 693a ldr r2, [r7, #16] + 80035b8: 605a str r2, [r3, #4] } if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) - 8003582: 683b ldr r3, [r7, #0] - 8003584: 685b ldr r3, [r3, #4] - 8003586: f003 0303 and.w r3, r3, #3 - 800358a: 2b03 cmp r3, #3 - 800358c: d017 beq.n 80035be + 80035ba: 683b ldr r3, [r7, #0] + 80035bc: 685b ldr r3, [r3, #4] + 80035be: f003 0303 and.w r3, r3, #3 + 80035c2: 2b03 cmp r3, #3 + 80035c4: d017 beq.n 80035f6 { /* Check the Pull parameter */ assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; - 800358e: 687b ldr r3, [r7, #4] - 8003590: 68db ldr r3, [r3, #12] - 8003592: 613b str r3, [r7, #16] + 80035c6: 687b ldr r3, [r7, #4] + 80035c8: 68db ldr r3, [r3, #12] + 80035ca: 613b str r3, [r7, #16] temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2u)); - 8003594: 697b ldr r3, [r7, #20] - 8003596: 005b lsls r3, r3, #1 - 8003598: 2203 movs r2, #3 - 800359a: fa02 f303 lsl.w r3, r2, r3 - 800359e: 43db mvns r3, r3 - 80035a0: 693a ldr r2, [r7, #16] - 80035a2: 4013 ands r3, r2 - 80035a4: 613b str r3, [r7, #16] + 80035cc: 697b ldr r3, [r7, #20] + 80035ce: 005b lsls r3, r3, #1 + 80035d0: 2203 movs r2, #3 + 80035d2: fa02 f303 lsl.w r3, r2, r3 + 80035d6: 43db mvns r3, r3 + 80035d8: 693a ldr r2, [r7, #16] + 80035da: 4013 ands r3, r2 + 80035dc: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Pull) << (position * 2u)); - 80035a6: 683b ldr r3, [r7, #0] - 80035a8: 689a ldr r2, [r3, #8] - 80035aa: 697b ldr r3, [r7, #20] - 80035ac: 005b lsls r3, r3, #1 - 80035ae: fa02 f303 lsl.w r3, r2, r3 - 80035b2: 693a ldr r2, [r7, #16] - 80035b4: 4313 orrs r3, r2 - 80035b6: 613b str r3, [r7, #16] + 80035de: 683b ldr r3, [r7, #0] + 80035e0: 689a ldr r2, [r3, #8] + 80035e2: 697b ldr r3, [r7, #20] + 80035e4: 005b lsls r3, r3, #1 + 80035e6: fa02 f303 lsl.w r3, r2, r3 + 80035ea: 693a ldr r2, [r7, #16] + 80035ec: 4313 orrs r3, r2 + 80035ee: 613b str r3, [r7, #16] GPIOx->PUPDR = temp; - 80035b8: 687b ldr r3, [r7, #4] - 80035ba: 693a ldr r2, [r7, #16] - 80035bc: 60da str r2, [r3, #12] + 80035f0: 687b ldr r3, [r7, #4] + 80035f2: 693a ldr r2, [r7, #16] + 80035f4: 60da str r2, [r3, #12] } /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Alternate function mode selection */ if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) - 80035be: 683b ldr r3, [r7, #0] - 80035c0: 685b ldr r3, [r3, #4] - 80035c2: f003 0303 and.w r3, r3, #3 - 80035c6: 2b02 cmp r3, #2 - 80035c8: d123 bne.n 8003612 + 80035f6: 683b ldr r3, [r7, #0] + 80035f8: 685b ldr r3, [r3, #4] + 80035fa: f003 0303 and.w r3, r3, #3 + 80035fe: 2b02 cmp r3, #2 + 8003600: d123 bne.n 800364a /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3u]; - 80035ca: 697b ldr r3, [r7, #20] - 80035cc: 08da lsrs r2, r3, #3 - 80035ce: 687b ldr r3, [r7, #4] - 80035d0: 3208 adds r2, #8 - 80035d2: f853 3022 ldr.w r3, [r3, r2, lsl #2] - 80035d6: 613b str r3, [r7, #16] + 8003602: 697b ldr r3, [r7, #20] + 8003604: 08da lsrs r2, r3, #3 + 8003606: 687b ldr r3, [r7, #4] + 8003608: 3208 adds r2, #8 + 800360a: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 800360e: 613b str r3, [r7, #16] temp &= ~(0xFu << ((position & 0x07u) * 4u)); - 80035d8: 697b ldr r3, [r7, #20] - 80035da: f003 0307 and.w r3, r3, #7 - 80035de: 009b lsls r3, r3, #2 - 80035e0: 220f movs r2, #15 - 80035e2: fa02 f303 lsl.w r3, r2, r3 - 80035e6: 43db mvns r3, r3 - 80035e8: 693a ldr r2, [r7, #16] - 80035ea: 4013 ands r3, r2 - 80035ec: 613b str r3, [r7, #16] + 8003610: 697b ldr r3, [r7, #20] + 8003612: f003 0307 and.w r3, r3, #7 + 8003616: 009b lsls r3, r3, #2 + 8003618: 220f movs r2, #15 + 800361a: fa02 f303 lsl.w r3, r2, r3 + 800361e: 43db mvns r3, r3 + 8003620: 693a ldr r2, [r7, #16] + 8003622: 4013 ands r3, r2 + 8003624: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u)); - 80035ee: 683b ldr r3, [r7, #0] - 80035f0: 691a ldr r2, [r3, #16] - 80035f2: 697b ldr r3, [r7, #20] - 80035f4: f003 0307 and.w r3, r3, #7 - 80035f8: 009b lsls r3, r3, #2 - 80035fa: fa02 f303 lsl.w r3, r2, r3 - 80035fe: 693a ldr r2, [r7, #16] - 8003600: 4313 orrs r3, r2 - 8003602: 613b str r3, [r7, #16] + 8003626: 683b ldr r3, [r7, #0] + 8003628: 691a ldr r2, [r3, #16] + 800362a: 697b ldr r3, [r7, #20] + 800362c: f003 0307 and.w r3, r3, #7 + 8003630: 009b lsls r3, r3, #2 + 8003632: fa02 f303 lsl.w r3, r2, r3 + 8003636: 693a ldr r2, [r7, #16] + 8003638: 4313 orrs r3, r2 + 800363a: 613b str r3, [r7, #16] GPIOx->AFR[position >> 3u] = temp; - 8003604: 697b ldr r3, [r7, #20] - 8003606: 08da lsrs r2, r3, #3 - 8003608: 687b ldr r3, [r7, #4] - 800360a: 3208 adds r2, #8 - 800360c: 6939 ldr r1, [r7, #16] - 800360e: f843 1022 str.w r1, [r3, r2, lsl #2] + 800363c: 697b ldr r3, [r7, #20] + 800363e: 08da lsrs r2, r3, #3 + 8003640: 687b ldr r3, [r7, #4] + 8003642: 3208 adds r2, #8 + 8003644: 6939 ldr r1, [r7, #16] + 8003646: f843 1022 str.w r1, [r3, r2, lsl #2] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; - 8003612: 687b ldr r3, [r7, #4] - 8003614: 681b ldr r3, [r3, #0] - 8003616: 613b str r3, [r7, #16] + 800364a: 687b ldr r3, [r7, #4] + 800364c: 681b ldr r3, [r3, #0] + 800364e: 613b str r3, [r7, #16] temp &= ~(GPIO_MODER_MODER0 << (position * 2u)); - 8003618: 697b ldr r3, [r7, #20] - 800361a: 005b lsls r3, r3, #1 - 800361c: 2203 movs r2, #3 - 800361e: fa02 f303 lsl.w r3, r2, r3 - 8003622: 43db mvns r3, r3 - 8003624: 693a ldr r2, [r7, #16] - 8003626: 4013 ands r3, r2 - 8003628: 613b str r3, [r7, #16] + 8003650: 697b ldr r3, [r7, #20] + 8003652: 005b lsls r3, r3, #1 + 8003654: 2203 movs r2, #3 + 8003656: fa02 f303 lsl.w r3, r2, r3 + 800365a: 43db mvns r3, r3 + 800365c: 693a ldr r2, [r7, #16] + 800365e: 4013 ands r3, r2 + 8003660: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u)); - 800362a: 683b ldr r3, [r7, #0] - 800362c: 685b ldr r3, [r3, #4] - 800362e: f003 0203 and.w r2, r3, #3 - 8003632: 697b ldr r3, [r7, #20] - 8003634: 005b lsls r3, r3, #1 - 8003636: fa02 f303 lsl.w r3, r2, r3 - 800363a: 693a ldr r2, [r7, #16] - 800363c: 4313 orrs r3, r2 - 800363e: 613b str r3, [r7, #16] + 8003662: 683b ldr r3, [r7, #0] + 8003664: 685b ldr r3, [r3, #4] + 8003666: f003 0203 and.w r2, r3, #3 + 800366a: 697b ldr r3, [r7, #20] + 800366c: 005b lsls r3, r3, #1 + 800366e: fa02 f303 lsl.w r3, r2, r3 + 8003672: 693a ldr r2, [r7, #16] + 8003674: 4313 orrs r3, r2 + 8003676: 613b str r3, [r7, #16] GPIOx->MODER = temp; - 8003640: 687b ldr r3, [r7, #4] - 8003642: 693a ldr r2, [r7, #16] - 8003644: 601a str r2, [r3, #0] + 8003678: 687b ldr r3, [r7, #4] + 800367a: 693a ldr r2, [r7, #16] + 800367c: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if((GPIO_Init->Mode & EXTI_MODE) != 0x00u) - 8003646: 683b ldr r3, [r7, #0] - 8003648: 685b ldr r3, [r3, #4] - 800364a: f403 3340 and.w r3, r3, #196608 @ 0x30000 - 800364e: 2b00 cmp r3, #0 - 8003650: f000 80a0 beq.w 8003794 + 800367e: 683b ldr r3, [r7, #0] + 8003680: 685b ldr r3, [r3, #4] + 8003682: f403 3340 and.w r3, r3, #196608 @ 0x30000 + 8003686: 2b00 cmp r3, #0 + 8003688: f000 80a0 beq.w 80037cc { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); - 8003654: 4b58 ldr r3, [pc, #352] @ (80037b8 ) - 8003656: 699b ldr r3, [r3, #24] - 8003658: 4a57 ldr r2, [pc, #348] @ (80037b8 ) - 800365a: f043 0301 orr.w r3, r3, #1 - 800365e: 6193 str r3, [r2, #24] - 8003660: 4b55 ldr r3, [pc, #340] @ (80037b8 ) - 8003662: 699b ldr r3, [r3, #24] - 8003664: f003 0301 and.w r3, r3, #1 - 8003668: 60bb str r3, [r7, #8] - 800366a: 68bb ldr r3, [r7, #8] + 800368c: 4b58 ldr r3, [pc, #352] @ (80037f0 ) + 800368e: 699b ldr r3, [r3, #24] + 8003690: 4a57 ldr r2, [pc, #348] @ (80037f0 ) + 8003692: f043 0301 orr.w r3, r3, #1 + 8003696: 6193 str r3, [r2, #24] + 8003698: 4b55 ldr r3, [pc, #340] @ (80037f0 ) + 800369a: 699b ldr r3, [r3, #24] + 800369c: f003 0301 and.w r3, r3, #1 + 80036a0: 60bb str r3, [r7, #8] + 80036a2: 68bb ldr r3, [r7, #8] temp = SYSCFG->EXTICR[position >> 2u]; - 800366c: 4a53 ldr r2, [pc, #332] @ (80037bc ) - 800366e: 697b ldr r3, [r7, #20] - 8003670: 089b lsrs r3, r3, #2 - 8003672: 3302 adds r3, #2 - 8003674: f852 3023 ldr.w r3, [r2, r3, lsl #2] - 8003678: 613b str r3, [r7, #16] + 80036a4: 4a53 ldr r2, [pc, #332] @ (80037f4 ) + 80036a6: 697b ldr r3, [r7, #20] + 80036a8: 089b lsrs r3, r3, #2 + 80036aa: 3302 adds r3, #2 + 80036ac: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 80036b0: 613b str r3, [r7, #16] temp &= ~(0x0FuL << (4u * (position & 0x03u))); - 800367a: 697b ldr r3, [r7, #20] - 800367c: f003 0303 and.w r3, r3, #3 - 8003680: 009b lsls r3, r3, #2 - 8003682: 220f movs r2, #15 - 8003684: fa02 f303 lsl.w r3, r2, r3 - 8003688: 43db mvns r3, r3 - 800368a: 693a ldr r2, [r7, #16] - 800368c: 4013 ands r3, r2 - 800368e: 613b str r3, [r7, #16] + 80036b2: 697b ldr r3, [r7, #20] + 80036b4: f003 0303 and.w r3, r3, #3 + 80036b8: 009b lsls r3, r3, #2 + 80036ba: 220f movs r2, #15 + 80036bc: fa02 f303 lsl.w r3, r2, r3 + 80036c0: 43db mvns r3, r3 + 80036c2: 693a ldr r2, [r7, #16] + 80036c4: 4013 ands r3, r2 + 80036c6: 613b str r3, [r7, #16] temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u))); - 8003690: 687b ldr r3, [r7, #4] - 8003692: f1b3 4f90 cmp.w r3, #1207959552 @ 0x48000000 - 8003696: d019 beq.n 80036cc - 8003698: 687b ldr r3, [r7, #4] - 800369a: 4a49 ldr r2, [pc, #292] @ (80037c0 ) - 800369c: 4293 cmp r3, r2 - 800369e: d013 beq.n 80036c8 - 80036a0: 687b ldr r3, [r7, #4] - 80036a2: 4a48 ldr r2, [pc, #288] @ (80037c4 ) - 80036a4: 4293 cmp r3, r2 - 80036a6: d00d beq.n 80036c4 - 80036a8: 687b ldr r3, [r7, #4] - 80036aa: 4a47 ldr r2, [pc, #284] @ (80037c8 ) - 80036ac: 4293 cmp r3, r2 - 80036ae: d007 beq.n 80036c0 - 80036b0: 687b ldr r3, [r7, #4] - 80036b2: 4a46 ldr r2, [pc, #280] @ (80037cc ) - 80036b4: 4293 cmp r3, r2 - 80036b6: d101 bne.n 80036bc - 80036b8: 2304 movs r3, #4 - 80036ba: e008 b.n 80036ce - 80036bc: 2305 movs r3, #5 - 80036be: e006 b.n 80036ce - 80036c0: 2303 movs r3, #3 - 80036c2: e004 b.n 80036ce - 80036c4: 2302 movs r3, #2 - 80036c6: e002 b.n 80036ce - 80036c8: 2301 movs r3, #1 - 80036ca: e000 b.n 80036ce - 80036cc: 2300 movs r3, #0 - 80036ce: 697a ldr r2, [r7, #20] - 80036d0: f002 0203 and.w r2, r2, #3 - 80036d4: 0092 lsls r2, r2, #2 - 80036d6: 4093 lsls r3, r2 - 80036d8: 693a ldr r2, [r7, #16] - 80036da: 4313 orrs r3, r2 - 80036dc: 613b str r3, [r7, #16] + 80036c8: 687b ldr r3, [r7, #4] + 80036ca: f1b3 4f90 cmp.w r3, #1207959552 @ 0x48000000 + 80036ce: d019 beq.n 8003704 + 80036d0: 687b ldr r3, [r7, #4] + 80036d2: 4a49 ldr r2, [pc, #292] @ (80037f8 ) + 80036d4: 4293 cmp r3, r2 + 80036d6: d013 beq.n 8003700 + 80036d8: 687b ldr r3, [r7, #4] + 80036da: 4a48 ldr r2, [pc, #288] @ (80037fc ) + 80036dc: 4293 cmp r3, r2 + 80036de: d00d beq.n 80036fc + 80036e0: 687b ldr r3, [r7, #4] + 80036e2: 4a47 ldr r2, [pc, #284] @ (8003800 ) + 80036e4: 4293 cmp r3, r2 + 80036e6: d007 beq.n 80036f8 + 80036e8: 687b ldr r3, [r7, #4] + 80036ea: 4a46 ldr r2, [pc, #280] @ (8003804 ) + 80036ec: 4293 cmp r3, r2 + 80036ee: d101 bne.n 80036f4 + 80036f0: 2304 movs r3, #4 + 80036f2: e008 b.n 8003706 + 80036f4: 2305 movs r3, #5 + 80036f6: e006 b.n 8003706 + 80036f8: 2303 movs r3, #3 + 80036fa: e004 b.n 8003706 + 80036fc: 2302 movs r3, #2 + 80036fe: e002 b.n 8003706 + 8003700: 2301 movs r3, #1 + 8003702: e000 b.n 8003706 + 8003704: 2300 movs r3, #0 + 8003706: 697a ldr r2, [r7, #20] + 8003708: f002 0203 and.w r2, r2, #3 + 800370c: 0092 lsls r2, r2, #2 + 800370e: 4093 lsls r3, r2 + 8003710: 693a ldr r2, [r7, #16] + 8003712: 4313 orrs r3, r2 + 8003714: 613b str r3, [r7, #16] SYSCFG->EXTICR[position >> 2u] = temp; - 80036de: 4937 ldr r1, [pc, #220] @ (80037bc ) - 80036e0: 697b ldr r3, [r7, #20] - 80036e2: 089b lsrs r3, r3, #2 - 80036e4: 3302 adds r3, #2 - 80036e6: 693a ldr r2, [r7, #16] - 80036e8: f841 2023 str.w r2, [r1, r3, lsl #2] + 8003716: 4937 ldr r1, [pc, #220] @ (80037f4 ) + 8003718: 697b ldr r3, [r7, #20] + 800371a: 089b lsrs r3, r3, #2 + 800371c: 3302 adds r3, #2 + 800371e: 693a ldr r2, [r7, #16] + 8003720: f841 2023 str.w r2, [r1, r3, lsl #2] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR; - 80036ec: 4b38 ldr r3, [pc, #224] @ (80037d0 ) - 80036ee: 689b ldr r3, [r3, #8] - 80036f0: 613b str r3, [r7, #16] + 8003724: 4b38 ldr r3, [pc, #224] @ (8003808 ) + 8003726: 689b ldr r3, [r3, #8] + 8003728: 613b str r3, [r7, #16] temp &= ~(iocurrent); - 80036f2: 68fb ldr r3, [r7, #12] - 80036f4: 43db mvns r3, r3 - 80036f6: 693a ldr r2, [r7, #16] - 80036f8: 4013 ands r3, r2 - 80036fa: 613b str r3, [r7, #16] + 800372a: 68fb ldr r3, [r7, #12] + 800372c: 43db mvns r3, r3 + 800372e: 693a ldr r2, [r7, #16] + 8003730: 4013 ands r3, r2 + 8003732: 613b str r3, [r7, #16] if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u) - 80036fc: 683b ldr r3, [r7, #0] - 80036fe: 685b ldr r3, [r3, #4] - 8003700: f403 1380 and.w r3, r3, #1048576 @ 0x100000 - 8003704: 2b00 cmp r3, #0 - 8003706: d003 beq.n 8003710 + 8003734: 683b ldr r3, [r7, #0] + 8003736: 685b ldr r3, [r3, #4] + 8003738: f403 1380 and.w r3, r3, #1048576 @ 0x100000 + 800373c: 2b00 cmp r3, #0 + 800373e: d003 beq.n 8003748 { temp |= iocurrent; - 8003708: 693a ldr r2, [r7, #16] - 800370a: 68fb ldr r3, [r7, #12] - 800370c: 4313 orrs r3, r2 - 800370e: 613b str r3, [r7, #16] + 8003740: 693a ldr r2, [r7, #16] + 8003742: 68fb ldr r3, [r7, #12] + 8003744: 4313 orrs r3, r2 + 8003746: 613b str r3, [r7, #16] } EXTI->RTSR = temp; - 8003710: 4a2f ldr r2, [pc, #188] @ (80037d0 ) - 8003712: 693b ldr r3, [r7, #16] - 8003714: 6093 str r3, [r2, #8] + 8003748: 4a2f ldr r2, [pc, #188] @ (8003808 ) + 800374a: 693b ldr r3, [r7, #16] + 800374c: 6093 str r3, [r2, #8] temp = EXTI->FTSR; - 8003716: 4b2e ldr r3, [pc, #184] @ (80037d0 ) - 8003718: 68db ldr r3, [r3, #12] - 800371a: 613b str r3, [r7, #16] + 800374e: 4b2e ldr r3, [pc, #184] @ (8003808 ) + 8003750: 68db ldr r3, [r3, #12] + 8003752: 613b str r3, [r7, #16] temp &= ~(iocurrent); - 800371c: 68fb ldr r3, [r7, #12] - 800371e: 43db mvns r3, r3 - 8003720: 693a ldr r2, [r7, #16] - 8003722: 4013 ands r3, r2 - 8003724: 613b str r3, [r7, #16] + 8003754: 68fb ldr r3, [r7, #12] + 8003756: 43db mvns r3, r3 + 8003758: 693a ldr r2, [r7, #16] + 800375a: 4013 ands r3, r2 + 800375c: 613b str r3, [r7, #16] if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u) - 8003726: 683b ldr r3, [r7, #0] - 8003728: 685b ldr r3, [r3, #4] - 800372a: f403 1300 and.w r3, r3, #2097152 @ 0x200000 - 800372e: 2b00 cmp r3, #0 - 8003730: d003 beq.n 800373a + 800375e: 683b ldr r3, [r7, #0] + 8003760: 685b ldr r3, [r3, #4] + 8003762: f403 1300 and.w r3, r3, #2097152 @ 0x200000 + 8003766: 2b00 cmp r3, #0 + 8003768: d003 beq.n 8003772 { temp |= iocurrent; - 8003732: 693a ldr r2, [r7, #16] - 8003734: 68fb ldr r3, [r7, #12] - 8003736: 4313 orrs r3, r2 - 8003738: 613b str r3, [r7, #16] + 800376a: 693a ldr r2, [r7, #16] + 800376c: 68fb ldr r3, [r7, #12] + 800376e: 4313 orrs r3, r2 + 8003770: 613b str r3, [r7, #16] } EXTI->FTSR = temp; - 800373a: 4a25 ldr r2, [pc, #148] @ (80037d0 ) - 800373c: 693b ldr r3, [r7, #16] - 800373e: 60d3 str r3, [r2, #12] + 8003772: 4a25 ldr r2, [pc, #148] @ (8003808 ) + 8003774: 693b ldr r3, [r7, #16] + 8003776: 60d3 str r3, [r2, #12] temp = EXTI->EMR; - 8003740: 4b23 ldr r3, [pc, #140] @ (80037d0 ) - 8003742: 685b ldr r3, [r3, #4] - 8003744: 613b str r3, [r7, #16] + 8003778: 4b23 ldr r3, [pc, #140] @ (8003808 ) + 800377a: 685b ldr r3, [r3, #4] + 800377c: 613b str r3, [r7, #16] temp &= ~(iocurrent); - 8003746: 68fb ldr r3, [r7, #12] - 8003748: 43db mvns r3, r3 - 800374a: 693a ldr r2, [r7, #16] - 800374c: 4013 ands r3, r2 - 800374e: 613b str r3, [r7, #16] + 800377e: 68fb ldr r3, [r7, #12] + 8003780: 43db mvns r3, r3 + 8003782: 693a ldr r2, [r7, #16] + 8003784: 4013 ands r3, r2 + 8003786: 613b str r3, [r7, #16] if((GPIO_Init->Mode & EXTI_EVT) != 0x00u) - 8003750: 683b ldr r3, [r7, #0] - 8003752: 685b ldr r3, [r3, #4] - 8003754: f403 3300 and.w r3, r3, #131072 @ 0x20000 - 8003758: 2b00 cmp r3, #0 - 800375a: d003 beq.n 8003764 + 8003788: 683b ldr r3, [r7, #0] + 800378a: 685b ldr r3, [r3, #4] + 800378c: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 8003790: 2b00 cmp r3, #0 + 8003792: d003 beq.n 800379c { temp |= iocurrent; - 800375c: 693a ldr r2, [r7, #16] - 800375e: 68fb ldr r3, [r7, #12] - 8003760: 4313 orrs r3, r2 - 8003762: 613b str r3, [r7, #16] + 8003794: 693a ldr r2, [r7, #16] + 8003796: 68fb ldr r3, [r7, #12] + 8003798: 4313 orrs r3, r2 + 800379a: 613b str r3, [r7, #16] } EXTI->EMR = temp; - 8003764: 4a1a ldr r2, [pc, #104] @ (80037d0 ) - 8003766: 693b ldr r3, [r7, #16] - 8003768: 6053 str r3, [r2, #4] + 800379c: 4a1a ldr r2, [pc, #104] @ (8003808 ) + 800379e: 693b ldr r3, [r7, #16] + 80037a0: 6053 str r3, [r2, #4] /* Clear EXTI line configuration */ temp = EXTI->IMR; - 800376a: 4b19 ldr r3, [pc, #100] @ (80037d0 ) - 800376c: 681b ldr r3, [r3, #0] - 800376e: 613b str r3, [r7, #16] + 80037a2: 4b19 ldr r3, [pc, #100] @ (8003808 ) + 80037a4: 681b ldr r3, [r3, #0] + 80037a6: 613b str r3, [r7, #16] temp &= ~(iocurrent); - 8003770: 68fb ldr r3, [r7, #12] - 8003772: 43db mvns r3, r3 - 8003774: 693a ldr r2, [r7, #16] - 8003776: 4013 ands r3, r2 - 8003778: 613b str r3, [r7, #16] + 80037a8: 68fb ldr r3, [r7, #12] + 80037aa: 43db mvns r3, r3 + 80037ac: 693a ldr r2, [r7, #16] + 80037ae: 4013 ands r3, r2 + 80037b0: 613b str r3, [r7, #16] if((GPIO_Init->Mode & EXTI_IT) != 0x00u) - 800377a: 683b ldr r3, [r7, #0] - 800377c: 685b ldr r3, [r3, #4] - 800377e: f403 3380 and.w r3, r3, #65536 @ 0x10000 - 8003782: 2b00 cmp r3, #0 - 8003784: d003 beq.n 800378e + 80037b2: 683b ldr r3, [r7, #0] + 80037b4: 685b ldr r3, [r3, #4] + 80037b6: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 80037ba: 2b00 cmp r3, #0 + 80037bc: d003 beq.n 80037c6 { temp |= iocurrent; - 8003786: 693a ldr r2, [r7, #16] - 8003788: 68fb ldr r3, [r7, #12] - 800378a: 4313 orrs r3, r2 - 800378c: 613b str r3, [r7, #16] + 80037be: 693a ldr r2, [r7, #16] + 80037c0: 68fb ldr r3, [r7, #12] + 80037c2: 4313 orrs r3, r2 + 80037c4: 613b str r3, [r7, #16] } EXTI->IMR = temp; - 800378e: 4a10 ldr r2, [pc, #64] @ (80037d0 ) - 8003790: 693b ldr r3, [r7, #16] - 8003792: 6013 str r3, [r2, #0] + 80037c6: 4a10 ldr r2, [pc, #64] @ (8003808 ) + 80037c8: 693b ldr r3, [r7, #16] + 80037ca: 6013 str r3, [r2, #0] } } position++; - 8003794: 697b ldr r3, [r7, #20] - 8003796: 3301 adds r3, #1 - 8003798: 617b str r3, [r7, #20] + 80037cc: 697b ldr r3, [r7, #20] + 80037ce: 3301 adds r3, #1 + 80037d0: 617b str r3, [r7, #20] while (((GPIO_Init->Pin) >> position) != 0x00u) - 800379a: 683b ldr r3, [r7, #0] - 800379c: 681a ldr r2, [r3, #0] - 800379e: 697b ldr r3, [r7, #20] - 80037a0: fa22 f303 lsr.w r3, r2, r3 - 80037a4: 2b00 cmp r3, #0 - 80037a6: f47f aea3 bne.w 80034f0 + 80037d2: 683b ldr r3, [r7, #0] + 80037d4: 681a ldr r2, [r3, #0] + 80037d6: 697b ldr r3, [r7, #20] + 80037d8: fa22 f303 lsr.w r3, r2, r3 + 80037dc: 2b00 cmp r3, #0 + 80037de: f47f aea3 bne.w 8003528 } } - 80037aa: bf00 nop - 80037ac: bf00 nop - 80037ae: 371c adds r7, #28 - 80037b0: 46bd mov sp, r7 - 80037b2: f85d 7b04 ldr.w r7, [sp], #4 - 80037b6: 4770 bx lr - 80037b8: 40021000 .word 0x40021000 - 80037bc: 40010000 .word 0x40010000 - 80037c0: 48000400 .word 0x48000400 - 80037c4: 48000800 .word 0x48000800 - 80037c8: 48000c00 .word 0x48000c00 - 80037cc: 48001000 .word 0x48001000 - 80037d0: 40010400 .word 0x40010400 + 80037e2: bf00 nop + 80037e4: bf00 nop + 80037e6: 371c adds r7, #28 + 80037e8: 46bd mov sp, r7 + 80037ea: f85d 7b04 ldr.w r7, [sp], #4 + 80037ee: 4770 bx lr + 80037f0: 40021000 .word 0x40021000 + 80037f4: 40010000 .word 0x40010000 + 80037f8: 48000400 .word 0x48000400 + 80037fc: 48000800 .word 0x48000800 + 8003800: 48000c00 .word 0x48000c00 + 8003804: 48001000 .word 0x48001000 + 8003808: 40010400 .word 0x40010400 -080037d4 : +0800380c : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { - 80037d4: b480 push {r7} - 80037d6: b083 sub sp, #12 - 80037d8: af00 add r7, sp, #0 - 80037da: 6078 str r0, [r7, #4] - 80037dc: 460b mov r3, r1 - 80037de: 807b strh r3, [r7, #2] - 80037e0: 4613 mov r3, r2 - 80037e2: 707b strb r3, [r7, #1] + 800380c: b480 push {r7} + 800380e: b083 sub sp, #12 + 8003810: af00 add r7, sp, #0 + 8003812: 6078 str r0, [r7, #4] + 8003814: 460b mov r3, r1 + 8003816: 807b strh r3, [r7, #2] + 8003818: 4613 mov r3, r2 + 800381a: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if(PinState != GPIO_PIN_RESET) - 80037e4: 787b ldrb r3, [r7, #1] - 80037e6: 2b00 cmp r3, #0 - 80037e8: d003 beq.n 80037f2 + 800381c: 787b ldrb r3, [r7, #1] + 800381e: 2b00 cmp r3, #0 + 8003820: d003 beq.n 800382a { GPIOx->BSRR = (uint32_t)GPIO_Pin; - 80037ea: 887a ldrh r2, [r7, #2] - 80037ec: 687b ldr r3, [r7, #4] - 80037ee: 619a str r2, [r3, #24] + 8003822: 887a ldrh r2, [r7, #2] + 8003824: 687b ldr r3, [r7, #4] + 8003826: 619a str r2, [r3, #24] } else { GPIOx->BRR = (uint32_t)GPIO_Pin; } } - 80037f0: e002 b.n 80037f8 + 8003828: e002 b.n 8003830 GPIOx->BRR = (uint32_t)GPIO_Pin; - 80037f2: 887a ldrh r2, [r7, #2] - 80037f4: 687b ldr r3, [r7, #4] - 80037f6: 629a str r2, [r3, #40] @ 0x28 + 800382a: 887a ldrh r2, [r7, #2] + 800382c: 687b ldr r3, [r7, #4] + 800382e: 629a str r2, [r3, #40] @ 0x28 } - 80037f8: bf00 nop - 80037fa: 370c adds r7, #12 - 80037fc: 46bd mov sp, r7 - 80037fe: f85d 7b04 ldr.w r7, [sp], #4 - 8003802: 4770 bx lr + 8003830: bf00 nop + 8003832: 370c adds r7, #12 + 8003834: 46bd mov sp, r7 + 8003836: f85d 7b04 ldr.w r7, [sp], #4 + 800383a: 4770 bx lr -08003804 : +0800383c : * supported by this macro. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { - 8003804: b580 push {r7, lr} - 8003806: f5ad 7d00 sub.w sp, sp, #512 @ 0x200 - 800380a: af00 add r7, sp, #0 - 800380c: f507 7300 add.w r3, r7, #512 @ 0x200 - 8003810: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc - 8003814: 6018 str r0, [r3, #0] + 800383c: b580 push {r7, lr} + 800383e: f5ad 7d00 sub.w sp, sp, #512 @ 0x200 + 8003842: af00 add r7, sp, #0 + 8003844: f507 7300 add.w r3, r7, #512 @ 0x200 + 8003848: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc + 800384c: 6018 str r0, [r3, #0] #if defined(RCC_CFGR_PLLSRC_HSI_PREDIV) uint32_t pll_config2; #endif /* RCC_CFGR_PLLSRC_HSI_PREDIV */ /* Check Null pointer */ if(RCC_OscInitStruct == NULL) - 8003816: f507 7300 add.w r3, r7, #512 @ 0x200 - 800381a: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc - 800381e: 681b ldr r3, [r3, #0] - 8003820: 2b00 cmp r3, #0 - 8003822: d102 bne.n 800382a + 800384e: f507 7300 add.w r3, r7, #512 @ 0x200 + 8003852: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc + 8003856: 681b ldr r3, [r3, #0] + 8003858: 2b00 cmp r3, #0 + 800385a: d102 bne.n 8003862 { return HAL_ERROR; - 8003824: 2301 movs r3, #1 - 8003826: f001 b823 b.w 8004870 + 800385c: 2301 movs r3, #1 + 800385e: f001 b823 b.w 80048a8 /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) - 800382a: f507 7300 add.w r3, r7, #512 @ 0x200 - 800382e: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc - 8003832: 681b ldr r3, [r3, #0] - 8003834: 681b ldr r3, [r3, #0] - 8003836: f003 0301 and.w r3, r3, #1 - 800383a: 2b00 cmp r3, #0 - 800383c: f000 817d beq.w 8003b3a + 8003862: f507 7300 add.w r3, r7, #512 @ 0x200 + 8003866: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc + 800386a: 681b ldr r3, [r3, #0] + 800386c: 681b ldr r3, [r3, #0] + 800386e: f003 0301 and.w r3, r3, #1 + 8003872: 2b00 cmp r3, #0 + 8003874: f000 817d beq.w 8003b72 { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) - 8003840: 4bbc ldr r3, [pc, #752] @ (8003b34 ) - 8003842: 685b ldr r3, [r3, #4] - 8003844: f003 030c and.w r3, r3, #12 - 8003848: 2b04 cmp r3, #4 - 800384a: d00c beq.n 8003866 + 8003878: 4bbc ldr r3, [pc, #752] @ (8003b6c ) + 800387a: 685b ldr r3, [r3, #4] + 800387c: f003 030c and.w r3, r3, #12 + 8003880: 2b04 cmp r3, #4 + 8003882: d00c beq.n 800389e || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) - 800384c: 4bb9 ldr r3, [pc, #740] @ (8003b34 ) - 800384e: 685b ldr r3, [r3, #4] - 8003850: f003 030c and.w r3, r3, #12 - 8003854: 2b08 cmp r3, #8 - 8003856: d15c bne.n 8003912 - 8003858: 4bb6 ldr r3, [pc, #728] @ (8003b34 ) - 800385a: 685b ldr r3, [r3, #4] - 800385c: f403 3380 and.w r3, r3, #65536 @ 0x10000 - 8003860: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 - 8003864: d155 bne.n 8003912 - 8003866: f44f 3300 mov.w r3, #131072 @ 0x20000 - 800386a: f8c7 31f0 str.w r3, [r7, #496] @ 0x1f0 + 8003884: 4bb9 ldr r3, [pc, #740] @ (8003b6c ) + 8003886: 685b ldr r3, [r3, #4] + 8003888: f003 030c and.w r3, r3, #12 + 800388c: 2b08 cmp r3, #8 + 800388e: d15c bne.n 800394a + 8003890: 4bb6 ldr r3, [pc, #728] @ (8003b6c ) + 8003892: 685b ldr r3, [r3, #4] + 8003894: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 8003898: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 + 800389c: d155 bne.n 800394a + 800389e: f44f 3300 mov.w r3, #131072 @ 0x20000 + 80038a2: f8c7 31f0 str.w r3, [r7, #496] @ 0x1f0 uint32_t result; #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 800386e: f8d7 31f0 ldr.w r3, [r7, #496] @ 0x1f0 - 8003872: fa93 f3a3 rbit r3, r3 - 8003876: f8c7 31ec str.w r3, [r7, #492] @ 0x1ec + 80038a6: f8d7 31f0 ldr.w r3, [r7, #496] @ 0x1f0 + 80038aa: fa93 f3a3 rbit r3, r3 + 80038ae: f8c7 31ec str.w r3, [r7, #492] @ 0x1ec result |= value & 1U; s--; } result <<= s; /* shift when v's highest bits are zero */ #endif return result; - 800387a: f8d7 31ec ldr.w r3, [r7, #492] @ 0x1ec + 80038b2: f8d7 31ec ldr.w r3, [r7, #492] @ 0x1ec { if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) - 800387e: fab3 f383 clz r3, r3 - 8003882: b2db uxtb r3, r3 - 8003884: 095b lsrs r3, r3, #5 - 8003886: b2db uxtb r3, r3 - 8003888: f043 0301 orr.w r3, r3, #1 - 800388c: b2db uxtb r3, r3 - 800388e: 2b01 cmp r3, #1 - 8003890: d102 bne.n 8003898 - 8003892: 4ba8 ldr r3, [pc, #672] @ (8003b34 ) - 8003894: 681b ldr r3, [r3, #0] - 8003896: e015 b.n 80038c4 - 8003898: f44f 3300 mov.w r3, #131072 @ 0x20000 - 800389c: f8c7 31e8 str.w r3, [r7, #488] @ 0x1e8 + 80038b6: fab3 f383 clz r3, r3 + 80038ba: b2db uxtb r3, r3 + 80038bc: 095b lsrs r3, r3, #5 + 80038be: b2db uxtb r3, r3 + 80038c0: f043 0301 orr.w r3, r3, #1 + 80038c4: b2db uxtb r3, r3 + 80038c6: 2b01 cmp r3, #1 + 80038c8: d102 bne.n 80038d0 + 80038ca: 4ba8 ldr r3, [pc, #672] @ (8003b6c ) + 80038cc: 681b ldr r3, [r3, #0] + 80038ce: e015 b.n 80038fc + 80038d0: f44f 3300 mov.w r3, #131072 @ 0x20000 + 80038d4: f8c7 31e8 str.w r3, [r7, #488] @ 0x1e8 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 80038a0: f8d7 31e8 ldr.w r3, [r7, #488] @ 0x1e8 - 80038a4: fa93 f3a3 rbit r3, r3 - 80038a8: f8c7 31e4 str.w r3, [r7, #484] @ 0x1e4 - 80038ac: f44f 3300 mov.w r3, #131072 @ 0x20000 - 80038b0: f8c7 31e0 str.w r3, [r7, #480] @ 0x1e0 - 80038b4: f8d7 31e0 ldr.w r3, [r7, #480] @ 0x1e0 - 80038b8: fa93 f3a3 rbit r3, r3 - 80038bc: f8c7 31dc str.w r3, [r7, #476] @ 0x1dc - 80038c0: 4b9c ldr r3, [pc, #624] @ (8003b34 ) - 80038c2: 6a5b ldr r3, [r3, #36] @ 0x24 - 80038c4: f44f 3200 mov.w r2, #131072 @ 0x20000 - 80038c8: f8c7 21d8 str.w r2, [r7, #472] @ 0x1d8 - 80038cc: f8d7 21d8 ldr.w r2, [r7, #472] @ 0x1d8 - 80038d0: fa92 f2a2 rbit r2, r2 - 80038d4: f8c7 21d4 str.w r2, [r7, #468] @ 0x1d4 + 80038d8: f8d7 31e8 ldr.w r3, [r7, #488] @ 0x1e8 + 80038dc: fa93 f3a3 rbit r3, r3 + 80038e0: f8c7 31e4 str.w r3, [r7, #484] @ 0x1e4 + 80038e4: f44f 3300 mov.w r3, #131072 @ 0x20000 + 80038e8: f8c7 31e0 str.w r3, [r7, #480] @ 0x1e0 + 80038ec: f8d7 31e0 ldr.w r3, [r7, #480] @ 0x1e0 + 80038f0: fa93 f3a3 rbit r3, r3 + 80038f4: f8c7 31dc str.w r3, [r7, #476] @ 0x1dc + 80038f8: 4b9c ldr r3, [pc, #624] @ (8003b6c ) + 80038fa: 6a5b ldr r3, [r3, #36] @ 0x24 + 80038fc: f44f 3200 mov.w r2, #131072 @ 0x20000 + 8003900: f8c7 21d8 str.w r2, [r7, #472] @ 0x1d8 + 8003904: f8d7 21d8 ldr.w r2, [r7, #472] @ 0x1d8 + 8003908: fa92 f2a2 rbit r2, r2 + 800390c: f8c7 21d4 str.w r2, [r7, #468] @ 0x1d4 return result; - 80038d8: f8d7 21d4 ldr.w r2, [r7, #468] @ 0x1d4 - 80038dc: fab2 f282 clz r2, r2 - 80038e0: b2d2 uxtb r2, r2 - 80038e2: f042 0220 orr.w r2, r2, #32 - 80038e6: b2d2 uxtb r2, r2 - 80038e8: f002 021f and.w r2, r2, #31 - 80038ec: 2101 movs r1, #1 - 80038ee: fa01 f202 lsl.w r2, r1, r2 - 80038f2: 4013 ands r3, r2 - 80038f4: 2b00 cmp r3, #0 - 80038f6: f000 811f beq.w 8003b38 - 80038fa: f507 7300 add.w r3, r7, #512 @ 0x200 - 80038fe: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc - 8003902: 681b ldr r3, [r3, #0] - 8003904: 685b ldr r3, [r3, #4] - 8003906: 2b00 cmp r3, #0 - 8003908: f040 8116 bne.w 8003b38 + 8003910: f8d7 21d4 ldr.w r2, [r7, #468] @ 0x1d4 + 8003914: fab2 f282 clz r2, r2 + 8003918: b2d2 uxtb r2, r2 + 800391a: f042 0220 orr.w r2, r2, #32 + 800391e: b2d2 uxtb r2, r2 + 8003920: f002 021f and.w r2, r2, #31 + 8003924: 2101 movs r1, #1 + 8003926: fa01 f202 lsl.w r2, r1, r2 + 800392a: 4013 ands r3, r2 + 800392c: 2b00 cmp r3, #0 + 800392e: f000 811f beq.w 8003b70 + 8003932: f507 7300 add.w r3, r7, #512 @ 0x200 + 8003936: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc + 800393a: 681b ldr r3, [r3, #0] + 800393c: 685b ldr r3, [r3, #4] + 800393e: 2b00 cmp r3, #0 + 8003940: f040 8116 bne.w 8003b70 { return HAL_ERROR; - 800390c: 2301 movs r3, #1 - 800390e: f000 bfaf b.w 8004870 + 8003944: 2301 movs r3, #1 + 8003946: f000 bfaf b.w 80048a8 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); - 8003912: f507 7300 add.w r3, r7, #512 @ 0x200 - 8003916: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc - 800391a: 681b ldr r3, [r3, #0] - 800391c: 685b ldr r3, [r3, #4] - 800391e: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 - 8003922: d106 bne.n 8003932 - 8003924: 4b83 ldr r3, [pc, #524] @ (8003b34 ) - 8003926: 681b ldr r3, [r3, #0] - 8003928: 4a82 ldr r2, [pc, #520] @ (8003b34 ) - 800392a: f443 3380 orr.w r3, r3, #65536 @ 0x10000 - 800392e: 6013 str r3, [r2, #0] - 8003930: e036 b.n 80039a0 - 8003932: f507 7300 add.w r3, r7, #512 @ 0x200 - 8003936: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc - 800393a: 681b ldr r3, [r3, #0] - 800393c: 685b ldr r3, [r3, #4] - 800393e: 2b00 cmp r3, #0 - 8003940: d10c bne.n 800395c - 8003942: 4b7c ldr r3, [pc, #496] @ (8003b34 ) - 8003944: 681b ldr r3, [r3, #0] - 8003946: 4a7b ldr r2, [pc, #492] @ (8003b34 ) - 8003948: f423 3380 bic.w r3, r3, #65536 @ 0x10000 - 800394c: 6013 str r3, [r2, #0] - 800394e: 4b79 ldr r3, [pc, #484] @ (8003b34 ) - 8003950: 681b ldr r3, [r3, #0] - 8003952: 4a78 ldr r2, [pc, #480] @ (8003b34 ) - 8003954: f423 2380 bic.w r3, r3, #262144 @ 0x40000 - 8003958: 6013 str r3, [r2, #0] - 800395a: e021 b.n 80039a0 - 800395c: f507 7300 add.w r3, r7, #512 @ 0x200 - 8003960: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc - 8003964: 681b ldr r3, [r3, #0] - 8003966: 685b ldr r3, [r3, #4] - 8003968: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 - 800396c: d10c bne.n 8003988 - 800396e: 4b71 ldr r3, [pc, #452] @ (8003b34 ) - 8003970: 681b ldr r3, [r3, #0] - 8003972: 4a70 ldr r2, [pc, #448] @ (8003b34 ) - 8003974: f443 2380 orr.w r3, r3, #262144 @ 0x40000 - 8003978: 6013 str r3, [r2, #0] - 800397a: 4b6e ldr r3, [pc, #440] @ (8003b34 ) + 800394a: f507 7300 add.w r3, r7, #512 @ 0x200 + 800394e: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc + 8003952: 681b ldr r3, [r3, #0] + 8003954: 685b ldr r3, [r3, #4] + 8003956: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 + 800395a: d106 bne.n 800396a + 800395c: 4b83 ldr r3, [pc, #524] @ (8003b6c ) + 800395e: 681b ldr r3, [r3, #0] + 8003960: 4a82 ldr r2, [pc, #520] @ (8003b6c ) + 8003962: f443 3380 orr.w r3, r3, #65536 @ 0x10000 + 8003966: 6013 str r3, [r2, #0] + 8003968: e036 b.n 80039d8 + 800396a: f507 7300 add.w r3, r7, #512 @ 0x200 + 800396e: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc + 8003972: 681b ldr r3, [r3, #0] + 8003974: 685b ldr r3, [r3, #4] + 8003976: 2b00 cmp r3, #0 + 8003978: d10c bne.n 8003994 + 800397a: 4b7c ldr r3, [pc, #496] @ (8003b6c ) 800397c: 681b ldr r3, [r3, #0] - 800397e: 4a6d ldr r2, [pc, #436] @ (8003b34 ) - 8003980: f443 3380 orr.w r3, r3, #65536 @ 0x10000 + 800397e: 4a7b ldr r2, [pc, #492] @ (8003b6c ) + 8003980: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8003984: 6013 str r3, [r2, #0] - 8003986: e00b b.n 80039a0 - 8003988: 4b6a ldr r3, [pc, #424] @ (8003b34 ) - 800398a: 681b ldr r3, [r3, #0] - 800398c: 4a69 ldr r2, [pc, #420] @ (8003b34 ) - 800398e: f423 3380 bic.w r3, r3, #65536 @ 0x10000 - 8003992: 6013 str r3, [r2, #0] - 8003994: 4b67 ldr r3, [pc, #412] @ (8003b34 ) - 8003996: 681b ldr r3, [r3, #0] - 8003998: 4a66 ldr r2, [pc, #408] @ (8003b34 ) - 800399a: f423 2380 bic.w r3, r3, #262144 @ 0x40000 - 800399e: 6013 str r3, [r2, #0] + 8003986: 4b79 ldr r3, [pc, #484] @ (8003b6c ) + 8003988: 681b ldr r3, [r3, #0] + 800398a: 4a78 ldr r2, [pc, #480] @ (8003b6c ) + 800398c: f423 2380 bic.w r3, r3, #262144 @ 0x40000 + 8003990: 6013 str r3, [r2, #0] + 8003992: e021 b.n 80039d8 + 8003994: f507 7300 add.w r3, r7, #512 @ 0x200 + 8003998: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc + 800399c: 681b ldr r3, [r3, #0] + 800399e: 685b ldr r3, [r3, #4] + 80039a0: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 + 80039a4: d10c bne.n 80039c0 + 80039a6: 4b71 ldr r3, [pc, #452] @ (8003b6c ) + 80039a8: 681b ldr r3, [r3, #0] + 80039aa: 4a70 ldr r2, [pc, #448] @ (8003b6c ) + 80039ac: f443 2380 orr.w r3, r3, #262144 @ 0x40000 + 80039b0: 6013 str r3, [r2, #0] + 80039b2: 4b6e ldr r3, [pc, #440] @ (8003b6c ) + 80039b4: 681b ldr r3, [r3, #0] + 80039b6: 4a6d ldr r2, [pc, #436] @ (8003b6c ) + 80039b8: f443 3380 orr.w r3, r3, #65536 @ 0x10000 + 80039bc: 6013 str r3, [r2, #0] + 80039be: e00b b.n 80039d8 + 80039c0: 4b6a ldr r3, [pc, #424] @ (8003b6c ) + 80039c2: 681b ldr r3, [r3, #0] + 80039c4: 4a69 ldr r2, [pc, #420] @ (8003b6c ) + 80039c6: f423 3380 bic.w r3, r3, #65536 @ 0x10000 + 80039ca: 6013 str r3, [r2, #0] + 80039cc: 4b67 ldr r3, [pc, #412] @ (8003b6c ) + 80039ce: 681b ldr r3, [r3, #0] + 80039d0: 4a66 ldr r2, [pc, #408] @ (8003b6c ) + 80039d2: f423 2380 bic.w r3, r3, #262144 @ 0x40000 + 80039d6: 6013 str r3, [r2, #0] #if defined(RCC_CFGR_PLLSRC_HSI_DIV2) /* Configure the HSE predivision factor --------------------------------*/ __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue); - 80039a0: 4b64 ldr r3, [pc, #400] @ (8003b34 ) - 80039a2: 6adb ldr r3, [r3, #44] @ 0x2c - 80039a4: f023 020f bic.w r2, r3, #15 - 80039a8: f507 7300 add.w r3, r7, #512 @ 0x200 - 80039ac: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc - 80039b0: 681b ldr r3, [r3, #0] - 80039b2: 689b ldr r3, [r3, #8] - 80039b4: 495f ldr r1, [pc, #380] @ (8003b34 ) - 80039b6: 4313 orrs r3, r2 - 80039b8: 62cb str r3, [r1, #44] @ 0x2c + 80039d8: 4b64 ldr r3, [pc, #400] @ (8003b6c ) + 80039da: 6adb ldr r3, [r3, #44] @ 0x2c + 80039dc: f023 020f bic.w r2, r3, #15 + 80039e0: f507 7300 add.w r3, r7, #512 @ 0x200 + 80039e4: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc + 80039e8: 681b ldr r3, [r3, #0] + 80039ea: 689b ldr r3, [r3, #8] + 80039ec: 495f ldr r1, [pc, #380] @ (8003b6c ) + 80039ee: 4313 orrs r3, r2 + 80039f0: 62cb str r3, [r1, #44] @ 0x2c #endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */ /* Check the HSE State */ if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) - 80039ba: f507 7300 add.w r3, r7, #512 @ 0x200 - 80039be: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc - 80039c2: 681b ldr r3, [r3, #0] - 80039c4: 685b ldr r3, [r3, #4] - 80039c6: 2b00 cmp r3, #0 - 80039c8: d059 beq.n 8003a7e + 80039f2: f507 7300 add.w r3, r7, #512 @ 0x200 + 80039f6: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc + 80039fa: 681b ldr r3, [r3, #0] + 80039fc: 685b ldr r3, [r3, #4] + 80039fe: 2b00 cmp r3, #0 + 8003a00: d059 beq.n 8003ab6 { /* Get Start Tick */ tickstart = HAL_GetTick(); - 80039ca: f7fd fd15 bl 80013f8 - 80039ce: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8 + 8003a02: f7fd fd15 bl 8001430 + 8003a06: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8 /* Wait till HSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) - 80039d2: e00a b.n 80039ea + 8003a0a: e00a b.n 8003a22 { if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) - 80039d4: f7fd fd10 bl 80013f8 - 80039d8: 4602 mov r2, r0 - 80039da: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8 - 80039de: 1ad3 subs r3, r2, r3 - 80039e0: 2b64 cmp r3, #100 @ 0x64 - 80039e2: d902 bls.n 80039ea + 8003a0c: f7fd fd10 bl 8001430 + 8003a10: 4602 mov r2, r0 + 8003a12: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8 + 8003a16: 1ad3 subs r3, r2, r3 + 8003a18: 2b64 cmp r3, #100 @ 0x64 + 8003a1a: d902 bls.n 8003a22 { return HAL_TIMEOUT; - 80039e4: 2303 movs r3, #3 - 80039e6: f000 bf43 b.w 8004870 - 80039ea: f44f 3300 mov.w r3, #131072 @ 0x20000 - 80039ee: f8c7 31d0 str.w r3, [r7, #464] @ 0x1d0 + 8003a1c: 2303 movs r3, #3 + 8003a1e: f000 bf43 b.w 80048a8 + 8003a22: f44f 3300 mov.w r3, #131072 @ 0x20000 + 8003a26: f8c7 31d0 str.w r3, [r7, #464] @ 0x1d0 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 80039f2: f8d7 31d0 ldr.w r3, [r7, #464] @ 0x1d0 - 80039f6: fa93 f3a3 rbit r3, r3 - 80039fa: f8c7 31cc str.w r3, [r7, #460] @ 0x1cc + 8003a2a: f8d7 31d0 ldr.w r3, [r7, #464] @ 0x1d0 + 8003a2e: fa93 f3a3 rbit r3, r3 + 8003a32: f8c7 31cc str.w r3, [r7, #460] @ 0x1cc return result; - 80039fe: f8d7 31cc ldr.w r3, [r7, #460] @ 0x1cc + 8003a36: f8d7 31cc ldr.w r3, [r7, #460] @ 0x1cc while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) - 8003a02: fab3 f383 clz r3, r3 - 8003a06: b2db uxtb r3, r3 - 8003a08: 095b lsrs r3, r3, #5 - 8003a0a: b2db uxtb r3, r3 - 8003a0c: f043 0301 orr.w r3, r3, #1 - 8003a10: b2db uxtb r3, r3 - 8003a12: 2b01 cmp r3, #1 - 8003a14: d102 bne.n 8003a1c - 8003a16: 4b47 ldr r3, [pc, #284] @ (8003b34 ) - 8003a18: 681b ldr r3, [r3, #0] - 8003a1a: e015 b.n 8003a48 - 8003a1c: f44f 3300 mov.w r3, #131072 @ 0x20000 - 8003a20: f8c7 31c8 str.w r3, [r7, #456] @ 0x1c8 + 8003a3a: fab3 f383 clz r3, r3 + 8003a3e: b2db uxtb r3, r3 + 8003a40: 095b lsrs r3, r3, #5 + 8003a42: b2db uxtb r3, r3 + 8003a44: f043 0301 orr.w r3, r3, #1 + 8003a48: b2db uxtb r3, r3 + 8003a4a: 2b01 cmp r3, #1 + 8003a4c: d102 bne.n 8003a54 + 8003a4e: 4b47 ldr r3, [pc, #284] @ (8003b6c ) + 8003a50: 681b ldr r3, [r3, #0] + 8003a52: e015 b.n 8003a80 + 8003a54: f44f 3300 mov.w r3, #131072 @ 0x20000 + 8003a58: f8c7 31c8 str.w r3, [r7, #456] @ 0x1c8 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8003a24: f8d7 31c8 ldr.w r3, [r7, #456] @ 0x1c8 - 8003a28: fa93 f3a3 rbit r3, r3 - 8003a2c: f8c7 31c4 str.w r3, [r7, #452] @ 0x1c4 - 8003a30: f44f 3300 mov.w r3, #131072 @ 0x20000 - 8003a34: f8c7 31c0 str.w r3, [r7, #448] @ 0x1c0 - 8003a38: f8d7 31c0 ldr.w r3, [r7, #448] @ 0x1c0 - 8003a3c: fa93 f3a3 rbit r3, r3 - 8003a40: f8c7 31bc str.w r3, [r7, #444] @ 0x1bc - 8003a44: 4b3b ldr r3, [pc, #236] @ (8003b34 ) - 8003a46: 6a5b ldr r3, [r3, #36] @ 0x24 - 8003a48: f44f 3200 mov.w r2, #131072 @ 0x20000 - 8003a4c: f8c7 21b8 str.w r2, [r7, #440] @ 0x1b8 - 8003a50: f8d7 21b8 ldr.w r2, [r7, #440] @ 0x1b8 - 8003a54: fa92 f2a2 rbit r2, r2 - 8003a58: f8c7 21b4 str.w r2, [r7, #436] @ 0x1b4 + 8003a5c: f8d7 31c8 ldr.w r3, [r7, #456] @ 0x1c8 + 8003a60: fa93 f3a3 rbit r3, r3 + 8003a64: f8c7 31c4 str.w r3, [r7, #452] @ 0x1c4 + 8003a68: f44f 3300 mov.w r3, #131072 @ 0x20000 + 8003a6c: f8c7 31c0 str.w r3, [r7, #448] @ 0x1c0 + 8003a70: f8d7 31c0 ldr.w r3, [r7, #448] @ 0x1c0 + 8003a74: fa93 f3a3 rbit r3, r3 + 8003a78: f8c7 31bc str.w r3, [r7, #444] @ 0x1bc + 8003a7c: 4b3b ldr r3, [pc, #236] @ (8003b6c ) + 8003a7e: 6a5b ldr r3, [r3, #36] @ 0x24 + 8003a80: f44f 3200 mov.w r2, #131072 @ 0x20000 + 8003a84: f8c7 21b8 str.w r2, [r7, #440] @ 0x1b8 + 8003a88: f8d7 21b8 ldr.w r2, [r7, #440] @ 0x1b8 + 8003a8c: fa92 f2a2 rbit r2, r2 + 8003a90: f8c7 21b4 str.w r2, [r7, #436] @ 0x1b4 return result; - 8003a5c: f8d7 21b4 ldr.w r2, [r7, #436] @ 0x1b4 - 8003a60: fab2 f282 clz r2, r2 - 8003a64: b2d2 uxtb r2, r2 - 8003a66: f042 0220 orr.w r2, r2, #32 - 8003a6a: b2d2 uxtb r2, r2 - 8003a6c: f002 021f and.w r2, r2, #31 - 8003a70: 2101 movs r1, #1 - 8003a72: fa01 f202 lsl.w r2, r1, r2 - 8003a76: 4013 ands r3, r2 - 8003a78: 2b00 cmp r3, #0 - 8003a7a: d0ab beq.n 80039d4 - 8003a7c: e05d b.n 8003b3a + 8003a94: f8d7 21b4 ldr.w r2, [r7, #436] @ 0x1b4 + 8003a98: fab2 f282 clz r2, r2 + 8003a9c: b2d2 uxtb r2, r2 + 8003a9e: f042 0220 orr.w r2, r2, #32 + 8003aa2: b2d2 uxtb r2, r2 + 8003aa4: f002 021f and.w r2, r2, #31 + 8003aa8: 2101 movs r1, #1 + 8003aaa: fa01 f202 lsl.w r2, r1, r2 + 8003aae: 4013 ands r3, r2 + 8003ab0: 2b00 cmp r3, #0 + 8003ab2: d0ab beq.n 8003a0c + 8003ab4: e05d b.n 8003b72 } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); - 8003a7e: f7fd fcbb bl 80013f8 - 8003a82: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8 + 8003ab6: f7fd fcbb bl 8001430 + 8003aba: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8 /* Wait till HSE is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) - 8003a86: e00a b.n 8003a9e + 8003abe: e00a b.n 8003ad6 { if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) - 8003a88: f7fd fcb6 bl 80013f8 - 8003a8c: 4602 mov r2, r0 - 8003a8e: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8 - 8003a92: 1ad3 subs r3, r2, r3 - 8003a94: 2b64 cmp r3, #100 @ 0x64 - 8003a96: d902 bls.n 8003a9e + 8003ac0: f7fd fcb6 bl 8001430 + 8003ac4: 4602 mov r2, r0 + 8003ac6: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8 + 8003aca: 1ad3 subs r3, r2, r3 + 8003acc: 2b64 cmp r3, #100 @ 0x64 + 8003ace: d902 bls.n 8003ad6 { return HAL_TIMEOUT; - 8003a98: 2303 movs r3, #3 - 8003a9a: f000 bee9 b.w 8004870 - 8003a9e: f44f 3300 mov.w r3, #131072 @ 0x20000 - 8003aa2: f8c7 31b0 str.w r3, [r7, #432] @ 0x1b0 + 8003ad0: 2303 movs r3, #3 + 8003ad2: f000 bee9 b.w 80048a8 + 8003ad6: f44f 3300 mov.w r3, #131072 @ 0x20000 + 8003ada: f8c7 31b0 str.w r3, [r7, #432] @ 0x1b0 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8003aa6: f8d7 31b0 ldr.w r3, [r7, #432] @ 0x1b0 - 8003aaa: fa93 f3a3 rbit r3, r3 - 8003aae: f8c7 31ac str.w r3, [r7, #428] @ 0x1ac + 8003ade: f8d7 31b0 ldr.w r3, [r7, #432] @ 0x1b0 + 8003ae2: fa93 f3a3 rbit r3, r3 + 8003ae6: f8c7 31ac str.w r3, [r7, #428] @ 0x1ac return result; - 8003ab2: f8d7 31ac ldr.w r3, [r7, #428] @ 0x1ac + 8003aea: f8d7 31ac ldr.w r3, [r7, #428] @ 0x1ac while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) - 8003ab6: fab3 f383 clz r3, r3 - 8003aba: b2db uxtb r3, r3 - 8003abc: 095b lsrs r3, r3, #5 - 8003abe: b2db uxtb r3, r3 - 8003ac0: f043 0301 orr.w r3, r3, #1 - 8003ac4: b2db uxtb r3, r3 - 8003ac6: 2b01 cmp r3, #1 - 8003ac8: d102 bne.n 8003ad0 - 8003aca: 4b1a ldr r3, [pc, #104] @ (8003b34 ) - 8003acc: 681b ldr r3, [r3, #0] - 8003ace: e015 b.n 8003afc - 8003ad0: f44f 3300 mov.w r3, #131072 @ 0x20000 - 8003ad4: f8c7 31a8 str.w r3, [r7, #424] @ 0x1a8 + 8003aee: fab3 f383 clz r3, r3 + 8003af2: b2db uxtb r3, r3 + 8003af4: 095b lsrs r3, r3, #5 + 8003af6: b2db uxtb r3, r3 + 8003af8: f043 0301 orr.w r3, r3, #1 + 8003afc: b2db uxtb r3, r3 + 8003afe: 2b01 cmp r3, #1 + 8003b00: d102 bne.n 8003b08 + 8003b02: 4b1a ldr r3, [pc, #104] @ (8003b6c ) + 8003b04: 681b ldr r3, [r3, #0] + 8003b06: e015 b.n 8003b34 + 8003b08: f44f 3300 mov.w r3, #131072 @ 0x20000 + 8003b0c: f8c7 31a8 str.w r3, [r7, #424] @ 0x1a8 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8003ad8: f8d7 31a8 ldr.w r3, [r7, #424] @ 0x1a8 - 8003adc: fa93 f3a3 rbit r3, r3 - 8003ae0: f8c7 31a4 str.w r3, [r7, #420] @ 0x1a4 - 8003ae4: f44f 3300 mov.w r3, #131072 @ 0x20000 - 8003ae8: f8c7 31a0 str.w r3, [r7, #416] @ 0x1a0 - 8003aec: f8d7 31a0 ldr.w r3, [r7, #416] @ 0x1a0 - 8003af0: fa93 f3a3 rbit r3, r3 - 8003af4: f8c7 319c str.w r3, [r7, #412] @ 0x19c - 8003af8: 4b0e ldr r3, [pc, #56] @ (8003b34 ) - 8003afa: 6a5b ldr r3, [r3, #36] @ 0x24 - 8003afc: f44f 3200 mov.w r2, #131072 @ 0x20000 - 8003b00: f8c7 2198 str.w r2, [r7, #408] @ 0x198 - 8003b04: f8d7 2198 ldr.w r2, [r7, #408] @ 0x198 - 8003b08: fa92 f2a2 rbit r2, r2 - 8003b0c: f8c7 2194 str.w r2, [r7, #404] @ 0x194 + 8003b10: f8d7 31a8 ldr.w r3, [r7, #424] @ 0x1a8 + 8003b14: fa93 f3a3 rbit r3, r3 + 8003b18: f8c7 31a4 str.w r3, [r7, #420] @ 0x1a4 + 8003b1c: f44f 3300 mov.w r3, #131072 @ 0x20000 + 8003b20: f8c7 31a0 str.w r3, [r7, #416] @ 0x1a0 + 8003b24: f8d7 31a0 ldr.w r3, [r7, #416] @ 0x1a0 + 8003b28: fa93 f3a3 rbit r3, r3 + 8003b2c: f8c7 319c str.w r3, [r7, #412] @ 0x19c + 8003b30: 4b0e ldr r3, [pc, #56] @ (8003b6c ) + 8003b32: 6a5b ldr r3, [r3, #36] @ 0x24 + 8003b34: f44f 3200 mov.w r2, #131072 @ 0x20000 + 8003b38: f8c7 2198 str.w r2, [r7, #408] @ 0x198 + 8003b3c: f8d7 2198 ldr.w r2, [r7, #408] @ 0x198 + 8003b40: fa92 f2a2 rbit r2, r2 + 8003b44: f8c7 2194 str.w r2, [r7, #404] @ 0x194 return result; - 8003b10: f8d7 2194 ldr.w r2, [r7, #404] @ 0x194 - 8003b14: fab2 f282 clz r2, r2 - 8003b18: b2d2 uxtb r2, r2 - 8003b1a: f042 0220 orr.w r2, r2, #32 - 8003b1e: b2d2 uxtb r2, r2 - 8003b20: f002 021f and.w r2, r2, #31 - 8003b24: 2101 movs r1, #1 - 8003b26: fa01 f202 lsl.w r2, r1, r2 - 8003b2a: 4013 ands r3, r2 - 8003b2c: 2b00 cmp r3, #0 - 8003b2e: d1ab bne.n 8003a88 - 8003b30: e003 b.n 8003b3a - 8003b32: bf00 nop - 8003b34: 40021000 .word 0x40021000 + 8003b48: f8d7 2194 ldr.w r2, [r7, #404] @ 0x194 + 8003b4c: fab2 f282 clz r2, r2 + 8003b50: b2d2 uxtb r2, r2 + 8003b52: f042 0220 orr.w r2, r2, #32 + 8003b56: b2d2 uxtb r2, r2 + 8003b58: f002 021f and.w r2, r2, #31 + 8003b5c: 2101 movs r1, #1 + 8003b5e: fa01 f202 lsl.w r2, r1, r2 + 8003b62: 4013 ands r3, r2 + 8003b64: 2b00 cmp r3, #0 + 8003b66: d1ab bne.n 8003ac0 + 8003b68: e003 b.n 8003b72 + 8003b6a: bf00 nop + 8003b6c: 40021000 .word 0x40021000 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) - 8003b38: bf00 nop + 8003b70: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) - 8003b3a: f507 7300 add.w r3, r7, #512 @ 0x200 - 8003b3e: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc - 8003b42: 681b ldr r3, [r3, #0] - 8003b44: 681b ldr r3, [r3, #0] - 8003b46: f003 0302 and.w r3, r3, #2 - 8003b4a: 2b00 cmp r3, #0 - 8003b4c: f000 817d beq.w 8003e4a + 8003b72: f507 7300 add.w r3, r7, #512 @ 0x200 + 8003b76: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc + 8003b7a: 681b ldr r3, [r3, #0] + 8003b7c: 681b ldr r3, [r3, #0] + 8003b7e: f003 0302 and.w r3, r3, #2 + 8003b82: 2b00 cmp r3, #0 + 8003b84: f000 817d beq.w 8003e82 /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) - 8003b50: 4ba6 ldr r3, [pc, #664] @ (8003dec ) - 8003b52: 685b ldr r3, [r3, #4] - 8003b54: f003 030c and.w r3, r3, #12 - 8003b58: 2b00 cmp r3, #0 - 8003b5a: d00b beq.n 8003b74 + 8003b88: 4ba6 ldr r3, [pc, #664] @ (8003e24 ) + 8003b8a: 685b ldr r3, [r3, #4] + 8003b8c: f003 030c and.w r3, r3, #12 + 8003b90: 2b00 cmp r3, #0 + 8003b92: d00b beq.n 8003bac || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI))) - 8003b5c: 4ba3 ldr r3, [pc, #652] @ (8003dec ) - 8003b5e: 685b ldr r3, [r3, #4] - 8003b60: f003 030c and.w r3, r3, #12 - 8003b64: 2b08 cmp r3, #8 - 8003b66: d172 bne.n 8003c4e - 8003b68: 4ba0 ldr r3, [pc, #640] @ (8003dec ) - 8003b6a: 685b ldr r3, [r3, #4] - 8003b6c: f403 3380 and.w r3, r3, #65536 @ 0x10000 - 8003b70: 2b00 cmp r3, #0 - 8003b72: d16c bne.n 8003c4e - 8003b74: 2302 movs r3, #2 - 8003b76: f8c7 3190 str.w r3, [r7, #400] @ 0x190 + 8003b94: 4ba3 ldr r3, [pc, #652] @ (8003e24 ) + 8003b96: 685b ldr r3, [r3, #4] + 8003b98: f003 030c and.w r3, r3, #12 + 8003b9c: 2b08 cmp r3, #8 + 8003b9e: d172 bne.n 8003c86 + 8003ba0: 4ba0 ldr r3, [pc, #640] @ (8003e24 ) + 8003ba2: 685b ldr r3, [r3, #4] + 8003ba4: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 8003ba8: 2b00 cmp r3, #0 + 8003baa: d16c bne.n 8003c86 + 8003bac: 2302 movs r3, #2 + 8003bae: f8c7 3190 str.w r3, [r7, #400] @ 0x190 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8003b7a: f8d7 3190 ldr.w r3, [r7, #400] @ 0x190 - 8003b7e: fa93 f3a3 rbit r3, r3 - 8003b82: f8c7 318c str.w r3, [r7, #396] @ 0x18c + 8003bb2: f8d7 3190 ldr.w r3, [r7, #400] @ 0x190 + 8003bb6: fa93 f3a3 rbit r3, r3 + 8003bba: f8c7 318c str.w r3, [r7, #396] @ 0x18c return result; - 8003b86: f8d7 318c ldr.w r3, [r7, #396] @ 0x18c + 8003bbe: f8d7 318c ldr.w r3, [r7, #396] @ 0x18c { /* When HSI is used as system clock it will not disabled */ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) - 8003b8a: fab3 f383 clz r3, r3 - 8003b8e: b2db uxtb r3, r3 - 8003b90: 095b lsrs r3, r3, #5 - 8003b92: b2db uxtb r3, r3 - 8003b94: f043 0301 orr.w r3, r3, #1 - 8003b98: b2db uxtb r3, r3 - 8003b9a: 2b01 cmp r3, #1 - 8003b9c: d102 bne.n 8003ba4 - 8003b9e: 4b93 ldr r3, [pc, #588] @ (8003dec ) - 8003ba0: 681b ldr r3, [r3, #0] - 8003ba2: e013 b.n 8003bcc - 8003ba4: 2302 movs r3, #2 - 8003ba6: f8c7 3188 str.w r3, [r7, #392] @ 0x188 + 8003bc2: fab3 f383 clz r3, r3 + 8003bc6: b2db uxtb r3, r3 + 8003bc8: 095b lsrs r3, r3, #5 + 8003bca: b2db uxtb r3, r3 + 8003bcc: f043 0301 orr.w r3, r3, #1 + 8003bd0: b2db uxtb r3, r3 + 8003bd2: 2b01 cmp r3, #1 + 8003bd4: d102 bne.n 8003bdc + 8003bd6: 4b93 ldr r3, [pc, #588] @ (8003e24 ) + 8003bd8: 681b ldr r3, [r3, #0] + 8003bda: e013 b.n 8003c04 + 8003bdc: 2302 movs r3, #2 + 8003bde: f8c7 3188 str.w r3, [r7, #392] @ 0x188 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8003baa: f8d7 3188 ldr.w r3, [r7, #392] @ 0x188 - 8003bae: fa93 f3a3 rbit r3, r3 - 8003bb2: f8c7 3184 str.w r3, [r7, #388] @ 0x184 - 8003bb6: 2302 movs r3, #2 - 8003bb8: f8c7 3180 str.w r3, [r7, #384] @ 0x180 - 8003bbc: f8d7 3180 ldr.w r3, [r7, #384] @ 0x180 - 8003bc0: fa93 f3a3 rbit r3, r3 - 8003bc4: f8c7 317c str.w r3, [r7, #380] @ 0x17c - 8003bc8: 4b88 ldr r3, [pc, #544] @ (8003dec ) - 8003bca: 6a5b ldr r3, [r3, #36] @ 0x24 - 8003bcc: 2202 movs r2, #2 - 8003bce: f8c7 2178 str.w r2, [r7, #376] @ 0x178 - 8003bd2: f8d7 2178 ldr.w r2, [r7, #376] @ 0x178 - 8003bd6: fa92 f2a2 rbit r2, r2 - 8003bda: f8c7 2174 str.w r2, [r7, #372] @ 0x174 + 8003be2: f8d7 3188 ldr.w r3, [r7, #392] @ 0x188 + 8003be6: fa93 f3a3 rbit r3, r3 + 8003bea: f8c7 3184 str.w r3, [r7, #388] @ 0x184 + 8003bee: 2302 movs r3, #2 + 8003bf0: f8c7 3180 str.w r3, [r7, #384] @ 0x180 + 8003bf4: f8d7 3180 ldr.w r3, [r7, #384] @ 0x180 + 8003bf8: fa93 f3a3 rbit r3, r3 + 8003bfc: f8c7 317c str.w r3, [r7, #380] @ 0x17c + 8003c00: 4b88 ldr r3, [pc, #544] @ (8003e24 ) + 8003c02: 6a5b ldr r3, [r3, #36] @ 0x24 + 8003c04: 2202 movs r2, #2 + 8003c06: f8c7 2178 str.w r2, [r7, #376] @ 0x178 + 8003c0a: f8d7 2178 ldr.w r2, [r7, #376] @ 0x178 + 8003c0e: fa92 f2a2 rbit r2, r2 + 8003c12: f8c7 2174 str.w r2, [r7, #372] @ 0x174 return result; - 8003bde: f8d7 2174 ldr.w r2, [r7, #372] @ 0x174 - 8003be2: fab2 f282 clz r2, r2 - 8003be6: b2d2 uxtb r2, r2 - 8003be8: f042 0220 orr.w r2, r2, #32 - 8003bec: b2d2 uxtb r2, r2 - 8003bee: f002 021f and.w r2, r2, #31 - 8003bf2: 2101 movs r1, #1 - 8003bf4: fa01 f202 lsl.w r2, r1, r2 - 8003bf8: 4013 ands r3, r2 - 8003bfa: 2b00 cmp r3, #0 - 8003bfc: d00a beq.n 8003c14 - 8003bfe: f507 7300 add.w r3, r7, #512 @ 0x200 - 8003c02: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc - 8003c06: 681b ldr r3, [r3, #0] - 8003c08: 691b ldr r3, [r3, #16] - 8003c0a: 2b01 cmp r3, #1 - 8003c0c: d002 beq.n 8003c14 + 8003c16: f8d7 2174 ldr.w r2, [r7, #372] @ 0x174 + 8003c1a: fab2 f282 clz r2, r2 + 8003c1e: b2d2 uxtb r2, r2 + 8003c20: f042 0220 orr.w r2, r2, #32 + 8003c24: b2d2 uxtb r2, r2 + 8003c26: f002 021f and.w r2, r2, #31 + 8003c2a: 2101 movs r1, #1 + 8003c2c: fa01 f202 lsl.w r2, r1, r2 + 8003c30: 4013 ands r3, r2 + 8003c32: 2b00 cmp r3, #0 + 8003c34: d00a beq.n 8003c4c + 8003c36: f507 7300 add.w r3, r7, #512 @ 0x200 + 8003c3a: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc + 8003c3e: 681b ldr r3, [r3, #0] + 8003c40: 691b ldr r3, [r3, #16] + 8003c42: 2b01 cmp r3, #1 + 8003c44: d002 beq.n 8003c4c { return HAL_ERROR; - 8003c0e: 2301 movs r3, #1 - 8003c10: f000 be2e b.w 8004870 + 8003c46: 2301 movs r3, #1 + 8003c48: f000 be2e b.w 80048a8 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); - 8003c14: 4b75 ldr r3, [pc, #468] @ (8003dec ) - 8003c16: 681b ldr r3, [r3, #0] - 8003c18: f023 02f8 bic.w r2, r3, #248 @ 0xf8 - 8003c1c: f507 7300 add.w r3, r7, #512 @ 0x200 - 8003c20: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc - 8003c24: 681b ldr r3, [r3, #0] - 8003c26: 695b ldr r3, [r3, #20] - 8003c28: 21f8 movs r1, #248 @ 0xf8 - 8003c2a: f8c7 1170 str.w r1, [r7, #368] @ 0x170 + 8003c4c: 4b75 ldr r3, [pc, #468] @ (8003e24 ) + 8003c4e: 681b ldr r3, [r3, #0] + 8003c50: f023 02f8 bic.w r2, r3, #248 @ 0xf8 + 8003c54: f507 7300 add.w r3, r7, #512 @ 0x200 + 8003c58: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc + 8003c5c: 681b ldr r3, [r3, #0] + 8003c5e: 695b ldr r3, [r3, #20] + 8003c60: 21f8 movs r1, #248 @ 0xf8 + 8003c62: f8c7 1170 str.w r1, [r7, #368] @ 0x170 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8003c2e: f8d7 1170 ldr.w r1, [r7, #368] @ 0x170 - 8003c32: fa91 f1a1 rbit r1, r1 - 8003c36: f8c7 116c str.w r1, [r7, #364] @ 0x16c + 8003c66: f8d7 1170 ldr.w r1, [r7, #368] @ 0x170 + 8003c6a: fa91 f1a1 rbit r1, r1 + 8003c6e: f8c7 116c str.w r1, [r7, #364] @ 0x16c return result; - 8003c3a: f8d7 116c ldr.w r1, [r7, #364] @ 0x16c - 8003c3e: fab1 f181 clz r1, r1 - 8003c42: b2c9 uxtb r1, r1 - 8003c44: 408b lsls r3, r1 - 8003c46: 4969 ldr r1, [pc, #420] @ (8003dec ) - 8003c48: 4313 orrs r3, r2 - 8003c4a: 600b str r3, [r1, #0] + 8003c72: f8d7 116c ldr.w r1, [r7, #364] @ 0x16c + 8003c76: fab1 f181 clz r1, r1 + 8003c7a: b2c9 uxtb r1, r1 + 8003c7c: 408b lsls r3, r1 + 8003c7e: 4969 ldr r1, [pc, #420] @ (8003e24 ) + 8003c80: 4313 orrs r3, r2 + 8003c82: 600b str r3, [r1, #0] if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) - 8003c4c: e0fd b.n 8003e4a + 8003c84: e0fd b.n 8003e82 } } else { /* Check the HSI State */ if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF) - 8003c4e: f507 7300 add.w r3, r7, #512 @ 0x200 - 8003c52: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc - 8003c56: 681b ldr r3, [r3, #0] - 8003c58: 691b ldr r3, [r3, #16] - 8003c5a: 2b00 cmp r3, #0 - 8003c5c: f000 8088 beq.w 8003d70 - 8003c60: 2301 movs r3, #1 - 8003c62: f8c7 3168 str.w r3, [r7, #360] @ 0x168 + 8003c86: f507 7300 add.w r3, r7, #512 @ 0x200 + 8003c8a: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc + 8003c8e: 681b ldr r3, [r3, #0] + 8003c90: 691b ldr r3, [r3, #16] + 8003c92: 2b00 cmp r3, #0 + 8003c94: f000 8088 beq.w 8003da8 + 8003c98: 2301 movs r3, #1 + 8003c9a: f8c7 3168 str.w r3, [r7, #360] @ 0x168 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8003c66: f8d7 3168 ldr.w r3, [r7, #360] @ 0x168 - 8003c6a: fa93 f3a3 rbit r3, r3 - 8003c6e: f8c7 3164 str.w r3, [r7, #356] @ 0x164 + 8003c9e: f8d7 3168 ldr.w r3, [r7, #360] @ 0x168 + 8003ca2: fa93 f3a3 rbit r3, r3 + 8003ca6: f8c7 3164 str.w r3, [r7, #356] @ 0x164 return result; - 8003c72: f8d7 3164 ldr.w r3, [r7, #356] @ 0x164 + 8003caa: f8d7 3164 ldr.w r3, [r7, #356] @ 0x164 { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); - 8003c76: fab3 f383 clz r3, r3 - 8003c7a: b2db uxtb r3, r3 - 8003c7c: f103 5384 add.w r3, r3, #276824064 @ 0x10800000 - 8003c80: f503 1384 add.w r3, r3, #1081344 @ 0x108000 - 8003c84: 009b lsls r3, r3, #2 - 8003c86: 461a mov r2, r3 - 8003c88: 2301 movs r3, #1 - 8003c8a: 6013 str r3, [r2, #0] + 8003cae: fab3 f383 clz r3, r3 + 8003cb2: b2db uxtb r3, r3 + 8003cb4: f103 5384 add.w r3, r3, #276824064 @ 0x10800000 + 8003cb8: f503 1384 add.w r3, r3, #1081344 @ 0x108000 + 8003cbc: 009b lsls r3, r3, #2 + 8003cbe: 461a mov r2, r3 + 8003cc0: 2301 movs r3, #1 + 8003cc2: 6013 str r3, [r2, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); - 8003c8c: f7fd fbb4 bl 80013f8 - 8003c90: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8 + 8003cc4: f7fd fbb4 bl 8001430 + 8003cc8: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8 /* Wait till HSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) - 8003c94: e00a b.n 8003cac + 8003ccc: e00a b.n 8003ce4 { if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) - 8003c96: f7fd fbaf bl 80013f8 - 8003c9a: 4602 mov r2, r0 - 8003c9c: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8 - 8003ca0: 1ad3 subs r3, r2, r3 - 8003ca2: 2b02 cmp r3, #2 - 8003ca4: d902 bls.n 8003cac + 8003cce: f7fd fbaf bl 8001430 + 8003cd2: 4602 mov r2, r0 + 8003cd4: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8 + 8003cd8: 1ad3 subs r3, r2, r3 + 8003cda: 2b02 cmp r3, #2 + 8003cdc: d902 bls.n 8003ce4 { return HAL_TIMEOUT; - 8003ca6: 2303 movs r3, #3 - 8003ca8: f000 bde2 b.w 8004870 - 8003cac: 2302 movs r3, #2 - 8003cae: f8c7 3160 str.w r3, [r7, #352] @ 0x160 + 8003cde: 2303 movs r3, #3 + 8003ce0: f000 bde2 b.w 80048a8 + 8003ce4: 2302 movs r3, #2 + 8003ce6: f8c7 3160 str.w r3, [r7, #352] @ 0x160 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8003cb2: f8d7 3160 ldr.w r3, [r7, #352] @ 0x160 - 8003cb6: fa93 f3a3 rbit r3, r3 - 8003cba: f8c7 315c str.w r3, [r7, #348] @ 0x15c + 8003cea: f8d7 3160 ldr.w r3, [r7, #352] @ 0x160 + 8003cee: fa93 f3a3 rbit r3, r3 + 8003cf2: f8c7 315c str.w r3, [r7, #348] @ 0x15c return result; - 8003cbe: f8d7 315c ldr.w r3, [r7, #348] @ 0x15c + 8003cf6: f8d7 315c ldr.w r3, [r7, #348] @ 0x15c while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) - 8003cc2: fab3 f383 clz r3, r3 - 8003cc6: b2db uxtb r3, r3 - 8003cc8: 095b lsrs r3, r3, #5 - 8003cca: b2db uxtb r3, r3 - 8003ccc: f043 0301 orr.w r3, r3, #1 - 8003cd0: b2db uxtb r3, r3 - 8003cd2: 2b01 cmp r3, #1 - 8003cd4: d102 bne.n 8003cdc - 8003cd6: 4b45 ldr r3, [pc, #276] @ (8003dec ) - 8003cd8: 681b ldr r3, [r3, #0] - 8003cda: e013 b.n 8003d04 - 8003cdc: 2302 movs r3, #2 - 8003cde: f8c7 3158 str.w r3, [r7, #344] @ 0x158 + 8003cfa: fab3 f383 clz r3, r3 + 8003cfe: b2db uxtb r3, r3 + 8003d00: 095b lsrs r3, r3, #5 + 8003d02: b2db uxtb r3, r3 + 8003d04: f043 0301 orr.w r3, r3, #1 + 8003d08: b2db uxtb r3, r3 + 8003d0a: 2b01 cmp r3, #1 + 8003d0c: d102 bne.n 8003d14 + 8003d0e: 4b45 ldr r3, [pc, #276] @ (8003e24 ) + 8003d10: 681b ldr r3, [r3, #0] + 8003d12: e013 b.n 8003d3c + 8003d14: 2302 movs r3, #2 + 8003d16: f8c7 3158 str.w r3, [r7, #344] @ 0x158 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8003ce2: f8d7 3158 ldr.w r3, [r7, #344] @ 0x158 - 8003ce6: fa93 f3a3 rbit r3, r3 - 8003cea: f8c7 3154 str.w r3, [r7, #340] @ 0x154 - 8003cee: 2302 movs r3, #2 - 8003cf0: f8c7 3150 str.w r3, [r7, #336] @ 0x150 - 8003cf4: f8d7 3150 ldr.w r3, [r7, #336] @ 0x150 - 8003cf8: fa93 f3a3 rbit r3, r3 - 8003cfc: f8c7 314c str.w r3, [r7, #332] @ 0x14c - 8003d00: 4b3a ldr r3, [pc, #232] @ (8003dec ) - 8003d02: 6a5b ldr r3, [r3, #36] @ 0x24 - 8003d04: 2202 movs r2, #2 - 8003d06: f8c7 2148 str.w r2, [r7, #328] @ 0x148 - 8003d0a: f8d7 2148 ldr.w r2, [r7, #328] @ 0x148 - 8003d0e: fa92 f2a2 rbit r2, r2 - 8003d12: f8c7 2144 str.w r2, [r7, #324] @ 0x144 + 8003d1a: f8d7 3158 ldr.w r3, [r7, #344] @ 0x158 + 8003d1e: fa93 f3a3 rbit r3, r3 + 8003d22: f8c7 3154 str.w r3, [r7, #340] @ 0x154 + 8003d26: 2302 movs r3, #2 + 8003d28: f8c7 3150 str.w r3, [r7, #336] @ 0x150 + 8003d2c: f8d7 3150 ldr.w r3, [r7, #336] @ 0x150 + 8003d30: fa93 f3a3 rbit r3, r3 + 8003d34: f8c7 314c str.w r3, [r7, #332] @ 0x14c + 8003d38: 4b3a ldr r3, [pc, #232] @ (8003e24 ) + 8003d3a: 6a5b ldr r3, [r3, #36] @ 0x24 + 8003d3c: 2202 movs r2, #2 + 8003d3e: f8c7 2148 str.w r2, [r7, #328] @ 0x148 + 8003d42: f8d7 2148 ldr.w r2, [r7, #328] @ 0x148 + 8003d46: fa92 f2a2 rbit r2, r2 + 8003d4a: f8c7 2144 str.w r2, [r7, #324] @ 0x144 return result; - 8003d16: f8d7 2144 ldr.w r2, [r7, #324] @ 0x144 - 8003d1a: fab2 f282 clz r2, r2 - 8003d1e: b2d2 uxtb r2, r2 - 8003d20: f042 0220 orr.w r2, r2, #32 - 8003d24: b2d2 uxtb r2, r2 - 8003d26: f002 021f and.w r2, r2, #31 - 8003d2a: 2101 movs r1, #1 - 8003d2c: fa01 f202 lsl.w r2, r1, r2 - 8003d30: 4013 ands r3, r2 - 8003d32: 2b00 cmp r3, #0 - 8003d34: d0af beq.n 8003c96 + 8003d4e: f8d7 2144 ldr.w r2, [r7, #324] @ 0x144 + 8003d52: fab2 f282 clz r2, r2 + 8003d56: b2d2 uxtb r2, r2 + 8003d58: f042 0220 orr.w r2, r2, #32 + 8003d5c: b2d2 uxtb r2, r2 + 8003d5e: f002 021f and.w r2, r2, #31 + 8003d62: 2101 movs r1, #1 + 8003d64: fa01 f202 lsl.w r2, r1, r2 + 8003d68: 4013 ands r3, r2 + 8003d6a: 2b00 cmp r3, #0 + 8003d6c: d0af beq.n 8003cce } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); - 8003d36: 4b2d ldr r3, [pc, #180] @ (8003dec ) - 8003d38: 681b ldr r3, [r3, #0] - 8003d3a: f023 02f8 bic.w r2, r3, #248 @ 0xf8 - 8003d3e: f507 7300 add.w r3, r7, #512 @ 0x200 - 8003d42: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc - 8003d46: 681b ldr r3, [r3, #0] - 8003d48: 695b ldr r3, [r3, #20] - 8003d4a: 21f8 movs r1, #248 @ 0xf8 - 8003d4c: f8c7 1140 str.w r1, [r7, #320] @ 0x140 + 8003d6e: 4b2d ldr r3, [pc, #180] @ (8003e24 ) + 8003d70: 681b ldr r3, [r3, #0] + 8003d72: f023 02f8 bic.w r2, r3, #248 @ 0xf8 + 8003d76: f507 7300 add.w r3, r7, #512 @ 0x200 + 8003d7a: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc + 8003d7e: 681b ldr r3, [r3, #0] + 8003d80: 695b ldr r3, [r3, #20] + 8003d82: 21f8 movs r1, #248 @ 0xf8 + 8003d84: f8c7 1140 str.w r1, [r7, #320] @ 0x140 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8003d50: f8d7 1140 ldr.w r1, [r7, #320] @ 0x140 - 8003d54: fa91 f1a1 rbit r1, r1 - 8003d58: f8c7 113c str.w r1, [r7, #316] @ 0x13c + 8003d88: f8d7 1140 ldr.w r1, [r7, #320] @ 0x140 + 8003d8c: fa91 f1a1 rbit r1, r1 + 8003d90: f8c7 113c str.w r1, [r7, #316] @ 0x13c return result; - 8003d5c: f8d7 113c ldr.w r1, [r7, #316] @ 0x13c - 8003d60: fab1 f181 clz r1, r1 - 8003d64: b2c9 uxtb r1, r1 - 8003d66: 408b lsls r3, r1 - 8003d68: 4920 ldr r1, [pc, #128] @ (8003dec ) - 8003d6a: 4313 orrs r3, r2 - 8003d6c: 600b str r3, [r1, #0] - 8003d6e: e06c b.n 8003e4a - 8003d70: 2301 movs r3, #1 - 8003d72: f8c7 3138 str.w r3, [r7, #312] @ 0x138 + 8003d94: f8d7 113c ldr.w r1, [r7, #316] @ 0x13c + 8003d98: fab1 f181 clz r1, r1 + 8003d9c: b2c9 uxtb r1, r1 + 8003d9e: 408b lsls r3, r1 + 8003da0: 4920 ldr r1, [pc, #128] @ (8003e24 ) + 8003da2: 4313 orrs r3, r2 + 8003da4: 600b str r3, [r1, #0] + 8003da6: e06c b.n 8003e82 + 8003da8: 2301 movs r3, #1 + 8003daa: f8c7 3138 str.w r3, [r7, #312] @ 0x138 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8003d76: f8d7 3138 ldr.w r3, [r7, #312] @ 0x138 - 8003d7a: fa93 f3a3 rbit r3, r3 - 8003d7e: f8c7 3134 str.w r3, [r7, #308] @ 0x134 + 8003dae: f8d7 3138 ldr.w r3, [r7, #312] @ 0x138 + 8003db2: fa93 f3a3 rbit r3, r3 + 8003db6: f8c7 3134 str.w r3, [r7, #308] @ 0x134 return result; - 8003d82: f8d7 3134 ldr.w r3, [r7, #308] @ 0x134 + 8003dba: f8d7 3134 ldr.w r3, [r7, #308] @ 0x134 } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); - 8003d86: fab3 f383 clz r3, r3 - 8003d8a: b2db uxtb r3, r3 - 8003d8c: f103 5384 add.w r3, r3, #276824064 @ 0x10800000 - 8003d90: f503 1384 add.w r3, r3, #1081344 @ 0x108000 - 8003d94: 009b lsls r3, r3, #2 - 8003d96: 461a mov r2, r3 - 8003d98: 2300 movs r3, #0 - 8003d9a: 6013 str r3, [r2, #0] + 8003dbe: fab3 f383 clz r3, r3 + 8003dc2: b2db uxtb r3, r3 + 8003dc4: f103 5384 add.w r3, r3, #276824064 @ 0x10800000 + 8003dc8: f503 1384 add.w r3, r3, #1081344 @ 0x108000 + 8003dcc: 009b lsls r3, r3, #2 + 8003dce: 461a mov r2, r3 + 8003dd0: 2300 movs r3, #0 + 8003dd2: 6013 str r3, [r2, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); - 8003d9c: f7fd fb2c bl 80013f8 - 8003da0: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8 + 8003dd4: f7fd fb2c bl 8001430 + 8003dd8: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8 /* Wait till HSI is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) - 8003da4: e00a b.n 8003dbc + 8003ddc: e00a b.n 8003df4 { if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) - 8003da6: f7fd fb27 bl 80013f8 - 8003daa: 4602 mov r2, r0 - 8003dac: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8 - 8003db0: 1ad3 subs r3, r2, r3 - 8003db2: 2b02 cmp r3, #2 - 8003db4: d902 bls.n 8003dbc + 8003dde: f7fd fb27 bl 8001430 + 8003de2: 4602 mov r2, r0 + 8003de4: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8 + 8003de8: 1ad3 subs r3, r2, r3 + 8003dea: 2b02 cmp r3, #2 + 8003dec: d902 bls.n 8003df4 { return HAL_TIMEOUT; - 8003db6: 2303 movs r3, #3 - 8003db8: f000 bd5a b.w 8004870 - 8003dbc: 2302 movs r3, #2 - 8003dbe: f8c7 3130 str.w r3, [r7, #304] @ 0x130 + 8003dee: 2303 movs r3, #3 + 8003df0: f000 bd5a b.w 80048a8 + 8003df4: 2302 movs r3, #2 + 8003df6: f8c7 3130 str.w r3, [r7, #304] @ 0x130 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8003dc2: f8d7 3130 ldr.w r3, [r7, #304] @ 0x130 - 8003dc6: fa93 f3a3 rbit r3, r3 - 8003dca: f8c7 312c str.w r3, [r7, #300] @ 0x12c + 8003dfa: f8d7 3130 ldr.w r3, [r7, #304] @ 0x130 + 8003dfe: fa93 f3a3 rbit r3, r3 + 8003e02: f8c7 312c str.w r3, [r7, #300] @ 0x12c return result; - 8003dce: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c + 8003e06: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) - 8003dd2: fab3 f383 clz r3, r3 - 8003dd6: b2db uxtb r3, r3 - 8003dd8: 095b lsrs r3, r3, #5 - 8003dda: b2db uxtb r3, r3 - 8003ddc: f043 0301 orr.w r3, r3, #1 - 8003de0: b2db uxtb r3, r3 - 8003de2: 2b01 cmp r3, #1 - 8003de4: d104 bne.n 8003df0 - 8003de6: 4b01 ldr r3, [pc, #4] @ (8003dec ) - 8003de8: 681b ldr r3, [r3, #0] - 8003dea: e015 b.n 8003e18 - 8003dec: 40021000 .word 0x40021000 - 8003df0: 2302 movs r3, #2 - 8003df2: f8c7 3128 str.w r3, [r7, #296] @ 0x128 + 8003e0a: fab3 f383 clz r3, r3 + 8003e0e: b2db uxtb r3, r3 + 8003e10: 095b lsrs r3, r3, #5 + 8003e12: b2db uxtb r3, r3 + 8003e14: f043 0301 orr.w r3, r3, #1 + 8003e18: b2db uxtb r3, r3 + 8003e1a: 2b01 cmp r3, #1 + 8003e1c: d104 bne.n 8003e28 + 8003e1e: 4b01 ldr r3, [pc, #4] @ (8003e24 ) + 8003e20: 681b ldr r3, [r3, #0] + 8003e22: e015 b.n 8003e50 + 8003e24: 40021000 .word 0x40021000 + 8003e28: 2302 movs r3, #2 + 8003e2a: f8c7 3128 str.w r3, [r7, #296] @ 0x128 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8003df6: f8d7 3128 ldr.w r3, [r7, #296] @ 0x128 - 8003dfa: fa93 f3a3 rbit r3, r3 - 8003dfe: f8c7 3124 str.w r3, [r7, #292] @ 0x124 - 8003e02: 2302 movs r3, #2 - 8003e04: f8c7 3120 str.w r3, [r7, #288] @ 0x120 - 8003e08: f8d7 3120 ldr.w r3, [r7, #288] @ 0x120 - 8003e0c: fa93 f3a3 rbit r3, r3 - 8003e10: f8c7 311c str.w r3, [r7, #284] @ 0x11c - 8003e14: 4bc8 ldr r3, [pc, #800] @ (8004138 ) - 8003e16: 6a5b ldr r3, [r3, #36] @ 0x24 - 8003e18: 2202 movs r2, #2 - 8003e1a: f8c7 2118 str.w r2, [r7, #280] @ 0x118 - 8003e1e: f8d7 2118 ldr.w r2, [r7, #280] @ 0x118 - 8003e22: fa92 f2a2 rbit r2, r2 - 8003e26: f8c7 2114 str.w r2, [r7, #276] @ 0x114 + 8003e2e: f8d7 3128 ldr.w r3, [r7, #296] @ 0x128 + 8003e32: fa93 f3a3 rbit r3, r3 + 8003e36: f8c7 3124 str.w r3, [r7, #292] @ 0x124 + 8003e3a: 2302 movs r3, #2 + 8003e3c: f8c7 3120 str.w r3, [r7, #288] @ 0x120 + 8003e40: f8d7 3120 ldr.w r3, [r7, #288] @ 0x120 + 8003e44: fa93 f3a3 rbit r3, r3 + 8003e48: f8c7 311c str.w r3, [r7, #284] @ 0x11c + 8003e4c: 4bc8 ldr r3, [pc, #800] @ (8004170 ) + 8003e4e: 6a5b ldr r3, [r3, #36] @ 0x24 + 8003e50: 2202 movs r2, #2 + 8003e52: f8c7 2118 str.w r2, [r7, #280] @ 0x118 + 8003e56: f8d7 2118 ldr.w r2, [r7, #280] @ 0x118 + 8003e5a: fa92 f2a2 rbit r2, r2 + 8003e5e: f8c7 2114 str.w r2, [r7, #276] @ 0x114 return result; - 8003e2a: f8d7 2114 ldr.w r2, [r7, #276] @ 0x114 - 8003e2e: fab2 f282 clz r2, r2 - 8003e32: b2d2 uxtb r2, r2 - 8003e34: f042 0220 orr.w r2, r2, #32 - 8003e38: b2d2 uxtb r2, r2 - 8003e3a: f002 021f and.w r2, r2, #31 - 8003e3e: 2101 movs r1, #1 - 8003e40: fa01 f202 lsl.w r2, r1, r2 - 8003e44: 4013 ands r3, r2 - 8003e46: 2b00 cmp r3, #0 - 8003e48: d1ad bne.n 8003da6 + 8003e62: f8d7 2114 ldr.w r2, [r7, #276] @ 0x114 + 8003e66: fab2 f282 clz r2, r2 + 8003e6a: b2d2 uxtb r2, r2 + 8003e6c: f042 0220 orr.w r2, r2, #32 + 8003e70: b2d2 uxtb r2, r2 + 8003e72: f002 021f and.w r2, r2, #31 + 8003e76: 2101 movs r1, #1 + 8003e78: fa01 f202 lsl.w r2, r1, r2 + 8003e7c: 4013 ands r3, r2 + 8003e7e: 2b00 cmp r3, #0 + 8003e80: d1ad bne.n 8003dde } } } } /*------------------------------ LSI Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) - 8003e4a: f507 7300 add.w r3, r7, #512 @ 0x200 - 8003e4e: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc - 8003e52: 681b ldr r3, [r3, #0] - 8003e54: 681b ldr r3, [r3, #0] - 8003e56: f003 0308 and.w r3, r3, #8 - 8003e5a: 2b00 cmp r3, #0 - 8003e5c: f000 8110 beq.w 8004080 + 8003e82: f507 7300 add.w r3, r7, #512 @ 0x200 + 8003e86: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc + 8003e8a: 681b ldr r3, [r3, #0] + 8003e8c: 681b ldr r3, [r3, #0] + 8003e8e: f003 0308 and.w r3, r3, #8 + 8003e92: 2b00 cmp r3, #0 + 8003e94: f000 8110 beq.w 80040b8 { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) - 8003e60: f507 7300 add.w r3, r7, #512 @ 0x200 - 8003e64: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc - 8003e68: 681b ldr r3, [r3, #0] - 8003e6a: 699b ldr r3, [r3, #24] - 8003e6c: 2b00 cmp r3, #0 - 8003e6e: d079 beq.n 8003f64 - 8003e70: 2301 movs r3, #1 - 8003e72: f8c7 3110 str.w r3, [r7, #272] @ 0x110 + 8003e98: f507 7300 add.w r3, r7, #512 @ 0x200 + 8003e9c: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc + 8003ea0: 681b ldr r3, [r3, #0] + 8003ea2: 699b ldr r3, [r3, #24] + 8003ea4: 2b00 cmp r3, #0 + 8003ea6: d079 beq.n 8003f9c + 8003ea8: 2301 movs r3, #1 + 8003eaa: f8c7 3110 str.w r3, [r7, #272] @ 0x110 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8003e76: f8d7 3110 ldr.w r3, [r7, #272] @ 0x110 - 8003e7a: fa93 f3a3 rbit r3, r3 - 8003e7e: f8c7 310c str.w r3, [r7, #268] @ 0x10c + 8003eae: f8d7 3110 ldr.w r3, [r7, #272] @ 0x110 + 8003eb2: fa93 f3a3 rbit r3, r3 + 8003eb6: f8c7 310c str.w r3, [r7, #268] @ 0x10c return result; - 8003e82: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c + 8003eba: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); - 8003e86: fab3 f383 clz r3, r3 - 8003e8a: b2db uxtb r3, r3 - 8003e8c: 461a mov r2, r3 - 8003e8e: 4bab ldr r3, [pc, #684] @ (800413c ) - 8003e90: 4413 add r3, r2 - 8003e92: 009b lsls r3, r3, #2 - 8003e94: 461a mov r2, r3 - 8003e96: 2301 movs r3, #1 - 8003e98: 6013 str r3, [r2, #0] + 8003ebe: fab3 f383 clz r3, r3 + 8003ec2: b2db uxtb r3, r3 + 8003ec4: 461a mov r2, r3 + 8003ec6: 4bab ldr r3, [pc, #684] @ (8004174 ) + 8003ec8: 4413 add r3, r2 + 8003eca: 009b lsls r3, r3, #2 + 8003ecc: 461a mov r2, r3 + 8003ece: 2301 movs r3, #1 + 8003ed0: 6013 str r3, [r2, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); - 8003e9a: f7fd faad bl 80013f8 - 8003e9e: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8 + 8003ed2: f7fd faad bl 8001430 + 8003ed6: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8 /* Wait till LSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) - 8003ea2: e00a b.n 8003eba + 8003eda: e00a b.n 8003ef2 { if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) - 8003ea4: f7fd faa8 bl 80013f8 - 8003ea8: 4602 mov r2, r0 - 8003eaa: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8 - 8003eae: 1ad3 subs r3, r2, r3 - 8003eb0: 2b02 cmp r3, #2 - 8003eb2: d902 bls.n 8003eba + 8003edc: f7fd faa8 bl 8001430 + 8003ee0: 4602 mov r2, r0 + 8003ee2: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8 + 8003ee6: 1ad3 subs r3, r2, r3 + 8003ee8: 2b02 cmp r3, #2 + 8003eea: d902 bls.n 8003ef2 { return HAL_TIMEOUT; - 8003eb4: 2303 movs r3, #3 - 8003eb6: f000 bcdb b.w 8004870 - 8003eba: 2302 movs r3, #2 - 8003ebc: f8c7 3108 str.w r3, [r7, #264] @ 0x108 + 8003eec: 2303 movs r3, #3 + 8003eee: f000 bcdb b.w 80048a8 + 8003ef2: 2302 movs r3, #2 + 8003ef4: f8c7 3108 str.w r3, [r7, #264] @ 0x108 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8003ec0: f8d7 3108 ldr.w r3, [r7, #264] @ 0x108 - 8003ec4: fa93 f3a3 rbit r3, r3 - 8003ec8: f8c7 3104 str.w r3, [r7, #260] @ 0x104 - 8003ecc: f507 7300 add.w r3, r7, #512 @ 0x200 - 8003ed0: f5a3 7380 sub.w r3, r3, #256 @ 0x100 - 8003ed4: 2202 movs r2, #2 - 8003ed6: 601a str r2, [r3, #0] - 8003ed8: f507 7300 add.w r3, r7, #512 @ 0x200 - 8003edc: f5a3 7380 sub.w r3, r3, #256 @ 0x100 - 8003ee0: 681b ldr r3, [r3, #0] - 8003ee2: fa93 f2a3 rbit r2, r3 - 8003ee6: f507 7300 add.w r3, r7, #512 @ 0x200 - 8003eea: f5a3 7382 sub.w r3, r3, #260 @ 0x104 - 8003eee: 601a str r2, [r3, #0] - 8003ef0: f507 7300 add.w r3, r7, #512 @ 0x200 - 8003ef4: f5a3 7384 sub.w r3, r3, #264 @ 0x108 - 8003ef8: 2202 movs r2, #2 - 8003efa: 601a str r2, [r3, #0] - 8003efc: f507 7300 add.w r3, r7, #512 @ 0x200 - 8003f00: f5a3 7384 sub.w r3, r3, #264 @ 0x108 - 8003f04: 681b ldr r3, [r3, #0] - 8003f06: fa93 f2a3 rbit r2, r3 - 8003f0a: f507 7300 add.w r3, r7, #512 @ 0x200 - 8003f0e: f5a3 7386 sub.w r3, r3, #268 @ 0x10c - 8003f12: 601a str r2, [r3, #0] + 8003ef8: f8d7 3108 ldr.w r3, [r7, #264] @ 0x108 + 8003efc: fa93 f3a3 rbit r3, r3 + 8003f00: f8c7 3104 str.w r3, [r7, #260] @ 0x104 + 8003f04: f507 7300 add.w r3, r7, #512 @ 0x200 + 8003f08: f5a3 7380 sub.w r3, r3, #256 @ 0x100 + 8003f0c: 2202 movs r2, #2 + 8003f0e: 601a str r2, [r3, #0] + 8003f10: f507 7300 add.w r3, r7, #512 @ 0x200 + 8003f14: f5a3 7380 sub.w r3, r3, #256 @ 0x100 + 8003f18: 681b ldr r3, [r3, #0] + 8003f1a: fa93 f2a3 rbit r2, r3 + 8003f1e: f507 7300 add.w r3, r7, #512 @ 0x200 + 8003f22: f5a3 7382 sub.w r3, r3, #260 @ 0x104 + 8003f26: 601a str r2, [r3, #0] + 8003f28: f507 7300 add.w r3, r7, #512 @ 0x200 + 8003f2c: f5a3 7384 sub.w r3, r3, #264 @ 0x108 + 8003f30: 2202 movs r2, #2 + 8003f32: 601a str r2, [r3, #0] + 8003f34: f507 7300 add.w r3, r7, #512 @ 0x200 + 8003f38: f5a3 7384 sub.w r3, r3, #264 @ 0x108 + 8003f3c: 681b ldr r3, [r3, #0] + 8003f3e: fa93 f2a3 rbit r2, r3 + 8003f42: f507 7300 add.w r3, r7, #512 @ 0x200 + 8003f46: f5a3 7386 sub.w r3, r3, #268 @ 0x10c + 8003f4a: 601a str r2, [r3, #0] while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) - 8003f14: 4b88 ldr r3, [pc, #544] @ (8004138 ) - 8003f16: 6a5a ldr r2, [r3, #36] @ 0x24 - 8003f18: f507 7300 add.w r3, r7, #512 @ 0x200 - 8003f1c: f5a3 7388 sub.w r3, r3, #272 @ 0x110 - 8003f20: 2102 movs r1, #2 - 8003f22: 6019 str r1, [r3, #0] - 8003f24: f507 7300 add.w r3, r7, #512 @ 0x200 - 8003f28: f5a3 7388 sub.w r3, r3, #272 @ 0x110 - 8003f2c: 681b ldr r3, [r3, #0] - 8003f2e: fa93 f1a3 rbit r1, r3 - 8003f32: f507 7300 add.w r3, r7, #512 @ 0x200 - 8003f36: f5a3 738a sub.w r3, r3, #276 @ 0x114 - 8003f3a: 6019 str r1, [r3, #0] + 8003f4c: 4b88 ldr r3, [pc, #544] @ (8004170 ) + 8003f4e: 6a5a ldr r2, [r3, #36] @ 0x24 + 8003f50: f507 7300 add.w r3, r7, #512 @ 0x200 + 8003f54: f5a3 7388 sub.w r3, r3, #272 @ 0x110 + 8003f58: 2102 movs r1, #2 + 8003f5a: 6019 str r1, [r3, #0] + 8003f5c: f507 7300 add.w r3, r7, #512 @ 0x200 + 8003f60: f5a3 7388 sub.w r3, r3, #272 @ 0x110 + 8003f64: 681b ldr r3, [r3, #0] + 8003f66: fa93 f1a3 rbit r1, r3 + 8003f6a: f507 7300 add.w r3, r7, #512 @ 0x200 + 8003f6e: f5a3 738a sub.w r3, r3, #276 @ 0x114 + 8003f72: 6019 str r1, [r3, #0] return result; - 8003f3c: f507 7300 add.w r3, r7, #512 @ 0x200 - 8003f40: f5a3 738a sub.w r3, r3, #276 @ 0x114 - 8003f44: 681b ldr r3, [r3, #0] - 8003f46: fab3 f383 clz r3, r3 - 8003f4a: b2db uxtb r3, r3 - 8003f4c: f043 0360 orr.w r3, r3, #96 @ 0x60 - 8003f50: b2db uxtb r3, r3 - 8003f52: f003 031f and.w r3, r3, #31 - 8003f56: 2101 movs r1, #1 - 8003f58: fa01 f303 lsl.w r3, r1, r3 - 8003f5c: 4013 ands r3, r2 - 8003f5e: 2b00 cmp r3, #0 - 8003f60: d0a0 beq.n 8003ea4 - 8003f62: e08d b.n 8004080 - 8003f64: f507 7300 add.w r3, r7, #512 @ 0x200 - 8003f68: f5a3 738c sub.w r3, r3, #280 @ 0x118 - 8003f6c: 2201 movs r2, #1 - 8003f6e: 601a str r2, [r3, #0] + 8003f74: f507 7300 add.w r3, r7, #512 @ 0x200 + 8003f78: f5a3 738a sub.w r3, r3, #276 @ 0x114 + 8003f7c: 681b ldr r3, [r3, #0] + 8003f7e: fab3 f383 clz r3, r3 + 8003f82: b2db uxtb r3, r3 + 8003f84: f043 0360 orr.w r3, r3, #96 @ 0x60 + 8003f88: b2db uxtb r3, r3 + 8003f8a: f003 031f and.w r3, r3, #31 + 8003f8e: 2101 movs r1, #1 + 8003f90: fa01 f303 lsl.w r3, r1, r3 + 8003f94: 4013 ands r3, r2 + 8003f96: 2b00 cmp r3, #0 + 8003f98: d0a0 beq.n 8003edc + 8003f9a: e08d b.n 80040b8 + 8003f9c: f507 7300 add.w r3, r7, #512 @ 0x200 + 8003fa0: f5a3 738c sub.w r3, r3, #280 @ 0x118 + 8003fa4: 2201 movs r2, #1 + 8003fa6: 601a str r2, [r3, #0] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8003f70: f507 7300 add.w r3, r7, #512 @ 0x200 - 8003f74: f5a3 738c sub.w r3, r3, #280 @ 0x118 - 8003f78: 681b ldr r3, [r3, #0] - 8003f7a: fa93 f2a3 rbit r2, r3 - 8003f7e: f507 7300 add.w r3, r7, #512 @ 0x200 - 8003f82: f5a3 738e sub.w r3, r3, #284 @ 0x11c - 8003f86: 601a str r2, [r3, #0] + 8003fa8: f507 7300 add.w r3, r7, #512 @ 0x200 + 8003fac: f5a3 738c sub.w r3, r3, #280 @ 0x118 + 8003fb0: 681b ldr r3, [r3, #0] + 8003fb2: fa93 f2a3 rbit r2, r3 + 8003fb6: f507 7300 add.w r3, r7, #512 @ 0x200 + 8003fba: f5a3 738e sub.w r3, r3, #284 @ 0x11c + 8003fbe: 601a str r2, [r3, #0] return result; - 8003f88: f507 7300 add.w r3, r7, #512 @ 0x200 - 8003f8c: f5a3 738e sub.w r3, r3, #284 @ 0x11c - 8003f90: 681b ldr r3, [r3, #0] + 8003fc0: f507 7300 add.w r3, r7, #512 @ 0x200 + 8003fc4: f5a3 738e sub.w r3, r3, #284 @ 0x11c + 8003fc8: 681b ldr r3, [r3, #0] } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); - 8003f92: fab3 f383 clz r3, r3 - 8003f96: b2db uxtb r3, r3 - 8003f98: 461a mov r2, r3 - 8003f9a: 4b68 ldr r3, [pc, #416] @ (800413c ) - 8003f9c: 4413 add r3, r2 - 8003f9e: 009b lsls r3, r3, #2 - 8003fa0: 461a mov r2, r3 - 8003fa2: 2300 movs r3, #0 - 8003fa4: 6013 str r3, [r2, #0] + 8003fca: fab3 f383 clz r3, r3 + 8003fce: b2db uxtb r3, r3 + 8003fd0: 461a mov r2, r3 + 8003fd2: 4b68 ldr r3, [pc, #416] @ (8004174 ) + 8003fd4: 4413 add r3, r2 + 8003fd6: 009b lsls r3, r3, #2 + 8003fd8: 461a mov r2, r3 + 8003fda: 2300 movs r3, #0 + 8003fdc: 6013 str r3, [r2, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); - 8003fa6: f7fd fa27 bl 80013f8 - 8003faa: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8 + 8003fde: f7fd fa27 bl 8001430 + 8003fe2: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8 /* Wait till LSI is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) - 8003fae: e00a b.n 8003fc6 + 8003fe6: e00a b.n 8003ffe { if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) - 8003fb0: f7fd fa22 bl 80013f8 - 8003fb4: 4602 mov r2, r0 - 8003fb6: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8 - 8003fba: 1ad3 subs r3, r2, r3 - 8003fbc: 2b02 cmp r3, #2 - 8003fbe: d902 bls.n 8003fc6 + 8003fe8: f7fd fa22 bl 8001430 + 8003fec: 4602 mov r2, r0 + 8003fee: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8 + 8003ff2: 1ad3 subs r3, r2, r3 + 8003ff4: 2b02 cmp r3, #2 + 8003ff6: d902 bls.n 8003ffe { return HAL_TIMEOUT; - 8003fc0: 2303 movs r3, #3 - 8003fc2: f000 bc55 b.w 8004870 - 8003fc6: f507 7300 add.w r3, r7, #512 @ 0x200 - 8003fca: f5a3 7390 sub.w r3, r3, #288 @ 0x120 - 8003fce: 2202 movs r2, #2 - 8003fd0: 601a str r2, [r3, #0] + 8003ff8: 2303 movs r3, #3 + 8003ffa: f000 bc55 b.w 80048a8 + 8003ffe: f507 7300 add.w r3, r7, #512 @ 0x200 + 8004002: f5a3 7390 sub.w r3, r3, #288 @ 0x120 + 8004006: 2202 movs r2, #2 + 8004008: 601a str r2, [r3, #0] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8003fd2: f507 7300 add.w r3, r7, #512 @ 0x200 - 8003fd6: f5a3 7390 sub.w r3, r3, #288 @ 0x120 - 8003fda: 681b ldr r3, [r3, #0] - 8003fdc: fa93 f2a3 rbit r2, r3 - 8003fe0: f507 7300 add.w r3, r7, #512 @ 0x200 - 8003fe4: f5a3 7392 sub.w r3, r3, #292 @ 0x124 - 8003fe8: 601a str r2, [r3, #0] - 8003fea: f507 7300 add.w r3, r7, #512 @ 0x200 - 8003fee: f5a3 7394 sub.w r3, r3, #296 @ 0x128 - 8003ff2: 2202 movs r2, #2 - 8003ff4: 601a str r2, [r3, #0] - 8003ff6: f507 7300 add.w r3, r7, #512 @ 0x200 - 8003ffa: f5a3 7394 sub.w r3, r3, #296 @ 0x128 - 8003ffe: 681b ldr r3, [r3, #0] - 8004000: fa93 f2a3 rbit r2, r3 - 8004004: f507 7300 add.w r3, r7, #512 @ 0x200 - 8004008: f5a3 7396 sub.w r3, r3, #300 @ 0x12c - 800400c: 601a str r2, [r3, #0] - 800400e: f507 7300 add.w r3, r7, #512 @ 0x200 - 8004012: f5a3 7398 sub.w r3, r3, #304 @ 0x130 - 8004016: 2202 movs r2, #2 - 8004018: 601a str r2, [r3, #0] - 800401a: f507 7300 add.w r3, r7, #512 @ 0x200 - 800401e: f5a3 7398 sub.w r3, r3, #304 @ 0x130 - 8004022: 681b ldr r3, [r3, #0] - 8004024: fa93 f2a3 rbit r2, r3 - 8004028: f507 7300 add.w r3, r7, #512 @ 0x200 - 800402c: f5a3 739a sub.w r3, r3, #308 @ 0x134 - 8004030: 601a str r2, [r3, #0] + 800400a: f507 7300 add.w r3, r7, #512 @ 0x200 + 800400e: f5a3 7390 sub.w r3, r3, #288 @ 0x120 + 8004012: 681b ldr r3, [r3, #0] + 8004014: fa93 f2a3 rbit r2, r3 + 8004018: f507 7300 add.w r3, r7, #512 @ 0x200 + 800401c: f5a3 7392 sub.w r3, r3, #292 @ 0x124 + 8004020: 601a str r2, [r3, #0] + 8004022: f507 7300 add.w r3, r7, #512 @ 0x200 + 8004026: f5a3 7394 sub.w r3, r3, #296 @ 0x128 + 800402a: 2202 movs r2, #2 + 800402c: 601a str r2, [r3, #0] + 800402e: f507 7300 add.w r3, r7, #512 @ 0x200 + 8004032: f5a3 7394 sub.w r3, r3, #296 @ 0x128 + 8004036: 681b ldr r3, [r3, #0] + 8004038: fa93 f2a3 rbit r2, r3 + 800403c: f507 7300 add.w r3, r7, #512 @ 0x200 + 8004040: f5a3 7396 sub.w r3, r3, #300 @ 0x12c + 8004044: 601a str r2, [r3, #0] + 8004046: f507 7300 add.w r3, r7, #512 @ 0x200 + 800404a: f5a3 7398 sub.w r3, r3, #304 @ 0x130 + 800404e: 2202 movs r2, #2 + 8004050: 601a str r2, [r3, #0] + 8004052: f507 7300 add.w r3, r7, #512 @ 0x200 + 8004056: f5a3 7398 sub.w r3, r3, #304 @ 0x130 + 800405a: 681b ldr r3, [r3, #0] + 800405c: fa93 f2a3 rbit r2, r3 + 8004060: f507 7300 add.w r3, r7, #512 @ 0x200 + 8004064: f5a3 739a sub.w r3, r3, #308 @ 0x134 + 8004068: 601a str r2, [r3, #0] while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) - 8004032: 4b41 ldr r3, [pc, #260] @ (8004138 ) - 8004034: 6a5a ldr r2, [r3, #36] @ 0x24 - 8004036: f507 7300 add.w r3, r7, #512 @ 0x200 - 800403a: f5a3 739c sub.w r3, r3, #312 @ 0x138 - 800403e: 2102 movs r1, #2 - 8004040: 6019 str r1, [r3, #0] - 8004042: f507 7300 add.w r3, r7, #512 @ 0x200 - 8004046: f5a3 739c sub.w r3, r3, #312 @ 0x138 - 800404a: 681b ldr r3, [r3, #0] - 800404c: fa93 f1a3 rbit r1, r3 - 8004050: f507 7300 add.w r3, r7, #512 @ 0x200 - 8004054: f5a3 739e sub.w r3, r3, #316 @ 0x13c - 8004058: 6019 str r1, [r3, #0] + 800406a: 4b41 ldr r3, [pc, #260] @ (8004170 ) + 800406c: 6a5a ldr r2, [r3, #36] @ 0x24 + 800406e: f507 7300 add.w r3, r7, #512 @ 0x200 + 8004072: f5a3 739c sub.w r3, r3, #312 @ 0x138 + 8004076: 2102 movs r1, #2 + 8004078: 6019 str r1, [r3, #0] + 800407a: f507 7300 add.w r3, r7, #512 @ 0x200 + 800407e: f5a3 739c sub.w r3, r3, #312 @ 0x138 + 8004082: 681b ldr r3, [r3, #0] + 8004084: fa93 f1a3 rbit r1, r3 + 8004088: f507 7300 add.w r3, r7, #512 @ 0x200 + 800408c: f5a3 739e sub.w r3, r3, #316 @ 0x13c + 8004090: 6019 str r1, [r3, #0] return result; - 800405a: f507 7300 add.w r3, r7, #512 @ 0x200 - 800405e: f5a3 739e sub.w r3, r3, #316 @ 0x13c - 8004062: 681b ldr r3, [r3, #0] - 8004064: fab3 f383 clz r3, r3 - 8004068: b2db uxtb r3, r3 - 800406a: f043 0360 orr.w r3, r3, #96 @ 0x60 - 800406e: b2db uxtb r3, r3 - 8004070: f003 031f and.w r3, r3, #31 - 8004074: 2101 movs r1, #1 - 8004076: fa01 f303 lsl.w r3, r1, r3 - 800407a: 4013 ands r3, r2 - 800407c: 2b00 cmp r3, #0 - 800407e: d197 bne.n 8003fb0 + 8004092: f507 7300 add.w r3, r7, #512 @ 0x200 + 8004096: f5a3 739e sub.w r3, r3, #316 @ 0x13c + 800409a: 681b ldr r3, [r3, #0] + 800409c: fab3 f383 clz r3, r3 + 80040a0: b2db uxtb r3, r3 + 80040a2: f043 0360 orr.w r3, r3, #96 @ 0x60 + 80040a6: b2db uxtb r3, r3 + 80040a8: f003 031f and.w r3, r3, #31 + 80040ac: 2101 movs r1, #1 + 80040ae: fa01 f303 lsl.w r3, r1, r3 + 80040b2: 4013 ands r3, r2 + 80040b4: 2b00 cmp r3, #0 + 80040b6: d197 bne.n 8003fe8 } } } } /*------------------------------ LSE Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) - 8004080: f507 7300 add.w r3, r7, #512 @ 0x200 - 8004084: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc - 8004088: 681b ldr r3, [r3, #0] - 800408a: 681b ldr r3, [r3, #0] - 800408c: f003 0304 and.w r3, r3, #4 - 8004090: 2b00 cmp r3, #0 - 8004092: f000 81a1 beq.w 80043d8 + 80040b8: f507 7300 add.w r3, r7, #512 @ 0x200 + 80040bc: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc + 80040c0: 681b ldr r3, [r3, #0] + 80040c2: 681b ldr r3, [r3, #0] + 80040c4: f003 0304 and.w r3, r3, #4 + 80040c8: 2b00 cmp r3, #0 + 80040ca: f000 81a1 beq.w 8004410 { FlagStatus pwrclkchanged = RESET; - 8004096: 2300 movs r3, #0 - 8004098: f887 31ff strb.w r3, [r7, #511] @ 0x1ff + 80040ce: 2300 movs r3, #0 + 80040d0: f887 31ff strb.w r3, [r7, #511] @ 0x1ff /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if(__HAL_RCC_PWR_IS_CLK_DISABLED()) - 800409c: 4b26 ldr r3, [pc, #152] @ (8004138 ) - 800409e: 69db ldr r3, [r3, #28] - 80040a0: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 - 80040a4: 2b00 cmp r3, #0 - 80040a6: d116 bne.n 80040d6 + 80040d4: 4b26 ldr r3, [pc, #152] @ (8004170 ) + 80040d6: 69db ldr r3, [r3, #28] + 80040d8: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 80040dc: 2b00 cmp r3, #0 + 80040de: d116 bne.n 800410e { __HAL_RCC_PWR_CLK_ENABLE(); - 80040a8: 4b23 ldr r3, [pc, #140] @ (8004138 ) - 80040aa: 69db ldr r3, [r3, #28] - 80040ac: 4a22 ldr r2, [pc, #136] @ (8004138 ) - 80040ae: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 - 80040b2: 61d3 str r3, [r2, #28] - 80040b4: 4b20 ldr r3, [pc, #128] @ (8004138 ) - 80040b6: 69db ldr r3, [r3, #28] - 80040b8: f003 5280 and.w r2, r3, #268435456 @ 0x10000000 - 80040bc: f507 7300 add.w r3, r7, #512 @ 0x200 - 80040c0: f5a3 73fc sub.w r3, r3, #504 @ 0x1f8 - 80040c4: 601a str r2, [r3, #0] - 80040c6: f507 7300 add.w r3, r7, #512 @ 0x200 - 80040ca: f5a3 73fc sub.w r3, r3, #504 @ 0x1f8 - 80040ce: 681b ldr r3, [r3, #0] + 80040e0: 4b23 ldr r3, [pc, #140] @ (8004170 ) + 80040e2: 69db ldr r3, [r3, #28] + 80040e4: 4a22 ldr r2, [pc, #136] @ (8004170 ) + 80040e6: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 80040ea: 61d3 str r3, [r2, #28] + 80040ec: 4b20 ldr r3, [pc, #128] @ (8004170 ) + 80040ee: 69db ldr r3, [r3, #28] + 80040f0: f003 5280 and.w r2, r3, #268435456 @ 0x10000000 + 80040f4: f507 7300 add.w r3, r7, #512 @ 0x200 + 80040f8: f5a3 73fc sub.w r3, r3, #504 @ 0x1f8 + 80040fc: 601a str r2, [r3, #0] + 80040fe: f507 7300 add.w r3, r7, #512 @ 0x200 + 8004102: f5a3 73fc sub.w r3, r3, #504 @ 0x1f8 + 8004106: 681b ldr r3, [r3, #0] pwrclkchanged = SET; - 80040d0: 2301 movs r3, #1 - 80040d2: f887 31ff strb.w r3, [r7, #511] @ 0x1ff + 8004108: 2301 movs r3, #1 + 800410a: f887 31ff strb.w r3, [r7, #511] @ 0x1ff } if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) - 80040d6: 4b1a ldr r3, [pc, #104] @ (8004140 ) - 80040d8: 681b ldr r3, [r3, #0] - 80040da: f403 7380 and.w r3, r3, #256 @ 0x100 - 80040de: 2b00 cmp r3, #0 - 80040e0: d11a bne.n 8004118 + 800410e: 4b1a ldr r3, [pc, #104] @ (8004178 ) + 8004110: 681b ldr r3, [r3, #0] + 8004112: f403 7380 and.w r3, r3, #256 @ 0x100 + 8004116: 2b00 cmp r3, #0 + 8004118: d11a bne.n 8004150 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); - 80040e2: 4b17 ldr r3, [pc, #92] @ (8004140 ) - 80040e4: 681b ldr r3, [r3, #0] - 80040e6: 4a16 ldr r2, [pc, #88] @ (8004140 ) - 80040e8: f443 7380 orr.w r3, r3, #256 @ 0x100 - 80040ec: 6013 str r3, [r2, #0] + 800411a: 4b17 ldr r3, [pc, #92] @ (8004178 ) + 800411c: 681b ldr r3, [r3, #0] + 800411e: 4a16 ldr r2, [pc, #88] @ (8004178 ) + 8004120: f443 7380 orr.w r3, r3, #256 @ 0x100 + 8004124: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); - 80040ee: f7fd f983 bl 80013f8 - 80040f2: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8 + 8004126: f7fd f983 bl 8001430 + 800412a: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8 while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) - 80040f6: e009 b.n 800410c + 800412e: e009 b.n 8004144 { if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) - 80040f8: f7fd f97e bl 80013f8 - 80040fc: 4602 mov r2, r0 - 80040fe: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8 - 8004102: 1ad3 subs r3, r2, r3 - 8004104: 2b64 cmp r3, #100 @ 0x64 - 8004106: d901 bls.n 800410c + 8004130: f7fd f97e bl 8001430 + 8004134: 4602 mov r2, r0 + 8004136: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8 + 800413a: 1ad3 subs r3, r2, r3 + 800413c: 2b64 cmp r3, #100 @ 0x64 + 800413e: d901 bls.n 8004144 { return HAL_TIMEOUT; - 8004108: 2303 movs r3, #3 - 800410a: e3b1 b.n 8004870 + 8004140: 2303 movs r3, #3 + 8004142: e3b1 b.n 80048a8 while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) - 800410c: 4b0c ldr r3, [pc, #48] @ (8004140 ) - 800410e: 681b ldr r3, [r3, #0] - 8004110: f403 7380 and.w r3, r3, #256 @ 0x100 - 8004114: 2b00 cmp r3, #0 - 8004116: d0ef beq.n 80040f8 + 8004144: 4b0c ldr r3, [pc, #48] @ (8004178 ) + 8004146: 681b ldr r3, [r3, #0] + 8004148: f403 7380 and.w r3, r3, #256 @ 0x100 + 800414c: 2b00 cmp r3, #0 + 800414e: d0ef beq.n 8004130 } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); - 8004118: f507 7300 add.w r3, r7, #512 @ 0x200 - 800411c: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc - 8004120: 681b ldr r3, [r3, #0] - 8004122: 68db ldr r3, [r3, #12] - 8004124: 2b01 cmp r3, #1 - 8004126: d10d bne.n 8004144 - 8004128: 4b03 ldr r3, [pc, #12] @ (8004138 ) - 800412a: 6a1b ldr r3, [r3, #32] - 800412c: 4a02 ldr r2, [pc, #8] @ (8004138 ) - 800412e: f043 0301 orr.w r3, r3, #1 - 8004132: 6213 str r3, [r2, #32] - 8004134: e03c b.n 80041b0 - 8004136: bf00 nop - 8004138: 40021000 .word 0x40021000 - 800413c: 10908120 .word 0x10908120 - 8004140: 40007000 .word 0x40007000 - 8004144: f507 7300 add.w r3, r7, #512 @ 0x200 - 8004148: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc - 800414c: 681b ldr r3, [r3, #0] - 800414e: 68db ldr r3, [r3, #12] - 8004150: 2b00 cmp r3, #0 - 8004152: d10c bne.n 800416e - 8004154: 4bc1 ldr r3, [pc, #772] @ (800445c ) - 8004156: 6a1b ldr r3, [r3, #32] - 8004158: 4ac0 ldr r2, [pc, #768] @ (800445c ) - 800415a: f023 0301 bic.w r3, r3, #1 - 800415e: 6213 str r3, [r2, #32] - 8004160: 4bbe ldr r3, [pc, #760] @ (800445c ) + 8004150: f507 7300 add.w r3, r7, #512 @ 0x200 + 8004154: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc + 8004158: 681b ldr r3, [r3, #0] + 800415a: 68db ldr r3, [r3, #12] + 800415c: 2b01 cmp r3, #1 + 800415e: d10d bne.n 800417c + 8004160: 4b03 ldr r3, [pc, #12] @ (8004170 ) 8004162: 6a1b ldr r3, [r3, #32] - 8004164: 4abd ldr r2, [pc, #756] @ (800445c ) - 8004166: f023 0304 bic.w r3, r3, #4 + 8004164: 4a02 ldr r2, [pc, #8] @ (8004170 ) + 8004166: f043 0301 orr.w r3, r3, #1 800416a: 6213 str r3, [r2, #32] - 800416c: e020 b.n 80041b0 - 800416e: f507 7300 add.w r3, r7, #512 @ 0x200 - 8004172: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc - 8004176: 681b ldr r3, [r3, #0] - 8004178: 68db ldr r3, [r3, #12] - 800417a: 2b05 cmp r3, #5 - 800417c: d10c bne.n 8004198 - 800417e: 4bb7 ldr r3, [pc, #732] @ (800445c ) - 8004180: 6a1b ldr r3, [r3, #32] - 8004182: 4ab6 ldr r2, [pc, #728] @ (800445c ) - 8004184: f043 0304 orr.w r3, r3, #4 - 8004188: 6213 str r3, [r2, #32] - 800418a: 4bb4 ldr r3, [pc, #720] @ (800445c ) - 800418c: 6a1b ldr r3, [r3, #32] - 800418e: 4ab3 ldr r2, [pc, #716] @ (800445c ) - 8004190: f043 0301 orr.w r3, r3, #1 - 8004194: 6213 str r3, [r2, #32] - 8004196: e00b b.n 80041b0 - 8004198: 4bb0 ldr r3, [pc, #704] @ (800445c ) + 800416c: e03c b.n 80041e8 + 800416e: bf00 nop + 8004170: 40021000 .word 0x40021000 + 8004174: 10908120 .word 0x10908120 + 8004178: 40007000 .word 0x40007000 + 800417c: f507 7300 add.w r3, r7, #512 @ 0x200 + 8004180: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc + 8004184: 681b ldr r3, [r3, #0] + 8004186: 68db ldr r3, [r3, #12] + 8004188: 2b00 cmp r3, #0 + 800418a: d10c bne.n 80041a6 + 800418c: 4bc1 ldr r3, [pc, #772] @ (8004494 ) + 800418e: 6a1b ldr r3, [r3, #32] + 8004190: 4ac0 ldr r2, [pc, #768] @ (8004494 ) + 8004192: f023 0301 bic.w r3, r3, #1 + 8004196: 6213 str r3, [r2, #32] + 8004198: 4bbe ldr r3, [pc, #760] @ (8004494 ) 800419a: 6a1b ldr r3, [r3, #32] - 800419c: 4aaf ldr r2, [pc, #700] @ (800445c ) - 800419e: f023 0301 bic.w r3, r3, #1 + 800419c: 4abd ldr r2, [pc, #756] @ (8004494 ) + 800419e: f023 0304 bic.w r3, r3, #4 80041a2: 6213 str r3, [r2, #32] - 80041a4: 4bad ldr r3, [pc, #692] @ (800445c ) - 80041a6: 6a1b ldr r3, [r3, #32] - 80041a8: 4aac ldr r2, [pc, #688] @ (800445c ) - 80041aa: f023 0304 bic.w r3, r3, #4 - 80041ae: 6213 str r3, [r2, #32] + 80041a4: e020 b.n 80041e8 + 80041a6: f507 7300 add.w r3, r7, #512 @ 0x200 + 80041aa: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc + 80041ae: 681b ldr r3, [r3, #0] + 80041b0: 68db ldr r3, [r3, #12] + 80041b2: 2b05 cmp r3, #5 + 80041b4: d10c bne.n 80041d0 + 80041b6: 4bb7 ldr r3, [pc, #732] @ (8004494 ) + 80041b8: 6a1b ldr r3, [r3, #32] + 80041ba: 4ab6 ldr r2, [pc, #728] @ (8004494 ) + 80041bc: f043 0304 orr.w r3, r3, #4 + 80041c0: 6213 str r3, [r2, #32] + 80041c2: 4bb4 ldr r3, [pc, #720] @ (8004494 ) + 80041c4: 6a1b ldr r3, [r3, #32] + 80041c6: 4ab3 ldr r2, [pc, #716] @ (8004494 ) + 80041c8: f043 0301 orr.w r3, r3, #1 + 80041cc: 6213 str r3, [r2, #32] + 80041ce: e00b b.n 80041e8 + 80041d0: 4bb0 ldr r3, [pc, #704] @ (8004494 ) + 80041d2: 6a1b ldr r3, [r3, #32] + 80041d4: 4aaf ldr r2, [pc, #700] @ (8004494 ) + 80041d6: f023 0301 bic.w r3, r3, #1 + 80041da: 6213 str r3, [r2, #32] + 80041dc: 4bad ldr r3, [pc, #692] @ (8004494 ) + 80041de: 6a1b ldr r3, [r3, #32] + 80041e0: 4aac ldr r2, [pc, #688] @ (8004494 ) + 80041e2: f023 0304 bic.w r3, r3, #4 + 80041e6: 6213 str r3, [r2, #32] /* Check the LSE State */ if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF) - 80041b0: f507 7300 add.w r3, r7, #512 @ 0x200 - 80041b4: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc - 80041b8: 681b ldr r3, [r3, #0] - 80041ba: 68db ldr r3, [r3, #12] - 80041bc: 2b00 cmp r3, #0 - 80041be: f000 8081 beq.w 80042c4 + 80041e8: f507 7300 add.w r3, r7, #512 @ 0x200 + 80041ec: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc + 80041f0: 681b ldr r3, [r3, #0] + 80041f2: 68db ldr r3, [r3, #12] + 80041f4: 2b00 cmp r3, #0 + 80041f6: f000 8081 beq.w 80042fc { /* Get Start Tick */ tickstart = HAL_GetTick(); - 80041c2: f7fd f919 bl 80013f8 - 80041c6: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8 + 80041fa: f7fd f919 bl 8001430 + 80041fe: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8 /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) - 80041ca: e00b b.n 80041e4 + 8004202: e00b b.n 800421c { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) - 80041cc: f7fd f914 bl 80013f8 - 80041d0: 4602 mov r2, r0 - 80041d2: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8 - 80041d6: 1ad3 subs r3, r2, r3 - 80041d8: f241 3288 movw r2, #5000 @ 0x1388 - 80041dc: 4293 cmp r3, r2 - 80041de: d901 bls.n 80041e4 + 8004204: f7fd f914 bl 8001430 + 8004208: 4602 mov r2, r0 + 800420a: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8 + 800420e: 1ad3 subs r3, r2, r3 + 8004210: f241 3288 movw r2, #5000 @ 0x1388 + 8004214: 4293 cmp r3, r2 + 8004216: d901 bls.n 800421c { return HAL_TIMEOUT; - 80041e0: 2303 movs r3, #3 - 80041e2: e345 b.n 8004870 - 80041e4: f507 7300 add.w r3, r7, #512 @ 0x200 - 80041e8: f5a3 73a0 sub.w r3, r3, #320 @ 0x140 - 80041ec: 2202 movs r2, #2 - 80041ee: 601a str r2, [r3, #0] + 8004218: 2303 movs r3, #3 + 800421a: e345 b.n 80048a8 + 800421c: f507 7300 add.w r3, r7, #512 @ 0x200 + 8004220: f5a3 73a0 sub.w r3, r3, #320 @ 0x140 + 8004224: 2202 movs r2, #2 + 8004226: 601a str r2, [r3, #0] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 80041f0: f507 7300 add.w r3, r7, #512 @ 0x200 - 80041f4: f5a3 73a0 sub.w r3, r3, #320 @ 0x140 - 80041f8: 681b ldr r3, [r3, #0] - 80041fa: fa93 f2a3 rbit r2, r3 - 80041fe: f507 7300 add.w r3, r7, #512 @ 0x200 - 8004202: f5a3 73a2 sub.w r3, r3, #324 @ 0x144 - 8004206: 601a str r2, [r3, #0] - 8004208: f507 7300 add.w r3, r7, #512 @ 0x200 - 800420c: f5a3 73a4 sub.w r3, r3, #328 @ 0x148 - 8004210: 2202 movs r2, #2 - 8004212: 601a str r2, [r3, #0] - 8004214: f507 7300 add.w r3, r7, #512 @ 0x200 - 8004218: f5a3 73a4 sub.w r3, r3, #328 @ 0x148 - 800421c: 681b ldr r3, [r3, #0] - 800421e: fa93 f2a3 rbit r2, r3 - 8004222: f507 7300 add.w r3, r7, #512 @ 0x200 - 8004226: f5a3 73a6 sub.w r3, r3, #332 @ 0x14c - 800422a: 601a str r2, [r3, #0] + 8004228: f507 7300 add.w r3, r7, #512 @ 0x200 + 800422c: f5a3 73a0 sub.w r3, r3, #320 @ 0x140 + 8004230: 681b ldr r3, [r3, #0] + 8004232: fa93 f2a3 rbit r2, r3 + 8004236: f507 7300 add.w r3, r7, #512 @ 0x200 + 800423a: f5a3 73a2 sub.w r3, r3, #324 @ 0x144 + 800423e: 601a str r2, [r3, #0] + 8004240: f507 7300 add.w r3, r7, #512 @ 0x200 + 8004244: f5a3 73a4 sub.w r3, r3, #328 @ 0x148 + 8004248: 2202 movs r2, #2 + 800424a: 601a str r2, [r3, #0] + 800424c: f507 7300 add.w r3, r7, #512 @ 0x200 + 8004250: f5a3 73a4 sub.w r3, r3, #328 @ 0x148 + 8004254: 681b ldr r3, [r3, #0] + 8004256: fa93 f2a3 rbit r2, r3 + 800425a: f507 7300 add.w r3, r7, #512 @ 0x200 + 800425e: f5a3 73a6 sub.w r3, r3, #332 @ 0x14c + 8004262: 601a str r2, [r3, #0] return result; - 800422c: f507 7300 add.w r3, r7, #512 @ 0x200 - 8004230: f5a3 73a6 sub.w r3, r3, #332 @ 0x14c - 8004234: 681b ldr r3, [r3, #0] + 8004264: f507 7300 add.w r3, r7, #512 @ 0x200 + 8004268: f5a3 73a6 sub.w r3, r3, #332 @ 0x14c + 800426c: 681b ldr r3, [r3, #0] while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) - 8004236: fab3 f383 clz r3, r3 - 800423a: b2db uxtb r3, r3 - 800423c: 095b lsrs r3, r3, #5 - 800423e: b2db uxtb r3, r3 - 8004240: f043 0302 orr.w r3, r3, #2 - 8004244: b2db uxtb r3, r3 - 8004246: 2b02 cmp r3, #2 - 8004248: d102 bne.n 8004250 - 800424a: 4b84 ldr r3, [pc, #528] @ (800445c ) - 800424c: 6a1b ldr r3, [r3, #32] - 800424e: e013 b.n 8004278 - 8004250: f507 7300 add.w r3, r7, #512 @ 0x200 - 8004254: f5a3 73a8 sub.w r3, r3, #336 @ 0x150 - 8004258: 2202 movs r2, #2 - 800425a: 601a str r2, [r3, #0] + 800426e: fab3 f383 clz r3, r3 + 8004272: b2db uxtb r3, r3 + 8004274: 095b lsrs r3, r3, #5 + 8004276: b2db uxtb r3, r3 + 8004278: f043 0302 orr.w r3, r3, #2 + 800427c: b2db uxtb r3, r3 + 800427e: 2b02 cmp r3, #2 + 8004280: d102 bne.n 8004288 + 8004282: 4b84 ldr r3, [pc, #528] @ (8004494 ) + 8004284: 6a1b ldr r3, [r3, #32] + 8004286: e013 b.n 80042b0 + 8004288: f507 7300 add.w r3, r7, #512 @ 0x200 + 800428c: f5a3 73a8 sub.w r3, r3, #336 @ 0x150 + 8004290: 2202 movs r2, #2 + 8004292: 601a str r2, [r3, #0] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 800425c: f507 7300 add.w r3, r7, #512 @ 0x200 - 8004260: f5a3 73a8 sub.w r3, r3, #336 @ 0x150 - 8004264: 681b ldr r3, [r3, #0] - 8004266: fa93 f2a3 rbit r2, r3 - 800426a: f507 7300 add.w r3, r7, #512 @ 0x200 - 800426e: f5a3 73aa sub.w r3, r3, #340 @ 0x154 - 8004272: 601a str r2, [r3, #0] - 8004274: 4b79 ldr r3, [pc, #484] @ (800445c ) - 8004276: 6a5b ldr r3, [r3, #36] @ 0x24 - 8004278: f507 7200 add.w r2, r7, #512 @ 0x200 - 800427c: f5a2 72ac sub.w r2, r2, #344 @ 0x158 - 8004280: 2102 movs r1, #2 - 8004282: 6011 str r1, [r2, #0] - 8004284: f507 7200 add.w r2, r7, #512 @ 0x200 - 8004288: f5a2 72ac sub.w r2, r2, #344 @ 0x158 - 800428c: 6812 ldr r2, [r2, #0] - 800428e: fa92 f1a2 rbit r1, r2 - 8004292: f507 7200 add.w r2, r7, #512 @ 0x200 - 8004296: f5a2 72ae sub.w r2, r2, #348 @ 0x15c - 800429a: 6011 str r1, [r2, #0] + 8004294: f507 7300 add.w r3, r7, #512 @ 0x200 + 8004298: f5a3 73a8 sub.w r3, r3, #336 @ 0x150 + 800429c: 681b ldr r3, [r3, #0] + 800429e: fa93 f2a3 rbit r2, r3 + 80042a2: f507 7300 add.w r3, r7, #512 @ 0x200 + 80042a6: f5a3 73aa sub.w r3, r3, #340 @ 0x154 + 80042aa: 601a str r2, [r3, #0] + 80042ac: 4b79 ldr r3, [pc, #484] @ (8004494 ) + 80042ae: 6a5b ldr r3, [r3, #36] @ 0x24 + 80042b0: f507 7200 add.w r2, r7, #512 @ 0x200 + 80042b4: f5a2 72ac sub.w r2, r2, #344 @ 0x158 + 80042b8: 2102 movs r1, #2 + 80042ba: 6011 str r1, [r2, #0] + 80042bc: f507 7200 add.w r2, r7, #512 @ 0x200 + 80042c0: f5a2 72ac sub.w r2, r2, #344 @ 0x158 + 80042c4: 6812 ldr r2, [r2, #0] + 80042c6: fa92 f1a2 rbit r1, r2 + 80042ca: f507 7200 add.w r2, r7, #512 @ 0x200 + 80042ce: f5a2 72ae sub.w r2, r2, #348 @ 0x15c + 80042d2: 6011 str r1, [r2, #0] return result; - 800429c: f507 7200 add.w r2, r7, #512 @ 0x200 - 80042a0: f5a2 72ae sub.w r2, r2, #348 @ 0x15c - 80042a4: 6812 ldr r2, [r2, #0] - 80042a6: fab2 f282 clz r2, r2 - 80042aa: b2d2 uxtb r2, r2 - 80042ac: f042 0240 orr.w r2, r2, #64 @ 0x40 - 80042b0: b2d2 uxtb r2, r2 - 80042b2: f002 021f and.w r2, r2, #31 - 80042b6: 2101 movs r1, #1 - 80042b8: fa01 f202 lsl.w r2, r1, r2 - 80042bc: 4013 ands r3, r2 - 80042be: 2b00 cmp r3, #0 - 80042c0: d084 beq.n 80041cc - 80042c2: e07f b.n 80043c4 + 80042d4: f507 7200 add.w r2, r7, #512 @ 0x200 + 80042d8: f5a2 72ae sub.w r2, r2, #348 @ 0x15c + 80042dc: 6812 ldr r2, [r2, #0] + 80042de: fab2 f282 clz r2, r2 + 80042e2: b2d2 uxtb r2, r2 + 80042e4: f042 0240 orr.w r2, r2, #64 @ 0x40 + 80042e8: b2d2 uxtb r2, r2 + 80042ea: f002 021f and.w r2, r2, #31 + 80042ee: 2101 movs r1, #1 + 80042f0: fa01 f202 lsl.w r2, r1, r2 + 80042f4: 4013 ands r3, r2 + 80042f6: 2b00 cmp r3, #0 + 80042f8: d084 beq.n 8004204 + 80042fa: e07f b.n 80043fc } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); - 80042c4: f7fd f898 bl 80013f8 - 80042c8: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8 + 80042fc: f7fd f898 bl 8001430 + 8004300: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8 /* Wait till LSE is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) - 80042cc: e00b b.n 80042e6 + 8004304: e00b b.n 800431e { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) - 80042ce: f7fd f893 bl 80013f8 - 80042d2: 4602 mov r2, r0 - 80042d4: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8 - 80042d8: 1ad3 subs r3, r2, r3 - 80042da: f241 3288 movw r2, #5000 @ 0x1388 - 80042de: 4293 cmp r3, r2 - 80042e0: d901 bls.n 80042e6 + 8004306: f7fd f893 bl 8001430 + 800430a: 4602 mov r2, r0 + 800430c: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8 + 8004310: 1ad3 subs r3, r2, r3 + 8004312: f241 3288 movw r2, #5000 @ 0x1388 + 8004316: 4293 cmp r3, r2 + 8004318: d901 bls.n 800431e { return HAL_TIMEOUT; - 80042e2: 2303 movs r3, #3 - 80042e4: e2c4 b.n 8004870 - 80042e6: f507 7300 add.w r3, r7, #512 @ 0x200 - 80042ea: f5a3 73b0 sub.w r3, r3, #352 @ 0x160 - 80042ee: 2202 movs r2, #2 - 80042f0: 601a str r2, [r3, #0] + 800431a: 2303 movs r3, #3 + 800431c: e2c4 b.n 80048a8 + 800431e: f507 7300 add.w r3, r7, #512 @ 0x200 + 8004322: f5a3 73b0 sub.w r3, r3, #352 @ 0x160 + 8004326: 2202 movs r2, #2 + 8004328: 601a str r2, [r3, #0] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 80042f2: f507 7300 add.w r3, r7, #512 @ 0x200 - 80042f6: f5a3 73b0 sub.w r3, r3, #352 @ 0x160 - 80042fa: 681b ldr r3, [r3, #0] - 80042fc: fa93 f2a3 rbit r2, r3 - 8004300: f507 7300 add.w r3, r7, #512 @ 0x200 - 8004304: f5a3 73b2 sub.w r3, r3, #356 @ 0x164 - 8004308: 601a str r2, [r3, #0] - 800430a: f507 7300 add.w r3, r7, #512 @ 0x200 - 800430e: f5a3 73b4 sub.w r3, r3, #360 @ 0x168 - 8004312: 2202 movs r2, #2 - 8004314: 601a str r2, [r3, #0] - 8004316: f507 7300 add.w r3, r7, #512 @ 0x200 - 800431a: f5a3 73b4 sub.w r3, r3, #360 @ 0x168 - 800431e: 681b ldr r3, [r3, #0] - 8004320: fa93 f2a3 rbit r2, r3 - 8004324: f507 7300 add.w r3, r7, #512 @ 0x200 - 8004328: f5a3 73b6 sub.w r3, r3, #364 @ 0x16c - 800432c: 601a str r2, [r3, #0] + 800432a: f507 7300 add.w r3, r7, #512 @ 0x200 + 800432e: f5a3 73b0 sub.w r3, r3, #352 @ 0x160 + 8004332: 681b ldr r3, [r3, #0] + 8004334: fa93 f2a3 rbit r2, r3 + 8004338: f507 7300 add.w r3, r7, #512 @ 0x200 + 800433c: f5a3 73b2 sub.w r3, r3, #356 @ 0x164 + 8004340: 601a str r2, [r3, #0] + 8004342: f507 7300 add.w r3, r7, #512 @ 0x200 + 8004346: f5a3 73b4 sub.w r3, r3, #360 @ 0x168 + 800434a: 2202 movs r2, #2 + 800434c: 601a str r2, [r3, #0] + 800434e: f507 7300 add.w r3, r7, #512 @ 0x200 + 8004352: f5a3 73b4 sub.w r3, r3, #360 @ 0x168 + 8004356: 681b ldr r3, [r3, #0] + 8004358: fa93 f2a3 rbit r2, r3 + 800435c: f507 7300 add.w r3, r7, #512 @ 0x200 + 8004360: f5a3 73b6 sub.w r3, r3, #364 @ 0x16c + 8004364: 601a str r2, [r3, #0] return result; - 800432e: f507 7300 add.w r3, r7, #512 @ 0x200 - 8004332: f5a3 73b6 sub.w r3, r3, #364 @ 0x16c - 8004336: 681b ldr r3, [r3, #0] + 8004366: f507 7300 add.w r3, r7, #512 @ 0x200 + 800436a: f5a3 73b6 sub.w r3, r3, #364 @ 0x16c + 800436e: 681b ldr r3, [r3, #0] while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) - 8004338: fab3 f383 clz r3, r3 - 800433c: b2db uxtb r3, r3 - 800433e: 095b lsrs r3, r3, #5 - 8004340: b2db uxtb r3, r3 - 8004342: f043 0302 orr.w r3, r3, #2 - 8004346: b2db uxtb r3, r3 - 8004348: 2b02 cmp r3, #2 - 800434a: d102 bne.n 8004352 - 800434c: 4b43 ldr r3, [pc, #268] @ (800445c ) - 800434e: 6a1b ldr r3, [r3, #32] - 8004350: e013 b.n 800437a - 8004352: f507 7300 add.w r3, r7, #512 @ 0x200 - 8004356: f5a3 73b8 sub.w r3, r3, #368 @ 0x170 - 800435a: 2202 movs r2, #2 - 800435c: 601a str r2, [r3, #0] + 8004370: fab3 f383 clz r3, r3 + 8004374: b2db uxtb r3, r3 + 8004376: 095b lsrs r3, r3, #5 + 8004378: b2db uxtb r3, r3 + 800437a: f043 0302 orr.w r3, r3, #2 + 800437e: b2db uxtb r3, r3 + 8004380: 2b02 cmp r3, #2 + 8004382: d102 bne.n 800438a + 8004384: 4b43 ldr r3, [pc, #268] @ (8004494 ) + 8004386: 6a1b ldr r3, [r3, #32] + 8004388: e013 b.n 80043b2 + 800438a: f507 7300 add.w r3, r7, #512 @ 0x200 + 800438e: f5a3 73b8 sub.w r3, r3, #368 @ 0x170 + 8004392: 2202 movs r2, #2 + 8004394: 601a str r2, [r3, #0] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 800435e: f507 7300 add.w r3, r7, #512 @ 0x200 - 8004362: f5a3 73b8 sub.w r3, r3, #368 @ 0x170 - 8004366: 681b ldr r3, [r3, #0] - 8004368: fa93 f2a3 rbit r2, r3 - 800436c: f507 7300 add.w r3, r7, #512 @ 0x200 - 8004370: f5a3 73ba sub.w r3, r3, #372 @ 0x174 - 8004374: 601a str r2, [r3, #0] - 8004376: 4b39 ldr r3, [pc, #228] @ (800445c ) - 8004378: 6a5b ldr r3, [r3, #36] @ 0x24 - 800437a: f507 7200 add.w r2, r7, #512 @ 0x200 - 800437e: f5a2 72bc sub.w r2, r2, #376 @ 0x178 - 8004382: 2102 movs r1, #2 - 8004384: 6011 str r1, [r2, #0] - 8004386: f507 7200 add.w r2, r7, #512 @ 0x200 - 800438a: f5a2 72bc sub.w r2, r2, #376 @ 0x178 - 800438e: 6812 ldr r2, [r2, #0] - 8004390: fa92 f1a2 rbit r1, r2 - 8004394: f507 7200 add.w r2, r7, #512 @ 0x200 - 8004398: f5a2 72be sub.w r2, r2, #380 @ 0x17c - 800439c: 6011 str r1, [r2, #0] + 8004396: f507 7300 add.w r3, r7, #512 @ 0x200 + 800439a: f5a3 73b8 sub.w r3, r3, #368 @ 0x170 + 800439e: 681b ldr r3, [r3, #0] + 80043a0: fa93 f2a3 rbit r2, r3 + 80043a4: f507 7300 add.w r3, r7, #512 @ 0x200 + 80043a8: f5a3 73ba sub.w r3, r3, #372 @ 0x174 + 80043ac: 601a str r2, [r3, #0] + 80043ae: 4b39 ldr r3, [pc, #228] @ (8004494 ) + 80043b0: 6a5b ldr r3, [r3, #36] @ 0x24 + 80043b2: f507 7200 add.w r2, r7, #512 @ 0x200 + 80043b6: f5a2 72bc sub.w r2, r2, #376 @ 0x178 + 80043ba: 2102 movs r1, #2 + 80043bc: 6011 str r1, [r2, #0] + 80043be: f507 7200 add.w r2, r7, #512 @ 0x200 + 80043c2: f5a2 72bc sub.w r2, r2, #376 @ 0x178 + 80043c6: 6812 ldr r2, [r2, #0] + 80043c8: fa92 f1a2 rbit r1, r2 + 80043cc: f507 7200 add.w r2, r7, #512 @ 0x200 + 80043d0: f5a2 72be sub.w r2, r2, #380 @ 0x17c + 80043d4: 6011 str r1, [r2, #0] return result; - 800439e: f507 7200 add.w r2, r7, #512 @ 0x200 - 80043a2: f5a2 72be sub.w r2, r2, #380 @ 0x17c - 80043a6: 6812 ldr r2, [r2, #0] - 80043a8: fab2 f282 clz r2, r2 - 80043ac: b2d2 uxtb r2, r2 - 80043ae: f042 0240 orr.w r2, r2, #64 @ 0x40 - 80043b2: b2d2 uxtb r2, r2 - 80043b4: f002 021f and.w r2, r2, #31 - 80043b8: 2101 movs r1, #1 - 80043ba: fa01 f202 lsl.w r2, r1, r2 - 80043be: 4013 ands r3, r2 - 80043c0: 2b00 cmp r3, #0 - 80043c2: d184 bne.n 80042ce + 80043d6: f507 7200 add.w r2, r7, #512 @ 0x200 + 80043da: f5a2 72be sub.w r2, r2, #380 @ 0x17c + 80043de: 6812 ldr r2, [r2, #0] + 80043e0: fab2 f282 clz r2, r2 + 80043e4: b2d2 uxtb r2, r2 + 80043e6: f042 0240 orr.w r2, r2, #64 @ 0x40 + 80043ea: b2d2 uxtb r2, r2 + 80043ec: f002 021f and.w r2, r2, #31 + 80043f0: 2101 movs r1, #1 + 80043f2: fa01 f202 lsl.w r2, r1, r2 + 80043f6: 4013 ands r3, r2 + 80043f8: 2b00 cmp r3, #0 + 80043fa: d184 bne.n 8004306 } } } /* Require to disable power clock if necessary */ if(pwrclkchanged == SET) - 80043c4: f897 31ff ldrb.w r3, [r7, #511] @ 0x1ff - 80043c8: 2b01 cmp r3, #1 - 80043ca: d105 bne.n 80043d8 + 80043fc: f897 31ff ldrb.w r3, [r7, #511] @ 0x1ff + 8004400: 2b01 cmp r3, #1 + 8004402: d105 bne.n 8004410 { __HAL_RCC_PWR_CLK_DISABLE(); - 80043cc: 4b23 ldr r3, [pc, #140] @ (800445c ) - 80043ce: 69db ldr r3, [r3, #28] - 80043d0: 4a22 ldr r2, [pc, #136] @ (800445c ) - 80043d2: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 - 80043d6: 61d3 str r3, [r2, #28] + 8004404: 4b23 ldr r3, [pc, #140] @ (8004494 ) + 8004406: 69db ldr r3, [r3, #28] + 8004408: 4a22 ldr r2, [pc, #136] @ (8004494 ) + 800440a: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 + 800440e: 61d3 str r3, [r2, #28] } /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) - 80043d8: f507 7300 add.w r3, r7, #512 @ 0x200 - 80043dc: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc - 80043e0: 681b ldr r3, [r3, #0] - 80043e2: 69db ldr r3, [r3, #28] - 80043e4: 2b00 cmp r3, #0 - 80043e6: f000 8242 beq.w 800486e + 8004410: f507 7300 add.w r3, r7, #512 @ 0x200 + 8004414: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc + 8004418: 681b ldr r3, [r3, #0] + 800441a: 69db ldr r3, [r3, #28] + 800441c: 2b00 cmp r3, #0 + 800441e: f000 8242 beq.w 80048a6 { /* Check if the PLL is used as system clock or not */ if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) - 80043ea: 4b1c ldr r3, [pc, #112] @ (800445c ) - 80043ec: 685b ldr r3, [r3, #4] - 80043ee: f003 030c and.w r3, r3, #12 - 80043f2: 2b08 cmp r3, #8 - 80043f4: f000 8213 beq.w 800481e + 8004422: 4b1c ldr r3, [pc, #112] @ (8004494 ) + 8004424: 685b ldr r3, [r3, #4] + 8004426: f003 030c and.w r3, r3, #12 + 800442a: 2b08 cmp r3, #8 + 800442c: f000 8213 beq.w 8004856 { if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) - 80043f8: f507 7300 add.w r3, r7, #512 @ 0x200 - 80043fc: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc - 8004400: 681b ldr r3, [r3, #0] - 8004402: 69db ldr r3, [r3, #28] - 8004404: 2b02 cmp r3, #2 - 8004406: f040 8162 bne.w 80046ce - 800440a: f507 7300 add.w r3, r7, #512 @ 0x200 - 800440e: f5a3 73c0 sub.w r3, r3, #384 @ 0x180 - 8004412: f04f 7280 mov.w r2, #16777216 @ 0x1000000 - 8004416: 601a str r2, [r3, #0] - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8004418: f507 7300 add.w r3, r7, #512 @ 0x200 - 800441c: f5a3 73c0 sub.w r3, r3, #384 @ 0x180 - 8004420: 681b ldr r3, [r3, #0] - 8004422: fa93 f2a3 rbit r2, r3 - 8004426: f507 7300 add.w r3, r7, #512 @ 0x200 - 800442a: f5a3 73c2 sub.w r3, r3, #388 @ 0x184 - 800442e: 601a str r2, [r3, #0] - return result; 8004430: f507 7300 add.w r3, r7, #512 @ 0x200 - 8004434: f5a3 73c2 sub.w r3, r3, #388 @ 0x184 + 8004434: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc 8004438: 681b ldr r3, [r3, #0] + 800443a: 69db ldr r3, [r3, #28] + 800443c: 2b02 cmp r3, #2 + 800443e: f040 8162 bne.w 8004706 + 8004442: f507 7300 add.w r3, r7, #512 @ 0x200 + 8004446: f5a3 73c0 sub.w r3, r3, #384 @ 0x180 + 800444a: f04f 7280 mov.w r2, #16777216 @ 0x1000000 + 800444e: 601a str r2, [r3, #0] + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + 8004450: f507 7300 add.w r3, r7, #512 @ 0x200 + 8004454: f5a3 73c0 sub.w r3, r3, #384 @ 0x180 + 8004458: 681b ldr r3, [r3, #0] + 800445a: fa93 f2a3 rbit r2, r3 + 800445e: f507 7300 add.w r3, r7, #512 @ 0x200 + 8004462: f5a3 73c2 sub.w r3, r3, #388 @ 0x184 + 8004466: 601a str r2, [r3, #0] + return result; + 8004468: f507 7300 add.w r3, r7, #512 @ 0x200 + 800446c: f5a3 73c2 sub.w r3, r3, #388 @ 0x184 + 8004470: 681b ldr r3, [r3, #0] #if defined(RCC_CFGR_PLLSRC_HSI_PREDIV) assert_param(IS_RCC_PREDIV(RCC_OscInitStruct->PLL.PREDIV)); #endif /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); - 800443a: fab3 f383 clz r3, r3 - 800443e: b2db uxtb r3, r3 - 8004440: f103 5384 add.w r3, r3, #276824064 @ 0x10800000 - 8004444: f503 1384 add.w r3, r3, #1081344 @ 0x108000 - 8004448: 009b lsls r3, r3, #2 - 800444a: 461a mov r2, r3 - 800444c: 2300 movs r3, #0 - 800444e: 6013 str r3, [r2, #0] + 8004472: fab3 f383 clz r3, r3 + 8004476: b2db uxtb r3, r3 + 8004478: f103 5384 add.w r3, r3, #276824064 @ 0x10800000 + 800447c: f503 1384 add.w r3, r3, #1081344 @ 0x108000 + 8004480: 009b lsls r3, r3, #2 + 8004482: 461a mov r2, r3 + 8004484: 2300 movs r3, #0 + 8004486: 6013 str r3, [r2, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); - 8004450: f7fc ffd2 bl 80013f8 - 8004454: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8 + 8004488: f7fc ffd2 bl 8001430 + 800448c: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8 /* Wait till PLL is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) - 8004458: e00c b.n 8004474 - 800445a: bf00 nop - 800445c: 40021000 .word 0x40021000 + 8004490: e00c b.n 80044ac + 8004492: bf00 nop + 8004494: 40021000 .word 0x40021000 { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) - 8004460: f7fc ffca bl 80013f8 - 8004464: 4602 mov r2, r0 - 8004466: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8 - 800446a: 1ad3 subs r3, r2, r3 - 800446c: 2b02 cmp r3, #2 - 800446e: d901 bls.n 8004474 + 8004498: f7fc ffca bl 8001430 + 800449c: 4602 mov r2, r0 + 800449e: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8 + 80044a2: 1ad3 subs r3, r2, r3 + 80044a4: 2b02 cmp r3, #2 + 80044a6: d901 bls.n 80044ac { return HAL_TIMEOUT; - 8004470: 2303 movs r3, #3 - 8004472: e1fd b.n 8004870 - 8004474: f507 7300 add.w r3, r7, #512 @ 0x200 - 8004478: f5a3 73c4 sub.w r3, r3, #392 @ 0x188 - 800447c: f04f 7200 mov.w r2, #33554432 @ 0x2000000 - 8004480: 601a str r2, [r3, #0] + 80044a8: 2303 movs r3, #3 + 80044aa: e1fd b.n 80048a8 + 80044ac: f507 7300 add.w r3, r7, #512 @ 0x200 + 80044b0: f5a3 73c4 sub.w r3, r3, #392 @ 0x188 + 80044b4: f04f 7200 mov.w r2, #33554432 @ 0x2000000 + 80044b8: 601a str r2, [r3, #0] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8004482: f507 7300 add.w r3, r7, #512 @ 0x200 - 8004486: f5a3 73c4 sub.w r3, r3, #392 @ 0x188 - 800448a: 681b ldr r3, [r3, #0] - 800448c: fa93 f2a3 rbit r2, r3 - 8004490: f507 7300 add.w r3, r7, #512 @ 0x200 - 8004494: f5a3 73c6 sub.w r3, r3, #396 @ 0x18c - 8004498: 601a str r2, [r3, #0] + 80044ba: f507 7300 add.w r3, r7, #512 @ 0x200 + 80044be: f5a3 73c4 sub.w r3, r3, #392 @ 0x188 + 80044c2: 681b ldr r3, [r3, #0] + 80044c4: fa93 f2a3 rbit r2, r3 + 80044c8: f507 7300 add.w r3, r7, #512 @ 0x200 + 80044cc: f5a3 73c6 sub.w r3, r3, #396 @ 0x18c + 80044d0: 601a str r2, [r3, #0] return result; - 800449a: f507 7300 add.w r3, r7, #512 @ 0x200 - 800449e: f5a3 73c6 sub.w r3, r3, #396 @ 0x18c - 80044a2: 681b ldr r3, [r3, #0] + 80044d2: f507 7300 add.w r3, r7, #512 @ 0x200 + 80044d6: f5a3 73c6 sub.w r3, r3, #396 @ 0x18c + 80044da: 681b ldr r3, [r3, #0] while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) - 80044a4: fab3 f383 clz r3, r3 - 80044a8: b2db uxtb r3, r3 - 80044aa: 095b lsrs r3, r3, #5 - 80044ac: b2db uxtb r3, r3 - 80044ae: f043 0301 orr.w r3, r3, #1 - 80044b2: b2db uxtb r3, r3 - 80044b4: 2b01 cmp r3, #1 - 80044b6: d102 bne.n 80044be - 80044b8: 4bb0 ldr r3, [pc, #704] @ (800477c ) - 80044ba: 681b ldr r3, [r3, #0] - 80044bc: e027 b.n 800450e - 80044be: f507 7300 add.w r3, r7, #512 @ 0x200 - 80044c2: f5a3 73c8 sub.w r3, r3, #400 @ 0x190 - 80044c6: f04f 7200 mov.w r2, #33554432 @ 0x2000000 - 80044ca: 601a str r2, [r3, #0] + 80044dc: fab3 f383 clz r3, r3 + 80044e0: b2db uxtb r3, r3 + 80044e2: 095b lsrs r3, r3, #5 + 80044e4: b2db uxtb r3, r3 + 80044e6: f043 0301 orr.w r3, r3, #1 + 80044ea: b2db uxtb r3, r3 + 80044ec: 2b01 cmp r3, #1 + 80044ee: d102 bne.n 80044f6 + 80044f0: 4bb0 ldr r3, [pc, #704] @ (80047b4 ) + 80044f2: 681b ldr r3, [r3, #0] + 80044f4: e027 b.n 8004546 + 80044f6: f507 7300 add.w r3, r7, #512 @ 0x200 + 80044fa: f5a3 73c8 sub.w r3, r3, #400 @ 0x190 + 80044fe: f04f 7200 mov.w r2, #33554432 @ 0x2000000 + 8004502: 601a str r2, [r3, #0] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 80044cc: f507 7300 add.w r3, r7, #512 @ 0x200 - 80044d0: f5a3 73c8 sub.w r3, r3, #400 @ 0x190 - 80044d4: 681b ldr r3, [r3, #0] - 80044d6: fa93 f2a3 rbit r2, r3 - 80044da: f507 7300 add.w r3, r7, #512 @ 0x200 - 80044de: f5a3 73ca sub.w r3, r3, #404 @ 0x194 - 80044e2: 601a str r2, [r3, #0] - 80044e4: f507 7300 add.w r3, r7, #512 @ 0x200 - 80044e8: f5a3 73cc sub.w r3, r3, #408 @ 0x198 - 80044ec: f04f 7200 mov.w r2, #33554432 @ 0x2000000 - 80044f0: 601a str r2, [r3, #0] - 80044f2: f507 7300 add.w r3, r7, #512 @ 0x200 - 80044f6: f5a3 73cc sub.w r3, r3, #408 @ 0x198 - 80044fa: 681b ldr r3, [r3, #0] - 80044fc: fa93 f2a3 rbit r2, r3 - 8004500: f507 7300 add.w r3, r7, #512 @ 0x200 - 8004504: f5a3 73ce sub.w r3, r3, #412 @ 0x19c - 8004508: 601a str r2, [r3, #0] - 800450a: 4b9c ldr r3, [pc, #624] @ (800477c ) - 800450c: 6a5b ldr r3, [r3, #36] @ 0x24 - 800450e: f507 7200 add.w r2, r7, #512 @ 0x200 - 8004512: f5a2 72d0 sub.w r2, r2, #416 @ 0x1a0 - 8004516: f04f 7100 mov.w r1, #33554432 @ 0x2000000 - 800451a: 6011 str r1, [r2, #0] - 800451c: f507 7200 add.w r2, r7, #512 @ 0x200 - 8004520: f5a2 72d0 sub.w r2, r2, #416 @ 0x1a0 - 8004524: 6812 ldr r2, [r2, #0] - 8004526: fa92 f1a2 rbit r1, r2 - 800452a: f507 7200 add.w r2, r7, #512 @ 0x200 - 800452e: f5a2 72d2 sub.w r2, r2, #420 @ 0x1a4 - 8004532: 6011 str r1, [r2, #0] + 8004504: f507 7300 add.w r3, r7, #512 @ 0x200 + 8004508: f5a3 73c8 sub.w r3, r3, #400 @ 0x190 + 800450c: 681b ldr r3, [r3, #0] + 800450e: fa93 f2a3 rbit r2, r3 + 8004512: f507 7300 add.w r3, r7, #512 @ 0x200 + 8004516: f5a3 73ca sub.w r3, r3, #404 @ 0x194 + 800451a: 601a str r2, [r3, #0] + 800451c: f507 7300 add.w r3, r7, #512 @ 0x200 + 8004520: f5a3 73cc sub.w r3, r3, #408 @ 0x198 + 8004524: f04f 7200 mov.w r2, #33554432 @ 0x2000000 + 8004528: 601a str r2, [r3, #0] + 800452a: f507 7300 add.w r3, r7, #512 @ 0x200 + 800452e: f5a3 73cc sub.w r3, r3, #408 @ 0x198 + 8004532: 681b ldr r3, [r3, #0] + 8004534: fa93 f2a3 rbit r2, r3 + 8004538: f507 7300 add.w r3, r7, #512 @ 0x200 + 800453c: f5a3 73ce sub.w r3, r3, #412 @ 0x19c + 8004540: 601a str r2, [r3, #0] + 8004542: 4b9c ldr r3, [pc, #624] @ (80047b4 ) + 8004544: 6a5b ldr r3, [r3, #36] @ 0x24 + 8004546: f507 7200 add.w r2, r7, #512 @ 0x200 + 800454a: f5a2 72d0 sub.w r2, r2, #416 @ 0x1a0 + 800454e: f04f 7100 mov.w r1, #33554432 @ 0x2000000 + 8004552: 6011 str r1, [r2, #0] + 8004554: f507 7200 add.w r2, r7, #512 @ 0x200 + 8004558: f5a2 72d0 sub.w r2, r2, #416 @ 0x1a0 + 800455c: 6812 ldr r2, [r2, #0] + 800455e: fa92 f1a2 rbit r1, r2 + 8004562: f507 7200 add.w r2, r7, #512 @ 0x200 + 8004566: f5a2 72d2 sub.w r2, r2, #420 @ 0x1a4 + 800456a: 6011 str r1, [r2, #0] return result; - 8004534: f507 7200 add.w r2, r7, #512 @ 0x200 - 8004538: f5a2 72d2 sub.w r2, r2, #420 @ 0x1a4 - 800453c: 6812 ldr r2, [r2, #0] - 800453e: fab2 f282 clz r2, r2 - 8004542: b2d2 uxtb r2, r2 - 8004544: f042 0220 orr.w r2, r2, #32 - 8004548: b2d2 uxtb r2, r2 - 800454a: f002 021f and.w r2, r2, #31 - 800454e: 2101 movs r1, #1 - 8004550: fa01 f202 lsl.w r2, r1, r2 - 8004554: 4013 ands r3, r2 - 8004556: 2b00 cmp r3, #0 - 8004558: d182 bne.n 8004460 + 800456c: f507 7200 add.w r2, r7, #512 @ 0x200 + 8004570: f5a2 72d2 sub.w r2, r2, #420 @ 0x1a4 + 8004574: 6812 ldr r2, [r2, #0] + 8004576: fab2 f282 clz r2, r2 + 800457a: b2d2 uxtb r2, r2 + 800457c: f042 0220 orr.w r2, r2, #32 + 8004580: b2d2 uxtb r2, r2 + 8004582: f002 021f and.w r2, r2, #31 + 8004586: 2101 movs r1, #1 + 8004588: fa01 f202 lsl.w r2, r1, r2 + 800458c: 4013 ands r3, r2 + 800458e: 2b00 cmp r3, #0 + 8004590: d182 bne.n 8004498 __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, RCC_OscInitStruct->PLL.PREDIV, RCC_OscInitStruct->PLL.PLLMUL); #else /* Configure the main PLL clock source and multiplication factor. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, - 800455a: 4b88 ldr r3, [pc, #544] @ (800477c ) - 800455c: 685b ldr r3, [r3, #4] - 800455e: f423 1274 bic.w r2, r3, #3997696 @ 0x3d0000 - 8004562: f507 7300 add.w r3, r7, #512 @ 0x200 - 8004566: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc - 800456a: 681b ldr r3, [r3, #0] - 800456c: 6a59 ldr r1, [r3, #36] @ 0x24 - 800456e: f507 7300 add.w r3, r7, #512 @ 0x200 - 8004572: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc - 8004576: 681b ldr r3, [r3, #0] - 8004578: 6a1b ldr r3, [r3, #32] - 800457a: 430b orrs r3, r1 - 800457c: 497f ldr r1, [pc, #508] @ (800477c ) - 800457e: 4313 orrs r3, r2 - 8004580: 604b str r3, [r1, #4] - 8004582: f507 7300 add.w r3, r7, #512 @ 0x200 - 8004586: f5a3 73d4 sub.w r3, r3, #424 @ 0x1a8 - 800458a: f04f 7280 mov.w r2, #16777216 @ 0x1000000 - 800458e: 601a str r2, [r3, #0] + 8004592: 4b88 ldr r3, [pc, #544] @ (80047b4 ) + 8004594: 685b ldr r3, [r3, #4] + 8004596: f423 1274 bic.w r2, r3, #3997696 @ 0x3d0000 + 800459a: f507 7300 add.w r3, r7, #512 @ 0x200 + 800459e: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc + 80045a2: 681b ldr r3, [r3, #0] + 80045a4: 6a59 ldr r1, [r3, #36] @ 0x24 + 80045a6: f507 7300 add.w r3, r7, #512 @ 0x200 + 80045aa: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc + 80045ae: 681b ldr r3, [r3, #0] + 80045b0: 6a1b ldr r3, [r3, #32] + 80045b2: 430b orrs r3, r1 + 80045b4: 497f ldr r1, [pc, #508] @ (80047b4 ) + 80045b6: 4313 orrs r3, r2 + 80045b8: 604b str r3, [r1, #4] + 80045ba: f507 7300 add.w r3, r7, #512 @ 0x200 + 80045be: f5a3 73d4 sub.w r3, r3, #424 @ 0x1a8 + 80045c2: f04f 7280 mov.w r2, #16777216 @ 0x1000000 + 80045c6: 601a str r2, [r3, #0] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8004590: f507 7300 add.w r3, r7, #512 @ 0x200 - 8004594: f5a3 73d4 sub.w r3, r3, #424 @ 0x1a8 - 8004598: 681b ldr r3, [r3, #0] - 800459a: fa93 f2a3 rbit r2, r3 - 800459e: f507 7300 add.w r3, r7, #512 @ 0x200 - 80045a2: f5a3 73d6 sub.w r3, r3, #428 @ 0x1ac - 80045a6: 601a str r2, [r3, #0] + 80045c8: f507 7300 add.w r3, r7, #512 @ 0x200 + 80045cc: f5a3 73d4 sub.w r3, r3, #424 @ 0x1a8 + 80045d0: 681b ldr r3, [r3, #0] + 80045d2: fa93 f2a3 rbit r2, r3 + 80045d6: f507 7300 add.w r3, r7, #512 @ 0x200 + 80045da: f5a3 73d6 sub.w r3, r3, #428 @ 0x1ac + 80045de: 601a str r2, [r3, #0] return result; - 80045a8: f507 7300 add.w r3, r7, #512 @ 0x200 - 80045ac: f5a3 73d6 sub.w r3, r3, #428 @ 0x1ac - 80045b0: 681b ldr r3, [r3, #0] + 80045e0: f507 7300 add.w r3, r7, #512 @ 0x200 + 80045e4: f5a3 73d6 sub.w r3, r3, #428 @ 0x1ac + 80045e8: 681b ldr r3, [r3, #0] RCC_OscInitStruct->PLL.PLLMUL); #endif /* RCC_CFGR_PLLSRC_HSI_PREDIV */ /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); - 80045b2: fab3 f383 clz r3, r3 - 80045b6: b2db uxtb r3, r3 - 80045b8: f103 5384 add.w r3, r3, #276824064 @ 0x10800000 - 80045bc: f503 1384 add.w r3, r3, #1081344 @ 0x108000 - 80045c0: 009b lsls r3, r3, #2 - 80045c2: 461a mov r2, r3 - 80045c4: 2301 movs r3, #1 - 80045c6: 6013 str r3, [r2, #0] + 80045ea: fab3 f383 clz r3, r3 + 80045ee: b2db uxtb r3, r3 + 80045f0: f103 5384 add.w r3, r3, #276824064 @ 0x10800000 + 80045f4: f503 1384 add.w r3, r3, #1081344 @ 0x108000 + 80045f8: 009b lsls r3, r3, #2 + 80045fa: 461a mov r2, r3 + 80045fc: 2301 movs r3, #1 + 80045fe: 6013 str r3, [r2, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); - 80045c8: f7fc ff16 bl 80013f8 - 80045cc: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8 + 8004600: f7fc ff16 bl 8001430 + 8004604: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8 /* Wait till PLL is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) - 80045d0: e009 b.n 80045e6 + 8004608: e009 b.n 800461e { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) - 80045d2: f7fc ff11 bl 80013f8 - 80045d6: 4602 mov r2, r0 - 80045d8: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8 - 80045dc: 1ad3 subs r3, r2, r3 - 80045de: 2b02 cmp r3, #2 - 80045e0: d901 bls.n 80045e6 + 800460a: f7fc ff11 bl 8001430 + 800460e: 4602 mov r2, r0 + 8004610: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8 + 8004614: 1ad3 subs r3, r2, r3 + 8004616: 2b02 cmp r3, #2 + 8004618: d901 bls.n 800461e { return HAL_TIMEOUT; - 80045e2: 2303 movs r3, #3 - 80045e4: e144 b.n 8004870 - 80045e6: f507 7300 add.w r3, r7, #512 @ 0x200 - 80045ea: f5a3 73d8 sub.w r3, r3, #432 @ 0x1b0 - 80045ee: f04f 7200 mov.w r2, #33554432 @ 0x2000000 - 80045f2: 601a str r2, [r3, #0] + 800461a: 2303 movs r3, #3 + 800461c: e144 b.n 80048a8 + 800461e: f507 7300 add.w r3, r7, #512 @ 0x200 + 8004622: f5a3 73d8 sub.w r3, r3, #432 @ 0x1b0 + 8004626: f04f 7200 mov.w r2, #33554432 @ 0x2000000 + 800462a: 601a str r2, [r3, #0] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 80045f4: f507 7300 add.w r3, r7, #512 @ 0x200 - 80045f8: f5a3 73d8 sub.w r3, r3, #432 @ 0x1b0 - 80045fc: 681b ldr r3, [r3, #0] - 80045fe: fa93 f2a3 rbit r2, r3 - 8004602: f507 7300 add.w r3, r7, #512 @ 0x200 - 8004606: f5a3 73da sub.w r3, r3, #436 @ 0x1b4 - 800460a: 601a str r2, [r3, #0] + 800462c: f507 7300 add.w r3, r7, #512 @ 0x200 + 8004630: f5a3 73d8 sub.w r3, r3, #432 @ 0x1b0 + 8004634: 681b ldr r3, [r3, #0] + 8004636: fa93 f2a3 rbit r2, r3 + 800463a: f507 7300 add.w r3, r7, #512 @ 0x200 + 800463e: f5a3 73da sub.w r3, r3, #436 @ 0x1b4 + 8004642: 601a str r2, [r3, #0] return result; - 800460c: f507 7300 add.w r3, r7, #512 @ 0x200 - 8004610: f5a3 73da sub.w r3, r3, #436 @ 0x1b4 - 8004614: 681b ldr r3, [r3, #0] + 8004644: f507 7300 add.w r3, r7, #512 @ 0x200 + 8004648: f5a3 73da sub.w r3, r3, #436 @ 0x1b4 + 800464c: 681b ldr r3, [r3, #0] while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) - 8004616: fab3 f383 clz r3, r3 - 800461a: b2db uxtb r3, r3 - 800461c: 095b lsrs r3, r3, #5 - 800461e: b2db uxtb r3, r3 - 8004620: f043 0301 orr.w r3, r3, #1 - 8004624: b2db uxtb r3, r3 - 8004626: 2b01 cmp r3, #1 - 8004628: d102 bne.n 8004630 - 800462a: 4b54 ldr r3, [pc, #336] @ (800477c ) - 800462c: 681b ldr r3, [r3, #0] - 800462e: e027 b.n 8004680 - 8004630: f507 7300 add.w r3, r7, #512 @ 0x200 - 8004634: f5a3 73dc sub.w r3, r3, #440 @ 0x1b8 - 8004638: f04f 7200 mov.w r2, #33554432 @ 0x2000000 - 800463c: 601a str r2, [r3, #0] + 800464e: fab3 f383 clz r3, r3 + 8004652: b2db uxtb r3, r3 + 8004654: 095b lsrs r3, r3, #5 + 8004656: b2db uxtb r3, r3 + 8004658: f043 0301 orr.w r3, r3, #1 + 800465c: b2db uxtb r3, r3 + 800465e: 2b01 cmp r3, #1 + 8004660: d102 bne.n 8004668 + 8004662: 4b54 ldr r3, [pc, #336] @ (80047b4 ) + 8004664: 681b ldr r3, [r3, #0] + 8004666: e027 b.n 80046b8 + 8004668: f507 7300 add.w r3, r7, #512 @ 0x200 + 800466c: f5a3 73dc sub.w r3, r3, #440 @ 0x1b8 + 8004670: f04f 7200 mov.w r2, #33554432 @ 0x2000000 + 8004674: 601a str r2, [r3, #0] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 800463e: f507 7300 add.w r3, r7, #512 @ 0x200 - 8004642: f5a3 73dc sub.w r3, r3, #440 @ 0x1b8 - 8004646: 681b ldr r3, [r3, #0] - 8004648: fa93 f2a3 rbit r2, r3 - 800464c: f507 7300 add.w r3, r7, #512 @ 0x200 - 8004650: f5a3 73de sub.w r3, r3, #444 @ 0x1bc - 8004654: 601a str r2, [r3, #0] - 8004656: f507 7300 add.w r3, r7, #512 @ 0x200 - 800465a: f5a3 73e0 sub.w r3, r3, #448 @ 0x1c0 - 800465e: f04f 7200 mov.w r2, #33554432 @ 0x2000000 - 8004662: 601a str r2, [r3, #0] - 8004664: f507 7300 add.w r3, r7, #512 @ 0x200 - 8004668: f5a3 73e0 sub.w r3, r3, #448 @ 0x1c0 - 800466c: 681b ldr r3, [r3, #0] - 800466e: fa93 f2a3 rbit r2, r3 - 8004672: f507 7300 add.w r3, r7, #512 @ 0x200 - 8004676: f5a3 73e2 sub.w r3, r3, #452 @ 0x1c4 - 800467a: 601a str r2, [r3, #0] - 800467c: 4b3f ldr r3, [pc, #252] @ (800477c ) - 800467e: 6a5b ldr r3, [r3, #36] @ 0x24 - 8004680: f507 7200 add.w r2, r7, #512 @ 0x200 - 8004684: f5a2 72e4 sub.w r2, r2, #456 @ 0x1c8 - 8004688: f04f 7100 mov.w r1, #33554432 @ 0x2000000 - 800468c: 6011 str r1, [r2, #0] - 800468e: f507 7200 add.w r2, r7, #512 @ 0x200 - 8004692: f5a2 72e4 sub.w r2, r2, #456 @ 0x1c8 - 8004696: 6812 ldr r2, [r2, #0] - 8004698: fa92 f1a2 rbit r1, r2 - 800469c: f507 7200 add.w r2, r7, #512 @ 0x200 - 80046a0: f5a2 72e6 sub.w r2, r2, #460 @ 0x1cc - 80046a4: 6011 str r1, [r2, #0] + 8004676: f507 7300 add.w r3, r7, #512 @ 0x200 + 800467a: f5a3 73dc sub.w r3, r3, #440 @ 0x1b8 + 800467e: 681b ldr r3, [r3, #0] + 8004680: fa93 f2a3 rbit r2, r3 + 8004684: f507 7300 add.w r3, r7, #512 @ 0x200 + 8004688: f5a3 73de sub.w r3, r3, #444 @ 0x1bc + 800468c: 601a str r2, [r3, #0] + 800468e: f507 7300 add.w r3, r7, #512 @ 0x200 + 8004692: f5a3 73e0 sub.w r3, r3, #448 @ 0x1c0 + 8004696: f04f 7200 mov.w r2, #33554432 @ 0x2000000 + 800469a: 601a str r2, [r3, #0] + 800469c: f507 7300 add.w r3, r7, #512 @ 0x200 + 80046a0: f5a3 73e0 sub.w r3, r3, #448 @ 0x1c0 + 80046a4: 681b ldr r3, [r3, #0] + 80046a6: fa93 f2a3 rbit r2, r3 + 80046aa: f507 7300 add.w r3, r7, #512 @ 0x200 + 80046ae: f5a3 73e2 sub.w r3, r3, #452 @ 0x1c4 + 80046b2: 601a str r2, [r3, #0] + 80046b4: 4b3f ldr r3, [pc, #252] @ (80047b4 ) + 80046b6: 6a5b ldr r3, [r3, #36] @ 0x24 + 80046b8: f507 7200 add.w r2, r7, #512 @ 0x200 + 80046bc: f5a2 72e4 sub.w r2, r2, #456 @ 0x1c8 + 80046c0: f04f 7100 mov.w r1, #33554432 @ 0x2000000 + 80046c4: 6011 str r1, [r2, #0] + 80046c6: f507 7200 add.w r2, r7, #512 @ 0x200 + 80046ca: f5a2 72e4 sub.w r2, r2, #456 @ 0x1c8 + 80046ce: 6812 ldr r2, [r2, #0] + 80046d0: fa92 f1a2 rbit r1, r2 + 80046d4: f507 7200 add.w r2, r7, #512 @ 0x200 + 80046d8: f5a2 72e6 sub.w r2, r2, #460 @ 0x1cc + 80046dc: 6011 str r1, [r2, #0] return result; - 80046a6: f507 7200 add.w r2, r7, #512 @ 0x200 - 80046aa: f5a2 72e6 sub.w r2, r2, #460 @ 0x1cc - 80046ae: 6812 ldr r2, [r2, #0] - 80046b0: fab2 f282 clz r2, r2 - 80046b4: b2d2 uxtb r2, r2 - 80046b6: f042 0220 orr.w r2, r2, #32 - 80046ba: b2d2 uxtb r2, r2 - 80046bc: f002 021f and.w r2, r2, #31 - 80046c0: 2101 movs r1, #1 - 80046c2: fa01 f202 lsl.w r2, r1, r2 - 80046c6: 4013 ands r3, r2 - 80046c8: 2b00 cmp r3, #0 - 80046ca: d082 beq.n 80045d2 - 80046cc: e0cf b.n 800486e - 80046ce: f507 7300 add.w r3, r7, #512 @ 0x200 - 80046d2: f5a3 73e8 sub.w r3, r3, #464 @ 0x1d0 - 80046d6: f04f 7280 mov.w r2, #16777216 @ 0x1000000 - 80046da: 601a str r2, [r3, #0] + 80046de: f507 7200 add.w r2, r7, #512 @ 0x200 + 80046e2: f5a2 72e6 sub.w r2, r2, #460 @ 0x1cc + 80046e6: 6812 ldr r2, [r2, #0] + 80046e8: fab2 f282 clz r2, r2 + 80046ec: b2d2 uxtb r2, r2 + 80046ee: f042 0220 orr.w r2, r2, #32 + 80046f2: b2d2 uxtb r2, r2 + 80046f4: f002 021f and.w r2, r2, #31 + 80046f8: 2101 movs r1, #1 + 80046fa: fa01 f202 lsl.w r2, r1, r2 + 80046fe: 4013 ands r3, r2 + 8004700: 2b00 cmp r3, #0 + 8004702: d082 beq.n 800460a + 8004704: e0cf b.n 80048a6 + 8004706: f507 7300 add.w r3, r7, #512 @ 0x200 + 800470a: f5a3 73e8 sub.w r3, r3, #464 @ 0x1d0 + 800470e: f04f 7280 mov.w r2, #16777216 @ 0x1000000 + 8004712: 601a str r2, [r3, #0] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 80046dc: f507 7300 add.w r3, r7, #512 @ 0x200 - 80046e0: f5a3 73e8 sub.w r3, r3, #464 @ 0x1d0 - 80046e4: 681b ldr r3, [r3, #0] - 80046e6: fa93 f2a3 rbit r2, r3 - 80046ea: f507 7300 add.w r3, r7, #512 @ 0x200 - 80046ee: f5a3 73ea sub.w r3, r3, #468 @ 0x1d4 - 80046f2: 601a str r2, [r3, #0] + 8004714: f507 7300 add.w r3, r7, #512 @ 0x200 + 8004718: f5a3 73e8 sub.w r3, r3, #464 @ 0x1d0 + 800471c: 681b ldr r3, [r3, #0] + 800471e: fa93 f2a3 rbit r2, r3 + 8004722: f507 7300 add.w r3, r7, #512 @ 0x200 + 8004726: f5a3 73ea sub.w r3, r3, #468 @ 0x1d4 + 800472a: 601a str r2, [r3, #0] return result; - 80046f4: f507 7300 add.w r3, r7, #512 @ 0x200 - 80046f8: f5a3 73ea sub.w r3, r3, #468 @ 0x1d4 - 80046fc: 681b ldr r3, [r3, #0] + 800472c: f507 7300 add.w r3, r7, #512 @ 0x200 + 8004730: f5a3 73ea sub.w r3, r3, #468 @ 0x1d4 + 8004734: 681b ldr r3, [r3, #0] } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); - 80046fe: fab3 f383 clz r3, r3 - 8004702: b2db uxtb r3, r3 - 8004704: f103 5384 add.w r3, r3, #276824064 @ 0x10800000 - 8004708: f503 1384 add.w r3, r3, #1081344 @ 0x108000 - 800470c: 009b lsls r3, r3, #2 - 800470e: 461a mov r2, r3 - 8004710: 2300 movs r3, #0 - 8004712: 6013 str r3, [r2, #0] + 8004736: fab3 f383 clz r3, r3 + 800473a: b2db uxtb r3, r3 + 800473c: f103 5384 add.w r3, r3, #276824064 @ 0x10800000 + 8004740: f503 1384 add.w r3, r3, #1081344 @ 0x108000 + 8004744: 009b lsls r3, r3, #2 + 8004746: 461a mov r2, r3 + 8004748: 2300 movs r3, #0 + 800474a: 6013 str r3, [r2, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); - 8004714: f7fc fe70 bl 80013f8 - 8004718: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8 + 800474c: f7fc fe70 bl 8001430 + 8004750: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8 /* Wait till PLL is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) - 800471c: e009 b.n 8004732 + 8004754: e009 b.n 800476a { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) - 800471e: f7fc fe6b bl 80013f8 - 8004722: 4602 mov r2, r0 - 8004724: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8 - 8004728: 1ad3 subs r3, r2, r3 - 800472a: 2b02 cmp r3, #2 - 800472c: d901 bls.n 8004732 + 8004756: f7fc fe6b bl 8001430 + 800475a: 4602 mov r2, r0 + 800475c: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8 + 8004760: 1ad3 subs r3, r2, r3 + 8004762: 2b02 cmp r3, #2 + 8004764: d901 bls.n 800476a { return HAL_TIMEOUT; - 800472e: 2303 movs r3, #3 - 8004730: e09e b.n 8004870 - 8004732: f507 7300 add.w r3, r7, #512 @ 0x200 - 8004736: f5a3 73ec sub.w r3, r3, #472 @ 0x1d8 - 800473a: f04f 7200 mov.w r2, #33554432 @ 0x2000000 - 800473e: 601a str r2, [r3, #0] + 8004766: 2303 movs r3, #3 + 8004768: e09e b.n 80048a8 + 800476a: f507 7300 add.w r3, r7, #512 @ 0x200 + 800476e: f5a3 73ec sub.w r3, r3, #472 @ 0x1d8 + 8004772: f04f 7200 mov.w r2, #33554432 @ 0x2000000 + 8004776: 601a str r2, [r3, #0] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8004740: f507 7300 add.w r3, r7, #512 @ 0x200 - 8004744: f5a3 73ec sub.w r3, r3, #472 @ 0x1d8 - 8004748: 681b ldr r3, [r3, #0] - 800474a: fa93 f2a3 rbit r2, r3 - 800474e: f507 7300 add.w r3, r7, #512 @ 0x200 - 8004752: f5a3 73ee sub.w r3, r3, #476 @ 0x1dc - 8004756: 601a str r2, [r3, #0] + 8004778: f507 7300 add.w r3, r7, #512 @ 0x200 + 800477c: f5a3 73ec sub.w r3, r3, #472 @ 0x1d8 + 8004780: 681b ldr r3, [r3, #0] + 8004782: fa93 f2a3 rbit r2, r3 + 8004786: f507 7300 add.w r3, r7, #512 @ 0x200 + 800478a: f5a3 73ee sub.w r3, r3, #476 @ 0x1dc + 800478e: 601a str r2, [r3, #0] return result; - 8004758: f507 7300 add.w r3, r7, #512 @ 0x200 - 800475c: f5a3 73ee sub.w r3, r3, #476 @ 0x1dc - 8004760: 681b ldr r3, [r3, #0] + 8004790: f507 7300 add.w r3, r7, #512 @ 0x200 + 8004794: f5a3 73ee sub.w r3, r3, #476 @ 0x1dc + 8004798: 681b ldr r3, [r3, #0] while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) - 8004762: fab3 f383 clz r3, r3 - 8004766: b2db uxtb r3, r3 - 8004768: 095b lsrs r3, r3, #5 - 800476a: b2db uxtb r3, r3 - 800476c: f043 0301 orr.w r3, r3, #1 - 8004770: b2db uxtb r3, r3 - 8004772: 2b01 cmp r3, #1 - 8004774: d104 bne.n 8004780 - 8004776: 4b01 ldr r3, [pc, #4] @ (800477c ) - 8004778: 681b ldr r3, [r3, #0] - 800477a: e029 b.n 80047d0 - 800477c: 40021000 .word 0x40021000 - 8004780: f507 7300 add.w r3, r7, #512 @ 0x200 - 8004784: f5a3 73f0 sub.w r3, r3, #480 @ 0x1e0 - 8004788: f04f 7200 mov.w r2, #33554432 @ 0x2000000 - 800478c: 601a str r2, [r3, #0] + 800479a: fab3 f383 clz r3, r3 + 800479e: b2db uxtb r3, r3 + 80047a0: 095b lsrs r3, r3, #5 + 80047a2: b2db uxtb r3, r3 + 80047a4: f043 0301 orr.w r3, r3, #1 + 80047a8: b2db uxtb r3, r3 + 80047aa: 2b01 cmp r3, #1 + 80047ac: d104 bne.n 80047b8 + 80047ae: 4b01 ldr r3, [pc, #4] @ (80047b4 ) + 80047b0: 681b ldr r3, [r3, #0] + 80047b2: e029 b.n 8004808 + 80047b4: 40021000 .word 0x40021000 + 80047b8: f507 7300 add.w r3, r7, #512 @ 0x200 + 80047bc: f5a3 73f0 sub.w r3, r3, #480 @ 0x1e0 + 80047c0: f04f 7200 mov.w r2, #33554432 @ 0x2000000 + 80047c4: 601a str r2, [r3, #0] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 800478e: f507 7300 add.w r3, r7, #512 @ 0x200 - 8004792: f5a3 73f0 sub.w r3, r3, #480 @ 0x1e0 - 8004796: 681b ldr r3, [r3, #0] - 8004798: fa93 f2a3 rbit r2, r3 - 800479c: f507 7300 add.w r3, r7, #512 @ 0x200 - 80047a0: f5a3 73f2 sub.w r3, r3, #484 @ 0x1e4 - 80047a4: 601a str r2, [r3, #0] - 80047a6: f507 7300 add.w r3, r7, #512 @ 0x200 - 80047aa: f5a3 73f4 sub.w r3, r3, #488 @ 0x1e8 - 80047ae: f04f 7200 mov.w r2, #33554432 @ 0x2000000 - 80047b2: 601a str r2, [r3, #0] - 80047b4: f507 7300 add.w r3, r7, #512 @ 0x200 - 80047b8: f5a3 73f4 sub.w r3, r3, #488 @ 0x1e8 - 80047bc: 681b ldr r3, [r3, #0] - 80047be: fa93 f2a3 rbit r2, r3 - 80047c2: f507 7300 add.w r3, r7, #512 @ 0x200 - 80047c6: f5a3 73f6 sub.w r3, r3, #492 @ 0x1ec - 80047ca: 601a str r2, [r3, #0] - 80047cc: 4b2b ldr r3, [pc, #172] @ (800487c ) - 80047ce: 6a5b ldr r3, [r3, #36] @ 0x24 - 80047d0: f507 7200 add.w r2, r7, #512 @ 0x200 - 80047d4: f5a2 72f8 sub.w r2, r2, #496 @ 0x1f0 - 80047d8: f04f 7100 mov.w r1, #33554432 @ 0x2000000 - 80047dc: 6011 str r1, [r2, #0] - 80047de: f507 7200 add.w r2, r7, #512 @ 0x200 - 80047e2: f5a2 72f8 sub.w r2, r2, #496 @ 0x1f0 - 80047e6: 6812 ldr r2, [r2, #0] - 80047e8: fa92 f1a2 rbit r1, r2 - 80047ec: f507 7200 add.w r2, r7, #512 @ 0x200 - 80047f0: f5a2 72fa sub.w r2, r2, #500 @ 0x1f4 - 80047f4: 6011 str r1, [r2, #0] + 80047c6: f507 7300 add.w r3, r7, #512 @ 0x200 + 80047ca: f5a3 73f0 sub.w r3, r3, #480 @ 0x1e0 + 80047ce: 681b ldr r3, [r3, #0] + 80047d0: fa93 f2a3 rbit r2, r3 + 80047d4: f507 7300 add.w r3, r7, #512 @ 0x200 + 80047d8: f5a3 73f2 sub.w r3, r3, #484 @ 0x1e4 + 80047dc: 601a str r2, [r3, #0] + 80047de: f507 7300 add.w r3, r7, #512 @ 0x200 + 80047e2: f5a3 73f4 sub.w r3, r3, #488 @ 0x1e8 + 80047e6: f04f 7200 mov.w r2, #33554432 @ 0x2000000 + 80047ea: 601a str r2, [r3, #0] + 80047ec: f507 7300 add.w r3, r7, #512 @ 0x200 + 80047f0: f5a3 73f4 sub.w r3, r3, #488 @ 0x1e8 + 80047f4: 681b ldr r3, [r3, #0] + 80047f6: fa93 f2a3 rbit r2, r3 + 80047fa: f507 7300 add.w r3, r7, #512 @ 0x200 + 80047fe: f5a3 73f6 sub.w r3, r3, #492 @ 0x1ec + 8004802: 601a str r2, [r3, #0] + 8004804: 4b2b ldr r3, [pc, #172] @ (80048b4 ) + 8004806: 6a5b ldr r3, [r3, #36] @ 0x24 + 8004808: f507 7200 add.w r2, r7, #512 @ 0x200 + 800480c: f5a2 72f8 sub.w r2, r2, #496 @ 0x1f0 + 8004810: f04f 7100 mov.w r1, #33554432 @ 0x2000000 + 8004814: 6011 str r1, [r2, #0] + 8004816: f507 7200 add.w r2, r7, #512 @ 0x200 + 800481a: f5a2 72f8 sub.w r2, r2, #496 @ 0x1f0 + 800481e: 6812 ldr r2, [r2, #0] + 8004820: fa92 f1a2 rbit r1, r2 + 8004824: f507 7200 add.w r2, r7, #512 @ 0x200 + 8004828: f5a2 72fa sub.w r2, r2, #500 @ 0x1f4 + 800482c: 6011 str r1, [r2, #0] return result; - 80047f6: f507 7200 add.w r2, r7, #512 @ 0x200 - 80047fa: f5a2 72fa sub.w r2, r2, #500 @ 0x1f4 - 80047fe: 6812 ldr r2, [r2, #0] - 8004800: fab2 f282 clz r2, r2 - 8004804: b2d2 uxtb r2, r2 - 8004806: f042 0220 orr.w r2, r2, #32 - 800480a: b2d2 uxtb r2, r2 - 800480c: f002 021f and.w r2, r2, #31 - 8004810: 2101 movs r1, #1 - 8004812: fa01 f202 lsl.w r2, r1, r2 - 8004816: 4013 ands r3, r2 - 8004818: 2b00 cmp r3, #0 - 800481a: d180 bne.n 800471e - 800481c: e027 b.n 800486e + 800482e: f507 7200 add.w r2, r7, #512 @ 0x200 + 8004832: f5a2 72fa sub.w r2, r2, #500 @ 0x1f4 + 8004836: 6812 ldr r2, [r2, #0] + 8004838: fab2 f282 clz r2, r2 + 800483c: b2d2 uxtb r2, r2 + 800483e: f042 0220 orr.w r2, r2, #32 + 8004842: b2d2 uxtb r2, r2 + 8004844: f002 021f and.w r2, r2, #31 + 8004848: 2101 movs r1, #1 + 800484a: fa01 f202 lsl.w r2, r1, r2 + 800484e: 4013 ands r3, r2 + 8004850: 2b00 cmp r3, #0 + 8004852: d180 bne.n 8004756 + 8004854: e027 b.n 80048a6 } } else { /* Check if there is a request to disable the PLL used as System clock source */ if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) - 800481e: f507 7300 add.w r3, r7, #512 @ 0x200 - 8004822: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc - 8004826: 681b ldr r3, [r3, #0] - 8004828: 69db ldr r3, [r3, #28] - 800482a: 2b01 cmp r3, #1 - 800482c: d101 bne.n 8004832 + 8004856: f507 7300 add.w r3, r7, #512 @ 0x200 + 800485a: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc + 800485e: 681b ldr r3, [r3, #0] + 8004860: 69db ldr r3, [r3, #28] + 8004862: 2b01 cmp r3, #1 + 8004864: d101 bne.n 800486a { return HAL_ERROR; - 800482e: 2301 movs r3, #1 - 8004830: e01e b.n 8004870 + 8004866: 2301 movs r3, #1 + 8004868: e01e b.n 80048a8 } else { /* Do not return HAL_ERROR if request repeats the current configuration */ pll_config = RCC->CFGR; - 8004832: 4b12 ldr r3, [pc, #72] @ (800487c ) - 8004834: 685b ldr r3, [r3, #4] - 8004836: f8c7 31f4 str.w r3, [r7, #500] @ 0x1f4 + 800486a: 4b12 ldr r3, [pc, #72] @ (80048b4 ) + 800486c: 685b ldr r3, [r3, #4] + 800486e: f8c7 31f4 str.w r3, [r7, #500] @ 0x1f4 pll_config2 = RCC->CFGR2; if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) || (READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV)) #else if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || - 800483a: f8d7 31f4 ldr.w r3, [r7, #500] @ 0x1f4 - 800483e: f403 3280 and.w r2, r3, #65536 @ 0x10000 - 8004842: f507 7300 add.w r3, r7, #512 @ 0x200 - 8004846: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc - 800484a: 681b ldr r3, [r3, #0] - 800484c: 6a1b ldr r3, [r3, #32] - 800484e: 429a cmp r2, r3 - 8004850: d10b bne.n 800486a + 8004872: f8d7 31f4 ldr.w r3, [r7, #500] @ 0x1f4 + 8004876: f403 3280 and.w r2, r3, #65536 @ 0x10000 + 800487a: f507 7300 add.w r3, r7, #512 @ 0x200 + 800487e: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc + 8004882: 681b ldr r3, [r3, #0] + 8004884: 6a1b ldr r3, [r3, #32] + 8004886: 429a cmp r2, r3 + 8004888: d10b bne.n 80048a2 (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL)) - 8004852: f8d7 31f4 ldr.w r3, [r7, #500] @ 0x1f4 - 8004856: f403 1270 and.w r2, r3, #3932160 @ 0x3c0000 - 800485a: f507 7300 add.w r3, r7, #512 @ 0x200 - 800485e: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc - 8004862: 681b ldr r3, [r3, #0] - 8004864: 6a5b ldr r3, [r3, #36] @ 0x24 + 800488a: f8d7 31f4 ldr.w r3, [r7, #500] @ 0x1f4 + 800488e: f403 1270 and.w r2, r3, #3932160 @ 0x3c0000 + 8004892: f507 7300 add.w r3, r7, #512 @ 0x200 + 8004896: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc + 800489a: 681b ldr r3, [r3, #0] + 800489c: 6a5b ldr r3, [r3, #36] @ 0x24 if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || - 8004866: 429a cmp r2, r3 - 8004868: d001 beq.n 800486e + 800489e: 429a cmp r2, r3 + 80048a0: d001 beq.n 80048a6 #endif { return HAL_ERROR; - 800486a: 2301 movs r3, #1 - 800486c: e000 b.n 8004870 + 80048a2: 2301 movs r3, #1 + 80048a4: e000 b.n 80048a8 } } } } return HAL_OK; - 800486e: 2300 movs r3, #0 + 80048a6: 2300 movs r3, #0 } - 8004870: 4618 mov r0, r3 - 8004872: f507 7700 add.w r7, r7, #512 @ 0x200 - 8004876: 46bd mov sp, r7 - 8004878: bd80 pop {r7, pc} - 800487a: bf00 nop - 800487c: 40021000 .word 0x40021000 + 80048a8: 4618 mov r0, r3 + 80048aa: f507 7700 add.w r7, r7, #512 @ 0x200 + 80048ae: 46bd mov sp, r7 + 80048b0: bd80 pop {r7, pc} + 80048b2: bf00 nop + 80048b4: 40021000 .word 0x40021000 -08004880 : +080048b8 : * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is * currently used as system clock source. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { - 8004880: b580 push {r7, lr} - 8004882: b09e sub sp, #120 @ 0x78 - 8004884: af00 add r7, sp, #0 - 8004886: 6078 str r0, [r7, #4] - 8004888: 6039 str r1, [r7, #0] + 80048b8: b580 push {r7, lr} + 80048ba: b09e sub sp, #120 @ 0x78 + 80048bc: af00 add r7, sp, #0 + 80048be: 6078 str r0, [r7, #4] + 80048c0: 6039 str r1, [r7, #0] uint32_t tickstart = 0U; - 800488a: 2300 movs r3, #0 - 800488c: 677b str r3, [r7, #116] @ 0x74 + 80048c2: 2300 movs r3, #0 + 80048c4: 677b str r3, [r7, #116] @ 0x74 /* Check Null pointer */ if(RCC_ClkInitStruct == NULL) - 800488e: 687b ldr r3, [r7, #4] - 8004890: 2b00 cmp r3, #0 - 8004892: d101 bne.n 8004898 + 80048c6: 687b ldr r3, [r7, #4] + 80048c8: 2b00 cmp r3, #0 + 80048ca: d101 bne.n 80048d0 { return HAL_ERROR; - 8004894: 2301 movs r3, #1 - 8004896: e162 b.n 8004b5e + 80048cc: 2301 movs r3, #1 + 80048ce: e162 b.n 8004b96 /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) of the device. */ /* Increasing the number of wait states because of higher CPU frequency */ if(FLatency > __HAL_FLASH_GET_LATENCY()) - 8004898: 4b90 ldr r3, [pc, #576] @ (8004adc ) - 800489a: 681b ldr r3, [r3, #0] - 800489c: f003 0307 and.w r3, r3, #7 - 80048a0: 683a ldr r2, [r7, #0] - 80048a2: 429a cmp r2, r3 - 80048a4: d910 bls.n 80048c8 + 80048d0: 4b90 ldr r3, [pc, #576] @ (8004b14 ) + 80048d2: 681b ldr r3, [r3, #0] + 80048d4: f003 0307 and.w r3, r3, #7 + 80048d8: 683a ldr r2, [r7, #0] + 80048da: 429a cmp r2, r3 + 80048dc: d910 bls.n 8004900 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); - 80048a6: 4b8d ldr r3, [pc, #564] @ (8004adc ) - 80048a8: 681b ldr r3, [r3, #0] - 80048aa: f023 0207 bic.w r2, r3, #7 - 80048ae: 498b ldr r1, [pc, #556] @ (8004adc ) - 80048b0: 683b ldr r3, [r7, #0] - 80048b2: 4313 orrs r3, r2 - 80048b4: 600b str r3, [r1, #0] + 80048de: 4b8d ldr r3, [pc, #564] @ (8004b14 ) + 80048e0: 681b ldr r3, [r3, #0] + 80048e2: f023 0207 bic.w r2, r3, #7 + 80048e6: 498b ldr r1, [pc, #556] @ (8004b14 ) + 80048e8: 683b ldr r3, [r7, #0] + 80048ea: 4313 orrs r3, r2 + 80048ec: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if(__HAL_FLASH_GET_LATENCY() != FLatency) - 80048b6: 4b89 ldr r3, [pc, #548] @ (8004adc ) - 80048b8: 681b ldr r3, [r3, #0] - 80048ba: f003 0307 and.w r3, r3, #7 - 80048be: 683a ldr r2, [r7, #0] - 80048c0: 429a cmp r2, r3 - 80048c2: d001 beq.n 80048c8 + 80048ee: 4b89 ldr r3, [pc, #548] @ (8004b14 ) + 80048f0: 681b ldr r3, [r3, #0] + 80048f2: f003 0307 and.w r3, r3, #7 + 80048f6: 683a ldr r2, [r7, #0] + 80048f8: 429a cmp r2, r3 + 80048fa: d001 beq.n 8004900 { return HAL_ERROR; - 80048c4: 2301 movs r3, #1 - 80048c6: e14a b.n 8004b5e + 80048fc: 2301 movs r3, #1 + 80048fe: e14a b.n 8004b96 } } /*-------------------------- HCLK Configuration --------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) - 80048c8: 687b ldr r3, [r7, #4] - 80048ca: 681b ldr r3, [r3, #0] - 80048cc: f003 0302 and.w r3, r3, #2 - 80048d0: 2b00 cmp r3, #0 - 80048d2: d008 beq.n 80048e6 + 8004900: 687b ldr r3, [r7, #4] + 8004902: 681b ldr r3, [r3, #0] + 8004904: f003 0302 and.w r3, r3, #2 + 8004908: 2b00 cmp r3, #0 + 800490a: d008 beq.n 800491e { assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); - 80048d4: 4b82 ldr r3, [pc, #520] @ (8004ae0 ) - 80048d6: 685b ldr r3, [r3, #4] - 80048d8: f023 02f0 bic.w r2, r3, #240 @ 0xf0 - 80048dc: 687b ldr r3, [r7, #4] - 80048de: 689b ldr r3, [r3, #8] - 80048e0: 497f ldr r1, [pc, #508] @ (8004ae0 ) - 80048e2: 4313 orrs r3, r2 - 80048e4: 604b str r3, [r1, #4] + 800490c: 4b82 ldr r3, [pc, #520] @ (8004b18 ) + 800490e: 685b ldr r3, [r3, #4] + 8004910: f023 02f0 bic.w r2, r3, #240 @ 0xf0 + 8004914: 687b ldr r3, [r7, #4] + 8004916: 689b ldr r3, [r3, #8] + 8004918: 497f ldr r1, [pc, #508] @ (8004b18 ) + 800491a: 4313 orrs r3, r2 + 800491c: 604b str r3, [r1, #4] } /*------------------------- SYSCLK Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) - 80048e6: 687b ldr r3, [r7, #4] - 80048e8: 681b ldr r3, [r3, #0] - 80048ea: f003 0301 and.w r3, r3, #1 - 80048ee: 2b00 cmp r3, #0 - 80048f0: f000 80dc beq.w 8004aac + 800491e: 687b ldr r3, [r7, #4] + 8004920: 681b ldr r3, [r3, #0] + 8004922: f003 0301 and.w r3, r3, #1 + 8004926: 2b00 cmp r3, #0 + 8004928: f000 80dc beq.w 8004ae4 { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) - 80048f4: 687b ldr r3, [r7, #4] - 80048f6: 685b ldr r3, [r3, #4] - 80048f8: 2b01 cmp r3, #1 - 80048fa: d13c bne.n 8004976 - 80048fc: f44f 3300 mov.w r3, #131072 @ 0x20000 - 8004900: 673b str r3, [r7, #112] @ 0x70 + 800492c: 687b ldr r3, [r7, #4] + 800492e: 685b ldr r3, [r3, #4] + 8004930: 2b01 cmp r3, #1 + 8004932: d13c bne.n 80049ae + 8004934: f44f 3300 mov.w r3, #131072 @ 0x20000 + 8004938: 673b str r3, [r7, #112] @ 0x70 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8004902: 6f3b ldr r3, [r7, #112] @ 0x70 - 8004904: fa93 f3a3 rbit r3, r3 - 8004908: 66fb str r3, [r7, #108] @ 0x6c + 800493a: 6f3b ldr r3, [r7, #112] @ 0x70 + 800493c: fa93 f3a3 rbit r3, r3 + 8004940: 66fb str r3, [r7, #108] @ 0x6c return result; - 800490a: 6efb ldr r3, [r7, #108] @ 0x6c + 8004942: 6efb ldr r3, [r7, #108] @ 0x6c { /* Check the HSE ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) - 800490c: fab3 f383 clz r3, r3 - 8004910: b2db uxtb r3, r3 - 8004912: 095b lsrs r3, r3, #5 - 8004914: b2db uxtb r3, r3 - 8004916: f043 0301 orr.w r3, r3, #1 - 800491a: b2db uxtb r3, r3 - 800491c: 2b01 cmp r3, #1 - 800491e: d102 bne.n 8004926 - 8004920: 4b6f ldr r3, [pc, #444] @ (8004ae0 ) - 8004922: 681b ldr r3, [r3, #0] - 8004924: e00f b.n 8004946 - 8004926: f44f 3300 mov.w r3, #131072 @ 0x20000 - 800492a: 66bb str r3, [r7, #104] @ 0x68 + 8004944: fab3 f383 clz r3, r3 + 8004948: b2db uxtb r3, r3 + 800494a: 095b lsrs r3, r3, #5 + 800494c: b2db uxtb r3, r3 + 800494e: f043 0301 orr.w r3, r3, #1 + 8004952: b2db uxtb r3, r3 + 8004954: 2b01 cmp r3, #1 + 8004956: d102 bne.n 800495e + 8004958: 4b6f ldr r3, [pc, #444] @ (8004b18 ) + 800495a: 681b ldr r3, [r3, #0] + 800495c: e00f b.n 800497e + 800495e: f44f 3300 mov.w r3, #131072 @ 0x20000 + 8004962: 66bb str r3, [r7, #104] @ 0x68 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 800492c: 6ebb ldr r3, [r7, #104] @ 0x68 - 800492e: fa93 f3a3 rbit r3, r3 - 8004932: 667b str r3, [r7, #100] @ 0x64 - 8004934: f44f 3300 mov.w r3, #131072 @ 0x20000 - 8004938: 663b str r3, [r7, #96] @ 0x60 - 800493a: 6e3b ldr r3, [r7, #96] @ 0x60 - 800493c: fa93 f3a3 rbit r3, r3 - 8004940: 65fb str r3, [r7, #92] @ 0x5c - 8004942: 4b67 ldr r3, [pc, #412] @ (8004ae0 ) - 8004944: 6a5b ldr r3, [r3, #36] @ 0x24 - 8004946: f44f 3200 mov.w r2, #131072 @ 0x20000 - 800494a: 65ba str r2, [r7, #88] @ 0x58 - 800494c: 6dba ldr r2, [r7, #88] @ 0x58 - 800494e: fa92 f2a2 rbit r2, r2 - 8004952: 657a str r2, [r7, #84] @ 0x54 + 8004964: 6ebb ldr r3, [r7, #104] @ 0x68 + 8004966: fa93 f3a3 rbit r3, r3 + 800496a: 667b str r3, [r7, #100] @ 0x64 + 800496c: f44f 3300 mov.w r3, #131072 @ 0x20000 + 8004970: 663b str r3, [r7, #96] @ 0x60 + 8004972: 6e3b ldr r3, [r7, #96] @ 0x60 + 8004974: fa93 f3a3 rbit r3, r3 + 8004978: 65fb str r3, [r7, #92] @ 0x5c + 800497a: 4b67 ldr r3, [pc, #412] @ (8004b18 ) + 800497c: 6a5b ldr r3, [r3, #36] @ 0x24 + 800497e: f44f 3200 mov.w r2, #131072 @ 0x20000 + 8004982: 65ba str r2, [r7, #88] @ 0x58 + 8004984: 6dba ldr r2, [r7, #88] @ 0x58 + 8004986: fa92 f2a2 rbit r2, r2 + 800498a: 657a str r2, [r7, #84] @ 0x54 return result; - 8004954: 6d7a ldr r2, [r7, #84] @ 0x54 - 8004956: fab2 f282 clz r2, r2 - 800495a: b2d2 uxtb r2, r2 - 800495c: f042 0220 orr.w r2, r2, #32 - 8004960: b2d2 uxtb r2, r2 - 8004962: f002 021f and.w r2, r2, #31 - 8004966: 2101 movs r1, #1 - 8004968: fa01 f202 lsl.w r2, r1, r2 - 800496c: 4013 ands r3, r2 - 800496e: 2b00 cmp r3, #0 - 8004970: d17b bne.n 8004a6a + 800498c: 6d7a ldr r2, [r7, #84] @ 0x54 + 800498e: fab2 f282 clz r2, r2 + 8004992: b2d2 uxtb r2, r2 + 8004994: f042 0220 orr.w r2, r2, #32 + 8004998: b2d2 uxtb r2, r2 + 800499a: f002 021f and.w r2, r2, #31 + 800499e: 2101 movs r1, #1 + 80049a0: fa01 f202 lsl.w r2, r1, r2 + 80049a4: 4013 ands r3, r2 + 80049a6: 2b00 cmp r3, #0 + 80049a8: d17b bne.n 8004aa2 { return HAL_ERROR; - 8004972: 2301 movs r3, #1 - 8004974: e0f3 b.n 8004b5e + 80049aa: 2301 movs r3, #1 + 80049ac: e0f3 b.n 8004b96 } } /* PLL is selected as System Clock Source */ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) - 8004976: 687b ldr r3, [r7, #4] - 8004978: 685b ldr r3, [r3, #4] - 800497a: 2b02 cmp r3, #2 - 800497c: d13c bne.n 80049f8 - 800497e: f04f 7300 mov.w r3, #33554432 @ 0x2000000 - 8004982: 653b str r3, [r7, #80] @ 0x50 + 80049ae: 687b ldr r3, [r7, #4] + 80049b0: 685b ldr r3, [r3, #4] + 80049b2: 2b02 cmp r3, #2 + 80049b4: d13c bne.n 8004a30 + 80049b6: f04f 7300 mov.w r3, #33554432 @ 0x2000000 + 80049ba: 653b str r3, [r7, #80] @ 0x50 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8004984: 6d3b ldr r3, [r7, #80] @ 0x50 - 8004986: fa93 f3a3 rbit r3, r3 - 800498a: 64fb str r3, [r7, #76] @ 0x4c + 80049bc: 6d3b ldr r3, [r7, #80] @ 0x50 + 80049be: fa93 f3a3 rbit r3, r3 + 80049c2: 64fb str r3, [r7, #76] @ 0x4c return result; - 800498c: 6cfb ldr r3, [r7, #76] @ 0x4c + 80049c4: 6cfb ldr r3, [r7, #76] @ 0x4c { /* Check the PLL ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) - 800498e: fab3 f383 clz r3, r3 - 8004992: b2db uxtb r3, r3 - 8004994: 095b lsrs r3, r3, #5 - 8004996: b2db uxtb r3, r3 - 8004998: f043 0301 orr.w r3, r3, #1 - 800499c: b2db uxtb r3, r3 - 800499e: 2b01 cmp r3, #1 - 80049a0: d102 bne.n 80049a8 - 80049a2: 4b4f ldr r3, [pc, #316] @ (8004ae0 ) - 80049a4: 681b ldr r3, [r3, #0] - 80049a6: e00f b.n 80049c8 - 80049a8: f04f 7300 mov.w r3, #33554432 @ 0x2000000 - 80049ac: 64bb str r3, [r7, #72] @ 0x48 + 80049c6: fab3 f383 clz r3, r3 + 80049ca: b2db uxtb r3, r3 + 80049cc: 095b lsrs r3, r3, #5 + 80049ce: b2db uxtb r3, r3 + 80049d0: f043 0301 orr.w r3, r3, #1 + 80049d4: b2db uxtb r3, r3 + 80049d6: 2b01 cmp r3, #1 + 80049d8: d102 bne.n 80049e0 + 80049da: 4b4f ldr r3, [pc, #316] @ (8004b18 ) + 80049dc: 681b ldr r3, [r3, #0] + 80049de: e00f b.n 8004a00 + 80049e0: f04f 7300 mov.w r3, #33554432 @ 0x2000000 + 80049e4: 64bb str r3, [r7, #72] @ 0x48 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 80049ae: 6cbb ldr r3, [r7, #72] @ 0x48 - 80049b0: fa93 f3a3 rbit r3, r3 - 80049b4: 647b str r3, [r7, #68] @ 0x44 - 80049b6: f04f 7300 mov.w r3, #33554432 @ 0x2000000 - 80049ba: 643b str r3, [r7, #64] @ 0x40 - 80049bc: 6c3b ldr r3, [r7, #64] @ 0x40 - 80049be: fa93 f3a3 rbit r3, r3 - 80049c2: 63fb str r3, [r7, #60] @ 0x3c - 80049c4: 4b46 ldr r3, [pc, #280] @ (8004ae0 ) - 80049c6: 6a5b ldr r3, [r3, #36] @ 0x24 - 80049c8: f04f 7200 mov.w r2, #33554432 @ 0x2000000 - 80049cc: 63ba str r2, [r7, #56] @ 0x38 - 80049ce: 6bba ldr r2, [r7, #56] @ 0x38 - 80049d0: fa92 f2a2 rbit r2, r2 - 80049d4: 637a str r2, [r7, #52] @ 0x34 + 80049e6: 6cbb ldr r3, [r7, #72] @ 0x48 + 80049e8: fa93 f3a3 rbit r3, r3 + 80049ec: 647b str r3, [r7, #68] @ 0x44 + 80049ee: f04f 7300 mov.w r3, #33554432 @ 0x2000000 + 80049f2: 643b str r3, [r7, #64] @ 0x40 + 80049f4: 6c3b ldr r3, [r7, #64] @ 0x40 + 80049f6: fa93 f3a3 rbit r3, r3 + 80049fa: 63fb str r3, [r7, #60] @ 0x3c + 80049fc: 4b46 ldr r3, [pc, #280] @ (8004b18 ) + 80049fe: 6a5b ldr r3, [r3, #36] @ 0x24 + 8004a00: f04f 7200 mov.w r2, #33554432 @ 0x2000000 + 8004a04: 63ba str r2, [r7, #56] @ 0x38 + 8004a06: 6bba ldr r2, [r7, #56] @ 0x38 + 8004a08: fa92 f2a2 rbit r2, r2 + 8004a0c: 637a str r2, [r7, #52] @ 0x34 return result; - 80049d6: 6b7a ldr r2, [r7, #52] @ 0x34 - 80049d8: fab2 f282 clz r2, r2 - 80049dc: b2d2 uxtb r2, r2 - 80049de: f042 0220 orr.w r2, r2, #32 - 80049e2: b2d2 uxtb r2, r2 - 80049e4: f002 021f and.w r2, r2, #31 - 80049e8: 2101 movs r1, #1 - 80049ea: fa01 f202 lsl.w r2, r1, r2 - 80049ee: 4013 ands r3, r2 - 80049f0: 2b00 cmp r3, #0 - 80049f2: d13a bne.n 8004a6a + 8004a0e: 6b7a ldr r2, [r7, #52] @ 0x34 + 8004a10: fab2 f282 clz r2, r2 + 8004a14: b2d2 uxtb r2, r2 + 8004a16: f042 0220 orr.w r2, r2, #32 + 8004a1a: b2d2 uxtb r2, r2 + 8004a1c: f002 021f and.w r2, r2, #31 + 8004a20: 2101 movs r1, #1 + 8004a22: fa01 f202 lsl.w r2, r1, r2 + 8004a26: 4013 ands r3, r2 + 8004a28: 2b00 cmp r3, #0 + 8004a2a: d13a bne.n 8004aa2 { return HAL_ERROR; - 80049f4: 2301 movs r3, #1 - 80049f6: e0b2 b.n 8004b5e - 80049f8: 2302 movs r3, #2 - 80049fa: 633b str r3, [r7, #48] @ 0x30 + 8004a2c: 2301 movs r3, #1 + 8004a2e: e0b2 b.n 8004b96 + 8004a30: 2302 movs r3, #2 + 8004a32: 633b str r3, [r7, #48] @ 0x30 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 80049fc: 6b3b ldr r3, [r7, #48] @ 0x30 - 80049fe: fa93 f3a3 rbit r3, r3 - 8004a02: 62fb str r3, [r7, #44] @ 0x2c + 8004a34: 6b3b ldr r3, [r7, #48] @ 0x30 + 8004a36: fa93 f3a3 rbit r3, r3 + 8004a3a: 62fb str r3, [r7, #44] @ 0x2c return result; - 8004a04: 6afb ldr r3, [r7, #44] @ 0x2c + 8004a3c: 6afb ldr r3, [r7, #44] @ 0x2c } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) - 8004a06: fab3 f383 clz r3, r3 - 8004a0a: b2db uxtb r3, r3 - 8004a0c: 095b lsrs r3, r3, #5 - 8004a0e: b2db uxtb r3, r3 - 8004a10: f043 0301 orr.w r3, r3, #1 - 8004a14: b2db uxtb r3, r3 - 8004a16: 2b01 cmp r3, #1 - 8004a18: d102 bne.n 8004a20 - 8004a1a: 4b31 ldr r3, [pc, #196] @ (8004ae0 ) - 8004a1c: 681b ldr r3, [r3, #0] - 8004a1e: e00d b.n 8004a3c - 8004a20: 2302 movs r3, #2 - 8004a22: 62bb str r3, [r7, #40] @ 0x28 + 8004a3e: fab3 f383 clz r3, r3 + 8004a42: b2db uxtb r3, r3 + 8004a44: 095b lsrs r3, r3, #5 + 8004a46: b2db uxtb r3, r3 + 8004a48: f043 0301 orr.w r3, r3, #1 + 8004a4c: b2db uxtb r3, r3 + 8004a4e: 2b01 cmp r3, #1 + 8004a50: d102 bne.n 8004a58 + 8004a52: 4b31 ldr r3, [pc, #196] @ (8004b18 ) + 8004a54: 681b ldr r3, [r3, #0] + 8004a56: e00d b.n 8004a74 + 8004a58: 2302 movs r3, #2 + 8004a5a: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8004a24: 6abb ldr r3, [r7, #40] @ 0x28 - 8004a26: fa93 f3a3 rbit r3, r3 - 8004a2a: 627b str r3, [r7, #36] @ 0x24 - 8004a2c: 2302 movs r3, #2 - 8004a2e: 623b str r3, [r7, #32] - 8004a30: 6a3b ldr r3, [r7, #32] - 8004a32: fa93 f3a3 rbit r3, r3 - 8004a36: 61fb str r3, [r7, #28] - 8004a38: 4b29 ldr r3, [pc, #164] @ (8004ae0 ) - 8004a3a: 6a5b ldr r3, [r3, #36] @ 0x24 - 8004a3c: 2202 movs r2, #2 - 8004a3e: 61ba str r2, [r7, #24] - 8004a40: 69ba ldr r2, [r7, #24] - 8004a42: fa92 f2a2 rbit r2, r2 - 8004a46: 617a str r2, [r7, #20] + 8004a5c: 6abb ldr r3, [r7, #40] @ 0x28 + 8004a5e: fa93 f3a3 rbit r3, r3 + 8004a62: 627b str r3, [r7, #36] @ 0x24 + 8004a64: 2302 movs r3, #2 + 8004a66: 623b str r3, [r7, #32] + 8004a68: 6a3b ldr r3, [r7, #32] + 8004a6a: fa93 f3a3 rbit r3, r3 + 8004a6e: 61fb str r3, [r7, #28] + 8004a70: 4b29 ldr r3, [pc, #164] @ (8004b18 ) + 8004a72: 6a5b ldr r3, [r3, #36] @ 0x24 + 8004a74: 2202 movs r2, #2 + 8004a76: 61ba str r2, [r7, #24] + 8004a78: 69ba ldr r2, [r7, #24] + 8004a7a: fa92 f2a2 rbit r2, r2 + 8004a7e: 617a str r2, [r7, #20] return result; - 8004a48: 697a ldr r2, [r7, #20] - 8004a4a: fab2 f282 clz r2, r2 - 8004a4e: b2d2 uxtb r2, r2 - 8004a50: f042 0220 orr.w r2, r2, #32 - 8004a54: b2d2 uxtb r2, r2 - 8004a56: f002 021f and.w r2, r2, #31 - 8004a5a: 2101 movs r1, #1 - 8004a5c: fa01 f202 lsl.w r2, r1, r2 - 8004a60: 4013 ands r3, r2 - 8004a62: 2b00 cmp r3, #0 - 8004a64: d101 bne.n 8004a6a + 8004a80: 697a ldr r2, [r7, #20] + 8004a82: fab2 f282 clz r2, r2 + 8004a86: b2d2 uxtb r2, r2 + 8004a88: f042 0220 orr.w r2, r2, #32 + 8004a8c: b2d2 uxtb r2, r2 + 8004a8e: f002 021f and.w r2, r2, #31 + 8004a92: 2101 movs r1, #1 + 8004a94: fa01 f202 lsl.w r2, r1, r2 + 8004a98: 4013 ands r3, r2 + 8004a9a: 2b00 cmp r3, #0 + 8004a9c: d101 bne.n 8004aa2 { return HAL_ERROR; - 8004a66: 2301 movs r3, #1 - 8004a68: e079 b.n 8004b5e + 8004a9e: 2301 movs r3, #1 + 8004aa0: e079 b.n 8004b96 } } __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); - 8004a6a: 4b1d ldr r3, [pc, #116] @ (8004ae0 ) - 8004a6c: 685b ldr r3, [r3, #4] - 8004a6e: f023 0203 bic.w r2, r3, #3 - 8004a72: 687b ldr r3, [r7, #4] - 8004a74: 685b ldr r3, [r3, #4] - 8004a76: 491a ldr r1, [pc, #104] @ (8004ae0 ) - 8004a78: 4313 orrs r3, r2 - 8004a7a: 604b str r3, [r1, #4] + 8004aa2: 4b1d ldr r3, [pc, #116] @ (8004b18 ) + 8004aa4: 685b ldr r3, [r3, #4] + 8004aa6: f023 0203 bic.w r2, r3, #3 + 8004aaa: 687b ldr r3, [r7, #4] + 8004aac: 685b ldr r3, [r3, #4] + 8004aae: 491a ldr r1, [pc, #104] @ (8004b18 ) + 8004ab0: 4313 orrs r3, r2 + 8004ab2: 604b str r3, [r1, #4] /* Get Start Tick */ tickstart = HAL_GetTick(); - 8004a7c: f7fc fcbc bl 80013f8 - 8004a80: 6778 str r0, [r7, #116] @ 0x74 + 8004ab4: f7fc fcbc bl 8001430 + 8004ab8: 6778 str r0, [r7, #116] @ 0x74 while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) - 8004a82: e00a b.n 8004a9a + 8004aba: e00a b.n 8004ad2 { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) - 8004a84: f7fc fcb8 bl 80013f8 - 8004a88: 4602 mov r2, r0 - 8004a8a: 6f7b ldr r3, [r7, #116] @ 0x74 - 8004a8c: 1ad3 subs r3, r2, r3 - 8004a8e: f241 3288 movw r2, #5000 @ 0x1388 - 8004a92: 4293 cmp r3, r2 - 8004a94: d901 bls.n 8004a9a + 8004abc: f7fc fcb8 bl 8001430 + 8004ac0: 4602 mov r2, r0 + 8004ac2: 6f7b ldr r3, [r7, #116] @ 0x74 + 8004ac4: 1ad3 subs r3, r2, r3 + 8004ac6: f241 3288 movw r2, #5000 @ 0x1388 + 8004aca: 4293 cmp r3, r2 + 8004acc: d901 bls.n 8004ad2 { return HAL_TIMEOUT; - 8004a96: 2303 movs r3, #3 - 8004a98: e061 b.n 8004b5e + 8004ace: 2303 movs r3, #3 + 8004ad0: e061 b.n 8004b96 while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) - 8004a9a: 4b11 ldr r3, [pc, #68] @ (8004ae0 ) - 8004a9c: 685b ldr r3, [r3, #4] - 8004a9e: f003 020c and.w r2, r3, #12 - 8004aa2: 687b ldr r3, [r7, #4] - 8004aa4: 685b ldr r3, [r3, #4] - 8004aa6: 009b lsls r3, r3, #2 - 8004aa8: 429a cmp r2, r3 - 8004aaa: d1eb bne.n 8004a84 + 8004ad2: 4b11 ldr r3, [pc, #68] @ (8004b18 ) + 8004ad4: 685b ldr r3, [r3, #4] + 8004ad6: f003 020c and.w r2, r3, #12 + 8004ada: 687b ldr r3, [r7, #4] + 8004adc: 685b ldr r3, [r3, #4] + 8004ade: 009b lsls r3, r3, #2 + 8004ae0: 429a cmp r2, r3 + 8004ae2: d1eb bne.n 8004abc } } } /* Decreasing the number of wait states because of lower CPU frequency */ if(FLatency < __HAL_FLASH_GET_LATENCY()) - 8004aac: 4b0b ldr r3, [pc, #44] @ (8004adc ) - 8004aae: 681b ldr r3, [r3, #0] - 8004ab0: f003 0307 and.w r3, r3, #7 - 8004ab4: 683a ldr r2, [r7, #0] - 8004ab6: 429a cmp r2, r3 - 8004ab8: d214 bcs.n 8004ae4 + 8004ae4: 4b0b ldr r3, [pc, #44] @ (8004b14 ) + 8004ae6: 681b ldr r3, [r3, #0] + 8004ae8: f003 0307 and.w r3, r3, #7 + 8004aec: 683a ldr r2, [r7, #0] + 8004aee: 429a cmp r2, r3 + 8004af0: d214 bcs.n 8004b1c { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); - 8004aba: 4b08 ldr r3, [pc, #32] @ (8004adc ) - 8004abc: 681b ldr r3, [r3, #0] - 8004abe: f023 0207 bic.w r2, r3, #7 - 8004ac2: 4906 ldr r1, [pc, #24] @ (8004adc ) - 8004ac4: 683b ldr r3, [r7, #0] - 8004ac6: 4313 orrs r3, r2 - 8004ac8: 600b str r3, [r1, #0] + 8004af2: 4b08 ldr r3, [pc, #32] @ (8004b14 ) + 8004af4: 681b ldr r3, [r3, #0] + 8004af6: f023 0207 bic.w r2, r3, #7 + 8004afa: 4906 ldr r1, [pc, #24] @ (8004b14 ) + 8004afc: 683b ldr r3, [r7, #0] + 8004afe: 4313 orrs r3, r2 + 8004b00: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if(__HAL_FLASH_GET_LATENCY() != FLatency) - 8004aca: 4b04 ldr r3, [pc, #16] @ (8004adc ) - 8004acc: 681b ldr r3, [r3, #0] - 8004ace: f003 0307 and.w r3, r3, #7 - 8004ad2: 683a ldr r2, [r7, #0] - 8004ad4: 429a cmp r2, r3 - 8004ad6: d005 beq.n 8004ae4 + 8004b02: 4b04 ldr r3, [pc, #16] @ (8004b14 ) + 8004b04: 681b ldr r3, [r3, #0] + 8004b06: f003 0307 and.w r3, r3, #7 + 8004b0a: 683a ldr r2, [r7, #0] + 8004b0c: 429a cmp r2, r3 + 8004b0e: d005 beq.n 8004b1c { return HAL_ERROR; - 8004ad8: 2301 movs r3, #1 - 8004ada: e040 b.n 8004b5e - 8004adc: 40022000 .word 0x40022000 - 8004ae0: 40021000 .word 0x40021000 + 8004b10: 2301 movs r3, #1 + 8004b12: e040 b.n 8004b96 + 8004b14: 40022000 .word 0x40022000 + 8004b18: 40021000 .word 0x40021000 } } /*-------------------------- PCLK1 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) - 8004ae4: 687b ldr r3, [r7, #4] - 8004ae6: 681b ldr r3, [r3, #0] - 8004ae8: f003 0304 and.w r3, r3, #4 - 8004aec: 2b00 cmp r3, #0 - 8004aee: d008 beq.n 8004b02 + 8004b1c: 687b ldr r3, [r7, #4] + 8004b1e: 681b ldr r3, [r3, #0] + 8004b20: f003 0304 and.w r3, r3, #4 + 8004b24: 2b00 cmp r3, #0 + 8004b26: d008 beq.n 8004b3a { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); - 8004af0: 4b1d ldr r3, [pc, #116] @ (8004b68 ) - 8004af2: 685b ldr r3, [r3, #4] - 8004af4: f423 62e0 bic.w r2, r3, #1792 @ 0x700 - 8004af8: 687b ldr r3, [r7, #4] - 8004afa: 68db ldr r3, [r3, #12] - 8004afc: 491a ldr r1, [pc, #104] @ (8004b68 ) - 8004afe: 4313 orrs r3, r2 - 8004b00: 604b str r3, [r1, #4] + 8004b28: 4b1d ldr r3, [pc, #116] @ (8004ba0 ) + 8004b2a: 685b ldr r3, [r3, #4] + 8004b2c: f423 62e0 bic.w r2, r3, #1792 @ 0x700 + 8004b30: 687b ldr r3, [r7, #4] + 8004b32: 68db ldr r3, [r3, #12] + 8004b34: 491a ldr r1, [pc, #104] @ (8004ba0 ) + 8004b36: 4313 orrs r3, r2 + 8004b38: 604b str r3, [r1, #4] } /*-------------------------- PCLK2 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) - 8004b02: 687b ldr r3, [r7, #4] - 8004b04: 681b ldr r3, [r3, #0] - 8004b06: f003 0308 and.w r3, r3, #8 - 8004b0a: 2b00 cmp r3, #0 - 8004b0c: d009 beq.n 8004b22 + 8004b3a: 687b ldr r3, [r7, #4] + 8004b3c: 681b ldr r3, [r3, #0] + 8004b3e: f003 0308 and.w r3, r3, #8 + 8004b42: 2b00 cmp r3, #0 + 8004b44: d009 beq.n 8004b5a { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); - 8004b0e: 4b16 ldr r3, [pc, #88] @ (8004b68 ) - 8004b10: 685b ldr r3, [r3, #4] - 8004b12: f423 5260 bic.w r2, r3, #14336 @ 0x3800 - 8004b16: 687b ldr r3, [r7, #4] - 8004b18: 691b ldr r3, [r3, #16] - 8004b1a: 00db lsls r3, r3, #3 - 8004b1c: 4912 ldr r1, [pc, #72] @ (8004b68 ) - 8004b1e: 4313 orrs r3, r2 - 8004b20: 604b str r3, [r1, #4] + 8004b46: 4b16 ldr r3, [pc, #88] @ (8004ba0 ) + 8004b48: 685b ldr r3, [r3, #4] + 8004b4a: f423 5260 bic.w r2, r3, #14336 @ 0x3800 + 8004b4e: 687b ldr r3, [r7, #4] + 8004b50: 691b ldr r3, [r3, #16] + 8004b52: 00db lsls r3, r3, #3 + 8004b54: 4912 ldr r1, [pc, #72] @ (8004ba0 ) + 8004b56: 4313 orrs r3, r2 + 8004b58: 604b str r3, [r1, #4] } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER]; - 8004b22: f000 f829 bl 8004b78 - 8004b26: 4601 mov r1, r0 - 8004b28: 4b0f ldr r3, [pc, #60] @ (8004b68 ) - 8004b2a: 685b ldr r3, [r3, #4] - 8004b2c: f003 03f0 and.w r3, r3, #240 @ 0xf0 - 8004b30: 22f0 movs r2, #240 @ 0xf0 - 8004b32: 613a str r2, [r7, #16] + 8004b5a: f000 f829 bl 8004bb0 + 8004b5e: 4601 mov r1, r0 + 8004b60: 4b0f ldr r3, [pc, #60] @ (8004ba0 ) + 8004b62: 685b ldr r3, [r3, #4] + 8004b64: f003 03f0 and.w r3, r3, #240 @ 0xf0 + 8004b68: 22f0 movs r2, #240 @ 0xf0 + 8004b6a: 613a str r2, [r7, #16] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8004b34: 693a ldr r2, [r7, #16] - 8004b36: fa92 f2a2 rbit r2, r2 - 8004b3a: 60fa str r2, [r7, #12] + 8004b6c: 693a ldr r2, [r7, #16] + 8004b6e: fa92 f2a2 rbit r2, r2 + 8004b72: 60fa str r2, [r7, #12] return result; - 8004b3c: 68fa ldr r2, [r7, #12] - 8004b3e: fab2 f282 clz r2, r2 - 8004b42: b2d2 uxtb r2, r2 - 8004b44: 40d3 lsrs r3, r2 - 8004b46: 4a09 ldr r2, [pc, #36] @ (8004b6c ) - 8004b48: 5cd3 ldrb r3, [r2, r3] - 8004b4a: fa21 f303 lsr.w r3, r1, r3 - 8004b4e: 4a08 ldr r2, [pc, #32] @ (8004b70 ) - 8004b50: 6013 str r3, [r2, #0] + 8004b74: 68fa ldr r2, [r7, #12] + 8004b76: fab2 f282 clz r2, r2 + 8004b7a: b2d2 uxtb r2, r2 + 8004b7c: 40d3 lsrs r3, r2 + 8004b7e: 4a09 ldr r2, [pc, #36] @ (8004ba4 ) + 8004b80: 5cd3 ldrb r3, [r2, r3] + 8004b82: fa21 f303 lsr.w r3, r1, r3 + 8004b86: 4a08 ldr r2, [pc, #32] @ (8004ba8 ) + 8004b88: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings*/ HAL_InitTick (uwTickPrio); - 8004b52: 4b08 ldr r3, [pc, #32] @ (8004b74 ) - 8004b54: 681b ldr r3, [r3, #0] - 8004b56: 4618 mov r0, r3 - 8004b58: f7fc fc0a bl 8001370 + 8004b8a: 4b08 ldr r3, [pc, #32] @ (8004bac ) + 8004b8c: 681b ldr r3, [r3, #0] + 8004b8e: 4618 mov r0, r3 + 8004b90: f7fc fc0a bl 80013a8 return HAL_OK; - 8004b5c: 2300 movs r3, #0 + 8004b94: 2300 movs r3, #0 } - 8004b5e: 4618 mov r0, r3 - 8004b60: 3778 adds r7, #120 @ 0x78 - 8004b62: 46bd mov sp, r7 - 8004b64: bd80 pop {r7, pc} - 8004b66: bf00 nop - 8004b68: 40021000 .word 0x40021000 - 8004b6c: 08005e6c .word 0x08005e6c - 8004b70: 20000000 .word 0x20000000 - 8004b74: 20000004 .word 0x20000004 + 8004b96: 4618 mov r0, r3 + 8004b98: 3778 adds r7, #120 @ 0x78 + 8004b9a: 46bd mov sp, r7 + 8004b9c: bd80 pop {r7, pc} + 8004b9e: bf00 nop + 8004ba0: 40021000 .word 0x40021000 + 8004ba4: 08005ea4 .word 0x08005ea4 + 8004ba8: 20000000 .word 0x20000000 + 8004bac: 20000004 .word 0x20000004 -08004b78 : +08004bb0 : * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { - 8004b78: b480 push {r7} - 8004b7a: b08b sub sp, #44 @ 0x2c - 8004b7c: af00 add r7, sp, #0 + 8004bb0: b480 push {r7} + 8004bb2: b08b sub sp, #44 @ 0x2c + 8004bb4: af00 add r7, sp, #0 uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U; - 8004b7e: 2300 movs r3, #0 - 8004b80: 61fb str r3, [r7, #28] - 8004b82: 2300 movs r3, #0 - 8004b84: 61bb str r3, [r7, #24] - 8004b86: 2300 movs r3, #0 - 8004b88: 627b str r3, [r7, #36] @ 0x24 - 8004b8a: 2300 movs r3, #0 - 8004b8c: 617b str r3, [r7, #20] + 8004bb6: 2300 movs r3, #0 + 8004bb8: 61fb str r3, [r7, #28] + 8004bba: 2300 movs r3, #0 + 8004bbc: 61bb str r3, [r7, #24] + 8004bbe: 2300 movs r3, #0 + 8004bc0: 627b str r3, [r7, #36] @ 0x24 + 8004bc2: 2300 movs r3, #0 + 8004bc4: 617b str r3, [r7, #20] uint32_t sysclockfreq = 0U; - 8004b8e: 2300 movs r3, #0 - 8004b90: 623b str r3, [r7, #32] + 8004bc6: 2300 movs r3, #0 + 8004bc8: 623b str r3, [r7, #32] tmpreg = RCC->CFGR; - 8004b92: 4b29 ldr r3, [pc, #164] @ (8004c38 ) - 8004b94: 685b ldr r3, [r3, #4] - 8004b96: 61fb str r3, [r7, #28] + 8004bca: 4b29 ldr r3, [pc, #164] @ (8004c70 ) + 8004bcc: 685b ldr r3, [r3, #4] + 8004bce: 61fb str r3, [r7, #28] /* Get SYSCLK source -------------------------------------------------------*/ switch (tmpreg & RCC_CFGR_SWS) - 8004b98: 69fb ldr r3, [r7, #28] - 8004b9a: f003 030c and.w r3, r3, #12 - 8004b9e: 2b04 cmp r3, #4 - 8004ba0: d002 beq.n 8004ba8 - 8004ba2: 2b08 cmp r3, #8 - 8004ba4: d003 beq.n 8004bae - 8004ba6: e03c b.n 8004c22 + 8004bd0: 69fb ldr r3, [r7, #28] + 8004bd2: f003 030c and.w r3, r3, #12 + 8004bd6: 2b04 cmp r3, #4 + 8004bd8: d002 beq.n 8004be0 + 8004bda: 2b08 cmp r3, #8 + 8004bdc: d003 beq.n 8004be6 + 8004bde: e03c b.n 8004c5a { case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ { sysclockfreq = HSE_VALUE; - 8004ba8: 4b24 ldr r3, [pc, #144] @ (8004c3c ) - 8004baa: 623b str r3, [r7, #32] + 8004be0: 4b24 ldr r3, [pc, #144] @ (8004c74 ) + 8004be2: 623b str r3, [r7, #32] break; - 8004bac: e03c b.n 8004c28 + 8004be4: e03c b.n 8004c60 } case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ { pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> POSITION_VAL(RCC_CFGR_PLLMUL)]; - 8004bae: 69fb ldr r3, [r7, #28] - 8004bb0: f403 1370 and.w r3, r3, #3932160 @ 0x3c0000 - 8004bb4: f44f 1270 mov.w r2, #3932160 @ 0x3c0000 - 8004bb8: 60ba str r2, [r7, #8] + 8004be6: 69fb ldr r3, [r7, #28] + 8004be8: f403 1370 and.w r3, r3, #3932160 @ 0x3c0000 + 8004bec: f44f 1270 mov.w r2, #3932160 @ 0x3c0000 + 8004bf0: 60ba str r2, [r7, #8] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8004bba: 68ba ldr r2, [r7, #8] - 8004bbc: fa92 f2a2 rbit r2, r2 - 8004bc0: 607a str r2, [r7, #4] + 8004bf2: 68ba ldr r2, [r7, #8] + 8004bf4: fa92 f2a2 rbit r2, r2 + 8004bf8: 607a str r2, [r7, #4] return result; - 8004bc2: 687a ldr r2, [r7, #4] - 8004bc4: fab2 f282 clz r2, r2 - 8004bc8: b2d2 uxtb r2, r2 - 8004bca: 40d3 lsrs r3, r2 - 8004bcc: 4a1c ldr r2, [pc, #112] @ (8004c40 ) - 8004bce: 5cd3 ldrb r3, [r2, r3] - 8004bd0: 617b str r3, [r7, #20] + 8004bfa: 687a ldr r2, [r7, #4] + 8004bfc: fab2 f282 clz r2, r2 + 8004c00: b2d2 uxtb r2, r2 + 8004c02: 40d3 lsrs r3, r2 + 8004c04: 4a1c ldr r2, [pc, #112] @ (8004c78 ) + 8004c06: 5cd3 ldrb r3, [r2, r3] + 8004c08: 617b str r3, [r7, #20] prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV) >> POSITION_VAL(RCC_CFGR2_PREDIV)]; - 8004bd2: 4b19 ldr r3, [pc, #100] @ (8004c38 ) - 8004bd4: 6adb ldr r3, [r3, #44] @ 0x2c - 8004bd6: f003 030f and.w r3, r3, #15 - 8004bda: 220f movs r2, #15 - 8004bdc: 613a str r2, [r7, #16] + 8004c0a: 4b19 ldr r3, [pc, #100] @ (8004c70 ) + 8004c0c: 6adb ldr r3, [r3, #44] @ 0x2c + 8004c0e: f003 030f and.w r3, r3, #15 + 8004c12: 220f movs r2, #15 + 8004c14: 613a str r2, [r7, #16] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8004bde: 693a ldr r2, [r7, #16] - 8004be0: fa92 f2a2 rbit r2, r2 - 8004be4: 60fa str r2, [r7, #12] + 8004c16: 693a ldr r2, [r7, #16] + 8004c18: fa92 f2a2 rbit r2, r2 + 8004c1c: 60fa str r2, [r7, #12] return result; - 8004be6: 68fa ldr r2, [r7, #12] - 8004be8: fab2 f282 clz r2, r2 - 8004bec: b2d2 uxtb r2, r2 - 8004bee: 40d3 lsrs r3, r2 - 8004bf0: 4a14 ldr r2, [pc, #80] @ (8004c44 ) - 8004bf2: 5cd3 ldrb r3, [r2, r3] - 8004bf4: 61bb str r3, [r7, #24] + 8004c1e: 68fa ldr r2, [r7, #12] + 8004c20: fab2 f282 clz r2, r2 + 8004c24: b2d2 uxtb r2, r2 + 8004c26: 40d3 lsrs r3, r2 + 8004c28: 4a14 ldr r2, [pc, #80] @ (8004c7c ) + 8004c2a: 5cd3 ldrb r3, [r2, r3] + 8004c2c: 61bb str r3, [r7, #24] #if defined(RCC_CFGR_PLLSRC_HSI_DIV2) if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI) - 8004bf6: 69fb ldr r3, [r7, #28] - 8004bf8: f403 3380 and.w r3, r3, #65536 @ 0x10000 - 8004bfc: 2b00 cmp r3, #0 - 8004bfe: d008 beq.n 8004c12 + 8004c2e: 69fb ldr r3, [r7, #28] + 8004c30: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 8004c34: 2b00 cmp r3, #0 + 8004c36: d008 beq.n 8004c4a { /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */ pllclk = (uint32_t)((uint64_t) HSE_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul); - 8004c00: 4a0e ldr r2, [pc, #56] @ (8004c3c ) - 8004c02: 69bb ldr r3, [r7, #24] - 8004c04: fbb2 f2f3 udiv r2, r2, r3 - 8004c08: 697b ldr r3, [r7, #20] - 8004c0a: fb02 f303 mul.w r3, r2, r3 - 8004c0e: 627b str r3, [r7, #36] @ 0x24 - 8004c10: e004 b.n 8004c1c + 8004c38: 4a0e ldr r2, [pc, #56] @ (8004c74 ) + 8004c3a: 69bb ldr r3, [r7, #24] + 8004c3c: fbb2 f2f3 udiv r2, r2, r3 + 8004c40: 697b ldr r3, [r7, #20] + 8004c42: fb02 f303 mul.w r3, r2, r3 + 8004c46: 627b str r3, [r7, #36] @ 0x24 + 8004c48: e004 b.n 8004c54 } else { /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ pllclk = (uint32_t)((uint64_t) (HSI_VALUE >> 1U) * ((uint64_t) pllmul)); - 8004c12: 697b ldr r3, [r7, #20] - 8004c14: 4a0c ldr r2, [pc, #48] @ (8004c48 ) - 8004c16: fb02 f303 mul.w r3, r2, r3 - 8004c1a: 627b str r3, [r7, #36] @ 0x24 + 8004c4a: 697b ldr r3, [r7, #20] + 8004c4c: 4a0c ldr r2, [pc, #48] @ (8004c80 ) + 8004c4e: fb02 f303 mul.w r3, r2, r3 + 8004c52: 627b str r3, [r7, #36] @ 0x24 { /* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */ pllclk = (uint32_t)((uint64_t) HSI_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul); } #endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */ sysclockfreq = pllclk; - 8004c1c: 6a7b ldr r3, [r7, #36] @ 0x24 - 8004c1e: 623b str r3, [r7, #32] + 8004c54: 6a7b ldr r3, [r7, #36] @ 0x24 + 8004c56: 623b str r3, [r7, #32] break; - 8004c20: e002 b.n 8004c28 + 8004c58: e002 b.n 8004c60 } case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ default: /* HSI used as system clock */ { sysclockfreq = HSI_VALUE; - 8004c22: 4b0a ldr r3, [pc, #40] @ (8004c4c ) - 8004c24: 623b str r3, [r7, #32] + 8004c5a: 4b0a ldr r3, [pc, #40] @ (8004c84 ) + 8004c5c: 623b str r3, [r7, #32] break; - 8004c26: bf00 nop + 8004c5e: bf00 nop } } return sysclockfreq; - 8004c28: 6a3b ldr r3, [r7, #32] + 8004c60: 6a3b ldr r3, [r7, #32] } - 8004c2a: 4618 mov r0, r3 - 8004c2c: 372c adds r7, #44 @ 0x2c - 8004c2e: 46bd mov sp, r7 - 8004c30: f85d 7b04 ldr.w r7, [sp], #4 - 8004c34: 4770 bx lr - 8004c36: bf00 nop - 8004c38: 40021000 .word 0x40021000 - 8004c3c: 00f42400 .word 0x00f42400 - 8004c40: 08005e84 .word 0x08005e84 - 8004c44: 08005e94 .word 0x08005e94 - 8004c48: 003d0900 .word 0x003d0900 - 8004c4c: 007a1200 .word 0x007a1200 + 8004c62: 4618 mov r0, r3 + 8004c64: 372c adds r7, #44 @ 0x2c + 8004c66: 46bd mov sp, r7 + 8004c68: f85d 7b04 ldr.w r7, [sp], #4 + 8004c6c: 4770 bx lr + 8004c6e: bf00 nop + 8004c70: 40021000 .word 0x40021000 + 8004c74: 00f42400 .word 0x00f42400 + 8004c78: 08005ebc .word 0x08005ebc + 8004c7c: 08005ecc .word 0x08005ecc + 8004c80: 003d0900 .word 0x003d0900 + 8004c84: 007a1200 .word 0x007a1200 -08004c50 : +08004c88 : * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency * and updated within this function * @retval HCLK frequency */ uint32_t HAL_RCC_GetHCLKFreq(void) { - 8004c50: b480 push {r7} - 8004c52: af00 add r7, sp, #0 + 8004c88: b480 push {r7} + 8004c8a: af00 add r7, sp, #0 return SystemCoreClock; - 8004c54: 4b03 ldr r3, [pc, #12] @ (8004c64 ) - 8004c56: 681b ldr r3, [r3, #0] + 8004c8c: 4b03 ldr r3, [pc, #12] @ (8004c9c ) + 8004c8e: 681b ldr r3, [r3, #0] } - 8004c58: 4618 mov r0, r3 - 8004c5a: 46bd mov sp, r7 - 8004c5c: f85d 7b04 ldr.w r7, [sp], #4 - 8004c60: 4770 bx lr - 8004c62: bf00 nop - 8004c64: 20000000 .word 0x20000000 + 8004c90: 4618 mov r0, r3 + 8004c92: 46bd mov sp, r7 + 8004c94: f85d 7b04 ldr.w r7, [sp], #4 + 8004c98: 4770 bx lr + 8004c9a: bf00 nop + 8004c9c: 20000000 .word 0x20000000 -08004c68 : +08004ca0 : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK1Freq(void) { - 8004c68: b580 push {r7, lr} - 8004c6a: b082 sub sp, #8 - 8004c6c: af00 add r7, sp, #0 + 8004ca0: b580 push {r7, lr} + 8004ca2: b082 sub sp, #8 + 8004ca4: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_BITNUMBER]); - 8004c6e: f7ff ffef bl 8004c50 - 8004c72: 4601 mov r1, r0 - 8004c74: 4b0b ldr r3, [pc, #44] @ (8004ca4 ) - 8004c76: 685b ldr r3, [r3, #4] - 8004c78: f403 63e0 and.w r3, r3, #1792 @ 0x700 - 8004c7c: f44f 62e0 mov.w r2, #1792 @ 0x700 - 8004c80: 607a str r2, [r7, #4] + 8004ca6: f7ff ffef bl 8004c88 + 8004caa: 4601 mov r1, r0 + 8004cac: 4b0b ldr r3, [pc, #44] @ (8004cdc ) + 8004cae: 685b ldr r3, [r3, #4] + 8004cb0: f403 63e0 and.w r3, r3, #1792 @ 0x700 + 8004cb4: f44f 62e0 mov.w r2, #1792 @ 0x700 + 8004cb8: 607a str r2, [r7, #4] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8004c82: 687a ldr r2, [r7, #4] - 8004c84: fa92 f2a2 rbit r2, r2 - 8004c88: 603a str r2, [r7, #0] + 8004cba: 687a ldr r2, [r7, #4] + 8004cbc: fa92 f2a2 rbit r2, r2 + 8004cc0: 603a str r2, [r7, #0] return result; - 8004c8a: 683a ldr r2, [r7, #0] - 8004c8c: fab2 f282 clz r2, r2 - 8004c90: b2d2 uxtb r2, r2 - 8004c92: 40d3 lsrs r3, r2 - 8004c94: 4a04 ldr r2, [pc, #16] @ (8004ca8 ) - 8004c96: 5cd3 ldrb r3, [r2, r3] - 8004c98: fa21 f303 lsr.w r3, r1, r3 + 8004cc2: 683a ldr r2, [r7, #0] + 8004cc4: fab2 f282 clz r2, r2 + 8004cc8: b2d2 uxtb r2, r2 + 8004cca: 40d3 lsrs r3, r2 + 8004ccc: 4a04 ldr r2, [pc, #16] @ (8004ce0 ) + 8004cce: 5cd3 ldrb r3, [r2, r3] + 8004cd0: fa21 f303 lsr.w r3, r1, r3 } - 8004c9c: 4618 mov r0, r3 - 8004c9e: 3708 adds r7, #8 - 8004ca0: 46bd mov sp, r7 - 8004ca2: bd80 pop {r7, pc} - 8004ca4: 40021000 .word 0x40021000 - 8004ca8: 08005e7c .word 0x08005e7c + 8004cd4: 4618 mov r0, r3 + 8004cd6: 3708 adds r7, #8 + 8004cd8: 46bd mov sp, r7 + 8004cda: bd80 pop {r7, pc} + 8004cdc: 40021000 .word 0x40021000 + 8004ce0: 08005eb4 .word 0x08005eb4 -08004cac : +08004ce4 : * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK2 frequency */ uint32_t HAL_RCC_GetPCLK2Freq(void) { - 8004cac: b580 push {r7, lr} - 8004cae: b082 sub sp, #8 - 8004cb0: af00 add r7, sp, #0 + 8004ce4: b580 push {r7, lr} + 8004ce6: b082 sub sp, #8 + 8004ce8: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_BITNUMBER]); - 8004cb2: f7ff ffcd bl 8004c50 - 8004cb6: 4601 mov r1, r0 - 8004cb8: 4b0b ldr r3, [pc, #44] @ (8004ce8 ) - 8004cba: 685b ldr r3, [r3, #4] - 8004cbc: f403 5360 and.w r3, r3, #14336 @ 0x3800 - 8004cc0: f44f 5260 mov.w r2, #14336 @ 0x3800 - 8004cc4: 607a str r2, [r7, #4] + 8004cea: f7ff ffcd bl 8004c88 + 8004cee: 4601 mov r1, r0 + 8004cf0: 4b0b ldr r3, [pc, #44] @ (8004d20 ) + 8004cf2: 685b ldr r3, [r3, #4] + 8004cf4: f403 5360 and.w r3, r3, #14336 @ 0x3800 + 8004cf8: f44f 5260 mov.w r2, #14336 @ 0x3800 + 8004cfc: 607a str r2, [r7, #4] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8004cc6: 687a ldr r2, [r7, #4] - 8004cc8: fa92 f2a2 rbit r2, r2 - 8004ccc: 603a str r2, [r7, #0] + 8004cfe: 687a ldr r2, [r7, #4] + 8004d00: fa92 f2a2 rbit r2, r2 + 8004d04: 603a str r2, [r7, #0] return result; - 8004cce: 683a ldr r2, [r7, #0] - 8004cd0: fab2 f282 clz r2, r2 - 8004cd4: b2d2 uxtb r2, r2 - 8004cd6: 40d3 lsrs r3, r2 - 8004cd8: 4a04 ldr r2, [pc, #16] @ (8004cec ) - 8004cda: 5cd3 ldrb r3, [r2, r3] - 8004cdc: fa21 f303 lsr.w r3, r1, r3 + 8004d06: 683a ldr r2, [r7, #0] + 8004d08: fab2 f282 clz r2, r2 + 8004d0c: b2d2 uxtb r2, r2 + 8004d0e: 40d3 lsrs r3, r2 + 8004d10: 4a04 ldr r2, [pc, #16] @ (8004d24 ) + 8004d12: 5cd3 ldrb r3, [r2, r3] + 8004d14: fa21 f303 lsr.w r3, r1, r3 } - 8004ce0: 4618 mov r0, r3 - 8004ce2: 3708 adds r7, #8 - 8004ce4: 46bd mov sp, r7 - 8004ce6: bd80 pop {r7, pc} - 8004ce8: 40021000 .word 0x40021000 - 8004cec: 08005e7c .word 0x08005e7c + 8004d18: 4618 mov r0, r3 + 8004d1a: 3708 adds r7, #8 + 8004d1c: 46bd mov sp, r7 + 8004d1e: bd80 pop {r7, pc} + 8004d20: 40021000 .word 0x40021000 + 8004d24: 08005eb4 .word 0x08005eb4 -08004cf0 : +08004d28 : * When the TIMx clock source is PLL clock, so the TIMx clock is PLL clock x 2. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { - 8004cf0: b580 push {r7, lr} - 8004cf2: b092 sub sp, #72 @ 0x48 - 8004cf4: af00 add r7, sp, #0 - 8004cf6: 6078 str r0, [r7, #4] + 8004d28: b580 push {r7, lr} + 8004d2a: b092 sub sp, #72 @ 0x48 + 8004d2c: af00 add r7, sp, #0 + 8004d2e: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; - 8004cf8: 2300 movs r3, #0 - 8004cfa: 643b str r3, [r7, #64] @ 0x40 + 8004d30: 2300 movs r3, #0 + 8004d32: 643b str r3, [r7, #64] @ 0x40 uint32_t temp_reg = 0U; - 8004cfc: 2300 movs r3, #0 - 8004cfe: 63fb str r3, [r7, #60] @ 0x3c + 8004d34: 2300 movs r3, #0 + 8004d36: 63fb str r3, [r7, #60] @ 0x3c FlagStatus pwrclkchanged = RESET; - 8004d00: 2300 movs r3, #0 - 8004d02: f887 3047 strb.w r3, [r7, #71] @ 0x47 + 8004d38: 2300 movs r3, #0 + 8004d3a: f887 3047 strb.w r3, [r7, #71] @ 0x47 /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); /*---------------------------- RTC configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) - 8004d06: 687b ldr r3, [r7, #4] - 8004d08: 681b ldr r3, [r3, #0] - 8004d0a: f403 3380 and.w r3, r3, #65536 @ 0x10000 - 8004d0e: 2b00 cmp r3, #0 - 8004d10: f000 80d4 beq.w 8004ebc + 8004d3e: 687b ldr r3, [r7, #4] + 8004d40: 681b ldr r3, [r3, #0] + 8004d42: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 8004d46: 2b00 cmp r3, #0 + 8004d48: f000 80d4 beq.w 8004ef4 /* As soon as function is called to change RTC clock source, activation of the power domain is done. */ /* Requires to enable write access to Backup Domain of necessary */ if(__HAL_RCC_PWR_IS_CLK_DISABLED()) - 8004d14: 4b4e ldr r3, [pc, #312] @ (8004e50 ) - 8004d16: 69db ldr r3, [r3, #28] - 8004d18: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 - 8004d1c: 2b00 cmp r3, #0 - 8004d1e: d10e bne.n 8004d3e + 8004d4c: 4b4e ldr r3, [pc, #312] @ (8004e88 ) + 8004d4e: 69db ldr r3, [r3, #28] + 8004d50: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 8004d54: 2b00 cmp r3, #0 + 8004d56: d10e bne.n 8004d76 { __HAL_RCC_PWR_CLK_ENABLE(); - 8004d20: 4b4b ldr r3, [pc, #300] @ (8004e50 ) - 8004d22: 69db ldr r3, [r3, #28] - 8004d24: 4a4a ldr r2, [pc, #296] @ (8004e50 ) - 8004d26: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 - 8004d2a: 61d3 str r3, [r2, #28] - 8004d2c: 4b48 ldr r3, [pc, #288] @ (8004e50 ) - 8004d2e: 69db ldr r3, [r3, #28] - 8004d30: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 - 8004d34: 60bb str r3, [r7, #8] - 8004d36: 68bb ldr r3, [r7, #8] + 8004d58: 4b4b ldr r3, [pc, #300] @ (8004e88 ) + 8004d5a: 69db ldr r3, [r3, #28] + 8004d5c: 4a4a ldr r2, [pc, #296] @ (8004e88 ) + 8004d5e: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 8004d62: 61d3 str r3, [r2, #28] + 8004d64: 4b48 ldr r3, [pc, #288] @ (8004e88 ) + 8004d66: 69db ldr r3, [r3, #28] + 8004d68: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 8004d6c: 60bb str r3, [r7, #8] + 8004d6e: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; - 8004d38: 2301 movs r3, #1 - 8004d3a: f887 3047 strb.w r3, [r7, #71] @ 0x47 + 8004d70: 2301 movs r3, #1 + 8004d72: f887 3047 strb.w r3, [r7, #71] @ 0x47 } if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) - 8004d3e: 4b45 ldr r3, [pc, #276] @ (8004e54 ) - 8004d40: 681b ldr r3, [r3, #0] - 8004d42: f403 7380 and.w r3, r3, #256 @ 0x100 - 8004d46: 2b00 cmp r3, #0 - 8004d48: d118 bne.n 8004d7c + 8004d76: 4b45 ldr r3, [pc, #276] @ (8004e8c ) + 8004d78: 681b ldr r3, [r3, #0] + 8004d7a: f403 7380 and.w r3, r3, #256 @ 0x100 + 8004d7e: 2b00 cmp r3, #0 + 8004d80: d118 bne.n 8004db4 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); - 8004d4a: 4b42 ldr r3, [pc, #264] @ (8004e54 ) - 8004d4c: 681b ldr r3, [r3, #0] - 8004d4e: 4a41 ldr r2, [pc, #260] @ (8004e54 ) - 8004d50: f443 7380 orr.w r3, r3, #256 @ 0x100 - 8004d54: 6013 str r3, [r2, #0] + 8004d82: 4b42 ldr r3, [pc, #264] @ (8004e8c ) + 8004d84: 681b ldr r3, [r3, #0] + 8004d86: 4a41 ldr r2, [pc, #260] @ (8004e8c ) + 8004d88: f443 7380 orr.w r3, r3, #256 @ 0x100 + 8004d8c: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); - 8004d56: f7fc fb4f bl 80013f8 - 8004d5a: 6438 str r0, [r7, #64] @ 0x40 + 8004d8e: f7fc fb4f bl 8001430 + 8004d92: 6438 str r0, [r7, #64] @ 0x40 while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) - 8004d5c: e008 b.n 8004d70 + 8004d94: e008 b.n 8004da8 { if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) - 8004d5e: f7fc fb4b bl 80013f8 - 8004d62: 4602 mov r2, r0 - 8004d64: 6c3b ldr r3, [r7, #64] @ 0x40 - 8004d66: 1ad3 subs r3, r2, r3 - 8004d68: 2b64 cmp r3, #100 @ 0x64 - 8004d6a: d901 bls.n 8004d70 + 8004d96: f7fc fb4b bl 8001430 + 8004d9a: 4602 mov r2, r0 + 8004d9c: 6c3b ldr r3, [r7, #64] @ 0x40 + 8004d9e: 1ad3 subs r3, r2, r3 + 8004da0: 2b64 cmp r3, #100 @ 0x64 + 8004da2: d901 bls.n 8004da8 { return HAL_TIMEOUT; - 8004d6c: 2303 movs r3, #3 - 8004d6e: e14b b.n 8005008 + 8004da4: 2303 movs r3, #3 + 8004da6: e14b b.n 8005040 while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) - 8004d70: 4b38 ldr r3, [pc, #224] @ (8004e54 ) - 8004d72: 681b ldr r3, [r3, #0] - 8004d74: f403 7380 and.w r3, r3, #256 @ 0x100 - 8004d78: 2b00 cmp r3, #0 - 8004d7a: d0f0 beq.n 8004d5e + 8004da8: 4b38 ldr r3, [pc, #224] @ (8004e8c ) + 8004daa: 681b ldr r3, [r3, #0] + 8004dac: f403 7380 and.w r3, r3, #256 @ 0x100 + 8004db0: 2b00 cmp r3, #0 + 8004db2: d0f0 beq.n 8004d96 } } } /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL); - 8004d7c: 4b34 ldr r3, [pc, #208] @ (8004e50 ) - 8004d7e: 6a1b ldr r3, [r3, #32] - 8004d80: f403 7340 and.w r3, r3, #768 @ 0x300 - 8004d84: 63fb str r3, [r7, #60] @ 0x3c + 8004db4: 4b34 ldr r3, [pc, #208] @ (8004e88 ) + 8004db6: 6a1b ldr r3, [r3, #32] + 8004db8: f403 7340 and.w r3, r3, #768 @ 0x300 + 8004dbc: 63fb str r3, [r7, #60] @ 0x3c if((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) - 8004d86: 6bfb ldr r3, [r7, #60] @ 0x3c - 8004d88: 2b00 cmp r3, #0 - 8004d8a: f000 8084 beq.w 8004e96 - 8004d8e: 687b ldr r3, [r7, #4] - 8004d90: 685b ldr r3, [r3, #4] - 8004d92: f403 7340 and.w r3, r3, #768 @ 0x300 - 8004d96: 6bfa ldr r2, [r7, #60] @ 0x3c - 8004d98: 429a cmp r2, r3 - 8004d9a: d07c beq.n 8004e96 + 8004dbe: 6bfb ldr r3, [r7, #60] @ 0x3c + 8004dc0: 2b00 cmp r3, #0 + 8004dc2: f000 8084 beq.w 8004ece + 8004dc6: 687b ldr r3, [r7, #4] + 8004dc8: 685b ldr r3, [r3, #4] + 8004dca: f403 7340 and.w r3, r3, #768 @ 0x300 + 8004dce: 6bfa ldr r2, [r7, #60] @ 0x3c + 8004dd0: 429a cmp r2, r3 + 8004dd2: d07c beq.n 8004ece { /* Store the content of BDCR register before the reset of Backup Domain */ temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); - 8004d9c: 4b2c ldr r3, [pc, #176] @ (8004e50 ) - 8004d9e: 6a1b ldr r3, [r3, #32] - 8004da0: f423 7340 bic.w r3, r3, #768 @ 0x300 - 8004da4: 63fb str r3, [r7, #60] @ 0x3c - 8004da6: f44f 3380 mov.w r3, #65536 @ 0x10000 - 8004daa: 633b str r3, [r7, #48] @ 0x30 + 8004dd4: 4b2c ldr r3, [pc, #176] @ (8004e88 ) + 8004dd6: 6a1b ldr r3, [r3, #32] + 8004dd8: f423 7340 bic.w r3, r3, #768 @ 0x300 + 8004ddc: 63fb str r3, [r7, #60] @ 0x3c + 8004dde: f44f 3380 mov.w r3, #65536 @ 0x10000 + 8004de2: 633b str r3, [r7, #48] @ 0x30 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8004dac: 6b3b ldr r3, [r7, #48] @ 0x30 - 8004dae: fa93 f3a3 rbit r3, r3 - 8004db2: 62fb str r3, [r7, #44] @ 0x2c + 8004de4: 6b3b ldr r3, [r7, #48] @ 0x30 + 8004de6: fa93 f3a3 rbit r3, r3 + 8004dea: 62fb str r3, [r7, #44] @ 0x2c return result; - 8004db4: 6afb ldr r3, [r7, #44] @ 0x2c + 8004dec: 6afb ldr r3, [r7, #44] @ 0x2c /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); - 8004db6: fab3 f383 clz r3, r3 - 8004dba: b2db uxtb r3, r3 - 8004dbc: 461a mov r2, r3 - 8004dbe: 4b26 ldr r3, [pc, #152] @ (8004e58 ) - 8004dc0: 4413 add r3, r2 - 8004dc2: 009b lsls r3, r3, #2 - 8004dc4: 461a mov r2, r3 - 8004dc6: 2301 movs r3, #1 - 8004dc8: 6013 str r3, [r2, #0] - 8004dca: f44f 3380 mov.w r3, #65536 @ 0x10000 - 8004dce: 63bb str r3, [r7, #56] @ 0x38 + 8004dee: fab3 f383 clz r3, r3 + 8004df2: b2db uxtb r3, r3 + 8004df4: 461a mov r2, r3 + 8004df6: 4b26 ldr r3, [pc, #152] @ (8004e90 ) + 8004df8: 4413 add r3, r2 + 8004dfa: 009b lsls r3, r3, #2 + 8004dfc: 461a mov r2, r3 + 8004dfe: 2301 movs r3, #1 + 8004e00: 6013 str r3, [r2, #0] + 8004e02: f44f 3380 mov.w r3, #65536 @ 0x10000 + 8004e06: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8004dd0: 6bbb ldr r3, [r7, #56] @ 0x38 - 8004dd2: fa93 f3a3 rbit r3, r3 - 8004dd6: 637b str r3, [r7, #52] @ 0x34 + 8004e08: 6bbb ldr r3, [r7, #56] @ 0x38 + 8004e0a: fa93 f3a3 rbit r3, r3 + 8004e0e: 637b str r3, [r7, #52] @ 0x34 return result; - 8004dd8: 6b7b ldr r3, [r7, #52] @ 0x34 + 8004e10: 6b7b ldr r3, [r7, #52] @ 0x34 __HAL_RCC_BACKUPRESET_RELEASE(); - 8004dda: fab3 f383 clz r3, r3 - 8004dde: b2db uxtb r3, r3 - 8004de0: 461a mov r2, r3 - 8004de2: 4b1d ldr r3, [pc, #116] @ (8004e58 ) - 8004de4: 4413 add r3, r2 - 8004de6: 009b lsls r3, r3, #2 - 8004de8: 461a mov r2, r3 - 8004dea: 2300 movs r3, #0 - 8004dec: 6013 str r3, [r2, #0] + 8004e12: fab3 f383 clz r3, r3 + 8004e16: b2db uxtb r3, r3 + 8004e18: 461a mov r2, r3 + 8004e1a: 4b1d ldr r3, [pc, #116] @ (8004e90 ) + 8004e1c: 4413 add r3, r2 + 8004e1e: 009b lsls r3, r3, #2 + 8004e20: 461a mov r2, r3 + 8004e22: 2300 movs r3, #0 + 8004e24: 6013 str r3, [r2, #0] /* Restore the Content of BDCR register */ RCC->BDCR = temp_reg; - 8004dee: 4a18 ldr r2, [pc, #96] @ (8004e50 ) - 8004df0: 6bfb ldr r3, [r7, #60] @ 0x3c - 8004df2: 6213 str r3, [r2, #32] + 8004e26: 4a18 ldr r2, [pc, #96] @ (8004e88 ) + 8004e28: 6bfb ldr r3, [r7, #60] @ 0x3c + 8004e2a: 6213 str r3, [r2, #32] /* Wait for LSERDY if LSE was enabled */ if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON)) - 8004df4: 6bfb ldr r3, [r7, #60] @ 0x3c - 8004df6: f003 0301 and.w r3, r3, #1 - 8004dfa: 2b00 cmp r3, #0 - 8004dfc: d04b beq.n 8004e96 + 8004e2c: 6bfb ldr r3, [r7, #60] @ 0x3c + 8004e2e: f003 0301 and.w r3, r3, #1 + 8004e32: 2b00 cmp r3, #0 + 8004e34: d04b beq.n 8004ece { /* Get Start Tick */ tickstart = HAL_GetTick(); - 8004dfe: f7fc fafb bl 80013f8 - 8004e02: 6438 str r0, [r7, #64] @ 0x40 + 8004e36: f7fc fafb bl 8001430 + 8004e3a: 6438 str r0, [r7, #64] @ 0x40 /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) - 8004e04: e00a b.n 8004e1c + 8004e3c: e00a b.n 8004e54 { if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) - 8004e06: f7fc faf7 bl 80013f8 - 8004e0a: 4602 mov r2, r0 - 8004e0c: 6c3b ldr r3, [r7, #64] @ 0x40 - 8004e0e: 1ad3 subs r3, r2, r3 - 8004e10: f241 3288 movw r2, #5000 @ 0x1388 - 8004e14: 4293 cmp r3, r2 - 8004e16: d901 bls.n 8004e1c + 8004e3e: f7fc faf7 bl 8001430 + 8004e42: 4602 mov r2, r0 + 8004e44: 6c3b ldr r3, [r7, #64] @ 0x40 + 8004e46: 1ad3 subs r3, r2, r3 + 8004e48: f241 3288 movw r2, #5000 @ 0x1388 + 8004e4c: 4293 cmp r3, r2 + 8004e4e: d901 bls.n 8004e54 { return HAL_TIMEOUT; - 8004e18: 2303 movs r3, #3 - 8004e1a: e0f5 b.n 8005008 - 8004e1c: 2302 movs r3, #2 - 8004e1e: 62bb str r3, [r7, #40] @ 0x28 + 8004e50: 2303 movs r3, #3 + 8004e52: e0f5 b.n 8005040 + 8004e54: 2302 movs r3, #2 + 8004e56: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8004e20: 6abb ldr r3, [r7, #40] @ 0x28 - 8004e22: fa93 f3a3 rbit r3, r3 - 8004e26: 627b str r3, [r7, #36] @ 0x24 - 8004e28: 2302 movs r3, #2 - 8004e2a: 623b str r3, [r7, #32] - 8004e2c: 6a3b ldr r3, [r7, #32] - 8004e2e: fa93 f3a3 rbit r3, r3 - 8004e32: 61fb str r3, [r7, #28] + 8004e58: 6abb ldr r3, [r7, #40] @ 0x28 + 8004e5a: fa93 f3a3 rbit r3, r3 + 8004e5e: 627b str r3, [r7, #36] @ 0x24 + 8004e60: 2302 movs r3, #2 + 8004e62: 623b str r3, [r7, #32] + 8004e64: 6a3b ldr r3, [r7, #32] + 8004e66: fa93 f3a3 rbit r3, r3 + 8004e6a: 61fb str r3, [r7, #28] return result; - 8004e34: 69fb ldr r3, [r7, #28] + 8004e6c: 69fb ldr r3, [r7, #28] while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) - 8004e36: fab3 f383 clz r3, r3 - 8004e3a: b2db uxtb r3, r3 - 8004e3c: 095b lsrs r3, r3, #5 - 8004e3e: b2db uxtb r3, r3 - 8004e40: f043 0302 orr.w r3, r3, #2 - 8004e44: b2db uxtb r3, r3 - 8004e46: 2b02 cmp r3, #2 - 8004e48: d108 bne.n 8004e5c - 8004e4a: 4b01 ldr r3, [pc, #4] @ (8004e50 ) - 8004e4c: 6a1b ldr r3, [r3, #32] - 8004e4e: e00d b.n 8004e6c - 8004e50: 40021000 .word 0x40021000 - 8004e54: 40007000 .word 0x40007000 - 8004e58: 10908100 .word 0x10908100 - 8004e5c: 2302 movs r3, #2 - 8004e5e: 61bb str r3, [r7, #24] + 8004e6e: fab3 f383 clz r3, r3 + 8004e72: b2db uxtb r3, r3 + 8004e74: 095b lsrs r3, r3, #5 + 8004e76: b2db uxtb r3, r3 + 8004e78: f043 0302 orr.w r3, r3, #2 + 8004e7c: b2db uxtb r3, r3 + 8004e7e: 2b02 cmp r3, #2 + 8004e80: d108 bne.n 8004e94 + 8004e82: 4b01 ldr r3, [pc, #4] @ (8004e88 ) + 8004e84: 6a1b ldr r3, [r3, #32] + 8004e86: e00d b.n 8004ea4 + 8004e88: 40021000 .word 0x40021000 + 8004e8c: 40007000 .word 0x40007000 + 8004e90: 10908100 .word 0x10908100 + 8004e94: 2302 movs r3, #2 + 8004e96: 61bb str r3, [r7, #24] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8004e60: 69bb ldr r3, [r7, #24] - 8004e62: fa93 f3a3 rbit r3, r3 - 8004e66: 617b str r3, [r7, #20] - 8004e68: 4b69 ldr r3, [pc, #420] @ (8005010 ) - 8004e6a: 6a5b ldr r3, [r3, #36] @ 0x24 - 8004e6c: 2202 movs r2, #2 - 8004e6e: 613a str r2, [r7, #16] - 8004e70: 693a ldr r2, [r7, #16] - 8004e72: fa92 f2a2 rbit r2, r2 - 8004e76: 60fa str r2, [r7, #12] + 8004e98: 69bb ldr r3, [r7, #24] + 8004e9a: fa93 f3a3 rbit r3, r3 + 8004e9e: 617b str r3, [r7, #20] + 8004ea0: 4b69 ldr r3, [pc, #420] @ (8005048 ) + 8004ea2: 6a5b ldr r3, [r3, #36] @ 0x24 + 8004ea4: 2202 movs r2, #2 + 8004ea6: 613a str r2, [r7, #16] + 8004ea8: 693a ldr r2, [r7, #16] + 8004eaa: fa92 f2a2 rbit r2, r2 + 8004eae: 60fa str r2, [r7, #12] return result; - 8004e78: 68fa ldr r2, [r7, #12] - 8004e7a: fab2 f282 clz r2, r2 - 8004e7e: b2d2 uxtb r2, r2 - 8004e80: f042 0240 orr.w r2, r2, #64 @ 0x40 - 8004e84: b2d2 uxtb r2, r2 - 8004e86: f002 021f and.w r2, r2, #31 - 8004e8a: 2101 movs r1, #1 - 8004e8c: fa01 f202 lsl.w r2, r1, r2 - 8004e90: 4013 ands r3, r2 - 8004e92: 2b00 cmp r3, #0 - 8004e94: d0b7 beq.n 8004e06 + 8004eb0: 68fa ldr r2, [r7, #12] + 8004eb2: fab2 f282 clz r2, r2 + 8004eb6: b2d2 uxtb r2, r2 + 8004eb8: f042 0240 orr.w r2, r2, #64 @ 0x40 + 8004ebc: b2d2 uxtb r2, r2 + 8004ebe: f002 021f and.w r2, r2, #31 + 8004ec2: 2101 movs r1, #1 + 8004ec4: fa01 f202 lsl.w r2, r1, r2 + 8004ec8: 4013 ands r3, r2 + 8004eca: 2b00 cmp r3, #0 + 8004ecc: d0b7 beq.n 8004e3e } } } } __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); - 8004e96: 4b5e ldr r3, [pc, #376] @ (8005010 ) - 8004e98: 6a1b ldr r3, [r3, #32] - 8004e9a: f423 7240 bic.w r2, r3, #768 @ 0x300 - 8004e9e: 687b ldr r3, [r7, #4] - 8004ea0: 685b ldr r3, [r3, #4] - 8004ea2: 495b ldr r1, [pc, #364] @ (8005010 ) - 8004ea4: 4313 orrs r3, r2 - 8004ea6: 620b str r3, [r1, #32] + 8004ece: 4b5e ldr r3, [pc, #376] @ (8005048 ) + 8004ed0: 6a1b ldr r3, [r3, #32] + 8004ed2: f423 7240 bic.w r2, r3, #768 @ 0x300 + 8004ed6: 687b ldr r3, [r7, #4] + 8004ed8: 685b ldr r3, [r3, #4] + 8004eda: 495b ldr r1, [pc, #364] @ (8005048 ) + 8004edc: 4313 orrs r3, r2 + 8004ede: 620b str r3, [r1, #32] /* Require to disable power clock if necessary */ if(pwrclkchanged == SET) - 8004ea8: f897 3047 ldrb.w r3, [r7, #71] @ 0x47 - 8004eac: 2b01 cmp r3, #1 - 8004eae: d105 bne.n 8004ebc + 8004ee0: f897 3047 ldrb.w r3, [r7, #71] @ 0x47 + 8004ee4: 2b01 cmp r3, #1 + 8004ee6: d105 bne.n 8004ef4 { __HAL_RCC_PWR_CLK_DISABLE(); - 8004eb0: 4b57 ldr r3, [pc, #348] @ (8005010 ) - 8004eb2: 69db ldr r3, [r3, #28] - 8004eb4: 4a56 ldr r2, [pc, #344] @ (8005010 ) - 8004eb6: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 - 8004eba: 61d3 str r3, [r2, #28] + 8004ee8: 4b57 ldr r3, [pc, #348] @ (8005048 ) + 8004eea: 69db ldr r3, [r3, #28] + 8004eec: 4a56 ldr r2, [pc, #344] @ (8005048 ) + 8004eee: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 + 8004ef2: 61d3 str r3, [r2, #28] } } /*------------------------------- USART1 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) - 8004ebc: 687b ldr r3, [r7, #4] - 8004ebe: 681b ldr r3, [r3, #0] - 8004ec0: f003 0301 and.w r3, r3, #1 - 8004ec4: 2b00 cmp r3, #0 - 8004ec6: d008 beq.n 8004eda + 8004ef4: 687b ldr r3, [r7, #4] + 8004ef6: 681b ldr r3, [r3, #0] + 8004ef8: f003 0301 and.w r3, r3, #1 + 8004efc: 2b00 cmp r3, #0 + 8004efe: d008 beq.n 8004f12 { /* Check the parameters */ assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); /* Configure the USART1 clock source */ __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); - 8004ec8: 4b51 ldr r3, [pc, #324] @ (8005010 ) - 8004eca: 6b1b ldr r3, [r3, #48] @ 0x30 - 8004ecc: f023 0203 bic.w r2, r3, #3 - 8004ed0: 687b ldr r3, [r7, #4] - 8004ed2: 689b ldr r3, [r3, #8] - 8004ed4: 494e ldr r1, [pc, #312] @ (8005010 ) - 8004ed6: 4313 orrs r3, r2 - 8004ed8: 630b str r3, [r1, #48] @ 0x30 + 8004f00: 4b51 ldr r3, [pc, #324] @ (8005048 ) + 8004f02: 6b1b ldr r3, [r3, #48] @ 0x30 + 8004f04: f023 0203 bic.w r2, r3, #3 + 8004f08: 687b ldr r3, [r7, #4] + 8004f0a: 689b ldr r3, [r3, #8] + 8004f0c: 494e ldr r1, [pc, #312] @ (8005048 ) + 8004f0e: 4313 orrs r3, r2 + 8004f10: 630b str r3, [r1, #48] @ 0x30 } #if defined(RCC_CFGR3_USART2SW) /*----------------------------- USART2 Configuration --------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) - 8004eda: 687b ldr r3, [r7, #4] - 8004edc: 681b ldr r3, [r3, #0] - 8004ede: f003 0302 and.w r3, r3, #2 - 8004ee2: 2b00 cmp r3, #0 - 8004ee4: d008 beq.n 8004ef8 + 8004f12: 687b ldr r3, [r7, #4] + 8004f14: 681b ldr r3, [r3, #0] + 8004f16: f003 0302 and.w r3, r3, #2 + 8004f1a: 2b00 cmp r3, #0 + 8004f1c: d008 beq.n 8004f30 { /* Check the parameters */ assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); /* Configure the USART2 clock source */ __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); - 8004ee6: 4b4a ldr r3, [pc, #296] @ (8005010 ) - 8004ee8: 6b1b ldr r3, [r3, #48] @ 0x30 - 8004eea: f423 3240 bic.w r2, r3, #196608 @ 0x30000 - 8004eee: 687b ldr r3, [r7, #4] - 8004ef0: 68db ldr r3, [r3, #12] - 8004ef2: 4947 ldr r1, [pc, #284] @ (8005010 ) - 8004ef4: 4313 orrs r3, r2 - 8004ef6: 630b str r3, [r1, #48] @ 0x30 + 8004f1e: 4b4a ldr r3, [pc, #296] @ (8005048 ) + 8004f20: 6b1b ldr r3, [r3, #48] @ 0x30 + 8004f22: f423 3240 bic.w r2, r3, #196608 @ 0x30000 + 8004f26: 687b ldr r3, [r7, #4] + 8004f28: 68db ldr r3, [r3, #12] + 8004f2a: 4947 ldr r1, [pc, #284] @ (8005048 ) + 8004f2c: 4313 orrs r3, r2 + 8004f2e: 630b str r3, [r1, #48] @ 0x30 } #endif /* RCC_CFGR3_USART2SW */ #if defined(RCC_CFGR3_USART3SW) /*------------------------------ USART3 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) - 8004ef8: 687b ldr r3, [r7, #4] - 8004efa: 681b ldr r3, [r3, #0] - 8004efc: f003 0304 and.w r3, r3, #4 - 8004f00: 2b00 cmp r3, #0 - 8004f02: d008 beq.n 8004f16 + 8004f30: 687b ldr r3, [r7, #4] + 8004f32: 681b ldr r3, [r3, #0] + 8004f34: f003 0304 and.w r3, r3, #4 + 8004f38: 2b00 cmp r3, #0 + 8004f3a: d008 beq.n 8004f4e { /* Check the parameters */ assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection)); /* Configure the USART3 clock source */ __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection); - 8004f04: 4b42 ldr r3, [pc, #264] @ (8005010 ) - 8004f06: 6b1b ldr r3, [r3, #48] @ 0x30 - 8004f08: f423 2240 bic.w r2, r3, #786432 @ 0xc0000 - 8004f0c: 687b ldr r3, [r7, #4] - 8004f0e: 691b ldr r3, [r3, #16] - 8004f10: 493f ldr r1, [pc, #252] @ (8005010 ) - 8004f12: 4313 orrs r3, r2 - 8004f14: 630b str r3, [r1, #48] @ 0x30 + 8004f3c: 4b42 ldr r3, [pc, #264] @ (8005048 ) + 8004f3e: 6b1b ldr r3, [r3, #48] @ 0x30 + 8004f40: f423 2240 bic.w r2, r3, #786432 @ 0xc0000 + 8004f44: 687b ldr r3, [r7, #4] + 8004f46: 691b ldr r3, [r3, #16] + 8004f48: 493f ldr r1, [pc, #252] @ (8005048 ) + 8004f4a: 4313 orrs r3, r2 + 8004f4c: 630b str r3, [r1, #48] @ 0x30 } #endif /* RCC_CFGR3_USART3SW */ /*------------------------------ I2C1 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) - 8004f16: 687b ldr r3, [r7, #4] - 8004f18: 681b ldr r3, [r3, #0] - 8004f1a: f003 0320 and.w r3, r3, #32 - 8004f1e: 2b00 cmp r3, #0 - 8004f20: d008 beq.n 8004f34 + 8004f4e: 687b ldr r3, [r7, #4] + 8004f50: 681b ldr r3, [r3, #0] + 8004f52: f003 0320 and.w r3, r3, #32 + 8004f56: 2b00 cmp r3, #0 + 8004f58: d008 beq.n 8004f6c { /* Check the parameters */ assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); /* Configure the I2C1 clock source */ __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); - 8004f22: 4b3b ldr r3, [pc, #236] @ (8005010 ) - 8004f24: 6b1b ldr r3, [r3, #48] @ 0x30 - 8004f26: f023 0210 bic.w r2, r3, #16 - 8004f2a: 687b ldr r3, [r7, #4] - 8004f2c: 69db ldr r3, [r3, #28] - 8004f2e: 4938 ldr r1, [pc, #224] @ (8005010 ) - 8004f30: 4313 orrs r3, r2 - 8004f32: 630b str r3, [r1, #48] @ 0x30 + 8004f5a: 4b3b ldr r3, [pc, #236] @ (8005048 ) + 8004f5c: 6b1b ldr r3, [r3, #48] @ 0x30 + 8004f5e: f023 0210 bic.w r2, r3, #16 + 8004f62: 687b ldr r3, [r7, #4] + 8004f64: 69db ldr r3, [r3, #28] + 8004f66: 4938 ldr r1, [pc, #224] @ (8005048 ) + 8004f68: 4313 orrs r3, r2 + 8004f6a: 630b str r3, [r1, #48] @ 0x30 #if defined(STM32F302xE) || defined(STM32F303xE)\ || defined(STM32F302xC) || defined(STM32F303xC)\ || defined(STM32F302x8) \ || defined(STM32F373xC) /*------------------------------ USB Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) - 8004f34: 687b ldr r3, [r7, #4] - 8004f36: 681b ldr r3, [r3, #0] - 8004f38: f403 3300 and.w r3, r3, #131072 @ 0x20000 - 8004f3c: 2b00 cmp r3, #0 - 8004f3e: d008 beq.n 8004f52 + 8004f6c: 687b ldr r3, [r7, #4] + 8004f6e: 681b ldr r3, [r3, #0] + 8004f70: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 8004f74: 2b00 cmp r3, #0 + 8004f76: d008 beq.n 8004f8a { /* Check the parameters */ assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->USBClockSelection)); /* Configure the USB clock source */ __HAL_RCC_USB_CONFIG(PeriphClkInit->USBClockSelection); - 8004f40: 4b33 ldr r3, [pc, #204] @ (8005010 ) - 8004f42: 685b ldr r3, [r3, #4] - 8004f44: f423 0280 bic.w r2, r3, #4194304 @ 0x400000 - 8004f48: 687b ldr r3, [r7, #4] - 8004f4a: 6b1b ldr r3, [r3, #48] @ 0x30 - 8004f4c: 4930 ldr r1, [pc, #192] @ (8005010 ) - 8004f4e: 4313 orrs r3, r2 - 8004f50: 604b str r3, [r1, #4] + 8004f78: 4b33 ldr r3, [pc, #204] @ (8005048 ) + 8004f7a: 685b ldr r3, [r3, #4] + 8004f7c: f423 0280 bic.w r2, r3, #4194304 @ 0x400000 + 8004f80: 687b ldr r3, [r7, #4] + 8004f82: 6b1b ldr r3, [r3, #48] @ 0x30 + 8004f84: 4930 ldr r1, [pc, #192] @ (8005048 ) + 8004f86: 4313 orrs r3, r2 + 8004f88: 604b str r3, [r1, #4] || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\ || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)\ || defined(STM32F373xC) || defined(STM32F378xx) /*------------------------------ I2C2 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) - 8004f52: 687b ldr r3, [r7, #4] - 8004f54: 681b ldr r3, [r3, #0] - 8004f56: f003 0340 and.w r3, r3, #64 @ 0x40 - 8004f5a: 2b00 cmp r3, #0 - 8004f5c: d008 beq.n 8004f70 + 8004f8a: 687b ldr r3, [r7, #4] + 8004f8c: 681b ldr r3, [r3, #0] + 8004f8e: f003 0340 and.w r3, r3, #64 @ 0x40 + 8004f92: 2b00 cmp r3, #0 + 8004f94: d008 beq.n 8004fa8 { /* Check the parameters */ assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection)); /* Configure the I2C2 clock source */ __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection); - 8004f5e: 4b2c ldr r3, [pc, #176] @ (8005010 ) - 8004f60: 6b1b ldr r3, [r3, #48] @ 0x30 - 8004f62: f023 0220 bic.w r2, r3, #32 - 8004f66: 687b ldr r3, [r7, #4] - 8004f68: 6a1b ldr r3, [r3, #32] - 8004f6a: 4929 ldr r1, [pc, #164] @ (8005010 ) - 8004f6c: 4313 orrs r3, r2 - 8004f6e: 630b str r3, [r1, #48] @ 0x30 + 8004f96: 4b2c ldr r3, [pc, #176] @ (8005048 ) + 8004f98: 6b1b ldr r3, [r3, #48] @ 0x30 + 8004f9a: f023 0220 bic.w r2, r3, #32 + 8004f9e: 687b ldr r3, [r7, #4] + 8004fa0: 6a1b ldr r3, [r3, #32] + 8004fa2: 4929 ldr r1, [pc, #164] @ (8005048 ) + 8004fa4: 4313 orrs r3, r2 + 8004fa6: 630b str r3, [r1, #48] @ 0x30 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) /*------------------------------ UART4 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) - 8004f70: 687b ldr r3, [r7, #4] - 8004f72: 681b ldr r3, [r3, #0] - 8004f74: f003 0308 and.w r3, r3, #8 - 8004f78: 2b00 cmp r3, #0 - 8004f7a: d008 beq.n 8004f8e + 8004fa8: 687b ldr r3, [r7, #4] + 8004faa: 681b ldr r3, [r3, #0] + 8004fac: f003 0308 and.w r3, r3, #8 + 8004fb0: 2b00 cmp r3, #0 + 8004fb2: d008 beq.n 8004fc6 { /* Check the parameters */ assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection)); /* Configure the UART4 clock source */ __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection); - 8004f7c: 4b24 ldr r3, [pc, #144] @ (8005010 ) - 8004f7e: 6b1b ldr r3, [r3, #48] @ 0x30 - 8004f80: f423 1240 bic.w r2, r3, #3145728 @ 0x300000 - 8004f84: 687b ldr r3, [r7, #4] - 8004f86: 695b ldr r3, [r3, #20] - 8004f88: 4921 ldr r1, [pc, #132] @ (8005010 ) - 8004f8a: 4313 orrs r3, r2 - 8004f8c: 630b str r3, [r1, #48] @ 0x30 + 8004fb4: 4b24 ldr r3, [pc, #144] @ (8005048 ) + 8004fb6: 6b1b ldr r3, [r3, #48] @ 0x30 + 8004fb8: f423 1240 bic.w r2, r3, #3145728 @ 0x300000 + 8004fbc: 687b ldr r3, [r7, #4] + 8004fbe: 695b ldr r3, [r3, #20] + 8004fc0: 4921 ldr r1, [pc, #132] @ (8005048 ) + 8004fc2: 4313 orrs r3, r2 + 8004fc4: 630b str r3, [r1, #48] @ 0x30 } /*------------------------------ UART5 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) - 8004f8e: 687b ldr r3, [r7, #4] - 8004f90: 681b ldr r3, [r3, #0] - 8004f92: f003 0310 and.w r3, r3, #16 - 8004f96: 2b00 cmp r3, #0 - 8004f98: d008 beq.n 8004fac + 8004fc6: 687b ldr r3, [r7, #4] + 8004fc8: 681b ldr r3, [r3, #0] + 8004fca: f003 0310 and.w r3, r3, #16 + 8004fce: 2b00 cmp r3, #0 + 8004fd0: d008 beq.n 8004fe4 { /* Check the parameters */ assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection)); /* Configure the UART5 clock source */ __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection); - 8004f9a: 4b1d ldr r3, [pc, #116] @ (8005010 ) - 8004f9c: 6b1b ldr r3, [r3, #48] @ 0x30 - 8004f9e: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000 - 8004fa2: 687b ldr r3, [r7, #4] - 8004fa4: 699b ldr r3, [r3, #24] - 8004fa6: 491a ldr r1, [pc, #104] @ (8005010 ) - 8004fa8: 4313 orrs r3, r2 - 8004faa: 630b str r3, [r1, #48] @ 0x30 + 8004fd2: 4b1d ldr r3, [pc, #116] @ (8005048 ) + 8004fd4: 6b1b ldr r3, [r3, #48] @ 0x30 + 8004fd6: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000 + 8004fda: 687b ldr r3, [r7, #4] + 8004fdc: 699b ldr r3, [r3, #24] + 8004fde: 491a ldr r1, [pc, #104] @ (8005048 ) + 8004fe0: 4313 orrs r3, r2 + 8004fe2: 630b str r3, [r1, #48] @ 0x30 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\ || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) /*------------------------------ I2S Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) - 8004fac: 687b ldr r3, [r7, #4] - 8004fae: 681b ldr r3, [r3, #0] - 8004fb0: f403 7300 and.w r3, r3, #512 @ 0x200 - 8004fb4: 2b00 cmp r3, #0 - 8004fb6: d008 beq.n 8004fca + 8004fe4: 687b ldr r3, [r7, #4] + 8004fe6: 681b ldr r3, [r3, #0] + 8004fe8: f403 7300 and.w r3, r3, #512 @ 0x200 + 8004fec: 2b00 cmp r3, #0 + 8004fee: d008 beq.n 8005002 { /* Check the parameters */ assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection)); /* Configure the I2S clock source */ __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection); - 8004fb8: 4b15 ldr r3, [pc, #84] @ (8005010 ) - 8004fba: 685b ldr r3, [r3, #4] - 8004fbc: f423 0200 bic.w r2, r3, #8388608 @ 0x800000 - 8004fc0: 687b ldr r3, [r7, #4] - 8004fc2: 6a9b ldr r3, [r3, #40] @ 0x28 - 8004fc4: 4912 ldr r1, [pc, #72] @ (8005010 ) - 8004fc6: 4313 orrs r3, r2 - 8004fc8: 604b str r3, [r1, #4] + 8004ff0: 4b15 ldr r3, [pc, #84] @ (8005048 ) + 8004ff2: 685b ldr r3, [r3, #4] + 8004ff4: f423 0200 bic.w r2, r3, #8388608 @ 0x800000 + 8004ff8: 687b ldr r3, [r7, #4] + 8004ffa: 6a9b ldr r3, [r3, #40] @ 0x28 + 8004ffc: 4912 ldr r1, [pc, #72] @ (8005048 ) + 8004ffe: 4313 orrs r3, r2 + 8005000: 604b str r3, [r1, #4] #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\ || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) /*------------------------------ ADC1 & ADC2 clock Configuration -------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) - 8004fca: 687b ldr r3, [r7, #4] - 8004fcc: 681b ldr r3, [r3, #0] - 8004fce: f003 0380 and.w r3, r3, #128 @ 0x80 - 8004fd2: 2b00 cmp r3, #0 - 8004fd4: d008 beq.n 8004fe8 + 8005002: 687b ldr r3, [r7, #4] + 8005004: 681b ldr r3, [r3, #0] + 8005006: f003 0380 and.w r3, r3, #128 @ 0x80 + 800500a: 2b00 cmp r3, #0 + 800500c: d008 beq.n 8005020 { /* Check the parameters */ assert_param(IS_RCC_ADC12PLLCLK_DIV(PeriphClkInit->Adc12ClockSelection)); /* Configure the ADC12 clock source */ __HAL_RCC_ADC12_CONFIG(PeriphClkInit->Adc12ClockSelection); - 8004fd6: 4b0e ldr r3, [pc, #56] @ (8005010 ) - 8004fd8: 6adb ldr r3, [r3, #44] @ 0x2c - 8004fda: f423 72f8 bic.w r2, r3, #496 @ 0x1f0 - 8004fde: 687b ldr r3, [r7, #4] - 8004fe0: 6a5b ldr r3, [r3, #36] @ 0x24 - 8004fe2: 490b ldr r1, [pc, #44] @ (8005010 ) - 8004fe4: 4313 orrs r3, r2 - 8004fe6: 62cb str r3, [r1, #44] @ 0x2c + 800500e: 4b0e ldr r3, [pc, #56] @ (8005048 ) + 8005010: 6adb ldr r3, [r3, #44] @ 0x2c + 8005012: f423 72f8 bic.w r2, r3, #496 @ 0x1f0 + 8005016: 687b ldr r3, [r7, #4] + 8005018: 6a5b ldr r3, [r3, #36] @ 0x24 + 800501a: 490b ldr r1, [pc, #44] @ (8005048 ) + 800501c: 4313 orrs r3, r2 + 800501e: 62cb str r3, [r1, #44] @ 0x2c || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\ || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\ || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) /*------------------------------ TIM1 clock Configuration ----------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1) - 8004fe8: 687b ldr r3, [r7, #4] - 8004fea: 681b ldr r3, [r3, #0] - 8004fec: f403 5380 and.w r3, r3, #4096 @ 0x1000 - 8004ff0: 2b00 cmp r3, #0 - 8004ff2: d008 beq.n 8005006 + 8005020: 687b ldr r3, [r7, #4] + 8005022: 681b ldr r3, [r3, #0] + 8005024: f403 5380 and.w r3, r3, #4096 @ 0x1000 + 8005028: 2b00 cmp r3, #0 + 800502a: d008 beq.n 800503e { /* Check the parameters */ assert_param(IS_RCC_TIM1CLKSOURCE(PeriphClkInit->Tim1ClockSelection)); /* Configure the TIM1 clock source */ __HAL_RCC_TIM1_CONFIG(PeriphClkInit->Tim1ClockSelection); - 8004ff4: 4b06 ldr r3, [pc, #24] @ (8005010 ) - 8004ff6: 6b1b ldr r3, [r3, #48] @ 0x30 - 8004ff8: f423 7280 bic.w r2, r3, #256 @ 0x100 - 8004ffc: 687b ldr r3, [r7, #4] - 8004ffe: 6adb ldr r3, [r3, #44] @ 0x2c - 8005000: 4903 ldr r1, [pc, #12] @ (8005010 ) - 8005002: 4313 orrs r3, r2 - 8005004: 630b str r3, [r1, #48] @ 0x30 + 800502c: 4b06 ldr r3, [pc, #24] @ (8005048 ) + 800502e: 6b1b ldr r3, [r3, #48] @ 0x30 + 8005030: f423 7280 bic.w r2, r3, #256 @ 0x100 + 8005034: 687b ldr r3, [r7, #4] + 8005036: 6adb ldr r3, [r3, #44] @ 0x2c + 8005038: 4903 ldr r1, [pc, #12] @ (8005048 ) + 800503a: 4313 orrs r3, r2 + 800503c: 630b str r3, [r1, #48] @ 0x30 __HAL_RCC_TIM20_CONFIG(PeriphClkInit->Tim20ClockSelection); } #endif /* STM32F303xE || STM32F398xx */ return HAL_OK; - 8005006: 2300 movs r3, #0 + 800503e: 2300 movs r3, #0 } - 8005008: 4618 mov r0, r3 - 800500a: 3748 adds r7, #72 @ 0x48 - 800500c: 46bd mov sp, r7 - 800500e: bd80 pop {r7, pc} - 8005010: 40021000 .word 0x40021000 + 8005040: 4618 mov r0, r3 + 8005042: 3748 adds r7, #72 @ 0x48 + 8005044: 46bd mov sp, r7 + 8005046: bd80 pop {r7, pc} + 8005048: 40021000 .word 0x40021000 -08005014 : +0800504c : * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { - 8005014: b580 push {r7, lr} - 8005016: b082 sub sp, #8 - 8005018: af00 add r7, sp, #0 - 800501a: 6078 str r0, [r7, #4] + 800504c: b580 push {r7, lr} + 800504e: b082 sub sp, #8 + 8005050: af00 add r7, sp, #0 + 8005052: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) - 800501c: 687b ldr r3, [r7, #4] - 800501e: 2b00 cmp r3, #0 - 8005020: d101 bne.n 8005026 + 8005054: 687b ldr r3, [r7, #4] + 8005056: 2b00 cmp r3, #0 + 8005058: d101 bne.n 800505e { return HAL_ERROR; - 8005022: 2301 movs r3, #1 - 8005024: e049 b.n 80050ba + 800505a: 2301 movs r3, #1 + 800505c: e049 b.n 80050f2 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) - 8005026: 687b ldr r3, [r7, #4] - 8005028: f893 303d ldrb.w r3, [r3, #61] @ 0x3d - 800502c: b2db uxtb r3, r3 - 800502e: 2b00 cmp r3, #0 - 8005030: d106 bne.n 8005040 + 800505e: 687b ldr r3, [r7, #4] + 8005060: f893 303d ldrb.w r3, [r3, #61] @ 0x3d + 8005064: b2db uxtb r3, r3 + 8005066: 2b00 cmp r3, #0 + 8005068: d106 bne.n 8005078 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; - 8005032: 687b ldr r3, [r7, #4] - 8005034: 2200 movs r2, #0 - 8005036: f883 203c strb.w r2, [r3, #60] @ 0x3c + 800506a: 687b ldr r3, [r7, #4] + 800506c: 2200 movs r2, #0 + 800506e: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Base_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspInit(htim); - 800503a: 6878 ldr r0, [r7, #4] - 800503c: f7fc f86c bl 8001118 + 8005072: 6878 ldr r0, [r7, #4] + 8005074: f7fc f86c bl 8001150 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; - 8005040: 687b ldr r3, [r7, #4] - 8005042: 2202 movs r2, #2 - 8005044: f883 203d strb.w r2, [r3, #61] @ 0x3d + 8005078: 687b ldr r3, [r7, #4] + 800507a: 2202 movs r2, #2 + 800507c: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); - 8005048: 687b ldr r3, [r7, #4] - 800504a: 681a ldr r2, [r3, #0] - 800504c: 687b ldr r3, [r7, #4] - 800504e: 3304 adds r3, #4 - 8005050: 4619 mov r1, r3 - 8005052: 4610 mov r0, r2 - 8005054: f000 f986 bl 8005364 + 8005080: 687b ldr r3, [r7, #4] + 8005082: 681a ldr r2, [r3, #0] + 8005084: 687b ldr r3, [r7, #4] + 8005086: 3304 adds r3, #4 + 8005088: 4619 mov r1, r3 + 800508a: 4610 mov r0, r2 + 800508c: f000 f986 bl 800539c /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; - 8005058: 687b ldr r3, [r7, #4] - 800505a: 2201 movs r2, #1 - 800505c: f883 2048 strb.w r2, [r3, #72] @ 0x48 + 8005090: 687b ldr r3, [r7, #4] + 8005092: 2201 movs r2, #1 + 8005094: f883 2048 strb.w r2, [r3, #72] @ 0x48 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); - 8005060: 687b ldr r3, [r7, #4] - 8005062: 2201 movs r2, #1 - 8005064: f883 203e strb.w r2, [r3, #62] @ 0x3e - 8005068: 687b ldr r3, [r7, #4] - 800506a: 2201 movs r2, #1 - 800506c: f883 203f strb.w r2, [r3, #63] @ 0x3f - 8005070: 687b ldr r3, [r7, #4] - 8005072: 2201 movs r2, #1 - 8005074: f883 2040 strb.w r2, [r3, #64] @ 0x40 - 8005078: 687b ldr r3, [r7, #4] - 800507a: 2201 movs r2, #1 - 800507c: f883 2041 strb.w r2, [r3, #65] @ 0x41 - 8005080: 687b ldr r3, [r7, #4] - 8005082: 2201 movs r2, #1 - 8005084: f883 2042 strb.w r2, [r3, #66] @ 0x42 - 8005088: 687b ldr r3, [r7, #4] - 800508a: 2201 movs r2, #1 - 800508c: f883 2043 strb.w r2, [r3, #67] @ 0x43 - TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); - 8005090: 687b ldr r3, [r7, #4] - 8005092: 2201 movs r2, #1 - 8005094: f883 2044 strb.w r2, [r3, #68] @ 0x44 8005098: 687b ldr r3, [r7, #4] 800509a: 2201 movs r2, #1 - 800509c: f883 2045 strb.w r2, [r3, #69] @ 0x45 + 800509c: f883 203e strb.w r2, [r3, #62] @ 0x3e 80050a0: 687b ldr r3, [r7, #4] 80050a2: 2201 movs r2, #1 - 80050a4: f883 2046 strb.w r2, [r3, #70] @ 0x46 + 80050a4: f883 203f strb.w r2, [r3, #63] @ 0x3f 80050a8: 687b ldr r3, [r7, #4] 80050aa: 2201 movs r2, #1 - 80050ac: f883 2047 strb.w r2, [r3, #71] @ 0x47 + 80050ac: f883 2040 strb.w r2, [r3, #64] @ 0x40 + 80050b0: 687b ldr r3, [r7, #4] + 80050b2: 2201 movs r2, #1 + 80050b4: f883 2041 strb.w r2, [r3, #65] @ 0x41 + 80050b8: 687b ldr r3, [r7, #4] + 80050ba: 2201 movs r2, #1 + 80050bc: f883 2042 strb.w r2, [r3, #66] @ 0x42 + 80050c0: 687b ldr r3, [r7, #4] + 80050c2: 2201 movs r2, #1 + 80050c4: f883 2043 strb.w r2, [r3, #67] @ 0x43 + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + 80050c8: 687b ldr r3, [r7, #4] + 80050ca: 2201 movs r2, #1 + 80050cc: f883 2044 strb.w r2, [r3, #68] @ 0x44 + 80050d0: 687b ldr r3, [r7, #4] + 80050d2: 2201 movs r2, #1 + 80050d4: f883 2045 strb.w r2, [r3, #69] @ 0x45 + 80050d8: 687b ldr r3, [r7, #4] + 80050da: 2201 movs r2, #1 + 80050dc: f883 2046 strb.w r2, [r3, #70] @ 0x46 + 80050e0: 687b ldr r3, [r7, #4] + 80050e2: 2201 movs r2, #1 + 80050e4: f883 2047 strb.w r2, [r3, #71] @ 0x47 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; - 80050b0: 687b ldr r3, [r7, #4] - 80050b2: 2201 movs r2, #1 - 80050b4: f883 203d strb.w r2, [r3, #61] @ 0x3d + 80050e8: 687b ldr r3, [r7, #4] + 80050ea: 2201 movs r2, #1 + 80050ec: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; - 80050b8: 2300 movs r3, #0 + 80050f0: 2300 movs r3, #0 } - 80050ba: 4618 mov r0, r3 - 80050bc: 3708 adds r7, #8 - 80050be: 46bd mov sp, r7 - 80050c0: bd80 pop {r7, pc} + 80050f2: 4618 mov r0, r3 + 80050f4: 3708 adds r7, #8 + 80050f6: 46bd mov sp, r7 + 80050f8: bd80 pop {r7, pc} -080050c2 : +080050fa : * @brief This function handles TIM interrupts requests. * @param htim TIM handle * @retval None */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { - 80050c2: b580 push {r7, lr} - 80050c4: b082 sub sp, #8 - 80050c6: af00 add r7, sp, #0 - 80050c8: 6078 str r0, [r7, #4] + 80050fa: b580 push {r7, lr} + 80050fc: b082 sub sp, #8 + 80050fe: af00 add r7, sp, #0 + 8005100: 6078 str r0, [r7, #4] /* Capture compare 1 event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) - 80050ca: 687b ldr r3, [r7, #4] - 80050cc: 681b ldr r3, [r3, #0] - 80050ce: 691b ldr r3, [r3, #16] - 80050d0: f003 0302 and.w r3, r3, #2 - 80050d4: 2b02 cmp r3, #2 - 80050d6: d122 bne.n 800511e + 8005102: 687b ldr r3, [r7, #4] + 8005104: 681b ldr r3, [r3, #0] + 8005106: 691b ldr r3, [r3, #16] + 8005108: f003 0302 and.w r3, r3, #2 + 800510c: 2b02 cmp r3, #2 + 800510e: d122 bne.n 8005156 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET) - 80050d8: 687b ldr r3, [r7, #4] - 80050da: 681b ldr r3, [r3, #0] - 80050dc: 68db ldr r3, [r3, #12] - 80050de: f003 0302 and.w r3, r3, #2 - 80050e2: 2b02 cmp r3, #2 - 80050e4: d11b bne.n 800511e + 8005110: 687b ldr r3, [r7, #4] + 8005112: 681b ldr r3, [r3, #0] + 8005114: 68db ldr r3, [r3, #12] + 8005116: f003 0302 and.w r3, r3, #2 + 800511a: 2b02 cmp r3, #2 + 800511c: d11b bne.n 8005156 { { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); - 80050e6: 687b ldr r3, [r7, #4] - 80050e8: 681b ldr r3, [r3, #0] - 80050ea: f06f 0202 mvn.w r2, #2 - 80050ee: 611a str r2, [r3, #16] + 800511e: 687b ldr r3, [r7, #4] + 8005120: 681b ldr r3, [r3, #0] + 8005122: f06f 0202 mvn.w r2, #2 + 8005126: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - 80050f0: 687b ldr r3, [r7, #4] - 80050f2: 2201 movs r2, #1 - 80050f4: 771a strb r2, [r3, #28] + 8005128: 687b ldr r3, [r7, #4] + 800512a: 2201 movs r2, #1 + 800512c: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) - 80050f6: 687b ldr r3, [r7, #4] - 80050f8: 681b ldr r3, [r3, #0] - 80050fa: 699b ldr r3, [r3, #24] - 80050fc: f003 0303 and.w r3, r3, #3 - 8005100: 2b00 cmp r3, #0 - 8005102: d003 beq.n 800510c + 800512e: 687b ldr r3, [r7, #4] + 8005130: 681b ldr r3, [r3, #0] + 8005132: 699b ldr r3, [r3, #24] + 8005134: f003 0303 and.w r3, r3, #3 + 8005138: 2b00 cmp r3, #0 + 800513a: d003 beq.n 8005144 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); - 8005104: 6878 ldr r0, [r7, #4] - 8005106: f000 f90f bl 8005328 - 800510a: e005 b.n 8005118 + 800513c: 6878 ldr r0, [r7, #4] + 800513e: f000 f90f bl 8005360 + 8005142: e005 b.n 8005150 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); - 800510c: 6878 ldr r0, [r7, #4] - 800510e: f000 f901 bl 8005314 + 8005144: 6878 ldr r0, [r7, #4] + 8005146: f000 f901 bl 800534c HAL_TIM_PWM_PulseFinishedCallback(htim); - 8005112: 6878 ldr r0, [r7, #4] - 8005114: f000 f912 bl 800533c + 800514a: 6878 ldr r0, [r7, #4] + 800514c: f000 f912 bl 8005374 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - 8005118: 687b ldr r3, [r7, #4] - 800511a: 2200 movs r2, #0 - 800511c: 771a strb r2, [r3, #28] + 8005150: 687b ldr r3, [r7, #4] + 8005152: 2200 movs r2, #0 + 8005154: 771a strb r2, [r3, #28] } } } /* Capture compare 2 event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) - 800511e: 687b ldr r3, [r7, #4] - 8005120: 681b ldr r3, [r3, #0] - 8005122: 691b ldr r3, [r3, #16] - 8005124: f003 0304 and.w r3, r3, #4 - 8005128: 2b04 cmp r3, #4 - 800512a: d122 bne.n 8005172 + 8005156: 687b ldr r3, [r7, #4] + 8005158: 681b ldr r3, [r3, #0] + 800515a: 691b ldr r3, [r3, #16] + 800515c: f003 0304 and.w r3, r3, #4 + 8005160: 2b04 cmp r3, #4 + 8005162: d122 bne.n 80051aa { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET) - 800512c: 687b ldr r3, [r7, #4] - 800512e: 681b ldr r3, [r3, #0] - 8005130: 68db ldr r3, [r3, #12] - 8005132: f003 0304 and.w r3, r3, #4 - 8005136: 2b04 cmp r3, #4 - 8005138: d11b bne.n 8005172 + 8005164: 687b ldr r3, [r7, #4] + 8005166: 681b ldr r3, [r3, #0] + 8005168: 68db ldr r3, [r3, #12] + 800516a: f003 0304 and.w r3, r3, #4 + 800516e: 2b04 cmp r3, #4 + 8005170: d11b bne.n 80051aa { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); - 800513a: 687b ldr r3, [r7, #4] - 800513c: 681b ldr r3, [r3, #0] - 800513e: f06f 0204 mvn.w r2, #4 - 8005142: 611a str r2, [r3, #16] + 8005172: 687b ldr r3, [r7, #4] + 8005174: 681b ldr r3, [r3, #0] + 8005176: f06f 0204 mvn.w r2, #4 + 800517a: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - 8005144: 687b ldr r3, [r7, #4] - 8005146: 2202 movs r2, #2 - 8005148: 771a strb r2, [r3, #28] + 800517c: 687b ldr r3, [r7, #4] + 800517e: 2202 movs r2, #2 + 8005180: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) - 800514a: 687b ldr r3, [r7, #4] - 800514c: 681b ldr r3, [r3, #0] - 800514e: 699b ldr r3, [r3, #24] - 8005150: f403 7340 and.w r3, r3, #768 @ 0x300 - 8005154: 2b00 cmp r3, #0 - 8005156: d003 beq.n 8005160 + 8005182: 687b ldr r3, [r7, #4] + 8005184: 681b ldr r3, [r3, #0] + 8005186: 699b ldr r3, [r3, #24] + 8005188: f403 7340 and.w r3, r3, #768 @ 0x300 + 800518c: 2b00 cmp r3, #0 + 800518e: d003 beq.n 8005198 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); - 8005158: 6878 ldr r0, [r7, #4] - 800515a: f000 f8e5 bl 8005328 - 800515e: e005 b.n 800516c + 8005190: 6878 ldr r0, [r7, #4] + 8005192: f000 f8e5 bl 8005360 + 8005196: e005 b.n 80051a4 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); - 8005160: 6878 ldr r0, [r7, #4] - 8005162: f000 f8d7 bl 8005314 + 8005198: 6878 ldr r0, [r7, #4] + 800519a: f000 f8d7 bl 800534c HAL_TIM_PWM_PulseFinishedCallback(htim); - 8005166: 6878 ldr r0, [r7, #4] - 8005168: f000 f8e8 bl 800533c + 800519e: 6878 ldr r0, [r7, #4] + 80051a0: f000 f8e8 bl 8005374 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - 800516c: 687b ldr r3, [r7, #4] - 800516e: 2200 movs r2, #0 - 8005170: 771a strb r2, [r3, #28] + 80051a4: 687b ldr r3, [r7, #4] + 80051a6: 2200 movs r2, #0 + 80051a8: 771a strb r2, [r3, #28] } } /* Capture compare 3 event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) - 8005172: 687b ldr r3, [r7, #4] - 8005174: 681b ldr r3, [r3, #0] - 8005176: 691b ldr r3, [r3, #16] - 8005178: f003 0308 and.w r3, r3, #8 - 800517c: 2b08 cmp r3, #8 - 800517e: d122 bne.n 80051c6 + 80051aa: 687b ldr r3, [r7, #4] + 80051ac: 681b ldr r3, [r3, #0] + 80051ae: 691b ldr r3, [r3, #16] + 80051b0: f003 0308 and.w r3, r3, #8 + 80051b4: 2b08 cmp r3, #8 + 80051b6: d122 bne.n 80051fe { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET) - 8005180: 687b ldr r3, [r7, #4] - 8005182: 681b ldr r3, [r3, #0] - 8005184: 68db ldr r3, [r3, #12] - 8005186: f003 0308 and.w r3, r3, #8 - 800518a: 2b08 cmp r3, #8 - 800518c: d11b bne.n 80051c6 + 80051b8: 687b ldr r3, [r7, #4] + 80051ba: 681b ldr r3, [r3, #0] + 80051bc: 68db ldr r3, [r3, #12] + 80051be: f003 0308 and.w r3, r3, #8 + 80051c2: 2b08 cmp r3, #8 + 80051c4: d11b bne.n 80051fe { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); - 800518e: 687b ldr r3, [r7, #4] - 8005190: 681b ldr r3, [r3, #0] - 8005192: f06f 0208 mvn.w r2, #8 - 8005196: 611a str r2, [r3, #16] + 80051c6: 687b ldr r3, [r7, #4] + 80051c8: 681b ldr r3, [r3, #0] + 80051ca: f06f 0208 mvn.w r2, #8 + 80051ce: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - 8005198: 687b ldr r3, [r7, #4] - 800519a: 2204 movs r2, #4 - 800519c: 771a strb r2, [r3, #28] + 80051d0: 687b ldr r3, [r7, #4] + 80051d2: 2204 movs r2, #4 + 80051d4: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) - 800519e: 687b ldr r3, [r7, #4] - 80051a0: 681b ldr r3, [r3, #0] - 80051a2: 69db ldr r3, [r3, #28] - 80051a4: f003 0303 and.w r3, r3, #3 - 80051a8: 2b00 cmp r3, #0 - 80051aa: d003 beq.n 80051b4 + 80051d6: 687b ldr r3, [r7, #4] + 80051d8: 681b ldr r3, [r3, #0] + 80051da: 69db ldr r3, [r3, #28] + 80051dc: f003 0303 and.w r3, r3, #3 + 80051e0: 2b00 cmp r3, #0 + 80051e2: d003 beq.n 80051ec { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); - 80051ac: 6878 ldr r0, [r7, #4] - 80051ae: f000 f8bb bl 8005328 - 80051b2: e005 b.n 80051c0 + 80051e4: 6878 ldr r0, [r7, #4] + 80051e6: f000 f8bb bl 8005360 + 80051ea: e005 b.n 80051f8 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); - 80051b4: 6878 ldr r0, [r7, #4] - 80051b6: f000 f8ad bl 8005314 + 80051ec: 6878 ldr r0, [r7, #4] + 80051ee: f000 f8ad bl 800534c HAL_TIM_PWM_PulseFinishedCallback(htim); - 80051ba: 6878 ldr r0, [r7, #4] - 80051bc: f000 f8be bl 800533c + 80051f2: 6878 ldr r0, [r7, #4] + 80051f4: f000 f8be bl 8005374 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - 80051c0: 687b ldr r3, [r7, #4] - 80051c2: 2200 movs r2, #0 - 80051c4: 771a strb r2, [r3, #28] + 80051f8: 687b ldr r3, [r7, #4] + 80051fa: 2200 movs r2, #0 + 80051fc: 771a strb r2, [r3, #28] } } /* Capture compare 4 event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) - 80051c6: 687b ldr r3, [r7, #4] - 80051c8: 681b ldr r3, [r3, #0] - 80051ca: 691b ldr r3, [r3, #16] - 80051cc: f003 0310 and.w r3, r3, #16 - 80051d0: 2b10 cmp r3, #16 - 80051d2: d122 bne.n 800521a + 80051fe: 687b ldr r3, [r7, #4] + 8005200: 681b ldr r3, [r3, #0] + 8005202: 691b ldr r3, [r3, #16] + 8005204: f003 0310 and.w r3, r3, #16 + 8005208: 2b10 cmp r3, #16 + 800520a: d122 bne.n 8005252 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET) - 80051d4: 687b ldr r3, [r7, #4] - 80051d6: 681b ldr r3, [r3, #0] - 80051d8: 68db ldr r3, [r3, #12] - 80051da: f003 0310 and.w r3, r3, #16 - 80051de: 2b10 cmp r3, #16 - 80051e0: d11b bne.n 800521a + 800520c: 687b ldr r3, [r7, #4] + 800520e: 681b ldr r3, [r3, #0] + 8005210: 68db ldr r3, [r3, #12] + 8005212: f003 0310 and.w r3, r3, #16 + 8005216: 2b10 cmp r3, #16 + 8005218: d11b bne.n 8005252 { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); - 80051e2: 687b ldr r3, [r7, #4] - 80051e4: 681b ldr r3, [r3, #0] - 80051e6: f06f 0210 mvn.w r2, #16 - 80051ea: 611a str r2, [r3, #16] + 800521a: 687b ldr r3, [r7, #4] + 800521c: 681b ldr r3, [r3, #0] + 800521e: f06f 0210 mvn.w r2, #16 + 8005222: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - 80051ec: 687b ldr r3, [r7, #4] - 80051ee: 2208 movs r2, #8 - 80051f0: 771a strb r2, [r3, #28] + 8005224: 687b ldr r3, [r7, #4] + 8005226: 2208 movs r2, #8 + 8005228: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) - 80051f2: 687b ldr r3, [r7, #4] - 80051f4: 681b ldr r3, [r3, #0] - 80051f6: 69db ldr r3, [r3, #28] - 80051f8: f403 7340 and.w r3, r3, #768 @ 0x300 - 80051fc: 2b00 cmp r3, #0 - 80051fe: d003 beq.n 8005208 + 800522a: 687b ldr r3, [r7, #4] + 800522c: 681b ldr r3, [r3, #0] + 800522e: 69db ldr r3, [r3, #28] + 8005230: f403 7340 and.w r3, r3, #768 @ 0x300 + 8005234: 2b00 cmp r3, #0 + 8005236: d003 beq.n 8005240 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); - 8005200: 6878 ldr r0, [r7, #4] - 8005202: f000 f891 bl 8005328 - 8005206: e005 b.n 8005214 + 8005238: 6878 ldr r0, [r7, #4] + 800523a: f000 f891 bl 8005360 + 800523e: e005 b.n 800524c { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); - 8005208: 6878 ldr r0, [r7, #4] - 800520a: f000 f883 bl 8005314 + 8005240: 6878 ldr r0, [r7, #4] + 8005242: f000 f883 bl 800534c HAL_TIM_PWM_PulseFinishedCallback(htim); - 800520e: 6878 ldr r0, [r7, #4] - 8005210: f000 f894 bl 800533c + 8005246: 6878 ldr r0, [r7, #4] + 8005248: f000 f894 bl 8005374 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - 8005214: 687b ldr r3, [r7, #4] - 8005216: 2200 movs r2, #0 - 8005218: 771a strb r2, [r3, #28] + 800524c: 687b ldr r3, [r7, #4] + 800524e: 2200 movs r2, #0 + 8005250: 771a strb r2, [r3, #28] } } /* TIM Update event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) - 800521a: 687b ldr r3, [r7, #4] - 800521c: 681b ldr r3, [r3, #0] - 800521e: 691b ldr r3, [r3, #16] - 8005220: f003 0301 and.w r3, r3, #1 - 8005224: 2b01 cmp r3, #1 - 8005226: d10e bne.n 8005246 + 8005252: 687b ldr r3, [r7, #4] + 8005254: 681b ldr r3, [r3, #0] + 8005256: 691b ldr r3, [r3, #16] + 8005258: f003 0301 and.w r3, r3, #1 + 800525c: 2b01 cmp r3, #1 + 800525e: d10e bne.n 800527e { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET) - 8005228: 687b ldr r3, [r7, #4] - 800522a: 681b ldr r3, [r3, #0] - 800522c: 68db ldr r3, [r3, #12] - 800522e: f003 0301 and.w r3, r3, #1 - 8005232: 2b01 cmp r3, #1 - 8005234: d107 bne.n 8005246 + 8005260: 687b ldr r3, [r7, #4] + 8005262: 681b ldr r3, [r3, #0] + 8005264: 68db ldr r3, [r3, #12] + 8005266: f003 0301 and.w r3, r3, #1 + 800526a: 2b01 cmp r3, #1 + 800526c: d107 bne.n 800527e { __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); - 8005236: 687b ldr r3, [r7, #4] - 8005238: 681b ldr r3, [r3, #0] - 800523a: f06f 0201 mvn.w r2, #1 - 800523e: 611a str r2, [r3, #16] + 800526e: 687b ldr r3, [r7, #4] + 8005270: 681b ldr r3, [r3, #0] + 8005272: f06f 0201 mvn.w r2, #1 + 8005276: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else HAL_TIM_PeriodElapsedCallback(htim); - 8005240: 6878 ldr r0, [r7, #4] - 8005242: f000 f85d bl 8005300 + 8005278: 6878 ldr r0, [r7, #4] + 800527a: f000 f85d bl 8005338 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break input event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET) - 8005246: 687b ldr r3, [r7, #4] - 8005248: 681b ldr r3, [r3, #0] - 800524a: 691b ldr r3, [r3, #16] - 800524c: f003 0380 and.w r3, r3, #128 @ 0x80 - 8005250: 2b80 cmp r3, #128 @ 0x80 - 8005252: d10e bne.n 8005272 + 800527e: 687b ldr r3, [r7, #4] + 8005280: 681b ldr r3, [r3, #0] + 8005282: 691b ldr r3, [r3, #16] + 8005284: f003 0380 and.w r3, r3, #128 @ 0x80 + 8005288: 2b80 cmp r3, #128 @ 0x80 + 800528a: d10e bne.n 80052aa { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) - 8005254: 687b ldr r3, [r7, #4] - 8005256: 681b ldr r3, [r3, #0] - 8005258: 68db ldr r3, [r3, #12] - 800525a: f003 0380 and.w r3, r3, #128 @ 0x80 - 800525e: 2b80 cmp r3, #128 @ 0x80 - 8005260: d107 bne.n 8005272 + 800528c: 687b ldr r3, [r7, #4] + 800528e: 681b ldr r3, [r3, #0] + 8005290: 68db ldr r3, [r3, #12] + 8005292: f003 0380 and.w r3, r3, #128 @ 0x80 + 8005296: 2b80 cmp r3, #128 @ 0x80 + 8005298: d107 bne.n 80052aa { __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); - 8005262: 687b ldr r3, [r7, #4] - 8005264: 681b ldr r3, [r3, #0] - 8005266: f06f 0280 mvn.w r2, #128 @ 0x80 - 800526a: 611a str r2, [r3, #16] + 800529a: 687b ldr r3, [r7, #4] + 800529c: 681b ldr r3, [r3, #0] + 800529e: f06f 0280 mvn.w r2, #128 @ 0x80 + 80052a2: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->BreakCallback(htim); #else HAL_TIMEx_BreakCallback(htim); - 800526c: 6878 ldr r0, [r7, #4] - 800526e: f000 f979 bl 8005564 + 80052a4: 6878 ldr r0, [r7, #4] + 80052a6: f000 f979 bl 800559c #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } #if defined(TIM_BDTR_BK2E) /* TIM Break2 input event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET) - 8005272: 687b ldr r3, [r7, #4] - 8005274: 681b ldr r3, [r3, #0] - 8005276: 691b ldr r3, [r3, #16] - 8005278: f403 7380 and.w r3, r3, #256 @ 0x100 - 800527c: f5b3 7f80 cmp.w r3, #256 @ 0x100 - 8005280: d10e bne.n 80052a0 + 80052aa: 687b ldr r3, [r7, #4] + 80052ac: 681b ldr r3, [r3, #0] + 80052ae: 691b ldr r3, [r3, #16] + 80052b0: f403 7380 and.w r3, r3, #256 @ 0x100 + 80052b4: f5b3 7f80 cmp.w r3, #256 @ 0x100 + 80052b8: d10e bne.n 80052d8 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) - 8005282: 687b ldr r3, [r7, #4] - 8005284: 681b ldr r3, [r3, #0] - 8005286: 68db ldr r3, [r3, #12] - 8005288: f003 0380 and.w r3, r3, #128 @ 0x80 - 800528c: 2b80 cmp r3, #128 @ 0x80 - 800528e: d107 bne.n 80052a0 + 80052ba: 687b ldr r3, [r7, #4] + 80052bc: 681b ldr r3, [r3, #0] + 80052be: 68db ldr r3, [r3, #12] + 80052c0: f003 0380 and.w r3, r3, #128 @ 0x80 + 80052c4: 2b80 cmp r3, #128 @ 0x80 + 80052c6: d107 bne.n 80052d8 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2); - 8005290: 687b ldr r3, [r7, #4] - 8005292: 681b ldr r3, [r3, #0] - 8005294: f46f 7280 mvn.w r2, #256 @ 0x100 - 8005298: 611a str r2, [r3, #16] + 80052c8: 687b ldr r3, [r7, #4] + 80052ca: 681b ldr r3, [r3, #0] + 80052cc: f46f 7280 mvn.w r2, #256 @ 0x100 + 80052d0: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->Break2Callback(htim); #else HAL_TIMEx_Break2Callback(htim); - 800529a: 6878 ldr r0, [r7, #4] - 800529c: f000 f96c bl 8005578 + 80052d2: 6878 ldr r0, [r7, #4] + 80052d4: f000 f96c bl 80055b0 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } #endif /* TIM_BDTR_BK2E */ /* TIM Trigger detection event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) - 80052a0: 687b ldr r3, [r7, #4] - 80052a2: 681b ldr r3, [r3, #0] - 80052a4: 691b ldr r3, [r3, #16] - 80052a6: f003 0340 and.w r3, r3, #64 @ 0x40 - 80052aa: 2b40 cmp r3, #64 @ 0x40 - 80052ac: d10e bne.n 80052cc + 80052d8: 687b ldr r3, [r7, #4] + 80052da: 681b ldr r3, [r3, #0] + 80052dc: 691b ldr r3, [r3, #16] + 80052de: f003 0340 and.w r3, r3, #64 @ 0x40 + 80052e2: 2b40 cmp r3, #64 @ 0x40 + 80052e4: d10e bne.n 8005304 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET) - 80052ae: 687b ldr r3, [r7, #4] - 80052b0: 681b ldr r3, [r3, #0] - 80052b2: 68db ldr r3, [r3, #12] - 80052b4: f003 0340 and.w r3, r3, #64 @ 0x40 - 80052b8: 2b40 cmp r3, #64 @ 0x40 - 80052ba: d107 bne.n 80052cc + 80052e6: 687b ldr r3, [r7, #4] + 80052e8: 681b ldr r3, [r3, #0] + 80052ea: 68db ldr r3, [r3, #12] + 80052ec: f003 0340 and.w r3, r3, #64 @ 0x40 + 80052f0: 2b40 cmp r3, #64 @ 0x40 + 80052f2: d107 bne.n 8005304 { __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); - 80052bc: 687b ldr r3, [r7, #4] - 80052be: 681b ldr r3, [r3, #0] - 80052c0: f06f 0240 mvn.w r2, #64 @ 0x40 - 80052c4: 611a str r2, [r3, #16] + 80052f4: 687b ldr r3, [r7, #4] + 80052f6: 681b ldr r3, [r3, #0] + 80052f8: f06f 0240 mvn.w r2, #64 @ 0x40 + 80052fc: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else HAL_TIM_TriggerCallback(htim); - 80052c6: 6878 ldr r0, [r7, #4] - 80052c8: f000 f842 bl 8005350 + 80052fe: 6878 ldr r0, [r7, #4] + 8005300: f000 f842 bl 8005388 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM commutation event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET) - 80052cc: 687b ldr r3, [r7, #4] - 80052ce: 681b ldr r3, [r3, #0] - 80052d0: 691b ldr r3, [r3, #16] - 80052d2: f003 0320 and.w r3, r3, #32 - 80052d6: 2b20 cmp r3, #32 - 80052d8: d10e bne.n 80052f8 + 8005304: 687b ldr r3, [r7, #4] + 8005306: 681b ldr r3, [r3, #0] + 8005308: 691b ldr r3, [r3, #16] + 800530a: f003 0320 and.w r3, r3, #32 + 800530e: 2b20 cmp r3, #32 + 8005310: d10e bne.n 8005330 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET) - 80052da: 687b ldr r3, [r7, #4] - 80052dc: 681b ldr r3, [r3, #0] - 80052de: 68db ldr r3, [r3, #12] - 80052e0: f003 0320 and.w r3, r3, #32 - 80052e4: 2b20 cmp r3, #32 - 80052e6: d107 bne.n 80052f8 + 8005312: 687b ldr r3, [r7, #4] + 8005314: 681b ldr r3, [r3, #0] + 8005316: 68db ldr r3, [r3, #12] + 8005318: f003 0320 and.w r3, r3, #32 + 800531c: 2b20 cmp r3, #32 + 800531e: d107 bne.n 8005330 { __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); - 80052e8: 687b ldr r3, [r7, #4] - 80052ea: 681b ldr r3, [r3, #0] - 80052ec: f06f 0220 mvn.w r2, #32 - 80052f0: 611a str r2, [r3, #16] + 8005320: 687b ldr r3, [r7, #4] + 8005322: 681b ldr r3, [r3, #0] + 8005324: f06f 0220 mvn.w r2, #32 + 8005328: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationCallback(htim); #else HAL_TIMEx_CommutCallback(htim); - 80052f2: 6878 ldr r0, [r7, #4] - 80052f4: f000 f92c bl 8005550 + 800532a: 6878 ldr r0, [r7, #4] + 800532c: f000 f92c bl 8005588 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } } - 80052f8: bf00 nop - 80052fa: 3708 adds r7, #8 - 80052fc: 46bd mov sp, r7 - 80052fe: bd80 pop {r7, pc} + 8005330: bf00 nop + 8005332: 3708 adds r7, #8 + 8005334: 46bd mov sp, r7 + 8005336: bd80 pop {r7, pc} -08005300 : +08005338 : * @brief Period elapsed callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { - 8005300: b480 push {r7} - 8005302: b083 sub sp, #12 - 8005304: af00 add r7, sp, #0 - 8005306: 6078 str r0, [r7, #4] + 8005338: b480 push {r7} + 800533a: b083 sub sp, #12 + 800533c: af00 add r7, sp, #0 + 800533e: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PeriodElapsedCallback could be implemented in the user file */ } - 8005308: bf00 nop - 800530a: 370c adds r7, #12 - 800530c: 46bd mov sp, r7 - 800530e: f85d 7b04 ldr.w r7, [sp], #4 - 8005312: 4770 bx lr + 8005340: bf00 nop + 8005342: 370c adds r7, #12 + 8005344: 46bd mov sp, r7 + 8005346: f85d 7b04 ldr.w r7, [sp], #4 + 800534a: 4770 bx lr -08005314 : +0800534c : * @brief Output Compare callback in non-blocking mode * @param htim TIM OC handle * @retval None */ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) { - 8005314: b480 push {r7} - 8005316: b083 sub sp, #12 - 8005318: af00 add r7, sp, #0 - 800531a: 6078 str r0, [r7, #4] + 800534c: b480 push {r7} + 800534e: b083 sub sp, #12 + 8005350: af00 add r7, sp, #0 + 8005352: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file */ } - 800531c: bf00 nop - 800531e: 370c adds r7, #12 - 8005320: 46bd mov sp, r7 - 8005322: f85d 7b04 ldr.w r7, [sp], #4 - 8005326: 4770 bx lr + 8005354: bf00 nop + 8005356: 370c adds r7, #12 + 8005358: 46bd mov sp, r7 + 800535a: f85d 7b04 ldr.w r7, [sp], #4 + 800535e: 4770 bx lr -08005328 : +08005360 : * @brief Input Capture callback in non-blocking mode * @param htim TIM IC handle * @retval None */ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) { - 8005328: b480 push {r7} - 800532a: b083 sub sp, #12 - 800532c: af00 add r7, sp, #0 - 800532e: 6078 str r0, [r7, #4] + 8005360: b480 push {r7} + 8005362: b083 sub sp, #12 + 8005364: af00 add r7, sp, #0 + 8005366: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_CaptureCallback could be implemented in the user file */ } - 8005330: bf00 nop - 8005332: 370c adds r7, #12 - 8005334: 46bd mov sp, r7 - 8005336: f85d 7b04 ldr.w r7, [sp], #4 - 800533a: 4770 bx lr + 8005368: bf00 nop + 800536a: 370c adds r7, #12 + 800536c: 46bd mov sp, r7 + 800536e: f85d 7b04 ldr.w r7, [sp], #4 + 8005372: 4770 bx lr -0800533c : +08005374 : * @brief PWM Pulse finished callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) { - 800533c: b480 push {r7} - 800533e: b083 sub sp, #12 - 8005340: af00 add r7, sp, #0 - 8005342: 6078 str r0, [r7, #4] + 8005374: b480 push {r7} + 8005376: b083 sub sp, #12 + 8005378: af00 add r7, sp, #0 + 800537a: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file */ } - 8005344: bf00 nop - 8005346: 370c adds r7, #12 - 8005348: 46bd mov sp, r7 - 800534a: f85d 7b04 ldr.w r7, [sp], #4 - 800534e: 4770 bx lr + 800537c: bf00 nop + 800537e: 370c adds r7, #12 + 8005380: 46bd mov sp, r7 + 8005382: f85d 7b04 ldr.w r7, [sp], #4 + 8005386: 4770 bx lr -08005350 : +08005388 : * @brief Hall Trigger detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) { - 8005350: b480 push {r7} - 8005352: b083 sub sp, #12 - 8005354: af00 add r7, sp, #0 - 8005356: 6078 str r0, [r7, #4] + 8005388: b480 push {r7} + 800538a: b083 sub sp, #12 + 800538c: af00 add r7, sp, #0 + 800538e: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_TriggerCallback could be implemented in the user file */ } - 8005358: bf00 nop - 800535a: 370c adds r7, #12 - 800535c: 46bd mov sp, r7 - 800535e: f85d 7b04 ldr.w r7, [sp], #4 - 8005362: 4770 bx lr + 8005390: bf00 nop + 8005392: 370c adds r7, #12 + 8005394: 46bd mov sp, r7 + 8005396: f85d 7b04 ldr.w r7, [sp], #4 + 800539a: 4770 bx lr -08005364 : +0800539c : * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) { - 8005364: b480 push {r7} - 8005366: b085 sub sp, #20 - 8005368: af00 add r7, sp, #0 - 800536a: 6078 str r0, [r7, #4] - 800536c: 6039 str r1, [r7, #0] + 800539c: b480 push {r7} + 800539e: b085 sub sp, #20 + 80053a0: af00 add r7, sp, #0 + 80053a2: 6078 str r0, [r7, #4] + 80053a4: 6039 str r1, [r7, #0] uint32_t tmpcr1; tmpcr1 = TIMx->CR1; - 800536e: 687b ldr r3, [r7, #4] - 8005370: 681b ldr r3, [r3, #0] - 8005372: 60fb str r3, [r7, #12] + 80053a6: 687b ldr r3, [r7, #4] + 80053a8: 681b ldr r3, [r3, #0] + 80053aa: 60fb str r3, [r7, #12] /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) - 8005374: 687b ldr r3, [r7, #4] - 8005376: 4a36 ldr r2, [pc, #216] @ (8005450 ) - 8005378: 4293 cmp r3, r2 - 800537a: d00b beq.n 8005394 - 800537c: 687b ldr r3, [r7, #4] - 800537e: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 - 8005382: d007 beq.n 8005394 - 8005384: 687b ldr r3, [r7, #4] - 8005386: 4a33 ldr r2, [pc, #204] @ (8005454 ) - 8005388: 4293 cmp r3, r2 - 800538a: d003 beq.n 8005394 - 800538c: 687b ldr r3, [r7, #4] - 800538e: 4a32 ldr r2, [pc, #200] @ (8005458 ) - 8005390: 4293 cmp r3, r2 - 8005392: d108 bne.n 80053a6 + 80053ac: 687b ldr r3, [r7, #4] + 80053ae: 4a36 ldr r2, [pc, #216] @ (8005488 ) + 80053b0: 4293 cmp r3, r2 + 80053b2: d00b beq.n 80053cc + 80053b4: 687b ldr r3, [r7, #4] + 80053b6: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 80053ba: d007 beq.n 80053cc + 80053bc: 687b ldr r3, [r7, #4] + 80053be: 4a33 ldr r2, [pc, #204] @ (800548c ) + 80053c0: 4293 cmp r3, r2 + 80053c2: d003 beq.n 80053cc + 80053c4: 687b ldr r3, [r7, #4] + 80053c6: 4a32 ldr r2, [pc, #200] @ (8005490 ) + 80053c8: 4293 cmp r3, r2 + 80053ca: d108 bne.n 80053de { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); - 8005394: 68fb ldr r3, [r7, #12] - 8005396: f023 0370 bic.w r3, r3, #112 @ 0x70 - 800539a: 60fb str r3, [r7, #12] + 80053cc: 68fb ldr r3, [r7, #12] + 80053ce: f023 0370 bic.w r3, r3, #112 @ 0x70 + 80053d2: 60fb str r3, [r7, #12] tmpcr1 |= Structure->CounterMode; - 800539c: 683b ldr r3, [r7, #0] - 800539e: 685b ldr r3, [r3, #4] - 80053a0: 68fa ldr r2, [r7, #12] - 80053a2: 4313 orrs r3, r2 - 80053a4: 60fb str r3, [r7, #12] + 80053d4: 683b ldr r3, [r7, #0] + 80053d6: 685b ldr r3, [r3, #4] + 80053d8: 68fa ldr r2, [r7, #12] + 80053da: 4313 orrs r3, r2 + 80053dc: 60fb str r3, [r7, #12] } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) - 80053a6: 687b ldr r3, [r7, #4] - 80053a8: 4a29 ldr r2, [pc, #164] @ (8005450 ) - 80053aa: 4293 cmp r3, r2 - 80053ac: d017 beq.n 80053de - 80053ae: 687b ldr r3, [r7, #4] - 80053b0: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 - 80053b4: d013 beq.n 80053de - 80053b6: 687b ldr r3, [r7, #4] - 80053b8: 4a26 ldr r2, [pc, #152] @ (8005454 ) - 80053ba: 4293 cmp r3, r2 - 80053bc: d00f beq.n 80053de - 80053be: 687b ldr r3, [r7, #4] - 80053c0: 4a25 ldr r2, [pc, #148] @ (8005458 ) - 80053c2: 4293 cmp r3, r2 - 80053c4: d00b beq.n 80053de - 80053c6: 687b ldr r3, [r7, #4] - 80053c8: 4a24 ldr r2, [pc, #144] @ (800545c ) - 80053ca: 4293 cmp r3, r2 - 80053cc: d007 beq.n 80053de - 80053ce: 687b ldr r3, [r7, #4] - 80053d0: 4a23 ldr r2, [pc, #140] @ (8005460 ) - 80053d2: 4293 cmp r3, r2 - 80053d4: d003 beq.n 80053de - 80053d6: 687b ldr r3, [r7, #4] - 80053d8: 4a22 ldr r2, [pc, #136] @ (8005464 ) - 80053da: 4293 cmp r3, r2 - 80053dc: d108 bne.n 80053f0 + 80053de: 687b ldr r3, [r7, #4] + 80053e0: 4a29 ldr r2, [pc, #164] @ (8005488 ) + 80053e2: 4293 cmp r3, r2 + 80053e4: d017 beq.n 8005416 + 80053e6: 687b ldr r3, [r7, #4] + 80053e8: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 80053ec: d013 beq.n 8005416 + 80053ee: 687b ldr r3, [r7, #4] + 80053f0: 4a26 ldr r2, [pc, #152] @ (800548c ) + 80053f2: 4293 cmp r3, r2 + 80053f4: d00f beq.n 8005416 + 80053f6: 687b ldr r3, [r7, #4] + 80053f8: 4a25 ldr r2, [pc, #148] @ (8005490 ) + 80053fa: 4293 cmp r3, r2 + 80053fc: d00b beq.n 8005416 + 80053fe: 687b ldr r3, [r7, #4] + 8005400: 4a24 ldr r2, [pc, #144] @ (8005494 ) + 8005402: 4293 cmp r3, r2 + 8005404: d007 beq.n 8005416 + 8005406: 687b ldr r3, [r7, #4] + 8005408: 4a23 ldr r2, [pc, #140] @ (8005498 ) + 800540a: 4293 cmp r3, r2 + 800540c: d003 beq.n 8005416 + 800540e: 687b ldr r3, [r7, #4] + 8005410: 4a22 ldr r2, [pc, #136] @ (800549c ) + 8005412: 4293 cmp r3, r2 + 8005414: d108 bne.n 8005428 { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; - 80053de: 68fb ldr r3, [r7, #12] - 80053e0: f423 7340 bic.w r3, r3, #768 @ 0x300 - 80053e4: 60fb str r3, [r7, #12] + 8005416: 68fb ldr r3, [r7, #12] + 8005418: f423 7340 bic.w r3, r3, #768 @ 0x300 + 800541c: 60fb str r3, [r7, #12] tmpcr1 |= (uint32_t)Structure->ClockDivision; - 80053e6: 683b ldr r3, [r7, #0] - 80053e8: 68db ldr r3, [r3, #12] - 80053ea: 68fa ldr r2, [r7, #12] - 80053ec: 4313 orrs r3, r2 - 80053ee: 60fb str r3, [r7, #12] + 800541e: 683b ldr r3, [r7, #0] + 8005420: 68db ldr r3, [r3, #12] + 8005422: 68fa ldr r2, [r7, #12] + 8005424: 4313 orrs r3, r2 + 8005426: 60fb str r3, [r7, #12] } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); - 80053f0: 68fb ldr r3, [r7, #12] - 80053f2: f023 0280 bic.w r2, r3, #128 @ 0x80 - 80053f6: 683b ldr r3, [r7, #0] - 80053f8: 695b ldr r3, [r3, #20] - 80053fa: 4313 orrs r3, r2 - 80053fc: 60fb str r3, [r7, #12] + 8005428: 68fb ldr r3, [r7, #12] + 800542a: f023 0280 bic.w r2, r3, #128 @ 0x80 + 800542e: 683b ldr r3, [r7, #0] + 8005430: 695b ldr r3, [r3, #20] + 8005432: 4313 orrs r3, r2 + 8005434: 60fb str r3, [r7, #12] TIMx->CR1 = tmpcr1; - 80053fe: 687b ldr r3, [r7, #4] - 8005400: 68fa ldr r2, [r7, #12] - 8005402: 601a str r2, [r3, #0] + 8005436: 687b ldr r3, [r7, #4] + 8005438: 68fa ldr r2, [r7, #12] + 800543a: 601a str r2, [r3, #0] /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; - 8005404: 683b ldr r3, [r7, #0] - 8005406: 689a ldr r2, [r3, #8] - 8005408: 687b ldr r3, [r7, #4] - 800540a: 62da str r2, [r3, #44] @ 0x2c + 800543c: 683b ldr r3, [r7, #0] + 800543e: 689a ldr r2, [r3, #8] + 8005440: 687b ldr r3, [r7, #4] + 8005442: 62da str r2, [r3, #44] @ 0x2c /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; - 800540c: 683b ldr r3, [r7, #0] - 800540e: 681a ldr r2, [r3, #0] - 8005410: 687b ldr r3, [r7, #4] - 8005412: 629a str r2, [r3, #40] @ 0x28 + 8005444: 683b ldr r3, [r7, #0] + 8005446: 681a ldr r2, [r3, #0] + 8005448: 687b ldr r3, [r7, #4] + 800544a: 629a str r2, [r3, #40] @ 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) - 8005414: 687b ldr r3, [r7, #4] - 8005416: 4a0e ldr r2, [pc, #56] @ (8005450 ) - 8005418: 4293 cmp r3, r2 - 800541a: d00b beq.n 8005434 - 800541c: 687b ldr r3, [r7, #4] - 800541e: 4a0f ldr r2, [pc, #60] @ (800545c ) - 8005420: 4293 cmp r3, r2 - 8005422: d007 beq.n 8005434 - 8005424: 687b ldr r3, [r7, #4] - 8005426: 4a0e ldr r2, [pc, #56] @ (8005460 ) - 8005428: 4293 cmp r3, r2 - 800542a: d003 beq.n 8005434 - 800542c: 687b ldr r3, [r7, #4] - 800542e: 4a0d ldr r2, [pc, #52] @ (8005464 ) - 8005430: 4293 cmp r3, r2 - 8005432: d103 bne.n 800543c + 800544c: 687b ldr r3, [r7, #4] + 800544e: 4a0e ldr r2, [pc, #56] @ (8005488 ) + 8005450: 4293 cmp r3, r2 + 8005452: d00b beq.n 800546c + 8005454: 687b ldr r3, [r7, #4] + 8005456: 4a0f ldr r2, [pc, #60] @ (8005494 ) + 8005458: 4293 cmp r3, r2 + 800545a: d007 beq.n 800546c + 800545c: 687b ldr r3, [r7, #4] + 800545e: 4a0e ldr r2, [pc, #56] @ (8005498 ) + 8005460: 4293 cmp r3, r2 + 8005462: d003 beq.n 800546c + 8005464: 687b ldr r3, [r7, #4] + 8005466: 4a0d ldr r2, [pc, #52] @ (800549c ) + 8005468: 4293 cmp r3, r2 + 800546a: d103 bne.n 8005474 { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; - 8005434: 683b ldr r3, [r7, #0] - 8005436: 691a ldr r2, [r3, #16] - 8005438: 687b ldr r3, [r7, #4] - 800543a: 631a str r2, [r3, #48] @ 0x30 + 800546c: 683b ldr r3, [r7, #0] + 800546e: 691a ldr r2, [r3, #16] + 8005470: 687b ldr r3, [r7, #4] + 8005472: 631a str r2, [r3, #48] @ 0x30 } /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; - 800543c: 687b ldr r3, [r7, #4] - 800543e: 2201 movs r2, #1 - 8005440: 615a str r2, [r3, #20] + 8005474: 687b ldr r3, [r7, #4] + 8005476: 2201 movs r2, #1 + 8005478: 615a str r2, [r3, #20] } - 8005442: bf00 nop - 8005444: 3714 adds r7, #20 - 8005446: 46bd mov sp, r7 - 8005448: f85d 7b04 ldr.w r7, [sp], #4 - 800544c: 4770 bx lr - 800544e: bf00 nop - 8005450: 40012c00 .word 0x40012c00 - 8005454: 40000400 .word 0x40000400 - 8005458: 40000800 .word 0x40000800 - 800545c: 40014000 .word 0x40014000 - 8005460: 40014400 .word 0x40014400 - 8005464: 40014800 .word 0x40014800 + 800547a: bf00 nop + 800547c: 3714 adds r7, #20 + 800547e: 46bd mov sp, r7 + 8005480: f85d 7b04 ldr.w r7, [sp], #4 + 8005484: 4770 bx lr + 8005486: bf00 nop + 8005488: 40012c00 .word 0x40012c00 + 800548c: 40000400 .word 0x40000400 + 8005490: 40000800 .word 0x40000800 + 8005494: 40014000 .word 0x40014000 + 8005498: 40014400 .word 0x40014400 + 800549c: 40014800 .word 0x40014800 -08005468 : +080054a0 : * mode. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, const TIM_MasterConfigTypeDef *sMasterConfig) { - 8005468: b480 push {r7} - 800546a: b085 sub sp, #20 - 800546c: af00 add r7, sp, #0 - 800546e: 6078 str r0, [r7, #4] - 8005470: 6039 str r1, [r7, #0] + 80054a0: b480 push {r7} + 80054a2: b085 sub sp, #20 + 80054a4: af00 add r7, sp, #0 + 80054a6: 6078 str r0, [r7, #4] + 80054a8: 6039 str r1, [r7, #0] assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); /* Check input state */ __HAL_LOCK(htim); - 8005472: 687b ldr r3, [r7, #4] - 8005474: f893 303c ldrb.w r3, [r3, #60] @ 0x3c - 8005478: 2b01 cmp r3, #1 - 800547a: d101 bne.n 8005480 - 800547c: 2302 movs r3, #2 - 800547e: e059 b.n 8005534 - 8005480: 687b ldr r3, [r7, #4] - 8005482: 2201 movs r2, #1 - 8005484: f883 203c strb.w r2, [r3, #60] @ 0x3c + 80054aa: 687b ldr r3, [r7, #4] + 80054ac: f893 303c ldrb.w r3, [r3, #60] @ 0x3c + 80054b0: 2b01 cmp r3, #1 + 80054b2: d101 bne.n 80054b8 + 80054b4: 2302 movs r3, #2 + 80054b6: e059 b.n 800556c + 80054b8: 687b ldr r3, [r7, #4] + 80054ba: 2201 movs r2, #1 + 80054bc: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Change the handler state */ htim->State = HAL_TIM_STATE_BUSY; - 8005488: 687b ldr r3, [r7, #4] - 800548a: 2202 movs r2, #2 - 800548c: f883 203d strb.w r2, [r3, #61] @ 0x3d + 80054c0: 687b ldr r3, [r7, #4] + 80054c2: 2202 movs r2, #2 + 80054c4: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; - 8005490: 687b ldr r3, [r7, #4] - 8005492: 681b ldr r3, [r3, #0] - 8005494: 685b ldr r3, [r3, #4] - 8005496: 60fb str r3, [r7, #12] + 80054c8: 687b ldr r3, [r7, #4] + 80054ca: 681b ldr r3, [r3, #0] + 80054cc: 685b ldr r3, [r3, #4] + 80054ce: 60fb str r3, [r7, #12] /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; - 8005498: 687b ldr r3, [r7, #4] - 800549a: 681b ldr r3, [r3, #0] - 800549c: 689b ldr r3, [r3, #8] - 800549e: 60bb str r3, [r7, #8] + 80054d0: 687b ldr r3, [r7, #4] + 80054d2: 681b ldr r3, [r3, #0] + 80054d4: 689b ldr r3, [r3, #8] + 80054d6: 60bb str r3, [r7, #8] #if defined(TIM_CR2_MMS2) /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */ if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) - 80054a0: 687b ldr r3, [r7, #4] - 80054a2: 681b ldr r3, [r3, #0] - 80054a4: 4a26 ldr r2, [pc, #152] @ (8005540 ) - 80054a6: 4293 cmp r3, r2 - 80054a8: d108 bne.n 80054bc + 80054d8: 687b ldr r3, [r7, #4] + 80054da: 681b ldr r3, [r3, #0] + 80054dc: 4a26 ldr r2, [pc, #152] @ (8005578 ) + 80054de: 4293 cmp r3, r2 + 80054e0: d108 bne.n 80054f4 { /* Check the parameters */ assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2)); /* Clear the MMS2 bits */ tmpcr2 &= ~TIM_CR2_MMS2; - 80054aa: 68fb ldr r3, [r7, #12] - 80054ac: f423 0370 bic.w r3, r3, #15728640 @ 0xf00000 - 80054b0: 60fb str r3, [r7, #12] + 80054e2: 68fb ldr r3, [r7, #12] + 80054e4: f423 0370 bic.w r3, r3, #15728640 @ 0xf00000 + 80054e8: 60fb str r3, [r7, #12] /* Select the TRGO2 source*/ tmpcr2 |= sMasterConfig->MasterOutputTrigger2; - 80054b2: 683b ldr r3, [r7, #0] - 80054b4: 685b ldr r3, [r3, #4] - 80054b6: 68fa ldr r2, [r7, #12] - 80054b8: 4313 orrs r3, r2 - 80054ba: 60fb str r3, [r7, #12] + 80054ea: 683b ldr r3, [r7, #0] + 80054ec: 685b ldr r3, [r3, #4] + 80054ee: 68fa ldr r2, [r7, #12] + 80054f0: 4313 orrs r3, r2 + 80054f2: 60fb str r3, [r7, #12] } #endif /* TIM_CR2_MMS2 */ /* Reset the MMS Bits */ tmpcr2 &= ~TIM_CR2_MMS; - 80054bc: 68fb ldr r3, [r7, #12] - 80054be: f023 0370 bic.w r3, r3, #112 @ 0x70 - 80054c2: 60fb str r3, [r7, #12] + 80054f4: 68fb ldr r3, [r7, #12] + 80054f6: f023 0370 bic.w r3, r3, #112 @ 0x70 + 80054fa: 60fb str r3, [r7, #12] /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; - 80054c4: 683b ldr r3, [r7, #0] - 80054c6: 681b ldr r3, [r3, #0] - 80054c8: 68fa ldr r2, [r7, #12] - 80054ca: 4313 orrs r3, r2 - 80054cc: 60fb str r3, [r7, #12] + 80054fc: 683b ldr r3, [r7, #0] + 80054fe: 681b ldr r3, [r3, #0] + 8005500: 68fa ldr r2, [r7, #12] + 8005502: 4313 orrs r3, r2 + 8005504: 60fb str r3, [r7, #12] /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; - 80054ce: 687b ldr r3, [r7, #4] - 80054d0: 681b ldr r3, [r3, #0] - 80054d2: 68fa ldr r2, [r7, #12] - 80054d4: 605a str r2, [r3, #4] + 8005506: 687b ldr r3, [r7, #4] + 8005508: 681b ldr r3, [r3, #0] + 800550a: 68fa ldr r2, [r7, #12] + 800550c: 605a str r2, [r3, #4] if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - 80054d6: 687b ldr r3, [r7, #4] - 80054d8: 681b ldr r3, [r3, #0] - 80054da: 4a19 ldr r2, [pc, #100] @ (8005540 ) - 80054dc: 4293 cmp r3, r2 - 80054de: d013 beq.n 8005508 - 80054e0: 687b ldr r3, [r7, #4] - 80054e2: 681b ldr r3, [r3, #0] - 80054e4: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 - 80054e8: d00e beq.n 8005508 - 80054ea: 687b ldr r3, [r7, #4] - 80054ec: 681b ldr r3, [r3, #0] - 80054ee: 4a15 ldr r2, [pc, #84] @ (8005544 ) - 80054f0: 4293 cmp r3, r2 - 80054f2: d009 beq.n 8005508 - 80054f4: 687b ldr r3, [r7, #4] - 80054f6: 681b ldr r3, [r3, #0] - 80054f8: 4a13 ldr r2, [pc, #76] @ (8005548 ) - 80054fa: 4293 cmp r3, r2 - 80054fc: d004 beq.n 8005508 - 80054fe: 687b ldr r3, [r7, #4] - 8005500: 681b ldr r3, [r3, #0] - 8005502: 4a12 ldr r2, [pc, #72] @ (800554c ) - 8005504: 4293 cmp r3, r2 - 8005506: d10c bne.n 8005522 + 800550e: 687b ldr r3, [r7, #4] + 8005510: 681b ldr r3, [r3, #0] + 8005512: 4a19 ldr r2, [pc, #100] @ (8005578 ) + 8005514: 4293 cmp r3, r2 + 8005516: d013 beq.n 8005540 + 8005518: 687b ldr r3, [r7, #4] + 800551a: 681b ldr r3, [r3, #0] + 800551c: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 8005520: d00e beq.n 8005540 + 8005522: 687b ldr r3, [r7, #4] + 8005524: 681b ldr r3, [r3, #0] + 8005526: 4a15 ldr r2, [pc, #84] @ (800557c ) + 8005528: 4293 cmp r3, r2 + 800552a: d009 beq.n 8005540 + 800552c: 687b ldr r3, [r7, #4] + 800552e: 681b ldr r3, [r3, #0] + 8005530: 4a13 ldr r2, [pc, #76] @ (8005580 ) + 8005532: 4293 cmp r3, r2 + 8005534: d004 beq.n 8005540 + 8005536: 687b ldr r3, [r7, #4] + 8005538: 681b ldr r3, [r3, #0] + 800553a: 4a12 ldr r2, [pc, #72] @ (8005584 ) + 800553c: 4293 cmp r3, r2 + 800553e: d10c bne.n 800555a { /* Reset the MSM Bit */ tmpsmcr &= ~TIM_SMCR_MSM; - 8005508: 68bb ldr r3, [r7, #8] - 800550a: f023 0380 bic.w r3, r3, #128 @ 0x80 - 800550e: 60bb str r3, [r7, #8] + 8005540: 68bb ldr r3, [r7, #8] + 8005542: f023 0380 bic.w r3, r3, #128 @ 0x80 + 8005546: 60bb str r3, [r7, #8] /* Set master mode */ tmpsmcr |= sMasterConfig->MasterSlaveMode; - 8005510: 683b ldr r3, [r7, #0] - 8005512: 689b ldr r3, [r3, #8] - 8005514: 68ba ldr r2, [r7, #8] - 8005516: 4313 orrs r3, r2 - 8005518: 60bb str r3, [r7, #8] + 8005548: 683b ldr r3, [r7, #0] + 800554a: 689b ldr r3, [r3, #8] + 800554c: 68ba ldr r2, [r7, #8] + 800554e: 4313 orrs r3, r2 + 8005550: 60bb str r3, [r7, #8] /* Update TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; - 800551a: 687b ldr r3, [r7, #4] - 800551c: 681b ldr r3, [r3, #0] - 800551e: 68ba ldr r2, [r7, #8] - 8005520: 609a str r2, [r3, #8] + 8005552: 687b ldr r3, [r7, #4] + 8005554: 681b ldr r3, [r3, #0] + 8005556: 68ba ldr r2, [r7, #8] + 8005558: 609a str r2, [r3, #8] } /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; - 8005522: 687b ldr r3, [r7, #4] - 8005524: 2201 movs r2, #1 - 8005526: f883 203d strb.w r2, [r3, #61] @ 0x3d + 800555a: 687b ldr r3, [r7, #4] + 800555c: 2201 movs r2, #1 + 800555e: f883 203d strb.w r2, [r3, #61] @ 0x3d __HAL_UNLOCK(htim); - 800552a: 687b ldr r3, [r7, #4] - 800552c: 2200 movs r2, #0 - 800552e: f883 203c strb.w r2, [r3, #60] @ 0x3c + 8005562: 687b ldr r3, [r7, #4] + 8005564: 2200 movs r2, #0 + 8005566: f883 203c strb.w r2, [r3, #60] @ 0x3c return HAL_OK; - 8005532: 2300 movs r3, #0 + 800556a: 2300 movs r3, #0 } - 8005534: 4618 mov r0, r3 - 8005536: 3714 adds r7, #20 - 8005538: 46bd mov sp, r7 - 800553a: f85d 7b04 ldr.w r7, [sp], #4 - 800553e: 4770 bx lr - 8005540: 40012c00 .word 0x40012c00 - 8005544: 40000400 .word 0x40000400 - 8005548: 40000800 .word 0x40000800 - 800554c: 40014000 .word 0x40014000 + 800556c: 4618 mov r0, r3 + 800556e: 3714 adds r7, #20 + 8005570: 46bd mov sp, r7 + 8005572: f85d 7b04 ldr.w r7, [sp], #4 + 8005576: 4770 bx lr + 8005578: 40012c00 .word 0x40012c00 + 800557c: 40000400 .word 0x40000400 + 8005580: 40000800 .word 0x40000800 + 8005584: 40014000 .word 0x40014000 -08005550 : +08005588 : * @brief Hall commutation changed callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) { - 8005550: b480 push {r7} - 8005552: b083 sub sp, #12 - 8005554: af00 add r7, sp, #0 - 8005556: 6078 str r0, [r7, #4] + 8005588: b480 push {r7} + 800558a: b083 sub sp, #12 + 800558c: af00 add r7, sp, #0 + 800558e: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_CommutCallback could be implemented in the user file */ } - 8005558: bf00 nop - 800555a: 370c adds r7, #12 - 800555c: 46bd mov sp, r7 - 800555e: f85d 7b04 ldr.w r7, [sp], #4 - 8005562: 4770 bx lr + 8005590: bf00 nop + 8005592: 370c adds r7, #12 + 8005594: 46bd mov sp, r7 + 8005596: f85d 7b04 ldr.w r7, [sp], #4 + 800559a: 4770 bx lr -08005564 : +0800559c : * @brief Hall Break detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) { - 8005564: b480 push {r7} - 8005566: b083 sub sp, #12 - 8005568: af00 add r7, sp, #0 - 800556a: 6078 str r0, [r7, #4] + 800559c: b480 push {r7} + 800559e: b083 sub sp, #12 + 80055a0: af00 add r7, sp, #0 + 80055a2: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_BreakCallback could be implemented in the user file */ } - 800556c: bf00 nop - 800556e: 370c adds r7, #12 - 8005570: 46bd mov sp, r7 - 8005572: f85d 7b04 ldr.w r7, [sp], #4 - 8005576: 4770 bx lr + 80055a4: bf00 nop + 80055a6: 370c adds r7, #12 + 80055a8: 46bd mov sp, r7 + 80055aa: f85d 7b04 ldr.w r7, [sp], #4 + 80055ae: 4770 bx lr -08005578 : +080055b0 : * @brief Hall Break2 detection callback in non blocking mode * @param htim: TIM handle * @retval None */ __weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim) { - 8005578: b480 push {r7} - 800557a: b083 sub sp, #12 - 800557c: af00 add r7, sp, #0 - 800557e: 6078 str r0, [r7, #4] + 80055b0: b480 push {r7} + 80055b2: b083 sub sp, #12 + 80055b4: af00 add r7, sp, #0 + 80055b6: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_TIMEx_Break2Callback could be implemented in the user file */ } - 8005580: bf00 nop - 8005582: 370c adds r7, #12 - 8005584: 46bd mov sp, r7 - 8005586: f85d 7b04 ldr.w r7, [sp], #4 - 800558a: 4770 bx lr + 80055b8: bf00 nop + 80055ba: 370c adds r7, #12 + 80055bc: 46bd mov sp, r7 + 80055be: f85d 7b04 ldr.w r7, [sp], #4 + 80055c2: 4770 bx lr -0800558c : +080055c4 : * parameters in the UART_InitTypeDef and initialize the associated handle. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { - 800558c: b580 push {r7, lr} - 800558e: b082 sub sp, #8 - 8005590: af00 add r7, sp, #0 - 8005592: 6078 str r0, [r7, #4] + 80055c4: b580 push {r7, lr} + 80055c6: b082 sub sp, #8 + 80055c8: af00 add r7, sp, #0 + 80055ca: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) - 8005594: 687b ldr r3, [r7, #4] - 8005596: 2b00 cmp r3, #0 - 8005598: d101 bne.n 800559e + 80055cc: 687b ldr r3, [r7, #4] + 80055ce: 2b00 cmp r3, #0 + 80055d0: d101 bne.n 80055d6 { return HAL_ERROR; - 800559a: 2301 movs r3, #1 - 800559c: e040 b.n 8005620 + 80055d2: 2301 movs r3, #1 + 80055d4: e040 b.n 8005658 { /* Check the parameters */ assert_param(IS_UART_INSTANCE(huart->Instance)); } if (huart->gState == HAL_UART_STATE_RESET) - 800559e: 687b ldr r3, [r7, #4] - 80055a0: 6fdb ldr r3, [r3, #124] @ 0x7c - 80055a2: 2b00 cmp r3, #0 - 80055a4: d106 bne.n 80055b4 + 80055d6: 687b ldr r3, [r7, #4] + 80055d8: 6fdb ldr r3, [r3, #124] @ 0x7c + 80055da: 2b00 cmp r3, #0 + 80055dc: d106 bne.n 80055ec { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; - 80055a6: 687b ldr r3, [r7, #4] - 80055a8: 2200 movs r2, #0 - 80055aa: f883 2078 strb.w r2, [r3, #120] @ 0x78 + 80055de: 687b ldr r3, [r7, #4] + 80055e0: 2200 movs r2, #0 + 80055e2: f883 2078 strb.w r2, [r3, #120] @ 0x78 /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); - 80055ae: 6878 ldr r0, [r7, #4] - 80055b0: f7fb fdd8 bl 8001164 + 80055e6: 6878 ldr r0, [r7, #4] + 80055e8: f7fb fdd8 bl 800119c #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; - 80055b4: 687b ldr r3, [r7, #4] - 80055b6: 2224 movs r2, #36 @ 0x24 - 80055b8: 67da str r2, [r3, #124] @ 0x7c + 80055ec: 687b ldr r3, [r7, #4] + 80055ee: 2224 movs r2, #36 @ 0x24 + 80055f0: 67da str r2, [r3, #124] @ 0x7c __HAL_UART_DISABLE(huart); - 80055ba: 687b ldr r3, [r7, #4] - 80055bc: 681b ldr r3, [r3, #0] - 80055be: 681a ldr r2, [r3, #0] - 80055c0: 687b ldr r3, [r7, #4] - 80055c2: 681b ldr r3, [r3, #0] - 80055c4: f022 0201 bic.w r2, r2, #1 - 80055c8: 601a str r2, [r3, #0] + 80055f2: 687b ldr r3, [r7, #4] + 80055f4: 681b ldr r3, [r3, #0] + 80055f6: 681a ldr r2, [r3, #0] + 80055f8: 687b ldr r3, [r7, #4] + 80055fa: 681b ldr r3, [r3, #0] + 80055fc: f022 0201 bic.w r2, r2, #1 + 8005600: 601a str r2, [r3, #0] /* Set the UART Communication parameters */ if (UART_SetConfig(huart) == HAL_ERROR) - 80055ca: 6878 ldr r0, [r7, #4] - 80055cc: f000 f82c bl 8005628 - 80055d0: 4603 mov r3, r0 - 80055d2: 2b01 cmp r3, #1 - 80055d4: d101 bne.n 80055da + 8005602: 6878 ldr r0, [r7, #4] + 8005604: f000 f82c bl 8005660 + 8005608: 4603 mov r3, r0 + 800560a: 2b01 cmp r3, #1 + 800560c: d101 bne.n 8005612 { return HAL_ERROR; - 80055d6: 2301 movs r3, #1 - 80055d8: e022 b.n 8005620 + 800560e: 2301 movs r3, #1 + 8005610: e022 b.n 8005658 } if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) - 80055da: 687b ldr r3, [r7, #4] - 80055dc: 6a5b ldr r3, [r3, #36] @ 0x24 - 80055de: 2b00 cmp r3, #0 - 80055e0: d002 beq.n 80055e8 + 8005612: 687b ldr r3, [r7, #4] + 8005614: 6a5b ldr r3, [r3, #36] @ 0x24 + 8005616: 2b00 cmp r3, #0 + 8005618: d002 beq.n 8005620 { UART_AdvFeatureConfig(huart); - 80055e2: 6878 ldr r0, [r7, #4] - 80055e4: f000 f9f4 bl 80059d0 + 800561a: 6878 ldr r0, [r7, #4] + 800561c: f000 f9f4 bl 8005a08 } /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); - 80055e8: 687b ldr r3, [r7, #4] - 80055ea: 681b ldr r3, [r3, #0] - 80055ec: 685a ldr r2, [r3, #4] - 80055ee: 687b ldr r3, [r7, #4] - 80055f0: 681b ldr r3, [r3, #0] - 80055f2: f422 4290 bic.w r2, r2, #18432 @ 0x4800 - 80055f6: 605a str r2, [r3, #4] + 8005620: 687b ldr r3, [r7, #4] + 8005622: 681b ldr r3, [r3, #0] + 8005624: 685a ldr r2, [r3, #4] + 8005626: 687b ldr r3, [r7, #4] + 8005628: 681b ldr r3, [r3, #0] + 800562a: f422 4290 bic.w r2, r2, #18432 @ 0x4800 + 800562e: 605a str r2, [r3, #4] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); - 80055f8: 687b ldr r3, [r7, #4] - 80055fa: 681b ldr r3, [r3, #0] - 80055fc: 689a ldr r2, [r3, #8] - 80055fe: 687b ldr r3, [r7, #4] - 8005600: 681b ldr r3, [r3, #0] - 8005602: f022 022a bic.w r2, r2, #42 @ 0x2a - 8005606: 609a str r2, [r3, #8] + 8005630: 687b ldr r3, [r7, #4] + 8005632: 681b ldr r3, [r3, #0] + 8005634: 689a ldr r2, [r3, #8] + 8005636: 687b ldr r3, [r7, #4] + 8005638: 681b ldr r3, [r3, #0] + 800563a: f022 022a bic.w r2, r2, #42 @ 0x2a + 800563e: 609a str r2, [r3, #8] __HAL_UART_ENABLE(huart); - 8005608: 687b ldr r3, [r7, #4] - 800560a: 681b ldr r3, [r3, #0] - 800560c: 681a ldr r2, [r3, #0] - 800560e: 687b ldr r3, [r7, #4] - 8005610: 681b ldr r3, [r3, #0] - 8005612: f042 0201 orr.w r2, r2, #1 - 8005616: 601a str r2, [r3, #0] + 8005640: 687b ldr r3, [r7, #4] + 8005642: 681b ldr r3, [r3, #0] + 8005644: 681a ldr r2, [r3, #0] + 8005646: 687b ldr r3, [r7, #4] + 8005648: 681b ldr r3, [r3, #0] + 800564a: f042 0201 orr.w r2, r2, #1 + 800564e: 601a str r2, [r3, #0] /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); - 8005618: 6878 ldr r0, [r7, #4] - 800561a: f000 fa7b bl 8005b14 - 800561e: 4603 mov r3, r0 + 8005650: 6878 ldr r0, [r7, #4] + 8005652: f000 fa7b bl 8005b4c + 8005656: 4603 mov r3, r0 } - 8005620: 4618 mov r0, r3 - 8005622: 3708 adds r7, #8 - 8005624: 46bd mov sp, r7 - 8005626: bd80 pop {r7, pc} + 8005658: 4618 mov r0, r3 + 800565a: 3708 adds r7, #8 + 800565c: 46bd mov sp, r7 + 800565e: bd80 pop {r7, pc} -08005628 : +08005660 : * @brief Configure the UART peripheral. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) { - 8005628: b580 push {r7, lr} - 800562a: b088 sub sp, #32 - 800562c: af00 add r7, sp, #0 - 800562e: 6078 str r0, [r7, #4] + 8005660: b580 push {r7, lr} + 8005662: b088 sub sp, #32 + 8005664: af00 add r7, sp, #0 + 8005666: 6078 str r0, [r7, #4] uint32_t tmpreg; uint16_t brrtemp; UART_ClockSourceTypeDef clocksource; uint32_t usartdiv; HAL_StatusTypeDef ret = HAL_OK; - 8005630: 2300 movs r3, #0 - 8005632: 77bb strb r3, [r7, #30] + 8005668: 2300 movs r3, #0 + 800566a: 77bb strb r3, [r7, #30] * the UART Word Length, Parity, Mode and oversampling: * set the M bits according to huart->Init.WordLength value * set PCE and PS bits according to huart->Init.Parity value * set TE and RE bits according to huart->Init.Mode value * set OVER8 bit according to huart->Init.OverSampling value */ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; - 8005634: 687b ldr r3, [r7, #4] - 8005636: 689a ldr r2, [r3, #8] - 8005638: 687b ldr r3, [r7, #4] - 800563a: 691b ldr r3, [r3, #16] - 800563c: 431a orrs r2, r3 - 800563e: 687b ldr r3, [r7, #4] - 8005640: 695b ldr r3, [r3, #20] - 8005642: 431a orrs r2, r3 - 8005644: 687b ldr r3, [r7, #4] - 8005646: 69db ldr r3, [r3, #28] - 8005648: 4313 orrs r3, r2 - 800564a: 617b str r3, [r7, #20] + 800566c: 687b ldr r3, [r7, #4] + 800566e: 689a ldr r2, [r3, #8] + 8005670: 687b ldr r3, [r7, #4] + 8005672: 691b ldr r3, [r3, #16] + 8005674: 431a orrs r2, r3 + 8005676: 687b ldr r3, [r7, #4] + 8005678: 695b ldr r3, [r3, #20] + 800567a: 431a orrs r2, r3 + 800567c: 687b ldr r3, [r7, #4] + 800567e: 69db ldr r3, [r3, #28] + 8005680: 4313 orrs r3, r2 + 8005682: 617b str r3, [r7, #20] MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); - 800564c: 687b ldr r3, [r7, #4] - 800564e: 681b ldr r3, [r3, #0] - 8005650: 681b ldr r3, [r3, #0] - 8005652: f423 4316 bic.w r3, r3, #38400 @ 0x9600 - 8005656: f023 030c bic.w r3, r3, #12 - 800565a: 687a ldr r2, [r7, #4] - 800565c: 6812 ldr r2, [r2, #0] - 800565e: 6979 ldr r1, [r7, #20] - 8005660: 430b orrs r3, r1 - 8005662: 6013 str r3, [r2, #0] + 8005684: 687b ldr r3, [r7, #4] + 8005686: 681b ldr r3, [r3, #0] + 8005688: 681b ldr r3, [r3, #0] + 800568a: f423 4316 bic.w r3, r3, #38400 @ 0x9600 + 800568e: f023 030c bic.w r3, r3, #12 + 8005692: 687a ldr r2, [r7, #4] + 8005694: 6812 ldr r2, [r2, #0] + 8005696: 6979 ldr r1, [r7, #20] + 8005698: 430b orrs r3, r1 + 800569a: 6013 str r3, [r2, #0] /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according * to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); - 8005664: 687b ldr r3, [r7, #4] - 8005666: 681b ldr r3, [r3, #0] - 8005668: 685b ldr r3, [r3, #4] - 800566a: f423 5140 bic.w r1, r3, #12288 @ 0x3000 - 800566e: 687b ldr r3, [r7, #4] - 8005670: 68da ldr r2, [r3, #12] - 8005672: 687b ldr r3, [r7, #4] - 8005674: 681b ldr r3, [r3, #0] - 8005676: 430a orrs r2, r1 - 8005678: 605a str r2, [r3, #4] + 800569c: 687b ldr r3, [r7, #4] + 800569e: 681b ldr r3, [r3, #0] + 80056a0: 685b ldr r3, [r3, #4] + 80056a2: f423 5140 bic.w r1, r3, #12288 @ 0x3000 + 80056a6: 687b ldr r3, [r7, #4] + 80056a8: 68da ldr r2, [r3, #12] + 80056aa: 687b ldr r3, [r7, #4] + 80056ac: 681b ldr r3, [r3, #0] + 80056ae: 430a orrs r2, r1 + 80056b0: 605a str r2, [r3, #4] /* Configure * - UART HardWare Flow Control: set CTSE and RTSE bits according * to huart->Init.HwFlowCtl value * - one-bit sampling method versus three samples' majority rule according * to huart->Init.OneBitSampling (not applicable to LPUART) */ tmpreg = (uint32_t)huart->Init.HwFlowCtl; - 800567a: 687b ldr r3, [r7, #4] - 800567c: 699b ldr r3, [r3, #24] - 800567e: 617b str r3, [r7, #20] + 80056b2: 687b ldr r3, [r7, #4] + 80056b4: 699b ldr r3, [r3, #24] + 80056b6: 617b str r3, [r7, #20] tmpreg |= huart->Init.OneBitSampling; - 8005680: 687b ldr r3, [r7, #4] - 8005682: 6a1b ldr r3, [r3, #32] - 8005684: 697a ldr r2, [r7, #20] - 8005686: 4313 orrs r3, r2 - 8005688: 617b str r3, [r7, #20] + 80056b8: 687b ldr r3, [r7, #4] + 80056ba: 6a1b ldr r3, [r3, #32] + 80056bc: 697a ldr r2, [r7, #20] + 80056be: 4313 orrs r3, r2 + 80056c0: 617b str r3, [r7, #20] MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); - 800568a: 687b ldr r3, [r7, #4] - 800568c: 681b ldr r3, [r3, #0] - 800568e: 689b ldr r3, [r3, #8] - 8005690: f423 6130 bic.w r1, r3, #2816 @ 0xb00 - 8005694: 687b ldr r3, [r7, #4] - 8005696: 681b ldr r3, [r3, #0] - 8005698: 697a ldr r2, [r7, #20] - 800569a: 430a orrs r2, r1 - 800569c: 609a str r2, [r3, #8] + 80056c2: 687b ldr r3, [r7, #4] + 80056c4: 681b ldr r3, [r3, #0] + 80056c6: 689b ldr r3, [r3, #8] + 80056c8: f423 6130 bic.w r1, r3, #2816 @ 0xb00 + 80056cc: 687b ldr r3, [r7, #4] + 80056ce: 681b ldr r3, [r3, #0] + 80056d0: 697a ldr r2, [r7, #20] + 80056d2: 430a orrs r2, r1 + 80056d4: 609a str r2, [r3, #8] /*-------------------------- USART BRR Configuration -----------------------*/ UART_GETCLOCKSOURCE(huart, clocksource); - 800569e: 687b ldr r3, [r7, #4] - 80056a0: 681b ldr r3, [r3, #0] - 80056a2: 4aa7 ldr r2, [pc, #668] @ (8005940 ) - 80056a4: 4293 cmp r3, r2 - 80056a6: d120 bne.n 80056ea - 80056a8: 4ba6 ldr r3, [pc, #664] @ (8005944 ) - 80056aa: 6b1b ldr r3, [r3, #48] @ 0x30 - 80056ac: f003 0303 and.w r3, r3, #3 - 80056b0: 2b03 cmp r3, #3 - 80056b2: d817 bhi.n 80056e4 - 80056b4: a201 add r2, pc, #4 @ (adr r2, 80056bc ) - 80056b6: f852 f023 ldr.w pc, [r2, r3, lsl #2] - 80056ba: bf00 nop - 80056bc: 080056cd .word 0x080056cd - 80056c0: 080056d9 .word 0x080056d9 - 80056c4: 080056df .word 0x080056df - 80056c8: 080056d3 .word 0x080056d3 - 80056cc: 2301 movs r3, #1 - 80056ce: 77fb strb r3, [r7, #31] - 80056d0: e0b5 b.n 800583e - 80056d2: 2302 movs r3, #2 - 80056d4: 77fb strb r3, [r7, #31] - 80056d6: e0b2 b.n 800583e - 80056d8: 2304 movs r3, #4 - 80056da: 77fb strb r3, [r7, #31] - 80056dc: e0af b.n 800583e - 80056de: 2308 movs r3, #8 - 80056e0: 77fb strb r3, [r7, #31] - 80056e2: e0ac b.n 800583e - 80056e4: 2310 movs r3, #16 - 80056e6: 77fb strb r3, [r7, #31] - 80056e8: e0a9 b.n 800583e - 80056ea: 687b ldr r3, [r7, #4] - 80056ec: 681b ldr r3, [r3, #0] - 80056ee: 4a96 ldr r2, [pc, #600] @ (8005948 ) - 80056f0: 4293 cmp r3, r2 - 80056f2: d124 bne.n 800573e - 80056f4: 4b93 ldr r3, [pc, #588] @ (8005944 ) - 80056f6: 6b1b ldr r3, [r3, #48] @ 0x30 - 80056f8: f403 3340 and.w r3, r3, #196608 @ 0x30000 - 80056fc: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 - 8005700: d011 beq.n 8005726 - 8005702: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 - 8005706: d817 bhi.n 8005738 - 8005708: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 - 800570c: d011 beq.n 8005732 - 800570e: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 - 8005712: d811 bhi.n 8005738 - 8005714: 2b00 cmp r3, #0 - 8005716: d003 beq.n 8005720 - 8005718: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 - 800571c: d006 beq.n 800572c - 800571e: e00b b.n 8005738 - 8005720: 2300 movs r3, #0 - 8005722: 77fb strb r3, [r7, #31] - 8005724: e08b b.n 800583e - 8005726: 2302 movs r3, #2 - 8005728: 77fb strb r3, [r7, #31] - 800572a: e088 b.n 800583e - 800572c: 2304 movs r3, #4 - 800572e: 77fb strb r3, [r7, #31] - 8005730: e085 b.n 800583e - 8005732: 2308 movs r3, #8 - 8005734: 77fb strb r3, [r7, #31] - 8005736: e082 b.n 800583e - 8005738: 2310 movs r3, #16 - 800573a: 77fb strb r3, [r7, #31] - 800573c: e07f b.n 800583e - 800573e: 687b ldr r3, [r7, #4] - 8005740: 681b ldr r3, [r3, #0] - 8005742: 4a82 ldr r2, [pc, #520] @ (800594c ) - 8005744: 4293 cmp r3, r2 - 8005746: d124 bne.n 8005792 - 8005748: 4b7e ldr r3, [pc, #504] @ (8005944 ) - 800574a: 6b1b ldr r3, [r3, #48] @ 0x30 - 800574c: f403 2340 and.w r3, r3, #786432 @ 0xc0000 - 8005750: f5b3 2f40 cmp.w r3, #786432 @ 0xc0000 - 8005754: d011 beq.n 800577a - 8005756: f5b3 2f40 cmp.w r3, #786432 @ 0xc0000 - 800575a: d817 bhi.n 800578c - 800575c: f5b3 2f00 cmp.w r3, #524288 @ 0x80000 - 8005760: d011 beq.n 8005786 - 8005762: f5b3 2f00 cmp.w r3, #524288 @ 0x80000 - 8005766: d811 bhi.n 800578c - 8005768: 2b00 cmp r3, #0 - 800576a: d003 beq.n 8005774 - 800576c: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 - 8005770: d006 beq.n 8005780 - 8005772: e00b b.n 800578c - 8005774: 2300 movs r3, #0 - 8005776: 77fb strb r3, [r7, #31] - 8005778: e061 b.n 800583e - 800577a: 2302 movs r3, #2 - 800577c: 77fb strb r3, [r7, #31] - 800577e: e05e b.n 800583e - 8005780: 2304 movs r3, #4 - 8005782: 77fb strb r3, [r7, #31] - 8005784: e05b b.n 800583e - 8005786: 2308 movs r3, #8 - 8005788: 77fb strb r3, [r7, #31] - 800578a: e058 b.n 800583e - 800578c: 2310 movs r3, #16 - 800578e: 77fb strb r3, [r7, #31] - 8005790: e055 b.n 800583e - 8005792: 687b ldr r3, [r7, #4] - 8005794: 681b ldr r3, [r3, #0] - 8005796: 4a6e ldr r2, [pc, #440] @ (8005950 ) - 8005798: 4293 cmp r3, r2 - 800579a: d124 bne.n 80057e6 - 800579c: 4b69 ldr r3, [pc, #420] @ (8005944 ) - 800579e: 6b1b ldr r3, [r3, #48] @ 0x30 - 80057a0: f403 1340 and.w r3, r3, #3145728 @ 0x300000 - 80057a4: f5b3 1f40 cmp.w r3, #3145728 @ 0x300000 - 80057a8: d011 beq.n 80057ce - 80057aa: f5b3 1f40 cmp.w r3, #3145728 @ 0x300000 - 80057ae: d817 bhi.n 80057e0 - 80057b0: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 - 80057b4: d011 beq.n 80057da - 80057b6: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 - 80057ba: d811 bhi.n 80057e0 - 80057bc: 2b00 cmp r3, #0 - 80057be: d003 beq.n 80057c8 - 80057c0: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 - 80057c4: d006 beq.n 80057d4 - 80057c6: e00b b.n 80057e0 - 80057c8: 2300 movs r3, #0 - 80057ca: 77fb strb r3, [r7, #31] - 80057cc: e037 b.n 800583e - 80057ce: 2302 movs r3, #2 - 80057d0: 77fb strb r3, [r7, #31] - 80057d2: e034 b.n 800583e - 80057d4: 2304 movs r3, #4 - 80057d6: 77fb strb r3, [r7, #31] - 80057d8: e031 b.n 800583e - 80057da: 2308 movs r3, #8 - 80057dc: 77fb strb r3, [r7, #31] - 80057de: e02e b.n 800583e - 80057e0: 2310 movs r3, #16 - 80057e2: 77fb strb r3, [r7, #31] - 80057e4: e02b b.n 800583e - 80057e6: 687b ldr r3, [r7, #4] - 80057e8: 681b ldr r3, [r3, #0] - 80057ea: 4a5a ldr r2, [pc, #360] @ (8005954 ) - 80057ec: 4293 cmp r3, r2 - 80057ee: d124 bne.n 800583a - 80057f0: 4b54 ldr r3, [pc, #336] @ (8005944 ) - 80057f2: 6b1b ldr r3, [r3, #48] @ 0x30 - 80057f4: f403 0340 and.w r3, r3, #12582912 @ 0xc00000 - 80057f8: f5b3 0f40 cmp.w r3, #12582912 @ 0xc00000 - 80057fc: d011 beq.n 8005822 - 80057fe: f5b3 0f40 cmp.w r3, #12582912 @ 0xc00000 - 8005802: d817 bhi.n 8005834 - 8005804: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 - 8005808: d011 beq.n 800582e - 800580a: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 - 800580e: d811 bhi.n 8005834 - 8005810: 2b00 cmp r3, #0 - 8005812: d003 beq.n 800581c - 8005814: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 - 8005818: d006 beq.n 8005828 - 800581a: e00b b.n 8005834 - 800581c: 2300 movs r3, #0 - 800581e: 77fb strb r3, [r7, #31] - 8005820: e00d b.n 800583e - 8005822: 2302 movs r3, #2 - 8005824: 77fb strb r3, [r7, #31] - 8005826: e00a b.n 800583e - 8005828: 2304 movs r3, #4 - 800582a: 77fb strb r3, [r7, #31] - 800582c: e007 b.n 800583e - 800582e: 2308 movs r3, #8 - 8005830: 77fb strb r3, [r7, #31] - 8005832: e004 b.n 800583e - 8005834: 2310 movs r3, #16 - 8005836: 77fb strb r3, [r7, #31] - 8005838: e001 b.n 800583e - 800583a: 2310 movs r3, #16 - 800583c: 77fb strb r3, [r7, #31] + 80056d6: 687b ldr r3, [r7, #4] + 80056d8: 681b ldr r3, [r3, #0] + 80056da: 4aa7 ldr r2, [pc, #668] @ (8005978 ) + 80056dc: 4293 cmp r3, r2 + 80056de: d120 bne.n 8005722 + 80056e0: 4ba6 ldr r3, [pc, #664] @ (800597c ) + 80056e2: 6b1b ldr r3, [r3, #48] @ 0x30 + 80056e4: f003 0303 and.w r3, r3, #3 + 80056e8: 2b03 cmp r3, #3 + 80056ea: d817 bhi.n 800571c + 80056ec: a201 add r2, pc, #4 @ (adr r2, 80056f4 ) + 80056ee: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 80056f2: bf00 nop + 80056f4: 08005705 .word 0x08005705 + 80056f8: 08005711 .word 0x08005711 + 80056fc: 08005717 .word 0x08005717 + 8005700: 0800570b .word 0x0800570b + 8005704: 2301 movs r3, #1 + 8005706: 77fb strb r3, [r7, #31] + 8005708: e0b5 b.n 8005876 + 800570a: 2302 movs r3, #2 + 800570c: 77fb strb r3, [r7, #31] + 800570e: e0b2 b.n 8005876 + 8005710: 2304 movs r3, #4 + 8005712: 77fb strb r3, [r7, #31] + 8005714: e0af b.n 8005876 + 8005716: 2308 movs r3, #8 + 8005718: 77fb strb r3, [r7, #31] + 800571a: e0ac b.n 8005876 + 800571c: 2310 movs r3, #16 + 800571e: 77fb strb r3, [r7, #31] + 8005720: e0a9 b.n 8005876 + 8005722: 687b ldr r3, [r7, #4] + 8005724: 681b ldr r3, [r3, #0] + 8005726: 4a96 ldr r2, [pc, #600] @ (8005980 ) + 8005728: 4293 cmp r3, r2 + 800572a: d124 bne.n 8005776 + 800572c: 4b93 ldr r3, [pc, #588] @ (800597c ) + 800572e: 6b1b ldr r3, [r3, #48] @ 0x30 + 8005730: f403 3340 and.w r3, r3, #196608 @ 0x30000 + 8005734: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 + 8005738: d011 beq.n 800575e + 800573a: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 + 800573e: d817 bhi.n 8005770 + 8005740: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 + 8005744: d011 beq.n 800576a + 8005746: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 + 800574a: d811 bhi.n 8005770 + 800574c: 2b00 cmp r3, #0 + 800574e: d003 beq.n 8005758 + 8005750: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 + 8005754: d006 beq.n 8005764 + 8005756: e00b b.n 8005770 + 8005758: 2300 movs r3, #0 + 800575a: 77fb strb r3, [r7, #31] + 800575c: e08b b.n 8005876 + 800575e: 2302 movs r3, #2 + 8005760: 77fb strb r3, [r7, #31] + 8005762: e088 b.n 8005876 + 8005764: 2304 movs r3, #4 + 8005766: 77fb strb r3, [r7, #31] + 8005768: e085 b.n 8005876 + 800576a: 2308 movs r3, #8 + 800576c: 77fb strb r3, [r7, #31] + 800576e: e082 b.n 8005876 + 8005770: 2310 movs r3, #16 + 8005772: 77fb strb r3, [r7, #31] + 8005774: e07f b.n 8005876 + 8005776: 687b ldr r3, [r7, #4] + 8005778: 681b ldr r3, [r3, #0] + 800577a: 4a82 ldr r2, [pc, #520] @ (8005984 ) + 800577c: 4293 cmp r3, r2 + 800577e: d124 bne.n 80057ca + 8005780: 4b7e ldr r3, [pc, #504] @ (800597c ) + 8005782: 6b1b ldr r3, [r3, #48] @ 0x30 + 8005784: f403 2340 and.w r3, r3, #786432 @ 0xc0000 + 8005788: f5b3 2f40 cmp.w r3, #786432 @ 0xc0000 + 800578c: d011 beq.n 80057b2 + 800578e: f5b3 2f40 cmp.w r3, #786432 @ 0xc0000 + 8005792: d817 bhi.n 80057c4 + 8005794: f5b3 2f00 cmp.w r3, #524288 @ 0x80000 + 8005798: d011 beq.n 80057be + 800579a: f5b3 2f00 cmp.w r3, #524288 @ 0x80000 + 800579e: d811 bhi.n 80057c4 + 80057a0: 2b00 cmp r3, #0 + 80057a2: d003 beq.n 80057ac + 80057a4: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 + 80057a8: d006 beq.n 80057b8 + 80057aa: e00b b.n 80057c4 + 80057ac: 2300 movs r3, #0 + 80057ae: 77fb strb r3, [r7, #31] + 80057b0: e061 b.n 8005876 + 80057b2: 2302 movs r3, #2 + 80057b4: 77fb strb r3, [r7, #31] + 80057b6: e05e b.n 8005876 + 80057b8: 2304 movs r3, #4 + 80057ba: 77fb strb r3, [r7, #31] + 80057bc: e05b b.n 8005876 + 80057be: 2308 movs r3, #8 + 80057c0: 77fb strb r3, [r7, #31] + 80057c2: e058 b.n 8005876 + 80057c4: 2310 movs r3, #16 + 80057c6: 77fb strb r3, [r7, #31] + 80057c8: e055 b.n 8005876 + 80057ca: 687b ldr r3, [r7, #4] + 80057cc: 681b ldr r3, [r3, #0] + 80057ce: 4a6e ldr r2, [pc, #440] @ (8005988 ) + 80057d0: 4293 cmp r3, r2 + 80057d2: d124 bne.n 800581e + 80057d4: 4b69 ldr r3, [pc, #420] @ (800597c ) + 80057d6: 6b1b ldr r3, [r3, #48] @ 0x30 + 80057d8: f403 1340 and.w r3, r3, #3145728 @ 0x300000 + 80057dc: f5b3 1f40 cmp.w r3, #3145728 @ 0x300000 + 80057e0: d011 beq.n 8005806 + 80057e2: f5b3 1f40 cmp.w r3, #3145728 @ 0x300000 + 80057e6: d817 bhi.n 8005818 + 80057e8: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 + 80057ec: d011 beq.n 8005812 + 80057ee: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 + 80057f2: d811 bhi.n 8005818 + 80057f4: 2b00 cmp r3, #0 + 80057f6: d003 beq.n 8005800 + 80057f8: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 + 80057fc: d006 beq.n 800580c + 80057fe: e00b b.n 8005818 + 8005800: 2300 movs r3, #0 + 8005802: 77fb strb r3, [r7, #31] + 8005804: e037 b.n 8005876 + 8005806: 2302 movs r3, #2 + 8005808: 77fb strb r3, [r7, #31] + 800580a: e034 b.n 8005876 + 800580c: 2304 movs r3, #4 + 800580e: 77fb strb r3, [r7, #31] + 8005810: e031 b.n 8005876 + 8005812: 2308 movs r3, #8 + 8005814: 77fb strb r3, [r7, #31] + 8005816: e02e b.n 8005876 + 8005818: 2310 movs r3, #16 + 800581a: 77fb strb r3, [r7, #31] + 800581c: e02b b.n 8005876 + 800581e: 687b ldr r3, [r7, #4] + 8005820: 681b ldr r3, [r3, #0] + 8005822: 4a5a ldr r2, [pc, #360] @ (800598c ) + 8005824: 4293 cmp r3, r2 + 8005826: d124 bne.n 8005872 + 8005828: 4b54 ldr r3, [pc, #336] @ (800597c ) + 800582a: 6b1b ldr r3, [r3, #48] @ 0x30 + 800582c: f403 0340 and.w r3, r3, #12582912 @ 0xc00000 + 8005830: f5b3 0f40 cmp.w r3, #12582912 @ 0xc00000 + 8005834: d011 beq.n 800585a + 8005836: f5b3 0f40 cmp.w r3, #12582912 @ 0xc00000 + 800583a: d817 bhi.n 800586c + 800583c: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 + 8005840: d011 beq.n 8005866 + 8005842: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 + 8005846: d811 bhi.n 800586c + 8005848: 2b00 cmp r3, #0 + 800584a: d003 beq.n 8005854 + 800584c: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 + 8005850: d006 beq.n 8005860 + 8005852: e00b b.n 800586c + 8005854: 2300 movs r3, #0 + 8005856: 77fb strb r3, [r7, #31] + 8005858: e00d b.n 8005876 + 800585a: 2302 movs r3, #2 + 800585c: 77fb strb r3, [r7, #31] + 800585e: e00a b.n 8005876 + 8005860: 2304 movs r3, #4 + 8005862: 77fb strb r3, [r7, #31] + 8005864: e007 b.n 8005876 + 8005866: 2308 movs r3, #8 + 8005868: 77fb strb r3, [r7, #31] + 800586a: e004 b.n 8005876 + 800586c: 2310 movs r3, #16 + 800586e: 77fb strb r3, [r7, #31] + 8005870: e001 b.n 8005876 + 8005872: 2310 movs r3, #16 + 8005874: 77fb strb r3, [r7, #31] if (huart->Init.OverSampling == UART_OVERSAMPLING_8) - 800583e: 687b ldr r3, [r7, #4] - 8005840: 69db ldr r3, [r3, #28] - 8005842: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 - 8005846: d15b bne.n 8005900 + 8005876: 687b ldr r3, [r7, #4] + 8005878: 69db ldr r3, [r3, #28] + 800587a: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 + 800587e: d15b bne.n 8005938 { switch (clocksource) - 8005848: 7ffb ldrb r3, [r7, #31] - 800584a: 2b08 cmp r3, #8 - 800584c: d827 bhi.n 800589e - 800584e: a201 add r2, pc, #4 @ (adr r2, 8005854 ) - 8005850: f852 f023 ldr.w pc, [r2, r3, lsl #2] - 8005854: 08005879 .word 0x08005879 - 8005858: 08005881 .word 0x08005881 - 800585c: 08005889 .word 0x08005889 - 8005860: 0800589f .word 0x0800589f - 8005864: 0800588f .word 0x0800588f - 8005868: 0800589f .word 0x0800589f - 800586c: 0800589f .word 0x0800589f - 8005870: 0800589f .word 0x0800589f - 8005874: 08005897 .word 0x08005897 + 8005880: 7ffb ldrb r3, [r7, #31] + 8005882: 2b08 cmp r3, #8 + 8005884: d827 bhi.n 80058d6 + 8005886: a201 add r2, pc, #4 @ (adr r2, 800588c ) + 8005888: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 800588c: 080058b1 .word 0x080058b1 + 8005890: 080058b9 .word 0x080058b9 + 8005894: 080058c1 .word 0x080058c1 + 8005898: 080058d7 .word 0x080058d7 + 800589c: 080058c7 .word 0x080058c7 + 80058a0: 080058d7 .word 0x080058d7 + 80058a4: 080058d7 .word 0x080058d7 + 80058a8: 080058d7 .word 0x080058d7 + 80058ac: 080058cf .word 0x080058cf { case UART_CLOCKSOURCE_PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); - 8005878: f7ff f9f6 bl 8004c68 - 800587c: 61b8 str r0, [r7, #24] + 80058b0: f7ff f9f6 bl 8004ca0 + 80058b4: 61b8 str r0, [r7, #24] break; - 800587e: e013 b.n 80058a8 + 80058b6: e013 b.n 80058e0 case UART_CLOCKSOURCE_PCLK2: pclk = HAL_RCC_GetPCLK2Freq(); - 8005880: f7ff fa14 bl 8004cac - 8005884: 61b8 str r0, [r7, #24] + 80058b8: f7ff fa14 bl 8004ce4 + 80058bc: 61b8 str r0, [r7, #24] break; - 8005886: e00f b.n 80058a8 + 80058be: e00f b.n 80058e0 case UART_CLOCKSOURCE_HSI: pclk = (uint32_t) HSI_VALUE; - 8005888: 4b33 ldr r3, [pc, #204] @ (8005958 ) - 800588a: 61bb str r3, [r7, #24] + 80058c0: 4b33 ldr r3, [pc, #204] @ (8005990 ) + 80058c2: 61bb str r3, [r7, #24] break; - 800588c: e00c b.n 80058a8 + 80058c4: e00c b.n 80058e0 case UART_CLOCKSOURCE_SYSCLK: pclk = HAL_RCC_GetSysClockFreq(); - 800588e: f7ff f973 bl 8004b78 - 8005892: 61b8 str r0, [r7, #24] + 80058c6: f7ff f973 bl 8004bb0 + 80058ca: 61b8 str r0, [r7, #24] break; - 8005894: e008 b.n 80058a8 + 80058cc: e008 b.n 80058e0 case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; - 8005896: f44f 4300 mov.w r3, #32768 @ 0x8000 - 800589a: 61bb str r3, [r7, #24] + 80058ce: f44f 4300 mov.w r3, #32768 @ 0x8000 + 80058d2: 61bb str r3, [r7, #24] break; - 800589c: e004 b.n 80058a8 + 80058d4: e004 b.n 80058e0 default: pclk = 0U; - 800589e: 2300 movs r3, #0 - 80058a0: 61bb str r3, [r7, #24] + 80058d6: 2300 movs r3, #0 + 80058d8: 61bb str r3, [r7, #24] ret = HAL_ERROR; - 80058a2: 2301 movs r3, #1 - 80058a4: 77bb strb r3, [r7, #30] + 80058da: 2301 movs r3, #1 + 80058dc: 77bb strb r3, [r7, #30] break; - 80058a6: bf00 nop + 80058de: bf00 nop } /* USARTDIV must be greater than or equal to 0d16 */ if (pclk != 0U) - 80058a8: 69bb ldr r3, [r7, #24] - 80058aa: 2b00 cmp r3, #0 - 80058ac: f000 8082 beq.w 80059b4 + 80058e0: 69bb ldr r3, [r7, #24] + 80058e2: 2b00 cmp r3, #0 + 80058e4: f000 8082 beq.w 80059ec { usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate)); - 80058b0: 69bb ldr r3, [r7, #24] - 80058b2: 005a lsls r2, r3, #1 - 80058b4: 687b ldr r3, [r7, #4] - 80058b6: 685b ldr r3, [r3, #4] - 80058b8: 085b lsrs r3, r3, #1 - 80058ba: 441a add r2, r3 - 80058bc: 687b ldr r3, [r7, #4] - 80058be: 685b ldr r3, [r3, #4] - 80058c0: fbb2 f3f3 udiv r3, r2, r3 - 80058c4: 613b str r3, [r7, #16] + 80058e8: 69bb ldr r3, [r7, #24] + 80058ea: 005a lsls r2, r3, #1 + 80058ec: 687b ldr r3, [r7, #4] + 80058ee: 685b ldr r3, [r3, #4] + 80058f0: 085b lsrs r3, r3, #1 + 80058f2: 441a add r2, r3 + 80058f4: 687b ldr r3, [r7, #4] + 80058f6: 685b ldr r3, [r3, #4] + 80058f8: fbb2 f3f3 udiv r3, r2, r3 + 80058fc: 613b str r3, [r7, #16] if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) - 80058c6: 693b ldr r3, [r7, #16] - 80058c8: 2b0f cmp r3, #15 - 80058ca: d916 bls.n 80058fa - 80058cc: 693b ldr r3, [r7, #16] - 80058ce: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 - 80058d2: d212 bcs.n 80058fa + 80058fe: 693b ldr r3, [r7, #16] + 8005900: 2b0f cmp r3, #15 + 8005902: d916 bls.n 8005932 + 8005904: 693b ldr r3, [r7, #16] + 8005906: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 + 800590a: d212 bcs.n 8005932 { brrtemp = (uint16_t)(usartdiv & 0xFFF0U); - 80058d4: 693b ldr r3, [r7, #16] - 80058d6: b29b uxth r3, r3 - 80058d8: f023 030f bic.w r3, r3, #15 - 80058dc: 81fb strh r3, [r7, #14] + 800590c: 693b ldr r3, [r7, #16] + 800590e: b29b uxth r3, r3 + 8005910: f023 030f bic.w r3, r3, #15 + 8005914: 81fb strh r3, [r7, #14] brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); - 80058de: 693b ldr r3, [r7, #16] - 80058e0: 085b lsrs r3, r3, #1 - 80058e2: b29b uxth r3, r3 - 80058e4: f003 0307 and.w r3, r3, #7 - 80058e8: b29a uxth r2, r3 - 80058ea: 89fb ldrh r3, [r7, #14] - 80058ec: 4313 orrs r3, r2 - 80058ee: 81fb strh r3, [r7, #14] + 8005916: 693b ldr r3, [r7, #16] + 8005918: 085b lsrs r3, r3, #1 + 800591a: b29b uxth r3, r3 + 800591c: f003 0307 and.w r3, r3, #7 + 8005920: b29a uxth r2, r3 + 8005922: 89fb ldrh r3, [r7, #14] + 8005924: 4313 orrs r3, r2 + 8005926: 81fb strh r3, [r7, #14] huart->Instance->BRR = brrtemp; - 80058f0: 687b ldr r3, [r7, #4] - 80058f2: 681b ldr r3, [r3, #0] - 80058f4: 89fa ldrh r2, [r7, #14] - 80058f6: 60da str r2, [r3, #12] - 80058f8: e05c b.n 80059b4 + 8005928: 687b ldr r3, [r7, #4] + 800592a: 681b ldr r3, [r3, #0] + 800592c: 89fa ldrh r2, [r7, #14] + 800592e: 60da str r2, [r3, #12] + 8005930: e05c b.n 80059ec } else { ret = HAL_ERROR; - 80058fa: 2301 movs r3, #1 - 80058fc: 77bb strb r3, [r7, #30] - 80058fe: e059 b.n 80059b4 + 8005932: 2301 movs r3, #1 + 8005934: 77bb strb r3, [r7, #30] + 8005936: e059 b.n 80059ec } } } else { switch (clocksource) - 8005900: 7ffb ldrb r3, [r7, #31] - 8005902: 2b08 cmp r3, #8 - 8005904: d835 bhi.n 8005972 - 8005906: a201 add r2, pc, #4 @ (adr r2, 800590c ) - 8005908: f852 f023 ldr.w pc, [r2, r3, lsl #2] - 800590c: 08005931 .word 0x08005931 - 8005910: 08005939 .word 0x08005939 - 8005914: 0800595d .word 0x0800595d - 8005918: 08005973 .word 0x08005973 - 800591c: 08005963 .word 0x08005963 - 8005920: 08005973 .word 0x08005973 - 8005924: 08005973 .word 0x08005973 - 8005928: 08005973 .word 0x08005973 - 800592c: 0800596b .word 0x0800596b + 8005938: 7ffb ldrb r3, [r7, #31] + 800593a: 2b08 cmp r3, #8 + 800593c: d835 bhi.n 80059aa + 800593e: a201 add r2, pc, #4 @ (adr r2, 8005944 ) + 8005940: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8005944: 08005969 .word 0x08005969 + 8005948: 08005971 .word 0x08005971 + 800594c: 08005995 .word 0x08005995 + 8005950: 080059ab .word 0x080059ab + 8005954: 0800599b .word 0x0800599b + 8005958: 080059ab .word 0x080059ab + 800595c: 080059ab .word 0x080059ab + 8005960: 080059ab .word 0x080059ab + 8005964: 080059a3 .word 0x080059a3 { case UART_CLOCKSOURCE_PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); - 8005930: f7ff f99a bl 8004c68 - 8005934: 61b8 str r0, [r7, #24] + 8005968: f7ff f99a bl 8004ca0 + 800596c: 61b8 str r0, [r7, #24] break; - 8005936: e021 b.n 800597c + 800596e: e021 b.n 80059b4 case UART_CLOCKSOURCE_PCLK2: pclk = HAL_RCC_GetPCLK2Freq(); - 8005938: f7ff f9b8 bl 8004cac - 800593c: 61b8 str r0, [r7, #24] + 8005970: f7ff f9b8 bl 8004ce4 + 8005974: 61b8 str r0, [r7, #24] break; - 800593e: e01d b.n 800597c - 8005940: 40013800 .word 0x40013800 - 8005944: 40021000 .word 0x40021000 - 8005948: 40004400 .word 0x40004400 - 800594c: 40004800 .word 0x40004800 - 8005950: 40004c00 .word 0x40004c00 - 8005954: 40005000 .word 0x40005000 - 8005958: 007a1200 .word 0x007a1200 + 8005976: e01d b.n 80059b4 + 8005978: 40013800 .word 0x40013800 + 800597c: 40021000 .word 0x40021000 + 8005980: 40004400 .word 0x40004400 + 8005984: 40004800 .word 0x40004800 + 8005988: 40004c00 .word 0x40004c00 + 800598c: 40005000 .word 0x40005000 + 8005990: 007a1200 .word 0x007a1200 case UART_CLOCKSOURCE_HSI: pclk = (uint32_t) HSI_VALUE; - 800595c: 4b1b ldr r3, [pc, #108] @ (80059cc ) - 800595e: 61bb str r3, [r7, #24] + 8005994: 4b1b ldr r3, [pc, #108] @ (8005a04 ) + 8005996: 61bb str r3, [r7, #24] break; - 8005960: e00c b.n 800597c + 8005998: e00c b.n 80059b4 case UART_CLOCKSOURCE_SYSCLK: pclk = HAL_RCC_GetSysClockFreq(); - 8005962: f7ff f909 bl 8004b78 - 8005966: 61b8 str r0, [r7, #24] + 800599a: f7ff f909 bl 8004bb0 + 800599e: 61b8 str r0, [r7, #24] break; - 8005968: e008 b.n 800597c + 80059a0: e008 b.n 80059b4 case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; - 800596a: f44f 4300 mov.w r3, #32768 @ 0x8000 - 800596e: 61bb str r3, [r7, #24] + 80059a2: f44f 4300 mov.w r3, #32768 @ 0x8000 + 80059a6: 61bb str r3, [r7, #24] break; - 8005970: e004 b.n 800597c + 80059a8: e004 b.n 80059b4 default: pclk = 0U; - 8005972: 2300 movs r3, #0 - 8005974: 61bb str r3, [r7, #24] + 80059aa: 2300 movs r3, #0 + 80059ac: 61bb str r3, [r7, #24] ret = HAL_ERROR; - 8005976: 2301 movs r3, #1 - 8005978: 77bb strb r3, [r7, #30] + 80059ae: 2301 movs r3, #1 + 80059b0: 77bb strb r3, [r7, #30] break; - 800597a: bf00 nop + 80059b2: bf00 nop } if (pclk != 0U) - 800597c: 69bb ldr r3, [r7, #24] - 800597e: 2b00 cmp r3, #0 - 8005980: d018 beq.n 80059b4 + 80059b4: 69bb ldr r3, [r7, #24] + 80059b6: 2b00 cmp r3, #0 + 80059b8: d018 beq.n 80059ec { /* USARTDIV must be greater than or equal to 0d16 */ usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate)); - 8005982: 687b ldr r3, [r7, #4] - 8005984: 685b ldr r3, [r3, #4] - 8005986: 085a lsrs r2, r3, #1 - 8005988: 69bb ldr r3, [r7, #24] - 800598a: 441a add r2, r3 - 800598c: 687b ldr r3, [r7, #4] - 800598e: 685b ldr r3, [r3, #4] - 8005990: fbb2 f3f3 udiv r3, r2, r3 - 8005994: 613b str r3, [r7, #16] + 80059ba: 687b ldr r3, [r7, #4] + 80059bc: 685b ldr r3, [r3, #4] + 80059be: 085a lsrs r2, r3, #1 + 80059c0: 69bb ldr r3, [r7, #24] + 80059c2: 441a add r2, r3 + 80059c4: 687b ldr r3, [r7, #4] + 80059c6: 685b ldr r3, [r3, #4] + 80059c8: fbb2 f3f3 udiv r3, r2, r3 + 80059cc: 613b str r3, [r7, #16] if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) - 8005996: 693b ldr r3, [r7, #16] - 8005998: 2b0f cmp r3, #15 - 800599a: d909 bls.n 80059b0 - 800599c: 693b ldr r3, [r7, #16] - 800599e: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 - 80059a2: d205 bcs.n 80059b0 + 80059ce: 693b ldr r3, [r7, #16] + 80059d0: 2b0f cmp r3, #15 + 80059d2: d909 bls.n 80059e8 + 80059d4: 693b ldr r3, [r7, #16] + 80059d6: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 + 80059da: d205 bcs.n 80059e8 { huart->Instance->BRR = (uint16_t)usartdiv; - 80059a4: 693b ldr r3, [r7, #16] - 80059a6: b29a uxth r2, r3 - 80059a8: 687b ldr r3, [r7, #4] - 80059aa: 681b ldr r3, [r3, #0] - 80059ac: 60da str r2, [r3, #12] - 80059ae: e001 b.n 80059b4 + 80059dc: 693b ldr r3, [r7, #16] + 80059de: b29a uxth r2, r3 + 80059e0: 687b ldr r3, [r7, #4] + 80059e2: 681b ldr r3, [r3, #0] + 80059e4: 60da str r2, [r3, #12] + 80059e6: e001 b.n 80059ec } else { ret = HAL_ERROR; - 80059b0: 2301 movs r3, #1 - 80059b2: 77bb strb r3, [r7, #30] + 80059e8: 2301 movs r3, #1 + 80059ea: 77bb strb r3, [r7, #30] } } /* Clear ISR function pointers */ huart->RxISR = NULL; - 80059b4: 687b ldr r3, [r7, #4] - 80059b6: 2200 movs r2, #0 - 80059b8: 669a str r2, [r3, #104] @ 0x68 + 80059ec: 687b ldr r3, [r7, #4] + 80059ee: 2200 movs r2, #0 + 80059f0: 669a str r2, [r3, #104] @ 0x68 huart->TxISR = NULL; - 80059ba: 687b ldr r3, [r7, #4] - 80059bc: 2200 movs r2, #0 - 80059be: 66da str r2, [r3, #108] @ 0x6c + 80059f2: 687b ldr r3, [r7, #4] + 80059f4: 2200 movs r2, #0 + 80059f6: 66da str r2, [r3, #108] @ 0x6c return ret; - 80059c0: 7fbb ldrb r3, [r7, #30] + 80059f8: 7fbb ldrb r3, [r7, #30] } - 80059c2: 4618 mov r0, r3 - 80059c4: 3720 adds r7, #32 - 80059c6: 46bd mov sp, r7 - 80059c8: bd80 pop {r7, pc} - 80059ca: bf00 nop - 80059cc: 007a1200 .word 0x007a1200 + 80059fa: 4618 mov r0, r3 + 80059fc: 3720 adds r7, #32 + 80059fe: 46bd mov sp, r7 + 8005a00: bd80 pop {r7, pc} + 8005a02: bf00 nop + 8005a04: 007a1200 .word 0x007a1200 -080059d0 : +08005a08 : * @brief Configure the UART peripheral advanced features. * @param huart UART handle. * @retval None */ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) { - 80059d0: b480 push {r7} - 80059d2: b083 sub sp, #12 - 80059d4: af00 add r7, sp, #0 - 80059d6: 6078 str r0, [r7, #4] + 8005a08: b480 push {r7} + 8005a0a: b083 sub sp, #12 + 8005a0c: af00 add r7, sp, #0 + 8005a0e: 6078 str r0, [r7, #4] /* Check whether the set of advanced features to configure is properly set */ assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); /* if required, configure TX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) - 80059d8: 687b ldr r3, [r7, #4] - 80059da: 6a5b ldr r3, [r3, #36] @ 0x24 - 80059dc: f003 0301 and.w r3, r3, #1 - 80059e0: 2b00 cmp r3, #0 - 80059e2: d00a beq.n 80059fa + 8005a10: 687b ldr r3, [r7, #4] + 8005a12: 6a5b ldr r3, [r3, #36] @ 0x24 + 8005a14: f003 0301 and.w r3, r3, #1 + 8005a18: 2b00 cmp r3, #0 + 8005a1a: d00a beq.n 8005a32 { assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); - 80059e4: 687b ldr r3, [r7, #4] - 80059e6: 681b ldr r3, [r3, #0] - 80059e8: 685b ldr r3, [r3, #4] - 80059ea: f423 3100 bic.w r1, r3, #131072 @ 0x20000 - 80059ee: 687b ldr r3, [r7, #4] - 80059f0: 6a9a ldr r2, [r3, #40] @ 0x28 - 80059f2: 687b ldr r3, [r7, #4] - 80059f4: 681b ldr r3, [r3, #0] - 80059f6: 430a orrs r2, r1 - 80059f8: 605a str r2, [r3, #4] + 8005a1c: 687b ldr r3, [r7, #4] + 8005a1e: 681b ldr r3, [r3, #0] + 8005a20: 685b ldr r3, [r3, #4] + 8005a22: f423 3100 bic.w r1, r3, #131072 @ 0x20000 + 8005a26: 687b ldr r3, [r7, #4] + 8005a28: 6a9a ldr r2, [r3, #40] @ 0x28 + 8005a2a: 687b ldr r3, [r7, #4] + 8005a2c: 681b ldr r3, [r3, #0] + 8005a2e: 430a orrs r2, r1 + 8005a30: 605a str r2, [r3, #4] } /* if required, configure RX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) - 80059fa: 687b ldr r3, [r7, #4] - 80059fc: 6a5b ldr r3, [r3, #36] @ 0x24 - 80059fe: f003 0302 and.w r3, r3, #2 - 8005a02: 2b00 cmp r3, #0 - 8005a04: d00a beq.n 8005a1c + 8005a32: 687b ldr r3, [r7, #4] + 8005a34: 6a5b ldr r3, [r3, #36] @ 0x24 + 8005a36: f003 0302 and.w r3, r3, #2 + 8005a3a: 2b00 cmp r3, #0 + 8005a3c: d00a beq.n 8005a54 { assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); - 8005a06: 687b ldr r3, [r7, #4] - 8005a08: 681b ldr r3, [r3, #0] - 8005a0a: 685b ldr r3, [r3, #4] - 8005a0c: f423 3180 bic.w r1, r3, #65536 @ 0x10000 - 8005a10: 687b ldr r3, [r7, #4] - 8005a12: 6ada ldr r2, [r3, #44] @ 0x2c - 8005a14: 687b ldr r3, [r7, #4] - 8005a16: 681b ldr r3, [r3, #0] - 8005a18: 430a orrs r2, r1 - 8005a1a: 605a str r2, [r3, #4] + 8005a3e: 687b ldr r3, [r7, #4] + 8005a40: 681b ldr r3, [r3, #0] + 8005a42: 685b ldr r3, [r3, #4] + 8005a44: f423 3180 bic.w r1, r3, #65536 @ 0x10000 + 8005a48: 687b ldr r3, [r7, #4] + 8005a4a: 6ada ldr r2, [r3, #44] @ 0x2c + 8005a4c: 687b ldr r3, [r7, #4] + 8005a4e: 681b ldr r3, [r3, #0] + 8005a50: 430a orrs r2, r1 + 8005a52: 605a str r2, [r3, #4] } /* if required, configure data inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) - 8005a1c: 687b ldr r3, [r7, #4] - 8005a1e: 6a5b ldr r3, [r3, #36] @ 0x24 - 8005a20: f003 0304 and.w r3, r3, #4 - 8005a24: 2b00 cmp r3, #0 - 8005a26: d00a beq.n 8005a3e + 8005a54: 687b ldr r3, [r7, #4] + 8005a56: 6a5b ldr r3, [r3, #36] @ 0x24 + 8005a58: f003 0304 and.w r3, r3, #4 + 8005a5c: 2b00 cmp r3, #0 + 8005a5e: d00a beq.n 8005a76 { assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); - 8005a28: 687b ldr r3, [r7, #4] - 8005a2a: 681b ldr r3, [r3, #0] - 8005a2c: 685b ldr r3, [r3, #4] - 8005a2e: f423 2180 bic.w r1, r3, #262144 @ 0x40000 - 8005a32: 687b ldr r3, [r7, #4] - 8005a34: 6b1a ldr r2, [r3, #48] @ 0x30 - 8005a36: 687b ldr r3, [r7, #4] - 8005a38: 681b ldr r3, [r3, #0] - 8005a3a: 430a orrs r2, r1 - 8005a3c: 605a str r2, [r3, #4] + 8005a60: 687b ldr r3, [r7, #4] + 8005a62: 681b ldr r3, [r3, #0] + 8005a64: 685b ldr r3, [r3, #4] + 8005a66: f423 2180 bic.w r1, r3, #262144 @ 0x40000 + 8005a6a: 687b ldr r3, [r7, #4] + 8005a6c: 6b1a ldr r2, [r3, #48] @ 0x30 + 8005a6e: 687b ldr r3, [r7, #4] + 8005a70: 681b ldr r3, [r3, #0] + 8005a72: 430a orrs r2, r1 + 8005a74: 605a str r2, [r3, #4] } /* if required, configure RX/TX pins swap */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) - 8005a3e: 687b ldr r3, [r7, #4] - 8005a40: 6a5b ldr r3, [r3, #36] @ 0x24 - 8005a42: f003 0308 and.w r3, r3, #8 - 8005a46: 2b00 cmp r3, #0 - 8005a48: d00a beq.n 8005a60 + 8005a76: 687b ldr r3, [r7, #4] + 8005a78: 6a5b ldr r3, [r3, #36] @ 0x24 + 8005a7a: f003 0308 and.w r3, r3, #8 + 8005a7e: 2b00 cmp r3, #0 + 8005a80: d00a beq.n 8005a98 { assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); - 8005a4a: 687b ldr r3, [r7, #4] - 8005a4c: 681b ldr r3, [r3, #0] - 8005a4e: 685b ldr r3, [r3, #4] - 8005a50: f423 4100 bic.w r1, r3, #32768 @ 0x8000 - 8005a54: 687b ldr r3, [r7, #4] - 8005a56: 6b5a ldr r2, [r3, #52] @ 0x34 - 8005a58: 687b ldr r3, [r7, #4] - 8005a5a: 681b ldr r3, [r3, #0] - 8005a5c: 430a orrs r2, r1 - 8005a5e: 605a str r2, [r3, #4] + 8005a82: 687b ldr r3, [r7, #4] + 8005a84: 681b ldr r3, [r3, #0] + 8005a86: 685b ldr r3, [r3, #4] + 8005a88: f423 4100 bic.w r1, r3, #32768 @ 0x8000 + 8005a8c: 687b ldr r3, [r7, #4] + 8005a8e: 6b5a ldr r2, [r3, #52] @ 0x34 + 8005a90: 687b ldr r3, [r7, #4] + 8005a92: 681b ldr r3, [r3, #0] + 8005a94: 430a orrs r2, r1 + 8005a96: 605a str r2, [r3, #4] } /* if required, configure RX overrun detection disabling */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) - 8005a60: 687b ldr r3, [r7, #4] - 8005a62: 6a5b ldr r3, [r3, #36] @ 0x24 - 8005a64: f003 0310 and.w r3, r3, #16 - 8005a68: 2b00 cmp r3, #0 - 8005a6a: d00a beq.n 8005a82 + 8005a98: 687b ldr r3, [r7, #4] + 8005a9a: 6a5b ldr r3, [r3, #36] @ 0x24 + 8005a9c: f003 0310 and.w r3, r3, #16 + 8005aa0: 2b00 cmp r3, #0 + 8005aa2: d00a beq.n 8005aba { assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); - 8005a6c: 687b ldr r3, [r7, #4] - 8005a6e: 681b ldr r3, [r3, #0] - 8005a70: 689b ldr r3, [r3, #8] - 8005a72: f423 5180 bic.w r1, r3, #4096 @ 0x1000 - 8005a76: 687b ldr r3, [r7, #4] - 8005a78: 6b9a ldr r2, [r3, #56] @ 0x38 - 8005a7a: 687b ldr r3, [r7, #4] - 8005a7c: 681b ldr r3, [r3, #0] - 8005a7e: 430a orrs r2, r1 - 8005a80: 609a str r2, [r3, #8] + 8005aa4: 687b ldr r3, [r7, #4] + 8005aa6: 681b ldr r3, [r3, #0] + 8005aa8: 689b ldr r3, [r3, #8] + 8005aaa: f423 5180 bic.w r1, r3, #4096 @ 0x1000 + 8005aae: 687b ldr r3, [r7, #4] + 8005ab0: 6b9a ldr r2, [r3, #56] @ 0x38 + 8005ab2: 687b ldr r3, [r7, #4] + 8005ab4: 681b ldr r3, [r3, #0] + 8005ab6: 430a orrs r2, r1 + 8005ab8: 609a str r2, [r3, #8] } /* if required, configure DMA disabling on reception error */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) - 8005a82: 687b ldr r3, [r7, #4] - 8005a84: 6a5b ldr r3, [r3, #36] @ 0x24 - 8005a86: f003 0320 and.w r3, r3, #32 - 8005a8a: 2b00 cmp r3, #0 - 8005a8c: d00a beq.n 8005aa4 + 8005aba: 687b ldr r3, [r7, #4] + 8005abc: 6a5b ldr r3, [r3, #36] @ 0x24 + 8005abe: f003 0320 and.w r3, r3, #32 + 8005ac2: 2b00 cmp r3, #0 + 8005ac4: d00a beq.n 8005adc { assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); - 8005a8e: 687b ldr r3, [r7, #4] - 8005a90: 681b ldr r3, [r3, #0] - 8005a92: 689b ldr r3, [r3, #8] - 8005a94: f423 5100 bic.w r1, r3, #8192 @ 0x2000 - 8005a98: 687b ldr r3, [r7, #4] - 8005a9a: 6bda ldr r2, [r3, #60] @ 0x3c - 8005a9c: 687b ldr r3, [r7, #4] - 8005a9e: 681b ldr r3, [r3, #0] - 8005aa0: 430a orrs r2, r1 - 8005aa2: 609a str r2, [r3, #8] + 8005ac6: 687b ldr r3, [r7, #4] + 8005ac8: 681b ldr r3, [r3, #0] + 8005aca: 689b ldr r3, [r3, #8] + 8005acc: f423 5100 bic.w r1, r3, #8192 @ 0x2000 + 8005ad0: 687b ldr r3, [r7, #4] + 8005ad2: 6bda ldr r2, [r3, #60] @ 0x3c + 8005ad4: 687b ldr r3, [r7, #4] + 8005ad6: 681b ldr r3, [r3, #0] + 8005ad8: 430a orrs r2, r1 + 8005ada: 609a str r2, [r3, #8] } /* if required, configure auto Baud rate detection scheme */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) - 8005aa4: 687b ldr r3, [r7, #4] - 8005aa6: 6a5b ldr r3, [r3, #36] @ 0x24 - 8005aa8: f003 0340 and.w r3, r3, #64 @ 0x40 - 8005aac: 2b00 cmp r3, #0 - 8005aae: d01a beq.n 8005ae6 + 8005adc: 687b ldr r3, [r7, #4] + 8005ade: 6a5b ldr r3, [r3, #36] @ 0x24 + 8005ae0: f003 0340 and.w r3, r3, #64 @ 0x40 + 8005ae4: 2b00 cmp r3, #0 + 8005ae6: d01a beq.n 8005b1e { assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance)); assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); - 8005ab0: 687b ldr r3, [r7, #4] - 8005ab2: 681b ldr r3, [r3, #0] - 8005ab4: 685b ldr r3, [r3, #4] - 8005ab6: f423 1180 bic.w r1, r3, #1048576 @ 0x100000 - 8005aba: 687b ldr r3, [r7, #4] - 8005abc: 6c1a ldr r2, [r3, #64] @ 0x40 - 8005abe: 687b ldr r3, [r7, #4] - 8005ac0: 681b ldr r3, [r3, #0] - 8005ac2: 430a orrs r2, r1 - 8005ac4: 605a str r2, [r3, #4] + 8005ae8: 687b ldr r3, [r7, #4] + 8005aea: 681b ldr r3, [r3, #0] + 8005aec: 685b ldr r3, [r3, #4] + 8005aee: f423 1180 bic.w r1, r3, #1048576 @ 0x100000 + 8005af2: 687b ldr r3, [r7, #4] + 8005af4: 6c1a ldr r2, [r3, #64] @ 0x40 + 8005af6: 687b ldr r3, [r7, #4] + 8005af8: 681b ldr r3, [r3, #0] + 8005afa: 430a orrs r2, r1 + 8005afc: 605a str r2, [r3, #4] /* set auto Baudrate detection parameters if detection is enabled */ if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) - 8005ac6: 687b ldr r3, [r7, #4] - 8005ac8: 6c1b ldr r3, [r3, #64] @ 0x40 - 8005aca: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 - 8005ace: d10a bne.n 8005ae6 + 8005afe: 687b ldr r3, [r7, #4] + 8005b00: 6c1b ldr r3, [r3, #64] @ 0x40 + 8005b02: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 + 8005b06: d10a bne.n 8005b1e { assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); - 8005ad0: 687b ldr r3, [r7, #4] - 8005ad2: 681b ldr r3, [r3, #0] - 8005ad4: 685b ldr r3, [r3, #4] - 8005ad6: f423 01c0 bic.w r1, r3, #6291456 @ 0x600000 - 8005ada: 687b ldr r3, [r7, #4] - 8005adc: 6c5a ldr r2, [r3, #68] @ 0x44 - 8005ade: 687b ldr r3, [r7, #4] - 8005ae0: 681b ldr r3, [r3, #0] - 8005ae2: 430a orrs r2, r1 - 8005ae4: 605a str r2, [r3, #4] + 8005b08: 687b ldr r3, [r7, #4] + 8005b0a: 681b ldr r3, [r3, #0] + 8005b0c: 685b ldr r3, [r3, #4] + 8005b0e: f423 01c0 bic.w r1, r3, #6291456 @ 0x600000 + 8005b12: 687b ldr r3, [r7, #4] + 8005b14: 6c5a ldr r2, [r3, #68] @ 0x44 + 8005b16: 687b ldr r3, [r7, #4] + 8005b18: 681b ldr r3, [r3, #0] + 8005b1a: 430a orrs r2, r1 + 8005b1c: 605a str r2, [r3, #4] } } /* if required, configure MSB first on communication line */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) - 8005ae6: 687b ldr r3, [r7, #4] - 8005ae8: 6a5b ldr r3, [r3, #36] @ 0x24 - 8005aea: f003 0380 and.w r3, r3, #128 @ 0x80 - 8005aee: 2b00 cmp r3, #0 - 8005af0: d00a beq.n 8005b08 + 8005b1e: 687b ldr r3, [r7, #4] + 8005b20: 6a5b ldr r3, [r3, #36] @ 0x24 + 8005b22: f003 0380 and.w r3, r3, #128 @ 0x80 + 8005b26: 2b00 cmp r3, #0 + 8005b28: d00a beq.n 8005b40 { assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); - 8005af2: 687b ldr r3, [r7, #4] - 8005af4: 681b ldr r3, [r3, #0] - 8005af6: 685b ldr r3, [r3, #4] - 8005af8: f423 2100 bic.w r1, r3, #524288 @ 0x80000 - 8005afc: 687b ldr r3, [r7, #4] - 8005afe: 6c9a ldr r2, [r3, #72] @ 0x48 - 8005b00: 687b ldr r3, [r7, #4] - 8005b02: 681b ldr r3, [r3, #0] - 8005b04: 430a orrs r2, r1 - 8005b06: 605a str r2, [r3, #4] + 8005b2a: 687b ldr r3, [r7, #4] + 8005b2c: 681b ldr r3, [r3, #0] + 8005b2e: 685b ldr r3, [r3, #4] + 8005b30: f423 2100 bic.w r1, r3, #524288 @ 0x80000 + 8005b34: 687b ldr r3, [r7, #4] + 8005b36: 6c9a ldr r2, [r3, #72] @ 0x48 + 8005b38: 687b ldr r3, [r7, #4] + 8005b3a: 681b ldr r3, [r3, #0] + 8005b3c: 430a orrs r2, r1 + 8005b3e: 605a str r2, [r3, #4] } } - 8005b08: bf00 nop - 8005b0a: 370c adds r7, #12 - 8005b0c: 46bd mov sp, r7 - 8005b0e: f85d 7b04 ldr.w r7, [sp], #4 - 8005b12: 4770 bx lr + 8005b40: bf00 nop + 8005b42: 370c adds r7, #12 + 8005b44: 46bd mov sp, r7 + 8005b46: f85d 7b04 ldr.w r7, [sp], #4 + 8005b4a: 4770 bx lr -08005b14 : +08005b4c : * @brief Check the UART Idle State. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) { - 8005b14: b580 push {r7, lr} - 8005b16: b098 sub sp, #96 @ 0x60 - 8005b18: af02 add r7, sp, #8 - 8005b1a: 6078 str r0, [r7, #4] + 8005b4c: b580 push {r7, lr} + 8005b4e: b098 sub sp, #96 @ 0x60 + 8005b50: af02 add r7, sp, #8 + 8005b52: 6078 str r0, [r7, #4] uint32_t tickstart; /* Initialize the UART ErrorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; - 8005b1c: 687b ldr r3, [r7, #4] - 8005b1e: 2200 movs r2, #0 - 8005b20: f8c3 2084 str.w r2, [r3, #132] @ 0x84 + 8005b54: 687b ldr r3, [r7, #4] + 8005b56: 2200 movs r2, #0 + 8005b58: f8c3 2084 str.w r2, [r3, #132] @ 0x84 /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); - 8005b24: f7fb fc68 bl 80013f8 - 8005b28: 6578 str r0, [r7, #84] @ 0x54 + 8005b5c: f7fb fc68 bl 8001430 + 8005b60: 6578 str r0, [r7, #84] @ 0x54 /* Check if the Transmitter is enabled */ if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) - 8005b2a: 687b ldr r3, [r7, #4] - 8005b2c: 681b ldr r3, [r3, #0] - 8005b2e: 681b ldr r3, [r3, #0] - 8005b30: f003 0308 and.w r3, r3, #8 - 8005b34: 2b08 cmp r3, #8 - 8005b36: d12e bne.n 8005b96 + 8005b62: 687b ldr r3, [r7, #4] + 8005b64: 681b ldr r3, [r3, #0] + 8005b66: 681b ldr r3, [r3, #0] + 8005b68: f003 0308 and.w r3, r3, #8 + 8005b6c: 2b08 cmp r3, #8 + 8005b6e: d12e bne.n 8005bce { /* Wait until TEACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) - 8005b38: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000 - 8005b3c: 9300 str r3, [sp, #0] - 8005b3e: 6d7b ldr r3, [r7, #84] @ 0x54 - 8005b40: 2200 movs r2, #0 - 8005b42: f44f 1100 mov.w r1, #2097152 @ 0x200000 - 8005b46: 6878 ldr r0, [r7, #4] - 8005b48: f000 f88c bl 8005c64 - 8005b4c: 4603 mov r3, r0 - 8005b4e: 2b00 cmp r3, #0 - 8005b50: d021 beq.n 8005b96 + 8005b70: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000 + 8005b74: 9300 str r3, [sp, #0] + 8005b76: 6d7b ldr r3, [r7, #84] @ 0x54 + 8005b78: 2200 movs r2, #0 + 8005b7a: f44f 1100 mov.w r1, #2097152 @ 0x200000 + 8005b7e: 6878 ldr r0, [r7, #4] + 8005b80: f000 f88c bl 8005c9c + 8005b84: 4603 mov r3, r0 + 8005b86: 2b00 cmp r3, #0 + 8005b88: d021 beq.n 8005bce { /* Disable TXE interrupt for the interrupt process */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE)); - 8005b52: 687b ldr r3, [r7, #4] - 8005b54: 681b ldr r3, [r3, #0] - 8005b56: 63bb str r3, [r7, #56] @ 0x38 + 8005b8a: 687b ldr r3, [r7, #4] + 8005b8c: 681b ldr r3, [r3, #0] + 8005b8e: 63bb str r3, [r7, #56] @ 0x38 */ __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) { uint32_t result; __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 8005b58: 6bbb ldr r3, [r7, #56] @ 0x38 - 8005b5a: e853 3f00 ldrex r3, [r3] - 8005b5e: 637b str r3, [r7, #52] @ 0x34 + 8005b90: 6bbb ldr r3, [r7, #56] @ 0x38 + 8005b92: e853 3f00 ldrex r3, [r3] + 8005b96: 637b str r3, [r7, #52] @ 0x34 return(result); - 8005b60: 6b7b ldr r3, [r7, #52] @ 0x34 - 8005b62: f023 0380 bic.w r3, r3, #128 @ 0x80 - 8005b66: 653b str r3, [r7, #80] @ 0x50 - 8005b68: 687b ldr r3, [r7, #4] - 8005b6a: 681b ldr r3, [r3, #0] - 8005b6c: 461a mov r2, r3 - 8005b6e: 6d3b ldr r3, [r7, #80] @ 0x50 - 8005b70: 647b str r3, [r7, #68] @ 0x44 - 8005b72: 643a str r2, [r7, #64] @ 0x40 + 8005b98: 6b7b ldr r3, [r7, #52] @ 0x34 + 8005b9a: f023 0380 bic.w r3, r3, #128 @ 0x80 + 8005b9e: 653b str r3, [r7, #80] @ 0x50 + 8005ba0: 687b ldr r3, [r7, #4] + 8005ba2: 681b ldr r3, [r3, #0] + 8005ba4: 461a mov r2, r3 + 8005ba6: 6d3b ldr r3, [r7, #80] @ 0x50 + 8005ba8: 647b str r3, [r7, #68] @ 0x44 + 8005baa: 643a str r2, [r7, #64] @ 0x40 */ __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) { uint32_t result; __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 8005b74: 6c39 ldr r1, [r7, #64] @ 0x40 - 8005b76: 6c7a ldr r2, [r7, #68] @ 0x44 - 8005b78: e841 2300 strex r3, r2, [r1] - 8005b7c: 63fb str r3, [r7, #60] @ 0x3c + 8005bac: 6c39 ldr r1, [r7, #64] @ 0x40 + 8005bae: 6c7a ldr r2, [r7, #68] @ 0x44 + 8005bb0: e841 2300 strex r3, r2, [r1] + 8005bb4: 63fb str r3, [r7, #60] @ 0x3c return(result); - 8005b7e: 6bfb ldr r3, [r7, #60] @ 0x3c - 8005b80: 2b00 cmp r3, #0 - 8005b82: d1e6 bne.n 8005b52 + 8005bb6: 6bfb ldr r3, [r7, #60] @ 0x3c + 8005bb8: 2b00 cmp r3, #0 + 8005bba: d1e6 bne.n 8005b8a huart->gState = HAL_UART_STATE_READY; - 8005b84: 687b ldr r3, [r7, #4] - 8005b86: 2220 movs r2, #32 - 8005b88: 67da str r2, [r3, #124] @ 0x7c + 8005bbc: 687b ldr r3, [r7, #4] + 8005bbe: 2220 movs r2, #32 + 8005bc0: 67da str r2, [r3, #124] @ 0x7c __HAL_UNLOCK(huart); - 8005b8a: 687b ldr r3, [r7, #4] - 8005b8c: 2200 movs r2, #0 - 8005b8e: f883 2078 strb.w r2, [r3, #120] @ 0x78 + 8005bc2: 687b ldr r3, [r7, #4] + 8005bc4: 2200 movs r2, #0 + 8005bc6: f883 2078 strb.w r2, [r3, #120] @ 0x78 /* Timeout occurred */ return HAL_TIMEOUT; - 8005b92: 2303 movs r3, #3 - 8005b94: e062 b.n 8005c5c + 8005bca: 2303 movs r3, #3 + 8005bcc: e062 b.n 8005c94 } } /* Check if the Receiver is enabled */ if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) - 8005b96: 687b ldr r3, [r7, #4] - 8005b98: 681b ldr r3, [r3, #0] - 8005b9a: 681b ldr r3, [r3, #0] - 8005b9c: f003 0304 and.w r3, r3, #4 - 8005ba0: 2b04 cmp r3, #4 - 8005ba2: d149 bne.n 8005c38 + 8005bce: 687b ldr r3, [r7, #4] + 8005bd0: 681b ldr r3, [r3, #0] + 8005bd2: 681b ldr r3, [r3, #0] + 8005bd4: f003 0304 and.w r3, r3, #4 + 8005bd8: 2b04 cmp r3, #4 + 8005bda: d149 bne.n 8005c70 { /* Wait until REACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) - 8005ba4: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000 - 8005ba8: 9300 str r3, [sp, #0] - 8005baa: 6d7b ldr r3, [r7, #84] @ 0x54 - 8005bac: 2200 movs r2, #0 - 8005bae: f44f 0180 mov.w r1, #4194304 @ 0x400000 - 8005bb2: 6878 ldr r0, [r7, #4] - 8005bb4: f000 f856 bl 8005c64 - 8005bb8: 4603 mov r3, r0 - 8005bba: 2b00 cmp r3, #0 - 8005bbc: d03c beq.n 8005c38 + 8005bdc: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000 + 8005be0: 9300 str r3, [sp, #0] + 8005be2: 6d7b ldr r3, [r7, #84] @ 0x54 + 8005be4: 2200 movs r2, #0 + 8005be6: f44f 0180 mov.w r1, #4194304 @ 0x400000 + 8005bea: 6878 ldr r0, [r7, #4] + 8005bec: f000 f856 bl 8005c9c + 8005bf0: 4603 mov r3, r0 + 8005bf2: 2b00 cmp r3, #0 + 8005bf4: d03c beq.n 8005c70 { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); - 8005bbe: 687b ldr r3, [r7, #4] - 8005bc0: 681b ldr r3, [r3, #0] - 8005bc2: 627b str r3, [r7, #36] @ 0x24 + 8005bf6: 687b ldr r3, [r7, #4] + 8005bf8: 681b ldr r3, [r3, #0] + 8005bfa: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 8005bc4: 6a7b ldr r3, [r7, #36] @ 0x24 - 8005bc6: e853 3f00 ldrex r3, [r3] - 8005bca: 623b str r3, [r7, #32] + 8005bfc: 6a7b ldr r3, [r7, #36] @ 0x24 + 8005bfe: e853 3f00 ldrex r3, [r3] + 8005c02: 623b str r3, [r7, #32] return(result); - 8005bcc: 6a3b ldr r3, [r7, #32] - 8005bce: f423 7390 bic.w r3, r3, #288 @ 0x120 - 8005bd2: 64fb str r3, [r7, #76] @ 0x4c - 8005bd4: 687b ldr r3, [r7, #4] - 8005bd6: 681b ldr r3, [r3, #0] - 8005bd8: 461a mov r2, r3 - 8005bda: 6cfb ldr r3, [r7, #76] @ 0x4c - 8005bdc: 633b str r3, [r7, #48] @ 0x30 - 8005bde: 62fa str r2, [r7, #44] @ 0x2c + 8005c04: 6a3b ldr r3, [r7, #32] + 8005c06: f423 7390 bic.w r3, r3, #288 @ 0x120 + 8005c0a: 64fb str r3, [r7, #76] @ 0x4c + 8005c0c: 687b ldr r3, [r7, #4] + 8005c0e: 681b ldr r3, [r3, #0] + 8005c10: 461a mov r2, r3 + 8005c12: 6cfb ldr r3, [r7, #76] @ 0x4c + 8005c14: 633b str r3, [r7, #48] @ 0x30 + 8005c16: 62fa str r2, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 8005be0: 6af9 ldr r1, [r7, #44] @ 0x2c - 8005be2: 6b3a ldr r2, [r7, #48] @ 0x30 - 8005be4: e841 2300 strex r3, r2, [r1] - 8005be8: 62bb str r3, [r7, #40] @ 0x28 + 8005c18: 6af9 ldr r1, [r7, #44] @ 0x2c + 8005c1a: 6b3a ldr r2, [r7, #48] @ 0x30 + 8005c1c: e841 2300 strex r3, r2, [r1] + 8005c20: 62bb str r3, [r7, #40] @ 0x28 return(result); - 8005bea: 6abb ldr r3, [r7, #40] @ 0x28 - 8005bec: 2b00 cmp r3, #0 - 8005bee: d1e6 bne.n 8005bbe + 8005c22: 6abb ldr r3, [r7, #40] @ 0x28 + 8005c24: 2b00 cmp r3, #0 + 8005c26: d1e6 bne.n 8005bf6 ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - 8005bf0: 687b ldr r3, [r7, #4] - 8005bf2: 681b ldr r3, [r3, #0] - 8005bf4: 3308 adds r3, #8 - 8005bf6: 613b str r3, [r7, #16] + 8005c28: 687b ldr r3, [r7, #4] + 8005c2a: 681b ldr r3, [r3, #0] + 8005c2c: 3308 adds r3, #8 + 8005c2e: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 8005bf8: 693b ldr r3, [r7, #16] - 8005bfa: e853 3f00 ldrex r3, [r3] - 8005bfe: 60fb str r3, [r7, #12] + 8005c30: 693b ldr r3, [r7, #16] + 8005c32: e853 3f00 ldrex r3, [r3] + 8005c36: 60fb str r3, [r7, #12] return(result); - 8005c00: 68fb ldr r3, [r7, #12] - 8005c02: f023 0301 bic.w r3, r3, #1 - 8005c06: 64bb str r3, [r7, #72] @ 0x48 - 8005c08: 687b ldr r3, [r7, #4] - 8005c0a: 681b ldr r3, [r3, #0] - 8005c0c: 3308 adds r3, #8 - 8005c0e: 6cba ldr r2, [r7, #72] @ 0x48 - 8005c10: 61fa str r2, [r7, #28] - 8005c12: 61bb str r3, [r7, #24] + 8005c38: 68fb ldr r3, [r7, #12] + 8005c3a: f023 0301 bic.w r3, r3, #1 + 8005c3e: 64bb str r3, [r7, #72] @ 0x48 + 8005c40: 687b ldr r3, [r7, #4] + 8005c42: 681b ldr r3, [r3, #0] + 8005c44: 3308 adds r3, #8 + 8005c46: 6cba ldr r2, [r7, #72] @ 0x48 + 8005c48: 61fa str r2, [r7, #28] + 8005c4a: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 8005c14: 69b9 ldr r1, [r7, #24] - 8005c16: 69fa ldr r2, [r7, #28] - 8005c18: e841 2300 strex r3, r2, [r1] - 8005c1c: 617b str r3, [r7, #20] + 8005c4c: 69b9 ldr r1, [r7, #24] + 8005c4e: 69fa ldr r2, [r7, #28] + 8005c50: e841 2300 strex r3, r2, [r1] + 8005c54: 617b str r3, [r7, #20] return(result); - 8005c1e: 697b ldr r3, [r7, #20] - 8005c20: 2b00 cmp r3, #0 - 8005c22: d1e5 bne.n 8005bf0 + 8005c56: 697b ldr r3, [r7, #20] + 8005c58: 2b00 cmp r3, #0 + 8005c5a: d1e5 bne.n 8005c28 huart->RxState = HAL_UART_STATE_READY; - 8005c24: 687b ldr r3, [r7, #4] - 8005c26: 2220 movs r2, #32 - 8005c28: f8c3 2080 str.w r2, [r3, #128] @ 0x80 + 8005c5c: 687b ldr r3, [r7, #4] + 8005c5e: 2220 movs r2, #32 + 8005c60: f8c3 2080 str.w r2, [r3, #128] @ 0x80 __HAL_UNLOCK(huart); - 8005c2c: 687b ldr r3, [r7, #4] - 8005c2e: 2200 movs r2, #0 - 8005c30: f883 2078 strb.w r2, [r3, #120] @ 0x78 + 8005c64: 687b ldr r3, [r7, #4] + 8005c66: 2200 movs r2, #0 + 8005c68: f883 2078 strb.w r2, [r3, #120] @ 0x78 /* Timeout occurred */ return HAL_TIMEOUT; - 8005c34: 2303 movs r3, #3 - 8005c36: e011 b.n 8005c5c + 8005c6c: 2303 movs r3, #3 + 8005c6e: e011 b.n 8005c94 } } /* Initialize the UART State */ huart->gState = HAL_UART_STATE_READY; - 8005c38: 687b ldr r3, [r7, #4] - 8005c3a: 2220 movs r2, #32 - 8005c3c: 67da str r2, [r3, #124] @ 0x7c + 8005c70: 687b ldr r3, [r7, #4] + 8005c72: 2220 movs r2, #32 + 8005c74: 67da str r2, [r3, #124] @ 0x7c huart->RxState = HAL_UART_STATE_READY; - 8005c3e: 687b ldr r3, [r7, #4] - 8005c40: 2220 movs r2, #32 - 8005c42: f8c3 2080 str.w r2, [r3, #128] @ 0x80 + 8005c76: 687b ldr r3, [r7, #4] + 8005c78: 2220 movs r2, #32 + 8005c7a: f8c3 2080 str.w r2, [r3, #128] @ 0x80 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - 8005c46: 687b ldr r3, [r7, #4] - 8005c48: 2200 movs r2, #0 - 8005c4a: 661a str r2, [r3, #96] @ 0x60 + 8005c7e: 687b ldr r3, [r7, #4] + 8005c80: 2200 movs r2, #0 + 8005c82: 661a str r2, [r3, #96] @ 0x60 huart->RxEventType = HAL_UART_RXEVENT_TC; - 8005c4c: 687b ldr r3, [r7, #4] - 8005c4e: 2200 movs r2, #0 - 8005c50: 665a str r2, [r3, #100] @ 0x64 + 8005c84: 687b ldr r3, [r7, #4] + 8005c86: 2200 movs r2, #0 + 8005c88: 665a str r2, [r3, #100] @ 0x64 __HAL_UNLOCK(huart); - 8005c52: 687b ldr r3, [r7, #4] - 8005c54: 2200 movs r2, #0 - 8005c56: f883 2078 strb.w r2, [r3, #120] @ 0x78 + 8005c8a: 687b ldr r3, [r7, #4] + 8005c8c: 2200 movs r2, #0 + 8005c8e: f883 2078 strb.w r2, [r3, #120] @ 0x78 return HAL_OK; - 8005c5a: 2300 movs r3, #0 + 8005c92: 2300 movs r3, #0 } - 8005c5c: 4618 mov r0, r3 - 8005c5e: 3758 adds r7, #88 @ 0x58 - 8005c60: 46bd mov sp, r7 - 8005c62: bd80 pop {r7, pc} + 8005c94: 4618 mov r0, r3 + 8005c96: 3758 adds r7, #88 @ 0x58 + 8005c98: 46bd mov sp, r7 + 8005c9a: bd80 pop {r7, pc} -08005c64 : +08005c9c : * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { - 8005c64: b580 push {r7, lr} - 8005c66: b084 sub sp, #16 - 8005c68: af00 add r7, sp, #0 - 8005c6a: 60f8 str r0, [r7, #12] - 8005c6c: 60b9 str r1, [r7, #8] - 8005c6e: 603b str r3, [r7, #0] - 8005c70: 4613 mov r3, r2 - 8005c72: 71fb strb r3, [r7, #7] + 8005c9c: b580 push {r7, lr} + 8005c9e: b084 sub sp, #16 + 8005ca0: af00 add r7, sp, #0 + 8005ca2: 60f8 str r0, [r7, #12] + 8005ca4: 60b9 str r1, [r7, #8] + 8005ca6: 603b str r3, [r7, #0] + 8005ca8: 4613 mov r3, r2 + 8005caa: 71fb strb r3, [r7, #7] /* Wait until flag is set */ while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) - 8005c74: e049 b.n 8005d0a + 8005cac: e049 b.n 8005d42 { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) - 8005c76: 69bb ldr r3, [r7, #24] - 8005c78: f1b3 3fff cmp.w r3, #4294967295 - 8005c7c: d045 beq.n 8005d0a + 8005cae: 69bb ldr r3, [r7, #24] + 8005cb0: f1b3 3fff cmp.w r3, #4294967295 + 8005cb4: d045 beq.n 8005d42 { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) - 8005c7e: f7fb fbbb bl 80013f8 - 8005c82: 4602 mov r2, r0 - 8005c84: 683b ldr r3, [r7, #0] - 8005c86: 1ad3 subs r3, r2, r3 - 8005c88: 69ba ldr r2, [r7, #24] - 8005c8a: 429a cmp r2, r3 - 8005c8c: d302 bcc.n 8005c94 - 8005c8e: 69bb ldr r3, [r7, #24] - 8005c90: 2b00 cmp r3, #0 - 8005c92: d101 bne.n 8005c98 + 8005cb6: f7fb fbbb bl 8001430 + 8005cba: 4602 mov r2, r0 + 8005cbc: 683b ldr r3, [r7, #0] + 8005cbe: 1ad3 subs r3, r2, r3 + 8005cc0: 69ba ldr r2, [r7, #24] + 8005cc2: 429a cmp r2, r3 + 8005cc4: d302 bcc.n 8005ccc + 8005cc6: 69bb ldr r3, [r7, #24] + 8005cc8: 2b00 cmp r3, #0 + 8005cca: d101 bne.n 8005cd0 { return HAL_TIMEOUT; - 8005c94: 2303 movs r3, #3 - 8005c96: e048 b.n 8005d2a + 8005ccc: 2303 movs r3, #3 + 8005cce: e048 b.n 8005d62 } if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) - 8005c98: 68fb ldr r3, [r7, #12] - 8005c9a: 681b ldr r3, [r3, #0] - 8005c9c: 681b ldr r3, [r3, #0] - 8005c9e: f003 0304 and.w r3, r3, #4 - 8005ca2: 2b00 cmp r3, #0 - 8005ca4: d031 beq.n 8005d0a + 8005cd0: 68fb ldr r3, [r7, #12] + 8005cd2: 681b ldr r3, [r3, #0] + 8005cd4: 681b ldr r3, [r3, #0] + 8005cd6: f003 0304 and.w r3, r3, #4 + 8005cda: 2b00 cmp r3, #0 + 8005cdc: d031 beq.n 8005d42 { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) - 8005ca6: 68fb ldr r3, [r7, #12] - 8005ca8: 681b ldr r3, [r3, #0] - 8005caa: 69db ldr r3, [r3, #28] - 8005cac: f003 0308 and.w r3, r3, #8 - 8005cb0: 2b08 cmp r3, #8 - 8005cb2: d110 bne.n 8005cd6 + 8005cde: 68fb ldr r3, [r7, #12] + 8005ce0: 681b ldr r3, [r3, #0] + 8005ce2: 69db ldr r3, [r3, #28] + 8005ce4: f003 0308 and.w r3, r3, #8 + 8005ce8: 2b08 cmp r3, #8 + 8005cea: d110 bne.n 8005d0e { /* Clear Overrun Error flag*/ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); - 8005cb4: 68fb ldr r3, [r7, #12] - 8005cb6: 681b ldr r3, [r3, #0] - 8005cb8: 2208 movs r2, #8 - 8005cba: 621a str r2, [r3, #32] + 8005cec: 68fb ldr r3, [r7, #12] + 8005cee: 681b ldr r3, [r3, #0] + 8005cf0: 2208 movs r2, #8 + 8005cf2: 621a str r2, [r3, #32] /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts if ongoing */ UART_EndRxTransfer(huart); - 8005cbc: 68f8 ldr r0, [r7, #12] - 8005cbe: f000 f838 bl 8005d32 + 8005cf4: 68f8 ldr r0, [r7, #12] + 8005cf6: f000 f838 bl 8005d6a huart->ErrorCode = HAL_UART_ERROR_ORE; - 8005cc2: 68fb ldr r3, [r7, #12] - 8005cc4: 2208 movs r2, #8 - 8005cc6: f8c3 2084 str.w r2, [r3, #132] @ 0x84 + 8005cfa: 68fb ldr r3, [r7, #12] + 8005cfc: 2208 movs r2, #8 + 8005cfe: f8c3 2084 str.w r2, [r3, #132] @ 0x84 /* Process Unlocked */ __HAL_UNLOCK(huart); - 8005cca: 68fb ldr r3, [r7, #12] - 8005ccc: 2200 movs r2, #0 - 8005cce: f883 2078 strb.w r2, [r3, #120] @ 0x78 + 8005d02: 68fb ldr r3, [r7, #12] + 8005d04: 2200 movs r2, #0 + 8005d06: f883 2078 strb.w r2, [r3, #120] @ 0x78 return HAL_ERROR; - 8005cd2: 2301 movs r3, #1 - 8005cd4: e029 b.n 8005d2a + 8005d0a: 2301 movs r3, #1 + 8005d0c: e029 b.n 8005d62 } if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) - 8005cd6: 68fb ldr r3, [r7, #12] - 8005cd8: 681b ldr r3, [r3, #0] - 8005cda: 69db ldr r3, [r3, #28] - 8005cdc: f403 6300 and.w r3, r3, #2048 @ 0x800 - 8005ce0: f5b3 6f00 cmp.w r3, #2048 @ 0x800 - 8005ce4: d111 bne.n 8005d0a + 8005d0e: 68fb ldr r3, [r7, #12] + 8005d10: 681b ldr r3, [r3, #0] + 8005d12: 69db ldr r3, [r3, #28] + 8005d14: f403 6300 and.w r3, r3, #2048 @ 0x800 + 8005d18: f5b3 6f00 cmp.w r3, #2048 @ 0x800 + 8005d1c: d111 bne.n 8005d42 { /* Clear Receiver Timeout flag*/ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); - 8005ce6: 68fb ldr r3, [r7, #12] - 8005ce8: 681b ldr r3, [r3, #0] - 8005cea: f44f 6200 mov.w r2, #2048 @ 0x800 - 8005cee: 621a str r2, [r3, #32] + 8005d1e: 68fb ldr r3, [r7, #12] + 8005d20: 681b ldr r3, [r3, #0] + 8005d22: f44f 6200 mov.w r2, #2048 @ 0x800 + 8005d26: 621a str r2, [r3, #32] /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts if ongoing */ UART_EndRxTransfer(huart); - 8005cf0: 68f8 ldr r0, [r7, #12] - 8005cf2: f000 f81e bl 8005d32 + 8005d28: 68f8 ldr r0, [r7, #12] + 8005d2a: f000 f81e bl 8005d6a huart->ErrorCode = HAL_UART_ERROR_RTO; - 8005cf6: 68fb ldr r3, [r7, #12] - 8005cf8: 2220 movs r2, #32 - 8005cfa: f8c3 2084 str.w r2, [r3, #132] @ 0x84 + 8005d2e: 68fb ldr r3, [r7, #12] + 8005d30: 2220 movs r2, #32 + 8005d32: f8c3 2084 str.w r2, [r3, #132] @ 0x84 /* Process Unlocked */ __HAL_UNLOCK(huart); - 8005cfe: 68fb ldr r3, [r7, #12] - 8005d00: 2200 movs r2, #0 - 8005d02: f883 2078 strb.w r2, [r3, #120] @ 0x78 + 8005d36: 68fb ldr r3, [r7, #12] + 8005d38: 2200 movs r2, #0 + 8005d3a: f883 2078 strb.w r2, [r3, #120] @ 0x78 return HAL_TIMEOUT; - 8005d06: 2303 movs r3, #3 - 8005d08: e00f b.n 8005d2a + 8005d3e: 2303 movs r3, #3 + 8005d40: e00f b.n 8005d62 while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) - 8005d0a: 68fb ldr r3, [r7, #12] - 8005d0c: 681b ldr r3, [r3, #0] - 8005d0e: 69da ldr r2, [r3, #28] - 8005d10: 68bb ldr r3, [r7, #8] - 8005d12: 4013 ands r3, r2 - 8005d14: 68ba ldr r2, [r7, #8] - 8005d16: 429a cmp r2, r3 - 8005d18: bf0c ite eq - 8005d1a: 2301 moveq r3, #1 - 8005d1c: 2300 movne r3, #0 - 8005d1e: b2db uxtb r3, r3 - 8005d20: 461a mov r2, r3 - 8005d22: 79fb ldrb r3, [r7, #7] - 8005d24: 429a cmp r2, r3 - 8005d26: d0a6 beq.n 8005c76 + 8005d42: 68fb ldr r3, [r7, #12] + 8005d44: 681b ldr r3, [r3, #0] + 8005d46: 69da ldr r2, [r3, #28] + 8005d48: 68bb ldr r3, [r7, #8] + 8005d4a: 4013 ands r3, r2 + 8005d4c: 68ba ldr r2, [r7, #8] + 8005d4e: 429a cmp r2, r3 + 8005d50: bf0c ite eq + 8005d52: 2301 moveq r3, #1 + 8005d54: 2300 movne r3, #0 + 8005d56: b2db uxtb r3, r3 + 8005d58: 461a mov r2, r3 + 8005d5a: 79fb ldrb r3, [r7, #7] + 8005d5c: 429a cmp r2, r3 + 8005d5e: d0a6 beq.n 8005cae } } } } return HAL_OK; - 8005d28: 2300 movs r3, #0 + 8005d60: 2300 movs r3, #0 } - 8005d2a: 4618 mov r0, r3 - 8005d2c: 3710 adds r7, #16 - 8005d2e: 46bd mov sp, r7 - 8005d30: bd80 pop {r7, pc} + 8005d62: 4618 mov r0, r3 + 8005d64: 3710 adds r7, #16 + 8005d66: 46bd mov sp, r7 + 8005d68: bd80 pop {r7, pc} -08005d32 : +08005d6a : * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). * @param huart UART handle. * @retval None */ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) { - 8005d32: b480 push {r7} - 8005d34: b095 sub sp, #84 @ 0x54 - 8005d36: af00 add r7, sp, #0 - 8005d38: 6078 str r0, [r7, #4] + 8005d6a: b480 push {r7} + 8005d6c: b095 sub sp, #84 @ 0x54 + 8005d6e: af00 add r7, sp, #0 + 8005d70: 6078 str r0, [r7, #4] /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); - 8005d3a: 687b ldr r3, [r7, #4] - 8005d3c: 681b ldr r3, [r3, #0] - 8005d3e: 637b str r3, [r7, #52] @ 0x34 + 8005d72: 687b ldr r3, [r7, #4] + 8005d74: 681b ldr r3, [r3, #0] + 8005d76: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 8005d40: 6b7b ldr r3, [r7, #52] @ 0x34 - 8005d42: e853 3f00 ldrex r3, [r3] - 8005d46: 633b str r3, [r7, #48] @ 0x30 + 8005d78: 6b7b ldr r3, [r7, #52] @ 0x34 + 8005d7a: e853 3f00 ldrex r3, [r3] + 8005d7e: 633b str r3, [r7, #48] @ 0x30 return(result); - 8005d48: 6b3b ldr r3, [r7, #48] @ 0x30 - 8005d4a: f423 7390 bic.w r3, r3, #288 @ 0x120 - 8005d4e: 64fb str r3, [r7, #76] @ 0x4c - 8005d50: 687b ldr r3, [r7, #4] - 8005d52: 681b ldr r3, [r3, #0] - 8005d54: 461a mov r2, r3 - 8005d56: 6cfb ldr r3, [r7, #76] @ 0x4c - 8005d58: 643b str r3, [r7, #64] @ 0x40 - 8005d5a: 63fa str r2, [r7, #60] @ 0x3c + 8005d80: 6b3b ldr r3, [r7, #48] @ 0x30 + 8005d82: f423 7390 bic.w r3, r3, #288 @ 0x120 + 8005d86: 64fb str r3, [r7, #76] @ 0x4c + 8005d88: 687b ldr r3, [r7, #4] + 8005d8a: 681b ldr r3, [r3, #0] + 8005d8c: 461a mov r2, r3 + 8005d8e: 6cfb ldr r3, [r7, #76] @ 0x4c + 8005d90: 643b str r3, [r7, #64] @ 0x40 + 8005d92: 63fa str r2, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 8005d5c: 6bf9 ldr r1, [r7, #60] @ 0x3c - 8005d5e: 6c3a ldr r2, [r7, #64] @ 0x40 - 8005d60: e841 2300 strex r3, r2, [r1] - 8005d64: 63bb str r3, [r7, #56] @ 0x38 + 8005d94: 6bf9 ldr r1, [r7, #60] @ 0x3c + 8005d96: 6c3a ldr r2, [r7, #64] @ 0x40 + 8005d98: e841 2300 strex r3, r2, [r1] + 8005d9c: 63bb str r3, [r7, #56] @ 0x38 return(result); - 8005d66: 6bbb ldr r3, [r7, #56] @ 0x38 - 8005d68: 2b00 cmp r3, #0 - 8005d6a: d1e6 bne.n 8005d3a + 8005d9e: 6bbb ldr r3, [r7, #56] @ 0x38 + 8005da0: 2b00 cmp r3, #0 + 8005da2: d1e6 bne.n 8005d72 ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - 8005d6c: 687b ldr r3, [r7, #4] - 8005d6e: 681b ldr r3, [r3, #0] - 8005d70: 3308 adds r3, #8 - 8005d72: 623b str r3, [r7, #32] + 8005da4: 687b ldr r3, [r7, #4] + 8005da6: 681b ldr r3, [r3, #0] + 8005da8: 3308 adds r3, #8 + 8005daa: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 8005d74: 6a3b ldr r3, [r7, #32] - 8005d76: e853 3f00 ldrex r3, [r3] - 8005d7a: 61fb str r3, [r7, #28] + 8005dac: 6a3b ldr r3, [r7, #32] + 8005dae: e853 3f00 ldrex r3, [r3] + 8005db2: 61fb str r3, [r7, #28] return(result); - 8005d7c: 69fb ldr r3, [r7, #28] - 8005d7e: f023 0301 bic.w r3, r3, #1 - 8005d82: 64bb str r3, [r7, #72] @ 0x48 - 8005d84: 687b ldr r3, [r7, #4] - 8005d86: 681b ldr r3, [r3, #0] - 8005d88: 3308 adds r3, #8 - 8005d8a: 6cba ldr r2, [r7, #72] @ 0x48 - 8005d8c: 62fa str r2, [r7, #44] @ 0x2c - 8005d8e: 62bb str r3, [r7, #40] @ 0x28 + 8005db4: 69fb ldr r3, [r7, #28] + 8005db6: f023 0301 bic.w r3, r3, #1 + 8005dba: 64bb str r3, [r7, #72] @ 0x48 + 8005dbc: 687b ldr r3, [r7, #4] + 8005dbe: 681b ldr r3, [r3, #0] + 8005dc0: 3308 adds r3, #8 + 8005dc2: 6cba ldr r2, [r7, #72] @ 0x48 + 8005dc4: 62fa str r2, [r7, #44] @ 0x2c + 8005dc6: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 8005d90: 6ab9 ldr r1, [r7, #40] @ 0x28 - 8005d92: 6afa ldr r2, [r7, #44] @ 0x2c - 8005d94: e841 2300 strex r3, r2, [r1] - 8005d98: 627b str r3, [r7, #36] @ 0x24 + 8005dc8: 6ab9 ldr r1, [r7, #40] @ 0x28 + 8005dca: 6afa ldr r2, [r7, #44] @ 0x2c + 8005dcc: e841 2300 strex r3, r2, [r1] + 8005dd0: 627b str r3, [r7, #36] @ 0x24 return(result); - 8005d9a: 6a7b ldr r3, [r7, #36] @ 0x24 - 8005d9c: 2b00 cmp r3, #0 - 8005d9e: d1e5 bne.n 8005d6c + 8005dd2: 6a7b ldr r3, [r7, #36] @ 0x24 + 8005dd4: 2b00 cmp r3, #0 + 8005dd6: d1e5 bne.n 8005da4 /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - 8005da0: 687b ldr r3, [r7, #4] - 8005da2: 6e1b ldr r3, [r3, #96] @ 0x60 - 8005da4: 2b01 cmp r3, #1 - 8005da6: d118 bne.n 8005dda + 8005dd8: 687b ldr r3, [r7, #4] + 8005dda: 6e1b ldr r3, [r3, #96] @ 0x60 + 8005ddc: 2b01 cmp r3, #1 + 8005dde: d118 bne.n 8005e12 { ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); - 8005da8: 687b ldr r3, [r7, #4] - 8005daa: 681b ldr r3, [r3, #0] - 8005dac: 60fb str r3, [r7, #12] + 8005de0: 687b ldr r3, [r7, #4] + 8005de2: 681b ldr r3, [r3, #0] + 8005de4: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 8005dae: 68fb ldr r3, [r7, #12] - 8005db0: e853 3f00 ldrex r3, [r3] - 8005db4: 60bb str r3, [r7, #8] + 8005de6: 68fb ldr r3, [r7, #12] + 8005de8: e853 3f00 ldrex r3, [r3] + 8005dec: 60bb str r3, [r7, #8] return(result); - 8005db6: 68bb ldr r3, [r7, #8] - 8005db8: f023 0310 bic.w r3, r3, #16 - 8005dbc: 647b str r3, [r7, #68] @ 0x44 - 8005dbe: 687b ldr r3, [r7, #4] - 8005dc0: 681b ldr r3, [r3, #0] - 8005dc2: 461a mov r2, r3 - 8005dc4: 6c7b ldr r3, [r7, #68] @ 0x44 - 8005dc6: 61bb str r3, [r7, #24] - 8005dc8: 617a str r2, [r7, #20] + 8005dee: 68bb ldr r3, [r7, #8] + 8005df0: f023 0310 bic.w r3, r3, #16 + 8005df4: 647b str r3, [r7, #68] @ 0x44 + 8005df6: 687b ldr r3, [r7, #4] + 8005df8: 681b ldr r3, [r3, #0] + 8005dfa: 461a mov r2, r3 + 8005dfc: 6c7b ldr r3, [r7, #68] @ 0x44 + 8005dfe: 61bb str r3, [r7, #24] + 8005e00: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 8005dca: 6979 ldr r1, [r7, #20] - 8005dcc: 69ba ldr r2, [r7, #24] - 8005dce: e841 2300 strex r3, r2, [r1] - 8005dd2: 613b str r3, [r7, #16] + 8005e02: 6979 ldr r1, [r7, #20] + 8005e04: 69ba ldr r2, [r7, #24] + 8005e06: e841 2300 strex r3, r2, [r1] + 8005e0a: 613b str r3, [r7, #16] return(result); - 8005dd4: 693b ldr r3, [r7, #16] - 8005dd6: 2b00 cmp r3, #0 - 8005dd8: d1e6 bne.n 8005da8 + 8005e0c: 693b ldr r3, [r7, #16] + 8005e0e: 2b00 cmp r3, #0 + 8005e10: d1e6 bne.n 8005de0 } /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; - 8005dda: 687b ldr r3, [r7, #4] - 8005ddc: 2220 movs r2, #32 - 8005dde: f8c3 2080 str.w r2, [r3, #128] @ 0x80 + 8005e12: 687b ldr r3, [r7, #4] + 8005e14: 2220 movs r2, #32 + 8005e16: f8c3 2080 str.w r2, [r3, #128] @ 0x80 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - 8005de2: 687b ldr r3, [r7, #4] - 8005de4: 2200 movs r2, #0 - 8005de6: 661a str r2, [r3, #96] @ 0x60 + 8005e1a: 687b ldr r3, [r7, #4] + 8005e1c: 2200 movs r2, #0 + 8005e1e: 661a str r2, [r3, #96] @ 0x60 /* Reset RxIsr function pointer */ huart->RxISR = NULL; - 8005de8: 687b ldr r3, [r7, #4] - 8005dea: 2200 movs r2, #0 - 8005dec: 669a str r2, [r3, #104] @ 0x68 + 8005e20: 687b ldr r3, [r7, #4] + 8005e22: 2200 movs r2, #0 + 8005e24: 669a str r2, [r3, #104] @ 0x68 } - 8005dee: bf00 nop - 8005df0: 3754 adds r7, #84 @ 0x54 - 8005df2: 46bd mov sp, r7 - 8005df4: f85d 7b04 ldr.w r7, [sp], #4 - 8005df8: 4770 bx lr + 8005e26: bf00 nop + 8005e28: 3754 adds r7, #84 @ 0x54 + 8005e2a: 46bd mov sp, r7 + 8005e2c: f85d 7b04 ldr.w r7, [sp], #4 + 8005e30: 4770 bx lr -08005dfa : - 8005dfa: 4402 add r2, r0 - 8005dfc: 4603 mov r3, r0 - 8005dfe: 4293 cmp r3, r2 - 8005e00: d100 bne.n 8005e04 - 8005e02: 4770 bx lr - 8005e04: f803 1b01 strb.w r1, [r3], #1 - 8005e08: e7f9 b.n 8005dfe +08005e32 : + 8005e32: 4402 add r2, r0 + 8005e34: 4603 mov r3, r0 + 8005e36: 4293 cmp r3, r2 + 8005e38: d100 bne.n 8005e3c + 8005e3a: 4770 bx lr + 8005e3c: f803 1b01 strb.w r1, [r3], #1 + 8005e40: e7f9 b.n 8005e36 ... -08005e0c <__libc_init_array>: - 8005e0c: b570 push {r4, r5, r6, lr} - 8005e0e: 4d0d ldr r5, [pc, #52] @ (8005e44 <__libc_init_array+0x38>) - 8005e10: 4c0d ldr r4, [pc, #52] @ (8005e48 <__libc_init_array+0x3c>) - 8005e12: 1b64 subs r4, r4, r5 - 8005e14: 10a4 asrs r4, r4, #2 - 8005e16: 2600 movs r6, #0 - 8005e18: 42a6 cmp r6, r4 - 8005e1a: d109 bne.n 8005e30 <__libc_init_array+0x24> - 8005e1c: 4d0b ldr r5, [pc, #44] @ (8005e4c <__libc_init_array+0x40>) - 8005e1e: 4c0c ldr r4, [pc, #48] @ (8005e50 <__libc_init_array+0x44>) - 8005e20: f000 f818 bl 8005e54 <_init> - 8005e24: 1b64 subs r4, r4, r5 - 8005e26: 10a4 asrs r4, r4, #2 - 8005e28: 2600 movs r6, #0 - 8005e2a: 42a6 cmp r6, r4 - 8005e2c: d105 bne.n 8005e3a <__libc_init_array+0x2e> - 8005e2e: bd70 pop {r4, r5, r6, pc} - 8005e30: f855 3b04 ldr.w r3, [r5], #4 - 8005e34: 4798 blx r3 - 8005e36: 3601 adds r6, #1 - 8005e38: e7ee b.n 8005e18 <__libc_init_array+0xc> - 8005e3a: f855 3b04 ldr.w r3, [r5], #4 - 8005e3e: 4798 blx r3 - 8005e40: 3601 adds r6, #1 - 8005e42: e7f2 b.n 8005e2a <__libc_init_array+0x1e> - 8005e44: 08005ea4 .word 0x08005ea4 - 8005e48: 08005ea4 .word 0x08005ea4 - 8005e4c: 08005ea4 .word 0x08005ea4 - 8005e50: 08005ea8 .word 0x08005ea8 +08005e44 <__libc_init_array>: + 8005e44: b570 push {r4, r5, r6, lr} + 8005e46: 4d0d ldr r5, [pc, #52] @ (8005e7c <__libc_init_array+0x38>) + 8005e48: 4c0d ldr r4, [pc, #52] @ (8005e80 <__libc_init_array+0x3c>) + 8005e4a: 1b64 subs r4, r4, r5 + 8005e4c: 10a4 asrs r4, r4, #2 + 8005e4e: 2600 movs r6, #0 + 8005e50: 42a6 cmp r6, r4 + 8005e52: d109 bne.n 8005e68 <__libc_init_array+0x24> + 8005e54: 4d0b ldr r5, [pc, #44] @ (8005e84 <__libc_init_array+0x40>) + 8005e56: 4c0c ldr r4, [pc, #48] @ (8005e88 <__libc_init_array+0x44>) + 8005e58: f000 f818 bl 8005e8c <_init> + 8005e5c: 1b64 subs r4, r4, r5 + 8005e5e: 10a4 asrs r4, r4, #2 + 8005e60: 2600 movs r6, #0 + 8005e62: 42a6 cmp r6, r4 + 8005e64: d105 bne.n 8005e72 <__libc_init_array+0x2e> + 8005e66: bd70 pop {r4, r5, r6, pc} + 8005e68: f855 3b04 ldr.w r3, [r5], #4 + 8005e6c: 4798 blx r3 + 8005e6e: 3601 adds r6, #1 + 8005e70: e7ee b.n 8005e50 <__libc_init_array+0xc> + 8005e72: f855 3b04 ldr.w r3, [r5], #4 + 8005e76: 4798 blx r3 + 8005e78: 3601 adds r6, #1 + 8005e7a: e7f2 b.n 8005e62 <__libc_init_array+0x1e> + 8005e7c: 08005edc .word 0x08005edc + 8005e80: 08005edc .word 0x08005edc + 8005e84: 08005edc .word 0x08005edc + 8005e88: 08005ee0 .word 0x08005ee0 -08005e54 <_init>: - 8005e54: b5f8 push {r3, r4, r5, r6, r7, lr} - 8005e56: bf00 nop - 8005e58: bcf8 pop {r3, r4, r5, r6, r7} - 8005e5a: bc08 pop {r3} - 8005e5c: 469e mov lr, r3 - 8005e5e: 4770 bx lr +08005e8c <_init>: + 8005e8c: b5f8 push {r3, r4, r5, r6, r7, lr} + 8005e8e: bf00 nop + 8005e90: bcf8 pop {r3, r4, r5, r6, r7} + 8005e92: bc08 pop {r3} + 8005e94: 469e mov lr, r3 + 8005e96: 4770 bx lr -08005e60 <_fini>: - 8005e60: b5f8 push {r3, r4, r5, r6, r7, lr} - 8005e62: bf00 nop - 8005e64: bcf8 pop {r3, r4, r5, r6, r7} - 8005e66: bc08 pop {r3} - 8005e68: 469e mov lr, r3 - 8005e6a: 4770 bx lr +08005e98 <_fini>: + 8005e98: b5f8 push {r3, r4, r5, r6, r7, lr} + 8005e9a: bf00 nop + 8005e9c: bcf8 pop {r3, r4, r5, r6, r7} + 8005e9e: bc08 pop {r3} + 8005ea0: 469e mov lr, r3 + 8005ea2: 4770 bx lr diff --git a/Software/Code/Debug/PDU_FT25.map b/Software/Code/Debug/PDU_FT25.map index 781c93c..8ee6011 100644 --- a/Software/Code/Debug/PDU_FT25.map +++ b/Software/Code/Debug/PDU_FT25.map @@ -4132,7 +4132,7 @@ LOAD C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.ext 0x08000000 g_pfnVectors 0x08000188 . = ALIGN (0x4) -.text 0x08000188 0x5ce4 +.text 0x08000188 0x5d1c 0x08000188 . = ALIGN (0x4) *(.text) .text 0x08000188 0x40 C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.1.0.202410251130/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+fp/hard/crtbegin.o @@ -4165,462 +4165,462 @@ LOAD C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.ext .text.ChannelControl_UpdateGPIOs 0x08000458 0x1b4 ./Core/Src/channel_control.o 0x08000458 ChannelControl_UpdateGPIOs - .text.main 0x0800060c 0x180 ./Core/Src/main.o + .text.main 0x0800060c 0x1b8 ./Core/Src/main.o 0x0800060c main .text.SystemClock_Config - 0x0800078c 0xb8 ./Core/Src/main.o - 0x0800078c SystemClock_Config + 0x080007c4 0xb8 ./Core/Src/main.o + 0x080007c4 SystemClock_Config .text.MX_ADC1_Init - 0x08000844 0x190 ./Core/Src/main.o + 0x0800087c 0x190 ./Core/Src/main.o .text.MX_ADC2_Init - 0x080009d4 0x138 ./Core/Src/main.o + 0x08000a0c 0x138 ./Core/Src/main.o .text.MX_CAN_Init - 0x08000b0c 0x6c ./Core/Src/main.o + 0x08000b44 0x6c ./Core/Src/main.o .text.MX_TIM6_Init - 0x08000b78 0x70 ./Core/Src/main.o + 0x08000bb0 0x70 ./Core/Src/main.o .text.MX_UART4_Init - 0x08000be8 0x60 ./Core/Src/main.o + 0x08000c20 0x60 ./Core/Src/main.o .text.MX_DMA_Init - 0x08000c48 0x64 ./Core/Src/main.o + 0x08000c80 0x64 ./Core/Src/main.o .text.MX_GPIO_Init - 0x08000cac 0x10c ./Core/Src/main.o + 0x08000ce4 0x10c ./Core/Src/main.o .text.Error_Handler - 0x08000db8 0xc ./Core/Src/main.o - 0x08000db8 Error_Handler + 0x08000df0 0xc ./Core/Src/main.o + 0x08000df0 Error_Handler .text.HAL_MspInit - 0x08000dc4 0x48 ./Core/Src/stm32f3xx_hal_msp.o - 0x08000dc4 HAL_MspInit + 0x08000dfc 0x48 ./Core/Src/stm32f3xx_hal_msp.o + 0x08000dfc HAL_MspInit .text.HAL_ADC_MspInit - 0x08000e0c 0x264 ./Core/Src/stm32f3xx_hal_msp.o - 0x08000e0c HAL_ADC_MspInit + 0x08000e44 0x264 ./Core/Src/stm32f3xx_hal_msp.o + 0x08000e44 HAL_ADC_MspInit .text.HAL_CAN_MspInit - 0x08001070 0xa8 ./Core/Src/stm32f3xx_hal_msp.o - 0x08001070 HAL_CAN_MspInit + 0x080010a8 0xa8 ./Core/Src/stm32f3xx_hal_msp.o + 0x080010a8 HAL_CAN_MspInit .text.HAL_TIM_Base_MspInit - 0x08001118 0x4c ./Core/Src/stm32f3xx_hal_msp.o - 0x08001118 HAL_TIM_Base_MspInit + 0x08001150 0x4c ./Core/Src/stm32f3xx_hal_msp.o + 0x08001150 HAL_TIM_Base_MspInit .text.HAL_UART_MspInit - 0x08001164 0x88 ./Core/Src/stm32f3xx_hal_msp.o - 0x08001164 HAL_UART_MspInit + 0x0800119c 0x88 ./Core/Src/stm32f3xx_hal_msp.o + 0x0800119c HAL_UART_MspInit .text.NMI_Handler - 0x080011ec 0x8 ./Core/Src/stm32f3xx_it.o - 0x080011ec NMI_Handler + 0x08001224 0x8 ./Core/Src/stm32f3xx_it.o + 0x08001224 NMI_Handler .text.HardFault_Handler - 0x080011f4 0x8 ./Core/Src/stm32f3xx_it.o - 0x080011f4 HardFault_Handler + 0x0800122c 0x8 ./Core/Src/stm32f3xx_it.o + 0x0800122c HardFault_Handler .text.MemManage_Handler - 0x080011fc 0x8 ./Core/Src/stm32f3xx_it.o - 0x080011fc MemManage_Handler + 0x08001234 0x8 ./Core/Src/stm32f3xx_it.o + 0x08001234 MemManage_Handler .text.BusFault_Handler - 0x08001204 0x8 ./Core/Src/stm32f3xx_it.o - 0x08001204 BusFault_Handler + 0x0800123c 0x8 ./Core/Src/stm32f3xx_it.o + 0x0800123c BusFault_Handler .text.UsageFault_Handler - 0x0800120c 0x8 ./Core/Src/stm32f3xx_it.o - 0x0800120c UsageFault_Handler + 0x08001244 0x8 ./Core/Src/stm32f3xx_it.o + 0x08001244 UsageFault_Handler .text.SVC_Handler - 0x08001214 0xe ./Core/Src/stm32f3xx_it.o - 0x08001214 SVC_Handler + 0x0800124c 0xe ./Core/Src/stm32f3xx_it.o + 0x0800124c SVC_Handler .text.DebugMon_Handler - 0x08001222 0xe ./Core/Src/stm32f3xx_it.o - 0x08001222 DebugMon_Handler + 0x0800125a 0xe ./Core/Src/stm32f3xx_it.o + 0x0800125a DebugMon_Handler .text.PendSV_Handler - 0x08001230 0xe ./Core/Src/stm32f3xx_it.o - 0x08001230 PendSV_Handler + 0x08001268 0xe ./Core/Src/stm32f3xx_it.o + 0x08001268 PendSV_Handler .text.SysTick_Handler - 0x0800123e 0xc ./Core/Src/stm32f3xx_it.o - 0x0800123e SysTick_Handler - *fill* 0x0800124a 0x2 + 0x08001276 0xc ./Core/Src/stm32f3xx_it.o + 0x08001276 SysTick_Handler + *fill* 0x08001282 0x2 .text.DMA1_Channel1_IRQHandler - 0x0800124c 0x14 ./Core/Src/stm32f3xx_it.o - 0x0800124c DMA1_Channel1_IRQHandler + 0x08001284 0x14 ./Core/Src/stm32f3xx_it.o + 0x08001284 DMA1_Channel1_IRQHandler .text.ADC1_2_IRQHandler - 0x08001260 0x1c ./Core/Src/stm32f3xx_it.o - 0x08001260 ADC1_2_IRQHandler + 0x08001298 0x1c ./Core/Src/stm32f3xx_it.o + 0x08001298 ADC1_2_IRQHandler .text.USB_LP_CAN_RX0_IRQHandler - 0x0800127c 0x14 ./Core/Src/stm32f3xx_it.o - 0x0800127c USB_LP_CAN_RX0_IRQHandler + 0x080012b4 0x14 ./Core/Src/stm32f3xx_it.o + 0x080012b4 USB_LP_CAN_RX0_IRQHandler .text.CAN_RX1_IRQHandler - 0x08001290 0x14 ./Core/Src/stm32f3xx_it.o - 0x08001290 CAN_RX1_IRQHandler + 0x080012c8 0x14 ./Core/Src/stm32f3xx_it.o + 0x080012c8 CAN_RX1_IRQHandler .text.TIM6_DAC_IRQHandler - 0x080012a4 0x14 ./Core/Src/stm32f3xx_it.o - 0x080012a4 TIM6_DAC_IRQHandler + 0x080012dc 0x14 ./Core/Src/stm32f3xx_it.o + 0x080012dc TIM6_DAC_IRQHandler .text.DMA2_Channel1_IRQHandler - 0x080012b8 0x14 ./Core/Src/stm32f3xx_it.o - 0x080012b8 DMA2_Channel1_IRQHandler + 0x080012f0 0x14 ./Core/Src/stm32f3xx_it.o + 0x080012f0 DMA2_Channel1_IRQHandler .text.SystemInit - 0x080012cc 0x24 ./Core/Src/system_stm32f3xx.o - 0x080012cc SystemInit + 0x08001304 0x24 ./Core/Src/system_stm32f3xx.o + 0x08001304 SystemInit .text.Reset_Handler - 0x080012f0 0x50 ./Core/Startup/startup_stm32f302rbtx.o - 0x080012f0 Reset_Handler + 0x08001328 0x50 ./Core/Startup/startup_stm32f302rbtx.o + 0x08001328 Reset_Handler .text.Default_Handler - 0x08001340 0x2 ./Core/Startup/startup_stm32f302rbtx.o - 0x08001340 RTC_Alarm_IRQHandler - 0x08001340 TIM1_CC_IRQHandler - 0x08001340 USB_HP_IRQHandler - 0x08001340 PVD_IRQHandler - 0x08001340 TAMP_STAMP_IRQHandler - 0x08001340 EXTI3_IRQHandler - 0x08001340 USB_HP_CAN_TX_IRQHandler - 0x08001340 EXTI0_IRQHandler - 0x08001340 I2C2_EV_IRQHandler - 0x08001340 FPU_IRQHandler - 0x08001340 TIM1_UP_TIM16_IRQHandler - 0x08001340 SPI1_IRQHandler - 0x08001340 CAN_SCE_IRQHandler - 0x08001340 DMA2_Channel2_IRQHandler - 0x08001340 DMA1_Channel4_IRQHandler - 0x08001340 USART3_IRQHandler - 0x08001340 DMA1_Channel7_IRQHandler - 0x08001340 UART5_IRQHandler - 0x08001340 TIM4_IRQHandler - 0x08001340 I2C1_EV_IRQHandler - 0x08001340 DMA1_Channel6_IRQHandler - 0x08001340 UART4_IRQHandler - 0x08001340 DMA2_Channel4_IRQHandler - 0x08001340 TIM3_IRQHandler - 0x08001340 RCC_IRQHandler - 0x08001340 Default_Handler - 0x08001340 USBWakeUp_RMP_IRQHandler - 0x08001340 EXTI15_10_IRQHandler - 0x08001340 EXTI9_5_IRQHandler - 0x08001340 RTC_WKUP_IRQHandler - 0x08001340 SPI2_IRQHandler - 0x08001340 DMA2_Channel5_IRQHandler - 0x08001340 DMA1_Channel5_IRQHandler - 0x08001340 USB_LP_IRQHandler - 0x08001340 EXTI4_IRQHandler - 0x08001340 COMP1_2_IRQHandler - 0x08001340 TIM1_TRG_COM_TIM17_IRQHandler - 0x08001340 DMA1_Channel3_IRQHandler - 0x08001340 WWDG_IRQHandler - 0x08001340 TIM2_IRQHandler - 0x08001340 EXTI1_IRQHandler - 0x08001340 COMP4_6_IRQHandler - 0x08001340 USART2_IRQHandler - 0x08001340 I2C2_ER_IRQHandler - 0x08001340 DMA1_Channel2_IRQHandler - 0x08001340 FLASH_IRQHandler - 0x08001340 USART1_IRQHandler - 0x08001340 SPI3_IRQHandler - 0x08001340 I2C1_ER_IRQHandler - 0x08001340 USBWakeUp_IRQHandler - 0x08001340 DMA2_Channel3_IRQHandler - 0x08001340 EXTI2_TSC_IRQHandler - 0x08001340 TIM1_BRK_TIM15_IRQHandler - *fill* 0x08001342 0x2 + 0x08001378 0x2 ./Core/Startup/startup_stm32f302rbtx.o + 0x08001378 RTC_Alarm_IRQHandler + 0x08001378 TIM1_CC_IRQHandler + 0x08001378 USB_HP_IRQHandler + 0x08001378 PVD_IRQHandler + 0x08001378 TAMP_STAMP_IRQHandler + 0x08001378 EXTI3_IRQHandler + 0x08001378 USB_HP_CAN_TX_IRQHandler + 0x08001378 EXTI0_IRQHandler + 0x08001378 I2C2_EV_IRQHandler + 0x08001378 FPU_IRQHandler + 0x08001378 TIM1_UP_TIM16_IRQHandler + 0x08001378 SPI1_IRQHandler + 0x08001378 CAN_SCE_IRQHandler + 0x08001378 DMA2_Channel2_IRQHandler + 0x08001378 DMA1_Channel4_IRQHandler + 0x08001378 USART3_IRQHandler + 0x08001378 DMA1_Channel7_IRQHandler + 0x08001378 UART5_IRQHandler + 0x08001378 TIM4_IRQHandler + 0x08001378 I2C1_EV_IRQHandler + 0x08001378 DMA1_Channel6_IRQHandler + 0x08001378 UART4_IRQHandler + 0x08001378 DMA2_Channel4_IRQHandler + 0x08001378 TIM3_IRQHandler + 0x08001378 RCC_IRQHandler + 0x08001378 Default_Handler + 0x08001378 USBWakeUp_RMP_IRQHandler + 0x08001378 EXTI15_10_IRQHandler + 0x08001378 EXTI9_5_IRQHandler + 0x08001378 RTC_WKUP_IRQHandler + 0x08001378 SPI2_IRQHandler + 0x08001378 DMA2_Channel5_IRQHandler + 0x08001378 DMA1_Channel5_IRQHandler + 0x08001378 USB_LP_IRQHandler + 0x08001378 EXTI4_IRQHandler + 0x08001378 COMP1_2_IRQHandler + 0x08001378 TIM1_TRG_COM_TIM17_IRQHandler + 0x08001378 DMA1_Channel3_IRQHandler + 0x08001378 WWDG_IRQHandler + 0x08001378 TIM2_IRQHandler + 0x08001378 EXTI1_IRQHandler + 0x08001378 COMP4_6_IRQHandler + 0x08001378 USART2_IRQHandler + 0x08001378 I2C2_ER_IRQHandler + 0x08001378 DMA1_Channel2_IRQHandler + 0x08001378 FLASH_IRQHandler + 0x08001378 USART1_IRQHandler + 0x08001378 SPI3_IRQHandler + 0x08001378 I2C1_ER_IRQHandler + 0x08001378 USBWakeUp_IRQHandler + 0x08001378 DMA2_Channel3_IRQHandler + 0x08001378 EXTI2_TSC_IRQHandler + 0x08001378 TIM1_BRK_TIM15_IRQHandler + *fill* 0x0800137a 0x2 .text.HAL_Init - 0x08001344 0x2c ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.o - 0x08001344 HAL_Init + 0x0800137c 0x2c ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.o + 0x0800137c HAL_Init .text.HAL_InitTick - 0x08001370 0x60 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.o - 0x08001370 HAL_InitTick + 0x080013a8 0x60 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.o + 0x080013a8 HAL_InitTick .text.HAL_IncTick - 0x080013d0 0x28 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.o - 0x080013d0 HAL_IncTick + 0x08001408 0x28 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.o + 0x08001408 HAL_IncTick .text.HAL_GetTick - 0x080013f8 0x18 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.o - 0x080013f8 HAL_GetTick + 0x08001430 0x18 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.o + 0x08001430 HAL_GetTick .text.HAL_Delay - 0x08001410 0x48 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.o - 0x08001410 HAL_Delay + 0x08001448 0x48 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.o + 0x08001448 HAL_Delay .text.HAL_ADC_ConvCpltCallback - 0x08001458 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.o - 0x08001458 HAL_ADC_ConvCpltCallback + 0x08001490 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.o + 0x08001490 HAL_ADC_ConvCpltCallback .text.HAL_ADC_LevelOutOfWindowCallback - 0x0800146c 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.o - 0x0800146c HAL_ADC_LevelOutOfWindowCallback + 0x080014a4 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.o + 0x080014a4 HAL_ADC_LevelOutOfWindowCallback .text.HAL_ADC_ErrorCallback - 0x08001480 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.o - 0x08001480 HAL_ADC_ErrorCallback + 0x080014b8 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.o + 0x080014b8 HAL_ADC_ErrorCallback .text.HAL_ADC_Init - 0x08001494 0x324 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.o - 0x08001494 HAL_ADC_Init + 0x080014cc 0x324 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.o + 0x080014cc HAL_ADC_Init .text.HAL_ADC_IRQHandler - 0x080017b8 0x3f4 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.o - 0x080017b8 HAL_ADC_IRQHandler + 0x080017f0 0x3f4 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.o + 0x080017f0 HAL_ADC_IRQHandler .text.HAL_ADCEx_InjectedConvCpltCallback - 0x08001bac 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.o - 0x08001bac HAL_ADCEx_InjectedConvCpltCallback + 0x08001be4 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.o + 0x08001be4 HAL_ADCEx_InjectedConvCpltCallback .text.HAL_ADCEx_InjectedQueueOverflowCallback - 0x08001bc0 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.o - 0x08001bc0 HAL_ADCEx_InjectedQueueOverflowCallback + 0x08001bf8 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.o + 0x08001bf8 HAL_ADCEx_InjectedQueueOverflowCallback .text.HAL_ADCEx_LevelOutOfWindow2Callback - 0x08001bd4 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.o - 0x08001bd4 HAL_ADCEx_LevelOutOfWindow2Callback + 0x08001c0c 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.o + 0x08001c0c HAL_ADCEx_LevelOutOfWindow2Callback .text.HAL_ADCEx_LevelOutOfWindow3Callback - 0x08001be8 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.o - 0x08001be8 HAL_ADCEx_LevelOutOfWindow3Callback + 0x08001c20 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.o + 0x08001c20 HAL_ADCEx_LevelOutOfWindow3Callback .text.HAL_ADC_ConfigChannel - 0x08001bfc 0x57c ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.o - 0x08001bfc HAL_ADC_ConfigChannel + 0x08001c34 0x57c ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.o + 0x08001c34 HAL_ADC_ConfigChannel .text.HAL_ADCEx_MultiModeConfigChannel - 0x08002178 0x18c ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.o - 0x08002178 HAL_ADCEx_MultiModeConfigChannel + 0x080021b0 0x18c ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.o + 0x080021b0 HAL_ADCEx_MultiModeConfigChannel .text.ADC_Disable - 0x08002304 0xcc ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.o + 0x0800233c 0xcc ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.o .text.HAL_CAN_Init - 0x080023d0 0x1f6 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o - 0x080023d0 HAL_CAN_Init + 0x08002408 0x1f6 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o + 0x08002408 HAL_CAN_Init .text.HAL_CAN_ConfigFilter - 0x080025c6 0x194 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o - 0x080025c6 HAL_CAN_ConfigFilter + 0x080025fe 0x194 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o + 0x080025fe HAL_CAN_ConfigFilter .text.HAL_CAN_Start - 0x0800275a 0x88 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o - 0x0800275a HAL_CAN_Start + 0x08002792 0x88 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o + 0x08002792 HAL_CAN_Start .text.HAL_CAN_AddTxMessage - 0x080027e2 0x1a0 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o - 0x080027e2 HAL_CAN_AddTxMessage + 0x0800281a 0x1a0 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o + 0x0800281a HAL_CAN_AddTxMessage .text.HAL_CAN_GetRxMessage - 0x08002982 0x244 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o - 0x08002982 HAL_CAN_GetRxMessage + 0x080029ba 0x244 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o + 0x080029ba HAL_CAN_GetRxMessage .text.HAL_CAN_ActivateNotification - 0x08002bc6 0x4c ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o - 0x08002bc6 HAL_CAN_ActivateNotification + 0x08002bfe 0x4c ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o + 0x08002bfe HAL_CAN_ActivateNotification .text.HAL_CAN_IRQHandler - 0x08002c12 0x36e ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o - 0x08002c12 HAL_CAN_IRQHandler + 0x08002c4a 0x36e ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o + 0x08002c4a HAL_CAN_IRQHandler .text.HAL_CAN_TxMailbox0CompleteCallback - 0x08002f80 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o - 0x08002f80 HAL_CAN_TxMailbox0CompleteCallback + 0x08002fb8 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o + 0x08002fb8 HAL_CAN_TxMailbox0CompleteCallback .text.HAL_CAN_TxMailbox1CompleteCallback - 0x08002f94 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o - 0x08002f94 HAL_CAN_TxMailbox1CompleteCallback + 0x08002fcc 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o + 0x08002fcc HAL_CAN_TxMailbox1CompleteCallback .text.HAL_CAN_TxMailbox2CompleteCallback - 0x08002fa8 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o - 0x08002fa8 HAL_CAN_TxMailbox2CompleteCallback + 0x08002fe0 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o + 0x08002fe0 HAL_CAN_TxMailbox2CompleteCallback .text.HAL_CAN_TxMailbox0AbortCallback - 0x08002fbc 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o - 0x08002fbc HAL_CAN_TxMailbox0AbortCallback + 0x08002ff4 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o + 0x08002ff4 HAL_CAN_TxMailbox0AbortCallback .text.HAL_CAN_TxMailbox1AbortCallback - 0x08002fd0 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o - 0x08002fd0 HAL_CAN_TxMailbox1AbortCallback + 0x08003008 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o + 0x08003008 HAL_CAN_TxMailbox1AbortCallback .text.HAL_CAN_TxMailbox2AbortCallback - 0x08002fe4 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o - 0x08002fe4 HAL_CAN_TxMailbox2AbortCallback + 0x0800301c 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o + 0x0800301c HAL_CAN_TxMailbox2AbortCallback .text.HAL_CAN_RxFifo0FullCallback - 0x08002ff8 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o - 0x08002ff8 HAL_CAN_RxFifo0FullCallback + 0x08003030 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o + 0x08003030 HAL_CAN_RxFifo0FullCallback .text.HAL_CAN_RxFifo1MsgPendingCallback - 0x0800300c 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o - 0x0800300c HAL_CAN_RxFifo1MsgPendingCallback + 0x08003044 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o + 0x08003044 HAL_CAN_RxFifo1MsgPendingCallback .text.HAL_CAN_RxFifo1FullCallback - 0x08003020 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o - 0x08003020 HAL_CAN_RxFifo1FullCallback + 0x08003058 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o + 0x08003058 HAL_CAN_RxFifo1FullCallback .text.HAL_CAN_SleepCallback - 0x08003034 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o - 0x08003034 HAL_CAN_SleepCallback + 0x0800306c 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o + 0x0800306c HAL_CAN_SleepCallback .text.HAL_CAN_WakeUpFromRxMsgCallback - 0x08003048 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o - 0x08003048 HAL_CAN_WakeUpFromRxMsgCallback + 0x08003080 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o + 0x08003080 HAL_CAN_WakeUpFromRxMsgCallback .text.HAL_CAN_ErrorCallback - 0x0800305c 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o - 0x0800305c HAL_CAN_ErrorCallback + 0x08003094 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o + 0x08003094 HAL_CAN_ErrorCallback .text.__NVIC_SetPriorityGrouping - 0x08003070 0x48 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.o + 0x080030a8 0x48 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.o .text.__NVIC_GetPriorityGrouping - 0x080030b8 0x1c ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.o + 0x080030f0 0x1c ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.o .text.__NVIC_EnableIRQ - 0x080030d4 0x3c ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.o + 0x0800310c 0x3c ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.o .text.__NVIC_SetPriority - 0x08003110 0x54 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.o + 0x08003148 0x54 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.o .text.NVIC_EncodePriority - 0x08003164 0x66 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.o - *fill* 0x080031ca 0x2 + 0x0800319c 0x66 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.o + *fill* 0x08003202 0x2 .text.SysTick_Config - 0x080031cc 0x44 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.o + 0x08003204 0x44 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.o .text.HAL_NVIC_SetPriorityGrouping - 0x08003210 0x16 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.o - 0x08003210 HAL_NVIC_SetPriorityGrouping + 0x08003248 0x16 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.o + 0x08003248 HAL_NVIC_SetPriorityGrouping .text.HAL_NVIC_SetPriority - 0x08003226 0x38 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.o - 0x08003226 HAL_NVIC_SetPriority + 0x0800325e 0x38 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.o + 0x0800325e HAL_NVIC_SetPriority .text.HAL_NVIC_EnableIRQ - 0x0800325e 0x1c ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.o - 0x0800325e HAL_NVIC_EnableIRQ + 0x08003296 0x1c ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.o + 0x08003296 HAL_NVIC_EnableIRQ .text.HAL_SYSTICK_Config - 0x0800327a 0x18 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.o - 0x0800327a HAL_SYSTICK_Config + 0x080032b2 0x18 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.o + 0x080032b2 HAL_SYSTICK_Config .text.HAL_DMA_Init - 0x08003292 0x8e ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.o - 0x08003292 HAL_DMA_Init + 0x080032ca 0x8e ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.o + 0x080032ca HAL_DMA_Init .text.HAL_DMA_IRQHandler - 0x08003320 0x146 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.o - 0x08003320 HAL_DMA_IRQHandler - *fill* 0x08003466 0x2 + 0x08003358 0x146 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.o + 0x08003358 HAL_DMA_IRQHandler + *fill* 0x0800349e 0x2 .text.DMA_CalcBaseAndBitshift - 0x08003468 0x78 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.o + 0x080034a0 0x78 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.o .text.HAL_GPIO_Init - 0x080034e0 0x2f4 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.o - 0x080034e0 HAL_GPIO_Init + 0x08003518 0x2f4 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.o + 0x08003518 HAL_GPIO_Init .text.HAL_GPIO_WritePin - 0x080037d4 0x30 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.o - 0x080037d4 HAL_GPIO_WritePin + 0x0800380c 0x30 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.o + 0x0800380c HAL_GPIO_WritePin .text.HAL_RCC_OscConfig - 0x08003804 0x107c ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.o - 0x08003804 HAL_RCC_OscConfig + 0x0800383c 0x107c ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.o + 0x0800383c HAL_RCC_OscConfig .text.HAL_RCC_ClockConfig - 0x08004880 0x2f8 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.o - 0x08004880 HAL_RCC_ClockConfig + 0x080048b8 0x2f8 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.o + 0x080048b8 HAL_RCC_ClockConfig .text.HAL_RCC_GetSysClockFreq - 0x08004b78 0xd8 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.o - 0x08004b78 HAL_RCC_GetSysClockFreq + 0x08004bb0 0xd8 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.o + 0x08004bb0 HAL_RCC_GetSysClockFreq .text.HAL_RCC_GetHCLKFreq - 0x08004c50 0x18 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.o - 0x08004c50 HAL_RCC_GetHCLKFreq + 0x08004c88 0x18 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.o + 0x08004c88 HAL_RCC_GetHCLKFreq .text.HAL_RCC_GetPCLK1Freq - 0x08004c68 0x44 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.o - 0x08004c68 HAL_RCC_GetPCLK1Freq + 0x08004ca0 0x44 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.o + 0x08004ca0 HAL_RCC_GetPCLK1Freq .text.HAL_RCC_GetPCLK2Freq - 0x08004cac 0x44 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.o - 0x08004cac HAL_RCC_GetPCLK2Freq + 0x08004ce4 0x44 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.o + 0x08004ce4 HAL_RCC_GetPCLK2Freq .text.HAL_RCCEx_PeriphCLKConfig - 0x08004cf0 0x324 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.o - 0x08004cf0 HAL_RCCEx_PeriphCLKConfig + 0x08004d28 0x324 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.o + 0x08004d28 HAL_RCCEx_PeriphCLKConfig .text.HAL_TIM_Base_Init - 0x08005014 0xae ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.o - 0x08005014 HAL_TIM_Base_Init + 0x0800504c 0xae ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.o + 0x0800504c HAL_TIM_Base_Init .text.HAL_TIM_IRQHandler - 0x080050c2 0x23e ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.o - 0x080050c2 HAL_TIM_IRQHandler + 0x080050fa 0x23e ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.o + 0x080050fa HAL_TIM_IRQHandler .text.HAL_TIM_PeriodElapsedCallback - 0x08005300 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.o - 0x08005300 HAL_TIM_PeriodElapsedCallback + 0x08005338 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.o + 0x08005338 HAL_TIM_PeriodElapsedCallback .text.HAL_TIM_OC_DelayElapsedCallback - 0x08005314 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.o - 0x08005314 HAL_TIM_OC_DelayElapsedCallback + 0x0800534c 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.o + 0x0800534c HAL_TIM_OC_DelayElapsedCallback .text.HAL_TIM_IC_CaptureCallback - 0x08005328 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.o - 0x08005328 HAL_TIM_IC_CaptureCallback + 0x08005360 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.o + 0x08005360 HAL_TIM_IC_CaptureCallback .text.HAL_TIM_PWM_PulseFinishedCallback - 0x0800533c 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.o - 0x0800533c HAL_TIM_PWM_PulseFinishedCallback + 0x08005374 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.o + 0x08005374 HAL_TIM_PWM_PulseFinishedCallback .text.HAL_TIM_TriggerCallback - 0x08005350 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.o - 0x08005350 HAL_TIM_TriggerCallback + 0x08005388 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.o + 0x08005388 HAL_TIM_TriggerCallback .text.TIM_Base_SetConfig - 0x08005364 0x104 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.o - 0x08005364 TIM_Base_SetConfig + 0x0800539c 0x104 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.o + 0x0800539c TIM_Base_SetConfig .text.HAL_TIMEx_MasterConfigSynchronization - 0x08005468 0xe8 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.o - 0x08005468 HAL_TIMEx_MasterConfigSynchronization + 0x080054a0 0xe8 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.o + 0x080054a0 HAL_TIMEx_MasterConfigSynchronization .text.HAL_TIMEx_CommutCallback - 0x08005550 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.o - 0x08005550 HAL_TIMEx_CommutCallback + 0x08005588 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.o + 0x08005588 HAL_TIMEx_CommutCallback .text.HAL_TIMEx_BreakCallback - 0x08005564 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.o - 0x08005564 HAL_TIMEx_BreakCallback + 0x0800559c 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.o + 0x0800559c HAL_TIMEx_BreakCallback .text.HAL_TIMEx_Break2Callback - 0x08005578 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.o - 0x08005578 HAL_TIMEx_Break2Callback + 0x080055b0 0x14 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.o + 0x080055b0 HAL_TIMEx_Break2Callback .text.HAL_UART_Init - 0x0800558c 0x9c ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.o - 0x0800558c HAL_UART_Init + 0x080055c4 0x9c ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.o + 0x080055c4 HAL_UART_Init .text.UART_SetConfig - 0x08005628 0x3a8 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.o - 0x08005628 UART_SetConfig + 0x08005660 0x3a8 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.o + 0x08005660 UART_SetConfig .text.UART_AdvFeatureConfig - 0x080059d0 0x144 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.o - 0x080059d0 UART_AdvFeatureConfig + 0x08005a08 0x144 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.o + 0x08005a08 UART_AdvFeatureConfig .text.UART_CheckIdleState - 0x08005b14 0x150 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.o - 0x08005b14 UART_CheckIdleState + 0x08005b4c 0x150 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.o + 0x08005b4c UART_CheckIdleState .text.UART_WaitOnFlagUntilTimeout - 0x08005c64 0xce ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.o - 0x08005c64 UART_WaitOnFlagUntilTimeout + 0x08005c9c 0xce ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.o + 0x08005c9c UART_WaitOnFlagUntilTimeout .text.UART_EndRxTransfer - 0x08005d32 0xc8 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.o - .text.memset 0x08005dfa 0x10 C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.1.0.202410251130/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-memset.o) - 0x08005dfa memset - *fill* 0x08005e0a 0x2 + 0x08005d6a 0xc8 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.o + .text.memset 0x08005e32 0x10 C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.1.0.202410251130/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-memset.o) + 0x08005e32 memset + *fill* 0x08005e42 0x2 .text.__libc_init_array - 0x08005e0c 0x48 C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.1.0.202410251130/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-init.o) - 0x08005e0c __libc_init_array + 0x08005e44 0x48 C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.1.0.202410251130/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-init.o) + 0x08005e44 __libc_init_array *(.glue_7) - .glue_7 0x08005e54 0x0 linker stubs + .glue_7 0x08005e8c 0x0 linker stubs *(.glue_7t) - .glue_7t 0x08005e54 0x0 linker stubs + .glue_7t 0x08005e8c 0x0 linker stubs *(.eh_frame) - .eh_frame 0x08005e54 0x0 C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.1.0.202410251130/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+fp/hard/crtbegin.o + .eh_frame 0x08005e8c 0x0 C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.1.0.202410251130/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+fp/hard/crtbegin.o *(.init) - .init 0x08005e54 0x4 C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.1.0.202410251130/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+fp/hard/crti.o - 0x08005e54 _init - .init 0x08005e58 0x8 C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.1.0.202410251130/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+fp/hard/crtn.o + .init 0x08005e8c 0x4 C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.1.0.202410251130/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+fp/hard/crti.o + 0x08005e8c _init + .init 0x08005e90 0x8 C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.1.0.202410251130/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+fp/hard/crtn.o *(.fini) - .fini 0x08005e60 0x4 C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.1.0.202410251130/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+fp/hard/crti.o - 0x08005e60 _fini - .fini 0x08005e64 0x8 C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.1.0.202410251130/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+fp/hard/crtn.o - 0x08005e6c . = ALIGN (0x4) - 0x08005e6c _etext = . + .fini 0x08005e98 0x4 C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.1.0.202410251130/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+fp/hard/crti.o + 0x08005e98 _fini + .fini 0x08005e9c 0x8 C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.1.0.202410251130/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+fp/hard/crtn.o + 0x08005ea4 . = ALIGN (0x4) + 0x08005ea4 _etext = . -.vfp11_veneer 0x08005e6c 0x0 - .vfp11_veneer 0x08005e6c 0x0 linker stubs +.vfp11_veneer 0x08005ea4 0x0 + .vfp11_veneer 0x08005ea4 0x0 linker stubs -.v4_bx 0x08005e6c 0x0 - .v4_bx 0x08005e6c 0x0 linker stubs +.v4_bx 0x08005ea4 0x0 + .v4_bx 0x08005ea4 0x0 linker stubs -.iplt 0x08005e6c 0x0 - .iplt 0x08005e6c 0x0 C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.1.0.202410251130/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+fp/hard/crtbegin.o +.iplt 0x08005ea4 0x0 + .iplt 0x08005ea4 0x0 C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.1.0.202410251130/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+fp/hard/crtbegin.o -.rodata 0x08005e6c 0x38 - 0x08005e6c . = ALIGN (0x4) +.rodata 0x08005ea4 0x38 + 0x08005ea4 . = ALIGN (0x4) *(.rodata) *(.rodata*) .rodata.AHBPrescTable - 0x08005e6c 0x10 ./Core/Src/system_stm32f3xx.o - 0x08005e6c AHBPrescTable + 0x08005ea4 0x10 ./Core/Src/system_stm32f3xx.o + 0x08005ea4 AHBPrescTable .rodata.APBPrescTable - 0x08005e7c 0x8 ./Core/Src/system_stm32f3xx.o - 0x08005e7c APBPrescTable + 0x08005eb4 0x8 ./Core/Src/system_stm32f3xx.o + 0x08005eb4 APBPrescTable .rodata.aPLLMULFactorTable - 0x08005e84 0x10 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.o + 0x08005ebc 0x10 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.o .rodata.aPredivFactorTable - 0x08005e94 0x10 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.o - 0x08005ea4 . = ALIGN (0x4) + 0x08005ecc 0x10 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.o + 0x08005edc . = ALIGN (0x4) -.ARM.extab 0x08005ea4 0x0 - 0x08005ea4 . = ALIGN (0x4) +.ARM.extab 0x08005edc 0x0 + 0x08005edc . = ALIGN (0x4) *(.ARM.extab* .gnu.linkonce.armextab.*) - 0x08005ea4 . = ALIGN (0x4) + 0x08005edc . = ALIGN (0x4) -.ARM 0x08005ea4 0x0 - 0x08005ea4 . = ALIGN (0x4) - 0x08005ea4 __exidx_start = . +.ARM 0x08005edc 0x0 + 0x08005edc . = ALIGN (0x4) + 0x08005edc __exidx_start = . *(.ARM.exidx*) - 0x08005ea4 __exidx_end = . - 0x08005ea4 . = ALIGN (0x4) + 0x08005edc __exidx_end = . + 0x08005edc . = ALIGN (0x4) -.preinit_array 0x08005ea4 0x0 - 0x08005ea4 . = ALIGN (0x4) - 0x08005ea4 PROVIDE (__preinit_array_start = .) +.preinit_array 0x08005edc 0x0 + 0x08005edc . = ALIGN (0x4) + 0x08005edc PROVIDE (__preinit_array_start = .) *(.preinit_array*) - 0x08005ea4 PROVIDE (__preinit_array_end = .) - 0x08005ea4 . = ALIGN (0x4) + 0x08005edc PROVIDE (__preinit_array_end = .) + 0x08005edc . = ALIGN (0x4) -.init_array 0x08005ea4 0x4 - 0x08005ea4 . = ALIGN (0x4) - 0x08005ea4 PROVIDE (__init_array_start = .) +.init_array 0x08005edc 0x4 + 0x08005edc . = ALIGN (0x4) + 0x08005edc PROVIDE (__init_array_start = .) *(SORT_BY_NAME(.init_array.*)) *(.init_array*) - .init_array 0x08005ea4 0x4 C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.1.0.202410251130/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+fp/hard/crtbegin.o - 0x08005ea8 PROVIDE (__init_array_end = .) - 0x08005ea8 . = ALIGN (0x4) + .init_array 0x08005edc 0x4 C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.1.0.202410251130/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+fp/hard/crtbegin.o + 0x08005ee0 PROVIDE (__init_array_end = .) + 0x08005ee0 . = ALIGN (0x4) -.fini_array 0x08005ea8 0x4 - 0x08005ea8 . = ALIGN (0x4) +.fini_array 0x08005ee0 0x4 + 0x08005ee0 . = ALIGN (0x4) [!provide] PROVIDE (__fini_array_start = .) *(SORT_BY_NAME(.fini_array.*)) *(.fini_array*) - .fini_array 0x08005ea8 0x4 C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.1.0.202410251130/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+fp/hard/crtbegin.o + .fini_array 0x08005ee0 0x4 C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.1.0.202410251130/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+fp/hard/crtbegin.o [!provide] PROVIDE (__fini_array_end = .) - 0x08005eac . = ALIGN (0x4) - 0x08005eac _sidata = LOADADDR (.data) + 0x08005ee4 . = ALIGN (0x4) + 0x08005ee4 _sidata = LOADADDR (.data) -.rel.dyn 0x08005eac 0x0 - .rel.iplt 0x08005eac 0x0 C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.1.0.202410251130/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+fp/hard/crtbegin.o +.rel.dyn 0x08005ee4 0x0 + .rel.iplt 0x08005ee4 0x0 C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.1.0.202410251130/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+fp/hard/crtbegin.o -.data 0x20000000 0xc load address 0x08005eac +.data 0x20000000 0xc load address 0x08005ee4 0x20000000 . = ALIGN (0x4) 0x20000000 _sdata = . *(.data) @@ -4640,11 +4640,11 @@ LOAD C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.ext *fill* 0x20000009 0x3 0x2000000c _edata = . -.igot.plt 0x2000000c 0x0 load address 0x08005eb8 +.igot.plt 0x2000000c 0x0 load address 0x08005ef0 .igot.plt 0x2000000c 0x0 C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.1.0.202410251130/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+fp/hard/crtbegin.o 0x2000000c . = ALIGN (0x4) -.bss 0x2000000c 0x2ac load address 0x08005eb8 +.bss 0x2000000c 0x2ac load address 0x08005ef0 0x2000000c _sbss = . 0x2000000c __bss_start__ = _sbss *(.bss) @@ -4703,7 +4703,7 @@ LOAD C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.ext 0x200002b8 __bss_end__ = _ebss ._user_heap_stack - 0x200002b8 0x600 load address 0x08005eb8 + 0x200002b8 0x600 load address 0x08005ef0 0x200002b8 . = ALIGN (0x8) [!provide] PROVIDE (end = .) 0x200002b8 PROVIDE (_end = .) @@ -4994,27 +4994,27 @@ LOAD C:/ST/STM32CubeIDE_1.17.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.ext .debug_macro 0x0001e0cc 0x1fa ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.o .debug_macro 0x0001e2c6 0x217 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.o -.debug_line 0x00000000 0x15c26 +.debug_line 0x00000000 0x15c41 .debug_line 0x00000000 0x852 ./Core/Src/can_communication.o .debug_line 0x00000852 0xadb ./Core/Src/can_halal.o .debug_line 0x0000132d 0x876 ./Core/Src/channel_control.o - .debug_line 0x00001ba3 0xb4a ./Core/Src/main.o - .debug_line 0x000026ed 0x9a8 ./Core/Src/stm32f3xx_hal_msp.o - .debug_line 0x00003095 0x90d ./Core/Src/stm32f3xx_it.o - .debug_line 0x000039a2 0x833 ./Core/Src/system_stm32f3xx.o - .debug_line 0x000041d5 0x7a ./Core/Startup/startup_stm32f302rbtx.o - .debug_line 0x0000424f 0xa6b ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.o - .debug_line 0x00004cba 0x9a9 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.o - .debug_line 0x00005663 0x2149 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.o - .debug_line 0x000077ac 0x1248 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o - .debug_line 0x000089f4 0xd2e ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.o - .debug_line 0x00009722 0xd77 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.o - .debug_line 0x0000a499 0xbe2 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.o - .debug_line 0x0000b07b 0x1440 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.o - .debug_line 0x0000c4bb 0xd42 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.o - .debug_line 0x0000d1fd 0x3d82 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.o - .debug_line 0x00010f7f 0x1b19 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.o - .debug_line 0x00012a98 0x318e ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.o + .debug_line 0x00001ba3 0xb65 ./Core/Src/main.o + .debug_line 0x00002708 0x9a8 ./Core/Src/stm32f3xx_hal_msp.o + .debug_line 0x000030b0 0x90d ./Core/Src/stm32f3xx_it.o + .debug_line 0x000039bd 0x833 ./Core/Src/system_stm32f3xx.o + .debug_line 0x000041f0 0x7a ./Core/Startup/startup_stm32f302rbtx.o + .debug_line 0x0000426a 0xa6b ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.o + .debug_line 0x00004cd5 0x9a9 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.o + .debug_line 0x0000567e 0x2149 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.o + .debug_line 0x000077c7 0x1248 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o + .debug_line 0x00008a0f 0xd2e ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.o + .debug_line 0x0000973d 0xd77 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.o + .debug_line 0x0000a4b4 0xbe2 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.o + .debug_line 0x0000b096 0x1440 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.o + .debug_line 0x0000c4d6 0xd42 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.o + .debug_line 0x0000d218 0x3d82 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.o + .debug_line 0x00010f9a 0x1b19 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.o + .debug_line 0x00012ab3 0x318e ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.o .debug_str 0x00000000 0xb7783 .debug_str 0x00000000 0xaf3f1 ./Core/Src/can_communication.o