1178 lines
70 KiB
Plaintext
1178 lines
70 KiB
Plaintext
ARM GAS /tmp/ccdoKIzP.s page 1
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1 .cpu cortex-m4
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2 .arch armv7e-m
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3 .fpu fpv4-sp-d16
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4 .eabi_attribute 27, 1
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5 .eabi_attribute 28, 1
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6 .eabi_attribute 20, 1
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7 .eabi_attribute 21, 1
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8 .eabi_attribute 23, 3
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9 .eabi_attribute 24, 1
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10 .eabi_attribute 25, 1
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11 .eabi_attribute 26, 1
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12 .eabi_attribute 30, 6
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13 .eabi_attribute 34, 1
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14 .eabi_attribute 18, 4
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15 .file "stm32f3xx_hal_pwr.c"
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16 .text
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17 .Ltext0:
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18 .cfi_sections .debug_frame
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19 .file 1 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c"
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20 .section .text.HAL_PWR_DeInit,"ax",%progbits
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21 .align 1
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22 .global HAL_PWR_DeInit
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23 .syntax unified
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24 .thumb
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25 .thumb_func
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27 HAL_PWR_DeInit:
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28 .LFB130:
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1:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
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2:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ******************************************************************************
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3:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @file stm32f3xx_hal_pwr.c
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4:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @author MCD Application Team
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5:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief PWR HAL module driver.
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6:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * This file provides firmware functions to manage the following
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7:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * functionalities of the Power Controller (PWR) peripheral:
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8:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * + Initialization/de-initialization functions
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9:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * + Peripheral Control functions
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10:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *
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11:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ******************************************************************************
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12:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @attention
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13:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *
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14:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * Copyright (c) 2016 STMicroelectronics.
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15:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * All rights reserved.
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16:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *
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17:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * This software is licensed under terms that can be found in the LICENSE file
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18:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * in the root directory of this software component.
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19:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * If no LICENSE file comes with this software, it is provided AS-IS.
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20:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *
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21:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ******************************************************************************
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22:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
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23:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
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24:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Includes ------------------------------------------------------------------*/
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25:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** #include "stm32f3xx_hal.h"
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26:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
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27:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /** @addtogroup STM32F3xx_HAL_Driver
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28:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @{
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29:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
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30:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
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ARM GAS /tmp/ccdoKIzP.s page 2
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31:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /** @defgroup PWR PWR
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32:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief PWR HAL module driver
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33:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @{
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34:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
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35:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
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36:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** #ifdef HAL_PWR_MODULE_ENABLED
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37:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
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38:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Private typedef -----------------------------------------------------------*/
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39:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Private define ------------------------------------------------------------*/
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40:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Private macro -------------------------------------------------------------*/
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41:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Private variables ---------------------------------------------------------*/
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42:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Private function prototypes -----------------------------------------------*/
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43:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Private functions ---------------------------------------------------------*/
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44:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
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45:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /** @defgroup PWR_Exported_Functions PWR Exported Functions
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46:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @{
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47:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
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48:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
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49:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
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50:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Initialization and de-initialization functions
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51:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *
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52:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** @verbatim
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53:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ===============================================================================
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54:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ##### Initialization and de-initialization functions #####
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55:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ===============================================================================
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56:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** [..]
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57:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** After reset, the backup domain (RTC registers, RTC backup data
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58:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** registers and backup SRAM) is protected against possible unwanted
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59:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** write accesses.
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60:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** To enable access to the RTC Domain and RTC registers, proceed as follows:
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61:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Enable the Power Controller (PWR) APB1 interface clock using the
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62:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __HAL_RCC_PWR_CLK_ENABLE() macro.
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63:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
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64:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
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65:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** @endverbatim
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66:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @{
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67:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
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68:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
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69:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
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70:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Deinitializes the PWR peripheral registers to their default reset values.
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71:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None
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72:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
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73:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_DeInit(void)
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74:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
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29 .loc 1 74 1
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30 .cfi_startproc
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31 @ args = 0, pretend = 0, frame = 0
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32 @ frame_needed = 1, uses_anonymous_args = 0
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33 @ link register save eliminated.
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34 0000 80B4 push {r7}
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35 .cfi_def_cfa_offset 4
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36 .cfi_offset 7, -4
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37 0002 00AF add r7, sp, #0
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38 .cfi_def_cfa_register 7
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75:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __HAL_RCC_PWR_FORCE_RESET();
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39 .loc 1 75 3
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40 0004 084B ldr r3, .L2
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ARM GAS /tmp/ccdoKIzP.s page 3
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41 0006 1B69 ldr r3, [r3, #16]
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42 0008 074A ldr r2, .L2
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43 000a 43F08053 orr r3, r3, #268435456
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44 000e 1361 str r3, [r2, #16]
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76:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __HAL_RCC_PWR_RELEASE_RESET();
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45 .loc 1 76 3
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46 0010 054B ldr r3, .L2
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47 0012 1B69 ldr r3, [r3, #16]
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48 0014 044A ldr r2, .L2
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49 0016 23F08053 bic r3, r3, #268435456
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50 001a 1361 str r3, [r2, #16]
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77:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
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51 .loc 1 77 1
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52 001c 00BF nop
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53 001e BD46 mov sp, r7
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54 .cfi_def_cfa_register 13
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55 @ sp needed
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56 0020 5DF8047B ldr r7, [sp], #4
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57 .cfi_restore 7
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58 .cfi_def_cfa_offset 0
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59 0024 7047 bx lr
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60 .L3:
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61 0026 00BF .align 2
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62 .L2:
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63 0028 00100240 .word 1073876992
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64 .cfi_endproc
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65 .LFE130:
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67 .section .text.HAL_PWR_EnableBkUpAccess,"ax",%progbits
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68 .align 1
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69 .global HAL_PWR_EnableBkUpAccess
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70 .syntax unified
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71 .thumb
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72 .thumb_func
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74 HAL_PWR_EnableBkUpAccess:
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75 .LFB131:
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78:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
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79:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
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80:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Enables access to the backup domain (RTC registers, RTC
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81:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * backup data registers and backup SRAM).
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82:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note If the HSE divided by 32 is used as the RTC clock, the
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83:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * Backup Domain Access should be kept enabled.
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84:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None
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85:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
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86:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_EnableBkUpAccess(void)
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87:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
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76 .loc 1 87 1
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77 .cfi_startproc
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78 @ args = 0, pretend = 0, frame = 0
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79 @ frame_needed = 1, uses_anonymous_args = 0
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80 @ link register save eliminated.
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81 0000 80B4 push {r7}
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82 .cfi_def_cfa_offset 4
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83 .cfi_offset 7, -4
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84 0002 00AF add r7, sp, #0
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85 .cfi_def_cfa_register 7
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88:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** SET_BIT(PWR->CR, PWR_CR_DBP);
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86 .loc 1 88 3
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ARM GAS /tmp/ccdoKIzP.s page 4
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87 0004 054B ldr r3, .L5
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88 0006 1B68 ldr r3, [r3]
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89 0008 044A ldr r2, .L5
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90 000a 43F48073 orr r3, r3, #256
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91 000e 1360 str r3, [r2]
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89:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
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92 .loc 1 89 1
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93 0010 00BF nop
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94 0012 BD46 mov sp, r7
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95 .cfi_def_cfa_register 13
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96 @ sp needed
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97 0014 5DF8047B ldr r7, [sp], #4
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98 .cfi_restore 7
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99 .cfi_def_cfa_offset 0
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100 0018 7047 bx lr
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101 .L6:
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102 001a 00BF .align 2
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103 .L5:
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104 001c 00700040 .word 1073770496
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105 .cfi_endproc
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106 .LFE131:
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108 .section .text.HAL_PWR_DisableBkUpAccess,"ax",%progbits
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109 .align 1
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110 .global HAL_PWR_DisableBkUpAccess
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111 .syntax unified
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112 .thumb
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113 .thumb_func
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115 HAL_PWR_DisableBkUpAccess:
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116 .LFB132:
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90:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
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91:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
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92:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Disables access to the backup domain (RTC registers, RTC
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93:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * backup data registers and backup SRAM).
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94:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note If the HSE divided by 32 is used as the RTC clock, the
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95:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * Backup Domain Access should be kept enabled.
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96:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None
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97:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
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98:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_DisableBkUpAccess(void)
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99:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
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117 .loc 1 99 1
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118 .cfi_startproc
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119 @ args = 0, pretend = 0, frame = 0
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120 @ frame_needed = 1, uses_anonymous_args = 0
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121 @ link register save eliminated.
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122 0000 80B4 push {r7}
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123 .cfi_def_cfa_offset 4
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124 .cfi_offset 7, -4
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125 0002 00AF add r7, sp, #0
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126 .cfi_def_cfa_register 7
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100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** CLEAR_BIT(PWR->CR, PWR_CR_DBP);
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127 .loc 1 100 3
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128 0004 054B ldr r3, .L8
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129 0006 1B68 ldr r3, [r3]
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130 0008 044A ldr r2, .L8
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131 000a 23F48073 bic r3, r3, #256
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132 000e 1360 str r3, [r2]
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101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
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ARM GAS /tmp/ccdoKIzP.s page 5
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133 .loc 1 101 1
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134 0010 00BF nop
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135 0012 BD46 mov sp, r7
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136 .cfi_def_cfa_register 13
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137 @ sp needed
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138 0014 5DF8047B ldr r7, [sp], #4
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139 .cfi_restore 7
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140 .cfi_def_cfa_offset 0
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141 0018 7047 bx lr
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142 .L9:
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143 001a 00BF .align 2
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144 .L8:
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145 001c 00700040 .word 1073770496
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146 .cfi_endproc
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147 .LFE132:
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149 .section .text.HAL_PWR_EnableWakeUpPin,"ax",%progbits
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150 .align 1
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151 .global HAL_PWR_EnableWakeUpPin
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152 .syntax unified
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153 .thumb
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154 .thumb_func
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156 HAL_PWR_EnableWakeUpPin:
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157 .LFB133:
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102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
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103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
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104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @}
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105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
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106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
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107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
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108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Low Power modes configuration functions
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109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *
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110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** @verbatim
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111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
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112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ===============================================================================
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113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ##### Peripheral Control functions #####
|
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114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ===============================================================================
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115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
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116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *** WakeUp pin configuration ***
|
||
117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ================================
|
||
118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** [..]
|
||
119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) WakeUp pin is used to wakeup the system from Standby mode. This pin is
|
||
120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** forced in input pull down configuration and is active on rising edges.
|
||
121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) There are up to three WakeUp pins:
|
||
122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++)WakeUp Pin 1 on PA.00.
|
||
123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++)WakeUp Pin 2 on PC.13 (STM32F303xC, STM32F303xE only).
|
||
124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++)WakeUp Pin 3 on PE.06.
|
||
125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *** Main and Backup Regulators configuration ***
|
||
127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ================================================
|
||
128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** [..]
|
||
129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) When the backup domain is supplied by VDD (analog switch connected to VDD)
|
||
130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** the backup SRAM is powered from VDD which replaces the VBAT power supply to
|
||
131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** save battery life.
|
||
132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) The backup SRAM is not mass erased by a tamper event. It is read
|
||
134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** protected to prevent confidential data, such as cryptographic private
|
||
135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** key, from being accessed. The backup SRAM can be erased only through
|
||
ARM GAS /tmp/ccdoKIzP.s page 6
|
||
|
||
|
||
136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** the Flash interface when a protection level change from level 1 to
|
||
137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** level 0 is requested.
|
||
138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** -@- Refer to the description of Read protection (RDP) in the Flash
|
||
139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** programming manual.
|
||
140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** Refer to the datasheets for more details.
|
||
142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *** Low Power modes configuration ***
|
||
144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** =====================================
|
||
145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** [..]
|
||
146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** The devices feature 3 low-power modes:
|
||
147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running.
|
||
148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Stop mode: all clocks are stopped, regulator running, regulator
|
||
149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** in low power mode
|
||
150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Standby mode: 1.2V domain powered off (mode not available on STM32F3x8 devices).
|
||
151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *** Sleep mode ***
|
||
153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ==================
|
||
154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** [..]
|
||
155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Entry:
|
||
156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_S
|
||
157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** functions with
|
||
158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
|
||
159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
|
||
160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Exit:
|
||
162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) Any peripheral interrupt acknowledged by the nested vectored interrupt
|
||
163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** controller (NVIC) can wake up the device from Sleep mode.
|
||
164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *** Stop mode ***
|
||
166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** =================
|
||
167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** [..]
|
||
168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** In Stop mode, all clocks in the 1.8V domain are stopped, the PLL, the HSI,
|
||
169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** and the HSE RC oscillators are disabled. Internal SRAM and register contents
|
||
170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** are preserved.
|
||
171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** The voltage regulator can be configured either in normal or low-power mode to minimize the co
|
||
172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Entry:
|
||
174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON, PWR_STOPEN
|
||
175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** function with:
|
||
176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) Main regulator ON or
|
||
177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) Low Power regulator ON.
|
||
178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) PWR_STOPENTRY_WFI: enter STOP mode with WFI instruction or
|
||
179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) PWR_STOPENTRY_WFE: enter STOP mode with WFE instruction
|
||
180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Exit:
|
||
181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
|
||
182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) Some specific communication peripherals (CEC, USART, I2C) interrupts,
|
||
183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** when programmed in wakeup mode (the peripheral must be
|
||
184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** programmed in wakeup mode and the corresponding interrupt vector
|
||
185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** must be enabled in the NVIC).
|
||
186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *** Standby mode ***
|
||
188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ====================
|
||
189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** [..]
|
||
190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** The Standby mode allows to achieve the lowest power consumption. It is based
|
||
191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** on the Cortex-M4 deep sleep mode, with the voltage regulator disabled.
|
||
192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** The 1.8V domain is consequently powered off. The PLL, the HSI oscillator and
|
||
ARM GAS /tmp/ccdoKIzP.s page 7
|
||
|
||
|
||
193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** the HSE oscillator are also switched off. SRAM and register contents are lost
|
||
194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** except for the RTC registers, RTC backup registers, backup SRAM and Standby
|
||
195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** circuitry.
|
||
196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** The voltage regulator is OFF.
|
||
197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Entry:
|
||
199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
|
||
200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Exit:
|
||
201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,
|
||
202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
|
||
203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *** Auto-wakeup (AWU) from low-power mode ***
|
||
205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** =============================================
|
||
206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** [..]
|
||
207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
|
||
208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** Wakeup event, a tamper event, a time-stamp event, or a comparator event,
|
||
209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** without depending on an external interrupt (Auto-wakeup mode).
|
||
210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) RTC auto-wakeup (AWU) from the Stop and Standby modes
|
||
212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
|
||
214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
|
||
215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
|
||
217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** is necessary to configure the RTC to detect the tamper or time stamp event using the
|
||
218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** HAL_RTC_SetTimeStamp_IT() or HAL_RTC_SetTamper_IT() functions.
|
||
219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
|
||
221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** configure the RTC to generate the RTC WakeUp event using the HAL_RTC_SetWakeUpTimer_IT()
|
||
222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Comparator auto-wakeup (AWU) from the Stop mode
|
||
224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) To wake up from the Stop mode with a comparator wakeup event, it is necessary to:
|
||
226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+++) Configure the EXTI Line associated with the comparator (example EXTI Line 22 for c
|
||
227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** to be sensitive to to the selected edges (falling, rising or falling
|
||
228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** and rising) (Interrupt or Event modes) using the EXTI_Init() function.
|
||
229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+++) Configure the comparator to generate the event.
|
||
230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** @endverbatim
|
||
231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @{
|
||
232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
|
||
233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
|
||
235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Enables the WakeUp PINx functionality.
|
||
236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @param WakeUpPinx Specifies the Power Wake-Up pin to enable.
|
||
237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * This parameter can be value of :
|
||
238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @ref PWR_WakeUp_Pins
|
||
239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None
|
||
240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
|
||
241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
|
||
242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
|
||
158 .loc 1 242 1
|
||
159 .cfi_startproc
|
||
160 @ args = 0, pretend = 0, frame = 8
|
||
161 @ frame_needed = 1, uses_anonymous_args = 0
|
||
162 @ link register save eliminated.
|
||
163 0000 80B4 push {r7}
|
||
164 .cfi_def_cfa_offset 4
|
||
ARM GAS /tmp/ccdoKIzP.s page 8
|
||
|
||
|
||
165 .cfi_offset 7, -4
|
||
166 0002 83B0 sub sp, sp, #12
|
||
167 .cfi_def_cfa_offset 16
|
||
168 0004 00AF add r7, sp, #0
|
||
169 .cfi_def_cfa_register 7
|
||
170 0006 7860 str r0, [r7, #4]
|
||
243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Check the parameters */
|
||
244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
|
||
245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Enable the EWUPx pin */
|
||
246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** SET_BIT(PWR->CSR, WakeUpPinx);
|
||
171 .loc 1 246 3
|
||
172 0008 054B ldr r3, .L11
|
||
173 000a 5A68 ldr r2, [r3, #4]
|
||
174 000c 0449 ldr r1, .L11
|
||
175 000e 7B68 ldr r3, [r7, #4]
|
||
176 0010 1343 orrs r3, r3, r2
|
||
177 0012 4B60 str r3, [r1, #4]
|
||
247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
|
||
178 .loc 1 247 1
|
||
179 0014 00BF nop
|
||
180 0016 0C37 adds r7, r7, #12
|
||
181 .cfi_def_cfa_offset 4
|
||
182 0018 BD46 mov sp, r7
|
||
183 .cfi_def_cfa_register 13
|
||
184 @ sp needed
|
||
185 001a 5DF8047B ldr r7, [sp], #4
|
||
186 .cfi_restore 7
|
||
187 .cfi_def_cfa_offset 0
|
||
188 001e 7047 bx lr
|
||
189 .L12:
|
||
190 .align 2
|
||
191 .L11:
|
||
192 0020 00700040 .word 1073770496
|
||
193 .cfi_endproc
|
||
194 .LFE133:
|
||
196 .section .text.HAL_PWR_DisableWakeUpPin,"ax",%progbits
|
||
197 .align 1
|
||
198 .global HAL_PWR_DisableWakeUpPin
|
||
199 .syntax unified
|
||
200 .thumb
|
||
201 .thumb_func
|
||
203 HAL_PWR_DisableWakeUpPin:
|
||
204 .LFB134:
|
||
248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
|
||
250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Disables the WakeUp PINx functionality.
|
||
251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @param WakeUpPinx Specifies the Power Wake-Up pin to disable.
|
||
252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * This parameter can be values of :
|
||
253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @ref PWR_WakeUp_Pins
|
||
254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None
|
||
255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
|
||
256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
|
||
257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
|
||
205 .loc 1 257 1
|
||
206 .cfi_startproc
|
||
207 @ args = 0, pretend = 0, frame = 8
|
||
208 @ frame_needed = 1, uses_anonymous_args = 0
|
||
ARM GAS /tmp/ccdoKIzP.s page 9
|
||
|
||
|
||
209 @ link register save eliminated.
|
||
210 0000 80B4 push {r7}
|
||
211 .cfi_def_cfa_offset 4
|
||
212 .cfi_offset 7, -4
|
||
213 0002 83B0 sub sp, sp, #12
|
||
214 .cfi_def_cfa_offset 16
|
||
215 0004 00AF add r7, sp, #0
|
||
216 .cfi_def_cfa_register 7
|
||
217 0006 7860 str r0, [r7, #4]
|
||
258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Check the parameters */
|
||
259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
|
||
260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Disable the EWUPx pin */
|
||
261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** CLEAR_BIT(PWR->CSR, WakeUpPinx);
|
||
218 .loc 1 261 3
|
||
219 0008 064B ldr r3, .L14
|
||
220 000a 5A68 ldr r2, [r3, #4]
|
||
221 000c 7B68 ldr r3, [r7, #4]
|
||
222 000e DB43 mvns r3, r3
|
||
223 0010 0449 ldr r1, .L14
|
||
224 0012 1340 ands r3, r3, r2
|
||
225 0014 4B60 str r3, [r1, #4]
|
||
262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
|
||
226 .loc 1 262 1
|
||
227 0016 00BF nop
|
||
228 0018 0C37 adds r7, r7, #12
|
||
229 .cfi_def_cfa_offset 4
|
||
230 001a BD46 mov sp, r7
|
||
231 .cfi_def_cfa_register 13
|
||
232 @ sp needed
|
||
233 001c 5DF8047B ldr r7, [sp], #4
|
||
234 .cfi_restore 7
|
||
235 .cfi_def_cfa_offset 0
|
||
236 0020 7047 bx lr
|
||
237 .L15:
|
||
238 0022 00BF .align 2
|
||
239 .L14:
|
||
240 0024 00700040 .word 1073770496
|
||
241 .cfi_endproc
|
||
242 .LFE134:
|
||
244 .section .text.HAL_PWR_EnterSLEEPMode,"ax",%progbits
|
||
245 .align 1
|
||
246 .global HAL_PWR_EnterSLEEPMode
|
||
247 .syntax unified
|
||
248 .thumb
|
||
249 .thumb_func
|
||
251 HAL_PWR_EnterSLEEPMode:
|
||
252 .LFB135:
|
||
263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
|
||
265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Enters Sleep mode.
|
||
266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note In Sleep mode, all I/O pins keep the same state as in Run mode.
|
||
267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @param Regulator Specifies the regulator state in SLEEP mode.
|
||
268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * This parameter can be one of the following values:
|
||
269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON
|
||
270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON
|
||
271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note This parameter has no effect in F3 family and is just maintained to
|
||
272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * offer full portability of other STM32 families software.
|
||
ARM GAS /tmp/ccdoKIzP.s page 10
|
||
|
||
|
||
273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @param SLEEPEntry Specifies if SLEEP mode is entered with WFI or WFE instruction.
|
||
274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * When WFI entry is used, tick interrupt have to be disabled if not desired as
|
||
275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * the interrupt wake up source.
|
||
276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * This parameter can be one of the following values:
|
||
277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
|
||
278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
|
||
279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None
|
||
280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
|
||
281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
|
||
282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
|
||
253 .loc 1 282 1
|
||
254 .cfi_startproc
|
||
255 @ args = 0, pretend = 0, frame = 8
|
||
256 @ frame_needed = 1, uses_anonymous_args = 0
|
||
257 @ link register save eliminated.
|
||
258 0000 80B4 push {r7}
|
||
259 .cfi_def_cfa_offset 4
|
||
260 .cfi_offset 7, -4
|
||
261 0002 83B0 sub sp, sp, #12
|
||
262 .cfi_def_cfa_offset 16
|
||
263 0004 00AF add r7, sp, #0
|
||
264 .cfi_def_cfa_register 7
|
||
265 0006 7860 str r0, [r7, #4]
|
||
266 0008 0B46 mov r3, r1
|
||
267 000a FB70 strb r3, [r7, #3]
|
||
283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Check the parameters */
|
||
284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
|
||
285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Clear SLEEPDEEP bit of Cortex System Control Register */
|
||
287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
|
||
268 .loc 1 287 6
|
||
269 000c 094B ldr r3, .L20
|
||
270 000e 1B69 ldr r3, [r3, #16]
|
||
271 0010 084A ldr r2, .L20
|
||
272 .loc 1 287 12
|
||
273 0012 23F00403 bic r3, r3, #4
|
||
274 0016 1361 str r3, [r2, #16]
|
||
288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Select SLEEP mode entry -------------------------------------------------*/
|
||
290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
|
||
275 .loc 1 290 5
|
||
276 0018 FB78 ldrb r3, [r7, #3] @ zero_extendqisi2
|
||
277 001a 012B cmp r3, #1
|
||
278 001c 01D1 bne .L17
|
||
291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
|
||
292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Request Wait For Interrupt */
|
||
293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __WFI();
|
||
279 .loc 1 293 5
|
||
280 .syntax unified
|
||
281 @ 293 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1
|
||
282 001e 30BF wfi
|
||
283 @ 0 "" 2
|
||
294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
|
||
295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** else
|
||
296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
|
||
297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Request Wait For Event */
|
||
298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __SEV();
|
||
ARM GAS /tmp/ccdoKIzP.s page 11
|
||
|
||
|
||
299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __WFE();
|
||
300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __WFE();
|
||
301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
|
||
302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
|
||
284 .loc 1 302 1
|
||
285 .thumb
|
||
286 .syntax unified
|
||
287 0020 02E0 b .L19
|
||
288 .L17:
|
||
298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __WFE();
|
||
289 .loc 1 298 5
|
||
290 .syntax unified
|
||
291 @ 298 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1
|
||
292 0022 40BF sev
|
||
293 @ 0 "" 2
|
||
299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __WFE();
|
||
294 .loc 1 299 5
|
||
295 @ 299 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1
|
||
296 0024 20BF wfe
|
||
297 @ 0 "" 2
|
||
300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
|
||
298 .loc 1 300 5
|
||
299 @ 300 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1
|
||
300 0026 20BF wfe
|
||
301 @ 0 "" 2
|
||
302 .thumb
|
||
303 .syntax unified
|
||
304 .L19:
|
||
305 .loc 1 302 1
|
||
306 0028 00BF nop
|
||
307 002a 0C37 adds r7, r7, #12
|
||
308 .cfi_def_cfa_offset 4
|
||
309 002c BD46 mov sp, r7
|
||
310 .cfi_def_cfa_register 13
|
||
311 @ sp needed
|
||
312 002e 5DF8047B ldr r7, [sp], #4
|
||
313 .cfi_restore 7
|
||
314 .cfi_def_cfa_offset 0
|
||
315 0032 7047 bx lr
|
||
316 .L21:
|
||
317 .align 2
|
||
318 .L20:
|
||
319 0034 00ED00E0 .word -536810240
|
||
320 .cfi_endproc
|
||
321 .LFE135:
|
||
323 .section .text.HAL_PWR_EnterSTOPMode,"ax",%progbits
|
||
324 .align 1
|
||
325 .global HAL_PWR_EnterSTOPMode
|
||
326 .syntax unified
|
||
327 .thumb
|
||
328 .thumb_func
|
||
330 HAL_PWR_EnterSTOPMode:
|
||
331 .LFB136:
|
||
303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
|
||
305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Enters STOP mode.
|
||
306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note In Stop mode, all I/O pins keep the same state as in Run mode.
|
||
ARM GAS /tmp/ccdoKIzP.s page 12
|
||
|
||
|
||
307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note When exiting Stop mode by issuing an interrupt or a wakeup event,
|
||
308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * the HSI RC oscillator is selected as system clock.
|
||
309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note When the voltage regulator operates in low power mode, an additional
|
||
310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * startup delay is incurred when waking up from Stop mode.
|
||
311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * By keeping the internal regulator ON during Stop mode, the consumption
|
||
312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * is higher although the startup time is reduced.
|
||
313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @param Regulator Specifies the regulator state in STOP mode.
|
||
314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * This parameter can be one of the following values:
|
||
315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @arg PWR_MAINREGULATOR_ON: STOP mode with regulator ON
|
||
316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @arg PWR_LOWPOWERREGULATOR_ON: STOP mode with low power regulator ON
|
||
317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @param STOPEntry specifies if STOP mode in entered with WFI or WFE instruction.
|
||
318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * This parameter can be one of the following values:
|
||
319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @arg PWR_STOPENTRY_WFI:Enter STOP mode with WFI instruction
|
||
320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @arg PWR_STOPENTRY_WFE: Enter STOP mode with WFE instruction
|
||
321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None
|
||
322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
|
||
323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
|
||
324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
|
||
332 .loc 1 324 1
|
||
333 .cfi_startproc
|
||
334 @ args = 0, pretend = 0, frame = 16
|
||
335 @ frame_needed = 1, uses_anonymous_args = 0
|
||
336 @ link register save eliminated.
|
||
337 0000 80B4 push {r7}
|
||
338 .cfi_def_cfa_offset 4
|
||
339 .cfi_offset 7, -4
|
||
340 0002 85B0 sub sp, sp, #20
|
||
341 .cfi_def_cfa_offset 24
|
||
342 0004 00AF add r7, sp, #0
|
||
343 .cfi_def_cfa_register 7
|
||
344 0006 7860 str r0, [r7, #4]
|
||
345 0008 0B46 mov r3, r1
|
||
346 000a FB70 strb r3, [r7, #3]
|
||
325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** uint32_t tmpreg = 0U;
|
||
347 .loc 1 325 12
|
||
348 000c 0023 movs r3, #0
|
||
349 000e FB60 str r3, [r7, #12]
|
||
326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Check the parameters */
|
||
328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** assert_param(IS_PWR_REGULATOR(Regulator));
|
||
329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
|
||
330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Select the regulator state in STOP mode ---------------------------------*/
|
||
332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** tmpreg = PWR->CR;
|
||
350 .loc 1 332 15
|
||
351 0010 134B ldr r3, .L25
|
||
352 .loc 1 332 10
|
||
353 0012 1B68 ldr r3, [r3]
|
||
354 0014 FB60 str r3, [r7, #12]
|
||
333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Clear PDDS and LPDS bits */
|
||
335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** tmpreg &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS);
|
||
355 .loc 1 335 10
|
||
356 0016 FB68 ldr r3, [r7, #12]
|
||
357 0018 23F00303 bic r3, r3, #3
|
||
358 001c FB60 str r3, [r7, #12]
|
||
336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
ARM GAS /tmp/ccdoKIzP.s page 13
|
||
|
||
|
||
337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Set LPDS bit according to Regulator value */
|
||
338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** tmpreg |= Regulator;
|
||
359 .loc 1 338 10
|
||
360 001e FA68 ldr r2, [r7, #12]
|
||
361 0020 7B68 ldr r3, [r7, #4]
|
||
362 0022 1343 orrs r3, r3, r2
|
||
363 0024 FB60 str r3, [r7, #12]
|
||
339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Store the new value */
|
||
341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** PWR->CR = tmpreg;
|
||
364 .loc 1 341 6
|
||
365 0026 0E4A ldr r2, .L25
|
||
366 .loc 1 341 11
|
||
367 0028 FB68 ldr r3, [r7, #12]
|
||
368 002a 1360 str r3, [r2]
|
||
342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Set SLEEPDEEP bit of Cortex System Control Register */
|
||
344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
|
||
369 .loc 1 344 6
|
||
370 002c 0D4B ldr r3, .L25+4
|
||
371 002e 1B69 ldr r3, [r3, #16]
|
||
372 0030 0C4A ldr r2, .L25+4
|
||
373 .loc 1 344 12
|
||
374 0032 43F00403 orr r3, r3, #4
|
||
375 0036 1361 str r3, [r2, #16]
|
||
345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Select STOP mode entry --------------------------------------------------*/
|
||
347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** if(STOPEntry == PWR_STOPENTRY_WFI)
|
||
376 .loc 1 347 5
|
||
377 0038 FB78 ldrb r3, [r7, #3] @ zero_extendqisi2
|
||
378 003a 012B cmp r3, #1
|
||
379 003c 01D1 bne .L23
|
||
348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
|
||
349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Request Wait For Interrupt */
|
||
350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __WFI();
|
||
380 .loc 1 350 5
|
||
381 .syntax unified
|
||
382 @ 350 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1
|
||
383 003e 30BF wfi
|
||
384 @ 0 "" 2
|
||
385 .thumb
|
||
386 .syntax unified
|
||
387 0040 02E0 b .L24
|
||
388 .L23:
|
||
351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
|
||
352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** else
|
||
353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
|
||
354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Request Wait For Event */
|
||
355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __SEV();
|
||
389 .loc 1 355 5
|
||
390 .syntax unified
|
||
391 @ 355 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1
|
||
392 0042 40BF sev
|
||
393 @ 0 "" 2
|
||
356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __WFE();
|
||
394 .loc 1 356 5
|
||
395 @ 356 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1
|
||
ARM GAS /tmp/ccdoKIzP.s page 14
|
||
|
||
|
||
396 0044 20BF wfe
|
||
397 @ 0 "" 2
|
||
357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __WFE();
|
||
398 .loc 1 357 5
|
||
399 @ 357 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1
|
||
400 0046 20BF wfe
|
||
401 @ 0 "" 2
|
||
402 .thumb
|
||
403 .syntax unified
|
||
404 .L24:
|
||
358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
|
||
359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Reset SLEEPDEEP bit of Cortex System Control Register */
|
||
361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
|
||
405 .loc 1 361 6
|
||
406 0048 064B ldr r3, .L25+4
|
||
407 004a 1B69 ldr r3, [r3, #16]
|
||
408 004c 054A ldr r2, .L25+4
|
||
409 .loc 1 361 12
|
||
410 004e 23F00403 bic r3, r3, #4
|
||
411 0052 1361 str r3, [r2, #16]
|
||
362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
|
||
412 .loc 1 362 1
|
||
413 0054 00BF nop
|
||
414 0056 1437 adds r7, r7, #20
|
||
415 .cfi_def_cfa_offset 4
|
||
416 0058 BD46 mov sp, r7
|
||
417 .cfi_def_cfa_register 13
|
||
418 @ sp needed
|
||
419 005a 5DF8047B ldr r7, [sp], #4
|
||
420 .cfi_restore 7
|
||
421 .cfi_def_cfa_offset 0
|
||
422 005e 7047 bx lr
|
||
423 .L26:
|
||
424 .align 2
|
||
425 .L25:
|
||
426 0060 00700040 .word 1073770496
|
||
427 0064 00ED00E0 .word -536810240
|
||
428 .cfi_endproc
|
||
429 .LFE136:
|
||
431 .section .text.HAL_PWR_EnterSTANDBYMode,"ax",%progbits
|
||
432 .align 1
|
||
433 .global HAL_PWR_EnterSTANDBYMode
|
||
434 .syntax unified
|
||
435 .thumb
|
||
436 .thumb_func
|
||
438 HAL_PWR_EnterSTANDBYMode:
|
||
439 .LFB137:
|
||
363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
|
||
365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Enters STANDBY mode.
|
||
366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note In Standby mode, all I/O pins are high impedance except for:
|
||
367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * - Reset pad (still available),
|
||
368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * - RTC alternate function pins if configured for tamper, time-stamp, RTC
|
||
369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * Alarm out, or RTC clock calibration out,
|
||
370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * - WKUP pins if enabled.
|
||
371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None
|
||
ARM GAS /tmp/ccdoKIzP.s page 15
|
||
|
||
|
||
372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
|
||
373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_EnterSTANDBYMode(void)
|
||
374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
|
||
440 .loc 1 374 1
|
||
441 .cfi_startproc
|
||
442 @ args = 0, pretend = 0, frame = 0
|
||
443 @ frame_needed = 1, uses_anonymous_args = 0
|
||
444 @ link register save eliminated.
|
||
445 0000 80B4 push {r7}
|
||
446 .cfi_def_cfa_offset 4
|
||
447 .cfi_offset 7, -4
|
||
448 0002 00AF add r7, sp, #0
|
||
449 .cfi_def_cfa_register 7
|
||
375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Select STANDBY mode */
|
||
376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** PWR->CR |= PWR_CR_PDDS;
|
||
450 .loc 1 376 6
|
||
451 0004 084B ldr r3, .L28
|
||
452 0006 1B68 ldr r3, [r3]
|
||
453 0008 074A ldr r2, .L28
|
||
454 .loc 1 376 11
|
||
455 000a 43F00203 orr r3, r3, #2
|
||
456 000e 1360 str r3, [r2]
|
||
377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Set SLEEPDEEP bit of Cortex System Control Register */
|
||
379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
|
||
457 .loc 1 379 6
|
||
458 0010 064B ldr r3, .L28+4
|
||
459 0012 1B69 ldr r3, [r3, #16]
|
||
460 0014 054A ldr r2, .L28+4
|
||
461 .loc 1 379 12
|
||
462 0016 43F00403 orr r3, r3, #4
|
||
463 001a 1361 str r3, [r2, #16]
|
||
380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* This option is used to ensure that store operations are completed */
|
||
382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** #if defined ( __CC_ARM)
|
||
383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __force_stores();
|
||
384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** #endif
|
||
385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Request Wait For Interrupt */
|
||
386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __WFI();
|
||
464 .loc 1 386 3
|
||
465 .syntax unified
|
||
466 @ 386 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1
|
||
467 001c 30BF wfi
|
||
468 @ 0 "" 2
|
||
387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
|
||
469 .loc 1 387 1
|
||
470 .thumb
|
||
471 .syntax unified
|
||
472 001e 00BF nop
|
||
473 0020 BD46 mov sp, r7
|
||
474 .cfi_def_cfa_register 13
|
||
475 @ sp needed
|
||
476 0022 5DF8047B ldr r7, [sp], #4
|
||
477 .cfi_restore 7
|
||
478 .cfi_def_cfa_offset 0
|
||
479 0026 7047 bx lr
|
||
480 .L29:
|
||
ARM GAS /tmp/ccdoKIzP.s page 16
|
||
|
||
|
||
481 .align 2
|
||
482 .L28:
|
||
483 0028 00700040 .word 1073770496
|
||
484 002c 00ED00E0 .word -536810240
|
||
485 .cfi_endproc
|
||
486 .LFE137:
|
||
488 .section .text.HAL_PWR_EnableSleepOnExit,"ax",%progbits
|
||
489 .align 1
|
||
490 .global HAL_PWR_EnableSleepOnExit
|
||
491 .syntax unified
|
||
492 .thumb
|
||
493 .thumb_func
|
||
495 HAL_PWR_EnableSleepOnExit:
|
||
496 .LFB138:
|
||
388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
|
||
390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
|
||
391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
|
||
392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * re-enters SLEEP mode when an interruption handling is over.
|
||
393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * Setting this bit is useful when the processor is expected to run only on
|
||
394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * interruptions handling.
|
||
395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None
|
||
396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
|
||
397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_EnableSleepOnExit(void)
|
||
398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
|
||
497 .loc 1 398 1
|
||
498 .cfi_startproc
|
||
499 @ args = 0, pretend = 0, frame = 0
|
||
500 @ frame_needed = 1, uses_anonymous_args = 0
|
||
501 @ link register save eliminated.
|
||
502 0000 80B4 push {r7}
|
||
503 .cfi_def_cfa_offset 4
|
||
504 .cfi_offset 7, -4
|
||
505 0002 00AF add r7, sp, #0
|
||
506 .cfi_def_cfa_register 7
|
||
399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Set SLEEPONEXIT bit of Cortex System Control Register */
|
||
400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
|
||
507 .loc 1 400 3
|
||
508 0004 054B ldr r3, .L31
|
||
509 0006 1B69 ldr r3, [r3, #16]
|
||
510 0008 044A ldr r2, .L31
|
||
511 000a 43F00203 orr r3, r3, #2
|
||
512 000e 1361 str r3, [r2, #16]
|
||
401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
|
||
513 .loc 1 401 1
|
||
514 0010 00BF nop
|
||
515 0012 BD46 mov sp, r7
|
||
516 .cfi_def_cfa_register 13
|
||
517 @ sp needed
|
||
518 0014 5DF8047B ldr r7, [sp], #4
|
||
519 .cfi_restore 7
|
||
520 .cfi_def_cfa_offset 0
|
||
521 0018 7047 bx lr
|
||
522 .L32:
|
||
523 001a 00BF .align 2
|
||
524 .L31:
|
||
525 001c 00ED00E0 .word -536810240
|
||
ARM GAS /tmp/ccdoKIzP.s page 17
|
||
|
||
|
||
526 .cfi_endproc
|
||
527 .LFE138:
|
||
529 .section .text.HAL_PWR_DisableSleepOnExit,"ax",%progbits
|
||
530 .align 1
|
||
531 .global HAL_PWR_DisableSleepOnExit
|
||
532 .syntax unified
|
||
533 .thumb
|
||
534 .thumb_func
|
||
536 HAL_PWR_DisableSleepOnExit:
|
||
537 .LFB139:
|
||
402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
|
||
405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
|
||
406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
|
||
407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * re-enters SLEEP mode when an interruption handling is over.
|
||
408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None
|
||
409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
|
||
410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_DisableSleepOnExit(void)
|
||
411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
|
||
538 .loc 1 411 1
|
||
539 .cfi_startproc
|
||
540 @ args = 0, pretend = 0, frame = 0
|
||
541 @ frame_needed = 1, uses_anonymous_args = 0
|
||
542 @ link register save eliminated.
|
||
543 0000 80B4 push {r7}
|
||
544 .cfi_def_cfa_offset 4
|
||
545 .cfi_offset 7, -4
|
||
546 0002 00AF add r7, sp, #0
|
||
547 .cfi_def_cfa_register 7
|
||
412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Clear SLEEPONEXIT bit of Cortex System Control Register */
|
||
413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
|
||
548 .loc 1 413 3
|
||
549 0004 054B ldr r3, .L34
|
||
550 0006 1B69 ldr r3, [r3, #16]
|
||
551 0008 044A ldr r2, .L34
|
||
552 000a 23F00203 bic r3, r3, #2
|
||
553 000e 1361 str r3, [r2, #16]
|
||
414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
|
||
554 .loc 1 414 1
|
||
555 0010 00BF nop
|
||
556 0012 BD46 mov sp, r7
|
||
557 .cfi_def_cfa_register 13
|
||
558 @ sp needed
|
||
559 0014 5DF8047B ldr r7, [sp], #4
|
||
560 .cfi_restore 7
|
||
561 .cfi_def_cfa_offset 0
|
||
562 0018 7047 bx lr
|
||
563 .L35:
|
||
564 001a 00BF .align 2
|
||
565 .L34:
|
||
566 001c 00ED00E0 .word -536810240
|
||
567 .cfi_endproc
|
||
568 .LFE139:
|
||
570 .section .text.HAL_PWR_EnableSEVOnPend,"ax",%progbits
|
||
571 .align 1
|
||
572 .global HAL_PWR_EnableSEVOnPend
|
||
ARM GAS /tmp/ccdoKIzP.s page 18
|
||
|
||
|
||
573 .syntax unified
|
||
574 .thumb
|
||
575 .thumb_func
|
||
577 HAL_PWR_EnableSEVOnPend:
|
||
578 .LFB140:
|
||
415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
|
||
419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Enables CORTEX M4 SEVONPEND bit.
|
||
420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
|
||
421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * WFE to wake up when an interrupt moves from inactive to pended.
|
||
422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None
|
||
423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
|
||
424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_EnableSEVOnPend(void)
|
||
425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
|
||
579 .loc 1 425 1
|
||
580 .cfi_startproc
|
||
581 @ args = 0, pretend = 0, frame = 0
|
||
582 @ frame_needed = 1, uses_anonymous_args = 0
|
||
583 @ link register save eliminated.
|
||
584 0000 80B4 push {r7}
|
||
585 .cfi_def_cfa_offset 4
|
||
586 .cfi_offset 7, -4
|
||
587 0002 00AF add r7, sp, #0
|
||
588 .cfi_def_cfa_register 7
|
||
426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Set SEVONPEND bit of Cortex System Control Register */
|
||
427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
|
||
589 .loc 1 427 3
|
||
590 0004 054B ldr r3, .L37
|
||
591 0006 1B69 ldr r3, [r3, #16]
|
||
592 0008 044A ldr r2, .L37
|
||
593 000a 43F01003 orr r3, r3, #16
|
||
594 000e 1361 str r3, [r2, #16]
|
||
428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
|
||
595 .loc 1 428 1
|
||
596 0010 00BF nop
|
||
597 0012 BD46 mov sp, r7
|
||
598 .cfi_def_cfa_register 13
|
||
599 @ sp needed
|
||
600 0014 5DF8047B ldr r7, [sp], #4
|
||
601 .cfi_restore 7
|
||
602 .cfi_def_cfa_offset 0
|
||
603 0018 7047 bx lr
|
||
604 .L38:
|
||
605 001a 00BF .align 2
|
||
606 .L37:
|
||
607 001c 00ED00E0 .word -536810240
|
||
608 .cfi_endproc
|
||
609 .LFE140:
|
||
611 .section .text.HAL_PWR_DisableSEVOnPend,"ax",%progbits
|
||
612 .align 1
|
||
613 .global HAL_PWR_DisableSEVOnPend
|
||
614 .syntax unified
|
||
615 .thumb
|
||
616 .thumb_func
|
||
618 HAL_PWR_DisableSEVOnPend:
|
||
ARM GAS /tmp/ccdoKIzP.s page 19
|
||
|
||
|
||
619 .LFB141:
|
||
429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
|
||
432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Disables CORTEX M4 SEVONPEND bit.
|
||
433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
|
||
434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * WFE to wake up when an interrupt moves from inactive to pended.
|
||
435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None
|
||
436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
|
||
437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_DisableSEVOnPend(void)
|
||
438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
|
||
620 .loc 1 438 1
|
||
621 .cfi_startproc
|
||
622 @ args = 0, pretend = 0, frame = 0
|
||
623 @ frame_needed = 1, uses_anonymous_args = 0
|
||
624 @ link register save eliminated.
|
||
625 0000 80B4 push {r7}
|
||
626 .cfi_def_cfa_offset 4
|
||
627 .cfi_offset 7, -4
|
||
628 0002 00AF add r7, sp, #0
|
||
629 .cfi_def_cfa_register 7
|
||
439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Clear SEVONPEND bit of Cortex System Control Register */
|
||
440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
|
||
630 .loc 1 440 3
|
||
631 0004 054B ldr r3, .L40
|
||
632 0006 1B69 ldr r3, [r3, #16]
|
||
633 0008 044A ldr r2, .L40
|
||
634 000a 23F01003 bic r3, r3, #16
|
||
635 000e 1361 str r3, [r2, #16]
|
||
441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
|
||
636 .loc 1 441 1
|
||
637 0010 00BF nop
|
||
638 0012 BD46 mov sp, r7
|
||
639 .cfi_def_cfa_register 13
|
||
640 @ sp needed
|
||
641 0014 5DF8047B ldr r7, [sp], #4
|
||
642 .cfi_restore 7
|
||
643 .cfi_def_cfa_offset 0
|
||
644 0018 7047 bx lr
|
||
645 .L41:
|
||
646 001a 00BF .align 2
|
||
647 .L40:
|
||
648 001c 00ED00E0 .word -536810240
|
||
649 .cfi_endproc
|
||
650 .LFE141:
|
||
652 .text
|
||
653 .Letext0:
|
||
654 .file 2 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl
|
||
655 .file 3 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl
|
||
656 .file 4 "Drivers/CMSIS/Include/core_cm4.h"
|
||
657 .file 5 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h"
|
||
ARM GAS /tmp/ccdoKIzP.s page 20
|
||
|
||
|
||
DEFINED SYMBOLS
|
||
*ABS*:00000000 stm32f3xx_hal_pwr.c
|
||
/tmp/ccdoKIzP.s:21 .text.HAL_PWR_DeInit:00000000 $t
|
||
/tmp/ccdoKIzP.s:27 .text.HAL_PWR_DeInit:00000000 HAL_PWR_DeInit
|
||
/tmp/ccdoKIzP.s:63 .text.HAL_PWR_DeInit:00000028 $d
|
||
/tmp/ccdoKIzP.s:68 .text.HAL_PWR_EnableBkUpAccess:00000000 $t
|
||
/tmp/ccdoKIzP.s:74 .text.HAL_PWR_EnableBkUpAccess:00000000 HAL_PWR_EnableBkUpAccess
|
||
/tmp/ccdoKIzP.s:104 .text.HAL_PWR_EnableBkUpAccess:0000001c $d
|
||
/tmp/ccdoKIzP.s:109 .text.HAL_PWR_DisableBkUpAccess:00000000 $t
|
||
/tmp/ccdoKIzP.s:115 .text.HAL_PWR_DisableBkUpAccess:00000000 HAL_PWR_DisableBkUpAccess
|
||
/tmp/ccdoKIzP.s:145 .text.HAL_PWR_DisableBkUpAccess:0000001c $d
|
||
/tmp/ccdoKIzP.s:150 .text.HAL_PWR_EnableWakeUpPin:00000000 $t
|
||
/tmp/ccdoKIzP.s:156 .text.HAL_PWR_EnableWakeUpPin:00000000 HAL_PWR_EnableWakeUpPin
|
||
/tmp/ccdoKIzP.s:192 .text.HAL_PWR_EnableWakeUpPin:00000020 $d
|
||
/tmp/ccdoKIzP.s:197 .text.HAL_PWR_DisableWakeUpPin:00000000 $t
|
||
/tmp/ccdoKIzP.s:203 .text.HAL_PWR_DisableWakeUpPin:00000000 HAL_PWR_DisableWakeUpPin
|
||
/tmp/ccdoKIzP.s:240 .text.HAL_PWR_DisableWakeUpPin:00000024 $d
|
||
/tmp/ccdoKIzP.s:245 .text.HAL_PWR_EnterSLEEPMode:00000000 $t
|
||
/tmp/ccdoKIzP.s:251 .text.HAL_PWR_EnterSLEEPMode:00000000 HAL_PWR_EnterSLEEPMode
|
||
/tmp/ccdoKIzP.s:319 .text.HAL_PWR_EnterSLEEPMode:00000034 $d
|
||
/tmp/ccdoKIzP.s:324 .text.HAL_PWR_EnterSTOPMode:00000000 $t
|
||
/tmp/ccdoKIzP.s:330 .text.HAL_PWR_EnterSTOPMode:00000000 HAL_PWR_EnterSTOPMode
|
||
/tmp/ccdoKIzP.s:426 .text.HAL_PWR_EnterSTOPMode:00000060 $d
|
||
/tmp/ccdoKIzP.s:432 .text.HAL_PWR_EnterSTANDBYMode:00000000 $t
|
||
/tmp/ccdoKIzP.s:438 .text.HAL_PWR_EnterSTANDBYMode:00000000 HAL_PWR_EnterSTANDBYMode
|
||
/tmp/ccdoKIzP.s:483 .text.HAL_PWR_EnterSTANDBYMode:00000028 $d
|
||
/tmp/ccdoKIzP.s:489 .text.HAL_PWR_EnableSleepOnExit:00000000 $t
|
||
/tmp/ccdoKIzP.s:495 .text.HAL_PWR_EnableSleepOnExit:00000000 HAL_PWR_EnableSleepOnExit
|
||
/tmp/ccdoKIzP.s:525 .text.HAL_PWR_EnableSleepOnExit:0000001c $d
|
||
/tmp/ccdoKIzP.s:530 .text.HAL_PWR_DisableSleepOnExit:00000000 $t
|
||
/tmp/ccdoKIzP.s:536 .text.HAL_PWR_DisableSleepOnExit:00000000 HAL_PWR_DisableSleepOnExit
|
||
/tmp/ccdoKIzP.s:566 .text.HAL_PWR_DisableSleepOnExit:0000001c $d
|
||
/tmp/ccdoKIzP.s:571 .text.HAL_PWR_EnableSEVOnPend:00000000 $t
|
||
/tmp/ccdoKIzP.s:577 .text.HAL_PWR_EnableSEVOnPend:00000000 HAL_PWR_EnableSEVOnPend
|
||
/tmp/ccdoKIzP.s:607 .text.HAL_PWR_EnableSEVOnPend:0000001c $d
|
||
/tmp/ccdoKIzP.s:612 .text.HAL_PWR_DisableSEVOnPend:00000000 $t
|
||
/tmp/ccdoKIzP.s:618 .text.HAL_PWR_DisableSEVOnPend:00000000 HAL_PWR_DisableSEVOnPend
|
||
/tmp/ccdoKIzP.s:648 .text.HAL_PWR_DisableSEVOnPend:0000001c $d
|
||
|
||
NO UNDEFINED SYMBOLS
|