1881 lines
82 KiB
Plaintext
1881 lines
82 KiB
Plaintext
ARM GAS /tmp/cc61sY4U.s page 1
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1 .cpu cortex-m4
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2 .arch armv7e-m
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3 .fpu fpv4-sp-d16
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4 .eabi_attribute 27, 1
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5 .eabi_attribute 28, 1
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6 .eabi_attribute 20, 1
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7 .eabi_attribute 21, 1
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8 .eabi_attribute 23, 3
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9 .eabi_attribute 24, 1
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10 .eabi_attribute 25, 1
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11 .eabi_attribute 26, 1
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12 .eabi_attribute 30, 6
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13 .eabi_attribute 34, 1
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14 .eabi_attribute 18, 4
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15 .file "stm32f3xx_hal_msp.c"
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16 .text
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17 .Ltext0:
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18 .cfi_sections .debug_frame
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19 .file 1 "Core/Src/stm32f3xx_hal_msp.c"
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20 .section .text.HAL_MspInit,"ax",%progbits
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21 .align 1
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22 .global HAL_MspInit
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23 .syntax unified
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24 .thumb
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25 .thumb_func
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27 HAL_MspInit:
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28 .LFB130:
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1:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN Header */
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2:Core/Src/stm32f3xx_hal_msp.c **** /**
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3:Core/Src/stm32f3xx_hal_msp.c **** ******************************************************************************
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4:Core/Src/stm32f3xx_hal_msp.c **** * @file stm32f3xx_hal_msp.c
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5:Core/Src/stm32f3xx_hal_msp.c **** * @brief This file provides code for the MSP Initialization
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6:Core/Src/stm32f3xx_hal_msp.c **** * and de-Initialization codes.
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7:Core/Src/stm32f3xx_hal_msp.c **** ******************************************************************************
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8:Core/Src/stm32f3xx_hal_msp.c **** * @attention
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9:Core/Src/stm32f3xx_hal_msp.c **** *
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10:Core/Src/stm32f3xx_hal_msp.c **** * Copyright (c) 2024 STMicroelectronics.
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11:Core/Src/stm32f3xx_hal_msp.c **** * All rights reserved.
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12:Core/Src/stm32f3xx_hal_msp.c **** *
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13:Core/Src/stm32f3xx_hal_msp.c **** * This software is licensed under terms that can be found in the LICENSE file
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14:Core/Src/stm32f3xx_hal_msp.c **** * in the root directory of this software component.
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15:Core/Src/stm32f3xx_hal_msp.c **** * If no LICENSE file comes with this software, it is provided AS-IS.
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16:Core/Src/stm32f3xx_hal_msp.c **** *
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17:Core/Src/stm32f3xx_hal_msp.c **** ******************************************************************************
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18:Core/Src/stm32f3xx_hal_msp.c **** */
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19:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END Header */
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20:Core/Src/stm32f3xx_hal_msp.c ****
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21:Core/Src/stm32f3xx_hal_msp.c **** /* Includes ------------------------------------------------------------------*/
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22:Core/Src/stm32f3xx_hal_msp.c **** #include "main.h"
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23:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN Includes */
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24:Core/Src/stm32f3xx_hal_msp.c ****
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25:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END Includes */
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26:Core/Src/stm32f3xx_hal_msp.c ****
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27:Core/Src/stm32f3xx_hal_msp.c **** /* Private typedef -----------------------------------------------------------*/
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28:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN TD */
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29:Core/Src/stm32f3xx_hal_msp.c ****
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30:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END TD */
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ARM GAS /tmp/cc61sY4U.s page 2
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31:Core/Src/stm32f3xx_hal_msp.c ****
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32:Core/Src/stm32f3xx_hal_msp.c **** /* Private define ------------------------------------------------------------*/
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33:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN Define */
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34:Core/Src/stm32f3xx_hal_msp.c ****
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35:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END Define */
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36:Core/Src/stm32f3xx_hal_msp.c ****
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37:Core/Src/stm32f3xx_hal_msp.c **** /* Private macro -------------------------------------------------------------*/
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38:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN Macro */
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39:Core/Src/stm32f3xx_hal_msp.c ****
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40:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END Macro */
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41:Core/Src/stm32f3xx_hal_msp.c ****
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42:Core/Src/stm32f3xx_hal_msp.c **** /* Private variables ---------------------------------------------------------*/
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43:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN PV */
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44:Core/Src/stm32f3xx_hal_msp.c ****
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45:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END PV */
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46:Core/Src/stm32f3xx_hal_msp.c ****
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47:Core/Src/stm32f3xx_hal_msp.c **** /* Private function prototypes -----------------------------------------------*/
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48:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN PFP */
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49:Core/Src/stm32f3xx_hal_msp.c ****
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50:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END PFP */
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51:Core/Src/stm32f3xx_hal_msp.c ****
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52:Core/Src/stm32f3xx_hal_msp.c **** /* External functions --------------------------------------------------------*/
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53:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN ExternalFunctions */
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54:Core/Src/stm32f3xx_hal_msp.c ****
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55:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END ExternalFunctions */
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56:Core/Src/stm32f3xx_hal_msp.c ****
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57:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN 0 */
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58:Core/Src/stm32f3xx_hal_msp.c ****
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59:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END 0 */
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60:Core/Src/stm32f3xx_hal_msp.c ****
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61:Core/Src/stm32f3xx_hal_msp.c **** void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
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62:Core/Src/stm32f3xx_hal_msp.c **** /**
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63:Core/Src/stm32f3xx_hal_msp.c **** * Initializes the Global MSP.
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64:Core/Src/stm32f3xx_hal_msp.c **** */
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65:Core/Src/stm32f3xx_hal_msp.c **** void HAL_MspInit(void)
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66:Core/Src/stm32f3xx_hal_msp.c **** {
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29 .loc 1 66 1
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30 .cfi_startproc
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31 @ args = 0, pretend = 0, frame = 8
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32 @ frame_needed = 1, uses_anonymous_args = 0
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33 @ link register save eliminated.
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34 0000 80B4 push {r7}
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35 .cfi_def_cfa_offset 4
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36 .cfi_offset 7, -4
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37 0002 83B0 sub sp, sp, #12
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38 .cfi_def_cfa_offset 16
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39 0004 00AF add r7, sp, #0
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40 .cfi_def_cfa_register 7
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41 .LBB2:
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67:Core/Src/stm32f3xx_hal_msp.c ****
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68:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN MspInit 0 */
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69:Core/Src/stm32f3xx_hal_msp.c ****
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70:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END MspInit 0 */
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71:Core/Src/stm32f3xx_hal_msp.c ****
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72:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_SYSCFG_CLK_ENABLE();
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42 .loc 1 72 3
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43 0006 0F4B ldr r3, .L2
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ARM GAS /tmp/cc61sY4U.s page 3
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44 0008 9B69 ldr r3, [r3, #24]
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45 000a 0E4A ldr r2, .L2
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46 000c 43F00103 orr r3, r3, #1
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47 0010 9361 str r3, [r2, #24]
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48 0012 0C4B ldr r3, .L2
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49 0014 9B69 ldr r3, [r3, #24]
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50 0016 03F00103 and r3, r3, #1
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51 001a 7B60 str r3, [r7, #4]
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52 001c 7B68 ldr r3, [r7, #4]
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53 .LBE2:
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54 .LBB3:
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73:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_PWR_CLK_ENABLE();
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55 .loc 1 73 3
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56 001e 094B ldr r3, .L2
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57 0020 DB69 ldr r3, [r3, #28]
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58 0022 084A ldr r2, .L2
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59 0024 43F08053 orr r3, r3, #268435456
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60 0028 D361 str r3, [r2, #28]
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61 002a 064B ldr r3, .L2
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62 002c DB69 ldr r3, [r3, #28]
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63 002e 03F08053 and r3, r3, #268435456
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64 0032 3B60 str r3, [r7]
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65 0034 3B68 ldr r3, [r7]
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66 .LBE3:
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74:Core/Src/stm32f3xx_hal_msp.c ****
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75:Core/Src/stm32f3xx_hal_msp.c **** /* System interrupt init*/
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76:Core/Src/stm32f3xx_hal_msp.c ****
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77:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN MspInit 1 */
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78:Core/Src/stm32f3xx_hal_msp.c ****
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79:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END MspInit 1 */
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80:Core/Src/stm32f3xx_hal_msp.c **** }
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67 .loc 1 80 1
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68 0036 00BF nop
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69 0038 0C37 adds r7, r7, #12
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70 .cfi_def_cfa_offset 4
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71 003a BD46 mov sp, r7
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72 .cfi_def_cfa_register 13
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73 @ sp needed
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74 003c 5DF8047B ldr r7, [sp], #4
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75 .cfi_restore 7
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76 .cfi_def_cfa_offset 0
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77 0040 7047 bx lr
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78 .L3:
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79 0042 00BF .align 2
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80 .L2:
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81 0044 00100240 .word 1073876992
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82 .cfi_endproc
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83 .LFE130:
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85 .section .text.HAL_CAN_MspInit,"ax",%progbits
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86 .align 1
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87 .global HAL_CAN_MspInit
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88 .syntax unified
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89 .thumb
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90 .thumb_func
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92 HAL_CAN_MspInit:
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93 .LFB131:
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81:Core/Src/stm32f3xx_hal_msp.c ****
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ARM GAS /tmp/cc61sY4U.s page 4
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82:Core/Src/stm32f3xx_hal_msp.c **** /**
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83:Core/Src/stm32f3xx_hal_msp.c **** * @brief CAN MSP Initialization
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84:Core/Src/stm32f3xx_hal_msp.c **** * This function configures the hardware resources used in this example
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85:Core/Src/stm32f3xx_hal_msp.c **** * @param hcan: CAN handle pointer
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86:Core/Src/stm32f3xx_hal_msp.c **** * @retval None
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87:Core/Src/stm32f3xx_hal_msp.c **** */
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88:Core/Src/stm32f3xx_hal_msp.c **** void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)
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89:Core/Src/stm32f3xx_hal_msp.c **** {
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94 .loc 1 89 1
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95 .cfi_startproc
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96 @ args = 0, pretend = 0, frame = 40
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97 @ frame_needed = 1, uses_anonymous_args = 0
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98 0000 80B5 push {r7, lr}
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99 .cfi_def_cfa_offset 8
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100 .cfi_offset 7, -8
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101 .cfi_offset 14, -4
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102 0002 8AB0 sub sp, sp, #40
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103 .cfi_def_cfa_offset 48
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104 0004 00AF add r7, sp, #0
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105 .cfi_def_cfa_register 7
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106 0006 7860 str r0, [r7, #4]
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90:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitTypeDef GPIO_InitStruct = {0};
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107 .loc 1 90 20
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108 0008 07F11403 add r3, r7, #20
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109 000c 0022 movs r2, #0
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110 000e 1A60 str r2, [r3]
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111 0010 5A60 str r2, [r3, #4]
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112 0012 9A60 str r2, [r3, #8]
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113 0014 DA60 str r2, [r3, #12]
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114 0016 1A61 str r2, [r3, #16]
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91:Core/Src/stm32f3xx_hal_msp.c **** if(hcan->Instance==CAN)
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115 .loc 1 91 10
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116 0018 7B68 ldr r3, [r7, #4]
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117 001a 1B68 ldr r3, [r3]
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118 .loc 1 91 5
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119 001c 204A ldr r2, .L7
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120 001e 9342 cmp r3, r2
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121 0020 39D1 bne .L6
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122 .LBB4:
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92:Core/Src/stm32f3xx_hal_msp.c **** {
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93:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN CAN_MspInit 0 */
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94:Core/Src/stm32f3xx_hal_msp.c ****
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95:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END CAN_MspInit 0 */
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96:Core/Src/stm32f3xx_hal_msp.c **** /* Peripheral clock enable */
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97:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_CAN1_CLK_ENABLE();
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123 .loc 1 97 5
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124 0022 204B ldr r3, .L7+4
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125 0024 DB69 ldr r3, [r3, #28]
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126 0026 1F4A ldr r2, .L7+4
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127 0028 43F00073 orr r3, r3, #33554432
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128 002c D361 str r3, [r2, #28]
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129 002e 1D4B ldr r3, .L7+4
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130 0030 DB69 ldr r3, [r3, #28]
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131 0032 03F00073 and r3, r3, #33554432
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132 0036 3B61 str r3, [r7, #16]
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133 0038 3B69 ldr r3, [r7, #16]
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134 .LBE4:
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ARM GAS /tmp/cc61sY4U.s page 5
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135 .LBB5:
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98:Core/Src/stm32f3xx_hal_msp.c ****
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99:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_GPIOA_CLK_ENABLE();
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136 .loc 1 99 5
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137 003a 1A4B ldr r3, .L7+4
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138 003c 5B69 ldr r3, [r3, #20]
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139 003e 194A ldr r2, .L7+4
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140 0040 43F40033 orr r3, r3, #131072
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141 0044 5361 str r3, [r2, #20]
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142 0046 174B ldr r3, .L7+4
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143 0048 5B69 ldr r3, [r3, #20]
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144 004a 03F40033 and r3, r3, #131072
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145 004e FB60 str r3, [r7, #12]
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146 0050 FB68 ldr r3, [r7, #12]
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147 .LBE5:
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100:Core/Src/stm32f3xx_hal_msp.c **** /**CAN GPIO Configuration
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101:Core/Src/stm32f3xx_hal_msp.c **** PA11 ------> CAN_RX
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102:Core/Src/stm32f3xx_hal_msp.c **** PA12 ------> CAN_TX
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103:Core/Src/stm32f3xx_hal_msp.c **** */
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104:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12;
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148 .loc 1 104 25
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149 0052 4FF4C053 mov r3, #6144
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150 0056 7B61 str r3, [r7, #20]
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105:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
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151 .loc 1 105 26
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152 0058 0223 movs r3, #2
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153 005a BB61 str r3, [r7, #24]
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106:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
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154 .loc 1 106 26
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155 005c 0023 movs r3, #0
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156 005e FB61 str r3, [r7, #28]
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107:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
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157 .loc 1 107 27
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158 0060 0323 movs r3, #3
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159 0062 3B62 str r3, [r7, #32]
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108:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF9_CAN;
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160 .loc 1 108 31
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161 0064 0923 movs r3, #9
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162 0066 7B62 str r3, [r7, #36]
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109:Core/Src/stm32f3xx_hal_msp.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
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163 .loc 1 109 5
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164 0068 07F11403 add r3, r7, #20
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165 006c 1946 mov r1, r3
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166 006e 4FF09040 mov r0, #1207959552
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167 0072 FFF7FEFF bl HAL_GPIO_Init
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110:Core/Src/stm32f3xx_hal_msp.c ****
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111:Core/Src/stm32f3xx_hal_msp.c **** /* CAN interrupt Init */
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112:Core/Src/stm32f3xx_hal_msp.c **** HAL_NVIC_SetPriority(USB_LP_CAN_RX0_IRQn, 0, 0);
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168 .loc 1 112 5
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169 0076 0022 movs r2, #0
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170 0078 0021 movs r1, #0
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171 007a 1420 movs r0, #20
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172 007c FFF7FEFF bl HAL_NVIC_SetPriority
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113:Core/Src/stm32f3xx_hal_msp.c **** HAL_NVIC_EnableIRQ(USB_LP_CAN_RX0_IRQn);
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173 .loc 1 113 5
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174 0080 1420 movs r0, #20
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175 0082 FFF7FEFF bl HAL_NVIC_EnableIRQ
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ARM GAS /tmp/cc61sY4U.s page 6
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114:Core/Src/stm32f3xx_hal_msp.c **** HAL_NVIC_SetPriority(CAN_RX1_IRQn, 0, 0);
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176 .loc 1 114 5
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177 0086 0022 movs r2, #0
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178 0088 0021 movs r1, #0
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179 008a 1520 movs r0, #21
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180 008c FFF7FEFF bl HAL_NVIC_SetPriority
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115:Core/Src/stm32f3xx_hal_msp.c **** HAL_NVIC_EnableIRQ(CAN_RX1_IRQn);
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181 .loc 1 115 5
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182 0090 1520 movs r0, #21
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183 0092 FFF7FEFF bl HAL_NVIC_EnableIRQ
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184 .L6:
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116:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN CAN_MspInit 1 */
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117:Core/Src/stm32f3xx_hal_msp.c ****
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118:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END CAN_MspInit 1 */
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119:Core/Src/stm32f3xx_hal_msp.c **** }
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120:Core/Src/stm32f3xx_hal_msp.c ****
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121:Core/Src/stm32f3xx_hal_msp.c **** }
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185 .loc 1 121 1
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186 0096 00BF nop
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187 0098 2837 adds r7, r7, #40
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188 .cfi_def_cfa_offset 8
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189 009a BD46 mov sp, r7
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190 .cfi_def_cfa_register 13
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191 @ sp needed
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192 009c 80BD pop {r7, pc}
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193 .L8:
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194 009e 00BF .align 2
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195 .L7:
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196 00a0 00640040 .word 1073767424
|
||
197 00a4 00100240 .word 1073876992
|
||
198 .cfi_endproc
|
||
199 .LFE131:
|
||
201 .section .text.HAL_CAN_MspDeInit,"ax",%progbits
|
||
202 .align 1
|
||
203 .global HAL_CAN_MspDeInit
|
||
204 .syntax unified
|
||
205 .thumb
|
||
206 .thumb_func
|
||
208 HAL_CAN_MspDeInit:
|
||
209 .LFB132:
|
||
122:Core/Src/stm32f3xx_hal_msp.c ****
|
||
123:Core/Src/stm32f3xx_hal_msp.c **** /**
|
||
124:Core/Src/stm32f3xx_hal_msp.c **** * @brief CAN MSP De-Initialization
|
||
125:Core/Src/stm32f3xx_hal_msp.c **** * This function freeze the hardware resources used in this example
|
||
126:Core/Src/stm32f3xx_hal_msp.c **** * @param hcan: CAN handle pointer
|
||
127:Core/Src/stm32f3xx_hal_msp.c **** * @retval None
|
||
128:Core/Src/stm32f3xx_hal_msp.c **** */
|
||
129:Core/Src/stm32f3xx_hal_msp.c **** void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan)
|
||
130:Core/Src/stm32f3xx_hal_msp.c **** {
|
||
210 .loc 1 130 1
|
||
211 .cfi_startproc
|
||
212 @ args = 0, pretend = 0, frame = 8
|
||
213 @ frame_needed = 1, uses_anonymous_args = 0
|
||
214 0000 80B5 push {r7, lr}
|
||
215 .cfi_def_cfa_offset 8
|
||
216 .cfi_offset 7, -8
|
||
217 .cfi_offset 14, -4
|
||
ARM GAS /tmp/cc61sY4U.s page 7
|
||
|
||
|
||
218 0002 82B0 sub sp, sp, #8
|
||
219 .cfi_def_cfa_offset 16
|
||
220 0004 00AF add r7, sp, #0
|
||
221 .cfi_def_cfa_register 7
|
||
222 0006 7860 str r0, [r7, #4]
|
||
131:Core/Src/stm32f3xx_hal_msp.c **** if(hcan->Instance==CAN)
|
||
223 .loc 1 131 10
|
||
224 0008 7B68 ldr r3, [r7, #4]
|
||
225 000a 1B68 ldr r3, [r3]
|
||
226 .loc 1 131 5
|
||
227 000c 0C4A ldr r2, .L12
|
||
228 000e 9342 cmp r3, r2
|
||
229 0010 11D1 bne .L11
|
||
132:Core/Src/stm32f3xx_hal_msp.c **** {
|
||
133:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN CAN_MspDeInit 0 */
|
||
134:Core/Src/stm32f3xx_hal_msp.c ****
|
||
135:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END CAN_MspDeInit 0 */
|
||
136:Core/Src/stm32f3xx_hal_msp.c **** /* Peripheral clock disable */
|
||
137:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_CAN1_CLK_DISABLE();
|
||
230 .loc 1 137 5
|
||
231 0012 0C4B ldr r3, .L12+4
|
||
232 0014 DB69 ldr r3, [r3, #28]
|
||
233 0016 0B4A ldr r2, .L12+4
|
||
234 0018 23F00073 bic r3, r3, #33554432
|
||
235 001c D361 str r3, [r2, #28]
|
||
138:Core/Src/stm32f3xx_hal_msp.c ****
|
||
139:Core/Src/stm32f3xx_hal_msp.c **** /**CAN GPIO Configuration
|
||
140:Core/Src/stm32f3xx_hal_msp.c **** PA11 ------> CAN_RX
|
||
141:Core/Src/stm32f3xx_hal_msp.c **** PA12 ------> CAN_TX
|
||
142:Core/Src/stm32f3xx_hal_msp.c **** */
|
||
143:Core/Src/stm32f3xx_hal_msp.c **** HAL_GPIO_DeInit(GPIOA, GPIO_PIN_11|GPIO_PIN_12);
|
||
236 .loc 1 143 5
|
||
237 001e 4FF4C051 mov r1, #6144
|
||
238 0022 4FF09040 mov r0, #1207959552
|
||
239 0026 FFF7FEFF bl HAL_GPIO_DeInit
|
||
144:Core/Src/stm32f3xx_hal_msp.c ****
|
||
145:Core/Src/stm32f3xx_hal_msp.c **** /* CAN interrupt DeInit */
|
||
146:Core/Src/stm32f3xx_hal_msp.c **** HAL_NVIC_DisableIRQ(USB_LP_CAN_RX0_IRQn);
|
||
240 .loc 1 146 5
|
||
241 002a 1420 movs r0, #20
|
||
242 002c FFF7FEFF bl HAL_NVIC_DisableIRQ
|
||
147:Core/Src/stm32f3xx_hal_msp.c **** HAL_NVIC_DisableIRQ(CAN_RX1_IRQn);
|
||
243 .loc 1 147 5
|
||
244 0030 1520 movs r0, #21
|
||
245 0032 FFF7FEFF bl HAL_NVIC_DisableIRQ
|
||
246 .L11:
|
||
148:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN CAN_MspDeInit 1 */
|
||
149:Core/Src/stm32f3xx_hal_msp.c ****
|
||
150:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END CAN_MspDeInit 1 */
|
||
151:Core/Src/stm32f3xx_hal_msp.c **** }
|
||
152:Core/Src/stm32f3xx_hal_msp.c ****
|
||
153:Core/Src/stm32f3xx_hal_msp.c **** }
|
||
247 .loc 1 153 1
|
||
248 0036 00BF nop
|
||
249 0038 0837 adds r7, r7, #8
|
||
250 .cfi_def_cfa_offset 8
|
||
251 003a BD46 mov sp, r7
|
||
ARM GAS /tmp/cc61sY4U.s page 8
|
||
|
||
|
||
252 .cfi_def_cfa_register 13
|
||
253 @ sp needed
|
||
254 003c 80BD pop {r7, pc}
|
||
255 .L13:
|
||
256 003e 00BF .align 2
|
||
257 .L12:
|
||
258 0040 00640040 .word 1073767424
|
||
259 0044 00100240 .word 1073876992
|
||
260 .cfi_endproc
|
||
261 .LFE132:
|
||
263 .section .text.HAL_I2C_MspInit,"ax",%progbits
|
||
264 .align 1
|
||
265 .global HAL_I2C_MspInit
|
||
266 .syntax unified
|
||
267 .thumb
|
||
268 .thumb_func
|
||
270 HAL_I2C_MspInit:
|
||
271 .LFB133:
|
||
154:Core/Src/stm32f3xx_hal_msp.c ****
|
||
155:Core/Src/stm32f3xx_hal_msp.c **** /**
|
||
156:Core/Src/stm32f3xx_hal_msp.c **** * @brief I2C MSP Initialization
|
||
157:Core/Src/stm32f3xx_hal_msp.c **** * This function configures the hardware resources used in this example
|
||
158:Core/Src/stm32f3xx_hal_msp.c **** * @param hi2c: I2C handle pointer
|
||
159:Core/Src/stm32f3xx_hal_msp.c **** * @retval None
|
||
160:Core/Src/stm32f3xx_hal_msp.c **** */
|
||
161:Core/Src/stm32f3xx_hal_msp.c **** void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c)
|
||
162:Core/Src/stm32f3xx_hal_msp.c **** {
|
||
272 .loc 1 162 1
|
||
273 .cfi_startproc
|
||
274 @ args = 0, pretend = 0, frame = 48
|
||
275 @ frame_needed = 1, uses_anonymous_args = 0
|
||
276 0000 80B5 push {r7, lr}
|
||
277 .cfi_def_cfa_offset 8
|
||
278 .cfi_offset 7, -8
|
||
279 .cfi_offset 14, -4
|
||
280 0002 8CB0 sub sp, sp, #48
|
||
281 .cfi_def_cfa_offset 56
|
||
282 0004 00AF add r7, sp, #0
|
||
283 .cfi_def_cfa_register 7
|
||
284 0006 7860 str r0, [r7, #4]
|
||
163:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitTypeDef GPIO_InitStruct = {0};
|
||
285 .loc 1 163 20
|
||
286 0008 07F11C03 add r3, r7, #28
|
||
287 000c 0022 movs r2, #0
|
||
288 000e 1A60 str r2, [r3]
|
||
289 0010 5A60 str r2, [r3, #4]
|
||
290 0012 9A60 str r2, [r3, #8]
|
||
291 0014 DA60 str r2, [r3, #12]
|
||
292 0016 1A61 str r2, [r3, #16]
|
||
164:Core/Src/stm32f3xx_hal_msp.c **** if(hi2c->Instance==I2C1)
|
||
293 .loc 1 164 10
|
||
294 0018 7B68 ldr r3, [r7, #4]
|
||
295 001a 1B68 ldr r3, [r3]
|
||
296 .loc 1 164 5
|
||
297 001c 3E4A ldr r2, .L18
|
||
298 001e 9342 cmp r3, r2
|
||
299 0020 47D1 bne .L15
|
||
ARM GAS /tmp/cc61sY4U.s page 9
|
||
|
||
|
||
300 .LBB6:
|
||
165:Core/Src/stm32f3xx_hal_msp.c **** {
|
||
166:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN I2C1_MspInit 0 */
|
||
167:Core/Src/stm32f3xx_hal_msp.c ****
|
||
168:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END I2C1_MspInit 0 */
|
||
169:Core/Src/stm32f3xx_hal_msp.c ****
|
||
170:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_GPIOA_CLK_ENABLE();
|
||
301 .loc 1 170 5
|
||
302 0022 3E4B ldr r3, .L18+4
|
||
303 0024 5B69 ldr r3, [r3, #20]
|
||
304 0026 3D4A ldr r2, .L18+4
|
||
305 0028 43F40033 orr r3, r3, #131072
|
||
306 002c 5361 str r3, [r2, #20]
|
||
307 002e 3B4B ldr r3, .L18+4
|
||
308 0030 5B69 ldr r3, [r3, #20]
|
||
309 0032 03F40033 and r3, r3, #131072
|
||
310 0036 BB61 str r3, [r7, #24]
|
||
311 0038 BB69 ldr r3, [r7, #24]
|
||
312 .LBE6:
|
||
313 .LBB7:
|
||
171:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_GPIOB_CLK_ENABLE();
|
||
314 .loc 1 171 5
|
||
315 003a 384B ldr r3, .L18+4
|
||
316 003c 5B69 ldr r3, [r3, #20]
|
||
317 003e 374A ldr r2, .L18+4
|
||
318 0040 43F48023 orr r3, r3, #262144
|
||
319 0044 5361 str r3, [r2, #20]
|
||
320 0046 354B ldr r3, .L18+4
|
||
321 0048 5B69 ldr r3, [r3, #20]
|
||
322 004a 03F48023 and r3, r3, #262144
|
||
323 004e 7B61 str r3, [r7, #20]
|
||
324 0050 7B69 ldr r3, [r7, #20]
|
||
325 .LBE7:
|
||
172:Core/Src/stm32f3xx_hal_msp.c **** /**I2C1 GPIO Configuration
|
||
173:Core/Src/stm32f3xx_hal_msp.c **** PA15 ------> I2C1_SCL
|
||
174:Core/Src/stm32f3xx_hal_msp.c **** PB9 ------> I2C1_SDA
|
||
175:Core/Src/stm32f3xx_hal_msp.c **** */
|
||
176:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Pin = TMP_SCL_Pin;
|
||
326 .loc 1 176 25
|
||
327 0052 4FF40043 mov r3, #32768
|
||
328 0056 FB61 str r3, [r7, #28]
|
||
177:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
|
||
329 .loc 1 177 26
|
||
330 0058 1223 movs r3, #18
|
||
331 005a 3B62 str r3, [r7, #32]
|
||
178:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||
332 .loc 1 178 26
|
||
333 005c 0023 movs r3, #0
|
||
334 005e 7B62 str r3, [r7, #36]
|
||
179:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
|
||
335 .loc 1 179 27
|
||
336 0060 0323 movs r3, #3
|
||
337 0062 BB62 str r3, [r7, #40]
|
||
180:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF4_I2C1;
|
||
338 .loc 1 180 31
|
||
339 0064 0423 movs r3, #4
|
||
340 0066 FB62 str r3, [r7, #44]
|
||
ARM GAS /tmp/cc61sY4U.s page 10
|
||
|
||
|
||
181:Core/Src/stm32f3xx_hal_msp.c **** HAL_GPIO_Init(TMP_SCL_GPIO_Port, &GPIO_InitStruct);
|
||
341 .loc 1 181 5
|
||
342 0068 07F11C03 add r3, r7, #28
|
||
343 006c 1946 mov r1, r3
|
||
344 006e 4FF09040 mov r0, #1207959552
|
||
345 0072 FFF7FEFF bl HAL_GPIO_Init
|
||
182:Core/Src/stm32f3xx_hal_msp.c ****
|
||
183:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Pin = TMP_SDA_Pin;
|
||
346 .loc 1 183 25
|
||
347 0076 4FF40073 mov r3, #512
|
||
348 007a FB61 str r3, [r7, #28]
|
||
184:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
|
||
349 .loc 1 184 26
|
||
350 007c 1223 movs r3, #18
|
||
351 007e 3B62 str r3, [r7, #32]
|
||
185:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||
352 .loc 1 185 26
|
||
353 0080 0023 movs r3, #0
|
||
354 0082 7B62 str r3, [r7, #36]
|
||
186:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
|
||
355 .loc 1 186 27
|
||
356 0084 0323 movs r3, #3
|
||
357 0086 BB62 str r3, [r7, #40]
|
||
187:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF4_I2C1;
|
||
358 .loc 1 187 31
|
||
359 0088 0423 movs r3, #4
|
||
360 008a FB62 str r3, [r7, #44]
|
||
188:Core/Src/stm32f3xx_hal_msp.c **** HAL_GPIO_Init(TMP_SDA_GPIO_Port, &GPIO_InitStruct);
|
||
361 .loc 1 188 5
|
||
362 008c 07F11C03 add r3, r7, #28
|
||
363 0090 1946 mov r1, r3
|
||
364 0092 2348 ldr r0, .L18+8
|
||
365 0094 FFF7FEFF bl HAL_GPIO_Init
|
||
366 .LBB8:
|
||
189:Core/Src/stm32f3xx_hal_msp.c ****
|
||
190:Core/Src/stm32f3xx_hal_msp.c **** /* Peripheral clock enable */
|
||
191:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_I2C1_CLK_ENABLE();
|
||
367 .loc 1 191 5
|
||
368 0098 204B ldr r3, .L18+4
|
||
369 009a DB69 ldr r3, [r3, #28]
|
||
370 009c 1F4A ldr r2, .L18+4
|
||
371 009e 43F40013 orr r3, r3, #2097152
|
||
372 00a2 D361 str r3, [r2, #28]
|
||
373 00a4 1D4B ldr r3, .L18+4
|
||
374 00a6 DB69 ldr r3, [r3, #28]
|
||
375 00a8 03F40013 and r3, r3, #2097152
|
||
376 00ac 3B61 str r3, [r7, #16]
|
||
377 00ae 3B69 ldr r3, [r7, #16]
|
||
378 .LBE8:
|
||
192:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN I2C1_MspInit 1 */
|
||
193:Core/Src/stm32f3xx_hal_msp.c ****
|
||
194:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END I2C1_MspInit 1 */
|
||
195:Core/Src/stm32f3xx_hal_msp.c **** }
|
||
196:Core/Src/stm32f3xx_hal_msp.c **** else if(hi2c->Instance==I2C2)
|
||
197:Core/Src/stm32f3xx_hal_msp.c **** {
|
||
198:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN I2C2_MspInit 0 */
|
||
199:Core/Src/stm32f3xx_hal_msp.c ****
|
||
ARM GAS /tmp/cc61sY4U.s page 11
|
||
|
||
|
||
200:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END I2C2_MspInit 0 */
|
||
201:Core/Src/stm32f3xx_hal_msp.c ****
|
||
202:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_GPIOA_CLK_ENABLE();
|
||
203:Core/Src/stm32f3xx_hal_msp.c **** /**I2C2 GPIO Configuration
|
||
204:Core/Src/stm32f3xx_hal_msp.c **** PA9 ------> I2C2_SCL
|
||
205:Core/Src/stm32f3xx_hal_msp.c **** PA10 ------> I2C2_SDA
|
||
206:Core/Src/stm32f3xx_hal_msp.c **** */
|
||
207:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Pin = EEPROM_SCL_Pin|EEPROM_SDA_Pin;
|
||
208:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
|
||
209:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||
210:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
|
||
211:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF4_I2C2;
|
||
212:Core/Src/stm32f3xx_hal_msp.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
||
213:Core/Src/stm32f3xx_hal_msp.c ****
|
||
214:Core/Src/stm32f3xx_hal_msp.c **** /* Peripheral clock enable */
|
||
215:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_I2C2_CLK_ENABLE();
|
||
216:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN I2C2_MspInit 1 */
|
||
217:Core/Src/stm32f3xx_hal_msp.c ****
|
||
218:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END I2C2_MspInit 1 */
|
||
219:Core/Src/stm32f3xx_hal_msp.c **** }
|
||
220:Core/Src/stm32f3xx_hal_msp.c ****
|
||
221:Core/Src/stm32f3xx_hal_msp.c **** }
|
||
379 .loc 1 221 1
|
||
380 00b0 2EE0 b .L17
|
||
381 .L15:
|
||
196:Core/Src/stm32f3xx_hal_msp.c **** {
|
||
382 .loc 1 196 15
|
||
383 00b2 7B68 ldr r3, [r7, #4]
|
||
384 00b4 1B68 ldr r3, [r3]
|
||
196:Core/Src/stm32f3xx_hal_msp.c **** {
|
||
385 .loc 1 196 10
|
||
386 00b6 1B4A ldr r2, .L18+12
|
||
387 00b8 9342 cmp r3, r2
|
||
388 00ba 29D1 bne .L17
|
||
389 .LBB9:
|
||
202:Core/Src/stm32f3xx_hal_msp.c **** /**I2C2 GPIO Configuration
|
||
390 .loc 1 202 5
|
||
391 00bc 174B ldr r3, .L18+4
|
||
392 00be 5B69 ldr r3, [r3, #20]
|
||
393 00c0 164A ldr r2, .L18+4
|
||
394 00c2 43F40033 orr r3, r3, #131072
|
||
395 00c6 5361 str r3, [r2, #20]
|
||
396 00c8 144B ldr r3, .L18+4
|
||
397 00ca 5B69 ldr r3, [r3, #20]
|
||
398 00cc 03F40033 and r3, r3, #131072
|
||
399 00d0 FB60 str r3, [r7, #12]
|
||
400 00d2 FB68 ldr r3, [r7, #12]
|
||
401 .LBE9:
|
||
207:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
|
||
402 .loc 1 207 25
|
||
403 00d4 4FF4C063 mov r3, #1536
|
||
404 00d8 FB61 str r3, [r7, #28]
|
||
208:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||
405 .loc 1 208 26
|
||
406 00da 1223 movs r3, #18
|
||
407 00dc 3B62 str r3, [r7, #32]
|
||
209:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
|
||
ARM GAS /tmp/cc61sY4U.s page 12
|
||
|
||
|
||
408 .loc 1 209 26
|
||
409 00de 0023 movs r3, #0
|
||
410 00e0 7B62 str r3, [r7, #36]
|
||
210:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF4_I2C2;
|
||
411 .loc 1 210 27
|
||
412 00e2 0323 movs r3, #3
|
||
413 00e4 BB62 str r3, [r7, #40]
|
||
211:Core/Src/stm32f3xx_hal_msp.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
||
414 .loc 1 211 31
|
||
415 00e6 0423 movs r3, #4
|
||
416 00e8 FB62 str r3, [r7, #44]
|
||
212:Core/Src/stm32f3xx_hal_msp.c ****
|
||
417 .loc 1 212 5
|
||
418 00ea 07F11C03 add r3, r7, #28
|
||
419 00ee 1946 mov r1, r3
|
||
420 00f0 4FF09040 mov r0, #1207959552
|
||
421 00f4 FFF7FEFF bl HAL_GPIO_Init
|
||
422 .LBB10:
|
||
215:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN I2C2_MspInit 1 */
|
||
423 .loc 1 215 5
|
||
424 00f8 084B ldr r3, .L18+4
|
||
425 00fa DB69 ldr r3, [r3, #28]
|
||
426 00fc 074A ldr r2, .L18+4
|
||
427 00fe 43F48003 orr r3, r3, #4194304
|
||
428 0102 D361 str r3, [r2, #28]
|
||
429 0104 054B ldr r3, .L18+4
|
||
430 0106 DB69 ldr r3, [r3, #28]
|
||
431 0108 03F48003 and r3, r3, #4194304
|
||
432 010c BB60 str r3, [r7, #8]
|
||
433 010e BB68 ldr r3, [r7, #8]
|
||
434 .L17:
|
||
435 .LBE10:
|
||
436 .loc 1 221 1
|
||
437 0110 00BF nop
|
||
438 0112 3037 adds r7, r7, #48
|
||
439 .cfi_def_cfa_offset 8
|
||
440 0114 BD46 mov sp, r7
|
||
441 .cfi_def_cfa_register 13
|
||
442 @ sp needed
|
||
443 0116 80BD pop {r7, pc}
|
||
444 .L19:
|
||
445 .align 2
|
||
446 .L18:
|
||
447 0118 00540040 .word 1073763328
|
||
448 011c 00100240 .word 1073876992
|
||
449 0120 00040048 .word 1207960576
|
||
450 0124 00580040 .word 1073764352
|
||
451 .cfi_endproc
|
||
452 .LFE133:
|
||
454 .section .text.HAL_I2C_MspDeInit,"ax",%progbits
|
||
455 .align 1
|
||
456 .global HAL_I2C_MspDeInit
|
||
457 .syntax unified
|
||
458 .thumb
|
||
459 .thumb_func
|
||
461 HAL_I2C_MspDeInit:
|
||
462 .LFB134:
|
||
ARM GAS /tmp/cc61sY4U.s page 13
|
||
|
||
|
||
222:Core/Src/stm32f3xx_hal_msp.c ****
|
||
223:Core/Src/stm32f3xx_hal_msp.c **** /**
|
||
224:Core/Src/stm32f3xx_hal_msp.c **** * @brief I2C MSP De-Initialization
|
||
225:Core/Src/stm32f3xx_hal_msp.c **** * This function freeze the hardware resources used in this example
|
||
226:Core/Src/stm32f3xx_hal_msp.c **** * @param hi2c: I2C handle pointer
|
||
227:Core/Src/stm32f3xx_hal_msp.c **** * @retval None
|
||
228:Core/Src/stm32f3xx_hal_msp.c **** */
|
||
229:Core/Src/stm32f3xx_hal_msp.c **** void HAL_I2C_MspDeInit(I2C_HandleTypeDef* hi2c)
|
||
230:Core/Src/stm32f3xx_hal_msp.c **** {
|
||
463 .loc 1 230 1
|
||
464 .cfi_startproc
|
||
465 @ args = 0, pretend = 0, frame = 8
|
||
466 @ frame_needed = 1, uses_anonymous_args = 0
|
||
467 0000 80B5 push {r7, lr}
|
||
468 .cfi_def_cfa_offset 8
|
||
469 .cfi_offset 7, -8
|
||
470 .cfi_offset 14, -4
|
||
471 0002 82B0 sub sp, sp, #8
|
||
472 .cfi_def_cfa_offset 16
|
||
473 0004 00AF add r7, sp, #0
|
||
474 .cfi_def_cfa_register 7
|
||
475 0006 7860 str r0, [r7, #4]
|
||
231:Core/Src/stm32f3xx_hal_msp.c **** if(hi2c->Instance==I2C1)
|
||
476 .loc 1 231 10
|
||
477 0008 7B68 ldr r3, [r7, #4]
|
||
478 000a 1B68 ldr r3, [r3]
|
||
479 .loc 1 231 5
|
||
480 000c 174A ldr r2, .L24
|
||
481 000e 9342 cmp r3, r2
|
||
482 0010 11D1 bne .L21
|
||
232:Core/Src/stm32f3xx_hal_msp.c **** {
|
||
233:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN I2C1_MspDeInit 0 */
|
||
234:Core/Src/stm32f3xx_hal_msp.c ****
|
||
235:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END I2C1_MspDeInit 0 */
|
||
236:Core/Src/stm32f3xx_hal_msp.c **** /* Peripheral clock disable */
|
||
237:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_I2C1_CLK_DISABLE();
|
||
483 .loc 1 237 5
|
||
484 0012 174B ldr r3, .L24+4
|
||
485 0014 DB69 ldr r3, [r3, #28]
|
||
486 0016 164A ldr r2, .L24+4
|
||
487 0018 23F40013 bic r3, r3, #2097152
|
||
488 001c D361 str r3, [r2, #28]
|
||
238:Core/Src/stm32f3xx_hal_msp.c ****
|
||
239:Core/Src/stm32f3xx_hal_msp.c **** /**I2C1 GPIO Configuration
|
||
240:Core/Src/stm32f3xx_hal_msp.c **** PA15 ------> I2C1_SCL
|
||
241:Core/Src/stm32f3xx_hal_msp.c **** PB9 ------> I2C1_SDA
|
||
242:Core/Src/stm32f3xx_hal_msp.c **** */
|
||
243:Core/Src/stm32f3xx_hal_msp.c **** HAL_GPIO_DeInit(TMP_SCL_GPIO_Port, TMP_SCL_Pin);
|
||
489 .loc 1 243 5
|
||
490 001e 4FF40041 mov r1, #32768
|
||
491 0022 4FF09040 mov r0, #1207959552
|
||
492 0026 FFF7FEFF bl HAL_GPIO_DeInit
|
||
244:Core/Src/stm32f3xx_hal_msp.c ****
|
||
245:Core/Src/stm32f3xx_hal_msp.c **** HAL_GPIO_DeInit(TMP_SDA_GPIO_Port, TMP_SDA_Pin);
|
||
493 .loc 1 245 5
|
||
494 002a 4FF40071 mov r1, #512
|
||
495 002e 1148 ldr r0, .L24+8
|
||
ARM GAS /tmp/cc61sY4U.s page 14
|
||
|
||
|
||
496 0030 FFF7FEFF bl HAL_GPIO_DeInit
|
||
246:Core/Src/stm32f3xx_hal_msp.c ****
|
||
247:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN I2C1_MspDeInit 1 */
|
||
248:Core/Src/stm32f3xx_hal_msp.c ****
|
||
249:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END I2C1_MspDeInit 1 */
|
||
250:Core/Src/stm32f3xx_hal_msp.c **** }
|
||
251:Core/Src/stm32f3xx_hal_msp.c **** else if(hi2c->Instance==I2C2)
|
||
252:Core/Src/stm32f3xx_hal_msp.c **** {
|
||
253:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN I2C2_MspDeInit 0 */
|
||
254:Core/Src/stm32f3xx_hal_msp.c ****
|
||
255:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END I2C2_MspDeInit 0 */
|
||
256:Core/Src/stm32f3xx_hal_msp.c **** /* Peripheral clock disable */
|
||
257:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_I2C2_CLK_DISABLE();
|
||
258:Core/Src/stm32f3xx_hal_msp.c ****
|
||
259:Core/Src/stm32f3xx_hal_msp.c **** /**I2C2 GPIO Configuration
|
||
260:Core/Src/stm32f3xx_hal_msp.c **** PA9 ------> I2C2_SCL
|
||
261:Core/Src/stm32f3xx_hal_msp.c **** PA10 ------> I2C2_SDA
|
||
262:Core/Src/stm32f3xx_hal_msp.c **** */
|
||
263:Core/Src/stm32f3xx_hal_msp.c **** HAL_GPIO_DeInit(EEPROM_SCL_GPIO_Port, EEPROM_SCL_Pin);
|
||
264:Core/Src/stm32f3xx_hal_msp.c ****
|
||
265:Core/Src/stm32f3xx_hal_msp.c **** HAL_GPIO_DeInit(EEPROM_SDA_GPIO_Port, EEPROM_SDA_Pin);
|
||
266:Core/Src/stm32f3xx_hal_msp.c ****
|
||
267:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN I2C2_MspDeInit 1 */
|
||
268:Core/Src/stm32f3xx_hal_msp.c ****
|
||
269:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END I2C2_MspDeInit 1 */
|
||
270:Core/Src/stm32f3xx_hal_msp.c **** }
|
||
271:Core/Src/stm32f3xx_hal_msp.c ****
|
||
272:Core/Src/stm32f3xx_hal_msp.c **** }
|
||
497 .loc 1 272 1
|
||
498 0034 16E0 b .L23
|
||
499 .L21:
|
||
251:Core/Src/stm32f3xx_hal_msp.c **** {
|
||
500 .loc 1 251 15
|
||
501 0036 7B68 ldr r3, [r7, #4]
|
||
502 0038 1B68 ldr r3, [r3]
|
||
251:Core/Src/stm32f3xx_hal_msp.c **** {
|
||
503 .loc 1 251 10
|
||
504 003a 0F4A ldr r2, .L24+12
|
||
505 003c 9342 cmp r3, r2
|
||
506 003e 11D1 bne .L23
|
||
257:Core/Src/stm32f3xx_hal_msp.c ****
|
||
507 .loc 1 257 5
|
||
508 0040 0B4B ldr r3, .L24+4
|
||
509 0042 DB69 ldr r3, [r3, #28]
|
||
510 0044 0A4A ldr r2, .L24+4
|
||
511 0046 23F48003 bic r3, r3, #4194304
|
||
512 004a D361 str r3, [r2, #28]
|
||
263:Core/Src/stm32f3xx_hal_msp.c ****
|
||
513 .loc 1 263 5
|
||
514 004c 4FF40071 mov r1, #512
|
||
515 0050 4FF09040 mov r0, #1207959552
|
||
516 0054 FFF7FEFF bl HAL_GPIO_DeInit
|
||
265:Core/Src/stm32f3xx_hal_msp.c ****
|
||
517 .loc 1 265 5
|
||
518 0058 4FF48061 mov r1, #1024
|
||
519 005c 4FF09040 mov r0, #1207959552
|
||
520 0060 FFF7FEFF bl HAL_GPIO_DeInit
|
||
ARM GAS /tmp/cc61sY4U.s page 15
|
||
|
||
|
||
521 .L23:
|
||
522 .loc 1 272 1
|
||
523 0064 00BF nop
|
||
524 0066 0837 adds r7, r7, #8
|
||
525 .cfi_def_cfa_offset 8
|
||
526 0068 BD46 mov sp, r7
|
||
527 .cfi_def_cfa_register 13
|
||
528 @ sp needed
|
||
529 006a 80BD pop {r7, pc}
|
||
530 .L25:
|
||
531 .align 2
|
||
532 .L24:
|
||
533 006c 00540040 .word 1073763328
|
||
534 0070 00100240 .word 1073876992
|
||
535 0074 00040048 .word 1207960576
|
||
536 0078 00580040 .word 1073764352
|
||
537 .cfi_endproc
|
||
538 .LFE134:
|
||
540 .section .text.HAL_SPI_MspInit,"ax",%progbits
|
||
541 .align 1
|
||
542 .global HAL_SPI_MspInit
|
||
543 .syntax unified
|
||
544 .thumb
|
||
545 .thumb_func
|
||
547 HAL_SPI_MspInit:
|
||
548 .LFB135:
|
||
273:Core/Src/stm32f3xx_hal_msp.c ****
|
||
274:Core/Src/stm32f3xx_hal_msp.c **** /**
|
||
275:Core/Src/stm32f3xx_hal_msp.c **** * @brief SPI MSP Initialization
|
||
276:Core/Src/stm32f3xx_hal_msp.c **** * This function configures the hardware resources used in this example
|
||
277:Core/Src/stm32f3xx_hal_msp.c **** * @param hspi: SPI handle pointer
|
||
278:Core/Src/stm32f3xx_hal_msp.c **** * @retval None
|
||
279:Core/Src/stm32f3xx_hal_msp.c **** */
|
||
280:Core/Src/stm32f3xx_hal_msp.c **** void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
|
||
281:Core/Src/stm32f3xx_hal_msp.c **** {
|
||
549 .loc 1 281 1
|
||
550 .cfi_startproc
|
||
551 @ args = 0, pretend = 0, frame = 40
|
||
552 @ frame_needed = 1, uses_anonymous_args = 0
|
||
553 0000 80B5 push {r7, lr}
|
||
554 .cfi_def_cfa_offset 8
|
||
555 .cfi_offset 7, -8
|
||
556 .cfi_offset 14, -4
|
||
557 0002 8AB0 sub sp, sp, #40
|
||
558 .cfi_def_cfa_offset 48
|
||
559 0004 00AF add r7, sp, #0
|
||
560 .cfi_def_cfa_register 7
|
||
561 0006 7860 str r0, [r7, #4]
|
||
282:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitTypeDef GPIO_InitStruct = {0};
|
||
562 .loc 1 282 20
|
||
563 0008 07F11403 add r3, r7, #20
|
||
564 000c 0022 movs r2, #0
|
||
565 000e 1A60 str r2, [r3]
|
||
566 0010 5A60 str r2, [r3, #4]
|
||
567 0012 9A60 str r2, [r3, #8]
|
||
568 0014 DA60 str r2, [r3, #12]
|
||
569 0016 1A61 str r2, [r3, #16]
|
||
ARM GAS /tmp/cc61sY4U.s page 16
|
||
|
||
|
||
283:Core/Src/stm32f3xx_hal_msp.c **** if(hspi->Instance==SPI1)
|
||
570 .loc 1 283 10
|
||
571 0018 7B68 ldr r3, [r7, #4]
|
||
572 001a 1B68 ldr r3, [r3]
|
||
573 .loc 1 283 5
|
||
574 001c 174A ldr r2, .L29
|
||
575 001e 9342 cmp r3, r2
|
||
576 0020 28D1 bne .L28
|
||
577 .LBB11:
|
||
284:Core/Src/stm32f3xx_hal_msp.c **** {
|
||
285:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN SPI1_MspInit 0 */
|
||
286:Core/Src/stm32f3xx_hal_msp.c ****
|
||
287:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END SPI1_MspInit 0 */
|
||
288:Core/Src/stm32f3xx_hal_msp.c **** /* Peripheral clock enable */
|
||
289:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_SPI1_CLK_ENABLE();
|
||
578 .loc 1 289 5
|
||
579 0022 174B ldr r3, .L29+4
|
||
580 0024 9B69 ldr r3, [r3, #24]
|
||
581 0026 164A ldr r2, .L29+4
|
||
582 0028 43F48053 orr r3, r3, #4096
|
||
583 002c 9361 str r3, [r2, #24]
|
||
584 002e 144B ldr r3, .L29+4
|
||
585 0030 9B69 ldr r3, [r3, #24]
|
||
586 0032 03F48053 and r3, r3, #4096
|
||
587 0036 3B61 str r3, [r7, #16]
|
||
588 0038 3B69 ldr r3, [r7, #16]
|
||
589 .LBE11:
|
||
590 .LBB12:
|
||
290:Core/Src/stm32f3xx_hal_msp.c ****
|
||
291:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_GPIOA_CLK_ENABLE();
|
||
591 .loc 1 291 5
|
||
592 003a 114B ldr r3, .L29+4
|
||
593 003c 5B69 ldr r3, [r3, #20]
|
||
594 003e 104A ldr r2, .L29+4
|
||
595 0040 43F40033 orr r3, r3, #131072
|
||
596 0044 5361 str r3, [r2, #20]
|
||
597 0046 0E4B ldr r3, .L29+4
|
||
598 0048 5B69 ldr r3, [r3, #20]
|
||
599 004a 03F40033 and r3, r3, #131072
|
||
600 004e FB60 str r3, [r7, #12]
|
||
601 0050 FB68 ldr r3, [r7, #12]
|
||
602 .LBE12:
|
||
292:Core/Src/stm32f3xx_hal_msp.c **** /**SPI1 GPIO Configuration
|
||
293:Core/Src/stm32f3xx_hal_msp.c **** PA5 ------> SPI1_SCK
|
||
294:Core/Src/stm32f3xx_hal_msp.c **** PA6 ------> SPI1_MISO
|
||
295:Core/Src/stm32f3xx_hal_msp.c **** PA7 ------> SPI1_MOSI
|
||
296:Core/Src/stm32f3xx_hal_msp.c **** */
|
||
297:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7;
|
||
603 .loc 1 297 25
|
||
604 0052 E023 movs r3, #224
|
||
605 0054 7B61 str r3, [r7, #20]
|
||
298:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||
606 .loc 1 298 26
|
||
607 0056 0223 movs r3, #2
|
||
608 0058 BB61 str r3, [r7, #24]
|
||
299:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||
609 .loc 1 299 26
|
||
ARM GAS /tmp/cc61sY4U.s page 17
|
||
|
||
|
||
610 005a 0023 movs r3, #0
|
||
611 005c FB61 str r3, [r7, #28]
|
||
300:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
|
||
612 .loc 1 300 27
|
||
613 005e 0323 movs r3, #3
|
||
614 0060 3B62 str r3, [r7, #32]
|
||
301:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
|
||
615 .loc 1 301 31
|
||
616 0062 0523 movs r3, #5
|
||
617 0064 7B62 str r3, [r7, #36]
|
||
302:Core/Src/stm32f3xx_hal_msp.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
||
618 .loc 1 302 5
|
||
619 0066 07F11403 add r3, r7, #20
|
||
620 006a 1946 mov r1, r3
|
||
621 006c 4FF09040 mov r0, #1207959552
|
||
622 0070 FFF7FEFF bl HAL_GPIO_Init
|
||
623 .L28:
|
||
303:Core/Src/stm32f3xx_hal_msp.c ****
|
||
304:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN SPI1_MspInit 1 */
|
||
305:Core/Src/stm32f3xx_hal_msp.c ****
|
||
306:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END SPI1_MspInit 1 */
|
||
307:Core/Src/stm32f3xx_hal_msp.c **** }
|
||
308:Core/Src/stm32f3xx_hal_msp.c ****
|
||
309:Core/Src/stm32f3xx_hal_msp.c **** }
|
||
624 .loc 1 309 1
|
||
625 0074 00BF nop
|
||
626 0076 2837 adds r7, r7, #40
|
||
627 .cfi_def_cfa_offset 8
|
||
628 0078 BD46 mov sp, r7
|
||
629 .cfi_def_cfa_register 13
|
||
630 @ sp needed
|
||
631 007a 80BD pop {r7, pc}
|
||
632 .L30:
|
||
633 .align 2
|
||
634 .L29:
|
||
635 007c 00300140 .word 1073819648
|
||
636 0080 00100240 .word 1073876992
|
||
637 .cfi_endproc
|
||
638 .LFE135:
|
||
640 .section .text.HAL_SPI_MspDeInit,"ax",%progbits
|
||
641 .align 1
|
||
642 .global HAL_SPI_MspDeInit
|
||
643 .syntax unified
|
||
644 .thumb
|
||
645 .thumb_func
|
||
647 HAL_SPI_MspDeInit:
|
||
648 .LFB136:
|
||
310:Core/Src/stm32f3xx_hal_msp.c ****
|
||
311:Core/Src/stm32f3xx_hal_msp.c **** /**
|
||
312:Core/Src/stm32f3xx_hal_msp.c **** * @brief SPI MSP De-Initialization
|
||
313:Core/Src/stm32f3xx_hal_msp.c **** * This function freeze the hardware resources used in this example
|
||
314:Core/Src/stm32f3xx_hal_msp.c **** * @param hspi: SPI handle pointer
|
||
315:Core/Src/stm32f3xx_hal_msp.c **** * @retval None
|
||
316:Core/Src/stm32f3xx_hal_msp.c **** */
|
||
317:Core/Src/stm32f3xx_hal_msp.c **** void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi)
|
||
318:Core/Src/stm32f3xx_hal_msp.c **** {
|
||
649 .loc 1 318 1
|
||
ARM GAS /tmp/cc61sY4U.s page 18
|
||
|
||
|
||
650 .cfi_startproc
|
||
651 @ args = 0, pretend = 0, frame = 8
|
||
652 @ frame_needed = 1, uses_anonymous_args = 0
|
||
653 0000 80B5 push {r7, lr}
|
||
654 .cfi_def_cfa_offset 8
|
||
655 .cfi_offset 7, -8
|
||
656 .cfi_offset 14, -4
|
||
657 0002 82B0 sub sp, sp, #8
|
||
658 .cfi_def_cfa_offset 16
|
||
659 0004 00AF add r7, sp, #0
|
||
660 .cfi_def_cfa_register 7
|
||
661 0006 7860 str r0, [r7, #4]
|
||
319:Core/Src/stm32f3xx_hal_msp.c **** if(hspi->Instance==SPI1)
|
||
662 .loc 1 319 10
|
||
663 0008 7B68 ldr r3, [r7, #4]
|
||
664 000a 1B68 ldr r3, [r3]
|
||
665 .loc 1 319 5
|
||
666 000c 084A ldr r2, .L34
|
||
667 000e 9342 cmp r3, r2
|
||
668 0010 0AD1 bne .L33
|
||
320:Core/Src/stm32f3xx_hal_msp.c **** {
|
||
321:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN SPI1_MspDeInit 0 */
|
||
322:Core/Src/stm32f3xx_hal_msp.c ****
|
||
323:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END SPI1_MspDeInit 0 */
|
||
324:Core/Src/stm32f3xx_hal_msp.c **** /* Peripheral clock disable */
|
||
325:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_SPI1_CLK_DISABLE();
|
||
669 .loc 1 325 5
|
||
670 0012 084B ldr r3, .L34+4
|
||
671 0014 9B69 ldr r3, [r3, #24]
|
||
672 0016 074A ldr r2, .L34+4
|
||
673 0018 23F48053 bic r3, r3, #4096
|
||
674 001c 9361 str r3, [r2, #24]
|
||
326:Core/Src/stm32f3xx_hal_msp.c ****
|
||
327:Core/Src/stm32f3xx_hal_msp.c **** /**SPI1 GPIO Configuration
|
||
328:Core/Src/stm32f3xx_hal_msp.c **** PA5 ------> SPI1_SCK
|
||
329:Core/Src/stm32f3xx_hal_msp.c **** PA6 ------> SPI1_MISO
|
||
330:Core/Src/stm32f3xx_hal_msp.c **** PA7 ------> SPI1_MOSI
|
||
331:Core/Src/stm32f3xx_hal_msp.c **** */
|
||
332:Core/Src/stm32f3xx_hal_msp.c **** HAL_GPIO_DeInit(GPIOA, GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7);
|
||
675 .loc 1 332 5
|
||
676 001e E021 movs r1, #224
|
||
677 0020 4FF09040 mov r0, #1207959552
|
||
678 0024 FFF7FEFF bl HAL_GPIO_DeInit
|
||
679 .L33:
|
||
333:Core/Src/stm32f3xx_hal_msp.c ****
|
||
334:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN SPI1_MspDeInit 1 */
|
||
335:Core/Src/stm32f3xx_hal_msp.c ****
|
||
336:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END SPI1_MspDeInit 1 */
|
||
337:Core/Src/stm32f3xx_hal_msp.c **** }
|
||
338:Core/Src/stm32f3xx_hal_msp.c ****
|
||
339:Core/Src/stm32f3xx_hal_msp.c **** }
|
||
680 .loc 1 339 1
|
||
681 0028 00BF nop
|
||
682 002a 0837 adds r7, r7, #8
|
||
683 .cfi_def_cfa_offset 8
|
||
684 002c BD46 mov sp, r7
|
||
685 .cfi_def_cfa_register 13
|
||
ARM GAS /tmp/cc61sY4U.s page 19
|
||
|
||
|
||
686 @ sp needed
|
||
687 002e 80BD pop {r7, pc}
|
||
688 .L35:
|
||
689 .align 2
|
||
690 .L34:
|
||
691 0030 00300140 .word 1073819648
|
||
692 0034 00100240 .word 1073876992
|
||
693 .cfi_endproc
|
||
694 .LFE136:
|
||
696 .section .text.HAL_TIM_PWM_MspInit,"ax",%progbits
|
||
697 .align 1
|
||
698 .global HAL_TIM_PWM_MspInit
|
||
699 .syntax unified
|
||
700 .thumb
|
||
701 .thumb_func
|
||
703 HAL_TIM_PWM_MspInit:
|
||
704 .LFB137:
|
||
340:Core/Src/stm32f3xx_hal_msp.c ****
|
||
341:Core/Src/stm32f3xx_hal_msp.c **** /**
|
||
342:Core/Src/stm32f3xx_hal_msp.c **** * @brief TIM_PWM MSP Initialization
|
||
343:Core/Src/stm32f3xx_hal_msp.c **** * This function configures the hardware resources used in this example
|
||
344:Core/Src/stm32f3xx_hal_msp.c **** * @param htim_pwm: TIM_PWM handle pointer
|
||
345:Core/Src/stm32f3xx_hal_msp.c **** * @retval None
|
||
346:Core/Src/stm32f3xx_hal_msp.c **** */
|
||
347:Core/Src/stm32f3xx_hal_msp.c **** void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef* htim_pwm)
|
||
348:Core/Src/stm32f3xx_hal_msp.c **** {
|
||
705 .loc 1 348 1
|
||
706 .cfi_startproc
|
||
707 @ args = 0, pretend = 0, frame = 24
|
||
708 @ frame_needed = 1, uses_anonymous_args = 0
|
||
709 @ link register save eliminated.
|
||
710 0000 80B4 push {r7}
|
||
711 .cfi_def_cfa_offset 4
|
||
712 .cfi_offset 7, -4
|
||
713 0002 87B0 sub sp, sp, #28
|
||
714 .cfi_def_cfa_offset 32
|
||
715 0004 00AF add r7, sp, #0
|
||
716 .cfi_def_cfa_register 7
|
||
717 0006 7860 str r0, [r7, #4]
|
||
349:Core/Src/stm32f3xx_hal_msp.c **** if(htim_pwm->Instance==TIM2)
|
||
718 .loc 1 349 14
|
||
719 0008 7B68 ldr r3, [r7, #4]
|
||
720 000a 1B68 ldr r3, [r3]
|
||
721 .loc 1 349 5
|
||
722 000c B3F1804F cmp r3, #1073741824
|
||
723 0010 0CD1 bne .L37
|
||
724 .LBB13:
|
||
350:Core/Src/stm32f3xx_hal_msp.c **** {
|
||
351:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN TIM2_MspInit 0 */
|
||
352:Core/Src/stm32f3xx_hal_msp.c ****
|
||
353:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END TIM2_MspInit 0 */
|
||
354:Core/Src/stm32f3xx_hal_msp.c **** /* Peripheral clock enable */
|
||
355:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_TIM2_CLK_ENABLE();
|
||
725 .loc 1 355 5
|
||
726 0012 244B ldr r3, .L42
|
||
727 0014 DB69 ldr r3, [r3, #28]
|
||
728 0016 234A ldr r2, .L42
|
||
ARM GAS /tmp/cc61sY4U.s page 20
|
||
|
||
|
||
729 0018 43F00103 orr r3, r3, #1
|
||
730 001c D361 str r3, [r2, #28]
|
||
731 001e 214B ldr r3, .L42
|
||
732 0020 DB69 ldr r3, [r3, #28]
|
||
733 0022 03F00103 and r3, r3, #1
|
||
734 0026 7B61 str r3, [r7, #20]
|
||
735 0028 7B69 ldr r3, [r7, #20]
|
||
736 .LBE13:
|
||
356:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN TIM2_MspInit 1 */
|
||
357:Core/Src/stm32f3xx_hal_msp.c ****
|
||
358:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END TIM2_MspInit 1 */
|
||
359:Core/Src/stm32f3xx_hal_msp.c **** }
|
||
360:Core/Src/stm32f3xx_hal_msp.c **** else if(htim_pwm->Instance==TIM3)
|
||
361:Core/Src/stm32f3xx_hal_msp.c **** {
|
||
362:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN TIM3_MspInit 0 */
|
||
363:Core/Src/stm32f3xx_hal_msp.c ****
|
||
364:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END TIM3_MspInit 0 */
|
||
365:Core/Src/stm32f3xx_hal_msp.c **** /* Peripheral clock enable */
|
||
366:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_TIM3_CLK_ENABLE();
|
||
367:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN TIM3_MspInit 1 */
|
||
368:Core/Src/stm32f3xx_hal_msp.c ****
|
||
369:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END TIM3_MspInit 1 */
|
||
370:Core/Src/stm32f3xx_hal_msp.c **** }
|
||
371:Core/Src/stm32f3xx_hal_msp.c **** else if(htim_pwm->Instance==TIM4)
|
||
372:Core/Src/stm32f3xx_hal_msp.c **** {
|
||
373:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN TIM4_MspInit 0 */
|
||
374:Core/Src/stm32f3xx_hal_msp.c ****
|
||
375:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END TIM4_MspInit 0 */
|
||
376:Core/Src/stm32f3xx_hal_msp.c **** /* Peripheral clock enable */
|
||
377:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_TIM4_CLK_ENABLE();
|
||
378:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN TIM4_MspInit 1 */
|
||
379:Core/Src/stm32f3xx_hal_msp.c ****
|
||
380:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END TIM4_MspInit 1 */
|
||
381:Core/Src/stm32f3xx_hal_msp.c **** }
|
||
382:Core/Src/stm32f3xx_hal_msp.c **** else if(htim_pwm->Instance==TIM15)
|
||
383:Core/Src/stm32f3xx_hal_msp.c **** {
|
||
384:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN TIM15_MspInit 0 */
|
||
385:Core/Src/stm32f3xx_hal_msp.c ****
|
||
386:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END TIM15_MspInit 0 */
|
||
387:Core/Src/stm32f3xx_hal_msp.c **** /* Peripheral clock enable */
|
||
388:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_TIM15_CLK_ENABLE();
|
||
389:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN TIM15_MspInit 1 */
|
||
390:Core/Src/stm32f3xx_hal_msp.c ****
|
||
391:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END TIM15_MspInit 1 */
|
||
392:Core/Src/stm32f3xx_hal_msp.c **** }
|
||
393:Core/Src/stm32f3xx_hal_msp.c ****
|
||
394:Core/Src/stm32f3xx_hal_msp.c **** }
|
||
737 .loc 1 394 1
|
||
738 002a 34E0 b .L41
|
||
739 .L37:
|
||
360:Core/Src/stm32f3xx_hal_msp.c **** {
|
||
740 .loc 1 360 19
|
||
741 002c 7B68 ldr r3, [r7, #4]
|
||
742 002e 1B68 ldr r3, [r3]
|
||
360:Core/Src/stm32f3xx_hal_msp.c **** {
|
||
743 .loc 1 360 10
|
||
744 0030 1D4A ldr r2, .L42+4
|
||
ARM GAS /tmp/cc61sY4U.s page 21
|
||
|
||
|
||
745 0032 9342 cmp r3, r2
|
||
746 0034 0CD1 bne .L39
|
||
747 .LBB14:
|
||
366:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN TIM3_MspInit 1 */
|
||
748 .loc 1 366 5
|
||
749 0036 1B4B ldr r3, .L42
|
||
750 0038 DB69 ldr r3, [r3, #28]
|
||
751 003a 1A4A ldr r2, .L42
|
||
752 003c 43F00203 orr r3, r3, #2
|
||
753 0040 D361 str r3, [r2, #28]
|
||
754 0042 184B ldr r3, .L42
|
||
755 0044 DB69 ldr r3, [r3, #28]
|
||
756 0046 03F00203 and r3, r3, #2
|
||
757 004a 3B61 str r3, [r7, #16]
|
||
758 004c 3B69 ldr r3, [r7, #16]
|
||
759 .LBE14:
|
||
760 .loc 1 394 1
|
||
761 004e 22E0 b .L41
|
||
762 .L39:
|
||
371:Core/Src/stm32f3xx_hal_msp.c **** {
|
||
763 .loc 1 371 19
|
||
764 0050 7B68 ldr r3, [r7, #4]
|
||
765 0052 1B68 ldr r3, [r3]
|
||
371:Core/Src/stm32f3xx_hal_msp.c **** {
|
||
766 .loc 1 371 10
|
||
767 0054 154A ldr r2, .L42+8
|
||
768 0056 9342 cmp r3, r2
|
||
769 0058 0CD1 bne .L40
|
||
770 .LBB15:
|
||
377:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN TIM4_MspInit 1 */
|
||
771 .loc 1 377 5
|
||
772 005a 124B ldr r3, .L42
|
||
773 005c DB69 ldr r3, [r3, #28]
|
||
774 005e 114A ldr r2, .L42
|
||
775 0060 43F00403 orr r3, r3, #4
|
||
776 0064 D361 str r3, [r2, #28]
|
||
777 0066 0F4B ldr r3, .L42
|
||
778 0068 DB69 ldr r3, [r3, #28]
|
||
779 006a 03F00403 and r3, r3, #4
|
||
780 006e FB60 str r3, [r7, #12]
|
||
781 0070 FB68 ldr r3, [r7, #12]
|
||
782 .LBE15:
|
||
783 .loc 1 394 1
|
||
784 0072 10E0 b .L41
|
||
785 .L40:
|
||
382:Core/Src/stm32f3xx_hal_msp.c **** {
|
||
786 .loc 1 382 19
|
||
787 0074 7B68 ldr r3, [r7, #4]
|
||
788 0076 1B68 ldr r3, [r3]
|
||
382:Core/Src/stm32f3xx_hal_msp.c **** {
|
||
789 .loc 1 382 10
|
||
790 0078 0D4A ldr r2, .L42+12
|
||
791 007a 9342 cmp r3, r2
|
||
792 007c 0BD1 bne .L41
|
||
793 .LBB16:
|
||
388:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN TIM15_MspInit 1 */
|
||
794 .loc 1 388 5
|
||
ARM GAS /tmp/cc61sY4U.s page 22
|
||
|
||
|
||
795 007e 094B ldr r3, .L42
|
||
796 0080 9B69 ldr r3, [r3, #24]
|
||
797 0082 084A ldr r2, .L42
|
||
798 0084 43F48033 orr r3, r3, #65536
|
||
799 0088 9361 str r3, [r2, #24]
|
||
800 008a 064B ldr r3, .L42
|
||
801 008c 9B69 ldr r3, [r3, #24]
|
||
802 008e 03F48033 and r3, r3, #65536
|
||
803 0092 BB60 str r3, [r7, #8]
|
||
804 0094 BB68 ldr r3, [r7, #8]
|
||
805 .L41:
|
||
806 .LBE16:
|
||
807 .loc 1 394 1
|
||
808 0096 00BF nop
|
||
809 0098 1C37 adds r7, r7, #28
|
||
810 .cfi_def_cfa_offset 4
|
||
811 009a BD46 mov sp, r7
|
||
812 .cfi_def_cfa_register 13
|
||
813 @ sp needed
|
||
814 009c 5DF8047B ldr r7, [sp], #4
|
||
815 .cfi_restore 7
|
||
816 .cfi_def_cfa_offset 0
|
||
817 00a0 7047 bx lr
|
||
818 .L43:
|
||
819 00a2 00BF .align 2
|
||
820 .L42:
|
||
821 00a4 00100240 .word 1073876992
|
||
822 00a8 00040040 .word 1073742848
|
||
823 00ac 00080040 .word 1073743872
|
||
824 00b0 00400140 .word 1073823744
|
||
825 .cfi_endproc
|
||
826 .LFE137:
|
||
828 .section .text.HAL_TIM_MspPostInit,"ax",%progbits
|
||
829 .align 1
|
||
830 .global HAL_TIM_MspPostInit
|
||
831 .syntax unified
|
||
832 .thumb
|
||
833 .thumb_func
|
||
835 HAL_TIM_MspPostInit:
|
||
836 .LFB138:
|
||
395:Core/Src/stm32f3xx_hal_msp.c ****
|
||
396:Core/Src/stm32f3xx_hal_msp.c **** void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
|
||
397:Core/Src/stm32f3xx_hal_msp.c **** {
|
||
837 .loc 1 397 1
|
||
838 .cfi_startproc
|
||
839 @ args = 0, pretend = 0, frame = 48
|
||
840 @ frame_needed = 1, uses_anonymous_args = 0
|
||
841 0000 80B5 push {r7, lr}
|
||
842 .cfi_def_cfa_offset 8
|
||
843 .cfi_offset 7, -8
|
||
844 .cfi_offset 14, -4
|
||
845 0002 8CB0 sub sp, sp, #48
|
||
846 .cfi_def_cfa_offset 56
|
||
847 0004 00AF add r7, sp, #0
|
||
848 .cfi_def_cfa_register 7
|
||
849 0006 7860 str r0, [r7, #4]
|
||
398:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitTypeDef GPIO_InitStruct = {0};
|
||
ARM GAS /tmp/cc61sY4U.s page 23
|
||
|
||
|
||
850 .loc 1 398 20
|
||
851 0008 07F11C03 add r3, r7, #28
|
||
852 000c 0022 movs r2, #0
|
||
853 000e 1A60 str r2, [r3]
|
||
854 0010 5A60 str r2, [r3, #4]
|
||
855 0012 9A60 str r2, [r3, #8]
|
||
856 0014 DA60 str r2, [r3, #12]
|
||
857 0016 1A61 str r2, [r3, #16]
|
||
399:Core/Src/stm32f3xx_hal_msp.c **** if(htim->Instance==TIM2)
|
||
858 .loc 1 399 10
|
||
859 0018 7B68 ldr r3, [r7, #4]
|
||
860 001a 1B68 ldr r3, [r3]
|
||
861 .loc 1 399 5
|
||
862 001c B3F1804F cmp r3, #1073741824
|
||
863 0020 1DD1 bne .L45
|
||
864 .LBB17:
|
||
400:Core/Src/stm32f3xx_hal_msp.c **** {
|
||
401:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN TIM2_MspPostInit 0 */
|
||
402:Core/Src/stm32f3xx_hal_msp.c ****
|
||
403:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END TIM2_MspPostInit 0 */
|
||
404:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_GPIOB_CLK_ENABLE();
|
||
865 .loc 1 404 5
|
||
866 0022 444B ldr r3, .L50
|
||
867 0024 5B69 ldr r3, [r3, #20]
|
||
868 0026 434A ldr r2, .L50
|
||
869 0028 43F48023 orr r3, r3, #262144
|
||
870 002c 5361 str r3, [r2, #20]
|
||
871 002e 414B ldr r3, .L50
|
||
872 0030 5B69 ldr r3, [r3, #20]
|
||
873 0032 03F48023 and r3, r3, #262144
|
||
874 0036 BB61 str r3, [r7, #24]
|
||
875 0038 BB69 ldr r3, [r7, #24]
|
||
876 .LBE17:
|
||
405:Core/Src/stm32f3xx_hal_msp.c **** /**TIM2 GPIO Configuration
|
||
406:Core/Src/stm32f3xx_hal_msp.c **** PB10 ------> TIM2_CH3
|
||
407:Core/Src/stm32f3xx_hal_msp.c **** PB11 ------> TIM2_CH4
|
||
408:Core/Src/stm32f3xx_hal_msp.c **** */
|
||
409:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Pin = BAT_COOLING_PWM_Pin|BAT_COOLING_ENABLE_Pin;
|
||
877 .loc 1 409 25
|
||
878 003a 4FF44063 mov r3, #3072
|
||
879 003e FB61 str r3, [r7, #28]
|
||
410:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||
880 .loc 1 410 26
|
||
881 0040 0223 movs r3, #2
|
||
882 0042 3B62 str r3, [r7, #32]
|
||
411:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||
883 .loc 1 411 26
|
||
884 0044 0023 movs r3, #0
|
||
885 0046 7B62 str r3, [r7, #36]
|
||
412:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
||
886 .loc 1 412 27
|
||
887 0048 0023 movs r3, #0
|
||
888 004a BB62 str r3, [r7, #40]
|
||
413:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF1_TIM2;
|
||
889 .loc 1 413 31
|
||
890 004c 0123 movs r3, #1
|
||
891 004e FB62 str r3, [r7, #44]
|
||
ARM GAS /tmp/cc61sY4U.s page 24
|
||
|
||
|
||
414:Core/Src/stm32f3xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
||
892 .loc 1 414 5
|
||
893 0050 07F11C03 add r3, r7, #28
|
||
894 0054 1946 mov r1, r3
|
||
895 0056 3848 ldr r0, .L50+4
|
||
896 0058 FFF7FEFF bl HAL_GPIO_Init
|
||
415:Core/Src/stm32f3xx_hal_msp.c ****
|
||
416:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN TIM2_MspPostInit 1 */
|
||
417:Core/Src/stm32f3xx_hal_msp.c ****
|
||
418:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END TIM2_MspPostInit 1 */
|
||
419:Core/Src/stm32f3xx_hal_msp.c **** }
|
||
420:Core/Src/stm32f3xx_hal_msp.c **** else if(htim->Instance==TIM3)
|
||
421:Core/Src/stm32f3xx_hal_msp.c **** {
|
||
422:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN TIM3_MspPostInit 0 */
|
||
423:Core/Src/stm32f3xx_hal_msp.c ****
|
||
424:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END TIM3_MspPostInit 0 */
|
||
425:Core/Src/stm32f3xx_hal_msp.c ****
|
||
426:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_GPIOB_CLK_ENABLE();
|
||
427:Core/Src/stm32f3xx_hal_msp.c **** /**TIM3 GPIO Configuration
|
||
428:Core/Src/stm32f3xx_hal_msp.c **** PB0 ------> TIM3_CH3
|
||
429:Core/Src/stm32f3xx_hal_msp.c **** PB1 ------> TIM3_CH4
|
||
430:Core/Src/stm32f3xx_hal_msp.c **** */
|
||
431:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Pin = ESC_L_PWM_Pin|ESC_R_PWM_Pin;
|
||
432:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||
433:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||
434:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
||
435:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF2_TIM3;
|
||
436:Core/Src/stm32f3xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
||
437:Core/Src/stm32f3xx_hal_msp.c ****
|
||
438:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN TIM3_MspPostInit 1 */
|
||
439:Core/Src/stm32f3xx_hal_msp.c ****
|
||
440:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END TIM3_MspPostInit 1 */
|
||
441:Core/Src/stm32f3xx_hal_msp.c **** }
|
||
442:Core/Src/stm32f3xx_hal_msp.c **** else if(htim->Instance==TIM4)
|
||
443:Core/Src/stm32f3xx_hal_msp.c **** {
|
||
444:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN TIM4_MspPostInit 0 */
|
||
445:Core/Src/stm32f3xx_hal_msp.c ****
|
||
446:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END TIM4_MspPostInit 0 */
|
||
447:Core/Src/stm32f3xx_hal_msp.c ****
|
||
448:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_GPIOB_CLK_ENABLE();
|
||
449:Core/Src/stm32f3xx_hal_msp.c **** /**TIM4 GPIO Configuration
|
||
450:Core/Src/stm32f3xx_hal_msp.c **** PB6 ------> TIM4_CH1
|
||
451:Core/Src/stm32f3xx_hal_msp.c **** PB7 ------> TIM4_CH2
|
||
452:Core/Src/stm32f3xx_hal_msp.c **** PB8 ------> TIM4_CH3
|
||
453:Core/Src/stm32f3xx_hal_msp.c **** */
|
||
454:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Pin = STATUS_LED_R_Pin|STATUS_LED_G_Pin|STATUS_LED_B_Pin;
|
||
455:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||
456:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_PULLDOWN;
|
||
457:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
||
458:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF2_TIM4;
|
||
459:Core/Src/stm32f3xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
||
460:Core/Src/stm32f3xx_hal_msp.c ****
|
||
461:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN TIM4_MspPostInit 1 */
|
||
462:Core/Src/stm32f3xx_hal_msp.c ****
|
||
463:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END TIM4_MspPostInit 1 */
|
||
464:Core/Src/stm32f3xx_hal_msp.c **** }
|
||
465:Core/Src/stm32f3xx_hal_msp.c **** else if(htim->Instance==TIM15)
|
||
ARM GAS /tmp/cc61sY4U.s page 25
|
||
|
||
|
||
466:Core/Src/stm32f3xx_hal_msp.c **** {
|
||
467:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN TIM15_MspPostInit 0 */
|
||
468:Core/Src/stm32f3xx_hal_msp.c ****
|
||
469:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END TIM15_MspPostInit 0 */
|
||
470:Core/Src/stm32f3xx_hal_msp.c ****
|
||
471:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_GPIOB_CLK_ENABLE();
|
||
472:Core/Src/stm32f3xx_hal_msp.c **** /**TIM15 GPIO Configuration
|
||
473:Core/Src/stm32f3xx_hal_msp.c **** PB14 ------> TIM15_CH1
|
||
474:Core/Src/stm32f3xx_hal_msp.c **** PB15 ------> TIM15_CH2
|
||
475:Core/Src/stm32f3xx_hal_msp.c **** */
|
||
476:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Pin = ESC_COOLING_ENABLE_Pin|ESC_COOLING_PWM_Pin;
|
||
477:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||
478:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||
479:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
||
480:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF1_TIM15;
|
||
481:Core/Src/stm32f3xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
||
482:Core/Src/stm32f3xx_hal_msp.c ****
|
||
483:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN TIM15_MspPostInit 1 */
|
||
484:Core/Src/stm32f3xx_hal_msp.c ****
|
||
485:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END TIM15_MspPostInit 1 */
|
||
486:Core/Src/stm32f3xx_hal_msp.c **** }
|
||
487:Core/Src/stm32f3xx_hal_msp.c ****
|
||
488:Core/Src/stm32f3xx_hal_msp.c **** }
|
||
897 .loc 1 488 1
|
||
898 005c 66E0 b .L49
|
||
899 .L45:
|
||
420:Core/Src/stm32f3xx_hal_msp.c **** {
|
||
900 .loc 1 420 15
|
||
901 005e 7B68 ldr r3, [r7, #4]
|
||
902 0060 1B68 ldr r3, [r3]
|
||
420:Core/Src/stm32f3xx_hal_msp.c **** {
|
||
903 .loc 1 420 10
|
||
904 0062 364A ldr r2, .L50+8
|
||
905 0064 9342 cmp r3, r2
|
||
906 0066 1CD1 bne .L47
|
||
907 .LBB18:
|
||
426:Core/Src/stm32f3xx_hal_msp.c **** /**TIM3 GPIO Configuration
|
||
908 .loc 1 426 5
|
||
909 0068 324B ldr r3, .L50
|
||
910 006a 5B69 ldr r3, [r3, #20]
|
||
911 006c 314A ldr r2, .L50
|
||
912 006e 43F48023 orr r3, r3, #262144
|
||
913 0072 5361 str r3, [r2, #20]
|
||
914 0074 2F4B ldr r3, .L50
|
||
915 0076 5B69 ldr r3, [r3, #20]
|
||
916 0078 03F48023 and r3, r3, #262144
|
||
917 007c 7B61 str r3, [r7, #20]
|
||
918 007e 7B69 ldr r3, [r7, #20]
|
||
919 .LBE18:
|
||
431:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||
920 .loc 1 431 25
|
||
921 0080 0323 movs r3, #3
|
||
922 0082 FB61 str r3, [r7, #28]
|
||
432:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||
923 .loc 1 432 26
|
||
924 0084 0223 movs r3, #2
|
||
925 0086 3B62 str r3, [r7, #32]
|
||
ARM GAS /tmp/cc61sY4U.s page 26
|
||
|
||
|
||
433:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
||
926 .loc 1 433 26
|
||
927 0088 0023 movs r3, #0
|
||
928 008a 7B62 str r3, [r7, #36]
|
||
434:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF2_TIM3;
|
||
929 .loc 1 434 27
|
||
930 008c 0023 movs r3, #0
|
||
931 008e BB62 str r3, [r7, #40]
|
||
435:Core/Src/stm32f3xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
||
932 .loc 1 435 31
|
||
933 0090 0223 movs r3, #2
|
||
934 0092 FB62 str r3, [r7, #44]
|
||
436:Core/Src/stm32f3xx_hal_msp.c ****
|
||
935 .loc 1 436 5
|
||
936 0094 07F11C03 add r3, r7, #28
|
||
937 0098 1946 mov r1, r3
|
||
938 009a 2748 ldr r0, .L50+4
|
||
939 009c FFF7FEFF bl HAL_GPIO_Init
|
||
940 .loc 1 488 1
|
||
941 00a0 44E0 b .L49
|
||
942 .L47:
|
||
442:Core/Src/stm32f3xx_hal_msp.c **** {
|
||
943 .loc 1 442 15
|
||
944 00a2 7B68 ldr r3, [r7, #4]
|
||
945 00a4 1B68 ldr r3, [r3]
|
||
442:Core/Src/stm32f3xx_hal_msp.c **** {
|
||
946 .loc 1 442 10
|
||
947 00a6 264A ldr r2, .L50+12
|
||
948 00a8 9342 cmp r3, r2
|
||
949 00aa 1DD1 bne .L48
|
||
950 .LBB19:
|
||
448:Core/Src/stm32f3xx_hal_msp.c **** /**TIM4 GPIO Configuration
|
||
951 .loc 1 448 5
|
||
952 00ac 214B ldr r3, .L50
|
||
953 00ae 5B69 ldr r3, [r3, #20]
|
||
954 00b0 204A ldr r2, .L50
|
||
955 00b2 43F48023 orr r3, r3, #262144
|
||
956 00b6 5361 str r3, [r2, #20]
|
||
957 00b8 1E4B ldr r3, .L50
|
||
958 00ba 5B69 ldr r3, [r3, #20]
|
||
959 00bc 03F48023 and r3, r3, #262144
|
||
960 00c0 3B61 str r3, [r7, #16]
|
||
961 00c2 3B69 ldr r3, [r7, #16]
|
||
962 .LBE19:
|
||
454:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||
963 .loc 1 454 25
|
||
964 00c4 4FF4E073 mov r3, #448
|
||
965 00c8 FB61 str r3, [r7, #28]
|
||
455:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_PULLDOWN;
|
||
966 .loc 1 455 26
|
||
967 00ca 0223 movs r3, #2
|
||
968 00cc 3B62 str r3, [r7, #32]
|
||
456:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
||
969 .loc 1 456 26
|
||
970 00ce 0223 movs r3, #2
|
||
971 00d0 7B62 str r3, [r7, #36]
|
||
457:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF2_TIM4;
|
||
ARM GAS /tmp/cc61sY4U.s page 27
|
||
|
||
|
||
972 .loc 1 457 27
|
||
973 00d2 0023 movs r3, #0
|
||
974 00d4 BB62 str r3, [r7, #40]
|
||
458:Core/Src/stm32f3xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
||
975 .loc 1 458 31
|
||
976 00d6 0223 movs r3, #2
|
||
977 00d8 FB62 str r3, [r7, #44]
|
||
459:Core/Src/stm32f3xx_hal_msp.c ****
|
||
978 .loc 1 459 5
|
||
979 00da 07F11C03 add r3, r7, #28
|
||
980 00de 1946 mov r1, r3
|
||
981 00e0 1548 ldr r0, .L50+4
|
||
982 00e2 FFF7FEFF bl HAL_GPIO_Init
|
||
983 .loc 1 488 1
|
||
984 00e6 21E0 b .L49
|
||
985 .L48:
|
||
465:Core/Src/stm32f3xx_hal_msp.c **** {
|
||
986 .loc 1 465 15
|
||
987 00e8 7B68 ldr r3, [r7, #4]
|
||
988 00ea 1B68 ldr r3, [r3]
|
||
465:Core/Src/stm32f3xx_hal_msp.c **** {
|
||
989 .loc 1 465 10
|
||
990 00ec 154A ldr r2, .L50+16
|
||
991 00ee 9342 cmp r3, r2
|
||
992 00f0 1CD1 bne .L49
|
||
993 .LBB20:
|
||
471:Core/Src/stm32f3xx_hal_msp.c **** /**TIM15 GPIO Configuration
|
||
994 .loc 1 471 5
|
||
995 00f2 104B ldr r3, .L50
|
||
996 00f4 5B69 ldr r3, [r3, #20]
|
||
997 00f6 0F4A ldr r2, .L50
|
||
998 00f8 43F48023 orr r3, r3, #262144
|
||
999 00fc 5361 str r3, [r2, #20]
|
||
1000 00fe 0D4B ldr r3, .L50
|
||
1001 0100 5B69 ldr r3, [r3, #20]
|
||
1002 0102 03F48023 and r3, r3, #262144
|
||
1003 0106 FB60 str r3, [r7, #12]
|
||
1004 0108 FB68 ldr r3, [r7, #12]
|
||
1005 .LBE20:
|
||
476:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||
1006 .loc 1 476 25
|
||
1007 010a 4FF44043 mov r3, #49152
|
||
1008 010e FB61 str r3, [r7, #28]
|
||
477:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||
1009 .loc 1 477 26
|
||
1010 0110 0223 movs r3, #2
|
||
1011 0112 3B62 str r3, [r7, #32]
|
||
478:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
||
1012 .loc 1 478 26
|
||
1013 0114 0023 movs r3, #0
|
||
1014 0116 7B62 str r3, [r7, #36]
|
||
479:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF1_TIM15;
|
||
1015 .loc 1 479 27
|
||
1016 0118 0023 movs r3, #0
|
||
1017 011a BB62 str r3, [r7, #40]
|
||
480:Core/Src/stm32f3xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
||
1018 .loc 1 480 31
|
||
ARM GAS /tmp/cc61sY4U.s page 28
|
||
|
||
|
||
1019 011c 0123 movs r3, #1
|
||
1020 011e FB62 str r3, [r7, #44]
|
||
481:Core/Src/stm32f3xx_hal_msp.c ****
|
||
1021 .loc 1 481 5
|
||
1022 0120 07F11C03 add r3, r7, #28
|
||
1023 0124 1946 mov r1, r3
|
||
1024 0126 0448 ldr r0, .L50+4
|
||
1025 0128 FFF7FEFF bl HAL_GPIO_Init
|
||
1026 .L49:
|
||
1027 .loc 1 488 1
|
||
1028 012c 00BF nop
|
||
1029 012e 3037 adds r7, r7, #48
|
||
1030 .cfi_def_cfa_offset 8
|
||
1031 0130 BD46 mov sp, r7
|
||
1032 .cfi_def_cfa_register 13
|
||
1033 @ sp needed
|
||
1034 0132 80BD pop {r7, pc}
|
||
1035 .L51:
|
||
1036 .align 2
|
||
1037 .L50:
|
||
1038 0134 00100240 .word 1073876992
|
||
1039 0138 00040048 .word 1207960576
|
||
1040 013c 00040040 .word 1073742848
|
||
1041 0140 00080040 .word 1073743872
|
||
1042 0144 00400140 .word 1073823744
|
||
1043 .cfi_endproc
|
||
1044 .LFE138:
|
||
1046 .section .text.HAL_TIM_PWM_MspDeInit,"ax",%progbits
|
||
1047 .align 1
|
||
1048 .global HAL_TIM_PWM_MspDeInit
|
||
1049 .syntax unified
|
||
1050 .thumb
|
||
1051 .thumb_func
|
||
1053 HAL_TIM_PWM_MspDeInit:
|
||
1054 .LFB139:
|
||
489:Core/Src/stm32f3xx_hal_msp.c **** /**
|
||
490:Core/Src/stm32f3xx_hal_msp.c **** * @brief TIM_PWM MSP De-Initialization
|
||
491:Core/Src/stm32f3xx_hal_msp.c **** * This function freeze the hardware resources used in this example
|
||
492:Core/Src/stm32f3xx_hal_msp.c **** * @param htim_pwm: TIM_PWM handle pointer
|
||
493:Core/Src/stm32f3xx_hal_msp.c **** * @retval None
|
||
494:Core/Src/stm32f3xx_hal_msp.c **** */
|
||
495:Core/Src/stm32f3xx_hal_msp.c **** void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef* htim_pwm)
|
||
496:Core/Src/stm32f3xx_hal_msp.c **** {
|
||
1055 .loc 1 496 1
|
||
1056 .cfi_startproc
|
||
1057 @ args = 0, pretend = 0, frame = 8
|
||
1058 @ frame_needed = 1, uses_anonymous_args = 0
|
||
1059 @ link register save eliminated.
|
||
1060 0000 80B4 push {r7}
|
||
1061 .cfi_def_cfa_offset 4
|
||
1062 .cfi_offset 7, -4
|
||
1063 0002 83B0 sub sp, sp, #12
|
||
1064 .cfi_def_cfa_offset 16
|
||
1065 0004 00AF add r7, sp, #0
|
||
1066 .cfi_def_cfa_register 7
|
||
1067 0006 7860 str r0, [r7, #4]
|
||
497:Core/Src/stm32f3xx_hal_msp.c **** if(htim_pwm->Instance==TIM2)
|
||
ARM GAS /tmp/cc61sY4U.s page 29
|
||
|
||
|
||
1068 .loc 1 497 14
|
||
1069 0008 7B68 ldr r3, [r7, #4]
|
||
1070 000a 1B68 ldr r3, [r3]
|
||
1071 .loc 1 497 5
|
||
1072 000c B3F1804F cmp r3, #1073741824
|
||
1073 0010 06D1 bne .L53
|
||
498:Core/Src/stm32f3xx_hal_msp.c **** {
|
||
499:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN TIM2_MspDeInit 0 */
|
||
500:Core/Src/stm32f3xx_hal_msp.c ****
|
||
501:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END TIM2_MspDeInit 0 */
|
||
502:Core/Src/stm32f3xx_hal_msp.c **** /* Peripheral clock disable */
|
||
503:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_TIM2_CLK_DISABLE();
|
||
1074 .loc 1 503 5
|
||
1075 0012 184B ldr r3, .L58
|
||
1076 0014 DB69 ldr r3, [r3, #28]
|
||
1077 0016 174A ldr r2, .L58
|
||
1078 0018 23F00103 bic r3, r3, #1
|
||
1079 001c D361 str r3, [r2, #28]
|
||
504:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN TIM2_MspDeInit 1 */
|
||
505:Core/Src/stm32f3xx_hal_msp.c ****
|
||
506:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END TIM2_MspDeInit 1 */
|
||
507:Core/Src/stm32f3xx_hal_msp.c **** }
|
||
508:Core/Src/stm32f3xx_hal_msp.c **** else if(htim_pwm->Instance==TIM3)
|
||
509:Core/Src/stm32f3xx_hal_msp.c **** {
|
||
510:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN TIM3_MspDeInit 0 */
|
||
511:Core/Src/stm32f3xx_hal_msp.c ****
|
||
512:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END TIM3_MspDeInit 0 */
|
||
513:Core/Src/stm32f3xx_hal_msp.c **** /* Peripheral clock disable */
|
||
514:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_TIM3_CLK_DISABLE();
|
||
515:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN TIM3_MspDeInit 1 */
|
||
516:Core/Src/stm32f3xx_hal_msp.c ****
|
||
517:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END TIM3_MspDeInit 1 */
|
||
518:Core/Src/stm32f3xx_hal_msp.c **** }
|
||
519:Core/Src/stm32f3xx_hal_msp.c **** else if(htim_pwm->Instance==TIM4)
|
||
520:Core/Src/stm32f3xx_hal_msp.c **** {
|
||
521:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN TIM4_MspDeInit 0 */
|
||
522:Core/Src/stm32f3xx_hal_msp.c ****
|
||
523:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END TIM4_MspDeInit 0 */
|
||
524:Core/Src/stm32f3xx_hal_msp.c **** /* Peripheral clock disable */
|
||
525:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_TIM4_CLK_DISABLE();
|
||
526:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN TIM4_MspDeInit 1 */
|
||
527:Core/Src/stm32f3xx_hal_msp.c ****
|
||
528:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END TIM4_MspDeInit 1 */
|
||
529:Core/Src/stm32f3xx_hal_msp.c **** }
|
||
530:Core/Src/stm32f3xx_hal_msp.c **** else if(htim_pwm->Instance==TIM15)
|
||
531:Core/Src/stm32f3xx_hal_msp.c **** {
|
||
532:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN TIM15_MspDeInit 0 */
|
||
533:Core/Src/stm32f3xx_hal_msp.c ****
|
||
534:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END TIM15_MspDeInit 0 */
|
||
535:Core/Src/stm32f3xx_hal_msp.c **** /* Peripheral clock disable */
|
||
536:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_TIM15_CLK_DISABLE();
|
||
537:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN TIM15_MspDeInit 1 */
|
||
538:Core/Src/stm32f3xx_hal_msp.c ****
|
||
539:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END TIM15_MspDeInit 1 */
|
||
540:Core/Src/stm32f3xx_hal_msp.c **** }
|
||
541:Core/Src/stm32f3xx_hal_msp.c ****
|
||
542:Core/Src/stm32f3xx_hal_msp.c **** }
|
||
ARM GAS /tmp/cc61sY4U.s page 30
|
||
|
||
|
||
1080 .loc 1 542 1
|
||
1081 001e 22E0 b .L57
|
||
1082 .L53:
|
||
508:Core/Src/stm32f3xx_hal_msp.c **** {
|
||
1083 .loc 1 508 19
|
||
1084 0020 7B68 ldr r3, [r7, #4]
|
||
1085 0022 1B68 ldr r3, [r3]
|
||
508:Core/Src/stm32f3xx_hal_msp.c **** {
|
||
1086 .loc 1 508 10
|
||
1087 0024 144A ldr r2, .L58+4
|
||
1088 0026 9342 cmp r3, r2
|
||
1089 0028 06D1 bne .L55
|
||
514:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN TIM3_MspDeInit 1 */
|
||
1090 .loc 1 514 5
|
||
1091 002a 124B ldr r3, .L58
|
||
1092 002c DB69 ldr r3, [r3, #28]
|
||
1093 002e 114A ldr r2, .L58
|
||
1094 0030 23F00203 bic r3, r3, #2
|
||
1095 0034 D361 str r3, [r2, #28]
|
||
1096 .loc 1 542 1
|
||
1097 0036 16E0 b .L57
|
||
1098 .L55:
|
||
519:Core/Src/stm32f3xx_hal_msp.c **** {
|
||
1099 .loc 1 519 19
|
||
1100 0038 7B68 ldr r3, [r7, #4]
|
||
1101 003a 1B68 ldr r3, [r3]
|
||
519:Core/Src/stm32f3xx_hal_msp.c **** {
|
||
1102 .loc 1 519 10
|
||
1103 003c 0F4A ldr r2, .L58+8
|
||
1104 003e 9342 cmp r3, r2
|
||
1105 0040 06D1 bne .L56
|
||
525:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN TIM4_MspDeInit 1 */
|
||
1106 .loc 1 525 5
|
||
1107 0042 0C4B ldr r3, .L58
|
||
1108 0044 DB69 ldr r3, [r3, #28]
|
||
1109 0046 0B4A ldr r2, .L58
|
||
1110 0048 23F00403 bic r3, r3, #4
|
||
1111 004c D361 str r3, [r2, #28]
|
||
1112 .loc 1 542 1
|
||
1113 004e 0AE0 b .L57
|
||
1114 .L56:
|
||
530:Core/Src/stm32f3xx_hal_msp.c **** {
|
||
1115 .loc 1 530 19
|
||
1116 0050 7B68 ldr r3, [r7, #4]
|
||
1117 0052 1B68 ldr r3, [r3]
|
||
530:Core/Src/stm32f3xx_hal_msp.c **** {
|
||
1118 .loc 1 530 10
|
||
1119 0054 0A4A ldr r2, .L58+12
|
||
1120 0056 9342 cmp r3, r2
|
||
1121 0058 05D1 bne .L57
|
||
536:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN TIM15_MspDeInit 1 */
|
||
1122 .loc 1 536 5
|
||
1123 005a 064B ldr r3, .L58
|
||
1124 005c 9B69 ldr r3, [r3, #24]
|
||
1125 005e 054A ldr r2, .L58
|
||
1126 0060 23F48033 bic r3, r3, #65536
|
||
1127 0064 9361 str r3, [r2, #24]
|
||
ARM GAS /tmp/cc61sY4U.s page 31
|
||
|
||
|
||
1128 .L57:
|
||
1129 .loc 1 542 1
|
||
1130 0066 00BF nop
|
||
1131 0068 0C37 adds r7, r7, #12
|
||
1132 .cfi_def_cfa_offset 4
|
||
1133 006a BD46 mov sp, r7
|
||
1134 .cfi_def_cfa_register 13
|
||
1135 @ sp needed
|
||
1136 006c 5DF8047B ldr r7, [sp], #4
|
||
1137 .cfi_restore 7
|
||
1138 .cfi_def_cfa_offset 0
|
||
1139 0070 7047 bx lr
|
||
1140 .L59:
|
||
1141 0072 00BF .align 2
|
||
1142 .L58:
|
||
1143 0074 00100240 .word 1073876992
|
||
1144 0078 00040040 .word 1073742848
|
||
1145 007c 00080040 .word 1073743872
|
||
1146 0080 00400140 .word 1073823744
|
||
1147 .cfi_endproc
|
||
1148 .LFE139:
|
||
1150 .text
|
||
1151 .Letext0:
|
||
1152 .file 2 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h"
|
||
1153 .file 3 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl
|
||
1154 .file 4 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl
|
||
1155 .file 5 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h"
|
||
1156 .file 6 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h"
|
||
1157 .file 7 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h"
|
||
1158 .file 8 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h"
|
||
1159 .file 9 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h"
|
||
1160 .file 10 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h"
|
||
1161 .file 11 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h"
|
||
1162 .file 12 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h"
|
||
1163 .file 13 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h"
|
||
ARM GAS /tmp/cc61sY4U.s page 32
|
||
|
||
|
||
DEFINED SYMBOLS
|
||
*ABS*:00000000 stm32f3xx_hal_msp.c
|
||
/tmp/cc61sY4U.s:21 .text.HAL_MspInit:00000000 $t
|
||
/tmp/cc61sY4U.s:27 .text.HAL_MspInit:00000000 HAL_MspInit
|
||
/tmp/cc61sY4U.s:81 .text.HAL_MspInit:00000044 $d
|
||
/tmp/cc61sY4U.s:86 .text.HAL_CAN_MspInit:00000000 $t
|
||
/tmp/cc61sY4U.s:92 .text.HAL_CAN_MspInit:00000000 HAL_CAN_MspInit
|
||
/tmp/cc61sY4U.s:196 .text.HAL_CAN_MspInit:000000a0 $d
|
||
/tmp/cc61sY4U.s:202 .text.HAL_CAN_MspDeInit:00000000 $t
|
||
/tmp/cc61sY4U.s:208 .text.HAL_CAN_MspDeInit:00000000 HAL_CAN_MspDeInit
|
||
/tmp/cc61sY4U.s:258 .text.HAL_CAN_MspDeInit:00000040 $d
|
||
/tmp/cc61sY4U.s:264 .text.HAL_I2C_MspInit:00000000 $t
|
||
/tmp/cc61sY4U.s:270 .text.HAL_I2C_MspInit:00000000 HAL_I2C_MspInit
|
||
/tmp/cc61sY4U.s:447 .text.HAL_I2C_MspInit:00000118 $d
|
||
/tmp/cc61sY4U.s:455 .text.HAL_I2C_MspDeInit:00000000 $t
|
||
/tmp/cc61sY4U.s:461 .text.HAL_I2C_MspDeInit:00000000 HAL_I2C_MspDeInit
|
||
/tmp/cc61sY4U.s:533 .text.HAL_I2C_MspDeInit:0000006c $d
|
||
/tmp/cc61sY4U.s:541 .text.HAL_SPI_MspInit:00000000 $t
|
||
/tmp/cc61sY4U.s:547 .text.HAL_SPI_MspInit:00000000 HAL_SPI_MspInit
|
||
/tmp/cc61sY4U.s:635 .text.HAL_SPI_MspInit:0000007c $d
|
||
/tmp/cc61sY4U.s:641 .text.HAL_SPI_MspDeInit:00000000 $t
|
||
/tmp/cc61sY4U.s:647 .text.HAL_SPI_MspDeInit:00000000 HAL_SPI_MspDeInit
|
||
/tmp/cc61sY4U.s:691 .text.HAL_SPI_MspDeInit:00000030 $d
|
||
/tmp/cc61sY4U.s:697 .text.HAL_TIM_PWM_MspInit:00000000 $t
|
||
/tmp/cc61sY4U.s:703 .text.HAL_TIM_PWM_MspInit:00000000 HAL_TIM_PWM_MspInit
|
||
/tmp/cc61sY4U.s:821 .text.HAL_TIM_PWM_MspInit:000000a4 $d
|
||
/tmp/cc61sY4U.s:829 .text.HAL_TIM_MspPostInit:00000000 $t
|
||
/tmp/cc61sY4U.s:835 .text.HAL_TIM_MspPostInit:00000000 HAL_TIM_MspPostInit
|
||
/tmp/cc61sY4U.s:1038 .text.HAL_TIM_MspPostInit:00000134 $d
|
||
/tmp/cc61sY4U.s:1047 .text.HAL_TIM_PWM_MspDeInit:00000000 $t
|
||
/tmp/cc61sY4U.s:1053 .text.HAL_TIM_PWM_MspDeInit:00000000 HAL_TIM_PWM_MspDeInit
|
||
/tmp/cc61sY4U.s:1143 .text.HAL_TIM_PWM_MspDeInit:00000074 $d
|
||
|
||
UNDEFINED SYMBOLS
|
||
HAL_GPIO_Init
|
||
HAL_NVIC_SetPriority
|
||
HAL_NVIC_EnableIRQ
|
||
HAL_GPIO_DeInit
|
||
HAL_NVIC_DisableIRQ
|