584 lines
32 KiB
Plaintext
584 lines
32 KiB
Plaintext
ARM GAS /tmp/cc0EV5A6.s page 1
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1 .cpu cortex-m4
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2 .arch armv7e-m
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3 .fpu fpv4-sp-d16
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4 .eabi_attribute 27, 1
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5 .eabi_attribute 28, 1
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6 .eabi_attribute 20, 1
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7 .eabi_attribute 21, 1
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8 .eabi_attribute 23, 3
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9 .eabi_attribute 24, 1
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10 .eabi_attribute 25, 1
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11 .eabi_attribute 26, 1
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12 .eabi_attribute 30, 6
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13 .eabi_attribute 34, 1
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14 .eabi_attribute 18, 4
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15 .file "system_stm32f3xx.c"
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16 .text
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17 .Ltext0:
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18 .cfi_sections .debug_frame
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19 .file 1 "Core/Src/system_stm32f3xx.c"
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20 .global SystemCoreClock
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21 .section .data.SystemCoreClock,"aw"
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22 .align 2
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25 SystemCoreClock:
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26 0000 00127A00 .word 8000000
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27 .global AHBPrescTable
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28 .section .rodata.AHBPrescTable,"a"
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29 .align 2
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32 AHBPrescTable:
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33 0000 00000000 .ascii "\000\000\000\000\000\000\000\000\001\002\003\004\006"
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33 00000000
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33 01020304
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33 06
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34 000d 070809 .ascii "\007\010\011"
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35 .global APBPrescTable
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36 .section .rodata.APBPrescTable,"a"
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37 .align 2
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40 APBPrescTable:
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41 0000 00000000 .ascii "\000\000\000\000\001\002\003\004"
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41 01020304
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42 .section .text.SystemInit,"ax",%progbits
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43 .align 1
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44 .global SystemInit
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45 .syntax unified
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46 .thumb
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47 .thumb_func
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49 SystemInit:
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50 .LFB130:
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1:Core/Src/system_stm32f3xx.c **** /**
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2:Core/Src/system_stm32f3xx.c **** ******************************************************************************
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3:Core/Src/system_stm32f3xx.c **** * @file system_stm32f3xx.c
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4:Core/Src/system_stm32f3xx.c **** * @author MCD Application Team
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5:Core/Src/system_stm32f3xx.c **** * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
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6:Core/Src/system_stm32f3xx.c **** *
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7:Core/Src/system_stm32f3xx.c **** * 1. This file provides two functions and one global variable to be called from
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8:Core/Src/system_stm32f3xx.c **** * user application:
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9:Core/Src/system_stm32f3xx.c **** * - SystemInit(): This function is called at startup just after reset and
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10:Core/Src/system_stm32f3xx.c **** * before branch to main program. This call is made inside
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ARM GAS /tmp/cc0EV5A6.s page 2
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11:Core/Src/system_stm32f3xx.c **** * the "startup_stm32f3xx.s" file.
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12:Core/Src/system_stm32f3xx.c **** *
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13:Core/Src/system_stm32f3xx.c **** * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
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14:Core/Src/system_stm32f3xx.c **** * by the user application to setup the SysTick
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15:Core/Src/system_stm32f3xx.c **** * timer or configure other parameters.
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16:Core/Src/system_stm32f3xx.c **** *
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17:Core/Src/system_stm32f3xx.c **** * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
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18:Core/Src/system_stm32f3xx.c **** * be called whenever the core clock is changed
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19:Core/Src/system_stm32f3xx.c **** * during program execution.
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20:Core/Src/system_stm32f3xx.c **** *
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21:Core/Src/system_stm32f3xx.c **** * 2. After each device reset the HSI (8 MHz) is used as system clock source.
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22:Core/Src/system_stm32f3xx.c **** * Then SystemInit() function is called, in "startup_stm32f3xx.s" file, to
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23:Core/Src/system_stm32f3xx.c **** * configure the system clock before to branch to main program.
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24:Core/Src/system_stm32f3xx.c **** *
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25:Core/Src/system_stm32f3xx.c **** * 3. This file configures the system clock as follows:
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26:Core/Src/system_stm32f3xx.c **** *=============================================================================
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27:Core/Src/system_stm32f3xx.c **** * Supported STM32F3xx device
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28:Core/Src/system_stm32f3xx.c **** *-----------------------------------------------------------------------------
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29:Core/Src/system_stm32f3xx.c **** * System Clock source | HSI
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30:Core/Src/system_stm32f3xx.c **** *-----------------------------------------------------------------------------
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31:Core/Src/system_stm32f3xx.c **** * SYSCLK(Hz) | 8000000
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32:Core/Src/system_stm32f3xx.c **** *-----------------------------------------------------------------------------
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33:Core/Src/system_stm32f3xx.c **** * HCLK(Hz) | 8000000
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34:Core/Src/system_stm32f3xx.c **** *-----------------------------------------------------------------------------
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35:Core/Src/system_stm32f3xx.c **** * AHB Prescaler | 1
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36:Core/Src/system_stm32f3xx.c **** *-----------------------------------------------------------------------------
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37:Core/Src/system_stm32f3xx.c **** * APB2 Prescaler | 1
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38:Core/Src/system_stm32f3xx.c **** *-----------------------------------------------------------------------------
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39:Core/Src/system_stm32f3xx.c **** * APB1 Prescaler | 1
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40:Core/Src/system_stm32f3xx.c **** *-----------------------------------------------------------------------------
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41:Core/Src/system_stm32f3xx.c **** * USB Clock | DISABLE
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42:Core/Src/system_stm32f3xx.c **** *-----------------------------------------------------------------------------
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43:Core/Src/system_stm32f3xx.c **** *=============================================================================
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44:Core/Src/system_stm32f3xx.c **** ******************************************************************************
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45:Core/Src/system_stm32f3xx.c **** * @attention
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46:Core/Src/system_stm32f3xx.c **** *
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47:Core/Src/system_stm32f3xx.c **** * Copyright (c) 2016 STMicroelectronics.
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48:Core/Src/system_stm32f3xx.c **** * All rights reserved.
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49:Core/Src/system_stm32f3xx.c **** *
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50:Core/Src/system_stm32f3xx.c **** * This software is licensed under terms that can be found in the LICENSE file
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51:Core/Src/system_stm32f3xx.c **** * in the root directory of this software component.
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52:Core/Src/system_stm32f3xx.c **** * If no LICENSE file comes with this software, it is provided AS-IS.
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53:Core/Src/system_stm32f3xx.c **** *
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54:Core/Src/system_stm32f3xx.c **** ******************************************************************************
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55:Core/Src/system_stm32f3xx.c **** */
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56:Core/Src/system_stm32f3xx.c ****
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57:Core/Src/system_stm32f3xx.c **** /** @addtogroup CMSIS
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58:Core/Src/system_stm32f3xx.c **** * @{
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59:Core/Src/system_stm32f3xx.c **** */
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60:Core/Src/system_stm32f3xx.c ****
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61:Core/Src/system_stm32f3xx.c **** /** @addtogroup stm32f3xx_system
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62:Core/Src/system_stm32f3xx.c **** * @{
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63:Core/Src/system_stm32f3xx.c **** */
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64:Core/Src/system_stm32f3xx.c ****
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65:Core/Src/system_stm32f3xx.c **** /** @addtogroup STM32F3xx_System_Private_Includes
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66:Core/Src/system_stm32f3xx.c **** * @{
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67:Core/Src/system_stm32f3xx.c **** */
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ARM GAS /tmp/cc0EV5A6.s page 3
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68:Core/Src/system_stm32f3xx.c ****
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69:Core/Src/system_stm32f3xx.c **** #include "stm32f3xx.h"
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70:Core/Src/system_stm32f3xx.c ****
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71:Core/Src/system_stm32f3xx.c **** /**
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72:Core/Src/system_stm32f3xx.c **** * @}
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73:Core/Src/system_stm32f3xx.c **** */
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74:Core/Src/system_stm32f3xx.c ****
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75:Core/Src/system_stm32f3xx.c **** /** @addtogroup STM32F3xx_System_Private_TypesDefinitions
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76:Core/Src/system_stm32f3xx.c **** * @{
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77:Core/Src/system_stm32f3xx.c **** */
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78:Core/Src/system_stm32f3xx.c ****
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79:Core/Src/system_stm32f3xx.c **** /**
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80:Core/Src/system_stm32f3xx.c **** * @}
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81:Core/Src/system_stm32f3xx.c **** */
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82:Core/Src/system_stm32f3xx.c ****
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83:Core/Src/system_stm32f3xx.c **** /** @addtogroup STM32F3xx_System_Private_Defines
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84:Core/Src/system_stm32f3xx.c **** * @{
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85:Core/Src/system_stm32f3xx.c **** */
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86:Core/Src/system_stm32f3xx.c **** #if !defined (HSE_VALUE)
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87:Core/Src/system_stm32f3xx.c **** #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
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88:Core/Src/system_stm32f3xx.c **** This value can be provided and adapted by the user
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89:Core/Src/system_stm32f3xx.c **** #endif /* HSE_VALUE */
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90:Core/Src/system_stm32f3xx.c ****
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91:Core/Src/system_stm32f3xx.c **** #if !defined (HSI_VALUE)
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92:Core/Src/system_stm32f3xx.c **** #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
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93:Core/Src/system_stm32f3xx.c **** This value can be provided and adapted by the user
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94:Core/Src/system_stm32f3xx.c **** #endif /* HSI_VALUE */
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95:Core/Src/system_stm32f3xx.c ****
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96:Core/Src/system_stm32f3xx.c **** /* Note: Following vector table addresses must be defined in line with linker
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97:Core/Src/system_stm32f3xx.c **** configuration. */
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98:Core/Src/system_stm32f3xx.c **** /*!< Uncomment the following line if you need to relocate the vector table
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99:Core/Src/system_stm32f3xx.c **** anywhere in Flash or Sram, else the vector table is kept at the automatic
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100:Core/Src/system_stm32f3xx.c **** remap of boot address selected */
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101:Core/Src/system_stm32f3xx.c **** /* #define USER_VECT_TAB_ADDRESS */
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102:Core/Src/system_stm32f3xx.c ****
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103:Core/Src/system_stm32f3xx.c **** #if defined(USER_VECT_TAB_ADDRESS)
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104:Core/Src/system_stm32f3xx.c **** /*!< Uncomment the following line if you need to relocate your vector Table
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105:Core/Src/system_stm32f3xx.c **** in Sram else user remap will be done in Flash. */
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106:Core/Src/system_stm32f3xx.c **** /* #define VECT_TAB_SRAM */
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107:Core/Src/system_stm32f3xx.c **** #if defined(VECT_TAB_SRAM)
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108:Core/Src/system_stm32f3xx.c **** #define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field.
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109:Core/Src/system_stm32f3xx.c **** This value must be a multiple of 0x200. */
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110:Core/Src/system_stm32f3xx.c **** #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
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111:Core/Src/system_stm32f3xx.c **** This value must be a multiple of 0x200. */
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112:Core/Src/system_stm32f3xx.c **** #else
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113:Core/Src/system_stm32f3xx.c **** #define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
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114:Core/Src/system_stm32f3xx.c **** This value must be a multiple of 0x200. */
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115:Core/Src/system_stm32f3xx.c **** #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
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116:Core/Src/system_stm32f3xx.c **** This value must be a multiple of 0x200. */
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117:Core/Src/system_stm32f3xx.c **** #endif /* VECT_TAB_SRAM */
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118:Core/Src/system_stm32f3xx.c **** #endif /* USER_VECT_TAB_ADDRESS */
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119:Core/Src/system_stm32f3xx.c ****
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120:Core/Src/system_stm32f3xx.c **** /******************************************************************************/
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121:Core/Src/system_stm32f3xx.c **** /**
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122:Core/Src/system_stm32f3xx.c **** * @}
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123:Core/Src/system_stm32f3xx.c **** */
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124:Core/Src/system_stm32f3xx.c ****
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ARM GAS /tmp/cc0EV5A6.s page 4
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125:Core/Src/system_stm32f3xx.c **** /** @addtogroup STM32F3xx_System_Private_Macros
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126:Core/Src/system_stm32f3xx.c **** * @{
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127:Core/Src/system_stm32f3xx.c **** */
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128:Core/Src/system_stm32f3xx.c ****
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129:Core/Src/system_stm32f3xx.c **** /**
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130:Core/Src/system_stm32f3xx.c **** * @}
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131:Core/Src/system_stm32f3xx.c **** */
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132:Core/Src/system_stm32f3xx.c ****
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133:Core/Src/system_stm32f3xx.c **** /** @addtogroup STM32F3xx_System_Private_Variables
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134:Core/Src/system_stm32f3xx.c **** * @{
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135:Core/Src/system_stm32f3xx.c **** */
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136:Core/Src/system_stm32f3xx.c **** /* This variable is updated in three ways:
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137:Core/Src/system_stm32f3xx.c **** 1) by calling CMSIS function SystemCoreClockUpdate()
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138:Core/Src/system_stm32f3xx.c **** 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
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139:Core/Src/system_stm32f3xx.c **** 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
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140:Core/Src/system_stm32f3xx.c **** Note: If you use this function to configure the system clock there is no need to
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141:Core/Src/system_stm32f3xx.c **** call the 2 first functions listed above, since SystemCoreClock variable is
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142:Core/Src/system_stm32f3xx.c **** updated automatically.
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143:Core/Src/system_stm32f3xx.c **** */
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144:Core/Src/system_stm32f3xx.c **** uint32_t SystemCoreClock = 8000000;
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145:Core/Src/system_stm32f3xx.c ****
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146:Core/Src/system_stm32f3xx.c **** const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
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147:Core/Src/system_stm32f3xx.c **** const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
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148:Core/Src/system_stm32f3xx.c ****
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149:Core/Src/system_stm32f3xx.c **** /**
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150:Core/Src/system_stm32f3xx.c **** * @}
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151:Core/Src/system_stm32f3xx.c **** */
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152:Core/Src/system_stm32f3xx.c ****
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153:Core/Src/system_stm32f3xx.c **** /** @addtogroup STM32F3xx_System_Private_FunctionPrototypes
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154:Core/Src/system_stm32f3xx.c **** * @{
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155:Core/Src/system_stm32f3xx.c **** */
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156:Core/Src/system_stm32f3xx.c ****
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157:Core/Src/system_stm32f3xx.c **** /**
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158:Core/Src/system_stm32f3xx.c **** * @}
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159:Core/Src/system_stm32f3xx.c **** */
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160:Core/Src/system_stm32f3xx.c ****
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161:Core/Src/system_stm32f3xx.c **** /** @addtogroup STM32F3xx_System_Private_Functions
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162:Core/Src/system_stm32f3xx.c **** * @{
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163:Core/Src/system_stm32f3xx.c **** */
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164:Core/Src/system_stm32f3xx.c ****
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165:Core/Src/system_stm32f3xx.c **** /**
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166:Core/Src/system_stm32f3xx.c **** * @brief Setup the microcontroller system
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167:Core/Src/system_stm32f3xx.c **** * @param None
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168:Core/Src/system_stm32f3xx.c **** * @retval None
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169:Core/Src/system_stm32f3xx.c **** */
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170:Core/Src/system_stm32f3xx.c **** void SystemInit(void)
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171:Core/Src/system_stm32f3xx.c **** {
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51 .loc 1 171 1
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52 .cfi_startproc
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53 @ args = 0, pretend = 0, frame = 0
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54 @ frame_needed = 1, uses_anonymous_args = 0
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55 @ link register save eliminated.
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56 0000 80B4 push {r7}
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57 .cfi_def_cfa_offset 4
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58 .cfi_offset 7, -4
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59 0002 00AF add r7, sp, #0
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60 .cfi_def_cfa_register 7
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ARM GAS /tmp/cc0EV5A6.s page 5
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172:Core/Src/system_stm32f3xx.c **** /* FPU settings --------------------------------------------------------------*/
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173:Core/Src/system_stm32f3xx.c **** #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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174:Core/Src/system_stm32f3xx.c **** SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
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61 .loc 1 174 6
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62 0004 064B ldr r3, .L2
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63 0006 D3F88830 ldr r3, [r3, #136]
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64 000a 054A ldr r2, .L2
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65 .loc 1 174 14
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66 000c 43F47003 orr r3, r3, #15728640
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67 0010 C2F88830 str r3, [r2, #136]
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175:Core/Src/system_stm32f3xx.c **** #endif
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176:Core/Src/system_stm32f3xx.c ****
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177:Core/Src/system_stm32f3xx.c **** /* Configure the Vector Table location -------------------------------------*/
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178:Core/Src/system_stm32f3xx.c **** #if defined(USER_VECT_TAB_ADDRESS)
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179:Core/Src/system_stm32f3xx.c **** SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM
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180:Core/Src/system_stm32f3xx.c **** #endif /* USER_VECT_TAB_ADDRESS */
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181:Core/Src/system_stm32f3xx.c **** }
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68 .loc 1 181 1
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69 0014 00BF nop
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70 0016 BD46 mov sp, r7
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71 .cfi_def_cfa_register 13
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72 @ sp needed
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73 0018 5DF8047B ldr r7, [sp], #4
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74 .cfi_restore 7
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75 .cfi_def_cfa_offset 0
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76 001c 7047 bx lr
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77 .L3:
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78 001e 00BF .align 2
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79 .L2:
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80 0020 00ED00E0 .word -536810240
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81 .cfi_endproc
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82 .LFE130:
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84 .section .text.SystemCoreClockUpdate,"ax",%progbits
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85 .align 1
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86 .global SystemCoreClockUpdate
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87 .syntax unified
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88 .thumb
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89 .thumb_func
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91 SystemCoreClockUpdate:
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92 .LFB131:
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182:Core/Src/system_stm32f3xx.c ****
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183:Core/Src/system_stm32f3xx.c **** /**
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184:Core/Src/system_stm32f3xx.c **** * @brief Update SystemCoreClock variable according to Clock Register Values.
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185:Core/Src/system_stm32f3xx.c **** * The SystemCoreClock variable contains the core clock (HCLK), it can
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186:Core/Src/system_stm32f3xx.c **** * be used by the user application to setup the SysTick timer or configure
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187:Core/Src/system_stm32f3xx.c **** * other parameters.
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188:Core/Src/system_stm32f3xx.c **** *
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189:Core/Src/system_stm32f3xx.c **** * @note Each time the core clock (HCLK) changes, this function must be called
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190:Core/Src/system_stm32f3xx.c **** * to update SystemCoreClock variable value. Otherwise, any configuration
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191:Core/Src/system_stm32f3xx.c **** * based on this variable will be incorrect.
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192:Core/Src/system_stm32f3xx.c **** *
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193:Core/Src/system_stm32f3xx.c **** * @note - The system frequency computed by this function is not the real
|
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194:Core/Src/system_stm32f3xx.c **** * frequency in the chip. It is calculated based on the predefined
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195:Core/Src/system_stm32f3xx.c **** * constant and the selected clock source:
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196:Core/Src/system_stm32f3xx.c **** *
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197:Core/Src/system_stm32f3xx.c **** * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
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198:Core/Src/system_stm32f3xx.c **** *
|
||
ARM GAS /tmp/cc0EV5A6.s page 6
|
||
|
||
|
||
199:Core/Src/system_stm32f3xx.c **** * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
|
||
200:Core/Src/system_stm32f3xx.c **** *
|
||
201:Core/Src/system_stm32f3xx.c **** * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
|
||
202:Core/Src/system_stm32f3xx.c **** * or HSI_VALUE(*) multiplied/divided by the PLL factors.
|
||
203:Core/Src/system_stm32f3xx.c **** *
|
||
204:Core/Src/system_stm32f3xx.c **** * (*) HSI_VALUE is a constant defined in stm32f3xx_hal.h file (default value
|
||
205:Core/Src/system_stm32f3xx.c **** * 8 MHz) but the real value may vary depending on the variations
|
||
206:Core/Src/system_stm32f3xx.c **** * in voltage and temperature.
|
||
207:Core/Src/system_stm32f3xx.c **** *
|
||
208:Core/Src/system_stm32f3xx.c **** * (**) HSE_VALUE is a constant defined in stm32f3xx_hal.h file (default value
|
||
209:Core/Src/system_stm32f3xx.c **** * 8 MHz), user has to ensure that HSE_VALUE is same as the real
|
||
210:Core/Src/system_stm32f3xx.c **** * frequency of the crystal used. Otherwise, this function may
|
||
211:Core/Src/system_stm32f3xx.c **** * have wrong result.
|
||
212:Core/Src/system_stm32f3xx.c **** *
|
||
213:Core/Src/system_stm32f3xx.c **** * - The result of this function could be not correct when using fractional
|
||
214:Core/Src/system_stm32f3xx.c **** * value for HSE crystal.
|
||
215:Core/Src/system_stm32f3xx.c **** *
|
||
216:Core/Src/system_stm32f3xx.c **** * @param None
|
||
217:Core/Src/system_stm32f3xx.c **** * @retval None
|
||
218:Core/Src/system_stm32f3xx.c **** */
|
||
219:Core/Src/system_stm32f3xx.c **** void SystemCoreClockUpdate (void)
|
||
220:Core/Src/system_stm32f3xx.c **** {
|
||
93 .loc 1 220 1
|
||
94 .cfi_startproc
|
||
95 @ args = 0, pretend = 0, frame = 16
|
||
96 @ frame_needed = 1, uses_anonymous_args = 0
|
||
97 @ link register save eliminated.
|
||
98 0000 80B4 push {r7}
|
||
99 .cfi_def_cfa_offset 4
|
||
100 .cfi_offset 7, -4
|
||
101 0002 85B0 sub sp, sp, #20
|
||
102 .cfi_def_cfa_offset 24
|
||
103 0004 00AF add r7, sp, #0
|
||
104 .cfi_def_cfa_register 7
|
||
221:Core/Src/system_stm32f3xx.c **** uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
|
||
105 .loc 1 221 12
|
||
106 0006 0023 movs r3, #0
|
||
107 0008 FB60 str r3, [r7, #12]
|
||
108 .loc 1 221 21
|
||
109 000a 0023 movs r3, #0
|
||
110 000c BB60 str r3, [r7, #8]
|
||
111 .loc 1 221 34
|
||
112 000e 0023 movs r3, #0
|
||
113 0010 7B60 str r3, [r7, #4]
|
||
114 .loc 1 221 49
|
||
115 0012 0023 movs r3, #0
|
||
116 0014 3B60 str r3, [r7]
|
||
222:Core/Src/system_stm32f3xx.c ****
|
||
223:Core/Src/system_stm32f3xx.c **** /* Get SYSCLK source -------------------------------------------------------*/
|
||
224:Core/Src/system_stm32f3xx.c **** tmp = RCC->CFGR & RCC_CFGR_SWS;
|
||
117 .loc 1 224 12
|
||
118 0016 2D4B ldr r3, .L12
|
||
119 0018 5B68 ldr r3, [r3, #4]
|
||
120 .loc 1 224 7
|
||
121 001a 03F00C03 and r3, r3, #12
|
||
122 001e FB60 str r3, [r7, #12]
|
||
225:Core/Src/system_stm32f3xx.c ****
|
||
ARM GAS /tmp/cc0EV5A6.s page 7
|
||
|
||
|
||
226:Core/Src/system_stm32f3xx.c **** switch (tmp)
|
||
123 .loc 1 226 3
|
||
124 0020 FB68 ldr r3, [r7, #12]
|
||
125 0022 082B cmp r3, #8
|
||
126 0024 11D0 beq .L5
|
||
127 0026 FB68 ldr r3, [r7, #12]
|
||
128 0028 082B cmp r3, #8
|
||
129 002a 36D8 bhi .L6
|
||
130 002c FB68 ldr r3, [r7, #12]
|
||
131 002e 002B cmp r3, #0
|
||
132 0030 03D0 beq .L7
|
||
133 0032 FB68 ldr r3, [r7, #12]
|
||
134 0034 042B cmp r3, #4
|
||
135 0036 04D0 beq .L8
|
||
136 0038 2FE0 b .L6
|
||
137 .L7:
|
||
227:Core/Src/system_stm32f3xx.c **** {
|
||
228:Core/Src/system_stm32f3xx.c **** case RCC_CFGR_SWS_HSI: /* HSI used as system clock */
|
||
229:Core/Src/system_stm32f3xx.c **** SystemCoreClock = HSI_VALUE;
|
||
138 .loc 1 229 23
|
||
139 003a 254B ldr r3, .L12+4
|
||
140 003c 254A ldr r2, .L12+8
|
||
141 003e 1A60 str r2, [r3]
|
||
230:Core/Src/system_stm32f3xx.c **** break;
|
||
142 .loc 1 230 7
|
||
143 0040 2FE0 b .L9
|
||
144 .L8:
|
||
231:Core/Src/system_stm32f3xx.c **** case RCC_CFGR_SWS_HSE: /* HSE used as system clock */
|
||
232:Core/Src/system_stm32f3xx.c **** SystemCoreClock = HSE_VALUE;
|
||
145 .loc 1 232 23
|
||
146 0042 234B ldr r3, .L12+4
|
||
147 0044 244A ldr r2, .L12+12
|
||
148 0046 1A60 str r2, [r3]
|
||
233:Core/Src/system_stm32f3xx.c **** break;
|
||
149 .loc 1 233 7
|
||
150 0048 2BE0 b .L9
|
||
151 .L5:
|
||
234:Core/Src/system_stm32f3xx.c **** case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
|
||
235:Core/Src/system_stm32f3xx.c **** /* Get PLL clock source and multiplication factor ----------------------*/
|
||
236:Core/Src/system_stm32f3xx.c **** pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
|
||
152 .loc 1 236 20
|
||
153 004a 204B ldr r3, .L12
|
||
154 004c 5B68 ldr r3, [r3, #4]
|
||
155 .loc 1 236 15
|
||
156 004e 03F47013 and r3, r3, #3932160
|
||
157 0052 BB60 str r3, [r7, #8]
|
||
237:Core/Src/system_stm32f3xx.c **** pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
|
||
158 .loc 1 237 22
|
||
159 0054 1D4B ldr r3, .L12
|
||
160 0056 5B68 ldr r3, [r3, #4]
|
||
161 .loc 1 237 17
|
||
162 0058 03F48033 and r3, r3, #65536
|
||
163 005c 7B60 str r3, [r7, #4]
|
||
238:Core/Src/system_stm32f3xx.c **** pllmull = ( pllmull >> 18) + 2;
|
||
164 .loc 1 238 27
|
||
165 005e BB68 ldr r3, [r7, #8]
|
||
166 0060 9B0C lsrs r3, r3, #18
|
||
ARM GAS /tmp/cc0EV5A6.s page 8
|
||
|
||
|
||
167 .loc 1 238 15
|
||
168 0062 0233 adds r3, r3, #2
|
||
169 0064 BB60 str r3, [r7, #8]
|
||
239:Core/Src/system_stm32f3xx.c ****
|
||
240:Core/Src/system_stm32f3xx.c **** #if defined (STM32F302xE) || defined (STM32F303xE) || defined (STM32F398xx)
|
||
241:Core/Src/system_stm32f3xx.c **** predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
|
||
242:Core/Src/system_stm32f3xx.c **** if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
|
||
243:Core/Src/system_stm32f3xx.c **** {
|
||
244:Core/Src/system_stm32f3xx.c **** /* HSE oscillator clock selected as PREDIV1 clock entry */
|
||
245:Core/Src/system_stm32f3xx.c **** SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull;
|
||
246:Core/Src/system_stm32f3xx.c **** }
|
||
247:Core/Src/system_stm32f3xx.c **** else
|
||
248:Core/Src/system_stm32f3xx.c **** {
|
||
249:Core/Src/system_stm32f3xx.c **** /* HSI oscillator clock selected as PREDIV1 clock entry */
|
||
250:Core/Src/system_stm32f3xx.c **** SystemCoreClock = (HSI_VALUE / predivfactor) * pllmull;
|
||
251:Core/Src/system_stm32f3xx.c **** }
|
||
252:Core/Src/system_stm32f3xx.c **** #else
|
||
253:Core/Src/system_stm32f3xx.c **** if (pllsource == RCC_CFGR_PLLSRC_HSI_DIV2)
|
||
170 .loc 1 253 10
|
||
171 0066 7B68 ldr r3, [r7, #4]
|
||
172 0068 002B cmp r3, #0
|
||
173 006a 06D1 bne .L10
|
||
254:Core/Src/system_stm32f3xx.c **** {
|
||
255:Core/Src/system_stm32f3xx.c **** /* HSI oscillator clock divided by 2 selected as PLL clock entry */
|
||
256:Core/Src/system_stm32f3xx.c **** SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
|
||
174 .loc 1 256 44
|
||
175 006c BB68 ldr r3, [r7, #8]
|
||
176 006e 1B4A ldr r2, .L12+16
|
||
177 0070 02FB03F3 mul r3, r2, r3
|
||
178 .loc 1 256 25
|
||
179 0074 164A ldr r2, .L12+4
|
||
180 0076 1360 str r3, [r2]
|
||
257:Core/Src/system_stm32f3xx.c **** }
|
||
258:Core/Src/system_stm32f3xx.c **** else
|
||
259:Core/Src/system_stm32f3xx.c **** {
|
||
260:Core/Src/system_stm32f3xx.c **** predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
|
||
261:Core/Src/system_stm32f3xx.c **** /* HSE oscillator clock selected as PREDIV1 clock entry */
|
||
262:Core/Src/system_stm32f3xx.c **** SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull;
|
||
263:Core/Src/system_stm32f3xx.c **** }
|
||
264:Core/Src/system_stm32f3xx.c **** #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
|
||
265:Core/Src/system_stm32f3xx.c **** break;
|
||
181 .loc 1 265 7
|
||
182 0078 13E0 b .L9
|
||
183 .L10:
|
||
260:Core/Src/system_stm32f3xx.c **** /* HSE oscillator clock selected as PREDIV1 clock entry */
|
||
184 .loc 1 260 28
|
||
185 007a 144B ldr r3, .L12
|
||
186 007c DB6A ldr r3, [r3, #44]
|
||
260:Core/Src/system_stm32f3xx.c **** /* HSE oscillator clock selected as PREDIV1 clock entry */
|
||
187 .loc 1 260 36
|
||
188 007e 03F00F03 and r3, r3, #15
|
||
260:Core/Src/system_stm32f3xx.c **** /* HSE oscillator clock selected as PREDIV1 clock entry */
|
||
189 .loc 1 260 22
|
||
190 0082 0133 adds r3, r3, #1
|
||
191 0084 3B60 str r3, [r7]
|
||
262:Core/Src/system_stm32f3xx.c **** }
|
||
192 .loc 1 262 38
|
||
ARM GAS /tmp/cc0EV5A6.s page 9
|
||
|
||
|
||
193 0086 144A ldr r2, .L12+12
|
||
194 0088 3B68 ldr r3, [r7]
|
||
195 008a B2FBF3F3 udiv r3, r2, r3
|
||
262:Core/Src/system_stm32f3xx.c **** }
|
||
196 .loc 1 262 54
|
||
197 008e BA68 ldr r2, [r7, #8]
|
||
198 0090 02FB03F3 mul r3, r2, r3
|
||
262:Core/Src/system_stm32f3xx.c **** }
|
||
199 .loc 1 262 25
|
||
200 0094 0E4A ldr r2, .L12+4
|
||
201 0096 1360 str r3, [r2]
|
||
202 .loc 1 265 7
|
||
203 0098 03E0 b .L9
|
||
204 .L6:
|
||
266:Core/Src/system_stm32f3xx.c **** default: /* HSI used as system clock */
|
||
267:Core/Src/system_stm32f3xx.c **** SystemCoreClock = HSI_VALUE;
|
||
205 .loc 1 267 23
|
||
206 009a 0D4B ldr r3, .L12+4
|
||
207 009c 0D4A ldr r2, .L12+8
|
||
208 009e 1A60 str r2, [r3]
|
||
268:Core/Src/system_stm32f3xx.c **** break;
|
||
209 .loc 1 268 7
|
||
210 00a0 00BF nop
|
||
211 .L9:
|
||
269:Core/Src/system_stm32f3xx.c **** }
|
||
270:Core/Src/system_stm32f3xx.c **** /* Compute HCLK clock frequency ----------------*/
|
||
271:Core/Src/system_stm32f3xx.c **** /* Get HCLK prescaler */
|
||
272:Core/Src/system_stm32f3xx.c **** tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
|
||
212 .loc 1 272 28
|
||
213 00a2 0A4B ldr r3, .L12
|
||
214 00a4 5B68 ldr r3, [r3, #4]
|
||
215 .loc 1 272 52
|
||
216 00a6 1B09 lsrs r3, r3, #4
|
||
217 00a8 03F00F03 and r3, r3, #15
|
||
218 .loc 1 272 22
|
||
219 00ac 0C4A ldr r2, .L12+20
|
||
220 00ae D35C ldrb r3, [r2, r3] @ zero_extendqisi2
|
||
221 .loc 1 272 7
|
||
222 00b0 FB60 str r3, [r7, #12]
|
||
273:Core/Src/system_stm32f3xx.c **** /* HCLK clock frequency */
|
||
274:Core/Src/system_stm32f3xx.c **** SystemCoreClock >>= tmp;
|
||
223 .loc 1 274 19
|
||
224 00b2 074B ldr r3, .L12+4
|
||
225 00b4 1A68 ldr r2, [r3]
|
||
226 00b6 FB68 ldr r3, [r7, #12]
|
||
227 00b8 22FA03F3 lsr r3, r2, r3
|
||
228 00bc 044A ldr r2, .L12+4
|
||
229 00be 1360 str r3, [r2]
|
||
275:Core/Src/system_stm32f3xx.c **** }
|
||
230 .loc 1 275 1
|
||
231 00c0 00BF nop
|
||
232 00c2 1437 adds r7, r7, #20
|
||
233 .cfi_def_cfa_offset 4
|
||
234 00c4 BD46 mov sp, r7
|
||
235 .cfi_def_cfa_register 13
|
||
236 @ sp needed
|
||
237 00c6 5DF8047B ldr r7, [sp], #4
|
||
ARM GAS /tmp/cc0EV5A6.s page 10
|
||
|
||
|
||
238 .cfi_restore 7
|
||
239 .cfi_def_cfa_offset 0
|
||
240 00ca 7047 bx lr
|
||
241 .L13:
|
||
242 .align 2
|
||
243 .L12:
|
||
244 00cc 00100240 .word 1073876992
|
||
245 00d0 00000000 .word SystemCoreClock
|
||
246 00d4 00127A00 .word 8000000
|
||
247 00d8 0024F400 .word 16000000
|
||
248 00dc 00093D00 .word 4000000
|
||
249 00e0 00000000 .word AHBPrescTable
|
||
250 .cfi_endproc
|
||
251 .LFE131:
|
||
253 .text
|
||
254 .Letext0:
|
||
255 .file 2 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl
|
||
256 .file 3 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl
|
||
257 .file 4 "Drivers/CMSIS/Include/core_cm4.h"
|
||
258 .file 5 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h"
|
||
259 .file 6 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h"
|
||
ARM GAS /tmp/cc0EV5A6.s page 11
|
||
|
||
|
||
DEFINED SYMBOLS
|
||
*ABS*:00000000 system_stm32f3xx.c
|
||
/tmp/cc0EV5A6.s:25 .data.SystemCoreClock:00000000 SystemCoreClock
|
||
/tmp/cc0EV5A6.s:22 .data.SystemCoreClock:00000000 $d
|
||
/tmp/cc0EV5A6.s:32 .rodata.AHBPrescTable:00000000 AHBPrescTable
|
||
/tmp/cc0EV5A6.s:29 .rodata.AHBPrescTable:00000000 $d
|
||
/tmp/cc0EV5A6.s:40 .rodata.APBPrescTable:00000000 APBPrescTable
|
||
/tmp/cc0EV5A6.s:37 .rodata.APBPrescTable:00000000 $d
|
||
/tmp/cc0EV5A6.s:43 .text.SystemInit:00000000 $t
|
||
/tmp/cc0EV5A6.s:49 .text.SystemInit:00000000 SystemInit
|
||
/tmp/cc0EV5A6.s:80 .text.SystemInit:00000020 $d
|
||
/tmp/cc0EV5A6.s:85 .text.SystemCoreClockUpdate:00000000 $t
|
||
/tmp/cc0EV5A6.s:91 .text.SystemCoreClockUpdate:00000000 SystemCoreClockUpdate
|
||
/tmp/cc0EV5A6.s:244 .text.SystemCoreClockUpdate:000000cc $d
|
||
|
||
NO UNDEFINED SYMBOLS
|