ARM GAS /tmp/ccSWt3lr.s page 1 1 .cpu cortex-m4 2 .arch armv7e-m 3 .fpu fpv4-sp-d16 4 .eabi_attribute 27, 1 5 .eabi_attribute 28, 1 6 .eabi_attribute 20, 1 7 .eabi_attribute 21, 1 8 .eabi_attribute 23, 3 9 .eabi_attribute 24, 1 10 .eabi_attribute 25, 1 11 .eabi_attribute 26, 1 12 .eabi_attribute 30, 6 13 .eabi_attribute 34, 1 14 .eabi_attribute 18, 4 15 .file "main.c" 16 .text 17 .Ltext0: 18 .cfi_sections .debug_frame 19 .file 1 "Core/Src/main.c" 20 .global hcan 21 .section .bss.hcan,"aw",%nobits 22 .align 2 25 hcan: 26 0000 00000000 .space 40 26 00000000 26 00000000 26 00000000 26 00000000 27 .global hi2c1 28 .section .bss.hi2c1,"aw",%nobits 29 .align 2 32 hi2c1: 33 0000 00000000 .space 84 33 00000000 33 00000000 33 00000000 33 00000000 34 .global hi2c2 35 .section .bss.hi2c2,"aw",%nobits 36 .align 2 39 hi2c2: 40 0000 00000000 .space 84 40 00000000 40 00000000 40 00000000 40 00000000 41 .global hspi1 42 .section .bss.hspi1,"aw",%nobits 43 .align 2 46 hspi1: 47 0000 00000000 .space 100 47 00000000 47 00000000 47 00000000 47 00000000 48 .global htim2 49 .section .bss.htim2,"aw",%nobits ARM GAS /tmp/ccSWt3lr.s page 2 50 .align 2 53 htim2: 54 0000 00000000 .space 76 54 00000000 54 00000000 54 00000000 54 00000000 55 .global htim3 56 .section .bss.htim3,"aw",%nobits 57 .align 2 60 htim3: 61 0000 00000000 .space 76 61 00000000 61 00000000 61 00000000 61 00000000 62 .global htim4 63 .section .bss.htim4,"aw",%nobits 64 .align 2 67 htim4: 68 0000 00000000 .space 76 68 00000000 68 00000000 68 00000000 68 00000000 69 .global htim15 70 .section .bss.htim15,"aw",%nobits 71 .align 2 74 htim15: 75 0000 00000000 .space 76 75 00000000 75 00000000 75 00000000 75 00000000 76 .section .text.main,"ax",%progbits 77 .align 1 78 .global main 79 .syntax unified 80 .thumb 81 .thumb_func 83 main: 84 .LFB130: 1:Core/Src/main.c **** /* USER CODE BEGIN Header */ 2:Core/Src/main.c **** /** 3:Core/Src/main.c **** ****************************************************************************** 4:Core/Src/main.c **** * @file : main.c 5:Core/Src/main.c **** * @brief : Main program body 6:Core/Src/main.c **** ****************************************************************************** 7:Core/Src/main.c **** * @attention 8:Core/Src/main.c **** * 9:Core/Src/main.c **** * Copyright (c) 2024 STMicroelectronics. 10:Core/Src/main.c **** * All rights reserved. 11:Core/Src/main.c **** * 12:Core/Src/main.c **** * This software is licensed under terms that can be found in the LICENSE file 13:Core/Src/main.c **** * in the root directory of this software component. 14:Core/Src/main.c **** * If no LICENSE file comes with this software, it is provided AS-IS. 15:Core/Src/main.c **** * ARM GAS /tmp/ccSWt3lr.s page 3 16:Core/Src/main.c **** ****************************************************************************** 17:Core/Src/main.c **** */ 18:Core/Src/main.c **** /* USER CODE END Header */ 19:Core/Src/main.c **** /* Includes ------------------------------------------------------------------*/ 20:Core/Src/main.c **** #include "main.h" 21:Core/Src/main.c **** 22:Core/Src/main.c **** /* Private includes ----------------------------------------------------------*/ 23:Core/Src/main.c **** /* USER CODE BEGIN Includes */ 24:Core/Src/main.c **** #include "ADBMS_Abstraction.h" 25:Core/Src/main.c **** #include "ADBMS_CMD_MAKROS.h" 26:Core/Src/main.c **** #include "PWM_control.h" 27:Core/Src/main.c **** #include "can.h" 28:Core/Src/main.c **** #include "AMS_HighLevel.h" 29:Core/Src/main.c **** #include "soc_estimation.h" 30:Core/Src/main.c **** #include "state_machine.h" 31:Core/Src/main.c **** #include 32:Core/Src/main.c **** #include 33:Core/Src/main.c **** #include "TMP1075.h" 34:Core/Src/main.c **** #include "errors.h" 35:Core/Src/main.c **** #include "stm32f302xc.h" 36:Core/Src/main.c **** #include "stm32f3xx_hal.h" 37:Core/Src/main.c **** #include "stm32f3xx_hal_tim.h" 38:Core/Src/main.c **** /* USER CODE END Includes */ 39:Core/Src/main.c **** 40:Core/Src/main.c **** /* Private typedef -----------------------------------------------------------*/ 41:Core/Src/main.c **** /* USER CODE BEGIN PTD */ 42:Core/Src/main.c **** 43:Core/Src/main.c **** /* USER CODE END PTD */ 44:Core/Src/main.c **** 45:Core/Src/main.c **** /* Private define ------------------------------------------------------------*/ 46:Core/Src/main.c **** /* USER CODE BEGIN PD */ 47:Core/Src/main.c **** 48:Core/Src/main.c **** /* USER CODE END PD */ 49:Core/Src/main.c **** 50:Core/Src/main.c **** /* Private macro -------------------------------------------------------------*/ 51:Core/Src/main.c **** /* USER CODE BEGIN PM */ 52:Core/Src/main.c **** 53:Core/Src/main.c **** // htim2 CH3,4 BAT_COOLING_PWM,ENABLE 54:Core/Src/main.c **** // htim3 CH3,4 ESC_L_PWM,R_PWM 55:Core/Src/main.c **** // htim4 CH1,2,3 LED R,G,B 56:Core/Src/main.c **** // htim15 CH1,2 ESC_COOLING_ENABLE,PWM 57:Core/Src/main.c **** 58:Core/Src/main.c **** /* USER CODE END PM */ 59:Core/Src/main.c **** 60:Core/Src/main.c **** /* Private variables ---------------------------------------------------------*/ 61:Core/Src/main.c **** CAN_HandleTypeDef hcan; 62:Core/Src/main.c **** 63:Core/Src/main.c **** I2C_HandleTypeDef hi2c1; 64:Core/Src/main.c **** I2C_HandleTypeDef hi2c2; 65:Core/Src/main.c **** 66:Core/Src/main.c **** SPI_HandleTypeDef hspi1; 67:Core/Src/main.c **** 68:Core/Src/main.c **** TIM_HandleTypeDef htim2; 69:Core/Src/main.c **** TIM_HandleTypeDef htim3; 70:Core/Src/main.c **** TIM_HandleTypeDef htim4; 71:Core/Src/main.c **** TIM_HandleTypeDef htim15; 72:Core/Src/main.c **** ARM GAS /tmp/ccSWt3lr.s page 4 73:Core/Src/main.c **** /* USER CODE BEGIN PV */ 74:Core/Src/main.c **** 75:Core/Src/main.c **** /* USER CODE END PV */ 76:Core/Src/main.c **** 77:Core/Src/main.c **** /* Private function prototypes -----------------------------------------------*/ 78:Core/Src/main.c **** void SystemClock_Config(void); 79:Core/Src/main.c **** static void MX_GPIO_Init(void); 80:Core/Src/main.c **** static void MX_CAN_Init(void); 81:Core/Src/main.c **** static void MX_I2C1_Init(void); 82:Core/Src/main.c **** static void MX_SPI1_Init(void); 83:Core/Src/main.c **** static void MX_TIM15_Init(void); 84:Core/Src/main.c **** static void MX_I2C2_Init(void); 85:Core/Src/main.c **** static void MX_TIM2_Init(void); 86:Core/Src/main.c **** static void MX_TIM3_Init(void); 87:Core/Src/main.c **** static void MX_TIM4_Init(void); 88:Core/Src/main.c **** /* USER CODE BEGIN PFP */ 89:Core/Src/main.c **** 90:Core/Src/main.c **** /* USER CODE END PFP */ 91:Core/Src/main.c **** 92:Core/Src/main.c **** /* Private user code ---------------------------------------------------------*/ 93:Core/Src/main.c **** /* USER CODE BEGIN 0 */ 94:Core/Src/main.c **** 95:Core/Src/main.c **** /* USER CODE END 0 */ 96:Core/Src/main.c **** 97:Core/Src/main.c **** /** 98:Core/Src/main.c **** * @brief The application entry point. 99:Core/Src/main.c **** * @retval int 100:Core/Src/main.c **** */ 101:Core/Src/main.c **** int main(void) 102:Core/Src/main.c **** { 85 .loc 1 102 1 86 .cfi_startproc 87 @ args = 0, pretend = 0, frame = 8 88 @ frame_needed = 1, uses_anonymous_args = 0 89 0000 80B5 push {r7, lr} 90 .cfi_def_cfa_offset 8 91 .cfi_offset 7, -8 92 .cfi_offset 14, -4 93 0002 82B0 sub sp, sp, #8 94 .cfi_def_cfa_offset 16 95 0004 00AF add r7, sp, #0 96 .cfi_def_cfa_register 7 103:Core/Src/main.c **** 104:Core/Src/main.c **** /* USER CODE BEGIN 1 */ 105:Core/Src/main.c **** 106:Core/Src/main.c **** /* USER CODE END 1 */ 107:Core/Src/main.c **** 108:Core/Src/main.c **** /* MCU Configuration--------------------------------------------------------*/ 109:Core/Src/main.c **** 110:Core/Src/main.c **** /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ 111:Core/Src/main.c **** HAL_Init(); 97 .loc 1 111 3 98 0006 FFF7FEFF bl HAL_Init 112:Core/Src/main.c **** 113:Core/Src/main.c **** /* USER CODE BEGIN Init */ 114:Core/Src/main.c **** 115:Core/Src/main.c **** /* USER CODE END Init */ ARM GAS /tmp/ccSWt3lr.s page 5 116:Core/Src/main.c **** 117:Core/Src/main.c **** /* Configure the system clock */ 118:Core/Src/main.c **** SystemClock_Config(); 99 .loc 1 118 3 100 000a FFF7FEFF bl SystemClock_Config 119:Core/Src/main.c **** 120:Core/Src/main.c **** /* USER CODE BEGIN SysInit */ 121:Core/Src/main.c **** 122:Core/Src/main.c **** /* USER CODE END SysInit */ 123:Core/Src/main.c **** 124:Core/Src/main.c **** /* Initialize all configured peripherals */ 125:Core/Src/main.c **** MX_GPIO_Init(); 101 .loc 1 125 3 102 000e FFF7FEFF bl MX_GPIO_Init 126:Core/Src/main.c **** MX_CAN_Init(); 103 .loc 1 126 3 104 0012 FFF7FEFF bl MX_CAN_Init 127:Core/Src/main.c **** MX_I2C1_Init(); 105 .loc 1 127 3 106 0016 FFF7FEFF bl MX_I2C1_Init 128:Core/Src/main.c **** MX_SPI1_Init(); 107 .loc 1 128 3 108 001a FFF7FEFF bl MX_SPI1_Init 129:Core/Src/main.c **** MX_TIM15_Init(); 109 .loc 1 129 3 110 001e FFF7FEFF bl MX_TIM15_Init 130:Core/Src/main.c **** MX_I2C2_Init(); 111 .loc 1 130 3 112 0022 FFF7FEFF bl MX_I2C2_Init 131:Core/Src/main.c **** MX_TIM2_Init(); 113 .loc 1 131 3 114 0026 FFF7FEFF bl MX_TIM2_Init 132:Core/Src/main.c **** MX_TIM3_Init(); 115 .loc 1 132 3 116 002a FFF7FEFF bl MX_TIM3_Init 133:Core/Src/main.c **** MX_TIM4_Init(); 117 .loc 1 133 3 118 002e FFF7FEFF bl MX_TIM4_Init 134:Core/Src/main.c **** /* USER CODE BEGIN 2 */ 135:Core/Src/main.c **** sm_init(); 119 .loc 1 135 3 120 0032 FFF7FEFF bl sm_init 136:Core/Src/main.c **** tmp1075_init(&hi2c1); 121 .loc 1 136 3 122 0036 1748 ldr r0, .L4 123 0038 FFF7FEFF bl tmp1075_init 137:Core/Src/main.c **** AMS_Init(&hspi1); 124 .loc 1 137 3 125 003c 1648 ldr r0, .L4+4 126 003e FFF7FEFF bl AMS_Init 138:Core/Src/main.c **** can_init(&hcan); 127 .loc 1 138 3 128 0042 1648 ldr r0, .L4+8 129 0044 FFF7FEFF bl can_init 139:Core/Src/main.c **** PWM_control_init(&htim3, &htim2, &htim15); 130 .loc 1 139 3 131 0048 154A ldr r2, .L4+12 ARM GAS /tmp/ccSWt3lr.s page 6 132 004a 1649 ldr r1, .L4+16 133 004c 1648 ldr r0, .L4+20 134 004e FFF7FEFF bl PWM_control_init 140:Core/Src/main.c **** soc_init(); 135 .loc 1 140 3 136 0052 FFF7FEFF bl soc_init 141:Core/Src/main.c **** status_led_init(&htim4, &htim4, &htim4); 137 .loc 1 141 3 138 0056 154A ldr r2, .L4+24 139 0058 1449 ldr r1, .L4+24 140 005a 1448 ldr r0, .L4+24 141 005c FFF7FEFF bl status_led_init 142:Core/Src/main.c **** sm_program_powerground(); 142 .loc 1 142 3 143 0060 FFF7FEFF bl sm_program_powerground 143:Core/Src/main.c **** eeprom_init(&hi2c2); 144 .loc 1 143 3 145 0064 1248 ldr r0, .L4+28 146 0066 FFF7FEFF bl eeprom_init 144:Core/Src/main.c **** AMS_Loop(); 147 .loc 1 144 3 148 006a FFF7FEFF bl AMS_Loop 145:Core/Src/main.c **** uint32_t startup_timer = 500 + HAL_GetTick(); 149 .loc 1 145 34 150 006e FFF7FEFF bl HAL_GetTick 151 0072 0346 mov r3, r0 152 .loc 1 145 12 discriminator 1 153 0074 03F5FA73 add r3, r3, #500 154 0078 7B60 str r3, [r7, #4] 146:Core/Src/main.c **** while (startup_timer > HAL_GetTick()); 155 .loc 1 146 9 156 007a 00BF nop 157 .L2: 158 .loc 1 146 26 discriminator 1 159 007c FFF7FEFF bl HAL_GetTick 160 0080 0246 mov r2, r0 161 .loc 1 146 24 discriminator 1 162 0082 7B68 ldr r3, [r7, #4] 163 0084 9342 cmp r3, r2 164 0086 F9D8 bhi .L2 165 .L3: 147:Core/Src/main.c **** /* USER CODE END 2 */ 148:Core/Src/main.c **** 149:Core/Src/main.c **** /* Infinite loop */ 150:Core/Src/main.c **** /* USER CODE BEGIN WHILE */ 151:Core/Src/main.c **** while (1) 152:Core/Src/main.c **** { 153:Core/Src/main.c **** /* USER CODE END WHILE */ 154:Core/Src/main.c **** 155:Core/Src/main.c **** /* USER CODE BEGIN 3 */ 156:Core/Src/main.c **** AMS_Loop(); 166 .loc 1 156 5 167 0088 FFF7FEFF bl AMS_Loop 157:Core/Src/main.c **** sm_update(); 168 .loc 1 157 5 discriminator 1 169 008c FFF7FEFF bl sm_update 156:Core/Src/main.c **** sm_update(); ARM GAS /tmp/ccSWt3lr.s page 7 170 .loc 1 156 5 171 0090 00BF nop 172 0092 F9E7 b .L3 173 .L5: 174 .align 2 175 .L4: 176 0094 00000000 .word hi2c1 177 0098 00000000 .word hspi1 178 009c 00000000 .word hcan 179 00a0 00000000 .word htim15 180 00a4 00000000 .word htim2 181 00a8 00000000 .word htim3 182 00ac 00000000 .word htim4 183 00b0 00000000 .word hi2c2 184 .cfi_endproc 185 .LFE130: 187 .section .text.SystemClock_Config,"ax",%progbits 188 .align 1 189 .global SystemClock_Config 190 .syntax unified 191 .thumb 192 .thumb_func 194 SystemClock_Config: 195 .LFB131: 158:Core/Src/main.c **** //sm_test_cycle_states(); 159:Core/Src/main.c **** } 160:Core/Src/main.c **** /* USER CODE END 3 */ 161:Core/Src/main.c **** } 162:Core/Src/main.c **** 163:Core/Src/main.c **** /** 164:Core/Src/main.c **** * @brief System Clock Configuration 165:Core/Src/main.c **** * @retval None 166:Core/Src/main.c **** */ 167:Core/Src/main.c **** void SystemClock_Config(void) 168:Core/Src/main.c **** { 196 .loc 1 168 1 197 .cfi_startproc 198 @ args = 0, pretend = 0, frame = 112 199 @ frame_needed = 1, uses_anonymous_args = 0 200 0000 80B5 push {r7, lr} 201 .cfi_def_cfa_offset 8 202 .cfi_offset 7, -8 203 .cfi_offset 14, -4 204 0002 9CB0 sub sp, sp, #112 205 .cfi_def_cfa_offset 120 206 0004 00AF add r7, sp, #0 207 .cfi_def_cfa_register 7 169:Core/Src/main.c **** RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 208 .loc 1 169 22 209 0006 07F14803 add r3, r7, #72 210 000a 2822 movs r2, #40 211 000c 0021 movs r1, #0 212 000e 1846 mov r0, r3 213 0010 FFF7FEFF bl memset 170:Core/Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 214 .loc 1 170 22 215 0014 07F13403 add r3, r7, #52 ARM GAS /tmp/ccSWt3lr.s page 8 216 0018 0022 movs r2, #0 217 001a 1A60 str r2, [r3] 218 001c 5A60 str r2, [r3, #4] 219 001e 9A60 str r2, [r3, #8] 220 0020 DA60 str r2, [r3, #12] 221 0022 1A61 str r2, [r3, #16] 171:Core/Src/main.c **** RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; 222 .loc 1 171 28 223 0024 3B46 mov r3, r7 224 0026 3422 movs r2, #52 225 0028 0021 movs r1, #0 226 002a 1846 mov r0, r3 227 002c FFF7FEFF bl memset 172:Core/Src/main.c **** 173:Core/Src/main.c **** /** Initializes the RCC Oscillators according to the specified parameters 174:Core/Src/main.c **** * in the RCC_OscInitTypeDef structure. 175:Core/Src/main.c **** */ 176:Core/Src/main.c **** RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; 228 .loc 1 176 36 229 0030 0123 movs r3, #1 230 0032 BB64 str r3, [r7, #72] 177:Core/Src/main.c **** RCC_OscInitStruct.HSEState = RCC_HSE_ON; 231 .loc 1 177 30 232 0034 4FF48033 mov r3, #65536 233 0038 FB64 str r3, [r7, #76] 178:Core/Src/main.c **** RCC_OscInitStruct.HSIState = RCC_HSI_ON; 234 .loc 1 178 30 235 003a 0123 movs r3, #1 236 003c BB65 str r3, [r7, #88] 179:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; 237 .loc 1 179 34 238 003e 0023 movs r3, #0 239 0040 7B66 str r3, [r7, #100] 180:Core/Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 240 .loc 1 180 7 241 0042 07F14803 add r3, r7, #72 242 0046 1846 mov r0, r3 243 0048 FFF7FEFF bl HAL_RCC_OscConfig 244 004c 0346 mov r3, r0 245 .loc 1 180 6 discriminator 1 246 004e 002B cmp r3, #0 247 0050 01D0 beq .L7 181:Core/Src/main.c **** { 182:Core/Src/main.c **** Error_Handler(); 248 .loc 1 182 5 249 0052 FFF7FEFF bl Error_Handler 250 .L7: 183:Core/Src/main.c **** } 184:Core/Src/main.c **** 185:Core/Src/main.c **** /** Initializes the CPU, AHB and APB buses clocks 186:Core/Src/main.c **** */ 187:Core/Src/main.c **** RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 251 .loc 1 187 31 252 0056 0F23 movs r3, #15 253 0058 7B63 str r3, [r7, #52] 188:Core/Src/main.c **** |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; 189:Core/Src/main.c **** RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE; ARM GAS /tmp/ccSWt3lr.s page 9 254 .loc 1 189 34 255 005a 0123 movs r3, #1 256 005c BB63 str r3, [r7, #56] 190:Core/Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 257 .loc 1 190 35 258 005e 0023 movs r3, #0 259 0060 FB63 str r3, [r7, #60] 191:Core/Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; 260 .loc 1 191 36 261 0062 0023 movs r3, #0 262 0064 3B64 str r3, [r7, #64] 192:Core/Src/main.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 263 .loc 1 192 36 264 0066 0023 movs r3, #0 265 0068 7B64 str r3, [r7, #68] 193:Core/Src/main.c **** 194:Core/Src/main.c **** if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) 266 .loc 1 194 7 267 006a 07F13403 add r3, r7, #52 268 006e 0021 movs r1, #0 269 0070 1846 mov r0, r3 270 0072 FFF7FEFF bl HAL_RCC_ClockConfig 271 0076 0346 mov r3, r0 272 .loc 1 194 6 discriminator 1 273 0078 002B cmp r3, #0 274 007a 01D0 beq .L8 195:Core/Src/main.c **** { 196:Core/Src/main.c **** Error_Handler(); 275 .loc 1 196 5 276 007c FFF7FEFF bl Error_Handler 277 .L8: 197:Core/Src/main.c **** } 198:Core/Src/main.c **** PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_I2C1|RCC_PERIPHCLK_I2C2; 278 .loc 1 198 38 279 0080 6023 movs r3, #96 280 0082 3B60 str r3, [r7] 199:Core/Src/main.c **** PeriphClkInit.I2c1ClockSelection = RCC_I2C1CLKSOURCE_SYSCLK; 281 .loc 1 199 36 282 0084 1023 movs r3, #16 283 0086 FB61 str r3, [r7, #28] 200:Core/Src/main.c **** PeriphClkInit.I2c2ClockSelection = RCC_I2C2CLKSOURCE_SYSCLK; 284 .loc 1 200 36 285 0088 2023 movs r3, #32 286 008a 3B62 str r3, [r7, #32] 201:Core/Src/main.c **** if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 287 .loc 1 201 7 288 008c 3B46 mov r3, r7 289 008e 1846 mov r0, r3 290 0090 FFF7FEFF bl HAL_RCCEx_PeriphCLKConfig 291 0094 0346 mov r3, r0 292 .loc 1 201 6 discriminator 1 293 0096 002B cmp r3, #0 294 0098 01D0 beq .L10 202:Core/Src/main.c **** { 203:Core/Src/main.c **** Error_Handler(); 295 .loc 1 203 5 296 009a FFF7FEFF bl Error_Handler ARM GAS /tmp/ccSWt3lr.s page 10 297 .L10: 204:Core/Src/main.c **** } 205:Core/Src/main.c **** } 298 .loc 1 205 1 299 009e 00BF nop 300 00a0 7037 adds r7, r7, #112 301 .cfi_def_cfa_offset 8 302 00a2 BD46 mov sp, r7 303 .cfi_def_cfa_register 13 304 @ sp needed 305 00a4 80BD pop {r7, pc} 306 .cfi_endproc 307 .LFE131: 309 .section .text.MX_CAN_Init,"ax",%progbits 310 .align 1 311 .syntax unified 312 .thumb 313 .thumb_func 315 MX_CAN_Init: 316 .LFB132: 206:Core/Src/main.c **** 207:Core/Src/main.c **** /** 208:Core/Src/main.c **** * @brief CAN Initialization Function 209:Core/Src/main.c **** * @param None 210:Core/Src/main.c **** * @retval None 211:Core/Src/main.c **** */ 212:Core/Src/main.c **** static void MX_CAN_Init(void) 213:Core/Src/main.c **** { 317 .loc 1 213 1 318 .cfi_startproc 319 @ args = 0, pretend = 0, frame = 0 320 @ frame_needed = 1, uses_anonymous_args = 0 321 0000 80B5 push {r7, lr} 322 .cfi_def_cfa_offset 8 323 .cfi_offset 7, -8 324 .cfi_offset 14, -4 325 0002 00AF add r7, sp, #0 326 .cfi_def_cfa_register 7 214:Core/Src/main.c **** 215:Core/Src/main.c **** /* USER CODE BEGIN CAN_Init 0 */ 216:Core/Src/main.c **** 217:Core/Src/main.c **** /* USER CODE END CAN_Init 0 */ 218:Core/Src/main.c **** 219:Core/Src/main.c **** /* USER CODE BEGIN CAN_Init 1 */ 220:Core/Src/main.c **** 221:Core/Src/main.c **** /* USER CODE END CAN_Init 1 */ 222:Core/Src/main.c **** hcan.Instance = CAN; 327 .loc 1 222 17 328 0004 174B ldr r3, .L14 329 0006 184A ldr r2, .L14+4 330 0008 1A60 str r2, [r3] 223:Core/Src/main.c **** hcan.Init.Prescaler = 2; 331 .loc 1 223 23 332 000a 164B ldr r3, .L14 333 000c 0222 movs r2, #2 334 000e 5A60 str r2, [r3, #4] 224:Core/Src/main.c **** hcan.Init.Mode = CAN_MODE_NORMAL; ARM GAS /tmp/ccSWt3lr.s page 11 335 .loc 1 224 18 336 0010 144B ldr r3, .L14 337 0012 0022 movs r2, #0 338 0014 9A60 str r2, [r3, #8] 225:Core/Src/main.c **** hcan.Init.SyncJumpWidth = CAN_SJW_1TQ; 339 .loc 1 225 27 340 0016 134B ldr r3, .L14 341 0018 0022 movs r2, #0 342 001a DA60 str r2, [r3, #12] 226:Core/Src/main.c **** hcan.Init.TimeSeg1 = CAN_BS1_13TQ; 343 .loc 1 226 22 344 001c 114B ldr r3, .L14 345 001e 4FF44022 mov r2, #786432 346 0022 1A61 str r2, [r3, #16] 227:Core/Src/main.c **** hcan.Init.TimeSeg2 = CAN_BS2_2TQ; 347 .loc 1 227 22 348 0024 0F4B ldr r3, .L14 349 0026 4FF48012 mov r2, #1048576 350 002a 5A61 str r2, [r3, #20] 228:Core/Src/main.c **** hcan.Init.TimeTriggeredMode = DISABLE; 351 .loc 1 228 31 352 002c 0D4B ldr r3, .L14 353 002e 0022 movs r2, #0 354 0030 1A76 strb r2, [r3, #24] 229:Core/Src/main.c **** hcan.Init.AutoBusOff = ENABLE; 355 .loc 1 229 24 356 0032 0C4B ldr r3, .L14 357 0034 0122 movs r2, #1 358 0036 5A76 strb r2, [r3, #25] 230:Core/Src/main.c **** hcan.Init.AutoWakeUp = DISABLE; 359 .loc 1 230 24 360 0038 0A4B ldr r3, .L14 361 003a 0022 movs r2, #0 362 003c 9A76 strb r2, [r3, #26] 231:Core/Src/main.c **** hcan.Init.AutoRetransmission = ENABLE; 363 .loc 1 231 32 364 003e 094B ldr r3, .L14 365 0040 0122 movs r2, #1 366 0042 DA76 strb r2, [r3, #27] 232:Core/Src/main.c **** hcan.Init.ReceiveFifoLocked = DISABLE; 367 .loc 1 232 31 368 0044 074B ldr r3, .L14 369 0046 0022 movs r2, #0 370 0048 1A77 strb r2, [r3, #28] 233:Core/Src/main.c **** hcan.Init.TransmitFifoPriority = DISABLE; 371 .loc 1 233 34 372 004a 064B ldr r3, .L14 373 004c 0022 movs r2, #0 374 004e 5A77 strb r2, [r3, #29] 234:Core/Src/main.c **** if (HAL_CAN_Init(&hcan) != HAL_OK) 375 .loc 1 234 7 376 0050 0448 ldr r0, .L14 377 0052 FFF7FEFF bl HAL_CAN_Init 378 0056 0346 mov r3, r0 379 .loc 1 234 6 discriminator 1 380 0058 002B cmp r3, #0 381 005a 01D0 beq .L13 ARM GAS /tmp/ccSWt3lr.s page 12 235:Core/Src/main.c **** { 236:Core/Src/main.c **** Error_Handler(); 382 .loc 1 236 5 383 005c FFF7FEFF bl Error_Handler 384 .L13: 237:Core/Src/main.c **** } 238:Core/Src/main.c **** /* USER CODE BEGIN CAN_Init 2 */ 239:Core/Src/main.c **** 240:Core/Src/main.c **** /* USER CODE END CAN_Init 2 */ 241:Core/Src/main.c **** 242:Core/Src/main.c **** } 385 .loc 1 242 1 386 0060 00BF nop 387 0062 80BD pop {r7, pc} 388 .L15: 389 .align 2 390 .L14: 391 0064 00000000 .word hcan 392 0068 00640040 .word 1073767424 393 .cfi_endproc 394 .LFE132: 396 .section .text.MX_I2C1_Init,"ax",%progbits 397 .align 1 398 .syntax unified 399 .thumb 400 .thumb_func 402 MX_I2C1_Init: 403 .LFB133: 243:Core/Src/main.c **** 244:Core/Src/main.c **** /** 245:Core/Src/main.c **** * @brief I2C1 Initialization Function 246:Core/Src/main.c **** * @param None 247:Core/Src/main.c **** * @retval None 248:Core/Src/main.c **** */ 249:Core/Src/main.c **** static void MX_I2C1_Init(void) 250:Core/Src/main.c **** { 404 .loc 1 250 1 405 .cfi_startproc 406 @ args = 0, pretend = 0, frame = 0 407 @ frame_needed = 1, uses_anonymous_args = 0 408 0000 80B5 push {r7, lr} 409 .cfi_def_cfa_offset 8 410 .cfi_offset 7, -8 411 .cfi_offset 14, -4 412 0002 00AF add r7, sp, #0 413 .cfi_def_cfa_register 7 251:Core/Src/main.c **** 252:Core/Src/main.c **** /* USER CODE BEGIN I2C1_Init 0 */ 253:Core/Src/main.c **** 254:Core/Src/main.c **** /* USER CODE END I2C1_Init 0 */ 255:Core/Src/main.c **** 256:Core/Src/main.c **** /* USER CODE BEGIN I2C1_Init 1 */ 257:Core/Src/main.c **** 258:Core/Src/main.c **** /* USER CODE END I2C1_Init 1 */ 259:Core/Src/main.c **** hi2c1.Instance = I2C1; 414 .loc 1 259 18 415 0004 1B4B ldr r3, .L21 ARM GAS /tmp/ccSWt3lr.s page 13 416 0006 1C4A ldr r2, .L21+4 417 0008 1A60 str r2, [r3] 260:Core/Src/main.c **** hi2c1.Init.Timing = 0x00303D5B; 418 .loc 1 260 21 419 000a 1A4B ldr r3, .L21 420 000c 1B4A ldr r2, .L21+8 421 000e 5A60 str r2, [r3, #4] 261:Core/Src/main.c **** hi2c1.Init.OwnAddress1 = 0; 422 .loc 1 261 26 423 0010 184B ldr r3, .L21 424 0012 0022 movs r2, #0 425 0014 9A60 str r2, [r3, #8] 262:Core/Src/main.c **** hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; 426 .loc 1 262 29 427 0016 174B ldr r3, .L21 428 0018 0122 movs r2, #1 429 001a DA60 str r2, [r3, #12] 263:Core/Src/main.c **** hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; 430 .loc 1 263 30 431 001c 154B ldr r3, .L21 432 001e 0022 movs r2, #0 433 0020 1A61 str r2, [r3, #16] 264:Core/Src/main.c **** hi2c1.Init.OwnAddress2 = 0; 434 .loc 1 264 26 435 0022 144B ldr r3, .L21 436 0024 0022 movs r2, #0 437 0026 5A61 str r2, [r3, #20] 265:Core/Src/main.c **** hi2c1.Init.OwnAddress2Masks = I2C_OA2_NOMASK; 438 .loc 1 265 31 439 0028 124B ldr r3, .L21 440 002a 0022 movs r2, #0 441 002c 9A61 str r2, [r3, #24] 266:Core/Src/main.c **** hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; 442 .loc 1 266 30 443 002e 114B ldr r3, .L21 444 0030 0022 movs r2, #0 445 0032 DA61 str r2, [r3, #28] 267:Core/Src/main.c **** hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; 446 .loc 1 267 28 447 0034 0F4B ldr r3, .L21 448 0036 0022 movs r2, #0 449 0038 1A62 str r2, [r3, #32] 268:Core/Src/main.c **** if (HAL_I2C_Init(&hi2c1) != HAL_OK) 450 .loc 1 268 7 451 003a 0E48 ldr r0, .L21 452 003c FFF7FEFF bl HAL_I2C_Init 453 0040 0346 mov r3, r0 454 .loc 1 268 6 discriminator 1 455 0042 002B cmp r3, #0 456 0044 01D0 beq .L17 269:Core/Src/main.c **** { 270:Core/Src/main.c **** Error_Handler(); 457 .loc 1 270 5 458 0046 FFF7FEFF bl Error_Handler 459 .L17: 271:Core/Src/main.c **** } 272:Core/Src/main.c **** ARM GAS /tmp/ccSWt3lr.s page 14 273:Core/Src/main.c **** /** Configure Analogue filter 274:Core/Src/main.c **** */ 275:Core/Src/main.c **** if (HAL_I2CEx_ConfigAnalogFilter(&hi2c1, I2C_ANALOGFILTER_ENABLE) != HAL_OK) 460 .loc 1 275 7 461 004a 0021 movs r1, #0 462 004c 0948 ldr r0, .L21 463 004e FFF7FEFF bl HAL_I2CEx_ConfigAnalogFilter 464 0052 0346 mov r3, r0 465 .loc 1 275 6 discriminator 1 466 0054 002B cmp r3, #0 467 0056 01D0 beq .L18 276:Core/Src/main.c **** { 277:Core/Src/main.c **** Error_Handler(); 468 .loc 1 277 5 469 0058 FFF7FEFF bl Error_Handler 470 .L18: 278:Core/Src/main.c **** } 279:Core/Src/main.c **** 280:Core/Src/main.c **** /** Configure Digital filter 281:Core/Src/main.c **** */ 282:Core/Src/main.c **** if (HAL_I2CEx_ConfigDigitalFilter(&hi2c1, 0) != HAL_OK) 471 .loc 1 282 7 472 005c 0021 movs r1, #0 473 005e 0548 ldr r0, .L21 474 0060 FFF7FEFF bl HAL_I2CEx_ConfigDigitalFilter 475 0064 0346 mov r3, r0 476 .loc 1 282 6 discriminator 1 477 0066 002B cmp r3, #0 478 0068 01D0 beq .L20 283:Core/Src/main.c **** { 284:Core/Src/main.c **** Error_Handler(); 479 .loc 1 284 5 480 006a FFF7FEFF bl Error_Handler 481 .L20: 285:Core/Src/main.c **** } 286:Core/Src/main.c **** /* USER CODE BEGIN I2C1_Init 2 */ 287:Core/Src/main.c **** 288:Core/Src/main.c **** /* USER CODE END I2C1_Init 2 */ 289:Core/Src/main.c **** 290:Core/Src/main.c **** } 482 .loc 1 290 1 483 006e 00BF nop 484 0070 80BD pop {r7, pc} 485 .L22: 486 0072 00BF .align 2 487 .L21: 488 0074 00000000 .word hi2c1 489 0078 00540040 .word 1073763328 490 007c 5B3D3000 .word 3161435 491 .cfi_endproc 492 .LFE133: 494 .section .text.MX_I2C2_Init,"ax",%progbits 495 .align 1 496 .syntax unified 497 .thumb 498 .thumb_func 500 MX_I2C2_Init: ARM GAS /tmp/ccSWt3lr.s page 15 501 .LFB134: 291:Core/Src/main.c **** 292:Core/Src/main.c **** /** 293:Core/Src/main.c **** * @brief I2C2 Initialization Function 294:Core/Src/main.c **** * @param None 295:Core/Src/main.c **** * @retval None 296:Core/Src/main.c **** */ 297:Core/Src/main.c **** static void MX_I2C2_Init(void) 298:Core/Src/main.c **** { 502 .loc 1 298 1 503 .cfi_startproc 504 @ args = 0, pretend = 0, frame = 0 505 @ frame_needed = 1, uses_anonymous_args = 0 506 0000 80B5 push {r7, lr} 507 .cfi_def_cfa_offset 8 508 .cfi_offset 7, -8 509 .cfi_offset 14, -4 510 0002 00AF add r7, sp, #0 511 .cfi_def_cfa_register 7 299:Core/Src/main.c **** 300:Core/Src/main.c **** /* USER CODE BEGIN I2C2_Init 0 */ 301:Core/Src/main.c **** 302:Core/Src/main.c **** /* USER CODE END I2C2_Init 0 */ 303:Core/Src/main.c **** 304:Core/Src/main.c **** /* USER CODE BEGIN I2C2_Init 1 */ 305:Core/Src/main.c **** 306:Core/Src/main.c **** /* USER CODE END I2C2_Init 1 */ 307:Core/Src/main.c **** hi2c2.Instance = I2C2; 512 .loc 1 307 18 513 0004 1B4B ldr r3, .L28 514 0006 1C4A ldr r2, .L28+4 515 0008 1A60 str r2, [r3] 308:Core/Src/main.c **** hi2c2.Init.Timing = 0x00303D5B; 516 .loc 1 308 21 517 000a 1A4B ldr r3, .L28 518 000c 1B4A ldr r2, .L28+8 519 000e 5A60 str r2, [r3, #4] 309:Core/Src/main.c **** hi2c2.Init.OwnAddress1 = 0; 520 .loc 1 309 26 521 0010 184B ldr r3, .L28 522 0012 0022 movs r2, #0 523 0014 9A60 str r2, [r3, #8] 310:Core/Src/main.c **** hi2c2.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; 524 .loc 1 310 29 525 0016 174B ldr r3, .L28 526 0018 0122 movs r2, #1 527 001a DA60 str r2, [r3, #12] 311:Core/Src/main.c **** hi2c2.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; 528 .loc 1 311 30 529 001c 154B ldr r3, .L28 530 001e 0022 movs r2, #0 531 0020 1A61 str r2, [r3, #16] 312:Core/Src/main.c **** hi2c2.Init.OwnAddress2 = 0; 532 .loc 1 312 26 533 0022 144B ldr r3, .L28 534 0024 0022 movs r2, #0 535 0026 5A61 str r2, [r3, #20] ARM GAS /tmp/ccSWt3lr.s page 16 313:Core/Src/main.c **** hi2c2.Init.OwnAddress2Masks = I2C_OA2_NOMASK; 536 .loc 1 313 31 537 0028 124B ldr r3, .L28 538 002a 0022 movs r2, #0 539 002c 9A61 str r2, [r3, #24] 314:Core/Src/main.c **** hi2c2.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; 540 .loc 1 314 30 541 002e 114B ldr r3, .L28 542 0030 0022 movs r2, #0 543 0032 DA61 str r2, [r3, #28] 315:Core/Src/main.c **** hi2c2.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; 544 .loc 1 315 28 545 0034 0F4B ldr r3, .L28 546 0036 0022 movs r2, #0 547 0038 1A62 str r2, [r3, #32] 316:Core/Src/main.c **** if (HAL_I2C_Init(&hi2c2) != HAL_OK) 548 .loc 1 316 7 549 003a 0E48 ldr r0, .L28 550 003c FFF7FEFF bl HAL_I2C_Init 551 0040 0346 mov r3, r0 552 .loc 1 316 6 discriminator 1 553 0042 002B cmp r3, #0 554 0044 01D0 beq .L24 317:Core/Src/main.c **** { 318:Core/Src/main.c **** Error_Handler(); 555 .loc 1 318 5 556 0046 FFF7FEFF bl Error_Handler 557 .L24: 319:Core/Src/main.c **** } 320:Core/Src/main.c **** 321:Core/Src/main.c **** /** Configure Analogue filter 322:Core/Src/main.c **** */ 323:Core/Src/main.c **** if (HAL_I2CEx_ConfigAnalogFilter(&hi2c2, I2C_ANALOGFILTER_ENABLE) != HAL_OK) 558 .loc 1 323 7 559 004a 0021 movs r1, #0 560 004c 0948 ldr r0, .L28 561 004e FFF7FEFF bl HAL_I2CEx_ConfigAnalogFilter 562 0052 0346 mov r3, r0 563 .loc 1 323 6 discriminator 1 564 0054 002B cmp r3, #0 565 0056 01D0 beq .L25 324:Core/Src/main.c **** { 325:Core/Src/main.c **** Error_Handler(); 566 .loc 1 325 5 567 0058 FFF7FEFF bl Error_Handler 568 .L25: 326:Core/Src/main.c **** } 327:Core/Src/main.c **** 328:Core/Src/main.c **** /** Configure Digital filter 329:Core/Src/main.c **** */ 330:Core/Src/main.c **** if (HAL_I2CEx_ConfigDigitalFilter(&hi2c2, 0) != HAL_OK) 569 .loc 1 330 7 570 005c 0021 movs r1, #0 571 005e 0548 ldr r0, .L28 572 0060 FFF7FEFF bl HAL_I2CEx_ConfigDigitalFilter 573 0064 0346 mov r3, r0 574 .loc 1 330 6 discriminator 1 ARM GAS /tmp/ccSWt3lr.s page 17 575 0066 002B cmp r3, #0 576 0068 01D0 beq .L27 331:Core/Src/main.c **** { 332:Core/Src/main.c **** Error_Handler(); 577 .loc 1 332 5 578 006a FFF7FEFF bl Error_Handler 579 .L27: 333:Core/Src/main.c **** } 334:Core/Src/main.c **** /* USER CODE BEGIN I2C2_Init 2 */ 335:Core/Src/main.c **** 336:Core/Src/main.c **** /* USER CODE END I2C2_Init 2 */ 337:Core/Src/main.c **** 338:Core/Src/main.c **** } 580 .loc 1 338 1 581 006e 00BF nop 582 0070 80BD pop {r7, pc} 583 .L29: 584 0072 00BF .align 2 585 .L28: 586 0074 00000000 .word hi2c2 587 0078 00580040 .word 1073764352 588 007c 5B3D3000 .word 3161435 589 .cfi_endproc 590 .LFE134: 592 .section .text.MX_SPI1_Init,"ax",%progbits 593 .align 1 594 .syntax unified 595 .thumb 596 .thumb_func 598 MX_SPI1_Init: 599 .LFB135: 339:Core/Src/main.c **** 340:Core/Src/main.c **** /** 341:Core/Src/main.c **** * @brief SPI1 Initialization Function 342:Core/Src/main.c **** * @param None 343:Core/Src/main.c **** * @retval None 344:Core/Src/main.c **** */ 345:Core/Src/main.c **** static void MX_SPI1_Init(void) 346:Core/Src/main.c **** { 600 .loc 1 346 1 601 .cfi_startproc 602 @ args = 0, pretend = 0, frame = 0 603 @ frame_needed = 1, uses_anonymous_args = 0 604 0000 80B5 push {r7, lr} 605 .cfi_def_cfa_offset 8 606 .cfi_offset 7, -8 607 .cfi_offset 14, -4 608 0002 00AF add r7, sp, #0 609 .cfi_def_cfa_register 7 347:Core/Src/main.c **** 348:Core/Src/main.c **** /* USER CODE BEGIN SPI1_Init 0 */ 349:Core/Src/main.c **** 350:Core/Src/main.c **** /* USER CODE END SPI1_Init 0 */ 351:Core/Src/main.c **** 352:Core/Src/main.c **** /* USER CODE BEGIN SPI1_Init 1 */ 353:Core/Src/main.c **** 354:Core/Src/main.c **** /* USER CODE END SPI1_Init 1 */ ARM GAS /tmp/ccSWt3lr.s page 18 355:Core/Src/main.c **** /* SPI1 parameter configuration*/ 356:Core/Src/main.c **** hspi1.Instance = SPI1; 610 .loc 1 356 18 611 0004 1B4B ldr r3, .L33 612 0006 1C4A ldr r2, .L33+4 613 0008 1A60 str r2, [r3] 357:Core/Src/main.c **** hspi1.Init.Mode = SPI_MODE_MASTER; 614 .loc 1 357 19 615 000a 1A4B ldr r3, .L33 616 000c 4FF48272 mov r2, #260 617 0010 5A60 str r2, [r3, #4] 358:Core/Src/main.c **** hspi1.Init.Direction = SPI_DIRECTION_2LINES; 618 .loc 1 358 24 619 0012 184B ldr r3, .L33 620 0014 0022 movs r2, #0 621 0016 9A60 str r2, [r3, #8] 359:Core/Src/main.c **** hspi1.Init.DataSize = SPI_DATASIZE_8BIT; 622 .loc 1 359 23 623 0018 164B ldr r3, .L33 624 001a 4FF4E062 mov r2, #1792 625 001e DA60 str r2, [r3, #12] 360:Core/Src/main.c **** hspi1.Init.CLKPolarity = SPI_POLARITY_LOW; 626 .loc 1 360 26 627 0020 144B ldr r3, .L33 628 0022 0022 movs r2, #0 629 0024 1A61 str r2, [r3, #16] 361:Core/Src/main.c **** hspi1.Init.CLKPhase = SPI_PHASE_1EDGE; 630 .loc 1 361 23 631 0026 134B ldr r3, .L33 632 0028 0022 movs r2, #0 633 002a 5A61 str r2, [r3, #20] 362:Core/Src/main.c **** hspi1.Init.NSS = SPI_NSS_SOFT; 634 .loc 1 362 18 635 002c 114B ldr r3, .L33 636 002e 4FF40072 mov r2, #512 637 0032 9A61 str r2, [r3, #24] 363:Core/Src/main.c **** hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_32; 638 .loc 1 363 32 639 0034 0F4B ldr r3, .L33 640 0036 2022 movs r2, #32 641 0038 DA61 str r2, [r3, #28] 364:Core/Src/main.c **** hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; 642 .loc 1 364 23 643 003a 0E4B ldr r3, .L33 644 003c 0022 movs r2, #0 645 003e 1A62 str r2, [r3, #32] 365:Core/Src/main.c **** hspi1.Init.TIMode = SPI_TIMODE_DISABLE; 646 .loc 1 365 21 647 0040 0C4B ldr r3, .L33 648 0042 0022 movs r2, #0 649 0044 5A62 str r2, [r3, #36] 366:Core/Src/main.c **** hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; 650 .loc 1 366 29 651 0046 0B4B ldr r3, .L33 652 0048 0022 movs r2, #0 653 004a 9A62 str r2, [r3, #40] 367:Core/Src/main.c **** hspi1.Init.CRCPolynomial = 7; ARM GAS /tmp/ccSWt3lr.s page 19 654 .loc 1 367 28 655 004c 094B ldr r3, .L33 656 004e 0722 movs r2, #7 657 0050 DA62 str r2, [r3, #44] 368:Core/Src/main.c **** hspi1.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE; 658 .loc 1 368 24 659 0052 084B ldr r3, .L33 660 0054 0022 movs r2, #0 661 0056 1A63 str r2, [r3, #48] 369:Core/Src/main.c **** hspi1.Init.NSSPMode = SPI_NSS_PULSE_ENABLE; 662 .loc 1 369 23 663 0058 064B ldr r3, .L33 664 005a 0822 movs r2, #8 665 005c 5A63 str r2, [r3, #52] 370:Core/Src/main.c **** if (HAL_SPI_Init(&hspi1) != HAL_OK) 666 .loc 1 370 7 667 005e 0548 ldr r0, .L33 668 0060 FFF7FEFF bl HAL_SPI_Init 669 0064 0346 mov r3, r0 670 .loc 1 370 6 discriminator 1 671 0066 002B cmp r3, #0 672 0068 01D0 beq .L32 371:Core/Src/main.c **** { 372:Core/Src/main.c **** Error_Handler(); 673 .loc 1 372 5 674 006a FFF7FEFF bl Error_Handler 675 .L32: 373:Core/Src/main.c **** } 374:Core/Src/main.c **** /* USER CODE BEGIN SPI1_Init 2 */ 375:Core/Src/main.c **** 376:Core/Src/main.c **** /* USER CODE END SPI1_Init 2 */ 377:Core/Src/main.c **** 378:Core/Src/main.c **** } 676 .loc 1 378 1 677 006e 00BF nop 678 0070 80BD pop {r7, pc} 679 .L34: 680 0072 00BF .align 2 681 .L33: 682 0074 00000000 .word hspi1 683 0078 00300140 .word 1073819648 684 .cfi_endproc 685 .LFE135: 687 .section .text.MX_TIM2_Init,"ax",%progbits 688 .align 1 689 .syntax unified 690 .thumb 691 .thumb_func 693 MX_TIM2_Init: 694 .LFB136: 379:Core/Src/main.c **** 380:Core/Src/main.c **** /** 381:Core/Src/main.c **** * @brief TIM2 Initialization Function 382:Core/Src/main.c **** * @param None 383:Core/Src/main.c **** * @retval None 384:Core/Src/main.c **** */ 385:Core/Src/main.c **** static void MX_TIM2_Init(void) ARM GAS /tmp/ccSWt3lr.s page 20 386:Core/Src/main.c **** { 695 .loc 1 386 1 696 .cfi_startproc 697 @ args = 0, pretend = 0, frame = 40 698 @ frame_needed = 1, uses_anonymous_args = 0 699 0000 80B5 push {r7, lr} 700 .cfi_def_cfa_offset 8 701 .cfi_offset 7, -8 702 .cfi_offset 14, -4 703 0002 8AB0 sub sp, sp, #40 704 .cfi_def_cfa_offset 48 705 0004 00AF add r7, sp, #0 706 .cfi_def_cfa_register 7 387:Core/Src/main.c **** 388:Core/Src/main.c **** /* USER CODE BEGIN TIM2_Init 0 */ 389:Core/Src/main.c **** 390:Core/Src/main.c **** /* USER CODE END TIM2_Init 0 */ 391:Core/Src/main.c **** 392:Core/Src/main.c **** TIM_MasterConfigTypeDef sMasterConfig = {0}; 707 .loc 1 392 27 708 0006 07F11C03 add r3, r7, #28 709 000a 0022 movs r2, #0 710 000c 1A60 str r2, [r3] 711 000e 5A60 str r2, [r3, #4] 712 0010 9A60 str r2, [r3, #8] 393:Core/Src/main.c **** TIM_OC_InitTypeDef sConfigOC = {0}; 713 .loc 1 393 22 714 0012 3B46 mov r3, r7 715 0014 0022 movs r2, #0 716 0016 1A60 str r2, [r3] 717 0018 5A60 str r2, [r3, #4] 718 001a 9A60 str r2, [r3, #8] 719 001c DA60 str r2, [r3, #12] 720 001e 1A61 str r2, [r3, #16] 721 0020 5A61 str r2, [r3, #20] 722 0022 9A61 str r2, [r3, #24] 394:Core/Src/main.c **** 395:Core/Src/main.c **** /* USER CODE BEGIN TIM2_Init 1 */ 396:Core/Src/main.c **** 397:Core/Src/main.c **** /* USER CODE END TIM2_Init 1 */ 398:Core/Src/main.c **** htim2.Instance = TIM2; 723 .loc 1 398 18 724 0024 274B ldr r3, .L40 725 0026 4FF08042 mov r2, #1073741824 726 002a 1A60 str r2, [r3] 399:Core/Src/main.c **** htim2.Init.Prescaler = 0; 727 .loc 1 399 24 728 002c 254B ldr r3, .L40 729 002e 0022 movs r2, #0 730 0030 5A60 str r2, [r3, #4] 400:Core/Src/main.c **** htim2.Init.CounterMode = TIM_COUNTERMODE_UP; 731 .loc 1 400 26 732 0032 244B ldr r3, .L40 733 0034 0022 movs r2, #0 734 0036 9A60 str r2, [r3, #8] 401:Core/Src/main.c **** htim2.Init.Period = 4294967295; 735 .loc 1 401 21 ARM GAS /tmp/ccSWt3lr.s page 21 736 0038 224B ldr r3, .L40 737 003a 4FF0FF32 mov r2, #-1 738 003e DA60 str r2, [r3, #12] 402:Core/Src/main.c **** htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 739 .loc 1 402 28 740 0040 204B ldr r3, .L40 741 0042 0022 movs r2, #0 742 0044 1A61 str r2, [r3, #16] 403:Core/Src/main.c **** htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 743 .loc 1 403 32 744 0046 1F4B ldr r3, .L40 745 0048 0022 movs r2, #0 746 004a 9A61 str r2, [r3, #24] 404:Core/Src/main.c **** if (HAL_TIM_PWM_Init(&htim2) != HAL_OK) 747 .loc 1 404 7 748 004c 1D48 ldr r0, .L40 749 004e FFF7FEFF bl HAL_TIM_PWM_Init 750 0052 0346 mov r3, r0 751 .loc 1 404 6 discriminator 1 752 0054 002B cmp r3, #0 753 0056 01D0 beq .L36 405:Core/Src/main.c **** { 406:Core/Src/main.c **** Error_Handler(); 754 .loc 1 406 5 755 0058 FFF7FEFF bl Error_Handler 756 .L36: 407:Core/Src/main.c **** } 408:Core/Src/main.c **** sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 757 .loc 1 408 37 758 005c 0023 movs r3, #0 759 005e FB61 str r3, [r7, #28] 409:Core/Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 760 .loc 1 409 33 761 0060 0023 movs r3, #0 762 0062 7B62 str r3, [r7, #36] 410:Core/Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) 763 .loc 1 410 7 764 0064 07F11C03 add r3, r7, #28 765 0068 1946 mov r1, r3 766 006a 1648 ldr r0, .L40 767 006c FFF7FEFF bl HAL_TIMEx_MasterConfigSynchronization 768 0070 0346 mov r3, r0 769 .loc 1 410 6 discriminator 1 770 0072 002B cmp r3, #0 771 0074 01D0 beq .L37 411:Core/Src/main.c **** { 412:Core/Src/main.c **** Error_Handler(); 772 .loc 1 412 5 773 0076 FFF7FEFF bl Error_Handler 774 .L37: 413:Core/Src/main.c **** } 414:Core/Src/main.c **** sConfigOC.OCMode = TIM_OCMODE_PWM1; 775 .loc 1 414 20 776 007a 6023 movs r3, #96 777 007c 3B60 str r3, [r7] 415:Core/Src/main.c **** sConfigOC.Pulse = 0; 778 .loc 1 415 19 ARM GAS /tmp/ccSWt3lr.s page 22 779 007e 0023 movs r3, #0 780 0080 7B60 str r3, [r7, #4] 416:Core/Src/main.c **** sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 781 .loc 1 416 24 782 0082 0023 movs r3, #0 783 0084 BB60 str r3, [r7, #8] 417:Core/Src/main.c **** sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 784 .loc 1 417 24 785 0086 0023 movs r3, #0 786 0088 3B61 str r3, [r7, #16] 418:Core/Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) 787 .loc 1 418 7 788 008a 3B46 mov r3, r7 789 008c 0822 movs r2, #8 790 008e 1946 mov r1, r3 791 0090 0C48 ldr r0, .L40 792 0092 FFF7FEFF bl HAL_TIM_PWM_ConfigChannel 793 0096 0346 mov r3, r0 794 .loc 1 418 6 discriminator 1 795 0098 002B cmp r3, #0 796 009a 01D0 beq .L38 419:Core/Src/main.c **** { 420:Core/Src/main.c **** Error_Handler(); 797 .loc 1 420 5 798 009c FFF7FEFF bl Error_Handler 799 .L38: 421:Core/Src/main.c **** } 422:Core/Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) 800 .loc 1 422 7 801 00a0 3B46 mov r3, r7 802 00a2 0C22 movs r2, #12 803 00a4 1946 mov r1, r3 804 00a6 0748 ldr r0, .L40 805 00a8 FFF7FEFF bl HAL_TIM_PWM_ConfigChannel 806 00ac 0346 mov r3, r0 807 .loc 1 422 6 discriminator 1 808 00ae 002B cmp r3, #0 809 00b0 01D0 beq .L39 423:Core/Src/main.c **** { 424:Core/Src/main.c **** Error_Handler(); 810 .loc 1 424 5 811 00b2 FFF7FEFF bl Error_Handler 812 .L39: 425:Core/Src/main.c **** } 426:Core/Src/main.c **** /* USER CODE BEGIN TIM2_Init 2 */ 427:Core/Src/main.c **** 428:Core/Src/main.c **** /* USER CODE END TIM2_Init 2 */ 429:Core/Src/main.c **** HAL_TIM_MspPostInit(&htim2); 813 .loc 1 429 3 814 00b6 0348 ldr r0, .L40 815 00b8 FFF7FEFF bl HAL_TIM_MspPostInit 430:Core/Src/main.c **** 431:Core/Src/main.c **** } 816 .loc 1 431 1 817 00bc 00BF nop 818 00be 2837 adds r7, r7, #40 819 .cfi_def_cfa_offset 8 ARM GAS /tmp/ccSWt3lr.s page 23 820 00c0 BD46 mov sp, r7 821 .cfi_def_cfa_register 13 822 @ sp needed 823 00c2 80BD pop {r7, pc} 824 .L41: 825 .align 2 826 .L40: 827 00c4 00000000 .word htim2 828 .cfi_endproc 829 .LFE136: 831 .section .text.MX_TIM3_Init,"ax",%progbits 832 .align 1 833 .syntax unified 834 .thumb 835 .thumb_func 837 MX_TIM3_Init: 838 .LFB137: 432:Core/Src/main.c **** 433:Core/Src/main.c **** /** 434:Core/Src/main.c **** * @brief TIM3 Initialization Function 435:Core/Src/main.c **** * @param None 436:Core/Src/main.c **** * @retval None 437:Core/Src/main.c **** */ 438:Core/Src/main.c **** static void MX_TIM3_Init(void) 439:Core/Src/main.c **** { 839 .loc 1 439 1 840 .cfi_startproc 841 @ args = 0, pretend = 0, frame = 40 842 @ frame_needed = 1, uses_anonymous_args = 0 843 0000 80B5 push {r7, lr} 844 .cfi_def_cfa_offset 8 845 .cfi_offset 7, -8 846 .cfi_offset 14, -4 847 0002 8AB0 sub sp, sp, #40 848 .cfi_def_cfa_offset 48 849 0004 00AF add r7, sp, #0 850 .cfi_def_cfa_register 7 440:Core/Src/main.c **** 441:Core/Src/main.c **** /* USER CODE BEGIN TIM3_Init 0 */ 442:Core/Src/main.c **** 443:Core/Src/main.c **** /* USER CODE END TIM3_Init 0 */ 444:Core/Src/main.c **** 445:Core/Src/main.c **** TIM_MasterConfigTypeDef sMasterConfig = {0}; 851 .loc 1 445 27 852 0006 07F11C03 add r3, r7, #28 853 000a 0022 movs r2, #0 854 000c 1A60 str r2, [r3] 855 000e 5A60 str r2, [r3, #4] 856 0010 9A60 str r2, [r3, #8] 446:Core/Src/main.c **** TIM_OC_InitTypeDef sConfigOC = {0}; 857 .loc 1 446 22 858 0012 3B46 mov r3, r7 859 0014 0022 movs r2, #0 860 0016 1A60 str r2, [r3] 861 0018 5A60 str r2, [r3, #4] 862 001a 9A60 str r2, [r3, #8] 863 001c DA60 str r2, [r3, #12] ARM GAS /tmp/ccSWt3lr.s page 24 864 001e 1A61 str r2, [r3, #16] 865 0020 5A61 str r2, [r3, #20] 866 0022 9A61 str r2, [r3, #24] 447:Core/Src/main.c **** 448:Core/Src/main.c **** /* USER CODE BEGIN TIM3_Init 1 */ 449:Core/Src/main.c **** 450:Core/Src/main.c **** /* USER CODE END TIM3_Init 1 */ 451:Core/Src/main.c **** htim3.Instance = TIM3; 867 .loc 1 451 18 868 0024 274B ldr r3, .L47 869 0026 284A ldr r2, .L47+4 870 0028 1A60 str r2, [r3] 452:Core/Src/main.c **** htim3.Init.Prescaler = 7; 871 .loc 1 452 24 872 002a 264B ldr r3, .L47 873 002c 0722 movs r2, #7 874 002e 5A60 str r2, [r3, #4] 453:Core/Src/main.c **** htim3.Init.CounterMode = TIM_COUNTERMODE_UP; 875 .loc 1 453 26 876 0030 244B ldr r3, .L47 877 0032 0022 movs r2, #0 878 0034 9A60 str r2, [r3, #8] 454:Core/Src/main.c **** htim3.Init.Period = 39999; 879 .loc 1 454 21 880 0036 234B ldr r3, .L47 881 0038 49F63F42 movw r2, #39999 882 003c DA60 str r2, [r3, #12] 455:Core/Src/main.c **** htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 883 .loc 1 455 28 884 003e 214B ldr r3, .L47 885 0040 0022 movs r2, #0 886 0042 1A61 str r2, [r3, #16] 456:Core/Src/main.c **** htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 887 .loc 1 456 32 888 0044 1F4B ldr r3, .L47 889 0046 0022 movs r2, #0 890 0048 9A61 str r2, [r3, #24] 457:Core/Src/main.c **** if (HAL_TIM_PWM_Init(&htim3) != HAL_OK) 891 .loc 1 457 7 892 004a 1E48 ldr r0, .L47 893 004c FFF7FEFF bl HAL_TIM_PWM_Init 894 0050 0346 mov r3, r0 895 .loc 1 457 6 discriminator 1 896 0052 002B cmp r3, #0 897 0054 01D0 beq .L43 458:Core/Src/main.c **** { 459:Core/Src/main.c **** Error_Handler(); 898 .loc 1 459 5 899 0056 FFF7FEFF bl Error_Handler 900 .L43: 460:Core/Src/main.c **** } 461:Core/Src/main.c **** sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 901 .loc 1 461 37 902 005a 0023 movs r3, #0 903 005c FB61 str r3, [r7, #28] 462:Core/Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 904 .loc 1 462 33 ARM GAS /tmp/ccSWt3lr.s page 25 905 005e 0023 movs r3, #0 906 0060 7B62 str r3, [r7, #36] 463:Core/Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) 907 .loc 1 463 7 908 0062 07F11C03 add r3, r7, #28 909 0066 1946 mov r1, r3 910 0068 1648 ldr r0, .L47 911 006a FFF7FEFF bl HAL_TIMEx_MasterConfigSynchronization 912 006e 0346 mov r3, r0 913 .loc 1 463 6 discriminator 1 914 0070 002B cmp r3, #0 915 0072 01D0 beq .L44 464:Core/Src/main.c **** { 465:Core/Src/main.c **** Error_Handler(); 916 .loc 1 465 5 917 0074 FFF7FEFF bl Error_Handler 918 .L44: 466:Core/Src/main.c **** } 467:Core/Src/main.c **** sConfigOC.OCMode = TIM_OCMODE_PWM1; 919 .loc 1 467 20 920 0078 6023 movs r3, #96 921 007a 3B60 str r3, [r7] 468:Core/Src/main.c **** sConfigOC.Pulse = 0; 922 .loc 1 468 19 923 007c 0023 movs r3, #0 924 007e 7B60 str r3, [r7, #4] 469:Core/Src/main.c **** sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 925 .loc 1 469 24 926 0080 0023 movs r3, #0 927 0082 BB60 str r3, [r7, #8] 470:Core/Src/main.c **** sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 928 .loc 1 470 24 929 0084 0023 movs r3, #0 930 0086 3B61 str r3, [r7, #16] 471:Core/Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) 931 .loc 1 471 7 932 0088 3B46 mov r3, r7 933 008a 0822 movs r2, #8 934 008c 1946 mov r1, r3 935 008e 0D48 ldr r0, .L47 936 0090 FFF7FEFF bl HAL_TIM_PWM_ConfigChannel 937 0094 0346 mov r3, r0 938 .loc 1 471 6 discriminator 1 939 0096 002B cmp r3, #0 940 0098 01D0 beq .L45 472:Core/Src/main.c **** { 473:Core/Src/main.c **** Error_Handler(); 941 .loc 1 473 5 942 009a FFF7FEFF bl Error_Handler 943 .L45: 474:Core/Src/main.c **** } 475:Core/Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) 944 .loc 1 475 7 945 009e 3B46 mov r3, r7 946 00a0 0C22 movs r2, #12 947 00a2 1946 mov r1, r3 948 00a4 0748 ldr r0, .L47 ARM GAS /tmp/ccSWt3lr.s page 26 949 00a6 FFF7FEFF bl HAL_TIM_PWM_ConfigChannel 950 00aa 0346 mov r3, r0 951 .loc 1 475 6 discriminator 1 952 00ac 002B cmp r3, #0 953 00ae 01D0 beq .L46 476:Core/Src/main.c **** { 477:Core/Src/main.c **** Error_Handler(); 954 .loc 1 477 5 955 00b0 FFF7FEFF bl Error_Handler 956 .L46: 478:Core/Src/main.c **** } 479:Core/Src/main.c **** /* USER CODE BEGIN TIM3_Init 2 */ 480:Core/Src/main.c **** 481:Core/Src/main.c **** /* USER CODE END TIM3_Init 2 */ 482:Core/Src/main.c **** HAL_TIM_MspPostInit(&htim3); 957 .loc 1 482 3 958 00b4 0348 ldr r0, .L47 959 00b6 FFF7FEFF bl HAL_TIM_MspPostInit 483:Core/Src/main.c **** 484:Core/Src/main.c **** } 960 .loc 1 484 1 961 00ba 00BF nop 962 00bc 2837 adds r7, r7, #40 963 .cfi_def_cfa_offset 8 964 00be BD46 mov sp, r7 965 .cfi_def_cfa_register 13 966 @ sp needed 967 00c0 80BD pop {r7, pc} 968 .L48: 969 00c2 00BF .align 2 970 .L47: 971 00c4 00000000 .word htim3 972 00c8 00040040 .word 1073742848 973 .cfi_endproc 974 .LFE137: 976 .section .text.MX_TIM4_Init,"ax",%progbits 977 .align 1 978 .syntax unified 979 .thumb 980 .thumb_func 982 MX_TIM4_Init: 983 .LFB138: 485:Core/Src/main.c **** 486:Core/Src/main.c **** /** 487:Core/Src/main.c **** * @brief TIM4 Initialization Function 488:Core/Src/main.c **** * @param None 489:Core/Src/main.c **** * @retval None 490:Core/Src/main.c **** */ 491:Core/Src/main.c **** static void MX_TIM4_Init(void) 492:Core/Src/main.c **** { 984 .loc 1 492 1 985 .cfi_startproc 986 @ args = 0, pretend = 0, frame = 40 987 @ frame_needed = 1, uses_anonymous_args = 0 988 0000 80B5 push {r7, lr} 989 .cfi_def_cfa_offset 8 990 .cfi_offset 7, -8 ARM GAS /tmp/ccSWt3lr.s page 27 991 .cfi_offset 14, -4 992 0002 8AB0 sub sp, sp, #40 993 .cfi_def_cfa_offset 48 994 0004 00AF add r7, sp, #0 995 .cfi_def_cfa_register 7 493:Core/Src/main.c **** 494:Core/Src/main.c **** /* USER CODE BEGIN TIM4_Init 0 */ 495:Core/Src/main.c **** 496:Core/Src/main.c **** /* USER CODE END TIM4_Init 0 */ 497:Core/Src/main.c **** 498:Core/Src/main.c **** TIM_MasterConfigTypeDef sMasterConfig = {0}; 996 .loc 1 498 27 997 0006 07F11C03 add r3, r7, #28 998 000a 0022 movs r2, #0 999 000c 1A60 str r2, [r3] 1000 000e 5A60 str r2, [r3, #4] 1001 0010 9A60 str r2, [r3, #8] 499:Core/Src/main.c **** TIM_OC_InitTypeDef sConfigOC = {0}; 1002 .loc 1 499 22 1003 0012 3B46 mov r3, r7 1004 0014 0022 movs r2, #0 1005 0016 1A60 str r2, [r3] 1006 0018 5A60 str r2, [r3, #4] 1007 001a 9A60 str r2, [r3, #8] 1008 001c DA60 str r2, [r3, #12] 1009 001e 1A61 str r2, [r3, #16] 1010 0020 5A61 str r2, [r3, #20] 1011 0022 9A61 str r2, [r3, #24] 500:Core/Src/main.c **** 501:Core/Src/main.c **** /* USER CODE BEGIN TIM4_Init 1 */ 502:Core/Src/main.c **** 503:Core/Src/main.c **** /* USER CODE END TIM4_Init 1 */ 504:Core/Src/main.c **** htim4.Instance = TIM4; 1012 .loc 1 504 18 1013 0024 2C4B ldr r3, .L55 1014 0026 2D4A ldr r2, .L55+4 1015 0028 1A60 str r2, [r3] 505:Core/Src/main.c **** htim4.Init.Prescaler = 624; 1016 .loc 1 505 24 1017 002a 2B4B ldr r3, .L55 1018 002c 4FF41C72 mov r2, #624 1019 0030 5A60 str r2, [r3, #4] 506:Core/Src/main.c **** htim4.Init.CounterMode = TIM_COUNTERMODE_UP; 1020 .loc 1 506 26 1021 0032 294B ldr r3, .L55 1022 0034 0022 movs r2, #0 1023 0036 9A60 str r2, [r3, #8] 507:Core/Src/main.c **** htim4.Init.Period = 255; 1024 .loc 1 507 21 1025 0038 274B ldr r3, .L55 1026 003a FF22 movs r2, #255 1027 003c DA60 str r2, [r3, #12] 508:Core/Src/main.c **** htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 1028 .loc 1 508 28 1029 003e 264B ldr r3, .L55 1030 0040 0022 movs r2, #0 1031 0042 1A61 str r2, [r3, #16] ARM GAS /tmp/ccSWt3lr.s page 28 509:Core/Src/main.c **** htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 1032 .loc 1 509 32 1033 0044 244B ldr r3, .L55 1034 0046 0022 movs r2, #0 1035 0048 9A61 str r2, [r3, #24] 510:Core/Src/main.c **** if (HAL_TIM_PWM_Init(&htim4) != HAL_OK) 1036 .loc 1 510 7 1037 004a 2348 ldr r0, .L55 1038 004c FFF7FEFF bl HAL_TIM_PWM_Init 1039 0050 0346 mov r3, r0 1040 .loc 1 510 6 discriminator 1 1041 0052 002B cmp r3, #0 1042 0054 01D0 beq .L50 511:Core/Src/main.c **** { 512:Core/Src/main.c **** Error_Handler(); 1043 .loc 1 512 5 1044 0056 FFF7FEFF bl Error_Handler 1045 .L50: 513:Core/Src/main.c **** } 514:Core/Src/main.c **** sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 1046 .loc 1 514 37 1047 005a 0023 movs r3, #0 1048 005c FB61 str r3, [r7, #28] 515:Core/Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 1049 .loc 1 515 33 1050 005e 0023 movs r3, #0 1051 0060 7B62 str r3, [r7, #36] 516:Core/Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK) 1052 .loc 1 516 7 1053 0062 07F11C03 add r3, r7, #28 1054 0066 1946 mov r1, r3 1055 0068 1B48 ldr r0, .L55 1056 006a FFF7FEFF bl HAL_TIMEx_MasterConfigSynchronization 1057 006e 0346 mov r3, r0 1058 .loc 1 516 6 discriminator 1 1059 0070 002B cmp r3, #0 1060 0072 01D0 beq .L51 517:Core/Src/main.c **** { 518:Core/Src/main.c **** Error_Handler(); 1061 .loc 1 518 5 1062 0074 FFF7FEFF bl Error_Handler 1063 .L51: 519:Core/Src/main.c **** } 520:Core/Src/main.c **** sConfigOC.OCMode = TIM_OCMODE_PWM1; 1064 .loc 1 520 20 1065 0078 6023 movs r3, #96 1066 007a 3B60 str r3, [r7] 521:Core/Src/main.c **** sConfigOC.Pulse = 0; 1067 .loc 1 521 19 1068 007c 0023 movs r3, #0 1069 007e 7B60 str r3, [r7, #4] 522:Core/Src/main.c **** sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 1070 .loc 1 522 24 1071 0080 0023 movs r3, #0 1072 0082 BB60 str r3, [r7, #8] 523:Core/Src/main.c **** sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 1073 .loc 1 523 24 ARM GAS /tmp/ccSWt3lr.s page 29 1074 0084 0023 movs r3, #0 1075 0086 3B61 str r3, [r7, #16] 524:Core/Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) 1076 .loc 1 524 7 1077 0088 3B46 mov r3, r7 1078 008a 0022 movs r2, #0 1079 008c 1946 mov r1, r3 1080 008e 1248 ldr r0, .L55 1081 0090 FFF7FEFF bl HAL_TIM_PWM_ConfigChannel 1082 0094 0346 mov r3, r0 1083 .loc 1 524 6 discriminator 1 1084 0096 002B cmp r3, #0 1085 0098 01D0 beq .L52 525:Core/Src/main.c **** { 526:Core/Src/main.c **** Error_Handler(); 1086 .loc 1 526 5 1087 009a FFF7FEFF bl Error_Handler 1088 .L52: 527:Core/Src/main.c **** } 528:Core/Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) 1089 .loc 1 528 7 1090 009e 3B46 mov r3, r7 1091 00a0 0422 movs r2, #4 1092 00a2 1946 mov r1, r3 1093 00a4 0C48 ldr r0, .L55 1094 00a6 FFF7FEFF bl HAL_TIM_PWM_ConfigChannel 1095 00aa 0346 mov r3, r0 1096 .loc 1 528 6 discriminator 1 1097 00ac 002B cmp r3, #0 1098 00ae 01D0 beq .L53 529:Core/Src/main.c **** { 530:Core/Src/main.c **** Error_Handler(); 1099 .loc 1 530 5 1100 00b0 FFF7FEFF bl Error_Handler 1101 .L53: 531:Core/Src/main.c **** } 532:Core/Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) 1102 .loc 1 532 7 1103 00b4 3B46 mov r3, r7 1104 00b6 0822 movs r2, #8 1105 00b8 1946 mov r1, r3 1106 00ba 0748 ldr r0, .L55 1107 00bc FFF7FEFF bl HAL_TIM_PWM_ConfigChannel 1108 00c0 0346 mov r3, r0 1109 .loc 1 532 6 discriminator 1 1110 00c2 002B cmp r3, #0 1111 00c4 01D0 beq .L54 533:Core/Src/main.c **** { 534:Core/Src/main.c **** Error_Handler(); 1112 .loc 1 534 5 1113 00c6 FFF7FEFF bl Error_Handler 1114 .L54: 535:Core/Src/main.c **** } 536:Core/Src/main.c **** /* USER CODE BEGIN TIM4_Init 2 */ 537:Core/Src/main.c **** 538:Core/Src/main.c **** /* USER CODE END TIM4_Init 2 */ 539:Core/Src/main.c **** HAL_TIM_MspPostInit(&htim4); ARM GAS /tmp/ccSWt3lr.s page 30 1115 .loc 1 539 3 1116 00ca 0348 ldr r0, .L55 1117 00cc FFF7FEFF bl HAL_TIM_MspPostInit 540:Core/Src/main.c **** 541:Core/Src/main.c **** } 1118 .loc 1 541 1 1119 00d0 00BF nop 1120 00d2 2837 adds r7, r7, #40 1121 .cfi_def_cfa_offset 8 1122 00d4 BD46 mov sp, r7 1123 .cfi_def_cfa_register 13 1124 @ sp needed 1125 00d6 80BD pop {r7, pc} 1126 .L56: 1127 .align 2 1128 .L55: 1129 00d8 00000000 .word htim4 1130 00dc 00080040 .word 1073743872 1131 .cfi_endproc 1132 .LFE138: 1134 .section .text.MX_TIM15_Init,"ax",%progbits 1135 .align 1 1136 .syntax unified 1137 .thumb 1138 .thumb_func 1140 MX_TIM15_Init: 1141 .LFB139: 542:Core/Src/main.c **** 543:Core/Src/main.c **** /** 544:Core/Src/main.c **** * @brief TIM15 Initialization Function 545:Core/Src/main.c **** * @param None 546:Core/Src/main.c **** * @retval None 547:Core/Src/main.c **** */ 548:Core/Src/main.c **** static void MX_TIM15_Init(void) 549:Core/Src/main.c **** { 1142 .loc 1 549 1 1143 .cfi_startproc 1144 @ args = 0, pretend = 0, frame = 88 1145 @ frame_needed = 1, uses_anonymous_args = 0 1146 0000 80B5 push {r7, lr} 1147 .cfi_def_cfa_offset 8 1148 .cfi_offset 7, -8 1149 .cfi_offset 14, -4 1150 0002 96B0 sub sp, sp, #88 1151 .cfi_def_cfa_offset 96 1152 0004 00AF add r7, sp, #0 1153 .cfi_def_cfa_register 7 550:Core/Src/main.c **** 551:Core/Src/main.c **** /* USER CODE BEGIN TIM15_Init 0 */ 552:Core/Src/main.c **** 553:Core/Src/main.c **** /* USER CODE END TIM15_Init 0 */ 554:Core/Src/main.c **** 555:Core/Src/main.c **** TIM_MasterConfigTypeDef sMasterConfig = {0}; 1154 .loc 1 555 27 1155 0006 07F14C03 add r3, r7, #76 1156 000a 0022 movs r2, #0 1157 000c 1A60 str r2, [r3] ARM GAS /tmp/ccSWt3lr.s page 31 1158 000e 5A60 str r2, [r3, #4] 1159 0010 9A60 str r2, [r3, #8] 556:Core/Src/main.c **** TIM_OC_InitTypeDef sConfigOC = {0}; 1160 .loc 1 556 22 1161 0012 07F13003 add r3, r7, #48 1162 0016 0022 movs r2, #0 1163 0018 1A60 str r2, [r3] 1164 001a 5A60 str r2, [r3, #4] 1165 001c 9A60 str r2, [r3, #8] 1166 001e DA60 str r2, [r3, #12] 1167 0020 1A61 str r2, [r3, #16] 1168 0022 5A61 str r2, [r3, #20] 1169 0024 9A61 str r2, [r3, #24] 557:Core/Src/main.c **** TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0}; 1170 .loc 1 557 34 1171 0026 3B1D adds r3, r7, #4 1172 0028 2C22 movs r2, #44 1173 002a 0021 movs r1, #0 1174 002c 1846 mov r0, r3 1175 002e FFF7FEFF bl memset 558:Core/Src/main.c **** 559:Core/Src/main.c **** /* USER CODE BEGIN TIM15_Init 1 */ 560:Core/Src/main.c **** 561:Core/Src/main.c **** /* USER CODE END TIM15_Init 1 */ 562:Core/Src/main.c **** htim15.Instance = TIM15; 1176 .loc 1 562 19 1177 0032 3A4B ldr r3, .L63 1178 0034 3A4A ldr r2, .L63+4 1179 0036 1A60 str r2, [r3] 563:Core/Src/main.c **** htim15.Init.Prescaler = 0; 1180 .loc 1 563 25 1181 0038 384B ldr r3, .L63 1182 003a 0022 movs r2, #0 1183 003c 5A60 str r2, [r3, #4] 564:Core/Src/main.c **** htim15.Init.CounterMode = TIM_COUNTERMODE_UP; 1184 .loc 1 564 27 1185 003e 374B ldr r3, .L63 1186 0040 0022 movs r2, #0 1187 0042 9A60 str r2, [r3, #8] 565:Core/Src/main.c **** htim15.Init.Period = 65535; 1188 .loc 1 565 22 1189 0044 354B ldr r3, .L63 1190 0046 4FF6FF72 movw r2, #65535 1191 004a DA60 str r2, [r3, #12] 566:Core/Src/main.c **** htim15.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 1192 .loc 1 566 29 1193 004c 334B ldr r3, .L63 1194 004e 0022 movs r2, #0 1195 0050 1A61 str r2, [r3, #16] 567:Core/Src/main.c **** htim15.Init.RepetitionCounter = 0; 1196 .loc 1 567 33 1197 0052 324B ldr r3, .L63 1198 0054 0022 movs r2, #0 1199 0056 5A61 str r2, [r3, #20] 568:Core/Src/main.c **** htim15.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 1200 .loc 1 568 33 1201 0058 304B ldr r3, .L63 ARM GAS /tmp/ccSWt3lr.s page 32 1202 005a 0022 movs r2, #0 1203 005c 9A61 str r2, [r3, #24] 569:Core/Src/main.c **** if (HAL_TIM_PWM_Init(&htim15) != HAL_OK) 1204 .loc 1 569 7 1205 005e 2F48 ldr r0, .L63 1206 0060 FFF7FEFF bl HAL_TIM_PWM_Init 1207 0064 0346 mov r3, r0 1208 .loc 1 569 6 discriminator 1 1209 0066 002B cmp r3, #0 1210 0068 01D0 beq .L58 570:Core/Src/main.c **** { 571:Core/Src/main.c **** Error_Handler(); 1211 .loc 1 571 5 1212 006a FFF7FEFF bl Error_Handler 1213 .L58: 572:Core/Src/main.c **** } 573:Core/Src/main.c **** sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 1214 .loc 1 573 37 1215 006e 0023 movs r3, #0 1216 0070 FB64 str r3, [r7, #76] 574:Core/Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 1217 .loc 1 574 33 1218 0072 0023 movs r3, #0 1219 0074 7B65 str r3, [r7, #84] 575:Core/Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim15, &sMasterConfig) != HAL_OK) 1220 .loc 1 575 7 1221 0076 07F14C03 add r3, r7, #76 1222 007a 1946 mov r1, r3 1223 007c 2748 ldr r0, .L63 1224 007e FFF7FEFF bl HAL_TIMEx_MasterConfigSynchronization 1225 0082 0346 mov r3, r0 1226 .loc 1 575 6 discriminator 1 1227 0084 002B cmp r3, #0 1228 0086 01D0 beq .L59 576:Core/Src/main.c **** { 577:Core/Src/main.c **** Error_Handler(); 1229 .loc 1 577 5 1230 0088 FFF7FEFF bl Error_Handler 1231 .L59: 578:Core/Src/main.c **** } 579:Core/Src/main.c **** sConfigOC.OCMode = TIM_OCMODE_PWM1; 1232 .loc 1 579 20 1233 008c 6023 movs r3, #96 1234 008e 3B63 str r3, [r7, #48] 580:Core/Src/main.c **** sConfigOC.Pulse = 0; 1235 .loc 1 580 19 1236 0090 0023 movs r3, #0 1237 0092 7B63 str r3, [r7, #52] 581:Core/Src/main.c **** sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 1238 .loc 1 581 24 1239 0094 0023 movs r3, #0 1240 0096 BB63 str r3, [r7, #56] 582:Core/Src/main.c **** sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH; 1241 .loc 1 582 25 1242 0098 0023 movs r3, #0 1243 009a FB63 str r3, [r7, #60] 583:Core/Src/main.c **** sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; ARM GAS /tmp/ccSWt3lr.s page 33 1244 .loc 1 583 24 1245 009c 0023 movs r3, #0 1246 009e 3B64 str r3, [r7, #64] 584:Core/Src/main.c **** sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET; 1247 .loc 1 584 25 1248 00a0 0023 movs r3, #0 1249 00a2 7B64 str r3, [r7, #68] 585:Core/Src/main.c **** sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET; 1250 .loc 1 585 26 1251 00a4 0023 movs r3, #0 1252 00a6 BB64 str r3, [r7, #72] 586:Core/Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim15, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) 1253 .loc 1 586 7 1254 00a8 07F13003 add r3, r7, #48 1255 00ac 0022 movs r2, #0 1256 00ae 1946 mov r1, r3 1257 00b0 1A48 ldr r0, .L63 1258 00b2 FFF7FEFF bl HAL_TIM_PWM_ConfigChannel 1259 00b6 0346 mov r3, r0 1260 .loc 1 586 6 discriminator 1 1261 00b8 002B cmp r3, #0 1262 00ba 01D0 beq .L60 587:Core/Src/main.c **** { 588:Core/Src/main.c **** Error_Handler(); 1263 .loc 1 588 5 1264 00bc FFF7FEFF bl Error_Handler 1265 .L60: 589:Core/Src/main.c **** } 590:Core/Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim15, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) 1266 .loc 1 590 7 1267 00c0 07F13003 add r3, r7, #48 1268 00c4 0422 movs r2, #4 1269 00c6 1946 mov r1, r3 1270 00c8 1448 ldr r0, .L63 1271 00ca FFF7FEFF bl HAL_TIM_PWM_ConfigChannel 1272 00ce 0346 mov r3, r0 1273 .loc 1 590 6 discriminator 1 1274 00d0 002B cmp r3, #0 1275 00d2 01D0 beq .L61 591:Core/Src/main.c **** { 592:Core/Src/main.c **** Error_Handler(); 1276 .loc 1 592 5 1277 00d4 FFF7FEFF bl Error_Handler 1278 .L61: 593:Core/Src/main.c **** } 594:Core/Src/main.c **** sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE; 1279 .loc 1 594 40 1280 00d8 0023 movs r3, #0 1281 00da 7B60 str r3, [r7, #4] 595:Core/Src/main.c **** sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE; 1282 .loc 1 595 41 1283 00dc 0023 movs r3, #0 1284 00de BB60 str r3, [r7, #8] 596:Core/Src/main.c **** sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF; 1285 .loc 1 596 34 1286 00e0 0023 movs r3, #0 1287 00e2 FB60 str r3, [r7, #12] ARM GAS /tmp/ccSWt3lr.s page 34 597:Core/Src/main.c **** sBreakDeadTimeConfig.DeadTime = 0; 1288 .loc 1 597 33 1289 00e4 0023 movs r3, #0 1290 00e6 3B61 str r3, [r7, #16] 598:Core/Src/main.c **** sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE; 1291 .loc 1 598 35 1292 00e8 0023 movs r3, #0 1293 00ea 7B61 str r3, [r7, #20] 599:Core/Src/main.c **** sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH; 1294 .loc 1 599 38 1295 00ec 4FF40053 mov r3, #8192 1296 00f0 BB61 str r3, [r7, #24] 600:Core/Src/main.c **** sBreakDeadTimeConfig.BreakFilter = 0; 1297 .loc 1 600 36 1298 00f2 0023 movs r3, #0 1299 00f4 FB61 str r3, [r7, #28] 601:Core/Src/main.c **** sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE; 1300 .loc 1 601 40 1301 00f6 0023 movs r3, #0 1302 00f8 FB62 str r3, [r7, #44] 602:Core/Src/main.c **** if (HAL_TIMEx_ConfigBreakDeadTime(&htim15, &sBreakDeadTimeConfig) != HAL_OK) 1303 .loc 1 602 7 1304 00fa 3B1D adds r3, r7, #4 1305 00fc 1946 mov r1, r3 1306 00fe 0748 ldr r0, .L63 1307 0100 FFF7FEFF bl HAL_TIMEx_ConfigBreakDeadTime 1308 0104 0346 mov r3, r0 1309 .loc 1 602 6 discriminator 1 1310 0106 002B cmp r3, #0 1311 0108 01D0 beq .L62 603:Core/Src/main.c **** { 604:Core/Src/main.c **** Error_Handler(); 1312 .loc 1 604 5 1313 010a FFF7FEFF bl Error_Handler 1314 .L62: 605:Core/Src/main.c **** } 606:Core/Src/main.c **** /* USER CODE BEGIN TIM15_Init 2 */ 607:Core/Src/main.c **** 608:Core/Src/main.c **** /* USER CODE END TIM15_Init 2 */ 609:Core/Src/main.c **** HAL_TIM_MspPostInit(&htim15); 1315 .loc 1 609 3 1316 010e 0348 ldr r0, .L63 1317 0110 FFF7FEFF bl HAL_TIM_MspPostInit 610:Core/Src/main.c **** 611:Core/Src/main.c **** } 1318 .loc 1 611 1 1319 0114 00BF nop 1320 0116 5837 adds r7, r7, #88 1321 .cfi_def_cfa_offset 8 1322 0118 BD46 mov sp, r7 1323 .cfi_def_cfa_register 13 1324 @ sp needed 1325 011a 80BD pop {r7, pc} 1326 .L64: 1327 .align 2 1328 .L63: 1329 011c 00000000 .word htim15 ARM GAS /tmp/ccSWt3lr.s page 35 1330 0120 00400140 .word 1073823744 1331 .cfi_endproc 1332 .LFE139: 1334 .section .text.MX_GPIO_Init,"ax",%progbits 1335 .align 1 1336 .syntax unified 1337 .thumb 1338 .thumb_func 1340 MX_GPIO_Init: 1341 .LFB140: 612:Core/Src/main.c **** 613:Core/Src/main.c **** /** 614:Core/Src/main.c **** * @brief GPIO Initialization Function 615:Core/Src/main.c **** * @param None 616:Core/Src/main.c **** * @retval None 617:Core/Src/main.c **** */ 618:Core/Src/main.c **** static void MX_GPIO_Init(void) 619:Core/Src/main.c **** { 1342 .loc 1 619 1 1343 .cfi_startproc 1344 @ args = 0, pretend = 0, frame = 40 1345 @ frame_needed = 1, uses_anonymous_args = 0 1346 0000 80B5 push {r7, lr} 1347 .cfi_def_cfa_offset 8 1348 .cfi_offset 7, -8 1349 .cfi_offset 14, -4 1350 0002 8AB0 sub sp, sp, #40 1351 .cfi_def_cfa_offset 48 1352 0004 00AF add r7, sp, #0 1353 .cfi_def_cfa_register 7 620:Core/Src/main.c **** GPIO_InitTypeDef GPIO_InitStruct = {0}; 1354 .loc 1 620 20 1355 0006 07F11403 add r3, r7, #20 1356 000a 0022 movs r2, #0 1357 000c 1A60 str r2, [r3] 1358 000e 5A60 str r2, [r3, #4] 1359 0010 9A60 str r2, [r3, #8] 1360 0012 DA60 str r2, [r3, #12] 1361 0014 1A61 str r2, [r3, #16] 1362 .LBB4: 621:Core/Src/main.c **** /* USER CODE BEGIN MX_GPIO_Init_1 */ 622:Core/Src/main.c **** /* USER CODE END MX_GPIO_Init_1 */ 623:Core/Src/main.c **** 624:Core/Src/main.c **** /* GPIO Ports Clock Enable */ 625:Core/Src/main.c **** __HAL_RCC_GPIOC_CLK_ENABLE(); 1363 .loc 1 625 3 1364 0016 424B ldr r3, .L66 1365 0018 5B69 ldr r3, [r3, #20] 1366 001a 414A ldr r2, .L66 1367 001c 43F40023 orr r3, r3, #524288 1368 0020 5361 str r3, [r2, #20] 1369 0022 3F4B ldr r3, .L66 1370 0024 5B69 ldr r3, [r3, #20] 1371 0026 03F40023 and r3, r3, #524288 1372 002a 3B61 str r3, [r7, #16] 1373 002c 3B69 ldr r3, [r7, #16] 1374 .LBE4: ARM GAS /tmp/ccSWt3lr.s page 36 1375 .LBB5: 626:Core/Src/main.c **** __HAL_RCC_GPIOF_CLK_ENABLE(); 1376 .loc 1 626 3 1377 002e 3C4B ldr r3, .L66 1378 0030 5B69 ldr r3, [r3, #20] 1379 0032 3B4A ldr r2, .L66 1380 0034 43F48003 orr r3, r3, #4194304 1381 0038 5361 str r3, [r2, #20] 1382 003a 394B ldr r3, .L66 1383 003c 5B69 ldr r3, [r3, #20] 1384 003e 03F48003 and r3, r3, #4194304 1385 0042 FB60 str r3, [r7, #12] 1386 0044 FB68 ldr r3, [r7, #12] 1387 .LBE5: 1388 .LBB6: 627:Core/Src/main.c **** __HAL_RCC_GPIOA_CLK_ENABLE(); 1389 .loc 1 627 3 1390 0046 364B ldr r3, .L66 1391 0048 5B69 ldr r3, [r3, #20] 1392 004a 354A ldr r2, .L66 1393 004c 43F40033 orr r3, r3, #131072 1394 0050 5361 str r3, [r2, #20] 1395 0052 334B ldr r3, .L66 1396 0054 5B69 ldr r3, [r3, #20] 1397 0056 03F40033 and r3, r3, #131072 1398 005a BB60 str r3, [r7, #8] 1399 005c BB68 ldr r3, [r7, #8] 1400 .LBE6: 1401 .LBB7: 628:Core/Src/main.c **** __HAL_RCC_GPIOB_CLK_ENABLE(); 1402 .loc 1 628 3 1403 005e 304B ldr r3, .L66 1404 0060 5B69 ldr r3, [r3, #20] 1405 0062 2F4A ldr r2, .L66 1406 0064 43F48023 orr r3, r3, #262144 1407 0068 5361 str r3, [r2, #20] 1408 006a 2D4B ldr r3, .L66 1409 006c 5B69 ldr r3, [r3, #20] 1410 006e 03F48023 and r3, r3, #262144 1411 0072 7B60 str r3, [r7, #4] 1412 0074 7B68 ldr r3, [r7, #4] 1413 .LBE7: 629:Core/Src/main.c **** 630:Core/Src/main.c **** /*Configure GPIO pin Output Level */ 631:Core/Src/main.c **** HAL_GPIO_WritePin(GPIOA, CSB_Pin|EEPROM___WC__Pin, GPIO_PIN_RESET); 1414 .loc 1 631 3 1415 0076 0022 movs r2, #0 1416 0078 4FF48871 mov r1, #272 1417 007c 4FF09040 mov r0, #1207959552 1418 0080 FFF7FEFF bl HAL_GPIO_WritePin 632:Core/Src/main.c **** 633:Core/Src/main.c **** /*Configure GPIO pin Output Level */ 634:Core/Src/main.c **** HAL_GPIO_WritePin(GPIOB, RELAY_ENABLE_Pin|PRECHARGE_ENABLE_Pin, GPIO_PIN_RESET); 1419 .loc 1 634 3 1420 0084 0022 movs r2, #0 1421 0086 3021 movs r1, #48 1422 0088 2648 ldr r0, .L66+4 ARM GAS /tmp/ccSWt3lr.s page 37 1423 008a FFF7FEFF bl HAL_GPIO_WritePin 635:Core/Src/main.c **** 636:Core/Src/main.c **** /*Configure GPIO pins : PC13 PC14 PC15 */ 637:Core/Src/main.c **** GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15; 1424 .loc 1 637 23 1425 008e 4FF46043 mov r3, #57344 1426 0092 7B61 str r3, [r7, #20] 638:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 1427 .loc 1 638 24 1428 0094 0323 movs r3, #3 1429 0096 BB61 str r3, [r7, #24] 639:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 1430 .loc 1 639 24 1431 0098 0023 movs r3, #0 1432 009a FB61 str r3, [r7, #28] 640:Core/Src/main.c **** HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 1433 .loc 1 640 3 1434 009c 07F11403 add r3, r7, #20 1435 00a0 1946 mov r1, r3 1436 00a2 2148 ldr r0, .L66+8 1437 00a4 FFF7FEFF bl HAL_GPIO_Init 641:Core/Src/main.c **** 642:Core/Src/main.c **** /*Configure GPIO pins : PA0 PA1 PA2 PA3 */ 643:Core/Src/main.c **** GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3; 1438 .loc 1 643 23 1439 00a8 0F23 movs r3, #15 1440 00aa 7B61 str r3, [r7, #20] 644:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 1441 .loc 1 644 24 1442 00ac 0323 movs r3, #3 1443 00ae BB61 str r3, [r7, #24] 645:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 1444 .loc 1 645 24 1445 00b0 0023 movs r3, #0 1446 00b2 FB61 str r3, [r7, #28] 646:Core/Src/main.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 1447 .loc 1 646 3 1448 00b4 07F11403 add r3, r7, #20 1449 00b8 1946 mov r1, r3 1450 00ba 4FF09040 mov r0, #1207959552 1451 00be FFF7FEFF bl HAL_GPIO_Init 647:Core/Src/main.c **** 648:Core/Src/main.c **** /*Configure GPIO pins : CSB_Pin EEPROM___WC__Pin */ 649:Core/Src/main.c **** GPIO_InitStruct.Pin = CSB_Pin|EEPROM___WC__Pin; 1452 .loc 1 649 23 1453 00c2 4FF48873 mov r3, #272 1454 00c6 7B61 str r3, [r7, #20] 650:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 1455 .loc 1 650 24 1456 00c8 0123 movs r3, #1 1457 00ca BB61 str r3, [r7, #24] 651:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 1458 .loc 1 651 24 1459 00cc 0023 movs r3, #0 1460 00ce FB61 str r3, [r7, #28] 652:Core/Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 1461 .loc 1 652 25 ARM GAS /tmp/ccSWt3lr.s page 38 1462 00d0 0323 movs r3, #3 1463 00d2 3B62 str r3, [r7, #32] 653:Core/Src/main.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 1464 .loc 1 653 3 1465 00d4 07F11403 add r3, r7, #20 1466 00d8 1946 mov r1, r3 1467 00da 4FF09040 mov r0, #1207959552 1468 00de FFF7FEFF bl HAL_GPIO_Init 654:Core/Src/main.c **** 655:Core/Src/main.c **** /*Configure GPIO pins : PB2 PB12 PB13 */ 656:Core/Src/main.c **** GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_12|GPIO_PIN_13; 1469 .loc 1 656 23 1470 00e2 43F20403 movw r3, #12292 1471 00e6 7B61 str r3, [r7, #20] 657:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 1472 .loc 1 657 24 1473 00e8 0323 movs r3, #3 1474 00ea BB61 str r3, [r7, #24] 658:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 1475 .loc 1 658 24 1476 00ec 0023 movs r3, #0 1477 00ee FB61 str r3, [r7, #28] 659:Core/Src/main.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 1478 .loc 1 659 3 1479 00f0 07F11403 add r3, r7, #20 1480 00f4 1946 mov r1, r3 1481 00f6 0B48 ldr r0, .L66+4 1482 00f8 FFF7FEFF bl HAL_GPIO_Init 660:Core/Src/main.c **** 661:Core/Src/main.c **** /*Configure GPIO pins : RELAY_ENABLE_Pin PRECHARGE_ENABLE_Pin */ 662:Core/Src/main.c **** GPIO_InitStruct.Pin = RELAY_ENABLE_Pin|PRECHARGE_ENABLE_Pin; 1483 .loc 1 662 23 1484 00fc 3023 movs r3, #48 1485 00fe 7B61 str r3, [r7, #20] 663:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 1486 .loc 1 663 24 1487 0100 0123 movs r3, #1 1488 0102 BB61 str r3, [r7, #24] 664:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 1489 .loc 1 664 24 1490 0104 0023 movs r3, #0 1491 0106 FB61 str r3, [r7, #28] 665:Core/Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 1492 .loc 1 665 25 1493 0108 0023 movs r3, #0 1494 010a 3B62 str r3, [r7, #32] 666:Core/Src/main.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 1495 .loc 1 666 3 1496 010c 07F11403 add r3, r7, #20 1497 0110 1946 mov r1, r3 1498 0112 0448 ldr r0, .L66+4 1499 0114 FFF7FEFF bl HAL_GPIO_Init 667:Core/Src/main.c **** 668:Core/Src/main.c **** /* USER CODE BEGIN MX_GPIO_Init_2 */ 669:Core/Src/main.c **** /* USER CODE END MX_GPIO_Init_2 */ 670:Core/Src/main.c **** } 1500 .loc 1 670 1 ARM GAS /tmp/ccSWt3lr.s page 39 1501 0118 00BF nop 1502 011a 2837 adds r7, r7, #40 1503 .cfi_def_cfa_offset 8 1504 011c BD46 mov sp, r7 1505 .cfi_def_cfa_register 13 1506 @ sp needed 1507 011e 80BD pop {r7, pc} 1508 .L67: 1509 .align 2 1510 .L66: 1511 0120 00100240 .word 1073876992 1512 0124 00040048 .word 1207960576 1513 0128 00080048 .word 1207961600 1514 .cfi_endproc 1515 .LFE140: 1517 .section .text.Error_Handler,"ax",%progbits 1518 .align 1 1519 .global Error_Handler 1520 .syntax unified 1521 .thumb 1522 .thumb_func 1524 Error_Handler: 1525 .LFB141: 671:Core/Src/main.c **** 672:Core/Src/main.c **** /* USER CODE BEGIN 4 */ 673:Core/Src/main.c **** 674:Core/Src/main.c **** /* USER CODE END 4 */ 675:Core/Src/main.c **** 676:Core/Src/main.c **** /** 677:Core/Src/main.c **** * @brief This function is executed in case of error occurrence. 678:Core/Src/main.c **** * @retval None 679:Core/Src/main.c **** */ 680:Core/Src/main.c **** void Error_Handler(void) 681:Core/Src/main.c **** { 1526 .loc 1 681 1 1527 .cfi_startproc 1528 @ args = 0, pretend = 0, frame = 0 1529 @ frame_needed = 1, uses_anonymous_args = 0 1530 @ link register save eliminated. 1531 0000 80B4 push {r7} 1532 .cfi_def_cfa_offset 4 1533 .cfi_offset 7, -4 1534 0002 00AF add r7, sp, #0 1535 .cfi_def_cfa_register 7 1536 .LBB8: 1537 .LBB9: 1538 .file 2 "Drivers/CMSIS/Include/cmsis_gcc.h" 1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//** 2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h 3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS compiler GCC header file 4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V5.0.4 5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 09. April 2018 6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/ 7:Drivers/CMSIS/Include/cmsis_gcc.h **** /* 8:Drivers/CMSIS/Include/cmsis_gcc.h **** * Copyright (c) 2009-2018 Arm Limited. All rights reserved. 9:Drivers/CMSIS/Include/cmsis_gcc.h **** * 10:Drivers/CMSIS/Include/cmsis_gcc.h **** * SPDX-License-Identifier: Apache-2.0 ARM GAS /tmp/ccSWt3lr.s page 40 11:Drivers/CMSIS/Include/cmsis_gcc.h **** * 12:Drivers/CMSIS/Include/cmsis_gcc.h **** * Licensed under the Apache License, Version 2.0 (the License); you may 13:Drivers/CMSIS/Include/cmsis_gcc.h **** * not use this file except in compliance with the License. 14:Drivers/CMSIS/Include/cmsis_gcc.h **** * You may obtain a copy of the License at 15:Drivers/CMSIS/Include/cmsis_gcc.h **** * 16:Drivers/CMSIS/Include/cmsis_gcc.h **** * www.apache.org/licenses/LICENSE-2.0 17:Drivers/CMSIS/Include/cmsis_gcc.h **** * 18:Drivers/CMSIS/Include/cmsis_gcc.h **** * Unless required by applicable law or agreed to in writing, software 19:Drivers/CMSIS/Include/cmsis_gcc.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20:Drivers/CMSIS/Include/cmsis_gcc.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21:Drivers/CMSIS/Include/cmsis_gcc.h **** * See the License for the specific language governing permissions and 22:Drivers/CMSIS/Include/cmsis_gcc.h **** * limitations under the License. 23:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 24:Drivers/CMSIS/Include/cmsis_gcc.h **** 25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H 26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H 27:Drivers/CMSIS/Include/cmsis_gcc.h **** 28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */ 29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion" 31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion" 32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter" 33:Drivers/CMSIS/Include/cmsis_gcc.h **** 34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */ 35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin 36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __has_builtin(x) (0) 37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 38:Drivers/CMSIS/Include/cmsis_gcc.h **** 39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */ 40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ASM 41:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ASM __asm 42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INLINE 44:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INLINE inline 45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_INLINE 47:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_INLINE static inline 48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_FORCEINLINE 50:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline 51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __NO_RETURN 53:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NO_RETURN __attribute__((__noreturn__)) 54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __USED 56:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USED __attribute__((used)) 57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __WEAK 59:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WEAK __attribute__((weak)) 60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED 62:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED __attribute__((packed, aligned(1))) 63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_STRUCT 65:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) 66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_UNION ARM GAS /tmp/ccSWt3lr.s page 41 68:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_UNION union __attribute__((packed, aligned(1))) 69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32 /* deprecated */ 71:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 72:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 73:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 74:Drivers/CMSIS/Include/cmsis_gcc.h **** struct __attribute__((packed)) T_UINT32 { uint32_t v; }; 75:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 76:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) 77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_WRITE 79:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 80:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 81:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 82:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; 83:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 84:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))- 85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_READ 87:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 88:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 89:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 90:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; 91:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 92:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(add 93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_WRITE 95:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 96:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 97:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 98:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; 99:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 100:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))- 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_READ 103:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 104:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 105:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 106:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; 107:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 108:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(add 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ALIGNED 111:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ALIGNED(x) __attribute__((aligned(x))) 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __RESTRICT 114:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __RESTRICT __restrict 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 116:Drivers/CMSIS/Include/cmsis_gcc.h **** 117:Drivers/CMSIS/Include/cmsis_gcc.h **** 118:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */ 119:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface 120:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions 121:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ 122:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 123:Drivers/CMSIS/Include/cmsis_gcc.h **** 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /** ARM GAS /tmp/ccSWt3lr.s page 42 125:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts 126:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR. 127:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. 128:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 129:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void) 130:Drivers/CMSIS/Include/cmsis_gcc.h **** { 131:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory"); 132:Drivers/CMSIS/Include/cmsis_gcc.h **** } 133:Drivers/CMSIS/Include/cmsis_gcc.h **** 134:Drivers/CMSIS/Include/cmsis_gcc.h **** 135:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 136:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts 137:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR. 138:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. 139:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 140:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void) 141:Drivers/CMSIS/Include/cmsis_gcc.h **** { 142:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory"); 1539 .loc 2 142 3 1540 .syntax unified 1541 @ 142 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 1542 0004 72B6 cpsid i 1543 @ 0 "" 2 143:Drivers/CMSIS/Include/cmsis_gcc.h **** } 1544 .loc 2 143 1 1545 .thumb 1546 .syntax unified 1547 0006 00BF nop 1548 .L69: 1549 .LBE9: 1550 .LBE8: 682:Core/Src/main.c **** /* USER CODE BEGIN Error_Handler_Debug */ 683:Core/Src/main.c **** /* User can add his own implementation to report the HAL error return state */ 684:Core/Src/main.c **** __disable_irq(); 685:Core/Src/main.c **** while (1) 1551 .loc 1 685 9 1552 0008 00BF nop 1553 000a FDE7 b .L69 1554 .cfi_endproc 1555 .LFE141: 1557 .text 1558 .Letext0: 1559 .file 3 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl 1560 .file 4 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl 1561 .file 5 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h" 1562 .file 6 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h" 1563 .file 7 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h" 1564 .file 8 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h" 1565 .file 9 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h" 1566 .file 10 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h" 1567 .file 11 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h" 1568 .file 12 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h" 1569 .file 13 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h" 1570 .file 14 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h" 1571 .file 15 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h" 1572 .file 16 "Core/Inc/main.h" 1573 .file 17 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h" ARM GAS /tmp/ccSWt3lr.s page 43 1574 .file 18 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h" 1575 .file 19 "Core/Inc/state_machine.h" 1576 .file 20 "Core/Inc/AMS_HighLevel.h" 1577 .file 21 "Core/Inc/eeprom.h" 1578 .file 22 "Core/Inc/status_LED.h" 1579 .file 23 "Core/Inc/soc_estimation.h" 1580 .file 24 "Core/Inc/PWM_control.h" 1581 .file 25 "Core/Inc/can.h" 1582 .file 26 "Core/Inc/TMP1075.h" 1583 .file 27 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h" ARM GAS /tmp/ccSWt3lr.s page 44 DEFINED SYMBOLS *ABS*:00000000 main.c /tmp/ccSWt3lr.s:25 .bss.hcan:00000000 hcan /tmp/ccSWt3lr.s:22 .bss.hcan:00000000 $d /tmp/ccSWt3lr.s:32 .bss.hi2c1:00000000 hi2c1 /tmp/ccSWt3lr.s:29 .bss.hi2c1:00000000 $d /tmp/ccSWt3lr.s:39 .bss.hi2c2:00000000 hi2c2 /tmp/ccSWt3lr.s:36 .bss.hi2c2:00000000 $d /tmp/ccSWt3lr.s:46 .bss.hspi1:00000000 hspi1 /tmp/ccSWt3lr.s:43 .bss.hspi1:00000000 $d /tmp/ccSWt3lr.s:53 .bss.htim2:00000000 htim2 /tmp/ccSWt3lr.s:50 .bss.htim2:00000000 $d /tmp/ccSWt3lr.s:60 .bss.htim3:00000000 htim3 /tmp/ccSWt3lr.s:57 .bss.htim3:00000000 $d /tmp/ccSWt3lr.s:67 .bss.htim4:00000000 htim4 /tmp/ccSWt3lr.s:64 .bss.htim4:00000000 $d /tmp/ccSWt3lr.s:74 .bss.htim15:00000000 htim15 /tmp/ccSWt3lr.s:71 .bss.htim15:00000000 $d /tmp/ccSWt3lr.s:77 .text.main:00000000 $t /tmp/ccSWt3lr.s:83 .text.main:00000000 main /tmp/ccSWt3lr.s:194 .text.SystemClock_Config:00000000 SystemClock_Config /tmp/ccSWt3lr.s:1340 .text.MX_GPIO_Init:00000000 MX_GPIO_Init /tmp/ccSWt3lr.s:315 .text.MX_CAN_Init:00000000 MX_CAN_Init /tmp/ccSWt3lr.s:402 .text.MX_I2C1_Init:00000000 MX_I2C1_Init /tmp/ccSWt3lr.s:598 .text.MX_SPI1_Init:00000000 MX_SPI1_Init /tmp/ccSWt3lr.s:1140 .text.MX_TIM15_Init:00000000 MX_TIM15_Init /tmp/ccSWt3lr.s:500 .text.MX_I2C2_Init:00000000 MX_I2C2_Init /tmp/ccSWt3lr.s:693 .text.MX_TIM2_Init:00000000 MX_TIM2_Init /tmp/ccSWt3lr.s:837 .text.MX_TIM3_Init:00000000 MX_TIM3_Init /tmp/ccSWt3lr.s:982 .text.MX_TIM4_Init:00000000 MX_TIM4_Init /tmp/ccSWt3lr.s:176 .text.main:00000094 $d /tmp/ccSWt3lr.s:188 .text.SystemClock_Config:00000000 $t /tmp/ccSWt3lr.s:1524 .text.Error_Handler:00000000 Error_Handler /tmp/ccSWt3lr.s:310 .text.MX_CAN_Init:00000000 $t /tmp/ccSWt3lr.s:391 .text.MX_CAN_Init:00000064 $d /tmp/ccSWt3lr.s:397 .text.MX_I2C1_Init:00000000 $t /tmp/ccSWt3lr.s:488 .text.MX_I2C1_Init:00000074 $d /tmp/ccSWt3lr.s:495 .text.MX_I2C2_Init:00000000 $t /tmp/ccSWt3lr.s:586 .text.MX_I2C2_Init:00000074 $d /tmp/ccSWt3lr.s:593 .text.MX_SPI1_Init:00000000 $t /tmp/ccSWt3lr.s:682 .text.MX_SPI1_Init:00000074 $d /tmp/ccSWt3lr.s:688 .text.MX_TIM2_Init:00000000 $t /tmp/ccSWt3lr.s:827 .text.MX_TIM2_Init:000000c4 $d /tmp/ccSWt3lr.s:832 .text.MX_TIM3_Init:00000000 $t /tmp/ccSWt3lr.s:971 .text.MX_TIM3_Init:000000c4 $d /tmp/ccSWt3lr.s:977 .text.MX_TIM4_Init:00000000 $t /tmp/ccSWt3lr.s:1129 .text.MX_TIM4_Init:000000d8 $d /tmp/ccSWt3lr.s:1135 .text.MX_TIM15_Init:00000000 $t /tmp/ccSWt3lr.s:1329 .text.MX_TIM15_Init:0000011c $d /tmp/ccSWt3lr.s:1335 .text.MX_GPIO_Init:00000000 $t /tmp/ccSWt3lr.s:1511 .text.MX_GPIO_Init:00000120 $d /tmp/ccSWt3lr.s:1518 .text.Error_Handler:00000000 $t UNDEFINED SYMBOLS HAL_Init sm_init tmp1075_init ARM GAS /tmp/ccSWt3lr.s page 45 AMS_Init can_init PWM_control_init soc_init status_led_init sm_program_powerground eeprom_init AMS_Loop HAL_GetTick sm_update memset HAL_RCC_OscConfig HAL_RCC_ClockConfig HAL_RCCEx_PeriphCLKConfig HAL_CAN_Init HAL_I2C_Init HAL_I2CEx_ConfigAnalogFilter HAL_I2CEx_ConfigDigitalFilter HAL_SPI_Init HAL_TIM_PWM_Init HAL_TIMEx_MasterConfigSynchronization HAL_TIM_PWM_ConfigChannel HAL_TIM_MspPostInit HAL_TIMEx_ConfigBreakDeadTime HAL_GPIO_WritePin HAL_GPIO_Init