ARM GAS /tmp/ccBZCjHD.s page 1 1 .cpu cortex-m4 2 .arch armv7e-m 3 .fpu fpv4-sp-d16 4 .eabi_attribute 27, 1 5 .eabi_attribute 28, 1 6 .eabi_attribute 20, 1 7 .eabi_attribute 21, 1 8 .eabi_attribute 23, 3 9 .eabi_attribute 24, 1 10 .eabi_attribute 25, 1 11 .eabi_attribute 26, 1 12 .eabi_attribute 30, 1 13 .eabi_attribute 34, 1 14 .eabi_attribute 18, 4 15 .file "main.c" 16 .text 17 .Ltext0: 18 .cfi_sections .debug_frame 19 .file 1 "Core/Src/main.c" 20 .section .text.MX_GPIO_Init,"ax",%progbits 21 .align 1 22 .syntax unified 23 .thumb 24 .thumb_func 26 MX_GPIO_Init: 27 .LFB138: 1:Core/Src/main.c **** /* USER CODE BEGIN Header */ 2:Core/Src/main.c **** /** 3:Core/Src/main.c **** ****************************************************************************** 4:Core/Src/main.c **** * @file : main.c 5:Core/Src/main.c **** * @brief : Main program body 6:Core/Src/main.c **** ****************************************************************************** 7:Core/Src/main.c **** * @attention 8:Core/Src/main.c **** * 9:Core/Src/main.c **** * Copyright (c) 2024 STMicroelectronics. 10:Core/Src/main.c **** * All rights reserved. 11:Core/Src/main.c **** * 12:Core/Src/main.c **** * This software is licensed under terms that can be found in the LICENSE file 13:Core/Src/main.c **** * in the root directory of this software component. 14:Core/Src/main.c **** * If no LICENSE file comes with this software, it is provided AS-IS. 15:Core/Src/main.c **** * 16:Core/Src/main.c **** ****************************************************************************** 17:Core/Src/main.c **** */ 18:Core/Src/main.c **** /* USER CODE END Header */ 19:Core/Src/main.c **** /* Includes ------------------------------------------------------------------*/ 20:Core/Src/main.c **** #include "main.h" 21:Core/Src/main.c **** 22:Core/Src/main.c **** /* Private includes ----------------------------------------------------------*/ 23:Core/Src/main.c **** /* USER CODE BEGIN Includes */ 24:Core/Src/main.c **** 25:Core/Src/main.c **** /* USER CODE END Includes */ 26:Core/Src/main.c **** 27:Core/Src/main.c **** /* Private typedef -----------------------------------------------------------*/ 28:Core/Src/main.c **** /* USER CODE BEGIN PTD */ 29:Core/Src/main.c **** 30:Core/Src/main.c **** /* USER CODE END PTD */ 31:Core/Src/main.c **** ARM GAS /tmp/ccBZCjHD.s page 2 32:Core/Src/main.c **** /* Private define ------------------------------------------------------------*/ 33:Core/Src/main.c **** /* USER CODE BEGIN PD */ 34:Core/Src/main.c **** 35:Core/Src/main.c **** /* USER CODE END PD */ 36:Core/Src/main.c **** 37:Core/Src/main.c **** /* Private macro -------------------------------------------------------------*/ 38:Core/Src/main.c **** /* USER CODE BEGIN PM */ 39:Core/Src/main.c **** 40:Core/Src/main.c **** /* USER CODE END PM */ 41:Core/Src/main.c **** 42:Core/Src/main.c **** /* Private variables ---------------------------------------------------------*/ 43:Core/Src/main.c **** CAN_HandleTypeDef hcan; 44:Core/Src/main.c **** 45:Core/Src/main.c **** I2C_HandleTypeDef hi2c1; 46:Core/Src/main.c **** 47:Core/Src/main.c **** SPI_HandleTypeDef hspi1; 48:Core/Src/main.c **** 49:Core/Src/main.c **** TIM_HandleTypeDef htim1; 50:Core/Src/main.c **** TIM_HandleTypeDef htim15; 51:Core/Src/main.c **** 52:Core/Src/main.c **** UART_HandleTypeDef huart1; 53:Core/Src/main.c **** 54:Core/Src/main.c **** /* USER CODE BEGIN PV */ 55:Core/Src/main.c **** 56:Core/Src/main.c **** /* USER CODE END PV */ 57:Core/Src/main.c **** 58:Core/Src/main.c **** /* Private function prototypes -----------------------------------------------*/ 59:Core/Src/main.c **** void SystemClock_Config(void); 60:Core/Src/main.c **** static void MX_GPIO_Init(void); 61:Core/Src/main.c **** static void MX_CAN_Init(void); 62:Core/Src/main.c **** static void MX_I2C1_Init(void); 63:Core/Src/main.c **** static void MX_SPI1_Init(void); 64:Core/Src/main.c **** static void MX_TIM15_Init(void); 65:Core/Src/main.c **** static void MX_USART1_UART_Init(void); 66:Core/Src/main.c **** static void MX_TIM1_Init(void); 67:Core/Src/main.c **** /* USER CODE BEGIN PFP */ 68:Core/Src/main.c **** 69:Core/Src/main.c **** /* USER CODE END PFP */ 70:Core/Src/main.c **** 71:Core/Src/main.c **** /* Private user code ---------------------------------------------------------*/ 72:Core/Src/main.c **** /* USER CODE BEGIN 0 */ 73:Core/Src/main.c **** 74:Core/Src/main.c **** /* USER CODE END 0 */ 75:Core/Src/main.c **** 76:Core/Src/main.c **** /** 77:Core/Src/main.c **** * @brief The application entry point. 78:Core/Src/main.c **** * @retval int 79:Core/Src/main.c **** */ 80:Core/Src/main.c **** int main(void) 81:Core/Src/main.c **** { 82:Core/Src/main.c **** 83:Core/Src/main.c **** /* USER CODE BEGIN 1 */ 84:Core/Src/main.c **** 85:Core/Src/main.c **** /* USER CODE END 1 */ 86:Core/Src/main.c **** 87:Core/Src/main.c **** /* MCU Configuration--------------------------------------------------------*/ 88:Core/Src/main.c **** ARM GAS /tmp/ccBZCjHD.s page 3 89:Core/Src/main.c **** /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ 90:Core/Src/main.c **** HAL_Init(); 91:Core/Src/main.c **** 92:Core/Src/main.c **** /* USER CODE BEGIN Init */ 93:Core/Src/main.c **** 94:Core/Src/main.c **** /* USER CODE END Init */ 95:Core/Src/main.c **** 96:Core/Src/main.c **** /* Configure the system clock */ 97:Core/Src/main.c **** SystemClock_Config(); 98:Core/Src/main.c **** 99:Core/Src/main.c **** /* USER CODE BEGIN SysInit */ 100:Core/Src/main.c **** 101:Core/Src/main.c **** /* USER CODE END SysInit */ 102:Core/Src/main.c **** 103:Core/Src/main.c **** /* Initialize all configured peripherals */ 104:Core/Src/main.c **** MX_GPIO_Init(); 105:Core/Src/main.c **** MX_CAN_Init(); 106:Core/Src/main.c **** MX_I2C1_Init(); 107:Core/Src/main.c **** MX_SPI1_Init(); 108:Core/Src/main.c **** MX_TIM15_Init(); 109:Core/Src/main.c **** MX_USART1_UART_Init(); 110:Core/Src/main.c **** MX_TIM1_Init(); 111:Core/Src/main.c **** /* USER CODE BEGIN 2 */ 112:Core/Src/main.c **** 113:Core/Src/main.c **** /* USER CODE END 2 */ 114:Core/Src/main.c **** 115:Core/Src/main.c **** /* Infinite loop */ 116:Core/Src/main.c **** /* USER CODE BEGIN WHILE */ 117:Core/Src/main.c **** while (1) 118:Core/Src/main.c **** { 119:Core/Src/main.c **** /* USER CODE END WHILE */ 120:Core/Src/main.c **** 121:Core/Src/main.c **** /* USER CODE BEGIN 3 */ 122:Core/Src/main.c **** } 123:Core/Src/main.c **** /* USER CODE END 3 */ 124:Core/Src/main.c **** } 125:Core/Src/main.c **** 126:Core/Src/main.c **** /** 127:Core/Src/main.c **** * @brief System Clock Configuration 128:Core/Src/main.c **** * @retval None 129:Core/Src/main.c **** */ 130:Core/Src/main.c **** void SystemClock_Config(void) 131:Core/Src/main.c **** { 132:Core/Src/main.c **** RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 133:Core/Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 134:Core/Src/main.c **** RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; 135:Core/Src/main.c **** 136:Core/Src/main.c **** /** Initializes the RCC Oscillators according to the specified parameters 137:Core/Src/main.c **** * in the RCC_OscInitTypeDef structure. 138:Core/Src/main.c **** */ 139:Core/Src/main.c **** RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; 140:Core/Src/main.c **** RCC_OscInitStruct.HSIState = RCC_HSI_ON; 141:Core/Src/main.c **** RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; 142:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; 143:Core/Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 144:Core/Src/main.c **** { 145:Core/Src/main.c **** Error_Handler(); ARM GAS /tmp/ccBZCjHD.s page 4 146:Core/Src/main.c **** } 147:Core/Src/main.c **** 148:Core/Src/main.c **** /** Initializes the CPU, AHB and APB buses clocks 149:Core/Src/main.c **** */ 150:Core/Src/main.c **** RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 151:Core/Src/main.c **** |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; 152:Core/Src/main.c **** RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; 153:Core/Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 154:Core/Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; 155:Core/Src/main.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 156:Core/Src/main.c **** 157:Core/Src/main.c **** if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) 158:Core/Src/main.c **** { 159:Core/Src/main.c **** Error_Handler(); 160:Core/Src/main.c **** } 161:Core/Src/main.c **** PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1|RCC_PERIPHCLK_I2C1 162:Core/Src/main.c **** |RCC_PERIPHCLK_TIM1; 163:Core/Src/main.c **** PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2; 164:Core/Src/main.c **** PeriphClkInit.I2c1ClockSelection = RCC_I2C1CLKSOURCE_HSI; 165:Core/Src/main.c **** PeriphClkInit.Tim1ClockSelection = RCC_TIM1CLK_HCLK; 166:Core/Src/main.c **** if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 167:Core/Src/main.c **** { 168:Core/Src/main.c **** Error_Handler(); 169:Core/Src/main.c **** } 170:Core/Src/main.c **** } 171:Core/Src/main.c **** 172:Core/Src/main.c **** /** 173:Core/Src/main.c **** * @brief CAN Initialization Function 174:Core/Src/main.c **** * @param None 175:Core/Src/main.c **** * @retval None 176:Core/Src/main.c **** */ 177:Core/Src/main.c **** static void MX_CAN_Init(void) 178:Core/Src/main.c **** { 179:Core/Src/main.c **** 180:Core/Src/main.c **** /* USER CODE BEGIN CAN_Init 0 */ 181:Core/Src/main.c **** 182:Core/Src/main.c **** /* USER CODE END CAN_Init 0 */ 183:Core/Src/main.c **** 184:Core/Src/main.c **** /* USER CODE BEGIN CAN_Init 1 */ 185:Core/Src/main.c **** 186:Core/Src/main.c **** /* USER CODE END CAN_Init 1 */ 187:Core/Src/main.c **** hcan.Instance = CAN; 188:Core/Src/main.c **** hcan.Init.Prescaler = 16; 189:Core/Src/main.c **** hcan.Init.Mode = CAN_MODE_NORMAL; 190:Core/Src/main.c **** hcan.Init.SyncJumpWidth = CAN_SJW_1TQ; 191:Core/Src/main.c **** hcan.Init.TimeSeg1 = CAN_BS1_1TQ; 192:Core/Src/main.c **** hcan.Init.TimeSeg2 = CAN_BS2_1TQ; 193:Core/Src/main.c **** hcan.Init.TimeTriggeredMode = DISABLE; 194:Core/Src/main.c **** hcan.Init.AutoBusOff = DISABLE; 195:Core/Src/main.c **** hcan.Init.AutoWakeUp = DISABLE; 196:Core/Src/main.c **** hcan.Init.AutoRetransmission = DISABLE; 197:Core/Src/main.c **** hcan.Init.ReceiveFifoLocked = DISABLE; 198:Core/Src/main.c **** hcan.Init.TransmitFifoPriority = DISABLE; 199:Core/Src/main.c **** if (HAL_CAN_Init(&hcan) != HAL_OK) 200:Core/Src/main.c **** { 201:Core/Src/main.c **** Error_Handler(); 202:Core/Src/main.c **** } ARM GAS /tmp/ccBZCjHD.s page 5 203:Core/Src/main.c **** /* USER CODE BEGIN CAN_Init 2 */ 204:Core/Src/main.c **** 205:Core/Src/main.c **** /* USER CODE END CAN_Init 2 */ 206:Core/Src/main.c **** 207:Core/Src/main.c **** } 208:Core/Src/main.c **** 209:Core/Src/main.c **** /** 210:Core/Src/main.c **** * @brief I2C1 Initialization Function 211:Core/Src/main.c **** * @param None 212:Core/Src/main.c **** * @retval None 213:Core/Src/main.c **** */ 214:Core/Src/main.c **** static void MX_I2C1_Init(void) 215:Core/Src/main.c **** { 216:Core/Src/main.c **** 217:Core/Src/main.c **** /* USER CODE BEGIN I2C1_Init 0 */ 218:Core/Src/main.c **** 219:Core/Src/main.c **** /* USER CODE END I2C1_Init 0 */ 220:Core/Src/main.c **** 221:Core/Src/main.c **** /* USER CODE BEGIN I2C1_Init 1 */ 222:Core/Src/main.c **** 223:Core/Src/main.c **** /* USER CODE END I2C1_Init 1 */ 224:Core/Src/main.c **** hi2c1.Instance = I2C1; 225:Core/Src/main.c **** hi2c1.Init.Timing = 0x2000090E; 226:Core/Src/main.c **** hi2c1.Init.OwnAddress1 = 0; 227:Core/Src/main.c **** hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; 228:Core/Src/main.c **** hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; 229:Core/Src/main.c **** hi2c1.Init.OwnAddress2 = 0; 230:Core/Src/main.c **** hi2c1.Init.OwnAddress2Masks = I2C_OA2_NOMASK; 231:Core/Src/main.c **** hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; 232:Core/Src/main.c **** hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; 233:Core/Src/main.c **** if (HAL_I2C_Init(&hi2c1) != HAL_OK) 234:Core/Src/main.c **** { 235:Core/Src/main.c **** Error_Handler(); 236:Core/Src/main.c **** } 237:Core/Src/main.c **** 238:Core/Src/main.c **** /** Configure Analogue filter 239:Core/Src/main.c **** */ 240:Core/Src/main.c **** if (HAL_I2CEx_ConfigAnalogFilter(&hi2c1, I2C_ANALOGFILTER_ENABLE) != HAL_OK) 241:Core/Src/main.c **** { 242:Core/Src/main.c **** Error_Handler(); 243:Core/Src/main.c **** } 244:Core/Src/main.c **** 245:Core/Src/main.c **** /** Configure Digital filter 246:Core/Src/main.c **** */ 247:Core/Src/main.c **** if (HAL_I2CEx_ConfigDigitalFilter(&hi2c1, 0) != HAL_OK) 248:Core/Src/main.c **** { 249:Core/Src/main.c **** Error_Handler(); 250:Core/Src/main.c **** } 251:Core/Src/main.c **** /* USER CODE BEGIN I2C1_Init 2 */ 252:Core/Src/main.c **** 253:Core/Src/main.c **** /* USER CODE END I2C1_Init 2 */ 254:Core/Src/main.c **** 255:Core/Src/main.c **** } 256:Core/Src/main.c **** 257:Core/Src/main.c **** /** 258:Core/Src/main.c **** * @brief SPI1 Initialization Function 259:Core/Src/main.c **** * @param None ARM GAS /tmp/ccBZCjHD.s page 6 260:Core/Src/main.c **** * @retval None 261:Core/Src/main.c **** */ 262:Core/Src/main.c **** static void MX_SPI1_Init(void) 263:Core/Src/main.c **** { 264:Core/Src/main.c **** 265:Core/Src/main.c **** /* USER CODE BEGIN SPI1_Init 0 */ 266:Core/Src/main.c **** 267:Core/Src/main.c **** /* USER CODE END SPI1_Init 0 */ 268:Core/Src/main.c **** 269:Core/Src/main.c **** /* USER CODE BEGIN SPI1_Init 1 */ 270:Core/Src/main.c **** 271:Core/Src/main.c **** /* USER CODE END SPI1_Init 1 */ 272:Core/Src/main.c **** /* SPI1 parameter configuration*/ 273:Core/Src/main.c **** hspi1.Instance = SPI1; 274:Core/Src/main.c **** hspi1.Init.Mode = SPI_MODE_MASTER; 275:Core/Src/main.c **** hspi1.Init.Direction = SPI_DIRECTION_2LINES; 276:Core/Src/main.c **** hspi1.Init.DataSize = SPI_DATASIZE_4BIT; 277:Core/Src/main.c **** hspi1.Init.CLKPolarity = SPI_POLARITY_LOW; 278:Core/Src/main.c **** hspi1.Init.CLKPhase = SPI_PHASE_1EDGE; 279:Core/Src/main.c **** hspi1.Init.NSS = SPI_NSS_HARD_INPUT; 280:Core/Src/main.c **** hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; 281:Core/Src/main.c **** hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; 282:Core/Src/main.c **** hspi1.Init.TIMode = SPI_TIMODE_DISABLE; 283:Core/Src/main.c **** hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; 284:Core/Src/main.c **** hspi1.Init.CRCPolynomial = 7; 285:Core/Src/main.c **** hspi1.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE; 286:Core/Src/main.c **** hspi1.Init.NSSPMode = SPI_NSS_PULSE_ENABLE; 287:Core/Src/main.c **** if (HAL_SPI_Init(&hspi1) != HAL_OK) 288:Core/Src/main.c **** { 289:Core/Src/main.c **** Error_Handler(); 290:Core/Src/main.c **** } 291:Core/Src/main.c **** /* USER CODE BEGIN SPI1_Init 2 */ 292:Core/Src/main.c **** 293:Core/Src/main.c **** /* USER CODE END SPI1_Init 2 */ 294:Core/Src/main.c **** 295:Core/Src/main.c **** } 296:Core/Src/main.c **** 297:Core/Src/main.c **** /** 298:Core/Src/main.c **** * @brief TIM1 Initialization Function 299:Core/Src/main.c **** * @param None 300:Core/Src/main.c **** * @retval None 301:Core/Src/main.c **** */ 302:Core/Src/main.c **** static void MX_TIM1_Init(void) 303:Core/Src/main.c **** { 304:Core/Src/main.c **** 305:Core/Src/main.c **** /* USER CODE BEGIN TIM1_Init 0 */ 306:Core/Src/main.c **** 307:Core/Src/main.c **** /* USER CODE END TIM1_Init 0 */ 308:Core/Src/main.c **** 309:Core/Src/main.c **** TIM_MasterConfigTypeDef sMasterConfig = {0}; 310:Core/Src/main.c **** TIM_OC_InitTypeDef sConfigOC = {0}; 311:Core/Src/main.c **** TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0}; 312:Core/Src/main.c **** 313:Core/Src/main.c **** /* USER CODE BEGIN TIM1_Init 1 */ 314:Core/Src/main.c **** 315:Core/Src/main.c **** /* USER CODE END TIM1_Init 1 */ 316:Core/Src/main.c **** htim1.Instance = TIM1; ARM GAS /tmp/ccBZCjHD.s page 7 317:Core/Src/main.c **** htim1.Init.Prescaler = 0; 318:Core/Src/main.c **** htim1.Init.CounterMode = TIM_COUNTERMODE_UP; 319:Core/Src/main.c **** htim1.Init.Period = 65535; 320:Core/Src/main.c **** htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 321:Core/Src/main.c **** htim1.Init.RepetitionCounter = 0; 322:Core/Src/main.c **** htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 323:Core/Src/main.c **** if (HAL_TIM_PWM_Init(&htim1) != HAL_OK) 324:Core/Src/main.c **** { 325:Core/Src/main.c **** Error_Handler(); 326:Core/Src/main.c **** } 327:Core/Src/main.c **** sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 328:Core/Src/main.c **** sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET; 329:Core/Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 330:Core/Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK) 331:Core/Src/main.c **** { 332:Core/Src/main.c **** Error_Handler(); 333:Core/Src/main.c **** } 334:Core/Src/main.c **** sConfigOC.OCMode = TIM_OCMODE_PWM1; 335:Core/Src/main.c **** sConfigOC.Pulse = 0; 336:Core/Src/main.c **** sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 337:Core/Src/main.c **** sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH; 338:Core/Src/main.c **** sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 339:Core/Src/main.c **** sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET; 340:Core/Src/main.c **** sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET; 341:Core/Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) 342:Core/Src/main.c **** { 343:Core/Src/main.c **** Error_Handler(); 344:Core/Src/main.c **** } 345:Core/Src/main.c **** sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE; 346:Core/Src/main.c **** sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE; 347:Core/Src/main.c **** sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF; 348:Core/Src/main.c **** sBreakDeadTimeConfig.DeadTime = 0; 349:Core/Src/main.c **** sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE; 350:Core/Src/main.c **** sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH; 351:Core/Src/main.c **** sBreakDeadTimeConfig.BreakFilter = 0; 352:Core/Src/main.c **** sBreakDeadTimeConfig.Break2State = TIM_BREAK2_DISABLE; 353:Core/Src/main.c **** sBreakDeadTimeConfig.Break2Polarity = TIM_BREAK2POLARITY_HIGH; 354:Core/Src/main.c **** sBreakDeadTimeConfig.Break2Filter = 0; 355:Core/Src/main.c **** sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE; 356:Core/Src/main.c **** if (HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig) != HAL_OK) 357:Core/Src/main.c **** { 358:Core/Src/main.c **** Error_Handler(); 359:Core/Src/main.c **** } 360:Core/Src/main.c **** /* USER CODE BEGIN TIM1_Init 2 */ 361:Core/Src/main.c **** 362:Core/Src/main.c **** /* USER CODE END TIM1_Init 2 */ 363:Core/Src/main.c **** HAL_TIM_MspPostInit(&htim1); 364:Core/Src/main.c **** 365:Core/Src/main.c **** } 366:Core/Src/main.c **** 367:Core/Src/main.c **** /** 368:Core/Src/main.c **** * @brief TIM15 Initialization Function 369:Core/Src/main.c **** * @param None 370:Core/Src/main.c **** * @retval None 371:Core/Src/main.c **** */ 372:Core/Src/main.c **** static void MX_TIM15_Init(void) 373:Core/Src/main.c **** { ARM GAS /tmp/ccBZCjHD.s page 8 374:Core/Src/main.c **** 375:Core/Src/main.c **** /* USER CODE BEGIN TIM15_Init 0 */ 376:Core/Src/main.c **** 377:Core/Src/main.c **** /* USER CODE END TIM15_Init 0 */ 378:Core/Src/main.c **** 379:Core/Src/main.c **** TIM_MasterConfigTypeDef sMasterConfig = {0}; 380:Core/Src/main.c **** TIM_OC_InitTypeDef sConfigOC = {0}; 381:Core/Src/main.c **** TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0}; 382:Core/Src/main.c **** 383:Core/Src/main.c **** /* USER CODE BEGIN TIM15_Init 1 */ 384:Core/Src/main.c **** 385:Core/Src/main.c **** /* USER CODE END TIM15_Init 1 */ 386:Core/Src/main.c **** htim15.Instance = TIM15; 387:Core/Src/main.c **** htim15.Init.Prescaler = 0; 388:Core/Src/main.c **** htim15.Init.CounterMode = TIM_COUNTERMODE_UP; 389:Core/Src/main.c **** htim15.Init.Period = 65535; 390:Core/Src/main.c **** htim15.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 391:Core/Src/main.c **** htim15.Init.RepetitionCounter = 0; 392:Core/Src/main.c **** htim15.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 393:Core/Src/main.c **** if (HAL_TIM_PWM_Init(&htim15) != HAL_OK) 394:Core/Src/main.c **** { 395:Core/Src/main.c **** Error_Handler(); 396:Core/Src/main.c **** } 397:Core/Src/main.c **** sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 398:Core/Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 399:Core/Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim15, &sMasterConfig) != HAL_OK) 400:Core/Src/main.c **** { 401:Core/Src/main.c **** Error_Handler(); 402:Core/Src/main.c **** } 403:Core/Src/main.c **** sConfigOC.OCMode = TIM_OCMODE_PWM1; 404:Core/Src/main.c **** sConfigOC.Pulse = 0; 405:Core/Src/main.c **** sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 406:Core/Src/main.c **** sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH; 407:Core/Src/main.c **** sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 408:Core/Src/main.c **** sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET; 409:Core/Src/main.c **** sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET; 410:Core/Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim15, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) 411:Core/Src/main.c **** { 412:Core/Src/main.c **** Error_Handler(); 413:Core/Src/main.c **** } 414:Core/Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim15, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) 415:Core/Src/main.c **** { 416:Core/Src/main.c **** Error_Handler(); 417:Core/Src/main.c **** } 418:Core/Src/main.c **** sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE; 419:Core/Src/main.c **** sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE; 420:Core/Src/main.c **** sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF; 421:Core/Src/main.c **** sBreakDeadTimeConfig.DeadTime = 0; 422:Core/Src/main.c **** sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE; 423:Core/Src/main.c **** sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH; 424:Core/Src/main.c **** sBreakDeadTimeConfig.BreakFilter = 0; 425:Core/Src/main.c **** sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE; 426:Core/Src/main.c **** if (HAL_TIMEx_ConfigBreakDeadTime(&htim15, &sBreakDeadTimeConfig) != HAL_OK) 427:Core/Src/main.c **** { 428:Core/Src/main.c **** Error_Handler(); 429:Core/Src/main.c **** } 430:Core/Src/main.c **** /* USER CODE BEGIN TIM15_Init 2 */ ARM GAS /tmp/ccBZCjHD.s page 9 431:Core/Src/main.c **** 432:Core/Src/main.c **** /* USER CODE END TIM15_Init 2 */ 433:Core/Src/main.c **** HAL_TIM_MspPostInit(&htim15); 434:Core/Src/main.c **** 435:Core/Src/main.c **** } 436:Core/Src/main.c **** 437:Core/Src/main.c **** /** 438:Core/Src/main.c **** * @brief USART1 Initialization Function 439:Core/Src/main.c **** * @param None 440:Core/Src/main.c **** * @retval None 441:Core/Src/main.c **** */ 442:Core/Src/main.c **** static void MX_USART1_UART_Init(void) 443:Core/Src/main.c **** { 444:Core/Src/main.c **** 445:Core/Src/main.c **** /* USER CODE BEGIN USART1_Init 0 */ 446:Core/Src/main.c **** 447:Core/Src/main.c **** /* USER CODE END USART1_Init 0 */ 448:Core/Src/main.c **** 449:Core/Src/main.c **** /* USER CODE BEGIN USART1_Init 1 */ 450:Core/Src/main.c **** 451:Core/Src/main.c **** /* USER CODE END USART1_Init 1 */ 452:Core/Src/main.c **** huart1.Instance = USART1; 453:Core/Src/main.c **** huart1.Init.BaudRate = 38400; 454:Core/Src/main.c **** huart1.Init.WordLength = UART_WORDLENGTH_8B; 455:Core/Src/main.c **** huart1.Init.StopBits = UART_STOPBITS_1; 456:Core/Src/main.c **** huart1.Init.Parity = UART_PARITY_NONE; 457:Core/Src/main.c **** huart1.Init.Mode = UART_MODE_TX_RX; 458:Core/Src/main.c **** huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; 459:Core/Src/main.c **** huart1.Init.OverSampling = UART_OVERSAMPLING_16; 460:Core/Src/main.c **** huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; 461:Core/Src/main.c **** huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; 462:Core/Src/main.c **** if (HAL_UART_Init(&huart1) != HAL_OK) 463:Core/Src/main.c **** { 464:Core/Src/main.c **** Error_Handler(); 465:Core/Src/main.c **** } 466:Core/Src/main.c **** /* USER CODE BEGIN USART1_Init 2 */ 467:Core/Src/main.c **** 468:Core/Src/main.c **** /* USER CODE END USART1_Init 2 */ 469:Core/Src/main.c **** 470:Core/Src/main.c **** } 471:Core/Src/main.c **** 472:Core/Src/main.c **** /** 473:Core/Src/main.c **** * @brief GPIO Initialization Function 474:Core/Src/main.c **** * @param None 475:Core/Src/main.c **** * @retval None 476:Core/Src/main.c **** */ 477:Core/Src/main.c **** static void MX_GPIO_Init(void) 478:Core/Src/main.c **** { 28 .loc 1 478 1 view -0 29 .cfi_startproc 30 @ args = 0, pretend = 0, frame = 40 31 @ frame_needed = 0, uses_anonymous_args = 0 32 0000 F0B5 push {r4, r5, r6, r7, lr} 33 .cfi_def_cfa_offset 20 34 .cfi_offset 4, -20 35 .cfi_offset 5, -16 36 .cfi_offset 6, -12 ARM GAS /tmp/ccBZCjHD.s page 10 37 .cfi_offset 7, -8 38 .cfi_offset 14, -4 39 0002 8BB0 sub sp, sp, #44 40 .cfi_def_cfa_offset 64 479:Core/Src/main.c **** GPIO_InitTypeDef GPIO_InitStruct = {0}; 41 .loc 1 479 3 view .LVU1 42 .loc 1 479 20 is_stmt 0 view .LVU2 43 0004 0024 movs r4, #0 44 0006 0594 str r4, [sp, #20] 45 0008 0694 str r4, [sp, #24] 46 000a 0794 str r4, [sp, #28] 47 000c 0894 str r4, [sp, #32] 48 000e 0994 str r4, [sp, #36] 480:Core/Src/main.c **** /* USER CODE BEGIN MX_GPIO_Init_1 */ 481:Core/Src/main.c **** /* USER CODE END MX_GPIO_Init_1 */ 482:Core/Src/main.c **** 483:Core/Src/main.c **** /* GPIO Ports Clock Enable */ 484:Core/Src/main.c **** __HAL_RCC_GPIOC_CLK_ENABLE(); 49 .loc 1 484 3 is_stmt 1 view .LVU3 50 .LBB4: 51 .loc 1 484 3 view .LVU4 52 .loc 1 484 3 view .LVU5 53 0010 364B ldr r3, .L3 54 0012 5A69 ldr r2, [r3, #20] 55 0014 42F40022 orr r2, r2, #524288 56 0018 5A61 str r2, [r3, #20] 57 .loc 1 484 3 view .LVU6 58 001a 5A69 ldr r2, [r3, #20] 59 001c 02F40022 and r2, r2, #524288 60 0020 0192 str r2, [sp, #4] 61 .loc 1 484 3 view .LVU7 62 0022 019A ldr r2, [sp, #4] 63 .LBE4: 64 .loc 1 484 3 view .LVU8 485:Core/Src/main.c **** __HAL_RCC_GPIOF_CLK_ENABLE(); 65 .loc 1 485 3 view .LVU9 66 .LBB5: 67 .loc 1 485 3 view .LVU10 68 .loc 1 485 3 view .LVU11 69 0024 5A69 ldr r2, [r3, #20] 70 0026 42F48002 orr r2, r2, #4194304 71 002a 5A61 str r2, [r3, #20] 72 .loc 1 485 3 view .LVU12 73 002c 5A69 ldr r2, [r3, #20] 74 002e 02F48002 and r2, r2, #4194304 75 0032 0292 str r2, [sp, #8] 76 .loc 1 485 3 view .LVU13 77 0034 029A ldr r2, [sp, #8] 78 .LBE5: 79 .loc 1 485 3 view .LVU14 486:Core/Src/main.c **** __HAL_RCC_GPIOA_CLK_ENABLE(); 80 .loc 1 486 3 view .LVU15 81 .LBB6: 82 .loc 1 486 3 view .LVU16 83 .loc 1 486 3 view .LVU17 84 0036 5A69 ldr r2, [r3, #20] 85 0038 42F40032 orr r2, r2, #131072 ARM GAS /tmp/ccBZCjHD.s page 11 86 003c 5A61 str r2, [r3, #20] 87 .loc 1 486 3 view .LVU18 88 003e 5A69 ldr r2, [r3, #20] 89 0040 02F40032 and r2, r2, #131072 90 0044 0392 str r2, [sp, #12] 91 .loc 1 486 3 view .LVU19 92 0046 039A ldr r2, [sp, #12] 93 .LBE6: 94 .loc 1 486 3 view .LVU20 487:Core/Src/main.c **** __HAL_RCC_GPIOB_CLK_ENABLE(); 95 .loc 1 487 3 view .LVU21 96 .LBB7: 97 .loc 1 487 3 view .LVU22 98 .loc 1 487 3 view .LVU23 99 0048 5A69 ldr r2, [r3, #20] 100 004a 42F48022 orr r2, r2, #262144 101 004e 5A61 str r2, [r3, #20] 102 .loc 1 487 3 view .LVU24 103 0050 5B69 ldr r3, [r3, #20] 104 0052 03F48023 and r3, r3, #262144 105 0056 0493 str r3, [sp, #16] 106 .loc 1 487 3 view .LVU25 107 0058 049B ldr r3, [sp, #16] 108 .LBE7: 109 .loc 1 487 3 view .LVU26 488:Core/Src/main.c **** 489:Core/Src/main.c **** /*Configure GPIO pin Output Level */ 490:Core/Src/main.c **** HAL_GPIO_WritePin(GPIOA, RELAY_EN_Pin|_60V_EN_Pin, GPIO_PIN_RESET); 110 .loc 1 490 3 view .LVU27 111 005a 2246 mov r2, r4 112 005c 0321 movs r1, #3 113 005e 4FF09040 mov r0, #1207959552 114 0062 FFF7FEFF bl HAL_GPIO_WritePin 115 .LVL0: 491:Core/Src/main.c **** 492:Core/Src/main.c **** /*Configure GPIO pin Output Level */ 493:Core/Src/main.c **** HAL_GPIO_WritePin(GPIOB, PRECHARGE_EN_Pin|AUX_IN_Pin, GPIO_PIN_RESET); 116 .loc 1 493 3 view .LVU28 117 0066 224D ldr r5, .L3+4 118 0068 2246 mov r2, r4 119 006a 4FF42051 mov r1, #10240 120 006e 2846 mov r0, r5 121 0070 FFF7FEFF bl HAL_GPIO_WritePin 122 .LVL1: 494:Core/Src/main.c **** 495:Core/Src/main.c **** /*Configure GPIO pins : PC13 PC14 PC15 */ 496:Core/Src/main.c **** GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15; 123 .loc 1 496 3 view .LVU29 124 .loc 1 496 23 is_stmt 0 view .LVU30 125 0074 4FF46043 mov r3, #57344 126 0078 0593 str r3, [sp, #20] 497:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 127 .loc 1 497 3 is_stmt 1 view .LVU31 128 .loc 1 497 24 is_stmt 0 view .LVU32 129 007a 0326 movs r6, #3 130 007c 0696 str r6, [sp, #24] 498:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; ARM GAS /tmp/ccBZCjHD.s page 12 131 .loc 1 498 3 is_stmt 1 view .LVU33 132 .loc 1 498 24 is_stmt 0 view .LVU34 133 007e 0794 str r4, [sp, #28] 499:Core/Src/main.c **** HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 134 .loc 1 499 3 is_stmt 1 view .LVU35 135 0080 05A9 add r1, sp, #20 136 0082 1C48 ldr r0, .L3+8 137 0084 FFF7FEFF bl HAL_GPIO_Init 138 .LVL2: 500:Core/Src/main.c **** 501:Core/Src/main.c **** /*Configure GPIO pins : RELAY_EN_Pin _60V_EN_Pin */ 502:Core/Src/main.c **** GPIO_InitStruct.Pin = RELAY_EN_Pin|_60V_EN_Pin; 139 .loc 1 502 3 view .LVU36 140 .loc 1 502 23 is_stmt 0 view .LVU37 141 0088 0596 str r6, [sp, #20] 503:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 142 .loc 1 503 3 is_stmt 1 view .LVU38 143 .loc 1 503 24 is_stmt 0 view .LVU39 144 008a 0127 movs r7, #1 145 008c 0697 str r7, [sp, #24] 504:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 146 .loc 1 504 3 is_stmt 1 view .LVU40 147 .loc 1 504 24 is_stmt 0 view .LVU41 148 008e 0794 str r4, [sp, #28] 505:Core/Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 149 .loc 1 505 3 is_stmt 1 view .LVU42 150 .loc 1 505 25 is_stmt 0 view .LVU43 151 0090 0894 str r4, [sp, #32] 506:Core/Src/main.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 152 .loc 1 506 3 is_stmt 1 view .LVU44 153 0092 05A9 add r1, sp, #20 154 0094 4FF09040 mov r0, #1207959552 155 0098 FFF7FEFF bl HAL_GPIO_Init 156 .LVL3: 507:Core/Src/main.c **** 508:Core/Src/main.c **** /*Configure GPIO pins : STATUS_LED_R_Pin STATUS_LED_B_Pin STATUS_LED_G_Pin AUX_OUT_Pin */ 509:Core/Src/main.c **** GPIO_InitStruct.Pin = STATUS_LED_R_Pin|STATUS_LED_B_Pin|STATUS_LED_G_Pin|AUX_OUT_Pin; 157 .loc 1 509 3 view .LVU45 158 .loc 1 509 23 is_stmt 0 view .LVU46 159 009c 44F20703 movw r3, #16391 160 00a0 0593 str r3, [sp, #20] 510:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 161 .loc 1 510 3 is_stmt 1 view .LVU47 162 .loc 1 510 24 is_stmt 0 view .LVU48 163 00a2 0694 str r4, [sp, #24] 511:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 164 .loc 1 511 3 is_stmt 1 view .LVU49 165 .loc 1 511 24 is_stmt 0 view .LVU50 166 00a4 0794 str r4, [sp, #28] 512:Core/Src/main.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 167 .loc 1 512 3 is_stmt 1 view .LVU51 168 00a6 05A9 add r1, sp, #20 169 00a8 2846 mov r0, r5 170 00aa FFF7FEFF bl HAL_GPIO_Init 171 .LVL4: 513:Core/Src/main.c **** 514:Core/Src/main.c **** /*Configure GPIO pins : PB10 PB12 PB4 PB5 ARM GAS /tmp/ccBZCjHD.s page 13 515:Core/Src/main.c **** PB8 */ 516:Core/Src/main.c **** GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_12|GPIO_PIN_4|GPIO_PIN_5 172 .loc 1 516 3 view .LVU52 173 .loc 1 516 23 is_stmt 0 view .LVU53 174 00ae 41F23053 movw r3, #5424 175 00b2 0593 str r3, [sp, #20] 517:Core/Src/main.c **** |GPIO_PIN_8; 518:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 176 .loc 1 518 3 is_stmt 1 view .LVU54 177 .loc 1 518 24 is_stmt 0 view .LVU55 178 00b4 0696 str r6, [sp, #24] 519:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 179 .loc 1 519 3 is_stmt 1 view .LVU56 180 .loc 1 519 24 is_stmt 0 view .LVU57 181 00b6 0794 str r4, [sp, #28] 520:Core/Src/main.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 182 .loc 1 520 3 is_stmt 1 view .LVU58 183 00b8 05A9 add r1, sp, #20 184 00ba 2846 mov r0, r5 185 00bc FFF7FEFF bl HAL_GPIO_Init 186 .LVL5: 521:Core/Src/main.c **** 522:Core/Src/main.c **** /*Configure GPIO pins : PRECHARGE_EN_Pin AUX_IN_Pin */ 523:Core/Src/main.c **** GPIO_InitStruct.Pin = PRECHARGE_EN_Pin|AUX_IN_Pin; 187 .loc 1 523 3 view .LVU59 188 .loc 1 523 23 is_stmt 0 view .LVU60 189 00c0 4FF42053 mov r3, #10240 190 00c4 0593 str r3, [sp, #20] 524:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 191 .loc 1 524 3 is_stmt 1 view .LVU61 192 .loc 1 524 24 is_stmt 0 view .LVU62 193 00c6 0697 str r7, [sp, #24] 525:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 194 .loc 1 525 3 is_stmt 1 view .LVU63 195 .loc 1 525 24 is_stmt 0 view .LVU64 196 00c8 0794 str r4, [sp, #28] 526:Core/Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 197 .loc 1 526 3 is_stmt 1 view .LVU65 198 .loc 1 526 25 is_stmt 0 view .LVU66 199 00ca 0894 str r4, [sp, #32] 527:Core/Src/main.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 200 .loc 1 527 3 is_stmt 1 view .LVU67 201 00cc 05A9 add r1, sp, #20 202 00ce 2846 mov r0, r5 203 00d0 FFF7FEFF bl HAL_GPIO_Init 204 .LVL6: 528:Core/Src/main.c **** 529:Core/Src/main.c **** /*Configure GPIO pins : RELAY_BATT_SIDE_ON_Pin RELAY_ESC_SIDE_ON_Pin CURRENT_SENSOR_ON_Pin */ 530:Core/Src/main.c **** GPIO_InitStruct.Pin = RELAY_BATT_SIDE_ON_Pin|RELAY_ESC_SIDE_ON_Pin|CURRENT_SENSOR_ON_Pin; 205 .loc 1 530 3 view .LVU68 206 .loc 1 530 23 is_stmt 0 view .LVU69 207 00d4 4FF4E063 mov r3, #1792 208 00d8 0593 str r3, [sp, #20] 531:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 209 .loc 1 531 3 is_stmt 1 view .LVU70 210 .loc 1 531 24 is_stmt 0 view .LVU71 211 00da 0694 str r4, [sp, #24] ARM GAS /tmp/ccBZCjHD.s page 14 532:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 212 .loc 1 532 3 is_stmt 1 view .LVU72 213 .loc 1 532 24 is_stmt 0 view .LVU73 214 00dc 0794 str r4, [sp, #28] 533:Core/Src/main.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 215 .loc 1 533 3 is_stmt 1 view .LVU74 216 00de 05A9 add r1, sp, #20 217 00e0 4FF09040 mov r0, #1207959552 218 00e4 FFF7FEFF bl HAL_GPIO_Init 219 .LVL7: 534:Core/Src/main.c **** 535:Core/Src/main.c **** /* USER CODE BEGIN MX_GPIO_Init_2 */ 536:Core/Src/main.c **** /* USER CODE END MX_GPIO_Init_2 */ 537:Core/Src/main.c **** } 220 .loc 1 537 1 is_stmt 0 view .LVU75 221 00e8 0BB0 add sp, sp, #44 222 .cfi_def_cfa_offset 20 223 @ sp needed 224 00ea F0BD pop {r4, r5, r6, r7, pc} 225 .L4: 226 .align 2 227 .L3: 228 00ec 00100240 .word 1073876992 229 00f0 00040048 .word 1207960576 230 00f4 00080048 .word 1207961600 231 .cfi_endproc 232 .LFE138: 234 .section .text.Error_Handler,"ax",%progbits 235 .align 1 236 .global Error_Handler 237 .syntax unified 238 .thumb 239 .thumb_func 241 Error_Handler: 242 .LFB139: 538:Core/Src/main.c **** 539:Core/Src/main.c **** /* USER CODE BEGIN 4 */ 540:Core/Src/main.c **** 541:Core/Src/main.c **** /* USER CODE END 4 */ 542:Core/Src/main.c **** 543:Core/Src/main.c **** /** 544:Core/Src/main.c **** * @brief This function is executed in case of error occurrence. 545:Core/Src/main.c **** * @retval None 546:Core/Src/main.c **** */ 547:Core/Src/main.c **** void Error_Handler(void) 548:Core/Src/main.c **** { 243 .loc 1 548 1 is_stmt 1 view -0 244 .cfi_startproc 245 @ Volatile: function does not return. 246 @ args = 0, pretend = 0, frame = 0 247 @ frame_needed = 0, uses_anonymous_args = 0 248 @ link register save eliminated. 549:Core/Src/main.c **** /* USER CODE BEGIN Error_Handler_Debug */ 550:Core/Src/main.c **** /* User can add his own implementation to report the HAL error return state */ 551:Core/Src/main.c **** __disable_irq(); 249 .loc 1 551 3 view .LVU77 250 .LBB8: ARM GAS /tmp/ccBZCjHD.s page 15 251 .LBI8: 252 .file 2 "Drivers/CMSIS/Include/cmsis_gcc.h" 1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//** 2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h 3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS compiler GCC header file 4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V5.0.4 5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 09. April 2018 6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/ 7:Drivers/CMSIS/Include/cmsis_gcc.h **** /* 8:Drivers/CMSIS/Include/cmsis_gcc.h **** * Copyright (c) 2009-2018 Arm Limited. All rights reserved. 9:Drivers/CMSIS/Include/cmsis_gcc.h **** * 10:Drivers/CMSIS/Include/cmsis_gcc.h **** * SPDX-License-Identifier: Apache-2.0 11:Drivers/CMSIS/Include/cmsis_gcc.h **** * 12:Drivers/CMSIS/Include/cmsis_gcc.h **** * Licensed under the Apache License, Version 2.0 (the License); you may 13:Drivers/CMSIS/Include/cmsis_gcc.h **** * not use this file except in compliance with the License. 14:Drivers/CMSIS/Include/cmsis_gcc.h **** * You may obtain a copy of the License at 15:Drivers/CMSIS/Include/cmsis_gcc.h **** * 16:Drivers/CMSIS/Include/cmsis_gcc.h **** * www.apache.org/licenses/LICENSE-2.0 17:Drivers/CMSIS/Include/cmsis_gcc.h **** * 18:Drivers/CMSIS/Include/cmsis_gcc.h **** * Unless required by applicable law or agreed to in writing, software 19:Drivers/CMSIS/Include/cmsis_gcc.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20:Drivers/CMSIS/Include/cmsis_gcc.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21:Drivers/CMSIS/Include/cmsis_gcc.h **** * See the License for the specific language governing permissions and 22:Drivers/CMSIS/Include/cmsis_gcc.h **** * limitations under the License. 23:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 24:Drivers/CMSIS/Include/cmsis_gcc.h **** 25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H 26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H 27:Drivers/CMSIS/Include/cmsis_gcc.h **** 28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */ 29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion" 31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion" 32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter" 33:Drivers/CMSIS/Include/cmsis_gcc.h **** 34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */ 35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin 36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __has_builtin(x) (0) 37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 38:Drivers/CMSIS/Include/cmsis_gcc.h **** 39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */ 40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ASM 41:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ASM __asm 42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INLINE 44:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INLINE inline 45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_INLINE 47:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_INLINE static inline 48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_FORCEINLINE 50:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline 51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __NO_RETURN 53:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NO_RETURN __attribute__((__noreturn__)) 54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __USED ARM GAS /tmp/ccBZCjHD.s page 16 56:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USED __attribute__((used)) 57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __WEAK 59:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WEAK __attribute__((weak)) 60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED 62:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED __attribute__((packed, aligned(1))) 63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_STRUCT 65:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) 66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_UNION 68:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_UNION union __attribute__((packed, aligned(1))) 69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32 /* deprecated */ 71:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 72:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 73:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 74:Drivers/CMSIS/Include/cmsis_gcc.h **** struct __attribute__((packed)) T_UINT32 { uint32_t v; }; 75:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 76:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) 77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_WRITE 79:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 80:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 81:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 82:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; 83:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 84:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))- 85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_READ 87:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 88:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 89:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 90:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; 91:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 92:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(add 93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_WRITE 95:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 96:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 97:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 98:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; 99:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 100:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))- 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_READ 103:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 104:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 105:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 106:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; 107:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 108:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(add 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ALIGNED 111:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ALIGNED(x) __attribute__((aligned(x))) 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif ARM GAS /tmp/ccBZCjHD.s page 17 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __RESTRICT 114:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __RESTRICT __restrict 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 116:Drivers/CMSIS/Include/cmsis_gcc.h **** 117:Drivers/CMSIS/Include/cmsis_gcc.h **** 118:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */ 119:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface 120:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions 121:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ 122:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 123:Drivers/CMSIS/Include/cmsis_gcc.h **** 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 125:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts 126:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR. 127:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. 128:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 129:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void) 130:Drivers/CMSIS/Include/cmsis_gcc.h **** { 131:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory"); 132:Drivers/CMSIS/Include/cmsis_gcc.h **** } 133:Drivers/CMSIS/Include/cmsis_gcc.h **** 134:Drivers/CMSIS/Include/cmsis_gcc.h **** 135:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 136:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts 137:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR. 138:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. 139:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 140:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void) 253 .loc 2 140 27 view .LVU78 254 .LBB9: 141:Drivers/CMSIS/Include/cmsis_gcc.h **** { 142:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory"); 255 .loc 2 142 3 view .LVU79 256 .syntax unified 257 @ 142 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 258 0000 72B6 cpsid i 259 @ 0 "" 2 260 .thumb 261 .syntax unified 262 .L6: 263 .LBE9: 264 .LBE8: 552:Core/Src/main.c **** while (1) 265 .loc 1 552 3 view .LVU80 553:Core/Src/main.c **** { 554:Core/Src/main.c **** } 266 .loc 1 554 3 view .LVU81 552:Core/Src/main.c **** while (1) 267 .loc 1 552 9 view .LVU82 268 0002 FEE7 b .L6 269 .cfi_endproc 270 .LFE139: 272 .section .text.MX_CAN_Init,"ax",%progbits 273 .align 1 274 .syntax unified 275 .thumb 276 .thumb_func ARM GAS /tmp/ccBZCjHD.s page 18 278 MX_CAN_Init: 279 .LFB132: 178:Core/Src/main.c **** 280 .loc 1 178 1 view -0 281 .cfi_startproc 282 @ args = 0, pretend = 0, frame = 0 283 @ frame_needed = 0, uses_anonymous_args = 0 284 0000 08B5 push {r3, lr} 285 .cfi_def_cfa_offset 8 286 .cfi_offset 3, -8 287 .cfi_offset 14, -4 187:Core/Src/main.c **** hcan.Init.Prescaler = 16; 288 .loc 1 187 3 view .LVU84 187:Core/Src/main.c **** hcan.Init.Prescaler = 16; 289 .loc 1 187 17 is_stmt 0 view .LVU85 290 0002 0B48 ldr r0, .L11 291 0004 0B4B ldr r3, .L11+4 292 0006 0360 str r3, [r0] 188:Core/Src/main.c **** hcan.Init.Mode = CAN_MODE_NORMAL; 293 .loc 1 188 3 is_stmt 1 view .LVU86 188:Core/Src/main.c **** hcan.Init.Mode = CAN_MODE_NORMAL; 294 .loc 1 188 23 is_stmt 0 view .LVU87 295 0008 1023 movs r3, #16 296 000a 4360 str r3, [r0, #4] 189:Core/Src/main.c **** hcan.Init.SyncJumpWidth = CAN_SJW_1TQ; 297 .loc 1 189 3 is_stmt 1 view .LVU88 189:Core/Src/main.c **** hcan.Init.SyncJumpWidth = CAN_SJW_1TQ; 298 .loc 1 189 18 is_stmt 0 view .LVU89 299 000c 0023 movs r3, #0 300 000e 8360 str r3, [r0, #8] 190:Core/Src/main.c **** hcan.Init.TimeSeg1 = CAN_BS1_1TQ; 301 .loc 1 190 3 is_stmt 1 view .LVU90 190:Core/Src/main.c **** hcan.Init.TimeSeg1 = CAN_BS1_1TQ; 302 .loc 1 190 27 is_stmt 0 view .LVU91 303 0010 C360 str r3, [r0, #12] 191:Core/Src/main.c **** hcan.Init.TimeSeg2 = CAN_BS2_1TQ; 304 .loc 1 191 3 is_stmt 1 view .LVU92 191:Core/Src/main.c **** hcan.Init.TimeSeg2 = CAN_BS2_1TQ; 305 .loc 1 191 22 is_stmt 0 view .LVU93 306 0012 0361 str r3, [r0, #16] 192:Core/Src/main.c **** hcan.Init.TimeTriggeredMode = DISABLE; 307 .loc 1 192 3 is_stmt 1 view .LVU94 192:Core/Src/main.c **** hcan.Init.TimeTriggeredMode = DISABLE; 308 .loc 1 192 22 is_stmt 0 view .LVU95 309 0014 4361 str r3, [r0, #20] 193:Core/Src/main.c **** hcan.Init.AutoBusOff = DISABLE; 310 .loc 1 193 3 is_stmt 1 view .LVU96 193:Core/Src/main.c **** hcan.Init.AutoBusOff = DISABLE; 311 .loc 1 193 31 is_stmt 0 view .LVU97 312 0016 0376 strb r3, [r0, #24] 194:Core/Src/main.c **** hcan.Init.AutoWakeUp = DISABLE; 313 .loc 1 194 3 is_stmt 1 view .LVU98 194:Core/Src/main.c **** hcan.Init.AutoWakeUp = DISABLE; 314 .loc 1 194 24 is_stmt 0 view .LVU99 315 0018 4376 strb r3, [r0, #25] 195:Core/Src/main.c **** hcan.Init.AutoRetransmission = DISABLE; 316 .loc 1 195 3 is_stmt 1 view .LVU100 ARM GAS /tmp/ccBZCjHD.s page 19 195:Core/Src/main.c **** hcan.Init.AutoRetransmission = DISABLE; 317 .loc 1 195 24 is_stmt 0 view .LVU101 318 001a 8376 strb r3, [r0, #26] 196:Core/Src/main.c **** hcan.Init.ReceiveFifoLocked = DISABLE; 319 .loc 1 196 3 is_stmt 1 view .LVU102 196:Core/Src/main.c **** hcan.Init.ReceiveFifoLocked = DISABLE; 320 .loc 1 196 32 is_stmt 0 view .LVU103 321 001c C376 strb r3, [r0, #27] 197:Core/Src/main.c **** hcan.Init.TransmitFifoPriority = DISABLE; 322 .loc 1 197 3 is_stmt 1 view .LVU104 197:Core/Src/main.c **** hcan.Init.TransmitFifoPriority = DISABLE; 323 .loc 1 197 31 is_stmt 0 view .LVU105 324 001e 0377 strb r3, [r0, #28] 198:Core/Src/main.c **** if (HAL_CAN_Init(&hcan) != HAL_OK) 325 .loc 1 198 3 is_stmt 1 view .LVU106 198:Core/Src/main.c **** if (HAL_CAN_Init(&hcan) != HAL_OK) 326 .loc 1 198 34 is_stmt 0 view .LVU107 327 0020 4377 strb r3, [r0, #29] 199:Core/Src/main.c **** { 328 .loc 1 199 3 is_stmt 1 view .LVU108 199:Core/Src/main.c **** { 329 .loc 1 199 7 is_stmt 0 view .LVU109 330 0022 FFF7FEFF bl HAL_CAN_Init 331 .LVL8: 199:Core/Src/main.c **** { 332 .loc 1 199 6 discriminator 1 view .LVU110 333 0026 00B9 cbnz r0, .L10 207:Core/Src/main.c **** 334 .loc 1 207 1 view .LVU111 335 0028 08BD pop {r3, pc} 336 .L10: 201:Core/Src/main.c **** } 337 .loc 1 201 5 is_stmt 1 view .LVU112 338 002a FFF7FEFF bl Error_Handler 339 .LVL9: 340 .L12: 341 002e 00BF .align 2 342 .L11: 343 0030 00000000 .word hcan 344 0034 00640040 .word 1073767424 345 .cfi_endproc 346 .LFE132: 348 .section .text.MX_I2C1_Init,"ax",%progbits 349 .align 1 350 .syntax unified 351 .thumb 352 .thumb_func 354 MX_I2C1_Init: 355 .LFB133: 215:Core/Src/main.c **** 356 .loc 1 215 1 view -0 357 .cfi_startproc 358 @ args = 0, pretend = 0, frame = 0 359 @ frame_needed = 0, uses_anonymous_args = 0 360 0000 08B5 push {r3, lr} 361 .cfi_def_cfa_offset 8 362 .cfi_offset 3, -8 ARM GAS /tmp/ccBZCjHD.s page 20 363 .cfi_offset 14, -4 224:Core/Src/main.c **** hi2c1.Init.Timing = 0x2000090E; 364 .loc 1 224 3 view .LVU114 224:Core/Src/main.c **** hi2c1.Init.Timing = 0x2000090E; 365 .loc 1 224 18 is_stmt 0 view .LVU115 366 0002 1148 ldr r0, .L21 367 0004 114B ldr r3, .L21+4 368 0006 0360 str r3, [r0] 225:Core/Src/main.c **** hi2c1.Init.OwnAddress1 = 0; 369 .loc 1 225 3 is_stmt 1 view .LVU116 225:Core/Src/main.c **** hi2c1.Init.OwnAddress1 = 0; 370 .loc 1 225 21 is_stmt 0 view .LVU117 371 0008 114B ldr r3, .L21+8 372 000a 4360 str r3, [r0, #4] 226:Core/Src/main.c **** hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; 373 .loc 1 226 3 is_stmt 1 view .LVU118 226:Core/Src/main.c **** hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; 374 .loc 1 226 26 is_stmt 0 view .LVU119 375 000c 0023 movs r3, #0 376 000e 8360 str r3, [r0, #8] 227:Core/Src/main.c **** hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; 377 .loc 1 227 3 is_stmt 1 view .LVU120 227:Core/Src/main.c **** hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; 378 .loc 1 227 29 is_stmt 0 view .LVU121 379 0010 0122 movs r2, #1 380 0012 C260 str r2, [r0, #12] 228:Core/Src/main.c **** hi2c1.Init.OwnAddress2 = 0; 381 .loc 1 228 3 is_stmt 1 view .LVU122 228:Core/Src/main.c **** hi2c1.Init.OwnAddress2 = 0; 382 .loc 1 228 30 is_stmt 0 view .LVU123 383 0014 0361 str r3, [r0, #16] 229:Core/Src/main.c **** hi2c1.Init.OwnAddress2Masks = I2C_OA2_NOMASK; 384 .loc 1 229 3 is_stmt 1 view .LVU124 229:Core/Src/main.c **** hi2c1.Init.OwnAddress2Masks = I2C_OA2_NOMASK; 385 .loc 1 229 26 is_stmt 0 view .LVU125 386 0016 4361 str r3, [r0, #20] 230:Core/Src/main.c **** hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; 387 .loc 1 230 3 is_stmt 1 view .LVU126 230:Core/Src/main.c **** hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; 388 .loc 1 230 31 is_stmt 0 view .LVU127 389 0018 8361 str r3, [r0, #24] 231:Core/Src/main.c **** hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; 390 .loc 1 231 3 is_stmt 1 view .LVU128 231:Core/Src/main.c **** hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; 391 .loc 1 231 30 is_stmt 0 view .LVU129 392 001a C361 str r3, [r0, #28] 232:Core/Src/main.c **** if (HAL_I2C_Init(&hi2c1) != HAL_OK) 393 .loc 1 232 3 is_stmt 1 view .LVU130 232:Core/Src/main.c **** if (HAL_I2C_Init(&hi2c1) != HAL_OK) 394 .loc 1 232 28 is_stmt 0 view .LVU131 395 001c 0362 str r3, [r0, #32] 233:Core/Src/main.c **** { 396 .loc 1 233 3 is_stmt 1 view .LVU132 233:Core/Src/main.c **** { 397 .loc 1 233 7 is_stmt 0 view .LVU133 398 001e FFF7FEFF bl HAL_I2C_Init 399 .LVL10: ARM GAS /tmp/ccBZCjHD.s page 21 233:Core/Src/main.c **** { 400 .loc 1 233 6 discriminator 1 view .LVU134 401 0022 50B9 cbnz r0, .L18 240:Core/Src/main.c **** { 402 .loc 1 240 3 is_stmt 1 view .LVU135 240:Core/Src/main.c **** { 403 .loc 1 240 7 is_stmt 0 view .LVU136 404 0024 0021 movs r1, #0 405 0026 0848 ldr r0, .L21 406 0028 FFF7FEFF bl HAL_I2CEx_ConfigAnalogFilter 407 .LVL11: 240:Core/Src/main.c **** { 408 .loc 1 240 6 discriminator 1 view .LVU137 409 002c 38B9 cbnz r0, .L19 247:Core/Src/main.c **** { 410 .loc 1 247 3 is_stmt 1 view .LVU138 247:Core/Src/main.c **** { 411 .loc 1 247 7 is_stmt 0 view .LVU139 412 002e 0021 movs r1, #0 413 0030 0548 ldr r0, .L21 414 0032 FFF7FEFF bl HAL_I2CEx_ConfigDigitalFilter 415 .LVL12: 247:Core/Src/main.c **** { 416 .loc 1 247 6 discriminator 1 view .LVU140 417 0036 20B9 cbnz r0, .L20 255:Core/Src/main.c **** 418 .loc 1 255 1 view .LVU141 419 0038 08BD pop {r3, pc} 420 .L18: 235:Core/Src/main.c **** } 421 .loc 1 235 5 is_stmt 1 view .LVU142 422 003a FFF7FEFF bl Error_Handler 423 .LVL13: 424 .L19: 242:Core/Src/main.c **** } 425 .loc 1 242 5 view .LVU143 426 003e FFF7FEFF bl Error_Handler 427 .LVL14: 428 .L20: 249:Core/Src/main.c **** } 429 .loc 1 249 5 view .LVU144 430 0042 FFF7FEFF bl Error_Handler 431 .LVL15: 432 .L22: 433 0046 00BF .align 2 434 .L21: 435 0048 00000000 .word hi2c1 436 004c 00540040 .word 1073763328 437 0050 0E090020 .word 536873230 438 .cfi_endproc 439 .LFE133: 441 .section .text.MX_SPI1_Init,"ax",%progbits 442 .align 1 443 .syntax unified 444 .thumb 445 .thumb_func 447 MX_SPI1_Init: ARM GAS /tmp/ccBZCjHD.s page 22 448 .LFB134: 263:Core/Src/main.c **** 449 .loc 1 263 1 view -0 450 .cfi_startproc 451 @ args = 0, pretend = 0, frame = 0 452 @ frame_needed = 0, uses_anonymous_args = 0 453 0000 08B5 push {r3, lr} 454 .cfi_def_cfa_offset 8 455 .cfi_offset 3, -8 456 .cfi_offset 14, -4 273:Core/Src/main.c **** hspi1.Init.Mode = SPI_MODE_MASTER; 457 .loc 1 273 3 view .LVU146 273:Core/Src/main.c **** hspi1.Init.Mode = SPI_MODE_MASTER; 458 .loc 1 273 18 is_stmt 0 view .LVU147 459 0002 0E48 ldr r0, .L27 460 0004 0E4B ldr r3, .L27+4 461 0006 0360 str r3, [r0] 274:Core/Src/main.c **** hspi1.Init.Direction = SPI_DIRECTION_2LINES; 462 .loc 1 274 3 is_stmt 1 view .LVU148 274:Core/Src/main.c **** hspi1.Init.Direction = SPI_DIRECTION_2LINES; 463 .loc 1 274 19 is_stmt 0 view .LVU149 464 0008 4FF48273 mov r3, #260 465 000c 4360 str r3, [r0, #4] 275:Core/Src/main.c **** hspi1.Init.DataSize = SPI_DATASIZE_4BIT; 466 .loc 1 275 3 is_stmt 1 view .LVU150 275:Core/Src/main.c **** hspi1.Init.DataSize = SPI_DATASIZE_4BIT; 467 .loc 1 275 24 is_stmt 0 view .LVU151 468 000e 0023 movs r3, #0 469 0010 8360 str r3, [r0, #8] 276:Core/Src/main.c **** hspi1.Init.CLKPolarity = SPI_POLARITY_LOW; 470 .loc 1 276 3 is_stmt 1 view .LVU152 276:Core/Src/main.c **** hspi1.Init.CLKPolarity = SPI_POLARITY_LOW; 471 .loc 1 276 23 is_stmt 0 view .LVU153 472 0012 4FF44072 mov r2, #768 473 0016 C260 str r2, [r0, #12] 277:Core/Src/main.c **** hspi1.Init.CLKPhase = SPI_PHASE_1EDGE; 474 .loc 1 277 3 is_stmt 1 view .LVU154 277:Core/Src/main.c **** hspi1.Init.CLKPhase = SPI_PHASE_1EDGE; 475 .loc 1 277 26 is_stmt 0 view .LVU155 476 0018 0361 str r3, [r0, #16] 278:Core/Src/main.c **** hspi1.Init.NSS = SPI_NSS_HARD_INPUT; 477 .loc 1 278 3 is_stmt 1 view .LVU156 278:Core/Src/main.c **** hspi1.Init.NSS = SPI_NSS_HARD_INPUT; 478 .loc 1 278 23 is_stmt 0 view .LVU157 479 001a 4361 str r3, [r0, #20] 279:Core/Src/main.c **** hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; 480 .loc 1 279 3 is_stmt 1 view .LVU158 279:Core/Src/main.c **** hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; 481 .loc 1 279 18 is_stmt 0 view .LVU159 482 001c 8361 str r3, [r0, #24] 280:Core/Src/main.c **** hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; 483 .loc 1 280 3 is_stmt 1 view .LVU160 280:Core/Src/main.c **** hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; 484 .loc 1 280 32 is_stmt 0 view .LVU161 485 001e C361 str r3, [r0, #28] 281:Core/Src/main.c **** hspi1.Init.TIMode = SPI_TIMODE_DISABLE; 486 .loc 1 281 3 is_stmt 1 view .LVU162 ARM GAS /tmp/ccBZCjHD.s page 23 281:Core/Src/main.c **** hspi1.Init.TIMode = SPI_TIMODE_DISABLE; 487 .loc 1 281 23 is_stmt 0 view .LVU163 488 0020 0362 str r3, [r0, #32] 282:Core/Src/main.c **** hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; 489 .loc 1 282 3 is_stmt 1 view .LVU164 282:Core/Src/main.c **** hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; 490 .loc 1 282 21 is_stmt 0 view .LVU165 491 0022 4362 str r3, [r0, #36] 283:Core/Src/main.c **** hspi1.Init.CRCPolynomial = 7; 492 .loc 1 283 3 is_stmt 1 view .LVU166 283:Core/Src/main.c **** hspi1.Init.CRCPolynomial = 7; 493 .loc 1 283 29 is_stmt 0 view .LVU167 494 0024 8362 str r3, [r0, #40] 284:Core/Src/main.c **** hspi1.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE; 495 .loc 1 284 3 is_stmt 1 view .LVU168 284:Core/Src/main.c **** hspi1.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE; 496 .loc 1 284 28 is_stmt 0 view .LVU169 497 0026 0722 movs r2, #7 498 0028 C262 str r2, [r0, #44] 285:Core/Src/main.c **** hspi1.Init.NSSPMode = SPI_NSS_PULSE_ENABLE; 499 .loc 1 285 3 is_stmt 1 view .LVU170 285:Core/Src/main.c **** hspi1.Init.NSSPMode = SPI_NSS_PULSE_ENABLE; 500 .loc 1 285 24 is_stmt 0 view .LVU171 501 002a 0363 str r3, [r0, #48] 286:Core/Src/main.c **** if (HAL_SPI_Init(&hspi1) != HAL_OK) 502 .loc 1 286 3 is_stmt 1 view .LVU172 286:Core/Src/main.c **** if (HAL_SPI_Init(&hspi1) != HAL_OK) 503 .loc 1 286 23 is_stmt 0 view .LVU173 504 002c 0823 movs r3, #8 505 002e 4363 str r3, [r0, #52] 287:Core/Src/main.c **** { 506 .loc 1 287 3 is_stmt 1 view .LVU174 287:Core/Src/main.c **** { 507 .loc 1 287 7 is_stmt 0 view .LVU175 508 0030 FFF7FEFF bl HAL_SPI_Init 509 .LVL16: 287:Core/Src/main.c **** { 510 .loc 1 287 6 discriminator 1 view .LVU176 511 0034 00B9 cbnz r0, .L26 295:Core/Src/main.c **** 512 .loc 1 295 1 view .LVU177 513 0036 08BD pop {r3, pc} 514 .L26: 289:Core/Src/main.c **** } 515 .loc 1 289 5 is_stmt 1 view .LVU178 516 0038 FFF7FEFF bl Error_Handler 517 .LVL17: 518 .L28: 519 .align 2 520 .L27: 521 003c 00000000 .word hspi1 522 0040 00300140 .word 1073819648 523 .cfi_endproc 524 .LFE134: 526 .section .text.MX_TIM15_Init,"ax",%progbits 527 .align 1 528 .syntax unified ARM GAS /tmp/ccBZCjHD.s page 24 529 .thumb 530 .thumb_func 532 MX_TIM15_Init: 533 .LFB136: 373:Core/Src/main.c **** 534 .loc 1 373 1 view -0 535 .cfi_startproc 536 @ args = 0, pretend = 0, frame = 88 537 @ frame_needed = 0, uses_anonymous_args = 0 538 0000 10B5 push {r4, lr} 539 .cfi_def_cfa_offset 8 540 .cfi_offset 4, -8 541 .cfi_offset 14, -4 542 0002 96B0 sub sp, sp, #88 543 .cfi_def_cfa_offset 96 379:Core/Src/main.c **** TIM_OC_InitTypeDef sConfigOC = {0}; 544 .loc 1 379 3 view .LVU180 379:Core/Src/main.c **** TIM_OC_InitTypeDef sConfigOC = {0}; 545 .loc 1 379 27 is_stmt 0 view .LVU181 546 0004 0024 movs r4, #0 547 0006 1394 str r4, [sp, #76] 548 0008 1494 str r4, [sp, #80] 549 000a 1594 str r4, [sp, #84] 380:Core/Src/main.c **** TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0}; 550 .loc 1 380 3 is_stmt 1 view .LVU182 380:Core/Src/main.c **** TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0}; 551 .loc 1 380 22 is_stmt 0 view .LVU183 552 000c 0C94 str r4, [sp, #48] 553 000e 0D94 str r4, [sp, #52] 554 0010 0E94 str r4, [sp, #56] 555 0012 0F94 str r4, [sp, #60] 556 0014 1094 str r4, [sp, #64] 557 0016 1194 str r4, [sp, #68] 558 0018 1294 str r4, [sp, #72] 381:Core/Src/main.c **** 559 .loc 1 381 3 is_stmt 1 view .LVU184 381:Core/Src/main.c **** 560 .loc 1 381 34 is_stmt 0 view .LVU185 561 001a 2C22 movs r2, #44 562 001c 2146 mov r1, r4 563 001e 01A8 add r0, sp, #4 564 0020 FFF7FEFF bl memset 565 .LVL18: 386:Core/Src/main.c **** htim15.Init.Prescaler = 0; 566 .loc 1 386 3 is_stmt 1 view .LVU186 386:Core/Src/main.c **** htim15.Init.Prescaler = 0; 567 .loc 1 386 19 is_stmt 0 view .LVU187 568 0024 2548 ldr r0, .L41 569 0026 264B ldr r3, .L41+4 570 0028 0360 str r3, [r0] 387:Core/Src/main.c **** htim15.Init.CounterMode = TIM_COUNTERMODE_UP; 571 .loc 1 387 3 is_stmt 1 view .LVU188 387:Core/Src/main.c **** htim15.Init.CounterMode = TIM_COUNTERMODE_UP; 572 .loc 1 387 25 is_stmt 0 view .LVU189 573 002a 4460 str r4, [r0, #4] 388:Core/Src/main.c **** htim15.Init.Period = 65535; 574 .loc 1 388 3 is_stmt 1 view .LVU190 ARM GAS /tmp/ccBZCjHD.s page 25 388:Core/Src/main.c **** htim15.Init.Period = 65535; 575 .loc 1 388 27 is_stmt 0 view .LVU191 576 002c 8460 str r4, [r0, #8] 389:Core/Src/main.c **** htim15.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 577 .loc 1 389 3 is_stmt 1 view .LVU192 389:Core/Src/main.c **** htim15.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 578 .loc 1 389 22 is_stmt 0 view .LVU193 579 002e 4FF6FF73 movw r3, #65535 580 0032 C360 str r3, [r0, #12] 390:Core/Src/main.c **** htim15.Init.RepetitionCounter = 0; 581 .loc 1 390 3 is_stmt 1 view .LVU194 390:Core/Src/main.c **** htim15.Init.RepetitionCounter = 0; 582 .loc 1 390 29 is_stmt 0 view .LVU195 583 0034 0461 str r4, [r0, #16] 391:Core/Src/main.c **** htim15.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 584 .loc 1 391 3 is_stmt 1 view .LVU196 391:Core/Src/main.c **** htim15.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 585 .loc 1 391 33 is_stmt 0 view .LVU197 586 0036 4461 str r4, [r0, #20] 392:Core/Src/main.c **** if (HAL_TIM_PWM_Init(&htim15) != HAL_OK) 587 .loc 1 392 3 is_stmt 1 view .LVU198 392:Core/Src/main.c **** if (HAL_TIM_PWM_Init(&htim15) != HAL_OK) 588 .loc 1 392 33 is_stmt 0 view .LVU199 589 0038 8461 str r4, [r0, #24] 393:Core/Src/main.c **** { 590 .loc 1 393 3 is_stmt 1 view .LVU200 393:Core/Src/main.c **** { 591 .loc 1 393 7 is_stmt 0 view .LVU201 592 003a FFF7FEFF bl HAL_TIM_PWM_Init 593 .LVL19: 393:Core/Src/main.c **** { 594 .loc 1 393 6 discriminator 1 view .LVU202 595 003e 0028 cmp r0, #0 596 0040 31D1 bne .L36 397:Core/Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 597 .loc 1 397 3 is_stmt 1 view .LVU203 397:Core/Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 598 .loc 1 397 37 is_stmt 0 view .LVU204 599 0042 0023 movs r3, #0 600 0044 1393 str r3, [sp, #76] 398:Core/Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim15, &sMasterConfig) != HAL_OK) 601 .loc 1 398 3 is_stmt 1 view .LVU205 398:Core/Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim15, &sMasterConfig) != HAL_OK) 602 .loc 1 398 33 is_stmt 0 view .LVU206 603 0046 1593 str r3, [sp, #84] 399:Core/Src/main.c **** { 604 .loc 1 399 3 is_stmt 1 view .LVU207 399:Core/Src/main.c **** { 605 .loc 1 399 7 is_stmt 0 view .LVU208 606 0048 13A9 add r1, sp, #76 607 004a 1C48 ldr r0, .L41 608 004c FFF7FEFF bl HAL_TIMEx_MasterConfigSynchronization 609 .LVL20: 399:Core/Src/main.c **** { 610 .loc 1 399 6 discriminator 1 view .LVU209 611 0050 0028 cmp r0, #0 612 0052 2AD1 bne .L37 ARM GAS /tmp/ccBZCjHD.s page 26 403:Core/Src/main.c **** sConfigOC.Pulse = 0; 613 .loc 1 403 3 is_stmt 1 view .LVU210 403:Core/Src/main.c **** sConfigOC.Pulse = 0; 614 .loc 1 403 20 is_stmt 0 view .LVU211 615 0054 6023 movs r3, #96 616 0056 0C93 str r3, [sp, #48] 404:Core/Src/main.c **** sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 617 .loc 1 404 3 is_stmt 1 view .LVU212 404:Core/Src/main.c **** sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 618 .loc 1 404 19 is_stmt 0 view .LVU213 619 0058 0022 movs r2, #0 620 005a 0D92 str r2, [sp, #52] 405:Core/Src/main.c **** sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH; 621 .loc 1 405 3 is_stmt 1 view .LVU214 405:Core/Src/main.c **** sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH; 622 .loc 1 405 24 is_stmt 0 view .LVU215 623 005c 0E92 str r2, [sp, #56] 406:Core/Src/main.c **** sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 624 .loc 1 406 3 is_stmt 1 view .LVU216 406:Core/Src/main.c **** sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 625 .loc 1 406 25 is_stmt 0 view .LVU217 626 005e 0F92 str r2, [sp, #60] 407:Core/Src/main.c **** sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET; 627 .loc 1 407 3 is_stmt 1 view .LVU218 407:Core/Src/main.c **** sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET; 628 .loc 1 407 24 is_stmt 0 view .LVU219 629 0060 1092 str r2, [sp, #64] 408:Core/Src/main.c **** sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET; 630 .loc 1 408 3 is_stmt 1 view .LVU220 408:Core/Src/main.c **** sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET; 631 .loc 1 408 25 is_stmt 0 view .LVU221 632 0062 1192 str r2, [sp, #68] 409:Core/Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim15, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) 633 .loc 1 409 3 is_stmt 1 view .LVU222 409:Core/Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim15, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) 634 .loc 1 409 26 is_stmt 0 view .LVU223 635 0064 1292 str r2, [sp, #72] 410:Core/Src/main.c **** { 636 .loc 1 410 3 is_stmt 1 view .LVU224 410:Core/Src/main.c **** { 637 .loc 1 410 7 is_stmt 0 view .LVU225 638 0066 0CA9 add r1, sp, #48 639 0068 1448 ldr r0, .L41 640 006a FFF7FEFF bl HAL_TIM_PWM_ConfigChannel 641 .LVL21: 410:Core/Src/main.c **** { 642 .loc 1 410 6 discriminator 1 view .LVU226 643 006e F0B9 cbnz r0, .L38 414:Core/Src/main.c **** { 644 .loc 1 414 3 is_stmt 1 view .LVU227 414:Core/Src/main.c **** { 645 .loc 1 414 7 is_stmt 0 view .LVU228 646 0070 0422 movs r2, #4 647 0072 0CA9 add r1, sp, #48 648 0074 1148 ldr r0, .L41 649 0076 FFF7FEFF bl HAL_TIM_PWM_ConfigChannel 650 .LVL22: ARM GAS /tmp/ccBZCjHD.s page 27 414:Core/Src/main.c **** { 651 .loc 1 414 6 discriminator 1 view .LVU229 652 007a D0B9 cbnz r0, .L39 418:Core/Src/main.c **** sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE; 653 .loc 1 418 3 is_stmt 1 view .LVU230 418:Core/Src/main.c **** sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE; 654 .loc 1 418 40 is_stmt 0 view .LVU231 655 007c 0023 movs r3, #0 656 007e 0193 str r3, [sp, #4] 419:Core/Src/main.c **** sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF; 657 .loc 1 419 3 is_stmt 1 view .LVU232 419:Core/Src/main.c **** sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF; 658 .loc 1 419 41 is_stmt 0 view .LVU233 659 0080 0293 str r3, [sp, #8] 420:Core/Src/main.c **** sBreakDeadTimeConfig.DeadTime = 0; 660 .loc 1 420 3 is_stmt 1 view .LVU234 420:Core/Src/main.c **** sBreakDeadTimeConfig.DeadTime = 0; 661 .loc 1 420 34 is_stmt 0 view .LVU235 662 0082 0393 str r3, [sp, #12] 421:Core/Src/main.c **** sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE; 663 .loc 1 421 3 is_stmt 1 view .LVU236 421:Core/Src/main.c **** sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE; 664 .loc 1 421 33 is_stmt 0 view .LVU237 665 0084 0493 str r3, [sp, #16] 422:Core/Src/main.c **** sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH; 666 .loc 1 422 3 is_stmt 1 view .LVU238 422:Core/Src/main.c **** sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH; 667 .loc 1 422 35 is_stmt 0 view .LVU239 668 0086 0593 str r3, [sp, #20] 423:Core/Src/main.c **** sBreakDeadTimeConfig.BreakFilter = 0; 669 .loc 1 423 3 is_stmt 1 view .LVU240 423:Core/Src/main.c **** sBreakDeadTimeConfig.BreakFilter = 0; 670 .loc 1 423 38 is_stmt 0 view .LVU241 671 0088 4FF40052 mov r2, #8192 672 008c 0692 str r2, [sp, #24] 424:Core/Src/main.c **** sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE; 673 .loc 1 424 3 is_stmt 1 view .LVU242 424:Core/Src/main.c **** sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE; 674 .loc 1 424 36 is_stmt 0 view .LVU243 675 008e 0793 str r3, [sp, #28] 425:Core/Src/main.c **** if (HAL_TIMEx_ConfigBreakDeadTime(&htim15, &sBreakDeadTimeConfig) != HAL_OK) 676 .loc 1 425 3 is_stmt 1 view .LVU244 425:Core/Src/main.c **** if (HAL_TIMEx_ConfigBreakDeadTime(&htim15, &sBreakDeadTimeConfig) != HAL_OK) 677 .loc 1 425 40 is_stmt 0 view .LVU245 678 0090 0B93 str r3, [sp, #44] 426:Core/Src/main.c **** { 679 .loc 1 426 3 is_stmt 1 view .LVU246 426:Core/Src/main.c **** { 680 .loc 1 426 7 is_stmt 0 view .LVU247 681 0092 01A9 add r1, sp, #4 682 0094 0948 ldr r0, .L41 683 0096 FFF7FEFF bl HAL_TIMEx_ConfigBreakDeadTime 684 .LVL23: 426:Core/Src/main.c **** { 685 .loc 1 426 6 discriminator 1 view .LVU248 686 009a 60B9 cbnz r0, .L40 433:Core/Src/main.c **** ARM GAS /tmp/ccBZCjHD.s page 28 687 .loc 1 433 3 is_stmt 1 view .LVU249 688 009c 0748 ldr r0, .L41 689 009e FFF7FEFF bl HAL_TIM_MspPostInit 690 .LVL24: 435:Core/Src/main.c **** 691 .loc 1 435 1 is_stmt 0 view .LVU250 692 00a2 16B0 add sp, sp, #88 693 .cfi_remember_state 694 .cfi_def_cfa_offset 8 695 @ sp needed 696 00a4 10BD pop {r4, pc} 697 .L36: 698 .cfi_restore_state 395:Core/Src/main.c **** } 699 .loc 1 395 5 is_stmt 1 view .LVU251 700 00a6 FFF7FEFF bl Error_Handler 701 .LVL25: 702 .L37: 401:Core/Src/main.c **** } 703 .loc 1 401 5 view .LVU252 704 00aa FFF7FEFF bl Error_Handler 705 .LVL26: 706 .L38: 412:Core/Src/main.c **** } 707 .loc 1 412 5 view .LVU253 708 00ae FFF7FEFF bl Error_Handler 709 .LVL27: 710 .L39: 416:Core/Src/main.c **** } 711 .loc 1 416 5 view .LVU254 712 00b2 FFF7FEFF bl Error_Handler 713 .LVL28: 714 .L40: 428:Core/Src/main.c **** } 715 .loc 1 428 5 view .LVU255 716 00b6 FFF7FEFF bl Error_Handler 717 .LVL29: 718 .L42: 719 00ba 00BF .align 2 720 .L41: 721 00bc 00000000 .word htim15 722 00c0 00400140 .word 1073823744 723 .cfi_endproc 724 .LFE136: 726 .section .text.MX_USART1_UART_Init,"ax",%progbits 727 .align 1 728 .syntax unified 729 .thumb 730 .thumb_func 732 MX_USART1_UART_Init: 733 .LFB137: 443:Core/Src/main.c **** 734 .loc 1 443 1 view -0 735 .cfi_startproc 736 @ args = 0, pretend = 0, frame = 0 737 @ frame_needed = 0, uses_anonymous_args = 0 738 0000 08B5 push {r3, lr} ARM GAS /tmp/ccBZCjHD.s page 29 739 .cfi_def_cfa_offset 8 740 .cfi_offset 3, -8 741 .cfi_offset 14, -4 452:Core/Src/main.c **** huart1.Init.BaudRate = 38400; 742 .loc 1 452 3 view .LVU257 452:Core/Src/main.c **** huart1.Init.BaudRate = 38400; 743 .loc 1 452 19 is_stmt 0 view .LVU258 744 0002 0B48 ldr r0, .L47 745 0004 0B4B ldr r3, .L47+4 746 0006 0360 str r3, [r0] 453:Core/Src/main.c **** huart1.Init.WordLength = UART_WORDLENGTH_8B; 747 .loc 1 453 3 is_stmt 1 view .LVU259 453:Core/Src/main.c **** huart1.Init.WordLength = UART_WORDLENGTH_8B; 748 .loc 1 453 24 is_stmt 0 view .LVU260 749 0008 4FF41643 mov r3, #38400 750 000c 4360 str r3, [r0, #4] 454:Core/Src/main.c **** huart1.Init.StopBits = UART_STOPBITS_1; 751 .loc 1 454 3 is_stmt 1 view .LVU261 454:Core/Src/main.c **** huart1.Init.StopBits = UART_STOPBITS_1; 752 .loc 1 454 26 is_stmt 0 view .LVU262 753 000e 0023 movs r3, #0 754 0010 8360 str r3, [r0, #8] 455:Core/Src/main.c **** huart1.Init.Parity = UART_PARITY_NONE; 755 .loc 1 455 3 is_stmt 1 view .LVU263 455:Core/Src/main.c **** huart1.Init.Parity = UART_PARITY_NONE; 756 .loc 1 455 24 is_stmt 0 view .LVU264 757 0012 C360 str r3, [r0, #12] 456:Core/Src/main.c **** huart1.Init.Mode = UART_MODE_TX_RX; 758 .loc 1 456 3 is_stmt 1 view .LVU265 456:Core/Src/main.c **** huart1.Init.Mode = UART_MODE_TX_RX; 759 .loc 1 456 22 is_stmt 0 view .LVU266 760 0014 0361 str r3, [r0, #16] 457:Core/Src/main.c **** huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; 761 .loc 1 457 3 is_stmt 1 view .LVU267 457:Core/Src/main.c **** huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; 762 .loc 1 457 20 is_stmt 0 view .LVU268 763 0016 0C22 movs r2, #12 764 0018 4261 str r2, [r0, #20] 458:Core/Src/main.c **** huart1.Init.OverSampling = UART_OVERSAMPLING_16; 765 .loc 1 458 3 is_stmt 1 view .LVU269 458:Core/Src/main.c **** huart1.Init.OverSampling = UART_OVERSAMPLING_16; 766 .loc 1 458 25 is_stmt 0 view .LVU270 767 001a 8361 str r3, [r0, #24] 459:Core/Src/main.c **** huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; 768 .loc 1 459 3 is_stmt 1 view .LVU271 459:Core/Src/main.c **** huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; 769 .loc 1 459 28 is_stmt 0 view .LVU272 770 001c C361 str r3, [r0, #28] 460:Core/Src/main.c **** huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; 771 .loc 1 460 3 is_stmt 1 view .LVU273 460:Core/Src/main.c **** huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; 772 .loc 1 460 30 is_stmt 0 view .LVU274 773 001e 0362 str r3, [r0, #32] 461:Core/Src/main.c **** if (HAL_UART_Init(&huart1) != HAL_OK) 774 .loc 1 461 3 is_stmt 1 view .LVU275 461:Core/Src/main.c **** if (HAL_UART_Init(&huart1) != HAL_OK) 775 .loc 1 461 38 is_stmt 0 view .LVU276 ARM GAS /tmp/ccBZCjHD.s page 30 776 0020 4362 str r3, [r0, #36] 462:Core/Src/main.c **** { 777 .loc 1 462 3 is_stmt 1 view .LVU277 462:Core/Src/main.c **** { 778 .loc 1 462 7 is_stmt 0 view .LVU278 779 0022 FFF7FEFF bl HAL_UART_Init 780 .LVL30: 462:Core/Src/main.c **** { 781 .loc 1 462 6 discriminator 1 view .LVU279 782 0026 00B9 cbnz r0, .L46 470:Core/Src/main.c **** 783 .loc 1 470 1 view .LVU280 784 0028 08BD pop {r3, pc} 785 .L46: 464:Core/Src/main.c **** } 786 .loc 1 464 5 is_stmt 1 view .LVU281 787 002a FFF7FEFF bl Error_Handler 788 .LVL31: 789 .L48: 790 002e 00BF .align 2 791 .L47: 792 0030 00000000 .word huart1 793 0034 00380140 .word 1073821696 794 .cfi_endproc 795 .LFE137: 797 .section .text.MX_TIM1_Init,"ax",%progbits 798 .align 1 799 .syntax unified 800 .thumb 801 .thumb_func 803 MX_TIM1_Init: 804 .LFB135: 303:Core/Src/main.c **** 805 .loc 1 303 1 view -0 806 .cfi_startproc 807 @ args = 0, pretend = 0, frame = 88 808 @ frame_needed = 0, uses_anonymous_args = 0 809 0000 10B5 push {r4, lr} 810 .cfi_def_cfa_offset 8 811 .cfi_offset 4, -8 812 .cfi_offset 14, -4 813 0002 96B0 sub sp, sp, #88 814 .cfi_def_cfa_offset 96 309:Core/Src/main.c **** TIM_OC_InitTypeDef sConfigOC = {0}; 815 .loc 1 309 3 view .LVU283 309:Core/Src/main.c **** TIM_OC_InitTypeDef sConfigOC = {0}; 816 .loc 1 309 27 is_stmt 0 view .LVU284 817 0004 0024 movs r4, #0 818 0006 1394 str r4, [sp, #76] 819 0008 1494 str r4, [sp, #80] 820 000a 1594 str r4, [sp, #84] 310:Core/Src/main.c **** TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0}; 821 .loc 1 310 3 is_stmt 1 view .LVU285 310:Core/Src/main.c **** TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0}; 822 .loc 1 310 22 is_stmt 0 view .LVU286 823 000c 0C94 str r4, [sp, #48] 824 000e 0D94 str r4, [sp, #52] ARM GAS /tmp/ccBZCjHD.s page 31 825 0010 0E94 str r4, [sp, #56] 826 0012 0F94 str r4, [sp, #60] 827 0014 1094 str r4, [sp, #64] 828 0016 1194 str r4, [sp, #68] 829 0018 1294 str r4, [sp, #72] 311:Core/Src/main.c **** 830 .loc 1 311 3 is_stmt 1 view .LVU287 311:Core/Src/main.c **** 831 .loc 1 311 34 is_stmt 0 view .LVU288 832 001a 2C22 movs r2, #44 833 001c 2146 mov r1, r4 834 001e 01A8 add r0, sp, #4 835 0020 FFF7FEFF bl memset 836 .LVL32: 316:Core/Src/main.c **** htim1.Init.Prescaler = 0; 837 .loc 1 316 3 is_stmt 1 view .LVU289 316:Core/Src/main.c **** htim1.Init.Prescaler = 0; 838 .loc 1 316 18 is_stmt 0 view .LVU290 839 0024 2448 ldr r0, .L59 840 0026 254B ldr r3, .L59+4 841 0028 0360 str r3, [r0] 317:Core/Src/main.c **** htim1.Init.CounterMode = TIM_COUNTERMODE_UP; 842 .loc 1 317 3 is_stmt 1 view .LVU291 317:Core/Src/main.c **** htim1.Init.CounterMode = TIM_COUNTERMODE_UP; 843 .loc 1 317 24 is_stmt 0 view .LVU292 844 002a 4460 str r4, [r0, #4] 318:Core/Src/main.c **** htim1.Init.Period = 65535; 845 .loc 1 318 3 is_stmt 1 view .LVU293 318:Core/Src/main.c **** htim1.Init.Period = 65535; 846 .loc 1 318 26 is_stmt 0 view .LVU294 847 002c 8460 str r4, [r0, #8] 319:Core/Src/main.c **** htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 848 .loc 1 319 3 is_stmt 1 view .LVU295 319:Core/Src/main.c **** htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 849 .loc 1 319 21 is_stmt 0 view .LVU296 850 002e 4FF6FF73 movw r3, #65535 851 0032 C360 str r3, [r0, #12] 320:Core/Src/main.c **** htim1.Init.RepetitionCounter = 0; 852 .loc 1 320 3 is_stmt 1 view .LVU297 320:Core/Src/main.c **** htim1.Init.RepetitionCounter = 0; 853 .loc 1 320 28 is_stmt 0 view .LVU298 854 0034 0461 str r4, [r0, #16] 321:Core/Src/main.c **** htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 855 .loc 1 321 3 is_stmt 1 view .LVU299 321:Core/Src/main.c **** htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 856 .loc 1 321 32 is_stmt 0 view .LVU300 857 0036 4461 str r4, [r0, #20] 322:Core/Src/main.c **** if (HAL_TIM_PWM_Init(&htim1) != HAL_OK) 858 .loc 1 322 3 is_stmt 1 view .LVU301 322:Core/Src/main.c **** if (HAL_TIM_PWM_Init(&htim1) != HAL_OK) 859 .loc 1 322 32 is_stmt 0 view .LVU302 860 0038 8461 str r4, [r0, #24] 323:Core/Src/main.c **** { 861 .loc 1 323 3 is_stmt 1 view .LVU303 323:Core/Src/main.c **** { 862 .loc 1 323 7 is_stmt 0 view .LVU304 863 003a FFF7FEFF bl HAL_TIM_PWM_Init ARM GAS /tmp/ccBZCjHD.s page 32 864 .LVL33: 323:Core/Src/main.c **** { 865 .loc 1 323 6 discriminator 1 view .LVU305 866 003e 0028 cmp r0, #0 867 0040 32D1 bne .L55 327:Core/Src/main.c **** sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET; 868 .loc 1 327 3 is_stmt 1 view .LVU306 327:Core/Src/main.c **** sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET; 869 .loc 1 327 37 is_stmt 0 view .LVU307 870 0042 0023 movs r3, #0 871 0044 1393 str r3, [sp, #76] 328:Core/Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 872 .loc 1 328 3 is_stmt 1 view .LVU308 328:Core/Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 873 .loc 1 328 38 is_stmt 0 view .LVU309 874 0046 1493 str r3, [sp, #80] 329:Core/Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK) 875 .loc 1 329 3 is_stmt 1 view .LVU310 329:Core/Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK) 876 .loc 1 329 33 is_stmt 0 view .LVU311 877 0048 1593 str r3, [sp, #84] 330:Core/Src/main.c **** { 878 .loc 1 330 3 is_stmt 1 view .LVU312 330:Core/Src/main.c **** { 879 .loc 1 330 7 is_stmt 0 view .LVU313 880 004a 13A9 add r1, sp, #76 881 004c 1A48 ldr r0, .L59 882 004e FFF7FEFF bl HAL_TIMEx_MasterConfigSynchronization 883 .LVL34: 330:Core/Src/main.c **** { 884 .loc 1 330 6 discriminator 1 view .LVU314 885 0052 0028 cmp r0, #0 886 0054 2AD1 bne .L56 334:Core/Src/main.c **** sConfigOC.Pulse = 0; 887 .loc 1 334 3 is_stmt 1 view .LVU315 334:Core/Src/main.c **** sConfigOC.Pulse = 0; 888 .loc 1 334 20 is_stmt 0 view .LVU316 889 0056 6023 movs r3, #96 890 0058 0C93 str r3, [sp, #48] 335:Core/Src/main.c **** sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 891 .loc 1 335 3 is_stmt 1 view .LVU317 335:Core/Src/main.c **** sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 892 .loc 1 335 19 is_stmt 0 view .LVU318 893 005a 0023 movs r3, #0 894 005c 0D93 str r3, [sp, #52] 336:Core/Src/main.c **** sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH; 895 .loc 1 336 3 is_stmt 1 view .LVU319 336:Core/Src/main.c **** sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH; 896 .loc 1 336 24 is_stmt 0 view .LVU320 897 005e 0E93 str r3, [sp, #56] 337:Core/Src/main.c **** sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 898 .loc 1 337 3 is_stmt 1 view .LVU321 337:Core/Src/main.c **** sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 899 .loc 1 337 25 is_stmt 0 view .LVU322 900 0060 0F93 str r3, [sp, #60] 338:Core/Src/main.c **** sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET; 901 .loc 1 338 3 is_stmt 1 view .LVU323 ARM GAS /tmp/ccBZCjHD.s page 33 338:Core/Src/main.c **** sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET; 902 .loc 1 338 24 is_stmt 0 view .LVU324 903 0062 1093 str r3, [sp, #64] 339:Core/Src/main.c **** sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET; 904 .loc 1 339 3 is_stmt 1 view .LVU325 339:Core/Src/main.c **** sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET; 905 .loc 1 339 25 is_stmt 0 view .LVU326 906 0064 1193 str r3, [sp, #68] 340:Core/Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) 907 .loc 1 340 3 is_stmt 1 view .LVU327 340:Core/Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) 908 .loc 1 340 26 is_stmt 0 view .LVU328 909 0066 1293 str r3, [sp, #72] 341:Core/Src/main.c **** { 910 .loc 1 341 3 is_stmt 1 view .LVU329 341:Core/Src/main.c **** { 911 .loc 1 341 7 is_stmt 0 view .LVU330 912 0068 0822 movs r2, #8 913 006a 0CA9 add r1, sp, #48 914 006c 1248 ldr r0, .L59 915 006e FFF7FEFF bl HAL_TIM_PWM_ConfigChannel 916 .LVL35: 341:Core/Src/main.c **** { 917 .loc 1 341 6 discriminator 1 view .LVU331 918 0072 E8B9 cbnz r0, .L57 345:Core/Src/main.c **** sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE; 919 .loc 1 345 3 is_stmt 1 view .LVU332 345:Core/Src/main.c **** sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE; 920 .loc 1 345 40 is_stmt 0 view .LVU333 921 0074 0023 movs r3, #0 922 0076 0193 str r3, [sp, #4] 346:Core/Src/main.c **** sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF; 923 .loc 1 346 3 is_stmt 1 view .LVU334 346:Core/Src/main.c **** sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF; 924 .loc 1 346 41 is_stmt 0 view .LVU335 925 0078 0293 str r3, [sp, #8] 347:Core/Src/main.c **** sBreakDeadTimeConfig.DeadTime = 0; 926 .loc 1 347 3 is_stmt 1 view .LVU336 347:Core/Src/main.c **** sBreakDeadTimeConfig.DeadTime = 0; 927 .loc 1 347 34 is_stmt 0 view .LVU337 928 007a 0393 str r3, [sp, #12] 348:Core/Src/main.c **** sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE; 929 .loc 1 348 3 is_stmt 1 view .LVU338 348:Core/Src/main.c **** sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE; 930 .loc 1 348 33 is_stmt 0 view .LVU339 931 007c 0493 str r3, [sp, #16] 349:Core/Src/main.c **** sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH; 932 .loc 1 349 3 is_stmt 1 view .LVU340 349:Core/Src/main.c **** sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH; 933 .loc 1 349 35 is_stmt 0 view .LVU341 934 007e 0593 str r3, [sp, #20] 350:Core/Src/main.c **** sBreakDeadTimeConfig.BreakFilter = 0; 935 .loc 1 350 3 is_stmt 1 view .LVU342 350:Core/Src/main.c **** sBreakDeadTimeConfig.BreakFilter = 0; 936 .loc 1 350 38 is_stmt 0 view .LVU343 937 0080 4FF40052 mov r2, #8192 938 0084 0692 str r2, [sp, #24] ARM GAS /tmp/ccBZCjHD.s page 34 351:Core/Src/main.c **** sBreakDeadTimeConfig.Break2State = TIM_BREAK2_DISABLE; 939 .loc 1 351 3 is_stmt 1 view .LVU344 351:Core/Src/main.c **** sBreakDeadTimeConfig.Break2State = TIM_BREAK2_DISABLE; 940 .loc 1 351 36 is_stmt 0 view .LVU345 941 0086 0793 str r3, [sp, #28] 352:Core/Src/main.c **** sBreakDeadTimeConfig.Break2Polarity = TIM_BREAK2POLARITY_HIGH; 942 .loc 1 352 3 is_stmt 1 view .LVU346 352:Core/Src/main.c **** sBreakDeadTimeConfig.Break2Polarity = TIM_BREAK2POLARITY_HIGH; 943 .loc 1 352 36 is_stmt 0 view .LVU347 944 0088 0893 str r3, [sp, #32] 353:Core/Src/main.c **** sBreakDeadTimeConfig.Break2Filter = 0; 945 .loc 1 353 3 is_stmt 1 view .LVU348 353:Core/Src/main.c **** sBreakDeadTimeConfig.Break2Filter = 0; 946 .loc 1 353 39 is_stmt 0 view .LVU349 947 008a 4FF00072 mov r2, #33554432 948 008e 0992 str r2, [sp, #36] 354:Core/Src/main.c **** sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE; 949 .loc 1 354 3 is_stmt 1 view .LVU350 354:Core/Src/main.c **** sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE; 950 .loc 1 354 37 is_stmt 0 view .LVU351 951 0090 0A93 str r3, [sp, #40] 355:Core/Src/main.c **** if (HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig) != HAL_OK) 952 .loc 1 355 3 is_stmt 1 view .LVU352 355:Core/Src/main.c **** if (HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig) != HAL_OK) 953 .loc 1 355 40 is_stmt 0 view .LVU353 954 0092 0B93 str r3, [sp, #44] 356:Core/Src/main.c **** { 955 .loc 1 356 3 is_stmt 1 view .LVU354 356:Core/Src/main.c **** { 956 .loc 1 356 7 is_stmt 0 view .LVU355 957 0094 01A9 add r1, sp, #4 958 0096 0848 ldr r0, .L59 959 0098 FFF7FEFF bl HAL_TIMEx_ConfigBreakDeadTime 960 .LVL36: 356:Core/Src/main.c **** { 961 .loc 1 356 6 discriminator 1 view .LVU356 962 009c 50B9 cbnz r0, .L58 363:Core/Src/main.c **** 963 .loc 1 363 3 is_stmt 1 view .LVU357 964 009e 0648 ldr r0, .L59 965 00a0 FFF7FEFF bl HAL_TIM_MspPostInit 966 .LVL37: 365:Core/Src/main.c **** 967 .loc 1 365 1 is_stmt 0 view .LVU358 968 00a4 16B0 add sp, sp, #88 969 .cfi_remember_state 970 .cfi_def_cfa_offset 8 971 @ sp needed 972 00a6 10BD pop {r4, pc} 973 .L55: 974 .cfi_restore_state 325:Core/Src/main.c **** } 975 .loc 1 325 5 is_stmt 1 view .LVU359 976 00a8 FFF7FEFF bl Error_Handler 977 .LVL38: 978 .L56: 332:Core/Src/main.c **** } ARM GAS /tmp/ccBZCjHD.s page 35 979 .loc 1 332 5 view .LVU360 980 00ac FFF7FEFF bl Error_Handler 981 .LVL39: 982 .L57: 343:Core/Src/main.c **** } 983 .loc 1 343 5 view .LVU361 984 00b0 FFF7FEFF bl Error_Handler 985 .LVL40: 986 .L58: 358:Core/Src/main.c **** } 987 .loc 1 358 5 view .LVU362 988 00b4 FFF7FEFF bl Error_Handler 989 .LVL41: 990 .L60: 991 .align 2 992 .L59: 993 00b8 00000000 .word htim1 994 00bc 002C0140 .word 1073818624 995 .cfi_endproc 996 .LFE135: 998 .section .text.SystemClock_Config,"ax",%progbits 999 .align 1 1000 .global SystemClock_Config 1001 .syntax unified 1002 .thumb 1003 .thumb_func 1005 SystemClock_Config: 1006 .LFB131: 131:Core/Src/main.c **** RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 1007 .loc 1 131 1 view -0 1008 .cfi_startproc 1009 @ args = 0, pretend = 0, frame = 112 1010 @ frame_needed = 0, uses_anonymous_args = 0 1011 0000 00B5 push {lr} 1012 .cfi_def_cfa_offset 4 1013 .cfi_offset 14, -4 1014 0002 9DB0 sub sp, sp, #116 1015 .cfi_def_cfa_offset 120 132:Core/Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 1016 .loc 1 132 3 view .LVU364 132:Core/Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 1017 .loc 1 132 22 is_stmt 0 view .LVU365 1018 0004 2822 movs r2, #40 1019 0006 0021 movs r1, #0 1020 0008 12A8 add r0, sp, #72 1021 000a FFF7FEFF bl memset 1022 .LVL42: 133:Core/Src/main.c **** RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; 1023 .loc 1 133 3 is_stmt 1 view .LVU366 133:Core/Src/main.c **** RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; 1024 .loc 1 133 22 is_stmt 0 view .LVU367 1025 000e 0021 movs r1, #0 1026 0010 0D91 str r1, [sp, #52] 1027 0012 0E91 str r1, [sp, #56] 1028 0014 0F91 str r1, [sp, #60] 1029 0016 1091 str r1, [sp, #64] 1030 0018 1191 str r1, [sp, #68] ARM GAS /tmp/ccBZCjHD.s page 36 134:Core/Src/main.c **** 1031 .loc 1 134 3 is_stmt 1 view .LVU368 134:Core/Src/main.c **** 1032 .loc 1 134 28 is_stmt 0 view .LVU369 1033 001a 3422 movs r2, #52 1034 001c 6846 mov r0, sp 1035 001e FFF7FEFF bl memset 1036 .LVL43: 139:Core/Src/main.c **** RCC_OscInitStruct.HSIState = RCC_HSI_ON; 1037 .loc 1 139 3 is_stmt 1 view .LVU370 139:Core/Src/main.c **** RCC_OscInitStruct.HSIState = RCC_HSI_ON; 1038 .loc 1 139 36 is_stmt 0 view .LVU371 1039 0022 0223 movs r3, #2 1040 0024 1293 str r3, [sp, #72] 140:Core/Src/main.c **** RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; 1041 .loc 1 140 3 is_stmt 1 view .LVU372 140:Core/Src/main.c **** RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; 1042 .loc 1 140 30 is_stmt 0 view .LVU373 1043 0026 0123 movs r3, #1 1044 0028 1693 str r3, [sp, #88] 141:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; 1045 .loc 1 141 3 is_stmt 1 view .LVU374 141:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; 1046 .loc 1 141 41 is_stmt 0 view .LVU375 1047 002a 1023 movs r3, #16 1048 002c 1793 str r3, [sp, #92] 142:Core/Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 1049 .loc 1 142 3 is_stmt 1 view .LVU376 143:Core/Src/main.c **** { 1050 .loc 1 143 3 view .LVU377 143:Core/Src/main.c **** { 1051 .loc 1 143 7 is_stmt 0 view .LVU378 1052 002e 12A8 add r0, sp, #72 1053 0030 FFF7FEFF bl HAL_RCC_OscConfig 1054 .LVL44: 143:Core/Src/main.c **** { 1055 .loc 1 143 6 discriminator 1 view .LVU379 1056 0034 C0B9 cbnz r0, .L66 150:Core/Src/main.c **** |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; 1057 .loc 1 150 3 is_stmt 1 view .LVU380 150:Core/Src/main.c **** |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; 1058 .loc 1 150 31 is_stmt 0 view .LVU381 1059 0036 0F23 movs r3, #15 1060 0038 0D93 str r3, [sp, #52] 152:Core/Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 1061 .loc 1 152 3 is_stmt 1 view .LVU382 152:Core/Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 1062 .loc 1 152 34 is_stmt 0 view .LVU383 1063 003a 0021 movs r1, #0 1064 003c 0E91 str r1, [sp, #56] 153:Core/Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; 1065 .loc 1 153 3 is_stmt 1 view .LVU384 153:Core/Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; 1066 .loc 1 153 35 is_stmt 0 view .LVU385 1067 003e 0F91 str r1, [sp, #60] 154:Core/Src/main.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 1068 .loc 1 154 3 is_stmt 1 view .LVU386 ARM GAS /tmp/ccBZCjHD.s page 37 154:Core/Src/main.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 1069 .loc 1 154 36 is_stmt 0 view .LVU387 1070 0040 1091 str r1, [sp, #64] 155:Core/Src/main.c **** 1071 .loc 1 155 3 is_stmt 1 view .LVU388 155:Core/Src/main.c **** 1072 .loc 1 155 36 is_stmt 0 view .LVU389 1073 0042 1191 str r1, [sp, #68] 157:Core/Src/main.c **** { 1074 .loc 1 157 3 is_stmt 1 view .LVU390 157:Core/Src/main.c **** { 1075 .loc 1 157 7 is_stmt 0 view .LVU391 1076 0044 0DA8 add r0, sp, #52 1077 0046 FFF7FEFF bl HAL_RCC_ClockConfig 1078 .LVL45: 157:Core/Src/main.c **** { 1079 .loc 1 157 6 discriminator 1 view .LVU392 1080 004a 78B9 cbnz r0, .L67 161:Core/Src/main.c **** |RCC_PERIPHCLK_TIM1; 1081 .loc 1 161 3 is_stmt 1 view .LVU393 161:Core/Src/main.c **** |RCC_PERIPHCLK_TIM1; 1082 .loc 1 161 38 is_stmt 0 view .LVU394 1083 004c 41F22103 movw r3, #4129 1084 0050 0093 str r3, [sp] 163:Core/Src/main.c **** PeriphClkInit.I2c1ClockSelection = RCC_I2C1CLKSOURCE_HSI; 1085 .loc 1 163 3 is_stmt 1 view .LVU395 163:Core/Src/main.c **** PeriphClkInit.I2c1ClockSelection = RCC_I2C1CLKSOURCE_HSI; 1086 .loc 1 163 38 is_stmt 0 view .LVU396 1087 0052 0023 movs r3, #0 1088 0054 0293 str r3, [sp, #8] 164:Core/Src/main.c **** PeriphClkInit.Tim1ClockSelection = RCC_TIM1CLK_HCLK; 1089 .loc 1 164 3 is_stmt 1 view .LVU397 164:Core/Src/main.c **** PeriphClkInit.Tim1ClockSelection = RCC_TIM1CLK_HCLK; 1090 .loc 1 164 36 is_stmt 0 view .LVU398 1091 0056 0793 str r3, [sp, #28] 165:Core/Src/main.c **** if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 1092 .loc 1 165 3 is_stmt 1 view .LVU399 165:Core/Src/main.c **** if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 1093 .loc 1 165 36 is_stmt 0 view .LVU400 1094 0058 0B93 str r3, [sp, #44] 166:Core/Src/main.c **** { 1095 .loc 1 166 3 is_stmt 1 view .LVU401 166:Core/Src/main.c **** { 1096 .loc 1 166 7 is_stmt 0 view .LVU402 1097 005a 6846 mov r0, sp 1098 005c FFF7FEFF bl HAL_RCCEx_PeriphCLKConfig 1099 .LVL46: 166:Core/Src/main.c **** { 1100 .loc 1 166 6 discriminator 1 view .LVU403 1101 0060 30B9 cbnz r0, .L68 170:Core/Src/main.c **** 1102 .loc 1 170 1 view .LVU404 1103 0062 1DB0 add sp, sp, #116 1104 .cfi_remember_state 1105 .cfi_def_cfa_offset 4 1106 @ sp needed 1107 0064 5DF804FB ldr pc, [sp], #4 ARM GAS /tmp/ccBZCjHD.s page 38 1108 .L66: 1109 .cfi_restore_state 145:Core/Src/main.c **** } 1110 .loc 1 145 5 is_stmt 1 view .LVU405 1111 0068 FFF7FEFF bl Error_Handler 1112 .LVL47: 1113 .L67: 159:Core/Src/main.c **** } 1114 .loc 1 159 5 view .LVU406 1115 006c FFF7FEFF bl Error_Handler 1116 .LVL48: 1117 .L68: 168:Core/Src/main.c **** } 1118 .loc 1 168 5 view .LVU407 1119 0070 FFF7FEFF bl Error_Handler 1120 .LVL49: 1121 .cfi_endproc 1122 .LFE131: 1124 .section .text.main,"ax",%progbits 1125 .align 1 1126 .global main 1127 .syntax unified 1128 .thumb 1129 .thumb_func 1131 main: 1132 .LFB130: 81:Core/Src/main.c **** 1133 .loc 1 81 1 view -0 1134 .cfi_startproc 1135 @ Volatile: function does not return. 1136 @ args = 0, pretend = 0, frame = 0 1137 @ frame_needed = 0, uses_anonymous_args = 0 1138 0000 08B5 push {r3, lr} 1139 .cfi_def_cfa_offset 8 1140 .cfi_offset 3, -8 1141 .cfi_offset 14, -4 90:Core/Src/main.c **** 1142 .loc 1 90 3 view .LVU409 1143 0002 FFF7FEFF bl HAL_Init 1144 .LVL50: 97:Core/Src/main.c **** 1145 .loc 1 97 3 view .LVU410 1146 0006 FFF7FEFF bl SystemClock_Config 1147 .LVL51: 104:Core/Src/main.c **** MX_CAN_Init(); 1148 .loc 1 104 3 view .LVU411 1149 000a FFF7FEFF bl MX_GPIO_Init 1150 .LVL52: 105:Core/Src/main.c **** MX_I2C1_Init(); 1151 .loc 1 105 3 view .LVU412 1152 000e FFF7FEFF bl MX_CAN_Init 1153 .LVL53: 106:Core/Src/main.c **** MX_SPI1_Init(); 1154 .loc 1 106 3 view .LVU413 1155 0012 FFF7FEFF bl MX_I2C1_Init 1156 .LVL54: 107:Core/Src/main.c **** MX_TIM15_Init(); ARM GAS /tmp/ccBZCjHD.s page 39 1157 .loc 1 107 3 view .LVU414 1158 0016 FFF7FEFF bl MX_SPI1_Init 1159 .LVL55: 108:Core/Src/main.c **** MX_USART1_UART_Init(); 1160 .loc 1 108 3 view .LVU415 1161 001a FFF7FEFF bl MX_TIM15_Init 1162 .LVL56: 109:Core/Src/main.c **** MX_TIM1_Init(); 1163 .loc 1 109 3 view .LVU416 1164 001e FFF7FEFF bl MX_USART1_UART_Init 1165 .LVL57: 110:Core/Src/main.c **** /* USER CODE BEGIN 2 */ 1166 .loc 1 110 3 view .LVU417 1167 0022 FFF7FEFF bl MX_TIM1_Init 1168 .LVL58: 1169 .L70: 117:Core/Src/main.c **** { 1170 .loc 1 117 3 view .LVU418 122:Core/Src/main.c **** /* USER CODE END 3 */ 1171 .loc 1 122 3 view .LVU419 117:Core/Src/main.c **** { 1172 .loc 1 117 9 view .LVU420 1173 0026 FEE7 b .L70 1174 .cfi_endproc 1175 .LFE130: 1177 .global huart1 1178 .section .bss.huart1,"aw",%nobits 1179 .align 2 1182 huart1: 1183 0000 00000000 .space 136 1183 00000000 1183 00000000 1183 00000000 1183 00000000 1184 .global htim15 1185 .section .bss.htim15,"aw",%nobits 1186 .align 2 1189 htim15: 1190 0000 00000000 .space 76 1190 00000000 1190 00000000 1190 00000000 1190 00000000 1191 .global htim1 1192 .section .bss.htim1,"aw",%nobits 1193 .align 2 1196 htim1: 1197 0000 00000000 .space 76 1197 00000000 1197 00000000 1197 00000000 1197 00000000 1198 .global hspi1 1199 .section .bss.hspi1,"aw",%nobits 1200 .align 2 1203 hspi1: 1204 0000 00000000 .space 100 ARM GAS /tmp/ccBZCjHD.s page 40 1204 00000000 1204 00000000 1204 00000000 1204 00000000 1205 .global hi2c1 1206 .section .bss.hi2c1,"aw",%nobits 1207 .align 2 1210 hi2c1: 1211 0000 00000000 .space 84 1211 00000000 1211 00000000 1211 00000000 1211 00000000 1212 .global hcan 1213 .section .bss.hcan,"aw",%nobits 1214 .align 2 1217 hcan: 1218 0000 00000000 .space 40 1218 00000000 1218 00000000 1218 00000000 1218 00000000 1219 .text 1220 .Letext0: 1221 .file 3 "/home/h/.var/app/com.visualstudio.code/config/Code/User/globalStorage/bmd.stm32-for-vscod 1222 .file 4 "/home/h/.var/app/com.visualstudio.code/config/Code/User/globalStorage/bmd.stm32-for-vscod 1223 .file 5 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h" 1224 .file 6 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h" 1225 .file 7 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h" 1226 .file 8 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h" 1227 .file 9 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h" 1228 .file 10 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h" 1229 .file 11 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h" 1230 .file 12 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h" 1231 .file 13 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h" 1232 .file 14 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h" 1233 .file 15 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h" 1234 .file 16 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_uart.h" 1235 .file 17 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h" 1236 .file 18 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h" 1237 .file 19 "Core/Inc/main.h" 1238 .file 20 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h" 1239 .file 21 "" ARM GAS /tmp/ccBZCjHD.s page 41 DEFINED SYMBOLS *ABS*:00000000 main.c /tmp/ccBZCjHD.s:21 .text.MX_GPIO_Init:00000000 $t /tmp/ccBZCjHD.s:26 .text.MX_GPIO_Init:00000000 MX_GPIO_Init /tmp/ccBZCjHD.s:228 .text.MX_GPIO_Init:000000ec $d /tmp/ccBZCjHD.s:235 .text.Error_Handler:00000000 $t /tmp/ccBZCjHD.s:241 .text.Error_Handler:00000000 Error_Handler /tmp/ccBZCjHD.s:273 .text.MX_CAN_Init:00000000 $t /tmp/ccBZCjHD.s:278 .text.MX_CAN_Init:00000000 MX_CAN_Init /tmp/ccBZCjHD.s:343 .text.MX_CAN_Init:00000030 $d /tmp/ccBZCjHD.s:1217 .bss.hcan:00000000 hcan /tmp/ccBZCjHD.s:349 .text.MX_I2C1_Init:00000000 $t /tmp/ccBZCjHD.s:354 .text.MX_I2C1_Init:00000000 MX_I2C1_Init /tmp/ccBZCjHD.s:435 .text.MX_I2C1_Init:00000048 $d /tmp/ccBZCjHD.s:1210 .bss.hi2c1:00000000 hi2c1 /tmp/ccBZCjHD.s:442 .text.MX_SPI1_Init:00000000 $t /tmp/ccBZCjHD.s:447 .text.MX_SPI1_Init:00000000 MX_SPI1_Init /tmp/ccBZCjHD.s:521 .text.MX_SPI1_Init:0000003c $d /tmp/ccBZCjHD.s:1203 .bss.hspi1:00000000 hspi1 /tmp/ccBZCjHD.s:527 .text.MX_TIM15_Init:00000000 $t /tmp/ccBZCjHD.s:532 .text.MX_TIM15_Init:00000000 MX_TIM15_Init /tmp/ccBZCjHD.s:721 .text.MX_TIM15_Init:000000bc $d /tmp/ccBZCjHD.s:1189 .bss.htim15:00000000 htim15 /tmp/ccBZCjHD.s:727 .text.MX_USART1_UART_Init:00000000 $t /tmp/ccBZCjHD.s:732 .text.MX_USART1_UART_Init:00000000 MX_USART1_UART_Init /tmp/ccBZCjHD.s:792 .text.MX_USART1_UART_Init:00000030 $d /tmp/ccBZCjHD.s:1182 .bss.huart1:00000000 huart1 /tmp/ccBZCjHD.s:798 .text.MX_TIM1_Init:00000000 $t /tmp/ccBZCjHD.s:803 .text.MX_TIM1_Init:00000000 MX_TIM1_Init /tmp/ccBZCjHD.s:993 .text.MX_TIM1_Init:000000b8 $d /tmp/ccBZCjHD.s:1196 .bss.htim1:00000000 htim1 /tmp/ccBZCjHD.s:999 .text.SystemClock_Config:00000000 $t /tmp/ccBZCjHD.s:1005 .text.SystemClock_Config:00000000 SystemClock_Config /tmp/ccBZCjHD.s:1125 .text.main:00000000 $t /tmp/ccBZCjHD.s:1131 .text.main:00000000 main /tmp/ccBZCjHD.s:1179 .bss.huart1:00000000 $d /tmp/ccBZCjHD.s:1186 .bss.htim15:00000000 $d /tmp/ccBZCjHD.s:1193 .bss.htim1:00000000 $d /tmp/ccBZCjHD.s:1200 .bss.hspi1:00000000 $d /tmp/ccBZCjHD.s:1207 .bss.hi2c1:00000000 $d /tmp/ccBZCjHD.s:1214 .bss.hcan:00000000 $d UNDEFINED SYMBOLS HAL_GPIO_WritePin HAL_GPIO_Init HAL_CAN_Init HAL_I2C_Init HAL_I2CEx_ConfigAnalogFilter HAL_I2CEx_ConfigDigitalFilter HAL_SPI_Init memset HAL_TIM_PWM_Init HAL_TIMEx_MasterConfigSynchronization HAL_TIM_PWM_ConfigChannel HAL_TIMEx_ConfigBreakDeadTime HAL_TIM_MspPostInit HAL_UART_Init ARM GAS /tmp/ccBZCjHD.s page 42 HAL_RCC_OscConfig HAL_RCC_ClockConfig HAL_RCCEx_PeriphCLKConfig HAL_Init