ARM GAS /tmp/ccpm1fqH.s page 1 1 .cpu cortex-m4 2 .arch armv7e-m 3 .fpu fpv4-sp-d16 4 .eabi_attribute 27, 1 5 .eabi_attribute 28, 1 6 .eabi_attribute 20, 1 7 .eabi_attribute 21, 1 8 .eabi_attribute 23, 3 9 .eabi_attribute 24, 1 10 .eabi_attribute 25, 1 11 .eabi_attribute 26, 1 12 .eabi_attribute 30, 6 13 .eabi_attribute 34, 1 14 .eabi_attribute 18, 4 15 .file "stm32f3xx_it.c" 16 .text 17 .Ltext0: 18 .cfi_sections .debug_frame 19 .file 1 "Core/Src/stm32f3xx_it.c" 20 .section .text.NMI_Handler,"ax",%progbits 21 .align 1 22 .global NMI_Handler 23 .syntax unified 24 .thumb 25 .thumb_func 27 NMI_Handler: 28 .LFB130: 1:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN Header */ 2:Core/Src/stm32f3xx_it.c **** /** 3:Core/Src/stm32f3xx_it.c **** ****************************************************************************** 4:Core/Src/stm32f3xx_it.c **** * @file stm32f3xx_it.c 5:Core/Src/stm32f3xx_it.c **** * @brief Interrupt Service Routines. 6:Core/Src/stm32f3xx_it.c **** ****************************************************************************** 7:Core/Src/stm32f3xx_it.c **** * @attention 8:Core/Src/stm32f3xx_it.c **** * 9:Core/Src/stm32f3xx_it.c **** * Copyright (c) 2024 STMicroelectronics. 10:Core/Src/stm32f3xx_it.c **** * All rights reserved. 11:Core/Src/stm32f3xx_it.c **** * 12:Core/Src/stm32f3xx_it.c **** * This software is licensed under terms that can be found in the LICENSE file 13:Core/Src/stm32f3xx_it.c **** * in the root directory of this software component. 14:Core/Src/stm32f3xx_it.c **** * If no LICENSE file comes with this software, it is provided AS-IS. 15:Core/Src/stm32f3xx_it.c **** * 16:Core/Src/stm32f3xx_it.c **** ****************************************************************************** 17:Core/Src/stm32f3xx_it.c **** */ 18:Core/Src/stm32f3xx_it.c **** /* USER CODE END Header */ 19:Core/Src/stm32f3xx_it.c **** 20:Core/Src/stm32f3xx_it.c **** /* Includes ------------------------------------------------------------------*/ 21:Core/Src/stm32f3xx_it.c **** #include "main.h" 22:Core/Src/stm32f3xx_it.c **** #include "stm32f3xx_it.h" 23:Core/Src/stm32f3xx_it.c **** /* Private includes ----------------------------------------------------------*/ 24:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN Includes */ 25:Core/Src/stm32f3xx_it.c **** /* USER CODE END Includes */ 26:Core/Src/stm32f3xx_it.c **** 27:Core/Src/stm32f3xx_it.c **** /* Private typedef -----------------------------------------------------------*/ 28:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN TD */ 29:Core/Src/stm32f3xx_it.c **** 30:Core/Src/stm32f3xx_it.c **** /* USER CODE END TD */ ARM GAS /tmp/ccpm1fqH.s page 2 31:Core/Src/stm32f3xx_it.c **** 32:Core/Src/stm32f3xx_it.c **** /* Private define ------------------------------------------------------------*/ 33:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN PD */ 34:Core/Src/stm32f3xx_it.c **** 35:Core/Src/stm32f3xx_it.c **** /* USER CODE END PD */ 36:Core/Src/stm32f3xx_it.c **** 37:Core/Src/stm32f3xx_it.c **** /* Private macro -------------------------------------------------------------*/ 38:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN PM */ 39:Core/Src/stm32f3xx_it.c **** 40:Core/Src/stm32f3xx_it.c **** /* USER CODE END PM */ 41:Core/Src/stm32f3xx_it.c **** 42:Core/Src/stm32f3xx_it.c **** /* Private variables ---------------------------------------------------------*/ 43:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN PV */ 44:Core/Src/stm32f3xx_it.c **** 45:Core/Src/stm32f3xx_it.c **** /* USER CODE END PV */ 46:Core/Src/stm32f3xx_it.c **** 47:Core/Src/stm32f3xx_it.c **** /* Private function prototypes -----------------------------------------------*/ 48:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN PFP */ 49:Core/Src/stm32f3xx_it.c **** 50:Core/Src/stm32f3xx_it.c **** /* USER CODE END PFP */ 51:Core/Src/stm32f3xx_it.c **** 52:Core/Src/stm32f3xx_it.c **** /* Private user code ---------------------------------------------------------*/ 53:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN 0 */ 54:Core/Src/stm32f3xx_it.c **** 55:Core/Src/stm32f3xx_it.c **** /* USER CODE END 0 */ 56:Core/Src/stm32f3xx_it.c **** 57:Core/Src/stm32f3xx_it.c **** /* External variables --------------------------------------------------------*/ 58:Core/Src/stm32f3xx_it.c **** extern CAN_HandleTypeDef hcan; 59:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN EV */ 60:Core/Src/stm32f3xx_it.c **** 61:Core/Src/stm32f3xx_it.c **** /* USER CODE END EV */ 62:Core/Src/stm32f3xx_it.c **** 63:Core/Src/stm32f3xx_it.c **** /******************************************************************************/ 64:Core/Src/stm32f3xx_it.c **** /* Cortex-M4 Processor Interruption and Exception Handlers */ 65:Core/Src/stm32f3xx_it.c **** /******************************************************************************/ 66:Core/Src/stm32f3xx_it.c **** /** 67:Core/Src/stm32f3xx_it.c **** * @brief This function handles Non maskable interrupt. 68:Core/Src/stm32f3xx_it.c **** */ 69:Core/Src/stm32f3xx_it.c **** void NMI_Handler(void) 70:Core/Src/stm32f3xx_it.c **** { 29 .loc 1 70 1 30 .cfi_startproc 31 @ args = 0, pretend = 0, frame = 0 32 @ frame_needed = 1, uses_anonymous_args = 0 33 @ link register save eliminated. 34 0000 80B4 push {r7} 35 .cfi_def_cfa_offset 4 36 .cfi_offset 7, -4 37 0002 00AF add r7, sp, #0 38 .cfi_def_cfa_register 7 39 .L2: 71:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ 72:Core/Src/stm32f3xx_it.c **** 73:Core/Src/stm32f3xx_it.c **** /* USER CODE END NonMaskableInt_IRQn 0 */ 74:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ 75:Core/Src/stm32f3xx_it.c **** while (1) 40 .loc 1 75 10 ARM GAS /tmp/ccpm1fqH.s page 3 41 0004 00BF nop 42 0006 FDE7 b .L2 43 .cfi_endproc 44 .LFE130: 46 .section .text.HardFault_Handler,"ax",%progbits 47 .align 1 48 .global HardFault_Handler 49 .syntax unified 50 .thumb 51 .thumb_func 53 HardFault_Handler: 54 .LFB131: 76:Core/Src/stm32f3xx_it.c **** { 77:Core/Src/stm32f3xx_it.c **** } 78:Core/Src/stm32f3xx_it.c **** /* USER CODE END NonMaskableInt_IRQn 1 */ 79:Core/Src/stm32f3xx_it.c **** } 80:Core/Src/stm32f3xx_it.c **** 81:Core/Src/stm32f3xx_it.c **** /** 82:Core/Src/stm32f3xx_it.c **** * @brief This function handles Hard fault interrupt. 83:Core/Src/stm32f3xx_it.c **** */ 84:Core/Src/stm32f3xx_it.c **** void HardFault_Handler(void) 85:Core/Src/stm32f3xx_it.c **** { 55 .loc 1 85 1 56 .cfi_startproc 57 @ args = 0, pretend = 0, frame = 0 58 @ frame_needed = 1, uses_anonymous_args = 0 59 @ link register save eliminated. 60 0000 80B4 push {r7} 61 .cfi_def_cfa_offset 4 62 .cfi_offset 7, -4 63 0002 00AF add r7, sp, #0 64 .cfi_def_cfa_register 7 65 .L4: 86:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN HardFault_IRQn 0 */ 87:Core/Src/stm32f3xx_it.c **** 88:Core/Src/stm32f3xx_it.c **** /* USER CODE END HardFault_IRQn 0 */ 89:Core/Src/stm32f3xx_it.c **** while (1) 66 .loc 1 89 9 67 0004 00BF nop 68 0006 FDE7 b .L4 69 .cfi_endproc 70 .LFE131: 72 .section .text.MemManage_Handler,"ax",%progbits 73 .align 1 74 .global MemManage_Handler 75 .syntax unified 76 .thumb 77 .thumb_func 79 MemManage_Handler: 80 .LFB132: 90:Core/Src/stm32f3xx_it.c **** { 91:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN W1_HardFault_IRQn 0 */ 92:Core/Src/stm32f3xx_it.c **** /* USER CODE END W1_HardFault_IRQn 0 */ 93:Core/Src/stm32f3xx_it.c **** } 94:Core/Src/stm32f3xx_it.c **** } 95:Core/Src/stm32f3xx_it.c **** 96:Core/Src/stm32f3xx_it.c **** /** ARM GAS /tmp/ccpm1fqH.s page 4 97:Core/Src/stm32f3xx_it.c **** * @brief This function handles Memory management fault. 98:Core/Src/stm32f3xx_it.c **** */ 99:Core/Src/stm32f3xx_it.c **** void MemManage_Handler(void) 100:Core/Src/stm32f3xx_it.c **** { 81 .loc 1 100 1 82 .cfi_startproc 83 @ args = 0, pretend = 0, frame = 0 84 @ frame_needed = 1, uses_anonymous_args = 0 85 @ link register save eliminated. 86 0000 80B4 push {r7} 87 .cfi_def_cfa_offset 4 88 .cfi_offset 7, -4 89 0002 00AF add r7, sp, #0 90 .cfi_def_cfa_register 7 91 .L6: 101:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN MemoryManagement_IRQn 0 */ 102:Core/Src/stm32f3xx_it.c **** 103:Core/Src/stm32f3xx_it.c **** /* USER CODE END MemoryManagement_IRQn 0 */ 104:Core/Src/stm32f3xx_it.c **** while (1) 92 .loc 1 104 9 93 0004 00BF nop 94 0006 FDE7 b .L6 95 .cfi_endproc 96 .LFE132: 98 .section .text.BusFault_Handler,"ax",%progbits 99 .align 1 100 .global BusFault_Handler 101 .syntax unified 102 .thumb 103 .thumb_func 105 BusFault_Handler: 106 .LFB133: 105:Core/Src/stm32f3xx_it.c **** { 106:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ 107:Core/Src/stm32f3xx_it.c **** /* USER CODE END W1_MemoryManagement_IRQn 0 */ 108:Core/Src/stm32f3xx_it.c **** } 109:Core/Src/stm32f3xx_it.c **** } 110:Core/Src/stm32f3xx_it.c **** 111:Core/Src/stm32f3xx_it.c **** /** 112:Core/Src/stm32f3xx_it.c **** * @brief This function handles Pre-fetch fault, memory access fault. 113:Core/Src/stm32f3xx_it.c **** */ 114:Core/Src/stm32f3xx_it.c **** void BusFault_Handler(void) 115:Core/Src/stm32f3xx_it.c **** { 107 .loc 1 115 1 108 .cfi_startproc 109 @ args = 0, pretend = 0, frame = 0 110 @ frame_needed = 1, uses_anonymous_args = 0 111 @ link register save eliminated. 112 0000 80B4 push {r7} 113 .cfi_def_cfa_offset 4 114 .cfi_offset 7, -4 115 0002 00AF add r7, sp, #0 116 .cfi_def_cfa_register 7 117 .L8: 116:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN BusFault_IRQn 0 */ 117:Core/Src/stm32f3xx_it.c **** 118:Core/Src/stm32f3xx_it.c **** /* USER CODE END BusFault_IRQn 0 */ ARM GAS /tmp/ccpm1fqH.s page 5 119:Core/Src/stm32f3xx_it.c **** while (1) 118 .loc 1 119 9 119 0004 00BF nop 120 0006 FDE7 b .L8 121 .cfi_endproc 122 .LFE133: 124 .section .text.UsageFault_Handler,"ax",%progbits 125 .align 1 126 .global UsageFault_Handler 127 .syntax unified 128 .thumb 129 .thumb_func 131 UsageFault_Handler: 132 .LFB134: 120:Core/Src/stm32f3xx_it.c **** { 121:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN W1_BusFault_IRQn 0 */ 122:Core/Src/stm32f3xx_it.c **** /* USER CODE END W1_BusFault_IRQn 0 */ 123:Core/Src/stm32f3xx_it.c **** } 124:Core/Src/stm32f3xx_it.c **** } 125:Core/Src/stm32f3xx_it.c **** 126:Core/Src/stm32f3xx_it.c **** /** 127:Core/Src/stm32f3xx_it.c **** * @brief This function handles Undefined instruction or illegal state. 128:Core/Src/stm32f3xx_it.c **** */ 129:Core/Src/stm32f3xx_it.c **** void UsageFault_Handler(void) 130:Core/Src/stm32f3xx_it.c **** { 133 .loc 1 130 1 134 .cfi_startproc 135 @ args = 0, pretend = 0, frame = 0 136 @ frame_needed = 1, uses_anonymous_args = 0 137 @ link register save eliminated. 138 0000 80B4 push {r7} 139 .cfi_def_cfa_offset 4 140 .cfi_offset 7, -4 141 0002 00AF add r7, sp, #0 142 .cfi_def_cfa_register 7 143 .L10: 131:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN UsageFault_IRQn 0 */ 132:Core/Src/stm32f3xx_it.c **** 133:Core/Src/stm32f3xx_it.c **** /* USER CODE END UsageFault_IRQn 0 */ 134:Core/Src/stm32f3xx_it.c **** while (1) 144 .loc 1 134 9 145 0004 00BF nop 146 0006 FDE7 b .L10 147 .cfi_endproc 148 .LFE134: 150 .section .text.SVC_Handler,"ax",%progbits 151 .align 1 152 .global SVC_Handler 153 .syntax unified 154 .thumb 155 .thumb_func 157 SVC_Handler: 158 .LFB135: 135:Core/Src/stm32f3xx_it.c **** { 136:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ 137:Core/Src/stm32f3xx_it.c **** /* USER CODE END W1_UsageFault_IRQn 0 */ 138:Core/Src/stm32f3xx_it.c **** } ARM GAS /tmp/ccpm1fqH.s page 6 139:Core/Src/stm32f3xx_it.c **** } 140:Core/Src/stm32f3xx_it.c **** 141:Core/Src/stm32f3xx_it.c **** /** 142:Core/Src/stm32f3xx_it.c **** * @brief This function handles System service call via SWI instruction. 143:Core/Src/stm32f3xx_it.c **** */ 144:Core/Src/stm32f3xx_it.c **** void SVC_Handler(void) 145:Core/Src/stm32f3xx_it.c **** { 159 .loc 1 145 1 160 .cfi_startproc 161 @ args = 0, pretend = 0, frame = 0 162 @ frame_needed = 1, uses_anonymous_args = 0 163 @ link register save eliminated. 164 0000 80B4 push {r7} 165 .cfi_def_cfa_offset 4 166 .cfi_offset 7, -4 167 0002 00AF add r7, sp, #0 168 .cfi_def_cfa_register 7 146:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN SVCall_IRQn 0 */ 147:Core/Src/stm32f3xx_it.c **** 148:Core/Src/stm32f3xx_it.c **** /* USER CODE END SVCall_IRQn 0 */ 149:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN SVCall_IRQn 1 */ 150:Core/Src/stm32f3xx_it.c **** 151:Core/Src/stm32f3xx_it.c **** /* USER CODE END SVCall_IRQn 1 */ 152:Core/Src/stm32f3xx_it.c **** } 169 .loc 1 152 1 170 0004 00BF nop 171 0006 BD46 mov sp, r7 172 .cfi_def_cfa_register 13 173 @ sp needed 174 0008 5DF8047B ldr r7, [sp], #4 175 .cfi_restore 7 176 .cfi_def_cfa_offset 0 177 000c 7047 bx lr 178 .cfi_endproc 179 .LFE135: 181 .section .text.DebugMon_Handler,"ax",%progbits 182 .align 1 183 .global DebugMon_Handler 184 .syntax unified 185 .thumb 186 .thumb_func 188 DebugMon_Handler: 189 .LFB136: 153:Core/Src/stm32f3xx_it.c **** 154:Core/Src/stm32f3xx_it.c **** /** 155:Core/Src/stm32f3xx_it.c **** * @brief This function handles Debug monitor. 156:Core/Src/stm32f3xx_it.c **** */ 157:Core/Src/stm32f3xx_it.c **** void DebugMon_Handler(void) 158:Core/Src/stm32f3xx_it.c **** { 190 .loc 1 158 1 191 .cfi_startproc 192 @ args = 0, pretend = 0, frame = 0 193 @ frame_needed = 1, uses_anonymous_args = 0 194 @ link register save eliminated. 195 0000 80B4 push {r7} 196 .cfi_def_cfa_offset 4 197 .cfi_offset 7, -4 ARM GAS /tmp/ccpm1fqH.s page 7 198 0002 00AF add r7, sp, #0 199 .cfi_def_cfa_register 7 159:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN DebugMonitor_IRQn 0 */ 160:Core/Src/stm32f3xx_it.c **** 161:Core/Src/stm32f3xx_it.c **** /* USER CODE END DebugMonitor_IRQn 0 */ 162:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN DebugMonitor_IRQn 1 */ 163:Core/Src/stm32f3xx_it.c **** 164:Core/Src/stm32f3xx_it.c **** /* USER CODE END DebugMonitor_IRQn 1 */ 165:Core/Src/stm32f3xx_it.c **** } 200 .loc 1 165 1 201 0004 00BF nop 202 0006 BD46 mov sp, r7 203 .cfi_def_cfa_register 13 204 @ sp needed 205 0008 5DF8047B ldr r7, [sp], #4 206 .cfi_restore 7 207 .cfi_def_cfa_offset 0 208 000c 7047 bx lr 209 .cfi_endproc 210 .LFE136: 212 .section .text.PendSV_Handler,"ax",%progbits 213 .align 1 214 .global PendSV_Handler 215 .syntax unified 216 .thumb 217 .thumb_func 219 PendSV_Handler: 220 .LFB137: 166:Core/Src/stm32f3xx_it.c **** 167:Core/Src/stm32f3xx_it.c **** /** 168:Core/Src/stm32f3xx_it.c **** * @brief This function handles Pendable request for system service. 169:Core/Src/stm32f3xx_it.c **** */ 170:Core/Src/stm32f3xx_it.c **** void PendSV_Handler(void) 171:Core/Src/stm32f3xx_it.c **** { 221 .loc 1 171 1 222 .cfi_startproc 223 @ args = 0, pretend = 0, frame = 0 224 @ frame_needed = 1, uses_anonymous_args = 0 225 @ link register save eliminated. 226 0000 80B4 push {r7} 227 .cfi_def_cfa_offset 4 228 .cfi_offset 7, -4 229 0002 00AF add r7, sp, #0 230 .cfi_def_cfa_register 7 172:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN PendSV_IRQn 0 */ 173:Core/Src/stm32f3xx_it.c **** 174:Core/Src/stm32f3xx_it.c **** /* USER CODE END PendSV_IRQn 0 */ 175:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN PendSV_IRQn 1 */ 176:Core/Src/stm32f3xx_it.c **** 177:Core/Src/stm32f3xx_it.c **** /* USER CODE END PendSV_IRQn 1 */ 178:Core/Src/stm32f3xx_it.c **** } 231 .loc 1 178 1 232 0004 00BF nop 233 0006 BD46 mov sp, r7 234 .cfi_def_cfa_register 13 235 @ sp needed 236 0008 5DF8047B ldr r7, [sp], #4 ARM GAS /tmp/ccpm1fqH.s page 8 237 .cfi_restore 7 238 .cfi_def_cfa_offset 0 239 000c 7047 bx lr 240 .cfi_endproc 241 .LFE137: 243 .section .text.SysTick_Handler,"ax",%progbits 244 .align 1 245 .global SysTick_Handler 246 .syntax unified 247 .thumb 248 .thumb_func 250 SysTick_Handler: 251 .LFB138: 179:Core/Src/stm32f3xx_it.c **** 180:Core/Src/stm32f3xx_it.c **** /** 181:Core/Src/stm32f3xx_it.c **** * @brief This function handles System tick timer. 182:Core/Src/stm32f3xx_it.c **** */ 183:Core/Src/stm32f3xx_it.c **** void SysTick_Handler(void) 184:Core/Src/stm32f3xx_it.c **** { 252 .loc 1 184 1 253 .cfi_startproc 254 @ args = 0, pretend = 0, frame = 0 255 @ frame_needed = 1, uses_anonymous_args = 0 256 0000 80B5 push {r7, lr} 257 .cfi_def_cfa_offset 8 258 .cfi_offset 7, -8 259 .cfi_offset 14, -4 260 0002 00AF add r7, sp, #0 261 .cfi_def_cfa_register 7 185:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN SysTick_IRQn 0 */ 186:Core/Src/stm32f3xx_it.c **** 187:Core/Src/stm32f3xx_it.c **** /* USER CODE END SysTick_IRQn 0 */ 188:Core/Src/stm32f3xx_it.c **** HAL_IncTick(); 262 .loc 1 188 3 263 0004 FFF7FEFF bl HAL_IncTick 189:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN SysTick_IRQn 1 */ 190:Core/Src/stm32f3xx_it.c **** 191:Core/Src/stm32f3xx_it.c **** /* USER CODE END SysTick_IRQn 1 */ 192:Core/Src/stm32f3xx_it.c **** } 264 .loc 1 192 1 265 0008 00BF nop 266 000a 80BD pop {r7, pc} 267 .cfi_endproc 268 .LFE138: 270 .section .text.USB_LP_CAN_RX0_IRQHandler,"ax",%progbits 271 .align 1 272 .global USB_LP_CAN_RX0_IRQHandler 273 .syntax unified 274 .thumb 275 .thumb_func 277 USB_LP_CAN_RX0_IRQHandler: 278 .LFB139: 193:Core/Src/stm32f3xx_it.c **** 194:Core/Src/stm32f3xx_it.c **** /******************************************************************************/ 195:Core/Src/stm32f3xx_it.c **** /* STM32F3xx Peripheral Interrupt Handlers */ 196:Core/Src/stm32f3xx_it.c **** /* Add here the Interrupt Handlers for the used peripherals. */ 197:Core/Src/stm32f3xx_it.c **** /* For the available peripheral interrupt handler names, */ ARM GAS /tmp/ccpm1fqH.s page 9 198:Core/Src/stm32f3xx_it.c **** /* please refer to the startup file (startup_stm32f3xx.s). */ 199:Core/Src/stm32f3xx_it.c **** /******************************************************************************/ 200:Core/Src/stm32f3xx_it.c **** 201:Core/Src/stm32f3xx_it.c **** /** 202:Core/Src/stm32f3xx_it.c **** * @brief This function handles USB low priority or CAN_RX0 interrupts. 203:Core/Src/stm32f3xx_it.c **** */ 204:Core/Src/stm32f3xx_it.c **** void USB_LP_CAN_RX0_IRQHandler(void) 205:Core/Src/stm32f3xx_it.c **** { 279 .loc 1 205 1 280 .cfi_startproc 281 @ args = 0, pretend = 0, frame = 0 282 @ frame_needed = 1, uses_anonymous_args = 0 283 0000 80B5 push {r7, lr} 284 .cfi_def_cfa_offset 8 285 .cfi_offset 7, -8 286 .cfi_offset 14, -4 287 0002 00AF add r7, sp, #0 288 .cfi_def_cfa_register 7 206:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN USB_LP_CAN_RX0_IRQn 0 */ 207:Core/Src/stm32f3xx_it.c **** 208:Core/Src/stm32f3xx_it.c **** /* USER CODE END USB_LP_CAN_RX0_IRQn 0 */ 209:Core/Src/stm32f3xx_it.c **** HAL_CAN_IRQHandler(&hcan); 289 .loc 1 209 3 290 0004 0248 ldr r0, .L16 291 0006 FFF7FEFF bl HAL_CAN_IRQHandler 210:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN USB_LP_CAN_RX0_IRQn 1 */ 211:Core/Src/stm32f3xx_it.c **** 212:Core/Src/stm32f3xx_it.c **** /* USER CODE END USB_LP_CAN_RX0_IRQn 1 */ 213:Core/Src/stm32f3xx_it.c **** } 292 .loc 1 213 1 293 000a 00BF nop 294 000c 80BD pop {r7, pc} 295 .L17: 296 000e 00BF .align 2 297 .L16: 298 0010 00000000 .word hcan 299 .cfi_endproc 300 .LFE139: 302 .section .text.CAN_RX1_IRQHandler,"ax",%progbits 303 .align 1 304 .global CAN_RX1_IRQHandler 305 .syntax unified 306 .thumb 307 .thumb_func 309 CAN_RX1_IRQHandler: 310 .LFB140: 214:Core/Src/stm32f3xx_it.c **** 215:Core/Src/stm32f3xx_it.c **** /** 216:Core/Src/stm32f3xx_it.c **** * @brief This function handles CAN RX1 interrupt. 217:Core/Src/stm32f3xx_it.c **** */ 218:Core/Src/stm32f3xx_it.c **** void CAN_RX1_IRQHandler(void) 219:Core/Src/stm32f3xx_it.c **** { 311 .loc 1 219 1 312 .cfi_startproc 313 @ args = 0, pretend = 0, frame = 0 314 @ frame_needed = 1, uses_anonymous_args = 0 315 0000 80B5 push {r7, lr} ARM GAS /tmp/ccpm1fqH.s page 10 316 .cfi_def_cfa_offset 8 317 .cfi_offset 7, -8 318 .cfi_offset 14, -4 319 0002 00AF add r7, sp, #0 320 .cfi_def_cfa_register 7 220:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN CAN_RX1_IRQn 0 */ 221:Core/Src/stm32f3xx_it.c **** 222:Core/Src/stm32f3xx_it.c **** /* USER CODE END CAN_RX1_IRQn 0 */ 223:Core/Src/stm32f3xx_it.c **** HAL_CAN_IRQHandler(&hcan); 321 .loc 1 223 3 322 0004 0248 ldr r0, .L19 323 0006 FFF7FEFF bl HAL_CAN_IRQHandler 224:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN CAN_RX1_IRQn 1 */ 225:Core/Src/stm32f3xx_it.c **** 226:Core/Src/stm32f3xx_it.c **** /* USER CODE END CAN_RX1_IRQn 1 */ 227:Core/Src/stm32f3xx_it.c **** } 324 .loc 1 227 1 325 000a 00BF nop 326 000c 80BD pop {r7, pc} 327 .L20: 328 000e 00BF .align 2 329 .L19: 330 0010 00000000 .word hcan 331 .cfi_endproc 332 .LFE140: 334 .text 335 .Letext0: 336 .file 2 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl 337 .file 3 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl 338 .file 4 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h" 339 .file 5 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h" 340 .file 6 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h" 341 .file 7 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h" ARM GAS /tmp/ccpm1fqH.s page 11 DEFINED SYMBOLS *ABS*:00000000 stm32f3xx_it.c /tmp/ccpm1fqH.s:21 .text.NMI_Handler:00000000 $t /tmp/ccpm1fqH.s:27 .text.NMI_Handler:00000000 NMI_Handler /tmp/ccpm1fqH.s:47 .text.HardFault_Handler:00000000 $t /tmp/ccpm1fqH.s:53 .text.HardFault_Handler:00000000 HardFault_Handler /tmp/ccpm1fqH.s:73 .text.MemManage_Handler:00000000 $t /tmp/ccpm1fqH.s:79 .text.MemManage_Handler:00000000 MemManage_Handler /tmp/ccpm1fqH.s:99 .text.BusFault_Handler:00000000 $t /tmp/ccpm1fqH.s:105 .text.BusFault_Handler:00000000 BusFault_Handler /tmp/ccpm1fqH.s:125 .text.UsageFault_Handler:00000000 $t /tmp/ccpm1fqH.s:131 .text.UsageFault_Handler:00000000 UsageFault_Handler /tmp/ccpm1fqH.s:151 .text.SVC_Handler:00000000 $t /tmp/ccpm1fqH.s:157 .text.SVC_Handler:00000000 SVC_Handler /tmp/ccpm1fqH.s:182 .text.DebugMon_Handler:00000000 $t /tmp/ccpm1fqH.s:188 .text.DebugMon_Handler:00000000 DebugMon_Handler /tmp/ccpm1fqH.s:213 .text.PendSV_Handler:00000000 $t /tmp/ccpm1fqH.s:219 .text.PendSV_Handler:00000000 PendSV_Handler /tmp/ccpm1fqH.s:244 .text.SysTick_Handler:00000000 $t /tmp/ccpm1fqH.s:250 .text.SysTick_Handler:00000000 SysTick_Handler /tmp/ccpm1fqH.s:271 .text.USB_LP_CAN_RX0_IRQHandler:00000000 $t /tmp/ccpm1fqH.s:277 .text.USB_LP_CAN_RX0_IRQHandler:00000000 USB_LP_CAN_RX0_IRQHandler /tmp/ccpm1fqH.s:298 .text.USB_LP_CAN_RX0_IRQHandler:00000010 $d /tmp/ccpm1fqH.s:303 .text.CAN_RX1_IRQHandler:00000000 $t /tmp/ccpm1fqH.s:309 .text.CAN_RX1_IRQHandler:00000000 CAN_RX1_IRQHandler /tmp/ccpm1fqH.s:330 .text.CAN_RX1_IRQHandler:00000010 $d UNDEFINED SYMBOLS HAL_IncTick HAL_CAN_IRQHandler hcan