ARM GAS /tmp/ccSuWkwR.s page 1 1 .cpu cortex-m4 2 .arch armv7e-m 3 .fpu fpv4-sp-d16 4 .eabi_attribute 27, 1 5 .eabi_attribute 28, 1 6 .eabi_attribute 20, 1 7 .eabi_attribute 21, 1 8 .eabi_attribute 23, 3 9 .eabi_attribute 24, 1 10 .eabi_attribute 25, 1 11 .eabi_attribute 26, 1 12 .eabi_attribute 30, 6 13 .eabi_attribute 34, 1 14 .eabi_attribute 18, 4 15 .file "stm32f3xx_hal_rcc.c" 16 .text 17 .Ltext0: 18 .cfi_sections .debug_frame 19 .file 1 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c" 20 .section .rodata.aPLLMULFactorTable,"a" 21 .align 2 24 aPLLMULFactorTable: 25 0000 02030405 .ascii "\002\003\004\005\006\007\010\011\012\013\014\015\016" 25 06070809 25 0A0B0C0D 25 0E 26 000d 0F1010 .ascii "\017\020\020" 27 .section .rodata.aPredivFactorTable,"a" 28 .align 2 31 aPredivFactorTable: 32 0000 01020304 .ascii "\001\002\003\004\005\006\007\010\011\012\013\014\015" 32 05060708 32 090A0B0C 32 0D 33 000d 0E0F10 .ascii "\016\017\020" 34 .section .text.HAL_RCC_DeInit,"ax",%progbits 35 .align 1 36 .global HAL_RCC_DeInit 37 .syntax unified 38 .thumb 39 .thumb_func 41 HAL_RCC_DeInit: 42 .LFB130: 1:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** 2:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** ****************************************************************************** 3:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @file stm32f3xx_hal_rcc.c 4:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @author MCD Application Team 5:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @brief RCC HAL module driver. 6:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * This file provides firmware functions to manage the following 7:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * functionalities of the Reset and Clock Control (RCC) peripheral: 8:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * + Initialization and de-initialization functions 9:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * + Peripheral Control functions 10:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * 11:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** @verbatim 12:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** ============================================================================== 13:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** ##### RCC specific features ##### 14:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** ============================================================================== ARM GAS /tmp/ccSuWkwR.s page 2 15:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** [..] 16:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** After reset the device is running from Internal High Speed oscillator 17:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is enabled, 18:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** and all peripherals are off except internal SRAM, Flash and JTAG. 19:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (+) There is no prescaler on High speed (AHB) and Low speed (APB) buses; 20:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** all peripherals mapped on these buses are running at HSI speed. 21:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (+) The clock for all peripherals is switched off, except the SRAM and FLASH. 22:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (+) All GPIOs are in input floating state, except the JTAG pins which 23:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** are assigned to be used for debug purpose. 24:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** [..] Once the device started from reset, the user application has to: 25:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (+) Configure the clock source to be used to drive the System clock 26:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (if the application needs higher frequency/performance) 27:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (+) Configure the System clock frequency and Flash settings 28:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (+) Configure the AHB and APB buses prescalers 29:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (+) Enable the clock for the peripheral(s) to be used 30:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (+) Configure the clock source(s) for peripherals whose clocks are not 31:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** derived from the System clock (RTC, ADC, I2C, I2S, TIM, USB FS) 32:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 33:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** ##### RCC Limitations ##### 34:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** ============================================================================== 35:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** [..] 36:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** A delay between an RCC peripheral clock enable and the effective peripheral 37:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** enabling should be taken into account in order to manage the peripheral read/write 38:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** from/to registers. 39:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (+) This delay depends on the peripheral mapping. 40:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (++) AHB & APB peripherals, 1 dummy read is necessary 41:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 42:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** [..] 43:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** Workarounds: 44:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (#) For AHB & APB peripherals, a dummy read to the peripheral register has been 45:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro. 46:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 47:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** @endverbatim 48:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** ****************************************************************************** 49:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @attention 50:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * 51:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * Copyright (c) 2016 STMicroelectronics. 52:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * All rights reserved. 53:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * 54:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * This software is licensed under terms that can be found in the LICENSE file in 55:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * the root directory of this software component. 56:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * If no LICENSE file comes with this software, it is provided AS-IS. 57:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** ****************************************************************************** 58:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ 59:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 60:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Includes ------------------------------------------------------------------*/ 61:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #include "stm32f3xx_hal.h" 62:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 63:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** @addtogroup STM32F3xx_HAL_Driver 64:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @{ 65:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ 66:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 67:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** @defgroup RCC RCC 68:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @brief RCC HAL module driver 69:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @{ 70:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ 71:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** ARM GAS /tmp/ccSuWkwR.s page 3 72:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #ifdef HAL_RCC_MODULE_ENABLED 73:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 74:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Private typedef -----------------------------------------------------------*/ 75:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Private define ------------------------------------------------------------*/ 76:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** @defgroup RCC_Private_Constants RCC Private Constants 77:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @{ 78:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ 79:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Bits position in in the CFGR register */ 80:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #define RCC_CFGR_HPRE_BITNUMBER POSITION_VAL(RCC_CFGR_HPRE) 81:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #define RCC_CFGR_PPRE1_BITNUMBER POSITION_VAL(RCC_CFGR_PPRE1) 82:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #define RCC_CFGR_PPRE2_BITNUMBER POSITION_VAL(RCC_CFGR_PPRE2) 83:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** 84:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @} 85:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ 86:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Private macro -------------------------------------------------------------*/ 87:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** @defgroup RCC_Private_Macros RCC Private Macros 88:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @{ 89:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ 90:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 91:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() 92:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #define MCO1_GPIO_PORT GPIOA 93:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #define MCO1_PIN GPIO_PIN_8 94:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 95:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** 96:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @} 97:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ 98:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 99:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Private variables ---------------------------------------------------------*/ 100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** @defgroup RCC_Private_Variables RCC Private Variables 101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @{ 102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ 103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** static const uint8_t aPLLMULFactorTable[16U] = { 2U, 3U, 4U, 5U, 6U, 7U, 8U, 9U, 104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 10U, 11U, 12U, 13U, 14U, 15U, 16U, 16U}; 105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** static const uint8_t aPredivFactorTable[16U] = { 1U, 2U, 3U, 4U, 5U, 6U, 7U, 8U, 106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 9U,10U, 11U, 12U, 13U, 14U, 15U, 16U}; 107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** 108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @} 109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ 110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Private function prototypes -----------------------------------------------*/ 112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Exported functions ---------------------------------------------------------*/ 113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** @defgroup RCC_Exported_Functions RCC Exported Functions 115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @{ 116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ 117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions 119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @brief Initialization and Configuration functions 120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * 121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** @verbatim 122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** =============================================================================== 123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** ##### Initialization and de-initialization functions ##### 124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** =============================================================================== 125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** [..] 126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** This section provides functions allowing to configure the internal/external oscillators 127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1 128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** and APB2). ARM GAS /tmp/ccSuWkwR.s page 4 129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** [..] Internal/external clock and PLL configuration 131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly or through 132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** the PLL as System clock source. 133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** The HSI clock can be used also to clock the USART and I2C peripherals. 134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (#) LSI (low-speed internal), ~40 KHz low consumption RC used as IWDG and/or RTC 136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** clock source. 137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (#) HSE (high-speed external), 4 to 32 MHz crystal oscillator used directly or 139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** through the PLL as System clock source. Can be used also as RTC clock source. 140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. 142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (#) PLL (clocked by HSI or HSE), featuring different output clocks: 144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (++) The first output is used to generate the high speed system clock (up to 72 MHz) 145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (++) The second output is used to generate the clock for the USB FS (48 MHz) 146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (++) The third output may be used to generate the clock for the ADC peripherals (up to 72 M 147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (++) The fourth output may be used to generate the clock for the TIM peripherals (144 MHz) 148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE() 150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** and if a HSE clock failure occurs(HSE used directly or through PLL as System 151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** clock source), the System clocks automatically switched to HSI and an interrupt 152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** is generated if enabled. The interrupt is linked to the Cortex-M4 NMI 153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (Non-Maskable Interrupt) exception vector. 154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (#) MCO (microcontroller clock output), used to output SYSCLK, HSI, HSE, LSI, LSE or PLL 156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** clock (divided by 2) output on pin (such as PA8 pin). 157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** [..] System, AHB and APB buses clocks configuration 159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI, 160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** HSE and PLL. 161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** The AHB clock (HCLK) is derived from System clock through configurable 162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** prescaler and used to clock the CPU, memory and peripherals mapped 163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived 164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** from AHB clock through configurable prescalers and used to clock 165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** the peripherals mapped on these buses. You can use 166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. 167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (#) All the peripheral clocks are derived from the System clock (SYSCLK) except: 169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (++) The FLASH program/erase clock which is always HSI 8MHz clock. 170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (++) The USB 48 MHz clock which is derived from the PLL VCO clock. 171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (++) The USART clock which can be derived as well from HSI 8MHz, LSI or LSE. 172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (++) The I2C clock which can be derived as well from HSI 8MHz clock. 173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (++) The ADC clock which is derived from PLL output. 174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (++) The RTC clock which is derived from the LSE, LSI or 1 MHz HSE_RTC 175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (HSE divided by a programmable prescaler). The System clock (SYSCLK) 176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** frequency must be higher or equal to the RTC clock frequency. 177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (++) IWDG clock which is always the LSI clock. 178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (#) For the STM32F3xx devices, the maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** Depending on the SYSCLK frequency, the flash latency should be adapted accordingly. 181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (#) After reset, the System clock source is the HSI (8 MHz) with 0 WS and 183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** prefetch is disabled. 184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** @endverbatim 185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @{ ARM GAS /tmp/ccSuWkwR.s page 5 186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ 187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* 189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** Additional consideration on the SYSCLK based on Latency settings: 190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** +-----------------------------------------------+ 191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** | Latency | SYSCLK clock frequency (MHz) | 192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** |---------------|-------------------------------| 193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** |0WS(1CPU cycle)| 0 < SYSCLK <= 24 | 194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** |---------------|-------------------------------| 195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** |1WS(2CPU cycle)| 24 < SYSCLK <= 48 | 196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** |---------------|-------------------------------| 197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** |2WS(3CPU cycle)| 48 < SYSCLK <= 72 | 198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** +-----------------------------------------------+ 199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ 200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** 202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @brief Resets the RCC clock configuration to the default reset state. 203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note The default reset state of the clock configuration is given below: 204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * - HSI ON and used as system clock source 205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * - HSE and PLL OFF 206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * - AHB, APB1 and APB2 prescaler set to 1. 207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * - CSS and MCO1 OFF 208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * - All interrupts disabled 209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note This function does not modify the configuration of the 210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * - Peripheral clocks 211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * - LSI, LSE and RTC clocks 212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @retval HAL status 213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ 214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** HAL_StatusTypeDef HAL_RCC_DeInit(void) 215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 43 .loc 1 215 1 44 .cfi_startproc 45 @ args = 0, pretend = 0, frame = 16 46 @ frame_needed = 1, uses_anonymous_args = 0 47 0000 80B5 push {r7, lr} 48 .cfi_def_cfa_offset 8 49 .cfi_offset 7, -8 50 .cfi_offset 14, -4 51 0002 84B0 sub sp, sp, #16 52 .cfi_def_cfa_offset 24 53 0004 00AF add r7, sp, #0 54 .cfi_def_cfa_register 7 216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** uint32_t tickstart = 0; 55 .loc 1 216 12 56 0006 0023 movs r3, #0 57 0008 FB60 str r3, [r7, #12] 217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Set HSION bit */ 219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** SET_BIT(RCC->CR, RCC_CR_HSION); 58 .loc 1 219 3 59 000a 494B ldr r3, .L11 60 000c 1B68 ldr r3, [r3] 61 000e 484A ldr r2, .L11 62 0010 43F00103 orr r3, r3, #1 63 0014 1360 str r3, [r2] 220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Insure HSIRDY bit is set before writing default HSITRIM value */ ARM GAS /tmp/ccSuWkwR.s page 6 222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get start tick */ 223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** tickstart = HAL_GetTick(); 64 .loc 1 223 15 65 0016 FFF7FEFF bl HAL_GetTick 66 001a F860 str r0, [r7, #12] 224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Wait till HSI is ready */ 226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET) 67 .loc 1 226 8 68 001c 08E0 b .L2 69 .L4: 227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 70 .loc 1 228 9 71 001e FFF7FEFF bl HAL_GetTick 72 0022 0246 mov r2, r0 73 .loc 1 228 23 discriminator 1 74 0024 FB68 ldr r3, [r7, #12] 75 0026 D31A subs r3, r2, r3 76 .loc 1 228 7 discriminator 1 77 0028 022B cmp r3, #2 78 002a 01D9 bls .L2 229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_TIMEOUT; 79 .loc 1 230 14 80 002c 0323 movs r3, #3 81 002e 7BE0 b .L3 82 .L2: 226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 83 .loc 1 226 9 84 0030 3F4B ldr r3, .L11 85 0032 1B68 ldr r3, [r3] 86 0034 03F00203 and r3, r3, #2 226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 87 .loc 1 226 42 88 0038 002B cmp r3, #0 89 003a F0D0 beq .L4 231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Set HSITRIM default value */ 235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, RCC_CR_HSITRIM_4); 90 .loc 1 235 3 91 003c 3C4B ldr r3, .L11 92 003e 1B68 ldr r3, [r3] 93 0040 23F0F803 bic r3, r3, #248 94 0044 3A4A ldr r2, .L11 95 0046 43F08003 orr r3, r3, #128 96 004a 1360 str r3, [r2] 236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0] and MCOSEL[2:0] bits */ 238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE1 | RCC_CFGR_PPRE2 | RCC_CFGR_MCO 97 .loc 1 238 3 98 004c 384B ldr r3, .L11 99 004e 5A68 ldr r2, [r3, #4] 100 0050 3749 ldr r1, .L11 101 0052 384B ldr r3, .L11+4 ARM GAS /tmp/ccSuWkwR.s page 7 102 0054 1340 ands r3, r3, r2 103 0056 4B60 str r3, [r1, #4] 239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Insure HSI selected as system clock source */ 241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get start tick */ 242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** tickstart = HAL_GetTick(); 104 .loc 1 242 15 105 0058 FFF7FEFF bl HAL_GetTick 106 005c F860 str r0, [r7, #12] 243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Wait till system clock source is ready */ 245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** while(READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) 107 .loc 1 245 8 108 005e 0AE0 b .L5 109 .L6: 246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 110 .loc 1 247 9 111 0060 FFF7FEFF bl HAL_GetTick 112 0064 0246 mov r2, r0 113 .loc 1 247 23 discriminator 1 114 0066 FB68 ldr r3, [r7, #12] 115 0068 D31A subs r3, r2, r3 116 .loc 1 247 7 discriminator 1 117 006a 41F28832 movw r2, #5000 118 006e 9342 cmp r3, r2 119 0070 01D9 bls .L5 248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_TIMEOUT; 120 .loc 1 249 14 121 0072 0323 movs r3, #3 122 0074 58E0 b .L3 123 .L5: 245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 124 .loc 1 245 9 125 0076 2E4B ldr r3, .L11 126 0078 5B68 ldr r3, [r3, #4] 127 007a 03F00C03 and r3, r3, #12 245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 128 .loc 1 245 43 129 007e 002B cmp r3, #0 130 0080 EED1 bne .L6 250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Update the SystemCoreClock global variable for HSI as system clock source */ 254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** SystemCoreClock = HSI_VALUE; 131 .loc 1 254 19 132 0082 2D4B ldr r3, .L11+8 133 0084 2D4A ldr r2, .L11+12 134 0086 1A60 str r2, [r3] 255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Configure the source of time base considering new system clock settings */ 257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(HAL_InitTick(uwTickPrio) != HAL_OK) 135 .loc 1 257 6 136 0088 2D4B ldr r3, .L11+16 137 008a 1B68 ldr r3, [r3] ARM GAS /tmp/ccSuWkwR.s page 8 138 008c 1846 mov r0, r3 139 008e FFF7FEFF bl HAL_InitTick 140 0092 0346 mov r3, r0 141 .loc 1 257 5 discriminator 1 142 0094 002B cmp r3, #0 143 0096 01D0 beq .L7 258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_ERROR; 144 .loc 1 259 12 145 0098 0123 movs r3, #1 146 009a 45E0 b .L3 147 .L7: 260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Reset HSEON, CSSON, PLLON bits */ 263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** CLEAR_BIT(RCC->CR, RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_HSEON); 148 .loc 1 263 3 149 009c 244B ldr r3, .L11 150 009e 1B68 ldr r3, [r3] 151 00a0 234A ldr r2, .L11 152 00a2 23F08473 bic r3, r3, #17301504 153 00a6 23F48033 bic r3, r3, #65536 154 00aa 1360 str r3, [r2] 264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Reset HSEBYP bit */ 266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); 155 .loc 1 266 3 156 00ac 204B ldr r3, .L11 157 00ae 1B68 ldr r3, [r3] 158 00b0 1F4A ldr r2, .L11 159 00b2 23F48023 bic r3, r3, #262144 160 00b6 1360 str r3, [r2] 267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Insure PLLRDY is reset */ 269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get start tick */ 270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** tickstart = HAL_GetTick(); 161 .loc 1 270 15 162 00b8 FFF7FEFF bl HAL_GetTick 163 00bc F860 str r0, [r7, #12] 271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) 164 .loc 1 271 8 165 00be 08E0 b .L8 166 .L9: 272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 167 .loc 1 273 9 168 00c0 FFF7FEFF bl HAL_GetTick 169 00c4 0246 mov r2, r0 170 .loc 1 273 23 discriminator 1 171 00c6 FB68 ldr r3, [r7, #12] 172 00c8 D31A subs r3, r2, r3 173 .loc 1 273 7 discriminator 1 174 00ca 022B cmp r3, #2 175 00cc 01D9 bls .L8 274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_TIMEOUT; 176 .loc 1 275 14 ARM GAS /tmp/ccSuWkwR.s page 9 177 00ce 0323 movs r3, #3 178 00d0 2AE0 b .L3 179 .L8: 271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 180 .loc 1 271 9 181 00d2 174B ldr r3, .L11 182 00d4 1B68 ldr r3, [r3] 183 00d6 03F00073 and r3, r3, #33554432 271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 184 .loc 1 271 42 185 00da 002B cmp r3, #0 186 00dc F0D1 bne .L9 276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Reset CFGR register */ 280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** CLEAR_REG(RCC->CFGR); 187 .loc 1 280 3 188 00de 144B ldr r3, .L11 189 00e0 0022 movs r2, #0 190 00e2 5A60 str r2, [r3, #4] 281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Reset CFGR2 register */ 283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** CLEAR_REG(RCC->CFGR2); 191 .loc 1 283 3 192 00e4 124B ldr r3, .L11 193 00e6 0022 movs r2, #0 194 00e8 DA62 str r2, [r3, #44] 284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Reset CFGR3 register */ 286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** CLEAR_REG(RCC->CFGR3); 195 .loc 1 286 3 196 00ea 114B ldr r3, .L11 197 00ec 0022 movs r2, #0 198 00ee 1A63 str r2, [r3, #48] 287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Clear all interrupt flags */ 289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR 199 .loc 1 289 3 200 00f0 0F4B ldr r3, .L11 201 00f2 9B68 ldr r3, [r3, #8] 202 00f4 0E4A ldr r2, .L11 203 00f6 43F41F03 orr r3, r3, #10420224 204 00fa 9360 str r3, [r2, #8] 290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Disable all interrupts */ 292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** CLEAR_REG(RCC->CIR); 205 .loc 1 292 3 206 00fc 0C4B ldr r3, .L11 207 00fe 0022 movs r2, #0 208 0100 9A60 str r2, [r3, #8] 209 0102 4FF08073 mov r3, #16777216 210 0106 BB60 str r3, [r7, #8] 211 .LBB168: 212 .LBB169: 213 .file 2 "Drivers/CMSIS/Include/cmsis_gcc.h" 1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//** ARM GAS /tmp/ccSuWkwR.s page 10 2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h 3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS compiler GCC header file 4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V5.0.4 5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 09. April 2018 6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/ 7:Drivers/CMSIS/Include/cmsis_gcc.h **** /* 8:Drivers/CMSIS/Include/cmsis_gcc.h **** * Copyright (c) 2009-2018 Arm Limited. All rights reserved. 9:Drivers/CMSIS/Include/cmsis_gcc.h **** * 10:Drivers/CMSIS/Include/cmsis_gcc.h **** * SPDX-License-Identifier: Apache-2.0 11:Drivers/CMSIS/Include/cmsis_gcc.h **** * 12:Drivers/CMSIS/Include/cmsis_gcc.h **** * Licensed under the Apache License, Version 2.0 (the License); you may 13:Drivers/CMSIS/Include/cmsis_gcc.h **** * not use this file except in compliance with the License. 14:Drivers/CMSIS/Include/cmsis_gcc.h **** * You may obtain a copy of the License at 15:Drivers/CMSIS/Include/cmsis_gcc.h **** * 16:Drivers/CMSIS/Include/cmsis_gcc.h **** * www.apache.org/licenses/LICENSE-2.0 17:Drivers/CMSIS/Include/cmsis_gcc.h **** * 18:Drivers/CMSIS/Include/cmsis_gcc.h **** * Unless required by applicable law or agreed to in writing, software 19:Drivers/CMSIS/Include/cmsis_gcc.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20:Drivers/CMSIS/Include/cmsis_gcc.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21:Drivers/CMSIS/Include/cmsis_gcc.h **** * See the License for the specific language governing permissions and 22:Drivers/CMSIS/Include/cmsis_gcc.h **** * limitations under the License. 23:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 24:Drivers/CMSIS/Include/cmsis_gcc.h **** 25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H 26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H 27:Drivers/CMSIS/Include/cmsis_gcc.h **** 28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */ 29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion" 31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion" 32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter" 33:Drivers/CMSIS/Include/cmsis_gcc.h **** 34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */ 35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin 36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __has_builtin(x) (0) 37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 38:Drivers/CMSIS/Include/cmsis_gcc.h **** 39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */ 40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ASM 41:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ASM __asm 42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INLINE 44:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INLINE inline 45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_INLINE 47:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_INLINE static inline 48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_FORCEINLINE 50:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline 51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __NO_RETURN 53:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NO_RETURN __attribute__((__noreturn__)) 54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __USED 56:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USED __attribute__((used)) 57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __WEAK ARM GAS /tmp/ccSuWkwR.s page 11 59:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WEAK __attribute__((weak)) 60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED 62:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED __attribute__((packed, aligned(1))) 63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_STRUCT 65:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) 66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_UNION 68:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_UNION union __attribute__((packed, aligned(1))) 69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32 /* deprecated */ 71:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 72:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 73:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 74:Drivers/CMSIS/Include/cmsis_gcc.h **** struct __attribute__((packed)) T_UINT32 { uint32_t v; }; 75:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 76:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) 77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_WRITE 79:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 80:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 81:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 82:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; 83:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 84:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))- 85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_READ 87:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 88:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 89:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 90:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; 91:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 92:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(add 93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_WRITE 95:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 96:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 97:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 98:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; 99:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 100:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))- 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_READ 103:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 104:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 105:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 106:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; 107:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 108:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(add 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ALIGNED 111:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ALIGNED(x) __attribute__((aligned(x))) 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __RESTRICT 114:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __RESTRICT __restrict 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif ARM GAS /tmp/ccSuWkwR.s page 12 116:Drivers/CMSIS/Include/cmsis_gcc.h **** 117:Drivers/CMSIS/Include/cmsis_gcc.h **** 118:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */ 119:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface 120:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions 121:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ 122:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 123:Drivers/CMSIS/Include/cmsis_gcc.h **** 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 125:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts 126:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR. 127:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. 128:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 129:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void) 130:Drivers/CMSIS/Include/cmsis_gcc.h **** { 131:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory"); 132:Drivers/CMSIS/Include/cmsis_gcc.h **** } 133:Drivers/CMSIS/Include/cmsis_gcc.h **** 134:Drivers/CMSIS/Include/cmsis_gcc.h **** 135:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 136:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts 137:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR. 138:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. 139:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 140:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void) 141:Drivers/CMSIS/Include/cmsis_gcc.h **** { 142:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory"); 143:Drivers/CMSIS/Include/cmsis_gcc.h **** } 144:Drivers/CMSIS/Include/cmsis_gcc.h **** 145:Drivers/CMSIS/Include/cmsis_gcc.h **** 146:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 147:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register 148:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the Control Register. 149:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Control Register value 150:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 151:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_CONTROL(void) 152:Drivers/CMSIS/Include/cmsis_gcc.h **** { 153:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 154:Drivers/CMSIS/Include/cmsis_gcc.h **** 155:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control" : "=r" (result) ); 156:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 157:Drivers/CMSIS/Include/cmsis_gcc.h **** } 158:Drivers/CMSIS/Include/cmsis_gcc.h **** 159:Drivers/CMSIS/Include/cmsis_gcc.h **** 160:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 161:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 162:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register (non-secure) 163:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the non-secure Control Register when in secure mode. 164:Drivers/CMSIS/Include/cmsis_gcc.h **** \return non-secure Control Register value 165:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 166:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) 167:Drivers/CMSIS/Include/cmsis_gcc.h **** { 168:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 169:Drivers/CMSIS/Include/cmsis_gcc.h **** 170:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); 171:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 172:Drivers/CMSIS/Include/cmsis_gcc.h **** } ARM GAS /tmp/ccSuWkwR.s page 13 173:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 174:Drivers/CMSIS/Include/cmsis_gcc.h **** 175:Drivers/CMSIS/Include/cmsis_gcc.h **** 176:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 177:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register 178:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the Control Register. 179:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set 180:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 181:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) 182:Drivers/CMSIS/Include/cmsis_gcc.h **** { 183:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); 184:Drivers/CMSIS/Include/cmsis_gcc.h **** } 185:Drivers/CMSIS/Include/cmsis_gcc.h **** 186:Drivers/CMSIS/Include/cmsis_gcc.h **** 187:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 188:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 189:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register (non-secure) 190:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the non-secure Control Register when in secure state. 191:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set 192:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 193:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) 194:Drivers/CMSIS/Include/cmsis_gcc.h **** { 195:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); 196:Drivers/CMSIS/Include/cmsis_gcc.h **** } 197:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 198:Drivers/CMSIS/Include/cmsis_gcc.h **** 199:Drivers/CMSIS/Include/cmsis_gcc.h **** 200:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 201:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get IPSR Register 202:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the IPSR Register. 203:Drivers/CMSIS/Include/cmsis_gcc.h **** \return IPSR Register value 204:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 205:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void) 206:Drivers/CMSIS/Include/cmsis_gcc.h **** { 207:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 208:Drivers/CMSIS/Include/cmsis_gcc.h **** 209:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 210:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 211:Drivers/CMSIS/Include/cmsis_gcc.h **** } 212:Drivers/CMSIS/Include/cmsis_gcc.h **** 213:Drivers/CMSIS/Include/cmsis_gcc.h **** 214:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 215:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get APSR Register 216:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the APSR Register. 217:Drivers/CMSIS/Include/cmsis_gcc.h **** \return APSR Register value 218:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 219:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_APSR(void) 220:Drivers/CMSIS/Include/cmsis_gcc.h **** { 221:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 222:Drivers/CMSIS/Include/cmsis_gcc.h **** 223:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, apsr" : "=r" (result) ); 224:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 225:Drivers/CMSIS/Include/cmsis_gcc.h **** } 226:Drivers/CMSIS/Include/cmsis_gcc.h **** 227:Drivers/CMSIS/Include/cmsis_gcc.h **** 228:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 229:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get xPSR Register ARM GAS /tmp/ccSuWkwR.s page 14 230:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the xPSR Register. 231:Drivers/CMSIS/Include/cmsis_gcc.h **** \return xPSR Register value 232:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 233:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_xPSR(void) 234:Drivers/CMSIS/Include/cmsis_gcc.h **** { 235:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 236:Drivers/CMSIS/Include/cmsis_gcc.h **** 237:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); 238:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 239:Drivers/CMSIS/Include/cmsis_gcc.h **** } 240:Drivers/CMSIS/Include/cmsis_gcc.h **** 241:Drivers/CMSIS/Include/cmsis_gcc.h **** 242:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 243:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer 244:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer (PSP). 245:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value 246:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 247:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSP(void) 248:Drivers/CMSIS/Include/cmsis_gcc.h **** { 249:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 250:Drivers/CMSIS/Include/cmsis_gcc.h **** 251:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp" : "=r" (result) ); 252:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 253:Drivers/CMSIS/Include/cmsis_gcc.h **** } 254:Drivers/CMSIS/Include/cmsis_gcc.h **** 255:Drivers/CMSIS/Include/cmsis_gcc.h **** 256:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 257:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 258:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer (non-secure) 259:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure s 260:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value 261:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 262:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) 263:Drivers/CMSIS/Include/cmsis_gcc.h **** { 264:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 265:Drivers/CMSIS/Include/cmsis_gcc.h **** 266:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); 267:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 268:Drivers/CMSIS/Include/cmsis_gcc.h **** } 269:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 270:Drivers/CMSIS/Include/cmsis_gcc.h **** 271:Drivers/CMSIS/Include/cmsis_gcc.h **** 272:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 273:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer 274:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer (PSP). 275:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set 276:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 277:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) 278:Drivers/CMSIS/Include/cmsis_gcc.h **** { 279:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); 280:Drivers/CMSIS/Include/cmsis_gcc.h **** } 281:Drivers/CMSIS/Include/cmsis_gcc.h **** 282:Drivers/CMSIS/Include/cmsis_gcc.h **** 283:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 284:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 285:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) 286:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure sta ARM GAS /tmp/ccSuWkwR.s page 15 287:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set 288:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 289:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) 290:Drivers/CMSIS/Include/cmsis_gcc.h **** { 291:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); 292:Drivers/CMSIS/Include/cmsis_gcc.h **** } 293:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 294:Drivers/CMSIS/Include/cmsis_gcc.h **** 295:Drivers/CMSIS/Include/cmsis_gcc.h **** 296:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 297:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer 298:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer (MSP). 299:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value 300:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 301:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSP(void) 302:Drivers/CMSIS/Include/cmsis_gcc.h **** { 303:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 304:Drivers/CMSIS/Include/cmsis_gcc.h **** 305:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp" : "=r" (result) ); 306:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 307:Drivers/CMSIS/Include/cmsis_gcc.h **** } 308:Drivers/CMSIS/Include/cmsis_gcc.h **** 309:Drivers/CMSIS/Include/cmsis_gcc.h **** 310:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 311:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 312:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer (non-secure) 313:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure stat 314:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value 315:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 316:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) 317:Drivers/CMSIS/Include/cmsis_gcc.h **** { 318:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 319:Drivers/CMSIS/Include/cmsis_gcc.h **** 320:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); 321:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 322:Drivers/CMSIS/Include/cmsis_gcc.h **** } 323:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 324:Drivers/CMSIS/Include/cmsis_gcc.h **** 325:Drivers/CMSIS/Include/cmsis_gcc.h **** 326:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 327:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer 328:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer (MSP). 329:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set 330:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 331:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) 332:Drivers/CMSIS/Include/cmsis_gcc.h **** { 333:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); 334:Drivers/CMSIS/Include/cmsis_gcc.h **** } 335:Drivers/CMSIS/Include/cmsis_gcc.h **** 336:Drivers/CMSIS/Include/cmsis_gcc.h **** 337:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 338:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 339:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer (non-secure) 340:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. 341:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set 342:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 343:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) ARM GAS /tmp/ccSuWkwR.s page 16 344:Drivers/CMSIS/Include/cmsis_gcc.h **** { 345:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); 346:Drivers/CMSIS/Include/cmsis_gcc.h **** } 347:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 348:Drivers/CMSIS/Include/cmsis_gcc.h **** 349:Drivers/CMSIS/Include/cmsis_gcc.h **** 350:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 351:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 352:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Stack Pointer (non-secure) 353:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. 354:Drivers/CMSIS/Include/cmsis_gcc.h **** \return SP Register value 355:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 356:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) 357:Drivers/CMSIS/Include/cmsis_gcc.h **** { 358:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 359:Drivers/CMSIS/Include/cmsis_gcc.h **** 360:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); 361:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 362:Drivers/CMSIS/Include/cmsis_gcc.h **** } 363:Drivers/CMSIS/Include/cmsis_gcc.h **** 364:Drivers/CMSIS/Include/cmsis_gcc.h **** 365:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 366:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Stack Pointer (non-secure) 367:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. 368:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfStack Stack Pointer value to set 369:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 370:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) 371:Drivers/CMSIS/Include/cmsis_gcc.h **** { 372:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); 373:Drivers/CMSIS/Include/cmsis_gcc.h **** } 374:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 375:Drivers/CMSIS/Include/cmsis_gcc.h **** 376:Drivers/CMSIS/Include/cmsis_gcc.h **** 377:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 378:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask 379:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the priority mask bit from the Priority Mask Register. 380:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value 381:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 382:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) 383:Drivers/CMSIS/Include/cmsis_gcc.h **** { 384:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 385:Drivers/CMSIS/Include/cmsis_gcc.h **** 386:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 387:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 388:Drivers/CMSIS/Include/cmsis_gcc.h **** } 389:Drivers/CMSIS/Include/cmsis_gcc.h **** 390:Drivers/CMSIS/Include/cmsis_gcc.h **** 391:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 392:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 393:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask (non-secure) 394:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the non-secure priority mask bit from the Priority Mask Reg 395:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value 396:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 397:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) 398:Drivers/CMSIS/Include/cmsis_gcc.h **** { 399:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 400:Drivers/CMSIS/Include/cmsis_gcc.h **** ARM GAS /tmp/ccSuWkwR.s page 17 401:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); 402:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 403:Drivers/CMSIS/Include/cmsis_gcc.h **** } 404:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 405:Drivers/CMSIS/Include/cmsis_gcc.h **** 406:Drivers/CMSIS/Include/cmsis_gcc.h **** 407:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 408:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask 409:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Priority Mask Register. 410:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask 411:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 412:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) 413:Drivers/CMSIS/Include/cmsis_gcc.h **** { 414:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 415:Drivers/CMSIS/Include/cmsis_gcc.h **** } 416:Drivers/CMSIS/Include/cmsis_gcc.h **** 417:Drivers/CMSIS/Include/cmsis_gcc.h **** 418:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 419:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 420:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask (non-secure) 421:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Priority Mask Register when in secure state. 422:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask 423:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 424:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) 425:Drivers/CMSIS/Include/cmsis_gcc.h **** { 426:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); 427:Drivers/CMSIS/Include/cmsis_gcc.h **** } 428:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 429:Drivers/CMSIS/Include/cmsis_gcc.h **** 430:Drivers/CMSIS/Include/cmsis_gcc.h **** 431:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 432:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 433:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) 434:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 435:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable FIQ 436:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables FIQ interrupts by clearing the F-bit in the CPSR. 437:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. 438:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 439:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_fault_irq(void) 440:Drivers/CMSIS/Include/cmsis_gcc.h **** { 441:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie f" : : : "memory"); 442:Drivers/CMSIS/Include/cmsis_gcc.h **** } 443:Drivers/CMSIS/Include/cmsis_gcc.h **** 444:Drivers/CMSIS/Include/cmsis_gcc.h **** 445:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 446:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable FIQ 447:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables FIQ interrupts by setting the F-bit in the CPSR. 448:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. 449:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 450:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_fault_irq(void) 451:Drivers/CMSIS/Include/cmsis_gcc.h **** { 452:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid f" : : : "memory"); 453:Drivers/CMSIS/Include/cmsis_gcc.h **** } 454:Drivers/CMSIS/Include/cmsis_gcc.h **** 455:Drivers/CMSIS/Include/cmsis_gcc.h **** 456:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 457:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority ARM GAS /tmp/ccSuWkwR.s page 18 458:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Base Priority register. 459:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value 460:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 461:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) 462:Drivers/CMSIS/Include/cmsis_gcc.h **** { 463:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 464:Drivers/CMSIS/Include/cmsis_gcc.h **** 465:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri" : "=r" (result) ); 466:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 467:Drivers/CMSIS/Include/cmsis_gcc.h **** } 468:Drivers/CMSIS/Include/cmsis_gcc.h **** 469:Drivers/CMSIS/Include/cmsis_gcc.h **** 470:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 471:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 472:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority (non-secure) 473:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Base Priority register when in secure state. 474:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value 475:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 476:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) 477:Drivers/CMSIS/Include/cmsis_gcc.h **** { 478:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 479:Drivers/CMSIS/Include/cmsis_gcc.h **** 480:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); 481:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 482:Drivers/CMSIS/Include/cmsis_gcc.h **** } 483:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 484:Drivers/CMSIS/Include/cmsis_gcc.h **** 485:Drivers/CMSIS/Include/cmsis_gcc.h **** 486:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 487:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority 488:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register. 489:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set 490:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 491:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) 492:Drivers/CMSIS/Include/cmsis_gcc.h **** { 493:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); 494:Drivers/CMSIS/Include/cmsis_gcc.h **** } 495:Drivers/CMSIS/Include/cmsis_gcc.h **** 496:Drivers/CMSIS/Include/cmsis_gcc.h **** 497:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 498:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 499:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority (non-secure) 500:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Base Priority register when in secure state. 501:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set 502:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 503:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) 504:Drivers/CMSIS/Include/cmsis_gcc.h **** { 505:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); 506:Drivers/CMSIS/Include/cmsis_gcc.h **** } 507:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 508:Drivers/CMSIS/Include/cmsis_gcc.h **** 509:Drivers/CMSIS/Include/cmsis_gcc.h **** 510:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 511:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority with condition 512:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable 513:Drivers/CMSIS/Include/cmsis_gcc.h **** or the new value increases the BASEPRI priority level. 514:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set ARM GAS /tmp/ccSuWkwR.s page 19 515:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 516:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) 517:Drivers/CMSIS/Include/cmsis_gcc.h **** { 518:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); 519:Drivers/CMSIS/Include/cmsis_gcc.h **** } 520:Drivers/CMSIS/Include/cmsis_gcc.h **** 521:Drivers/CMSIS/Include/cmsis_gcc.h **** 522:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 523:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask 524:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Fault Mask register. 525:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value 526:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 527:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) 528:Drivers/CMSIS/Include/cmsis_gcc.h **** { 529:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 530:Drivers/CMSIS/Include/cmsis_gcc.h **** 531:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); 532:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 533:Drivers/CMSIS/Include/cmsis_gcc.h **** } 534:Drivers/CMSIS/Include/cmsis_gcc.h **** 535:Drivers/CMSIS/Include/cmsis_gcc.h **** 536:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 537:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 538:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask (non-secure) 539:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Fault Mask register when in secure state. 540:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value 541:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 542:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) 543:Drivers/CMSIS/Include/cmsis_gcc.h **** { 544:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 545:Drivers/CMSIS/Include/cmsis_gcc.h **** 546:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); 547:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 548:Drivers/CMSIS/Include/cmsis_gcc.h **** } 549:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 550:Drivers/CMSIS/Include/cmsis_gcc.h **** 551:Drivers/CMSIS/Include/cmsis_gcc.h **** 552:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 553:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask 554:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Fault Mask register. 555:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set 556:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 557:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) 558:Drivers/CMSIS/Include/cmsis_gcc.h **** { 559:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); 560:Drivers/CMSIS/Include/cmsis_gcc.h **** } 561:Drivers/CMSIS/Include/cmsis_gcc.h **** 562:Drivers/CMSIS/Include/cmsis_gcc.h **** 563:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 564:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 565:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask (non-secure) 566:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Fault Mask register when in secure state. 567:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set 568:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 569:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) 570:Drivers/CMSIS/Include/cmsis_gcc.h **** { 571:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); ARM GAS /tmp/ccSuWkwR.s page 20 572:Drivers/CMSIS/Include/cmsis_gcc.h **** } 573:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 574:Drivers/CMSIS/Include/cmsis_gcc.h **** 575:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 576:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 577:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ 578:Drivers/CMSIS/Include/cmsis_gcc.h **** 579:Drivers/CMSIS/Include/cmsis_gcc.h **** 580:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 581:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) 582:Drivers/CMSIS/Include/cmsis_gcc.h **** 583:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 584:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit 585:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 586:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure 587:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. 588:Drivers/CMSIS/Include/cmsis_gcc.h **** 589:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). 590:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value 591:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 592:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) 593:Drivers/CMSIS/Include/cmsis_gcc.h **** { 594:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 595:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) 596:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI 597:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; 598:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 599:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 600:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim" : "=r" (result) ); 601:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 602:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 603:Drivers/CMSIS/Include/cmsis_gcc.h **** } 604:Drivers/CMSIS/Include/cmsis_gcc.h **** 605:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) 606:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 607:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit (non-secure) 608:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 609:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. 610:Drivers/CMSIS/Include/cmsis_gcc.h **** 611:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in 612:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value 613:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 614:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) 615:Drivers/CMSIS/Include/cmsis_gcc.h **** { 616:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) 617:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI 618:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; 619:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 620:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 621:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); 622:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 623:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 624:Drivers/CMSIS/Include/cmsis_gcc.h **** } 625:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 626:Drivers/CMSIS/Include/cmsis_gcc.h **** 627:Drivers/CMSIS/Include/cmsis_gcc.h **** 628:Drivers/CMSIS/Include/cmsis_gcc.h **** /** ARM GAS /tmp/ccSuWkwR.s page 21 629:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer Limit 630:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 631:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure 632:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. 633:Drivers/CMSIS/Include/cmsis_gcc.h **** 634:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). 635:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set 636:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 637:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) 638:Drivers/CMSIS/Include/cmsis_gcc.h **** { 639:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 640:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) 641:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI 642:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; 643:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 644:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); 645:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 646:Drivers/CMSIS/Include/cmsis_gcc.h **** } 647:Drivers/CMSIS/Include/cmsis_gcc.h **** 648:Drivers/CMSIS/Include/cmsis_gcc.h **** 649:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 650:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 651:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) 652:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 653:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. 654:Drivers/CMSIS/Include/cmsis_gcc.h **** 655:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in s 656:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set 657:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 658:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) 659:Drivers/CMSIS/Include/cmsis_gcc.h **** { 660:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) 661:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI 662:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; 663:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 664:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); 665:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 666:Drivers/CMSIS/Include/cmsis_gcc.h **** } 667:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 668:Drivers/CMSIS/Include/cmsis_gcc.h **** 669:Drivers/CMSIS/Include/cmsis_gcc.h **** 670:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 671:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit 672:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 673:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure 674:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. 675:Drivers/CMSIS/Include/cmsis_gcc.h **** 676:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). 677:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value 678:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 679:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) 680:Drivers/CMSIS/Include/cmsis_gcc.h **** { 681:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 682:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) 683:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI 684:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; 685:Drivers/CMSIS/Include/cmsis_gcc.h **** #else ARM GAS /tmp/ccSuWkwR.s page 22 686:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 687:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim" : "=r" (result) ); 688:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 689:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 690:Drivers/CMSIS/Include/cmsis_gcc.h **** } 691:Drivers/CMSIS/Include/cmsis_gcc.h **** 692:Drivers/CMSIS/Include/cmsis_gcc.h **** 693:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 694:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 695:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit (non-secure) 696:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 697:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. 698:Drivers/CMSIS/Include/cmsis_gcc.h **** 699:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in sec 700:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value 701:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 702:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) 703:Drivers/CMSIS/Include/cmsis_gcc.h **** { 704:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) 705:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI 706:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; 707:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 708:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 709:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); 710:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 711:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 712:Drivers/CMSIS/Include/cmsis_gcc.h **** } 713:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 714:Drivers/CMSIS/Include/cmsis_gcc.h **** 715:Drivers/CMSIS/Include/cmsis_gcc.h **** 716:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 717:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit 718:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 719:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure 720:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. 721:Drivers/CMSIS/Include/cmsis_gcc.h **** 722:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). 723:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set 724:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 725:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) 726:Drivers/CMSIS/Include/cmsis_gcc.h **** { 727:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 728:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) 729:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI 730:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; 731:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 732:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); 733:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 734:Drivers/CMSIS/Include/cmsis_gcc.h **** } 735:Drivers/CMSIS/Include/cmsis_gcc.h **** 736:Drivers/CMSIS/Include/cmsis_gcc.h **** 737:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 738:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 739:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit (non-secure) 740:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 741:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. 742:Drivers/CMSIS/Include/cmsis_gcc.h **** ARM GAS /tmp/ccSuWkwR.s page 23 743:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secu 744:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer value to set 745:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 746:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) 747:Drivers/CMSIS/Include/cmsis_gcc.h **** { 748:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) 749:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI 750:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; 751:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 752:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); 753:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 754:Drivers/CMSIS/Include/cmsis_gcc.h **** } 755:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 756:Drivers/CMSIS/Include/cmsis_gcc.h **** 757:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 758:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ 759:Drivers/CMSIS/Include/cmsis_gcc.h **** 760:Drivers/CMSIS/Include/cmsis_gcc.h **** 761:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 762:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get FPSCR 763:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Floating Point Status/Control register. 764:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Floating Point Status/Control register value 765:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 766:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FPSCR(void) 767:Drivers/CMSIS/Include/cmsis_gcc.h **** { 768:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ 769:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) 770:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_get_fpscr) 771:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed 772:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) 773:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ 774:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_arm_get_fpscr(); 775:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 776:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 777:Drivers/CMSIS/Include/cmsis_gcc.h **** 778:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); 779:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 780:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 781:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 782:Drivers/CMSIS/Include/cmsis_gcc.h **** return(0U); 783:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 784:Drivers/CMSIS/Include/cmsis_gcc.h **** } 785:Drivers/CMSIS/Include/cmsis_gcc.h **** 786:Drivers/CMSIS/Include/cmsis_gcc.h **** 787:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 788:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set FPSCR 789:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Floating Point Status/Control register. 790:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] fpscr Floating Point Status/Control value to set 791:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) 793:Drivers/CMSIS/Include/cmsis_gcc.h **** { 794:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ 795:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) 796:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_set_fpscr) 797:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed 798:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) 799:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ ARM GAS /tmp/ccSuWkwR.s page 24 800:Drivers/CMSIS/Include/cmsis_gcc.h **** __builtin_arm_set_fpscr(fpscr); 801:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 802:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); 803:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 804:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 805:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)fpscr; 806:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 807:Drivers/CMSIS/Include/cmsis_gcc.h **** } 808:Drivers/CMSIS/Include/cmsis_gcc.h **** 809:Drivers/CMSIS/Include/cmsis_gcc.h **** 810:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */ 811:Drivers/CMSIS/Include/cmsis_gcc.h **** 812:Drivers/CMSIS/Include/cmsis_gcc.h **** 813:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################## Core Instruction Access ######################### */ 814:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface 815:Drivers/CMSIS/Include/cmsis_gcc.h **** Access to dedicated instructions 816:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ 817:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 818:Drivers/CMSIS/Include/cmsis_gcc.h **** 819:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2. 820:Drivers/CMSIS/Include/cmsis_gcc.h **** * For thumb1, use low register (r0-r7), specified by constraint "l" 821:Drivers/CMSIS/Include/cmsis_gcc.h **** * Otherwise, use general registers, specified by constraint "r" */ 822:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__) 823:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r) 824:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r) 825:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r) 826:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 827:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r) 828:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r) 829:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r) 830:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 831:Drivers/CMSIS/Include/cmsis_gcc.h **** 832:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 833:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief No Operation 834:Drivers/CMSIS/Include/cmsis_gcc.h **** \details No Operation does nothing. This instruction can be used for code alignment purposes. 835:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 836:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP() __ASM volatile ("nop") 837:Drivers/CMSIS/Include/cmsis_gcc.h **** 838:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 839:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Interrupt 840:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o 841:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 842:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI() __ASM volatile ("wfi") 843:Drivers/CMSIS/Include/cmsis_gcc.h **** 844:Drivers/CMSIS/Include/cmsis_gcc.h **** 845:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 846:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Event 847:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Event is a hint instruction that permits the processor to enter 848:Drivers/CMSIS/Include/cmsis_gcc.h **** a low-power state until one of a number of events occurs. 849:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 850:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE() __ASM volatile ("wfe") 851:Drivers/CMSIS/Include/cmsis_gcc.h **** 852:Drivers/CMSIS/Include/cmsis_gcc.h **** 853:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 854:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Send Event 855:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. 856:Drivers/CMSIS/Include/cmsis_gcc.h **** */ ARM GAS /tmp/ccSuWkwR.s page 25 857:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV() __ASM volatile ("sev") 858:Drivers/CMSIS/Include/cmsis_gcc.h **** 859:Drivers/CMSIS/Include/cmsis_gcc.h **** 860:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 861:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Instruction Synchronization Barrier 862:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Instruction Synchronization Barrier flushes the pipeline in the processor, 863:Drivers/CMSIS/Include/cmsis_gcc.h **** so that all instructions following the ISB are fetched from cache or memory, 864:Drivers/CMSIS/Include/cmsis_gcc.h **** after the instruction has been completed. 865:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 866:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void) 867:Drivers/CMSIS/Include/cmsis_gcc.h **** { 868:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("isb 0xF":::"memory"); 869:Drivers/CMSIS/Include/cmsis_gcc.h **** } 870:Drivers/CMSIS/Include/cmsis_gcc.h **** 871:Drivers/CMSIS/Include/cmsis_gcc.h **** 872:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 873:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Synchronization Barrier 874:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Acts as a special kind of Data Memory Barrier. 875:Drivers/CMSIS/Include/cmsis_gcc.h **** It completes when all explicit memory accesses before this instruction complete. 876:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 877:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void) 878:Drivers/CMSIS/Include/cmsis_gcc.h **** { 879:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dsb 0xF":::"memory"); 880:Drivers/CMSIS/Include/cmsis_gcc.h **** } 881:Drivers/CMSIS/Include/cmsis_gcc.h **** 882:Drivers/CMSIS/Include/cmsis_gcc.h **** 883:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 884:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Memory Barrier 885:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Ensures the apparent order of the explicit memory operations before 886:Drivers/CMSIS/Include/cmsis_gcc.h **** and after the instruction, without ensuring their completion. 887:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 888:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DMB(void) 889:Drivers/CMSIS/Include/cmsis_gcc.h **** { 890:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dmb 0xF":::"memory"); 891:Drivers/CMSIS/Include/cmsis_gcc.h **** } 892:Drivers/CMSIS/Include/cmsis_gcc.h **** 893:Drivers/CMSIS/Include/cmsis_gcc.h **** 894:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 895:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (32 bit) 896:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x785 897:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse 898:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value 899:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 900:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV(uint32_t value) 901:Drivers/CMSIS/Include/cmsis_gcc.h **** { 902:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) 903:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_bswap32(value); 904:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 905:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 906:Drivers/CMSIS/Include/cmsis_gcc.h **** 907:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); 908:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 909:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 910:Drivers/CMSIS/Include/cmsis_gcc.h **** } 911:Drivers/CMSIS/Include/cmsis_gcc.h **** 912:Drivers/CMSIS/Include/cmsis_gcc.h **** 913:Drivers/CMSIS/Include/cmsis_gcc.h **** /** ARM GAS /tmp/ccSuWkwR.s page 26 914:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (16 bit) 915:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 916:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse 917:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value 918:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 919:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) 920:Drivers/CMSIS/Include/cmsis_gcc.h **** { 921:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 922:Drivers/CMSIS/Include/cmsis_gcc.h **** 923:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); 924:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 925:Drivers/CMSIS/Include/cmsis_gcc.h **** } 926:Drivers/CMSIS/Include/cmsis_gcc.h **** 927:Drivers/CMSIS/Include/cmsis_gcc.h **** 928:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 929:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (16 bit) 930:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For exam 931:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse 932:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value 933:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 934:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE int16_t __REVSH(int16_t value) 935:Drivers/CMSIS/Include/cmsis_gcc.h **** { 936:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) 937:Drivers/CMSIS/Include/cmsis_gcc.h **** return (int16_t)__builtin_bswap16(value); 938:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 939:Drivers/CMSIS/Include/cmsis_gcc.h **** int16_t result; 940:Drivers/CMSIS/Include/cmsis_gcc.h **** 941:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); 942:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 943:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 944:Drivers/CMSIS/Include/cmsis_gcc.h **** } 945:Drivers/CMSIS/Include/cmsis_gcc.h **** 946:Drivers/CMSIS/Include/cmsis_gcc.h **** 947:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 948:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Rotate Right in unsigned value (32 bit) 949:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Rotate Right (immediate) provides the value of the contents of a register rotated by a v 950:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] op1 Value to rotate 951:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] op2 Number of Bits to rotate 952:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Rotated value 953:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 954:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) 955:Drivers/CMSIS/Include/cmsis_gcc.h **** { 956:Drivers/CMSIS/Include/cmsis_gcc.h **** op2 %= 32U; 957:Drivers/CMSIS/Include/cmsis_gcc.h **** if (op2 == 0U) 958:Drivers/CMSIS/Include/cmsis_gcc.h **** { 959:Drivers/CMSIS/Include/cmsis_gcc.h **** return op1; 960:Drivers/CMSIS/Include/cmsis_gcc.h **** } 961:Drivers/CMSIS/Include/cmsis_gcc.h **** return (op1 >> op2) | (op1 << (32U - op2)); 962:Drivers/CMSIS/Include/cmsis_gcc.h **** } 963:Drivers/CMSIS/Include/cmsis_gcc.h **** 964:Drivers/CMSIS/Include/cmsis_gcc.h **** 965:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 966:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Breakpoint 967:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Causes the processor to enter Debug state. 968:Drivers/CMSIS/Include/cmsis_gcc.h **** Debug tools can use this to investigate system state when the instruction at a particula 969:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value is ignored by the processor. 970:Drivers/CMSIS/Include/cmsis_gcc.h **** If required, a debugger can use it to store additional information about the break ARM GAS /tmp/ccSuWkwR.s page 27 971:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 972:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __BKPT(value) __ASM volatile ("bkpt "#value) 973:Drivers/CMSIS/Include/cmsis_gcc.h **** 974:Drivers/CMSIS/Include/cmsis_gcc.h **** 975:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 976:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse bit order of value 977:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the bit order of the given value. 978:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse 979:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value 980:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 981:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) 982:Drivers/CMSIS/Include/cmsis_gcc.h **** { 983:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 984:Drivers/CMSIS/Include/cmsis_gcc.h **** 985:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 986:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 987:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) 988:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 214 .loc 2 988 4 215 0108 BB68 ldr r3, [r7, #8] 216 .syntax unified 217 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 218 010a 93FAA3F3 rbit r3, r3 219 @ 0 "" 2 220 .thumb 221 .syntax unified 222 010e 7B60 str r3, [r7, #4] 989:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 990:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ 991:Drivers/CMSIS/Include/cmsis_gcc.h **** 992:Drivers/CMSIS/Include/cmsis_gcc.h **** result = value; /* r will be reversed bits of v; first get LSB of v */ 993:Drivers/CMSIS/Include/cmsis_gcc.h **** for (value >>= 1U; value != 0U; value >>= 1U) 994:Drivers/CMSIS/Include/cmsis_gcc.h **** { 995:Drivers/CMSIS/Include/cmsis_gcc.h **** result <<= 1U; 996:Drivers/CMSIS/Include/cmsis_gcc.h **** result |= value & 1U; 997:Drivers/CMSIS/Include/cmsis_gcc.h **** s--; 998:Drivers/CMSIS/Include/cmsis_gcc.h **** } 999:Drivers/CMSIS/Include/cmsis_gcc.h **** result <<= s; /* shift when v's highest bits are zero */ 1000:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 1001:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 223 .loc 2 1001 10 224 0110 7B68 ldr r3, [r7, #4] 225 .LBE169: 226 .LBE168: 293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Reset all CSR flags */ 295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** __HAL_RCC_CLEAR_RESET_FLAGS(); 227 .loc 1 295 3 discriminator 1 228 0112 B3FA83F3 clz r3, r3 229 .loc 1 295 3 is_stmt 0 discriminator 2 230 0116 DBB2 uxtb r3, r3 231 0118 1A46 mov r2, r3 232 011a 0A4B ldr r3, .L11+20 233 011c 1344 add r3, r3, r2 234 011e 9B00 lsls r3, r3, #2 235 0120 1A46 mov r2, r3 236 0122 0123 movs r3, #1 ARM GAS /tmp/ccSuWkwR.s page 28 237 0124 1360 str r3, [r2] 296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_OK; 238 .loc 1 297 10 is_stmt 1 239 0126 0023 movs r3, #0 240 .L3: 298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 241 .loc 1 298 1 242 0128 1846 mov r0, r3 243 012a 1037 adds r7, r7, #16 244 .cfi_def_cfa_offset 8 245 012c BD46 mov sp, r7 246 .cfi_def_cfa_register 13 247 @ sp needed 248 012e 80BD pop {r7, pc} 249 .L12: 250 .align 2 251 .L11: 252 0130 00100240 .word 1073876992 253 0134 0CC0FFF8 .word -117456884 254 0138 00000000 .word SystemCoreClock 255 013c 00127A00 .word 8000000 256 0140 00000000 .word uwTickPrio 257 0144 20819010 .word 277905696 258 .cfi_endproc 259 .LFE130: 261 .section .text.HAL_RCC_OscConfig,"ax",%progbits 262 .align 1 263 .global HAL_RCC_OscConfig 264 .syntax unified 265 .thumb 266 .thumb_func 268 HAL_RCC_OscConfig: 269 .LFB131: 299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** 301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @brief Initializes the RCC Oscillators according to the specified parameters in the 302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * RCC_OscInitTypeDef. 303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that 304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * contains the configuration information for the RCC Oscillators. 305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note The PLL is not disabled when used as system clock. 306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not 307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * supported by this macro. User should request a transition to LSE Off 308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * first and then LSE On or LSE Bypass. 309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not 310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * supported by this macro. User should request a transition to HSE Off 311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * first and then HSE On or HSE Bypass. 312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @retval HAL status 313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ 314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) 315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 270 .loc 1 315 1 271 .cfi_startproc 272 @ args = 0, pretend = 0, frame = 512 273 @ frame_needed = 1, uses_anonymous_args = 0 274 0000 80B5 push {r7, lr} 275 .cfi_def_cfa_offset 8 ARM GAS /tmp/ccSuWkwR.s page 29 276 .cfi_offset 7, -8 277 .cfi_offset 14, -4 278 0002 ADF5007D sub sp, sp, #512 279 .cfi_def_cfa_offset 520 280 0006 00AF add r7, sp, #0 281 .cfi_def_cfa_register 7 282 0008 07F50073 add r3, r7, #512 283 000c A3F5FE73 sub r3, r3, #508 284 0010 1860 str r0, [r3] 316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** uint32_t tickstart; 317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** uint32_t pll_config; 318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #if defined(RCC_CFGR_PLLSRC_HSI_PREDIV) 319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** uint32_t pll_config2; 320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #endif /* RCC_CFGR_PLLSRC_HSI_PREDIV */ 321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check Null pointer */ 323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(RCC_OscInitStruct == NULL) 285 .loc 1 323 5 286 0012 07F50073 add r3, r7, #512 287 0016 A3F5FE73 sub r3, r3, #508 288 001a 1B68 ldr r3, [r3] 289 001c 002B cmp r3, #0 290 001e 02D1 bne .L14 324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_ERROR; 291 .loc 1 325 12 292 0020 0123 movs r3, #1 293 0022 00F0F4BF b .L15 294 .L14: 326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check the parameters */ 329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); 330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /*------------------------------- HSE Configuration ------------------------*/ 332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 295 .loc 1 332 25 296 0026 07F50073 add r3, r7, #512 297 002a A3F5FE73 sub r3, r3, #508 298 002e 1B68 ldr r3, [r3] 299 0030 1B68 ldr r3, [r3] 300 .loc 1 332 43 301 0032 03F00103 and r3, r3, #1 302 .loc 1 332 5 303 0036 002B cmp r3, #0 304 0038 00F06D81 beq .L16 333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check the parameters */ 335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); 336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowe 338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) 305 .loc 1 338 9 306 003c B44B ldr r3, .L154 307 003e 5B68 ldr r3, [r3, #4] 308 0040 03F00C03 and r3, r3, #12 309 .loc 1 338 7 ARM GAS /tmp/ccSuWkwR.s page 30 310 0044 042B cmp r3, #4 311 0046 0CD0 beq .L17 339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_ 312 .loc 1 339 13 313 0048 B14B ldr r3, .L154 314 004a 5B68 ldr r3, [r3, #4] 315 004c 03F00C03 and r3, r3, #12 316 .loc 1 339 8 317 0050 082B cmp r3, #8 318 0052 57D1 bne .L18 319 .loc 1 339 82 discriminator 1 320 0054 AE4B ldr r3, .L154 321 0056 5B68 ldr r3, [r3, #4] 322 0058 03F48033 and r3, r3, #65536 323 .loc 1 339 78 discriminator 1 324 005c B3F5803F cmp r3, #65536 325 0060 50D1 bne .L18 326 .L17: 327 0062 4FF40033 mov r3, #131072 328 0066 C7F8F031 str r3, [r7, #496] 329 .LBB170: 330 .LBB171: 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 331 .loc 2 988 4 332 006a D7F8F031 ldr r3, [r7, #496] 333 .syntax unified 334 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 335 006e 93FAA3F3 rbit r3, r3 336 @ 0 "" 2 337 .thumb 338 .syntax unified 339 0072 C7F8EC31 str r3, [r7, #492] 340 .loc 2 1001 10 341 0076 D7F8EC31 ldr r3, [r7, #492] 342 .LBE171: 343 .LBE170: 340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_ 344 .loc 1 341 11 discriminator 1 345 007a B3FA83F3 clz r3, r3 346 .loc 1 341 11 is_stmt 0 discriminator 2 347 007e DBB2 uxtb r3, r3 348 0080 3F2B cmp r3, #63 349 0082 02D8 bhi .L20 350 .loc 1 341 11 discriminator 1 351 0084 A24B ldr r3, .L154 352 0086 1B68 ldr r3, [r3] 353 0088 15E0 b .L21 354 .L20: 355 008a 4FF40033 mov r3, #131072 356 008e C7F8E831 str r3, [r7, #488] 357 .LBB172: 358 .LBB173: 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 359 .loc 2 988 4 is_stmt 1 360 0092 D7F8E831 ldr r3, [r7, #488] 361 .syntax unified ARM GAS /tmp/ccSuWkwR.s page 31 362 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 363 0096 93FAA3F3 rbit r3, r3 364 @ 0 "" 2 365 .thumb 366 .syntax unified 367 009a C7F8E431 str r3, [r7, #484] 368 009e 4FF40033 mov r3, #131072 369 00a2 C7F8E031 str r3, [r7, #480] 370 .LBE173: 371 .LBE172: 372 .LBB174: 373 .LBB175: 374 00a6 D7F8E031 ldr r3, [r7, #480] 375 .syntax unified 376 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 377 00aa 93FAA3F3 rbit r3, r3 378 @ 0 "" 2 379 .thumb 380 .syntax unified 381 00ae C7F8DC31 str r3, [r7, #476] 382 .LBE175: 383 .LBE174: 384 .loc 1 341 11 discriminator 8 385 00b2 974B ldr r3, .L154 386 00b4 5B6A ldr r3, [r3, #36] 387 .L21: 388 00b6 4FF40032 mov r2, #131072 389 00ba C7F8D821 str r2, [r7, #472] 390 .LBB176: 391 .LBB177: 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 392 .loc 2 988 4 393 00be D7F8D821 ldr r2, [r7, #472] 394 .syntax unified 395 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 396 00c2 92FAA2F2 rbit r2, r2 397 @ 0 "" 2 398 .thumb 399 .syntax unified 400 00c6 C7F8D421 str r2, [r7, #468] 401 .loc 2 1001 10 402 00ca D7F8D421 ldr r2, [r7, #468] 403 .LBE177: 404 .LBE176: 405 .loc 1 341 11 discriminator 1 406 00ce B2FA82F2 clz r2, r2 407 .loc 1 341 11 is_stmt 0 discriminator 2 408 00d2 D2B2 uxtb r2, r2 409 00d4 42F02002 orr r2, r2, #32 410 00d8 D2B2 uxtb r2, r2 411 00da 02F01F02 and r2, r2, #31 412 00de 0121 movs r1, #1 413 00e0 01FA02F2 lsl r2, r1, r2 414 00e4 1340 ands r3, r3, r2 415 .loc 1 341 9 is_stmt 1 discriminator 2 416 00e6 002B cmp r3, #0 417 00e8 00F01481 beq .L153 ARM GAS /tmp/ccSuWkwR.s page 32 418 .loc 1 341 78 discriminator 13 419 00ec 07F50073 add r3, r7, #512 420 00f0 A3F5FE73 sub r3, r3, #508 421 00f4 1B68 ldr r3, [r3] 422 00f6 5B68 ldr r3, [r3, #4] 423 .loc 1 341 57 discriminator 13 424 00f8 002B cmp r3, #0 425 00fa 40F00B81 bne .L153 342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_ERROR; 426 .loc 1 343 16 427 00fe 0123 movs r3, #1 428 0100 00F085BF b .L15 429 .L18: 344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** else 347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Set the new HSE configuration ---------------------------------------*/ 349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 430 .loc 1 349 7 431 0104 07F50073 add r3, r7, #512 432 0108 A3F5FE73 sub r3, r3, #508 433 010c 1B68 ldr r3, [r3] 434 010e 5B68 ldr r3, [r3, #4] 435 0110 B3F5803F cmp r3, #65536 436 0114 06D1 bne .L26 437 .loc 1 349 7 is_stmt 0 discriminator 1 438 0116 7E4B ldr r3, .L154 439 0118 1B68 ldr r3, [r3] 440 011a 7D4A ldr r2, .L154 441 011c 43F48033 orr r3, r3, #65536 442 0120 1360 str r3, [r2] 443 0122 36E0 b .L27 444 .L26: 445 .loc 1 349 7 discriminator 2 446 0124 07F50073 add r3, r7, #512 447 0128 A3F5FE73 sub r3, r3, #508 448 012c 1B68 ldr r3, [r3] 449 012e 5B68 ldr r3, [r3, #4] 450 0130 002B cmp r3, #0 451 0132 0CD1 bne .L28 452 .loc 1 349 7 discriminator 3 453 0134 764B ldr r3, .L154 454 0136 1B68 ldr r3, [r3] 455 0138 754A ldr r2, .L154 456 013a 23F48033 bic r3, r3, #65536 457 013e 1360 str r3, [r2] 458 0140 734B ldr r3, .L154 459 0142 1B68 ldr r3, [r3] 460 0144 724A ldr r2, .L154 461 0146 23F48023 bic r3, r3, #262144 462 014a 1360 str r3, [r2] 463 014c 21E0 b .L27 464 .L28: 465 .loc 1 349 7 discriminator 4 466 014e 07F50073 add r3, r7, #512 ARM GAS /tmp/ccSuWkwR.s page 33 467 0152 A3F5FE73 sub r3, r3, #508 468 0156 1B68 ldr r3, [r3] 469 0158 5B68 ldr r3, [r3, #4] 470 015a B3F5A02F cmp r3, #327680 471 015e 0CD1 bne .L29 472 .loc 1 349 7 discriminator 5 473 0160 6B4B ldr r3, .L154 474 0162 1B68 ldr r3, [r3] 475 0164 6A4A ldr r2, .L154 476 0166 43F48023 orr r3, r3, #262144 477 016a 1360 str r3, [r2] 478 016c 684B ldr r3, .L154 479 016e 1B68 ldr r3, [r3] 480 0170 674A ldr r2, .L154 481 0172 43F48033 orr r3, r3, #65536 482 0176 1360 str r3, [r2] 483 0178 0BE0 b .L27 484 .L29: 485 .loc 1 349 7 discriminator 6 486 017a 654B ldr r3, .L154 487 017c 1B68 ldr r3, [r3] 488 017e 644A ldr r2, .L154 489 0180 23F48033 bic r3, r3, #65536 490 0184 1360 str r3, [r2] 491 0186 624B ldr r3, .L154 492 0188 1B68 ldr r3, [r3] 493 018a 614A ldr r2, .L154 494 018c 23F48023 bic r3, r3, #262144 495 0190 1360 str r3, [r2] 496 .L27: 350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #if defined(RCC_CFGR_PLLSRC_HSI_DIV2) 352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Configure the HSE predivision factor --------------------------------*/ 353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue); 497 .loc 1 353 7 is_stmt 1 498 0192 5F4B ldr r3, .L154 499 0194 DB6A ldr r3, [r3, #44] 500 0196 23F00F02 bic r2, r3, #15 501 019a 07F50073 add r3, r7, #512 502 019e A3F5FE73 sub r3, r3, #508 503 01a2 1B68 ldr r3, [r3] 504 01a4 9B68 ldr r3, [r3, #8] 505 01a6 5A49 ldr r1, .L154 506 01a8 1343 orrs r3, r3, r2 507 01aa CB62 str r3, [r1, #44] 354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */ 355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check the HSE State */ 357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 508 .loc 1 357 27 509 01ac 07F50073 add r3, r7, #512 510 01b0 A3F5FE73 sub r3, r3, #508 511 01b4 1B68 ldr r3, [r3] 512 01b6 5B68 ldr r3, [r3, #4] 513 .loc 1 357 9 514 01b8 002B cmp r3, #0 515 01ba 54D0 beq .L30 ARM GAS /tmp/ccSuWkwR.s page 34 358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get Start Tick */ 360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** tickstart = HAL_GetTick(); 516 .loc 1 360 21 517 01bc FFF7FEFF bl HAL_GetTick 518 01c0 C7F8F801 str r0, [r7, #504] 361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Wait till HSE is ready */ 363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 519 .loc 1 363 14 520 01c4 0AE0 b .L31 521 .L38: 364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) 522 .loc 1 365 15 523 01c6 FFF7FEFF bl HAL_GetTick 524 01ca 0246 mov r2, r0 525 .loc 1 365 29 discriminator 1 526 01cc D7F8F831 ldr r3, [r7, #504] 527 01d0 D31A subs r3, r2, r3 528 .loc 1 365 13 discriminator 1 529 01d2 642B cmp r3, #100 530 01d4 02D9 bls .L31 366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_TIMEOUT; 531 .loc 1 367 20 532 01d6 0323 movs r3, #3 533 01d8 00F019BF b .L15 534 .L31: 535 01dc 4FF40033 mov r3, #131072 536 01e0 C7F8D031 str r3, [r7, #464] 537 .LBB178: 538 .LBB179: 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 539 .loc 2 988 4 540 01e4 D7F8D031 ldr r3, [r7, #464] 541 .syntax unified 542 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 543 01e8 93FAA3F3 rbit r3, r3 544 @ 0 "" 2 545 .thumb 546 .syntax unified 547 01ec C7F8CC31 str r3, [r7, #460] 548 .loc 2 1001 10 549 01f0 D7F8CC31 ldr r3, [r7, #460] 550 .LBE179: 551 .LBE178: 363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 552 .loc 1 363 15 discriminator 1 553 01f4 B3FA83F3 clz r3, r3 363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 554 .loc 1 363 15 is_stmt 0 discriminator 2 555 01f8 DBB2 uxtb r3, r3 556 01fa 3F2B cmp r3, #63 557 01fc 02D8 bhi .L33 363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 558 .loc 1 363 15 discriminator 1 ARM GAS /tmp/ccSuWkwR.s page 35 559 01fe 444B ldr r3, .L154 560 0200 1B68 ldr r3, [r3] 561 0202 15E0 b .L34 562 .L33: 563 0204 4FF40033 mov r3, #131072 564 0208 C7F8C831 str r3, [r7, #456] 565 .LBB180: 566 .LBB181: 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 567 .loc 2 988 4 is_stmt 1 568 020c D7F8C831 ldr r3, [r7, #456] 569 .syntax unified 570 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 571 0210 93FAA3F3 rbit r3, r3 572 @ 0 "" 2 573 .thumb 574 .syntax unified 575 0214 C7F8C431 str r3, [r7, #452] 576 0218 4FF40033 mov r3, #131072 577 021c C7F8C031 str r3, [r7, #448] 578 .LBE181: 579 .LBE180: 580 .LBB182: 581 .LBB183: 582 0220 D7F8C031 ldr r3, [r7, #448] 583 .syntax unified 584 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 585 0224 93FAA3F3 rbit r3, r3 586 @ 0 "" 2 587 .thumb 588 .syntax unified 589 0228 C7F8BC31 str r3, [r7, #444] 590 .LBE183: 591 .LBE182: 363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 592 .loc 1 363 15 discriminator 8 593 022c 384B ldr r3, .L154 594 022e 5B6A ldr r3, [r3, #36] 595 .L34: 596 0230 4FF40032 mov r2, #131072 597 0234 C7F8B821 str r2, [r7, #440] 598 .LBB184: 599 .LBB185: 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 600 .loc 2 988 4 601 0238 D7F8B821 ldr r2, [r7, #440] 602 .syntax unified 603 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 604 023c 92FAA2F2 rbit r2, r2 605 @ 0 "" 2 606 .thumb 607 .syntax unified 608 0240 C7F8B421 str r2, [r7, #436] 609 .loc 2 1001 10 610 0244 D7F8B421 ldr r2, [r7, #436] 611 .LBE185: 612 .LBE184: ARM GAS /tmp/ccSuWkwR.s page 36 363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 613 .loc 1 363 15 discriminator 1 614 0248 B2FA82F2 clz r2, r2 363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 615 .loc 1 363 15 is_stmt 0 discriminator 2 616 024c D2B2 uxtb r2, r2 617 024e 42F02002 orr r2, r2, #32 618 0252 D2B2 uxtb r2, r2 619 0254 02F01F02 and r2, r2, #31 620 0258 0121 movs r1, #1 621 025a 01FA02F2 lsl r2, r1, r2 622 025e 1340 ands r3, r3, r2 363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 623 .loc 1 363 51 is_stmt 1 discriminator 2 624 0260 002B cmp r3, #0 625 0262 B0D0 beq .L38 626 0264 57E0 b .L16 627 .L30: 368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** else 372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get Start Tick */ 374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** tickstart = HAL_GetTick(); 628 .loc 1 374 21 629 0266 FFF7FEFF bl HAL_GetTick 630 026a C7F8F801 str r0, [r7, #504] 375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Wait till HSE is disabled */ 377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 631 .loc 1 377 14 632 026e 0AE0 b .L39 633 .L46: 378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) 634 .loc 1 379 16 635 0270 FFF7FEFF bl HAL_GetTick 636 0274 0246 mov r2, r0 637 .loc 1 379 30 discriminator 1 638 0276 D7F8F831 ldr r3, [r7, #504] 639 027a D31A subs r3, r2, r3 640 .loc 1 379 14 discriminator 1 641 027c 642B cmp r3, #100 642 027e 02D9 bls .L39 380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_TIMEOUT; 643 .loc 1 381 20 644 0280 0323 movs r3, #3 645 0282 00F0C4BE b .L15 646 .L39: 647 0286 4FF40033 mov r3, #131072 648 028a C7F8B031 str r3, [r7, #432] 649 .LBB186: 650 .LBB187: 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 651 .loc 2 988 4 ARM GAS /tmp/ccSuWkwR.s page 37 652 028e D7F8B031 ldr r3, [r7, #432] 653 .syntax unified 654 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 655 0292 93FAA3F3 rbit r3, r3 656 @ 0 "" 2 657 .thumb 658 .syntax unified 659 0296 C7F8AC31 str r3, [r7, #428] 660 .loc 2 1001 10 661 029a D7F8AC31 ldr r3, [r7, #428] 662 .LBE187: 663 .LBE186: 377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 664 .loc 1 377 15 discriminator 1 665 029e B3FA83F3 clz r3, r3 377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 666 .loc 1 377 15 is_stmt 0 discriminator 2 667 02a2 DBB2 uxtb r3, r3 668 02a4 3F2B cmp r3, #63 669 02a6 02D8 bhi .L41 377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 670 .loc 1 377 15 discriminator 1 671 02a8 194B ldr r3, .L154 672 02aa 1B68 ldr r3, [r3] 673 02ac 15E0 b .L42 674 .L41: 675 02ae 4FF40033 mov r3, #131072 676 02b2 C7F8A831 str r3, [r7, #424] 677 .LBB188: 678 .LBB189: 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 679 .loc 2 988 4 is_stmt 1 680 02b6 D7F8A831 ldr r3, [r7, #424] 681 .syntax unified 682 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 683 02ba 93FAA3F3 rbit r3, r3 684 @ 0 "" 2 685 .thumb 686 .syntax unified 687 02be C7F8A431 str r3, [r7, #420] 688 02c2 4FF40033 mov r3, #131072 689 02c6 C7F8A031 str r3, [r7, #416] 690 .LBE189: 691 .LBE188: 692 .LBB190: 693 .LBB191: 694 02ca D7F8A031 ldr r3, [r7, #416] 695 .syntax unified 696 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 697 02ce 93FAA3F3 rbit r3, r3 698 @ 0 "" 2 699 .thumb 700 .syntax unified 701 02d2 C7F89C31 str r3, [r7, #412] 702 .LBE191: 703 .LBE190: 377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { ARM GAS /tmp/ccSuWkwR.s page 38 704 .loc 1 377 15 discriminator 8 705 02d6 0E4B ldr r3, .L154 706 02d8 5B6A ldr r3, [r3, #36] 707 .L42: 708 02da 4FF40032 mov r2, #131072 709 02de C7F89821 str r2, [r7, #408] 710 .LBB192: 711 .LBB193: 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 712 .loc 2 988 4 713 02e2 D7F89821 ldr r2, [r7, #408] 714 .syntax unified 715 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 716 02e6 92FAA2F2 rbit r2, r2 717 @ 0 "" 2 718 .thumb 719 .syntax unified 720 02ea C7F89421 str r2, [r7, #404] 721 .loc 2 1001 10 722 02ee D7F89421 ldr r2, [r7, #404] 723 .LBE193: 724 .LBE192: 377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 725 .loc 1 377 15 discriminator 1 726 02f2 B2FA82F2 clz r2, r2 377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 727 .loc 1 377 15 is_stmt 0 discriminator 2 728 02f6 D2B2 uxtb r2, r2 729 02f8 42F02002 orr r2, r2, #32 730 02fc D2B2 uxtb r2, r2 731 02fe 02F01F02 and r2, r2, #31 732 0302 0121 movs r1, #1 733 0304 01FA02F2 lsl r2, r1, r2 734 0308 1340 ands r3, r3, r2 377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 735 .loc 1 377 51 is_stmt 1 discriminator 2 736 030a 002B cmp r3, #0 737 030c B0D1 bne .L46 738 030e 02E0 b .L16 739 .L155: 740 .align 2 741 .L154: 742 0310 00100240 .word 1073876992 743 .L153: 341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 744 .loc 1 341 9 745 0314 00BF nop 746 .L16: 382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /*----------------------------- HSI Configuration --------------------------*/ 388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 747 .loc 1 388 25 748 0316 07F50073 add r3, r7, #512 ARM GAS /tmp/ccSuWkwR.s page 39 749 031a A3F5FE73 sub r3, r3, #508 750 031e 1B68 ldr r3, [r3] 751 0320 1B68 ldr r3, [r3] 752 .loc 1 388 43 753 0322 03F00203 and r3, r3, #2 754 .loc 1 388 5 755 0326 002B cmp r3, #0 756 0328 00F06C81 beq .L47 389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check the parameters */ 391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); 392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); 393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock * 395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) 757 .loc 1 395 9 758 032c CC4B ldr r3, .L156 759 032e 5B68 ldr r3, [r3, #4] 760 0330 03F00C03 and r3, r3, #12 761 .loc 1 395 7 762 0334 002B cmp r3, #0 763 0336 0BD0 beq .L48 396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_ 764 .loc 1 396 13 765 0338 C94B ldr r3, .L156 766 033a 5B68 ldr r3, [r3, #4] 767 033c 03F00C03 and r3, r3, #12 768 .loc 1 396 8 769 0340 082B cmp r3, #8 770 0342 6DD1 bne .L49 771 .loc 1 396 82 discriminator 1 772 0344 C64B ldr r3, .L156 773 0346 5B68 ldr r3, [r3, #4] 774 0348 03F48033 and r3, r3, #65536 775 .loc 1 396 78 discriminator 1 776 034c 002B cmp r3, #0 777 034e 67D1 bne .L49 778 .L48: 779 0350 0223 movs r3, #2 780 0352 C7F89031 str r3, [r7, #400] 781 .LBB194: 782 .LBB195: 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 783 .loc 2 988 4 784 0356 D7F89031 ldr r3, [r7, #400] 785 .syntax unified 786 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 787 035a 93FAA3F3 rbit r3, r3 788 @ 0 "" 2 789 .thumb 790 .syntax unified 791 035e C7F88C31 str r3, [r7, #396] 792 .loc 2 1001 10 793 0362 D7F88C31 ldr r3, [r7, #396] 794 .LBE195: 795 .LBE194: 397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { ARM GAS /tmp/ccSuWkwR.s page 40 398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* When HSI is used as system clock it will not disabled */ 399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ 796 .loc 1 399 11 discriminator 1 797 0366 B3FA83F3 clz r3, r3 798 .loc 1 399 11 is_stmt 0 discriminator 2 799 036a DBB2 uxtb r3, r3 800 036c 3F2B cmp r3, #63 801 036e 02D8 bhi .L51 802 .loc 1 399 11 discriminator 1 803 0370 BB4B ldr r3, .L156 804 0372 1B68 ldr r3, [r3] 805 0374 13E0 b .L52 806 .L51: 807 0376 0223 movs r3, #2 808 0378 C7F88831 str r3, [r7, #392] 809 .LBB196: 810 .LBB197: 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 811 .loc 2 988 4 is_stmt 1 812 037c D7F88831 ldr r3, [r7, #392] 813 .syntax unified 814 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 815 0380 93FAA3F3 rbit r3, r3 816 @ 0 "" 2 817 .thumb 818 .syntax unified 819 0384 C7F88431 str r3, [r7, #388] 820 0388 0223 movs r3, #2 821 038a C7F88031 str r3, [r7, #384] 822 .LBE197: 823 .LBE196: 824 .LBB198: 825 .LBB199: 826 038e D7F88031 ldr r3, [r7, #384] 827 .syntax unified 828 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 829 0392 93FAA3F3 rbit r3, r3 830 @ 0 "" 2 831 .thumb 832 .syntax unified 833 0396 C7F87C31 str r3, [r7, #380] 834 .LBE199: 835 .LBE198: 836 .loc 1 399 11 discriminator 8 837 039a B14B ldr r3, .L156 838 039c 5B6A ldr r3, [r3, #36] 839 .L52: 840 039e 0222 movs r2, #2 841 03a0 C7F87821 str r2, [r7, #376] 842 .LBB200: 843 .LBB201: 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 844 .loc 2 988 4 845 03a4 D7F87821 ldr r2, [r7, #376] 846 .syntax unified 847 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 848 03a8 92FAA2F2 rbit r2, r2 ARM GAS /tmp/ccSuWkwR.s page 41 849 @ 0 "" 2 850 .thumb 851 .syntax unified 852 03ac C7F87421 str r2, [r7, #372] 853 .loc 2 1001 10 854 03b0 D7F87421 ldr r2, [r7, #372] 855 .LBE201: 856 .LBE200: 857 .loc 1 399 11 discriminator 1 858 03b4 B2FA82F2 clz r2, r2 859 .loc 1 399 11 is_stmt 0 discriminator 2 860 03b8 D2B2 uxtb r2, r2 861 03ba 42F02002 orr r2, r2, #32 862 03be D2B2 uxtb r2, r2 863 03c0 02F01F02 and r2, r2, #31 864 03c4 0121 movs r1, #1 865 03c6 01FA02F2 lsl r2, r1, r2 866 03ca 1340 ands r3, r3, r2 867 .loc 1 399 9 is_stmt 1 discriminator 2 868 03cc 002B cmp r3, #0 869 03ce 0AD0 beq .L56 870 .loc 1 399 78 discriminator 13 871 03d0 07F50073 add r3, r7, #512 872 03d4 A3F5FE73 sub r3, r3, #508 873 03d8 1B68 ldr r3, [r3] 874 03da 1B69 ldr r3, [r3, #16] 875 .loc 1 399 57 discriminator 13 876 03dc 012B cmp r3, #1 877 03de 02D0 beq .L56 400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_ERROR; 878 .loc 1 401 16 879 03e0 0123 movs r3, #1 880 03e2 00F014BE b .L15 881 .L56: 402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Otherwise, just the calibration is allowed */ 404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** else 405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ 407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 882 .loc 1 407 9 883 03e6 9E4B ldr r3, .L156 884 03e8 1B68 ldr r3, [r3] 885 03ea 23F0F802 bic r2, r3, #248 886 03ee 07F50073 add r3, r7, #512 887 03f2 A3F5FE73 sub r3, r3, #508 888 03f6 1B68 ldr r3, [r3] 889 03f8 5B69 ldr r3, [r3, #20] 890 03fa F821 movs r1, #248 891 03fc C7F87011 str r1, [r7, #368] 892 .LBB202: 893 .LBB203: 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 894 .loc 2 988 4 895 0400 D7F87011 ldr r1, [r7, #368] 896 .syntax unified ARM GAS /tmp/ccSuWkwR.s page 42 897 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 898 0404 91FAA1F1 rbit r1, r1 899 @ 0 "" 2 900 .thumb 901 .syntax unified 902 0408 C7F86C11 str r1, [r7, #364] 903 .loc 2 1001 10 904 040c D7F86C11 ldr r1, [r7, #364] 905 .LBE203: 906 .LBE202: 907 .loc 1 407 9 discriminator 1 908 0410 B1FA81F1 clz r1, r1 909 .loc 1 407 9 is_stmt 0 discriminator 2 910 0414 C9B2 uxtb r1, r1 911 0416 8B40 lsls r3, r3, r1 912 0418 9149 ldr r1, .L156 913 041a 1343 orrs r3, r3, r2 914 041c 0B60 str r3, [r1] 399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 915 .loc 1 399 9 is_stmt 1 916 041e F1E0 b .L47 917 .L49: 408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** else 411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check the HSI State */ 413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF) 918 .loc 1 413 27 919 0420 07F50073 add r3, r7, #512 920 0424 A3F5FE73 sub r3, r3, #508 921 0428 1B68 ldr r3, [r3] 922 042a 1B69 ldr r3, [r3, #16] 923 .loc 1 413 9 924 042c 002B cmp r3, #0 925 042e 00F08380 beq .L58 926 0432 0123 movs r3, #1 927 0434 C7F86831 str r3, [r7, #360] 928 .LBB204: 929 .LBB205: 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 930 .loc 2 988 4 931 0438 D7F86831 ldr r3, [r7, #360] 932 .syntax unified 933 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 934 043c 93FAA3F3 rbit r3, r3 935 @ 0 "" 2 936 .thumb 937 .syntax unified 938 0440 C7F86431 str r3, [r7, #356] 939 .loc 2 1001 10 940 0444 D7F86431 ldr r3, [r7, #356] 941 .LBE205: 942 .LBE204: 414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Enable the Internal High Speed oscillator (HSI). */ 416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** __HAL_RCC_HSI_ENABLE(); ARM GAS /tmp/ccSuWkwR.s page 43 943 .loc 1 416 9 discriminator 1 944 0448 B3FA83F3 clz r3, r3 945 .loc 1 416 9 is_stmt 0 discriminator 2 946 044c DBB2 uxtb r3, r3 947 044e 03F18453 add r3, r3, #276824064 948 0452 03F58413 add r3, r3, #1081344 949 0456 9B00 lsls r3, r3, #2 950 0458 1A46 mov r2, r3 951 045a 0123 movs r3, #1 952 045c 1360 str r3, [r2] 417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get Start Tick */ 419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** tickstart = HAL_GetTick(); 953 .loc 1 419 21 is_stmt 1 954 045e FFF7FEFF bl HAL_GetTick 955 0462 C7F8F801 str r0, [r7, #504] 420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Wait till HSI is ready */ 422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 956 .loc 1 422 14 957 0466 0AE0 b .L60 958 .L67: 423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) 959 .loc 1 424 15 960 0468 FFF7FEFF bl HAL_GetTick 961 046c 0246 mov r2, r0 962 .loc 1 424 29 discriminator 1 963 046e D7F8F831 ldr r3, [r7, #504] 964 0472 D31A subs r3, r2, r3 965 .loc 1 424 13 discriminator 1 966 0474 022B cmp r3, #2 967 0476 02D9 bls .L60 425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_TIMEOUT; 968 .loc 1 426 20 969 0478 0323 movs r3, #3 970 047a 00F0C8BD b .L15 971 .L60: 972 047e 0223 movs r3, #2 973 0480 C7F86031 str r3, [r7, #352] 974 .LBB206: 975 .LBB207: 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 976 .loc 2 988 4 977 0484 D7F86031 ldr r3, [r7, #352] 978 .syntax unified 979 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 980 0488 93FAA3F3 rbit r3, r3 981 @ 0 "" 2 982 .thumb 983 .syntax unified 984 048c C7F85C31 str r3, [r7, #348] 985 .loc 2 1001 10 986 0490 D7F85C31 ldr r3, [r7, #348] 987 .LBE207: 988 .LBE206: ARM GAS /tmp/ccSuWkwR.s page 44 422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 989 .loc 1 422 15 discriminator 1 990 0494 B3FA83F3 clz r3, r3 422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 991 .loc 1 422 15 is_stmt 0 discriminator 2 992 0498 DBB2 uxtb r3, r3 993 049a 3F2B cmp r3, #63 994 049c 02D8 bhi .L62 422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 995 .loc 1 422 15 discriminator 1 996 049e 704B ldr r3, .L156 997 04a0 1B68 ldr r3, [r3] 998 04a2 13E0 b .L63 999 .L62: 1000 04a4 0223 movs r3, #2 1001 04a6 C7F85831 str r3, [r7, #344] 1002 .LBB208: 1003 .LBB209: 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 1004 .loc 2 988 4 is_stmt 1 1005 04aa D7F85831 ldr r3, [r7, #344] 1006 .syntax unified 1007 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 1008 04ae 93FAA3F3 rbit r3, r3 1009 @ 0 "" 2 1010 .thumb 1011 .syntax unified 1012 04b2 C7F85431 str r3, [r7, #340] 1013 04b6 0223 movs r3, #2 1014 04b8 C7F85031 str r3, [r7, #336] 1015 .LBE209: 1016 .LBE208: 1017 .LBB210: 1018 .LBB211: 1019 04bc D7F85031 ldr r3, [r7, #336] 1020 .syntax unified 1021 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 1022 04c0 93FAA3F3 rbit r3, r3 1023 @ 0 "" 2 1024 .thumb 1025 .syntax unified 1026 04c4 C7F84C31 str r3, [r7, #332] 1027 .LBE211: 1028 .LBE210: 422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 1029 .loc 1 422 15 discriminator 8 1030 04c8 654B ldr r3, .L156 1031 04ca 5B6A ldr r3, [r3, #36] 1032 .L63: 1033 04cc 0222 movs r2, #2 1034 04ce C7F84821 str r2, [r7, #328] 1035 .LBB212: 1036 .LBB213: 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 1037 .loc 2 988 4 1038 04d2 D7F84821 ldr r2, [r7, #328] 1039 .syntax unified ARM GAS /tmp/ccSuWkwR.s page 45 1040 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 1041 04d6 92FAA2F2 rbit r2, r2 1042 @ 0 "" 2 1043 .thumb 1044 .syntax unified 1045 04da C7F84421 str r2, [r7, #324] 1046 .loc 2 1001 10 1047 04de D7F84421 ldr r2, [r7, #324] 1048 .LBE213: 1049 .LBE212: 422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 1050 .loc 1 422 15 discriminator 1 1051 04e2 B2FA82F2 clz r2, r2 422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 1052 .loc 1 422 15 is_stmt 0 discriminator 2 1053 04e6 D2B2 uxtb r2, r2 1054 04e8 42F02002 orr r2, r2, #32 1055 04ec D2B2 uxtb r2, r2 1056 04ee 02F01F02 and r2, r2, #31 1057 04f2 0121 movs r1, #1 1058 04f4 01FA02F2 lsl r2, r1, r2 1059 04f8 1340 ands r3, r3, r2 422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 1060 .loc 1 422 51 is_stmt 1 discriminator 2 1061 04fa 002B cmp r3, #0 1062 04fc B4D0 beq .L67 427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ 431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 1063 .loc 1 431 9 1064 04fe 584B ldr r3, .L156 1065 0500 1B68 ldr r3, [r3] 1066 0502 23F0F802 bic r2, r3, #248 1067 0506 07F50073 add r3, r7, #512 1068 050a A3F5FE73 sub r3, r3, #508 1069 050e 1B68 ldr r3, [r3] 1070 0510 5B69 ldr r3, [r3, #20] 1071 0512 F821 movs r1, #248 1072 0514 C7F84011 str r1, [r7, #320] 1073 .LBB214: 1074 .LBB215: 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 1075 .loc 2 988 4 1076 0518 D7F84011 ldr r1, [r7, #320] 1077 .syntax unified 1078 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 1079 051c 91FAA1F1 rbit r1, r1 1080 @ 0 "" 2 1081 .thumb 1082 .syntax unified 1083 0520 C7F83C11 str r1, [r7, #316] 1084 .loc 2 1001 10 1085 0524 D7F83C11 ldr r1, [r7, #316] 1086 .LBE215: 1087 .LBE214: ARM GAS /tmp/ccSuWkwR.s page 46 1088 .loc 1 431 9 discriminator 1 1089 0528 B1FA81F1 clz r1, r1 1090 .loc 1 431 9 is_stmt 0 discriminator 2 1091 052c C9B2 uxtb r1, r1 1092 052e 8B40 lsls r3, r3, r1 1093 0530 4B49 ldr r1, .L156 1094 0532 1343 orrs r3, r3, r2 1095 0534 0B60 str r3, [r1] 1096 0536 65E0 b .L47 1097 .L58: 1098 0538 0123 movs r3, #1 1099 053a C7F83831 str r3, [r7, #312] 1100 .LBB216: 1101 .LBB217: 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 1102 .loc 2 988 4 is_stmt 1 1103 053e D7F83831 ldr r3, [r7, #312] 1104 .syntax unified 1105 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 1106 0542 93FAA3F3 rbit r3, r3 1107 @ 0 "" 2 1108 .thumb 1109 .syntax unified 1110 0546 C7F83431 str r3, [r7, #308] 1111 .loc 2 1001 10 1112 054a D7F83431 ldr r3, [r7, #308] 1113 .LBE217: 1114 .LBE216: 432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** else 434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Disable the Internal High Speed oscillator (HSI). */ 436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** __HAL_RCC_HSI_DISABLE(); 1115 .loc 1 436 9 discriminator 1 1116 054e B3FA83F3 clz r3, r3 1117 .loc 1 436 9 is_stmt 0 discriminator 2 1118 0552 DBB2 uxtb r3, r3 1119 0554 03F18453 add r3, r3, #276824064 1120 0558 03F58413 add r3, r3, #1081344 1121 055c 9B00 lsls r3, r3, #2 1122 055e 1A46 mov r2, r3 1123 0560 0023 movs r3, #0 1124 0562 1360 str r3, [r2] 437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get Start Tick */ 439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** tickstart = HAL_GetTick(); 1125 .loc 1 439 21 is_stmt 1 1126 0564 FFF7FEFF bl HAL_GetTick 1127 0568 C7F8F801 str r0, [r7, #504] 440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Wait till HSI is disabled */ 442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 1128 .loc 1 442 14 1129 056c 0AE0 b .L70 1130 .L77: 443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) ARM GAS /tmp/ccSuWkwR.s page 47 1131 .loc 1 444 15 1132 056e FFF7FEFF bl HAL_GetTick 1133 0572 0246 mov r2, r0 1134 .loc 1 444 29 discriminator 1 1135 0574 D7F8F831 ldr r3, [r7, #504] 1136 0578 D31A subs r3, r2, r3 1137 .loc 1 444 13 discriminator 1 1138 057a 022B cmp r3, #2 1139 057c 02D9 bls .L70 445:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_TIMEOUT; 1140 .loc 1 446 20 1141 057e 0323 movs r3, #3 1142 0580 00F045BD b .L15 1143 .L70: 1144 0584 0223 movs r3, #2 1145 0586 C7F83031 str r3, [r7, #304] 1146 .LBB218: 1147 .LBB219: 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 1148 .loc 2 988 4 1149 058a D7F83031 ldr r3, [r7, #304] 1150 .syntax unified 1151 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 1152 058e 93FAA3F3 rbit r3, r3 1153 @ 0 "" 2 1154 .thumb 1155 .syntax unified 1156 0592 C7F82C31 str r3, [r7, #300] 1157 .loc 2 1001 10 1158 0596 D7F82C31 ldr r3, [r7, #300] 1159 .LBE219: 1160 .LBE218: 442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 1161 .loc 1 442 15 discriminator 1 1162 059a B3FA83F3 clz r3, r3 442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 1163 .loc 1 442 15 is_stmt 0 discriminator 2 1164 059e DBB2 uxtb r3, r3 1165 05a0 3F2B cmp r3, #63 1166 05a2 02D8 bhi .L72 442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 1167 .loc 1 442 15 discriminator 1 1168 05a4 2E4B ldr r3, .L156 1169 05a6 1B68 ldr r3, [r3] 1170 05a8 13E0 b .L73 1171 .L72: 1172 05aa 0223 movs r3, #2 1173 05ac C7F82831 str r3, [r7, #296] 1174 .LBB220: 1175 .LBB221: 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 1176 .loc 2 988 4 is_stmt 1 1177 05b0 D7F82831 ldr r3, [r7, #296] 1178 .syntax unified 1179 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 1180 05b4 93FAA3F3 rbit r3, r3 ARM GAS /tmp/ccSuWkwR.s page 48 1181 @ 0 "" 2 1182 .thumb 1183 .syntax unified 1184 05b8 C7F82431 str r3, [r7, #292] 1185 05bc 0223 movs r3, #2 1186 05be C7F82031 str r3, [r7, #288] 1187 .LBE221: 1188 .LBE220: 1189 .LBB222: 1190 .LBB223: 1191 05c2 D7F82031 ldr r3, [r7, #288] 1192 .syntax unified 1193 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 1194 05c6 93FAA3F3 rbit r3, r3 1195 @ 0 "" 2 1196 .thumb 1197 .syntax unified 1198 05ca C7F81C31 str r3, [r7, #284] 1199 .LBE223: 1200 .LBE222: 442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 1201 .loc 1 442 15 discriminator 8 1202 05ce 244B ldr r3, .L156 1203 05d0 5B6A ldr r3, [r3, #36] 1204 .L73: 1205 05d2 0222 movs r2, #2 1206 05d4 C7F81821 str r2, [r7, #280] 1207 .LBB224: 1208 .LBB225: 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 1209 .loc 2 988 4 1210 05d8 D7F81821 ldr r2, [r7, #280] 1211 .syntax unified 1212 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 1213 05dc 92FAA2F2 rbit r2, r2 1214 @ 0 "" 2 1215 .thumb 1216 .syntax unified 1217 05e0 C7F81421 str r2, [r7, #276] 1218 .loc 2 1001 10 1219 05e4 D7F81421 ldr r2, [r7, #276] 1220 .LBE225: 1221 .LBE224: 442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 1222 .loc 1 442 15 discriminator 1 1223 05e8 B2FA82F2 clz r2, r2 442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 1224 .loc 1 442 15 is_stmt 0 discriminator 2 1225 05ec D2B2 uxtb r2, r2 1226 05ee 42F02002 orr r2, r2, #32 1227 05f2 D2B2 uxtb r2, r2 1228 05f4 02F01F02 and r2, r2, #31 1229 05f8 0121 movs r1, #1 1230 05fa 01FA02F2 lsl r2, r1, r2 1231 05fe 1340 ands r3, r3, r2 442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 1232 .loc 1 442 51 is_stmt 1 discriminator 2 ARM GAS /tmp/ccSuWkwR.s page 49 1233 0600 002B cmp r3, #0 1234 0602 B4D1 bne .L77 1235 .L47: 447:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 448:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 452:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /*------------------------------ LSI Configuration -------------------------*/ 453:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 1236 .loc 1 453 25 1237 0604 07F50073 add r3, r7, #512 1238 0608 A3F5FE73 sub r3, r3, #508 1239 060c 1B68 ldr r3, [r3] 1240 060e 1B68 ldr r3, [r3] 1241 .loc 1 453 43 1242 0610 03F00803 and r3, r3, #8 1243 .loc 1 453 5 1244 0614 002B cmp r3, #0 1245 0616 00F01581 beq .L78 454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check the parameters */ 456:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); 457:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 458:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check the LSI State */ 459:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) 1246 .loc 1 459 25 1247 061a 07F50073 add r3, r7, #512 1248 061e A3F5FE73 sub r3, r3, #508 1249 0622 1B68 ldr r3, [r3] 1250 0624 9B69 ldr r3, [r3, #24] 1251 .loc 1 459 7 1252 0626 002B cmp r3, #0 1253 0628 7ED0 beq .L79 1254 062a 0123 movs r3, #1 1255 062c C7F81031 str r3, [r7, #272] 1256 .LBB226: 1257 .LBB227: 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 1258 .loc 2 988 4 1259 0630 D7F81031 ldr r3, [r7, #272] 1260 .syntax unified 1261 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 1262 0634 93FAA3F3 rbit r3, r3 1263 @ 0 "" 2 1264 .thumb 1265 .syntax unified 1266 0638 C7F80C31 str r3, [r7, #268] 1267 .loc 2 1001 10 1268 063c D7F80C31 ldr r3, [r7, #268] 1269 .LBE227: 1270 .LBE226: 460:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 461:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Enable the Internal Low Speed oscillator (LSI). */ 462:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** __HAL_RCC_LSI_ENABLE(); 1271 .loc 1 462 7 discriminator 1 1272 0640 B3FA83F3 clz r3, r3 ARM GAS /tmp/ccSuWkwR.s page 50 1273 .loc 1 462 7 is_stmt 0 discriminator 2 1274 0644 DBB2 uxtb r3, r3 1275 0646 1A46 mov r2, r3 1276 0648 064B ldr r3, .L156+4 1277 064a 1344 add r3, r3, r2 1278 064c 9B00 lsls r3, r3, #2 1279 064e 1A46 mov r2, r3 1280 0650 0123 movs r3, #1 1281 0652 1360 str r3, [r2] 463:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get Start Tick */ 465:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** tickstart = HAL_GetTick(); 1282 .loc 1 465 19 is_stmt 1 1283 0654 FFF7FEFF bl HAL_GetTick 1284 0658 C7F8F801 str r0, [r7, #504] 466:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 467:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Wait till LSI is ready */ 468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 1285 .loc 1 468 12 1286 065c 0FE0 b .L81 1287 .L157: 1288 065e 00BF .align 2 1289 .L156: 1290 0660 00100240 .word 1073876992 1291 0664 20819010 .word 277905696 1292 .L86: 469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 470:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) 1293 .loc 1 470 13 1294 0668 FFF7FEFF bl HAL_GetTick 1295 066c 0246 mov r2, r0 1296 .loc 1 470 27 discriminator 1 1297 066e D7F8F831 ldr r3, [r7, #504] 1298 0672 D31A subs r3, r2, r3 1299 .loc 1 470 11 discriminator 1 1300 0674 022B cmp r3, #2 1301 0676 02D9 bls .L81 471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 472:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_TIMEOUT; 1302 .loc 1 472 18 1303 0678 0323 movs r3, #3 1304 067a 00F0C8BC b .L15 1305 .L81: 1306 067e 0223 movs r3, #2 1307 0680 C7F80831 str r3, [r7, #264] 1308 .LBB228: 1309 .LBB229: 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 1310 .loc 2 988 4 1311 0684 D7F80831 ldr r3, [r7, #264] 1312 .syntax unified 1313 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 1314 0688 93FAA3F3 rbit r3, r3 1315 @ 0 "" 2 1316 .thumb 1317 .syntax unified 1318 068c C7F80431 str r3, [r7, #260] ARM GAS /tmp/ccSuWkwR.s page 51 1319 0690 07F50073 add r3, r7, #512 1320 0694 A3F58073 sub r3, r3, #256 1321 0698 0222 movs r2, #2 1322 069a 1A60 str r2, [r3] 1323 .LBE229: 1324 .LBE228: 1325 .LBB230: 1326 .LBB231: 1327 069c 07F50073 add r3, r7, #512 1328 06a0 A3F58073 sub r3, r3, #256 1329 06a4 1B68 ldr r3, [r3] 1330 .syntax unified 1331 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 1332 06a6 93FAA3F2 rbit r2, r3 1333 @ 0 "" 2 1334 .thumb 1335 .syntax unified 1336 06aa 07F50073 add r3, r7, #512 1337 06ae A3F58273 sub r3, r3, #260 1338 06b2 1A60 str r2, [r3] 1339 06b4 07F50073 add r3, r7, #512 1340 06b8 A3F58473 sub r3, r3, #264 1341 06bc 0222 movs r2, #2 1342 06be 1A60 str r2, [r3] 1343 .LBE231: 1344 .LBE230: 1345 .LBB232: 1346 .LBB233: 1347 06c0 07F50073 add r3, r7, #512 1348 06c4 A3F58473 sub r3, r3, #264 1349 06c8 1B68 ldr r3, [r3] 1350 .syntax unified 1351 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 1352 06ca 93FAA3F2 rbit r2, r3 1353 @ 0 "" 2 1354 .thumb 1355 .syntax unified 1356 06ce 07F50073 add r3, r7, #512 1357 06d2 A3F58673 sub r3, r3, #268 1358 06d6 1A60 str r2, [r3] 1359 .LBE233: 1360 .LBE232: 468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 1361 .loc 1 468 13 discriminator 8 1362 06d8 B04B ldr r3, .L158 1363 06da 5A6A ldr r2, [r3, #36] 1364 06dc 07F50073 add r3, r7, #512 1365 06e0 A3F58873 sub r3, r3, #272 1366 06e4 0221 movs r1, #2 1367 06e6 1960 str r1, [r3] 1368 .LBB234: 1369 .LBB235: 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 1370 .loc 2 988 4 1371 06e8 07F50073 add r3, r7, #512 1372 06ec A3F58873 sub r3, r3, #272 1373 06f0 1B68 ldr r3, [r3] ARM GAS /tmp/ccSuWkwR.s page 52 1374 .syntax unified 1375 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 1376 06f2 93FAA3F1 rbit r1, r3 1377 @ 0 "" 2 1378 .thumb 1379 .syntax unified 1380 06f6 07F50073 add r3, r7, #512 1381 06fa A3F58A73 sub r3, r3, #276 1382 06fe 1960 str r1, [r3] 1383 .loc 2 1001 10 1384 0700 07F50073 add r3, r7, #512 1385 0704 A3F58A73 sub r3, r3, #276 1386 0708 1B68 ldr r3, [r3] 1387 .LBE235: 1388 .LBE234: 468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 1389 .loc 1 468 13 discriminator 1 1390 070a B3FA83F3 clz r3, r3 468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 1391 .loc 1 468 13 is_stmt 0 discriminator 2 1392 070e DBB2 uxtb r3, r3 1393 0710 43F06003 orr r3, r3, #96 1394 0714 DBB2 uxtb r3, r3 1395 0716 03F01F03 and r3, r3, #31 1396 071a 0121 movs r1, #1 1397 071c 01FA03F3 lsl r3, r1, r3 1398 0720 1340 ands r3, r3, r2 468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 1399 .loc 1 468 49 is_stmt 1 discriminator 2 1400 0722 002B cmp r3, #0 1401 0724 A0D0 beq .L86 1402 0726 8DE0 b .L78 1403 .L79: 1404 0728 07F50073 add r3, r7, #512 1405 072c A3F58C73 sub r3, r3, #280 1406 0730 0122 movs r2, #1 1407 0732 1A60 str r2, [r3] 1408 .LBB236: 1409 .LBB237: 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 1410 .loc 2 988 4 1411 0734 07F50073 add r3, r7, #512 1412 0738 A3F58C73 sub r3, r3, #280 1413 073c 1B68 ldr r3, [r3] 1414 .syntax unified 1415 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 1416 073e 93FAA3F2 rbit r2, r3 1417 @ 0 "" 2 1418 .thumb 1419 .syntax unified 1420 0742 07F50073 add r3, r7, #512 1421 0746 A3F58E73 sub r3, r3, #284 1422 074a 1A60 str r2, [r3] 1423 .loc 2 1001 10 1424 074c 07F50073 add r3, r7, #512 1425 0750 A3F58E73 sub r3, r3, #284 1426 0754 1B68 ldr r3, [r3] ARM GAS /tmp/ccSuWkwR.s page 53 1427 .LBE237: 1428 .LBE236: 473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 474:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 475:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 476:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** else 477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Disable the Internal Low Speed oscillator (LSI). */ 479:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** __HAL_RCC_LSI_DISABLE(); 1429 .loc 1 479 7 discriminator 1 1430 0756 B3FA83F3 clz r3, r3 1431 .loc 1 479 7 is_stmt 0 discriminator 2 1432 075a DBB2 uxtb r3, r3 1433 075c 1A46 mov r2, r3 1434 075e 904B ldr r3, .L158+4 1435 0760 1344 add r3, r3, r2 1436 0762 9B00 lsls r3, r3, #2 1437 0764 1A46 mov r2, r3 1438 0766 0023 movs r3, #0 1439 0768 1360 str r3, [r2] 480:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 481:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get Start Tick */ 482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** tickstart = HAL_GetTick(); 1440 .loc 1 482 19 is_stmt 1 1441 076a FFF7FEFF bl HAL_GetTick 1442 076e C7F8F801 str r0, [r7, #504] 483:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Wait till LSI is disabled */ 485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 1443 .loc 1 485 12 1444 0772 0AE0 b .L88 1445 .L93: 486:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 487:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) 1446 .loc 1 487 13 1447 0774 FFF7FEFF bl HAL_GetTick 1448 0778 0246 mov r2, r0 1449 .loc 1 487 27 discriminator 1 1450 077a D7F8F831 ldr r3, [r7, #504] 1451 077e D31A subs r3, r2, r3 1452 .loc 1 487 11 discriminator 1 1453 0780 022B cmp r3, #2 1454 0782 02D9 bls .L88 488:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 489:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_TIMEOUT; 1455 .loc 1 489 18 1456 0784 0323 movs r3, #3 1457 0786 00F042BC b .L15 1458 .L88: 1459 078a 07F50073 add r3, r7, #512 1460 078e A3F59073 sub r3, r3, #288 1461 0792 0222 movs r2, #2 1462 0794 1A60 str r2, [r3] 1463 .LBB238: 1464 .LBB239: 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 1465 .loc 2 988 4 ARM GAS /tmp/ccSuWkwR.s page 54 1466 0796 07F50073 add r3, r7, #512 1467 079a A3F59073 sub r3, r3, #288 1468 079e 1B68 ldr r3, [r3] 1469 .syntax unified 1470 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 1471 07a0 93FAA3F2 rbit r2, r3 1472 @ 0 "" 2 1473 .thumb 1474 .syntax unified 1475 07a4 07F50073 add r3, r7, #512 1476 07a8 A3F59273 sub r3, r3, #292 1477 07ac 1A60 str r2, [r3] 1478 07ae 07F50073 add r3, r7, #512 1479 07b2 A3F59473 sub r3, r3, #296 1480 07b6 0222 movs r2, #2 1481 07b8 1A60 str r2, [r3] 1482 .LBE239: 1483 .LBE238: 1484 .LBB240: 1485 .LBB241: 1486 07ba 07F50073 add r3, r7, #512 1487 07be A3F59473 sub r3, r3, #296 1488 07c2 1B68 ldr r3, [r3] 1489 .syntax unified 1490 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 1491 07c4 93FAA3F2 rbit r2, r3 1492 @ 0 "" 2 1493 .thumb 1494 .syntax unified 1495 07c8 07F50073 add r3, r7, #512 1496 07cc A3F59673 sub r3, r3, #300 1497 07d0 1A60 str r2, [r3] 1498 07d2 07F50073 add r3, r7, #512 1499 07d6 A3F59873 sub r3, r3, #304 1500 07da 0222 movs r2, #2 1501 07dc 1A60 str r2, [r3] 1502 .LBE241: 1503 .LBE240: 1504 .LBB242: 1505 .LBB243: 1506 07de 07F50073 add r3, r7, #512 1507 07e2 A3F59873 sub r3, r3, #304 1508 07e6 1B68 ldr r3, [r3] 1509 .syntax unified 1510 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 1511 07e8 93FAA3F2 rbit r2, r3 1512 @ 0 "" 2 1513 .thumb 1514 .syntax unified 1515 07ec 07F50073 add r3, r7, #512 1516 07f0 A3F59A73 sub r3, r3, #308 1517 07f4 1A60 str r2, [r3] 1518 .LBE243: 1519 .LBE242: 485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 1520 .loc 1 485 13 discriminator 8 1521 07f6 694B ldr r3, .L158 ARM GAS /tmp/ccSuWkwR.s page 55 1522 07f8 5A6A ldr r2, [r3, #36] 1523 07fa 07F50073 add r3, r7, #512 1524 07fe A3F59C73 sub r3, r3, #312 1525 0802 0221 movs r1, #2 1526 0804 1960 str r1, [r3] 1527 .LBB244: 1528 .LBB245: 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 1529 .loc 2 988 4 1530 0806 07F50073 add r3, r7, #512 1531 080a A3F59C73 sub r3, r3, #312 1532 080e 1B68 ldr r3, [r3] 1533 .syntax unified 1534 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 1535 0810 93FAA3F1 rbit r1, r3 1536 @ 0 "" 2 1537 .thumb 1538 .syntax unified 1539 0814 07F50073 add r3, r7, #512 1540 0818 A3F59E73 sub r3, r3, #316 1541 081c 1960 str r1, [r3] 1542 .loc 2 1001 10 1543 081e 07F50073 add r3, r7, #512 1544 0822 A3F59E73 sub r3, r3, #316 1545 0826 1B68 ldr r3, [r3] 1546 .LBE245: 1547 .LBE244: 485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 1548 .loc 1 485 13 discriminator 1 1549 0828 B3FA83F3 clz r3, r3 485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 1550 .loc 1 485 13 is_stmt 0 discriminator 2 1551 082c DBB2 uxtb r3, r3 1552 082e 43F06003 orr r3, r3, #96 1553 0832 DBB2 uxtb r3, r3 1554 0834 03F01F03 and r3, r3, #31 1555 0838 0121 movs r1, #1 1556 083a 01FA03F3 lsl r3, r1, r3 1557 083e 1340 ands r3, r3, r2 485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 1558 .loc 1 485 49 is_stmt 1 discriminator 2 1559 0840 002B cmp r3, #0 1560 0842 97D1 bne .L93 1561 .L78: 490:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 492:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 493:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 494:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /*------------------------------ LSE Configuration -------------------------*/ 495:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 1562 .loc 1 495 25 1563 0844 07F50073 add r3, r7, #512 1564 0848 A3F5FE73 sub r3, r3, #508 1565 084c 1B68 ldr r3, [r3] 1566 084e 1B68 ldr r3, [r3] 1567 .loc 1 495 43 1568 0850 03F00403 and r3, r3, #4 ARM GAS /tmp/ccSuWkwR.s page 56 1569 .loc 1 495 5 1570 0854 002B cmp r3, #0 1571 0856 00F09E81 beq .L94 1572 .LBB246: 496:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 497:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** FlagStatus pwrclkchanged = RESET; 1573 .loc 1 497 22 1574 085a 0023 movs r3, #0 1575 085c 87F8FF31 strb r3, [r7, #511] 498:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 499:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check the parameters */ 500:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); 501:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 502:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Update LSE configuration in Backup Domain control register */ 503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Requires to enable write access to Backup Domain of necessary */ 504:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(__HAL_RCC_PWR_IS_CLK_DISABLED()) 1576 .loc 1 504 8 1577 0860 4E4B ldr r3, .L158 1578 0862 DB69 ldr r3, [r3, #28] 1579 0864 03F08053 and r3, r3, #268435456 1580 .loc 1 504 7 1581 0868 002B cmp r3, #0 1582 086a 16D1 bne .L95 1583 .LBB247: 505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 506:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** __HAL_RCC_PWR_CLK_ENABLE(); 1584 .loc 1 506 7 1585 086c 4B4B ldr r3, .L158 1586 086e DB69 ldr r3, [r3, #28] 1587 0870 4A4A ldr r2, .L158 1588 0872 43F08053 orr r3, r3, #268435456 1589 0876 D361 str r3, [r2, #28] 1590 0878 484B ldr r3, .L158 1591 087a DB69 ldr r3, [r3, #28] 1592 087c 03F08052 and r2, r3, #268435456 1593 0880 07F50073 add r3, r7, #512 1594 0884 A3F5FC73 sub r3, r3, #504 1595 0888 1A60 str r2, [r3] 1596 088a 07F50073 add r3, r7, #512 1597 088e A3F5FC73 sub r3, r3, #504 1598 0892 1B68 ldr r3, [r3] 1599 .LBE247: 507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** pwrclkchanged = SET; 1600 .loc 1 507 21 1601 0894 0123 movs r3, #1 1602 0896 87F8FF31 strb r3, [r7, #511] 1603 .L95: 508:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 509:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 1604 .loc 1 510 8 1605 089a 424B ldr r3, .L158+8 1606 089c 1B68 ldr r3, [r3] 1607 089e 03F48073 and r3, r3, #256 1608 .loc 1 510 7 1609 08a2 002B cmp r3, #0 1610 08a4 1AD1 bne .L96 ARM GAS /tmp/ccSuWkwR.s page 57 511:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 512:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Enable write access to Backup domain */ 513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** SET_BIT(PWR->CR, PWR_CR_DBP); 1611 .loc 1 513 7 1612 08a6 3F4B ldr r3, .L158+8 1613 08a8 1B68 ldr r3, [r3] 1614 08aa 3E4A ldr r2, .L158+8 1615 08ac 43F48073 orr r3, r3, #256 1616 08b0 1360 str r3, [r2] 514:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 515:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Wait for Backup domain Write protection disable */ 516:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** tickstart = HAL_GetTick(); 1617 .loc 1 516 19 1618 08b2 FFF7FEFF bl HAL_GetTick 1619 08b6 C7F8F801 str r0, [r7, #504] 517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 1620 .loc 1 518 12 1621 08ba 09E0 b .L97 1622 .L98: 519:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 520:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 1623 .loc 1 520 13 1624 08bc FFF7FEFF bl HAL_GetTick 1625 08c0 0246 mov r2, r0 1626 .loc 1 520 27 discriminator 1 1627 08c2 D7F8F831 ldr r3, [r7, #504] 1628 08c6 D31A subs r3, r2, r3 1629 .loc 1 520 11 discriminator 1 1630 08c8 642B cmp r3, #100 1631 08ca 01D9 bls .L97 521:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_TIMEOUT; 1632 .loc 1 522 18 1633 08cc 0323 movs r3, #3 1634 08ce 9EE3 b .L15 1635 .L97: 518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 1636 .loc 1 518 13 1637 08d0 344B ldr r3, .L158+8 1638 08d2 1B68 ldr r3, [r3] 1639 08d4 03F48073 and r3, r3, #256 1640 08d8 002B cmp r3, #0 1641 08da EFD0 beq .L98 1642 .L96: 523:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 524:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 525:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 526:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 527:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Set the new LSE configuration -----------------------------------------*/ 528:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 1643 .loc 1 528 5 1644 08dc 07F50073 add r3, r7, #512 1645 08e0 A3F5FE73 sub r3, r3, #508 1646 08e4 1B68 ldr r3, [r3] 1647 08e6 DB68 ldr r3, [r3, #12] 1648 08e8 012B cmp r3, #1 ARM GAS /tmp/ccSuWkwR.s page 58 1649 08ea 06D1 bne .L99 1650 .loc 1 528 5 is_stmt 0 discriminator 1 1651 08ec 2B4B ldr r3, .L158 1652 08ee 1B6A ldr r3, [r3, #32] 1653 08f0 2A4A ldr r2, .L158 1654 08f2 43F00103 orr r3, r3, #1 1655 08f6 1362 str r3, [r2, #32] 1656 08f8 35E0 b .L100 1657 .L99: 1658 .loc 1 528 5 discriminator 2 1659 08fa 07F50073 add r3, r7, #512 1660 08fe A3F5FE73 sub r3, r3, #508 1661 0902 1B68 ldr r3, [r3] 1662 0904 DB68 ldr r3, [r3, #12] 1663 0906 002B cmp r3, #0 1664 0908 0CD1 bne .L101 1665 .loc 1 528 5 discriminator 3 1666 090a 244B ldr r3, .L158 1667 090c 1B6A ldr r3, [r3, #32] 1668 090e 234A ldr r2, .L158 1669 0910 23F00103 bic r3, r3, #1 1670 0914 1362 str r3, [r2, #32] 1671 0916 214B ldr r3, .L158 1672 0918 1B6A ldr r3, [r3, #32] 1673 091a 204A ldr r2, .L158 1674 091c 23F00403 bic r3, r3, #4 1675 0920 1362 str r3, [r2, #32] 1676 0922 20E0 b .L100 1677 .L101: 1678 .loc 1 528 5 discriminator 4 1679 0924 07F50073 add r3, r7, #512 1680 0928 A3F5FE73 sub r3, r3, #508 1681 092c 1B68 ldr r3, [r3] 1682 092e DB68 ldr r3, [r3, #12] 1683 0930 052B cmp r3, #5 1684 0932 0CD1 bne .L102 1685 .loc 1 528 5 discriminator 5 1686 0934 194B ldr r3, .L158 1687 0936 1B6A ldr r3, [r3, #32] 1688 0938 184A ldr r2, .L158 1689 093a 43F00403 orr r3, r3, #4 1690 093e 1362 str r3, [r2, #32] 1691 0940 164B ldr r3, .L158 1692 0942 1B6A ldr r3, [r3, #32] 1693 0944 154A ldr r2, .L158 1694 0946 43F00103 orr r3, r3, #1 1695 094a 1362 str r3, [r2, #32] 1696 094c 0BE0 b .L100 1697 .L102: 1698 .loc 1 528 5 discriminator 6 1699 094e 134B ldr r3, .L158 1700 0950 1B6A ldr r3, [r3, #32] 1701 0952 124A ldr r2, .L158 1702 0954 23F00103 bic r3, r3, #1 1703 0958 1362 str r3, [r2, #32] 1704 095a 104B ldr r3, .L158 1705 095c 1B6A ldr r3, [r3, #32] ARM GAS /tmp/ccSuWkwR.s page 59 1706 095e 0F4A ldr r2, .L158 1707 0960 23F00403 bic r3, r3, #4 1708 0964 1362 str r3, [r2, #32] 1709 .L100: 529:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check the LSE State */ 530:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF) 1710 .loc 1 530 25 is_stmt 1 1711 0966 07F50073 add r3, r7, #512 1712 096a A3F5FE73 sub r3, r3, #508 1713 096e 1B68 ldr r3, [r3] 1714 0970 DB68 ldr r3, [r3, #12] 1715 .loc 1 530 7 1716 0972 002B cmp r3, #0 1717 0974 00F08780 beq .L103 531:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 532:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get Start Tick */ 533:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** tickstart = HAL_GetTick(); 1718 .loc 1 533 19 1719 0978 FFF7FEFF bl HAL_GetTick 1720 097c C7F8F801 str r0, [r7, #504] 534:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Wait till LSE is ready */ 536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 1721 .loc 1 536 12 1722 0980 12E0 b .L104 1723 .L111: 537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 538:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) 1724 .loc 1 538 13 1725 0982 FFF7FEFF bl HAL_GetTick 1726 0986 0246 mov r2, r0 1727 .loc 1 538 27 discriminator 1 1728 0988 D7F8F831 ldr r3, [r7, #504] 1729 098c D31A subs r3, r2, r3 1730 .loc 1 538 11 discriminator 1 1731 098e 41F28832 movw r2, #5000 1732 0992 9342 cmp r3, r2 1733 0994 08D9 bls .L104 539:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 540:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_TIMEOUT; 1734 .loc 1 540 18 1735 0996 0323 movs r3, #3 1736 0998 39E3 b .L15 1737 .L159: 1738 099a 00BF .align 2 1739 .L158: 1740 099c 00100240 .word 1073876992 1741 09a0 20819010 .word 277905696 1742 09a4 00700040 .word 1073770496 1743 .L104: 1744 09a8 07F50073 add r3, r7, #512 1745 09ac A3F5A073 sub r3, r3, #320 1746 09b0 0222 movs r2, #2 1747 09b2 1A60 str r2, [r3] 1748 .LBB248: 1749 .LBB249: 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else ARM GAS /tmp/ccSuWkwR.s page 60 1750 .loc 2 988 4 1751 09b4 07F50073 add r3, r7, #512 1752 09b8 A3F5A073 sub r3, r3, #320 1753 09bc 1B68 ldr r3, [r3] 1754 .syntax unified 1755 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 1756 09be 93FAA3F2 rbit r2, r3 1757 @ 0 "" 2 1758 .thumb 1759 .syntax unified 1760 09c2 07F50073 add r3, r7, #512 1761 09c6 A3F5A273 sub r3, r3, #324 1762 09ca 1A60 str r2, [r3] 1763 09cc 07F50073 add r3, r7, #512 1764 09d0 A3F5A473 sub r3, r3, #328 1765 09d4 0222 movs r2, #2 1766 09d6 1A60 str r2, [r3] 1767 .LBE249: 1768 .LBE248: 1769 .LBB250: 1770 .LBB251: 1771 09d8 07F50073 add r3, r7, #512 1772 09dc A3F5A473 sub r3, r3, #328 1773 09e0 1B68 ldr r3, [r3] 1774 .syntax unified 1775 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 1776 09e2 93FAA3F2 rbit r2, r3 1777 @ 0 "" 2 1778 .thumb 1779 .syntax unified 1780 09e6 07F50073 add r3, r7, #512 1781 09ea A3F5A673 sub r3, r3, #332 1782 09ee 1A60 str r2, [r3] 1783 .loc 2 1001 10 1784 09f0 07F50073 add r3, r7, #512 1785 09f4 A3F5A673 sub r3, r3, #332 1786 09f8 1B68 ldr r3, [r3] 1787 .LBE251: 1788 .LBE250: 536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 1789 .loc 1 536 13 discriminator 1 1790 09fa B3FA83F3 clz r3, r3 536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 1791 .loc 1 536 13 is_stmt 0 discriminator 2 1792 09fe DBB2 uxtb r3, r3 1793 0a00 23F05F03 bic r3, r3, #95 1794 0a04 DBB2 uxtb r3, r3 1795 0a06 002B cmp r3, #0 1796 0a08 02D1 bne .L107 536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 1797 .loc 1 536 13 discriminator 4 1798 0a0a 984B ldr r3, .L160 1799 0a0c 1B6A ldr r3, [r3, #32] 1800 0a0e 13E0 b .L108 1801 .L107: 1802 0a10 07F50073 add r3, r7, #512 1803 0a14 A3F5A873 sub r3, r3, #336 ARM GAS /tmp/ccSuWkwR.s page 61 1804 0a18 0222 movs r2, #2 1805 0a1a 1A60 str r2, [r3] 1806 .LBB252: 1807 .LBB253: 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 1808 .loc 2 988 4 is_stmt 1 1809 0a1c 07F50073 add r3, r7, #512 1810 0a20 A3F5A873 sub r3, r3, #336 1811 0a24 1B68 ldr r3, [r3] 1812 .syntax unified 1813 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 1814 0a26 93FAA3F2 rbit r2, r3 1815 @ 0 "" 2 1816 .thumb 1817 .syntax unified 1818 0a2a 07F50073 add r3, r7, #512 1819 0a2e A3F5AA73 sub r3, r3, #340 1820 0a32 1A60 str r2, [r3] 1821 .LBE253: 1822 .LBE252: 536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 1823 .loc 1 536 13 discriminator 8 1824 0a34 8D4B ldr r3, .L160 1825 0a36 5B6A ldr r3, [r3, #36] 1826 .L108: 1827 0a38 07F50072 add r2, r7, #512 1828 0a3c A2F5AC72 sub r2, r2, #344 1829 0a40 0221 movs r1, #2 1830 0a42 1160 str r1, [r2] 1831 .LBB254: 1832 .LBB255: 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 1833 .loc 2 988 4 1834 0a44 07F50072 add r2, r7, #512 1835 0a48 A2F5AC72 sub r2, r2, #344 1836 0a4c 1268 ldr r2, [r2] 1837 .syntax unified 1838 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 1839 0a4e 92FAA2F1 rbit r1, r2 1840 @ 0 "" 2 1841 .thumb 1842 .syntax unified 1843 0a52 07F50072 add r2, r7, #512 1844 0a56 A2F5AE72 sub r2, r2, #348 1845 0a5a 1160 str r1, [r2] 1846 .loc 2 1001 10 1847 0a5c 07F50072 add r2, r7, #512 1848 0a60 A2F5AE72 sub r2, r2, #348 1849 0a64 1268 ldr r2, [r2] 1850 .LBE255: 1851 .LBE254: 536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 1852 .loc 1 536 13 discriminator 1 1853 0a66 B2FA82F2 clz r2, r2 536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 1854 .loc 1 536 13 is_stmt 0 discriminator 2 1855 0a6a D2B2 uxtb r2, r2 ARM GAS /tmp/ccSuWkwR.s page 62 1856 0a6c 42F04002 orr r2, r2, #64 1857 0a70 D2B2 uxtb r2, r2 1858 0a72 02F01F02 and r2, r2, #31 1859 0a76 0121 movs r1, #1 1860 0a78 01FA02F2 lsl r2, r1, r2 1861 0a7c 1340 ands r3, r3, r2 536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 1862 .loc 1 536 49 is_stmt 1 discriminator 2 1863 0a7e 002B cmp r3, #0 1864 0a80 3FF47FAF beq .L111 1865 0a84 7DE0 b .L112 1866 .L103: 541:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 543:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 544:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** else 545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 546:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get Start Tick */ 547:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** tickstart = HAL_GetTick(); 1867 .loc 1 547 19 1868 0a86 FFF7FEFF bl HAL_GetTick 1869 0a8a C7F8F801 str r0, [r7, #504] 548:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 549:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Wait till LSE is disabled */ 550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 1870 .loc 1 550 12 1871 0a8e 0BE0 b .L113 1872 .L120: 551:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 552:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) 1873 .loc 1 552 13 1874 0a90 FFF7FEFF bl HAL_GetTick 1875 0a94 0246 mov r2, r0 1876 .loc 1 552 27 discriminator 1 1877 0a96 D7F8F831 ldr r3, [r7, #504] 1878 0a9a D31A subs r3, r2, r3 1879 .loc 1 552 11 discriminator 1 1880 0a9c 41F28832 movw r2, #5000 1881 0aa0 9342 cmp r3, r2 1882 0aa2 01D9 bls .L113 553:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 554:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_TIMEOUT; 1883 .loc 1 554 18 1884 0aa4 0323 movs r3, #3 1885 0aa6 B2E2 b .L15 1886 .L113: 1887 0aa8 07F50073 add r3, r7, #512 1888 0aac A3F5B073 sub r3, r3, #352 1889 0ab0 0222 movs r2, #2 1890 0ab2 1A60 str r2, [r3] 1891 .LBB256: 1892 .LBB257: 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 1893 .loc 2 988 4 1894 0ab4 07F50073 add r3, r7, #512 1895 0ab8 A3F5B073 sub r3, r3, #352 1896 0abc 1B68 ldr r3, [r3] ARM GAS /tmp/ccSuWkwR.s page 63 1897 .syntax unified 1898 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 1899 0abe 93FAA3F2 rbit r2, r3 1900 @ 0 "" 2 1901 .thumb 1902 .syntax unified 1903 0ac2 07F50073 add r3, r7, #512 1904 0ac6 A3F5B273 sub r3, r3, #356 1905 0aca 1A60 str r2, [r3] 1906 0acc 07F50073 add r3, r7, #512 1907 0ad0 A3F5B473 sub r3, r3, #360 1908 0ad4 0222 movs r2, #2 1909 0ad6 1A60 str r2, [r3] 1910 .LBE257: 1911 .LBE256: 1912 .LBB258: 1913 .LBB259: 1914 0ad8 07F50073 add r3, r7, #512 1915 0adc A3F5B473 sub r3, r3, #360 1916 0ae0 1B68 ldr r3, [r3] 1917 .syntax unified 1918 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 1919 0ae2 93FAA3F2 rbit r2, r3 1920 @ 0 "" 2 1921 .thumb 1922 .syntax unified 1923 0ae6 07F50073 add r3, r7, #512 1924 0aea A3F5B673 sub r3, r3, #364 1925 0aee 1A60 str r2, [r3] 1926 .loc 2 1001 10 1927 0af0 07F50073 add r3, r7, #512 1928 0af4 A3F5B673 sub r3, r3, #364 1929 0af8 1B68 ldr r3, [r3] 1930 .LBE259: 1931 .LBE258: 550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 1932 .loc 1 550 13 discriminator 1 1933 0afa B3FA83F3 clz r3, r3 550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 1934 .loc 1 550 13 is_stmt 0 discriminator 2 1935 0afe DBB2 uxtb r3, r3 1936 0b00 23F05F03 bic r3, r3, #95 1937 0b04 DBB2 uxtb r3, r3 1938 0b06 002B cmp r3, #0 1939 0b08 02D1 bne .L116 550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 1940 .loc 1 550 13 discriminator 4 1941 0b0a 584B ldr r3, .L160 1942 0b0c 1B6A ldr r3, [r3, #32] 1943 0b0e 13E0 b .L117 1944 .L116: 1945 0b10 07F50073 add r3, r7, #512 1946 0b14 A3F5B873 sub r3, r3, #368 1947 0b18 0222 movs r2, #2 1948 0b1a 1A60 str r2, [r3] 1949 .LBB260: 1950 .LBB261: ARM GAS /tmp/ccSuWkwR.s page 64 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 1951 .loc 2 988 4 is_stmt 1 1952 0b1c 07F50073 add r3, r7, #512 1953 0b20 A3F5B873 sub r3, r3, #368 1954 0b24 1B68 ldr r3, [r3] 1955 .syntax unified 1956 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 1957 0b26 93FAA3F2 rbit r2, r3 1958 @ 0 "" 2 1959 .thumb 1960 .syntax unified 1961 0b2a 07F50073 add r3, r7, #512 1962 0b2e A3F5BA73 sub r3, r3, #372 1963 0b32 1A60 str r2, [r3] 1964 .LBE261: 1965 .LBE260: 550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 1966 .loc 1 550 13 discriminator 8 1967 0b34 4D4B ldr r3, .L160 1968 0b36 5B6A ldr r3, [r3, #36] 1969 .L117: 1970 0b38 07F50072 add r2, r7, #512 1971 0b3c A2F5BC72 sub r2, r2, #376 1972 0b40 0221 movs r1, #2 1973 0b42 1160 str r1, [r2] 1974 .LBB262: 1975 .LBB263: 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 1976 .loc 2 988 4 1977 0b44 07F50072 add r2, r7, #512 1978 0b48 A2F5BC72 sub r2, r2, #376 1979 0b4c 1268 ldr r2, [r2] 1980 .syntax unified 1981 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 1982 0b4e 92FAA2F1 rbit r1, r2 1983 @ 0 "" 2 1984 .thumb 1985 .syntax unified 1986 0b52 07F50072 add r2, r7, #512 1987 0b56 A2F5BE72 sub r2, r2, #380 1988 0b5a 1160 str r1, [r2] 1989 .loc 2 1001 10 1990 0b5c 07F50072 add r2, r7, #512 1991 0b60 A2F5BE72 sub r2, r2, #380 1992 0b64 1268 ldr r2, [r2] 1993 .LBE263: 1994 .LBE262: 550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 1995 .loc 1 550 13 discriminator 1 1996 0b66 B2FA82F2 clz r2, r2 550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 1997 .loc 1 550 13 is_stmt 0 discriminator 2 1998 0b6a D2B2 uxtb r2, r2 1999 0b6c 42F04002 orr r2, r2, #64 2000 0b70 D2B2 uxtb r2, r2 2001 0b72 02F01F02 and r2, r2, #31 2002 0b76 0121 movs r1, #1 ARM GAS /tmp/ccSuWkwR.s page 65 2003 0b78 01FA02F2 lsl r2, r1, r2 2004 0b7c 1340 ands r3, r3, r2 550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 2005 .loc 1 550 49 is_stmt 1 discriminator 2 2006 0b7e 002B cmp r3, #0 2007 0b80 86D1 bne .L120 2008 .L112: 555:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 556:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 557:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 558:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 559:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Require to disable power clock if necessary */ 560:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(pwrclkchanged == SET) 2009 .loc 1 560 7 2010 0b82 97F8FF31 ldrb r3, [r7, #511] @ zero_extendqisi2 2011 0b86 012B cmp r3, #1 2012 0b88 05D1 bne .L94 561:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 562:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** __HAL_RCC_PWR_CLK_DISABLE(); 2013 .loc 1 562 7 2014 0b8a 384B ldr r3, .L160 2015 0b8c DB69 ldr r3, [r3, #28] 2016 0b8e 374A ldr r2, .L160 2017 0b90 23F08053 bic r3, r3, #268435456 2018 0b94 D361 str r3, [r2, #28] 2019 .L94: 2020 .LBE246: 563:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 564:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 565:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 566:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /*-------------------------------- PLL Configuration -----------------------*/ 567:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check the parameters */ 568:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); 569:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 2021 .loc 1 569 30 2022 0b96 07F50073 add r3, r7, #512 2023 0b9a A3F5FE73 sub r3, r3, #508 2024 0b9e 1B68 ldr r3, [r3] 2025 0ba0 DB69 ldr r3, [r3, #28] 2026 .loc 1 569 6 2027 0ba2 002B cmp r3, #0 2028 0ba4 00F03282 beq .L121 570:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 571:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check if the PLL is used as system clock or not */ 572:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) 2029 .loc 1 572 8 2030 0ba8 304B ldr r3, .L160 2031 0baa 5B68 ldr r3, [r3, #4] 2032 0bac 03F00C03 and r3, r3, #12 2033 .loc 1 572 7 2034 0bb0 082B cmp r3, #8 2035 0bb2 00F00182 beq .L122 573:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 574:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 2036 .loc 1 574 33 2037 0bb6 07F50073 add r3, r7, #512 2038 0bba A3F5FE73 sub r3, r3, #508 ARM GAS /tmp/ccSuWkwR.s page 66 2039 0bbe 1B68 ldr r3, [r3] 2040 0bc0 DB69 ldr r3, [r3, #28] 2041 .loc 1 574 9 2042 0bc2 022B cmp r3, #2 2043 0bc4 40F05781 bne .L123 2044 0bc8 07F50073 add r3, r7, #512 2045 0bcc A3F5C073 sub r3, r3, #384 2046 0bd0 4FF08072 mov r2, #16777216 2047 0bd4 1A60 str r2, [r3] 2048 .LBB264: 2049 .LBB265: 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 2050 .loc 2 988 4 2051 0bd6 07F50073 add r3, r7, #512 2052 0bda A3F5C073 sub r3, r3, #384 2053 0bde 1B68 ldr r3, [r3] 2054 .syntax unified 2055 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 2056 0be0 93FAA3F2 rbit r2, r3 2057 @ 0 "" 2 2058 .thumb 2059 .syntax unified 2060 0be4 07F50073 add r3, r7, #512 2061 0be8 A3F5C273 sub r3, r3, #388 2062 0bec 1A60 str r2, [r3] 2063 .loc 2 1001 10 2064 0bee 07F50073 add r3, r7, #512 2065 0bf2 A3F5C273 sub r3, r3, #388 2066 0bf6 1B68 ldr r3, [r3] 2067 .LBE265: 2068 .LBE264: 575:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 576:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check the parameters */ 577:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); 578:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); 579:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #if defined(RCC_CFGR_PLLSRC_HSI_PREDIV) 580:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** assert_param(IS_RCC_PREDIV(RCC_OscInitStruct->PLL.PREDIV)); 581:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #endif 582:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 583:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Disable the main PLL. */ 584:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** __HAL_RCC_PLL_DISABLE(); 2069 .loc 1 584 9 discriminator 1 2070 0bf8 B3FA83F3 clz r3, r3 2071 .loc 1 584 9 is_stmt 0 discriminator 2 2072 0bfc DBB2 uxtb r3, r3 2073 0bfe 03F18453 add r3, r3, #276824064 2074 0c02 03F58413 add r3, r3, #1081344 2075 0c06 9B00 lsls r3, r3, #2 2076 0c08 1A46 mov r2, r3 2077 0c0a 0023 movs r3, #0 2078 0c0c 1360 str r3, [r2] 585:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 586:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get Start Tick */ 587:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** tickstart = HAL_GetTick(); 2079 .loc 1 587 21 is_stmt 1 2080 0c0e FFF7FEFF bl HAL_GetTick 2081 0c12 C7F8F801 str r0, [r7, #504] ARM GAS /tmp/ccSuWkwR.s page 67 588:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 589:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Wait till PLL is disabled */ 590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 2082 .loc 1 590 14 2083 0c16 09E0 b .L125 2084 .L132: 591:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 592:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 2085 .loc 1 592 15 2086 0c18 FFF7FEFF bl HAL_GetTick 2087 0c1c 0246 mov r2, r0 2088 .loc 1 592 29 discriminator 1 2089 0c1e D7F8F831 ldr r3, [r7, #504] 2090 0c22 D31A subs r3, r2, r3 2091 .loc 1 592 13 discriminator 1 2092 0c24 022B cmp r3, #2 2093 0c26 01D9 bls .L125 593:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 594:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_TIMEOUT; 2094 .loc 1 594 20 2095 0c28 0323 movs r3, #3 2096 0c2a F0E1 b .L15 2097 .L125: 2098 0c2c 07F50073 add r3, r7, #512 2099 0c30 A3F5C473 sub r3, r3, #392 2100 0c34 4FF00072 mov r2, #33554432 2101 0c38 1A60 str r2, [r3] 2102 .LBB266: 2103 .LBB267: 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 2104 .loc 2 988 4 2105 0c3a 07F50073 add r3, r7, #512 2106 0c3e A3F5C473 sub r3, r3, #392 2107 0c42 1B68 ldr r3, [r3] 2108 .syntax unified 2109 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 2110 0c44 93FAA3F2 rbit r2, r3 2111 @ 0 "" 2 2112 .thumb 2113 .syntax unified 2114 0c48 07F50073 add r3, r7, #512 2115 0c4c A3F5C673 sub r3, r3, #396 2116 0c50 1A60 str r2, [r3] 2117 .loc 2 1001 10 2118 0c52 07F50073 add r3, r7, #512 2119 0c56 A3F5C673 sub r3, r3, #396 2120 0c5a 1B68 ldr r3, [r3] 2121 .LBE267: 2122 .LBE266: 590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 2123 .loc 1 590 15 discriminator 1 2124 0c5c B3FA83F3 clz r3, r3 590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 2125 .loc 1 590 15 is_stmt 0 discriminator 2 2126 0c60 DBB2 uxtb r3, r3 2127 0c62 3F2B cmp r3, #63 2128 0c64 04D8 bhi .L127 ARM GAS /tmp/ccSuWkwR.s page 68 590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 2129 .loc 1 590 15 discriminator 1 2130 0c66 014B ldr r3, .L160 2131 0c68 1B68 ldr r3, [r3] 2132 0c6a 29E0 b .L128 2133 .L161: 2134 .align 2 2135 .L160: 2136 0c6c 00100240 .word 1073876992 2137 .L127: 2138 0c70 07F50073 add r3, r7, #512 2139 0c74 A3F5C873 sub r3, r3, #400 2140 0c78 4FF00072 mov r2, #33554432 2141 0c7c 1A60 str r2, [r3] 2142 .LBB268: 2143 .LBB269: 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 2144 .loc 2 988 4 is_stmt 1 2145 0c7e 07F50073 add r3, r7, #512 2146 0c82 A3F5C873 sub r3, r3, #400 2147 0c86 1B68 ldr r3, [r3] 2148 .syntax unified 2149 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 2150 0c88 93FAA3F2 rbit r2, r3 2151 @ 0 "" 2 2152 .thumb 2153 .syntax unified 2154 0c8c 07F50073 add r3, r7, #512 2155 0c90 A3F5CA73 sub r3, r3, #404 2156 0c94 1A60 str r2, [r3] 2157 0c96 07F50073 add r3, r7, #512 2158 0c9a A3F5CC73 sub r3, r3, #408 2159 0c9e 4FF00072 mov r2, #33554432 2160 0ca2 1A60 str r2, [r3] 2161 .LBE269: 2162 .LBE268: 2163 .LBB270: 2164 .LBB271: 2165 0ca4 07F50073 add r3, r7, #512 2166 0ca8 A3F5CC73 sub r3, r3, #408 2167 0cac 1B68 ldr r3, [r3] 2168 .syntax unified 2169 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 2170 0cae 93FAA3F2 rbit r2, r3 2171 @ 0 "" 2 2172 .thumb 2173 .syntax unified 2174 0cb2 07F50073 add r3, r7, #512 2175 0cb6 A3F5CE73 sub r3, r3, #412 2176 0cba 1A60 str r2, [r3] 2177 .LBE271: 2178 .LBE270: 590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 2179 .loc 1 590 15 discriminator 8 2180 0cbc C34B ldr r3, .L162 2181 0cbe 5B6A ldr r3, [r3, #36] 2182 .L128: ARM GAS /tmp/ccSuWkwR.s page 69 2183 0cc0 07F50072 add r2, r7, #512 2184 0cc4 A2F5D072 sub r2, r2, #416 2185 0cc8 4FF00071 mov r1, #33554432 2186 0ccc 1160 str r1, [r2] 2187 .LBB272: 2188 .LBB273: 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 2189 .loc 2 988 4 2190 0cce 07F50072 add r2, r7, #512 2191 0cd2 A2F5D072 sub r2, r2, #416 2192 0cd6 1268 ldr r2, [r2] 2193 .syntax unified 2194 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 2195 0cd8 92FAA2F1 rbit r1, r2 2196 @ 0 "" 2 2197 .thumb 2198 .syntax unified 2199 0cdc 07F50072 add r2, r7, #512 2200 0ce0 A2F5D272 sub r2, r2, #420 2201 0ce4 1160 str r1, [r2] 2202 .loc 2 1001 10 2203 0ce6 07F50072 add r2, r7, #512 2204 0cea A2F5D272 sub r2, r2, #420 2205 0cee 1268 ldr r2, [r2] 2206 .LBE273: 2207 .LBE272: 590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 2208 .loc 1 590 15 discriminator 1 2209 0cf0 B2FA82F2 clz r2, r2 590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 2210 .loc 1 590 15 is_stmt 0 discriminator 2 2211 0cf4 D2B2 uxtb r2, r2 2212 0cf6 42F02002 orr r2, r2, #32 2213 0cfa D2B2 uxtb r2, r2 2214 0cfc 02F01F02 and r2, r2, #31 2215 0d00 0121 movs r1, #1 2216 0d02 01FA02F2 lsl r2, r1, r2 2217 0d06 1340 ands r3, r3, r2 590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 2218 .loc 1 590 52 is_stmt 1 discriminator 2 2219 0d08 002B cmp r3, #0 2220 0d0a 85D1 bne .L132 595:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 596:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 597:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 598:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #if defined(RCC_CFGR_PLLSRC_HSI_PREDIV) 599:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Configure the main PLL clock source, predivider and multiplication factor. */ 600:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 601:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PREDIV, 602:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLMUL); 603:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #else 604:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Configure the main PLL clock source and multiplication factor. */ 605:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 2221 .loc 1 605 7 2222 0d0c AF4B ldr r3, .L162 2223 0d0e 5B68 ldr r3, [r3, #4] 2224 0d10 23F47412 bic r2, r3, #3997696 ARM GAS /tmp/ccSuWkwR.s page 70 2225 0d14 07F50073 add r3, r7, #512 2226 0d18 A3F5FE73 sub r3, r3, #508 2227 0d1c 1B68 ldr r3, [r3] 2228 0d1e 596A ldr r1, [r3, #36] 2229 0d20 07F50073 add r3, r7, #512 2230 0d24 A3F5FE73 sub r3, r3, #508 2231 0d28 1B68 ldr r3, [r3] 2232 0d2a 1B6A ldr r3, [r3, #32] 2233 0d2c 0B43 orrs r3, r3, r1 2234 0d2e A749 ldr r1, .L162 2235 0d30 1343 orrs r3, r3, r2 2236 0d32 4B60 str r3, [r1, #4] 2237 0d34 07F50073 add r3, r7, #512 2238 0d38 A3F5D473 sub r3, r3, #424 2239 0d3c 4FF08072 mov r2, #16777216 2240 0d40 1A60 str r2, [r3] 2241 .LBB274: 2242 .LBB275: 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 2243 .loc 2 988 4 2244 0d42 07F50073 add r3, r7, #512 2245 0d46 A3F5D473 sub r3, r3, #424 2246 0d4a 1B68 ldr r3, [r3] 2247 .syntax unified 2248 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 2249 0d4c 93FAA3F2 rbit r2, r3 2250 @ 0 "" 2 2251 .thumb 2252 .syntax unified 2253 0d50 07F50073 add r3, r7, #512 2254 0d54 A3F5D673 sub r3, r3, #428 2255 0d58 1A60 str r2, [r3] 2256 .loc 2 1001 10 2257 0d5a 07F50073 add r3, r7, #512 2258 0d5e A3F5D673 sub r3, r3, #428 2259 0d62 1B68 ldr r3, [r3] 2260 .LBE275: 2261 .LBE274: 606:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLMUL); 607:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #endif /* RCC_CFGR_PLLSRC_HSI_PREDIV */ 608:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Enable the main PLL. */ 609:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** __HAL_RCC_PLL_ENABLE(); 2262 .loc 1 609 9 discriminator 1 2263 0d64 B3FA83F3 clz r3, r3 2264 .loc 1 609 9 is_stmt 0 discriminator 2 2265 0d68 DBB2 uxtb r3, r3 2266 0d6a 03F18453 add r3, r3, #276824064 2267 0d6e 03F58413 add r3, r3, #1081344 2268 0d72 9B00 lsls r3, r3, #2 2269 0d74 1A46 mov r2, r3 2270 0d76 0123 movs r3, #1 2271 0d78 1360 str r3, [r2] 610:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 611:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get Start Tick */ 612:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** tickstart = HAL_GetTick(); 2272 .loc 1 612 21 is_stmt 1 2273 0d7a FFF7FEFF bl HAL_GetTick ARM GAS /tmp/ccSuWkwR.s page 71 2274 0d7e C7F8F801 str r0, [r7, #504] 613:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 614:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Wait till PLL is ready */ 615:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 2275 .loc 1 615 14 2276 0d82 09E0 b .L134 2277 .L141: 616:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 617:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 2278 .loc 1 617 15 2279 0d84 FFF7FEFF bl HAL_GetTick 2280 0d88 0246 mov r2, r0 2281 .loc 1 617 29 discriminator 1 2282 0d8a D7F8F831 ldr r3, [r7, #504] 2283 0d8e D31A subs r3, r2, r3 2284 .loc 1 617 13 discriminator 1 2285 0d90 022B cmp r3, #2 2286 0d92 01D9 bls .L134 618:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 619:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_TIMEOUT; 2287 .loc 1 619 20 2288 0d94 0323 movs r3, #3 2289 0d96 3AE1 b .L15 2290 .L134: 2291 0d98 07F50073 add r3, r7, #512 2292 0d9c A3F5D873 sub r3, r3, #432 2293 0da0 4FF00072 mov r2, #33554432 2294 0da4 1A60 str r2, [r3] 2295 .LBB276: 2296 .LBB277: 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 2297 .loc 2 988 4 2298 0da6 07F50073 add r3, r7, #512 2299 0daa A3F5D873 sub r3, r3, #432 2300 0dae 1B68 ldr r3, [r3] 2301 .syntax unified 2302 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 2303 0db0 93FAA3F2 rbit r2, r3 2304 @ 0 "" 2 2305 .thumb 2306 .syntax unified 2307 0db4 07F50073 add r3, r7, #512 2308 0db8 A3F5DA73 sub r3, r3, #436 2309 0dbc 1A60 str r2, [r3] 2310 .loc 2 1001 10 2311 0dbe 07F50073 add r3, r7, #512 2312 0dc2 A3F5DA73 sub r3, r3, #436 2313 0dc6 1B68 ldr r3, [r3] 2314 .LBE277: 2315 .LBE276: 615:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 2316 .loc 1 615 15 discriminator 1 2317 0dc8 B3FA83F3 clz r3, r3 615:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 2318 .loc 1 615 15 is_stmt 0 discriminator 2 2319 0dcc DBB2 uxtb r3, r3 2320 0dce 3F2B cmp r3, #63 ARM GAS /tmp/ccSuWkwR.s page 72 2321 0dd0 02D8 bhi .L136 615:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 2322 .loc 1 615 15 discriminator 1 2323 0dd2 7E4B ldr r3, .L162 2324 0dd4 1B68 ldr r3, [r3] 2325 0dd6 27E0 b .L137 2326 .L136: 2327 0dd8 07F50073 add r3, r7, #512 2328 0ddc A3F5DC73 sub r3, r3, #440 2329 0de0 4FF00072 mov r2, #33554432 2330 0de4 1A60 str r2, [r3] 2331 .LBB278: 2332 .LBB279: 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 2333 .loc 2 988 4 is_stmt 1 2334 0de6 07F50073 add r3, r7, #512 2335 0dea A3F5DC73 sub r3, r3, #440 2336 0dee 1B68 ldr r3, [r3] 2337 .syntax unified 2338 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 2339 0df0 93FAA3F2 rbit r2, r3 2340 @ 0 "" 2 2341 .thumb 2342 .syntax unified 2343 0df4 07F50073 add r3, r7, #512 2344 0df8 A3F5DE73 sub r3, r3, #444 2345 0dfc 1A60 str r2, [r3] 2346 0dfe 07F50073 add r3, r7, #512 2347 0e02 A3F5E073 sub r3, r3, #448 2348 0e06 4FF00072 mov r2, #33554432 2349 0e0a 1A60 str r2, [r3] 2350 .LBE279: 2351 .LBE278: 2352 .LBB280: 2353 .LBB281: 2354 0e0c 07F50073 add r3, r7, #512 2355 0e10 A3F5E073 sub r3, r3, #448 2356 0e14 1B68 ldr r3, [r3] 2357 .syntax unified 2358 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 2359 0e16 93FAA3F2 rbit r2, r3 2360 @ 0 "" 2 2361 .thumb 2362 .syntax unified 2363 0e1a 07F50073 add r3, r7, #512 2364 0e1e A3F5E273 sub r3, r3, #452 2365 0e22 1A60 str r2, [r3] 2366 .LBE281: 2367 .LBE280: 615:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 2368 .loc 1 615 15 discriminator 8 2369 0e24 694B ldr r3, .L162 2370 0e26 5B6A ldr r3, [r3, #36] 2371 .L137: 2372 0e28 07F50072 add r2, r7, #512 2373 0e2c A2F5E472 sub r2, r2, #456 2374 0e30 4FF00071 mov r1, #33554432 ARM GAS /tmp/ccSuWkwR.s page 73 2375 0e34 1160 str r1, [r2] 2376 .LBB282: 2377 .LBB283: 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 2378 .loc 2 988 4 2379 0e36 07F50072 add r2, r7, #512 2380 0e3a A2F5E472 sub r2, r2, #456 2381 0e3e 1268 ldr r2, [r2] 2382 .syntax unified 2383 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 2384 0e40 92FAA2F1 rbit r1, r2 2385 @ 0 "" 2 2386 .thumb 2387 .syntax unified 2388 0e44 07F50072 add r2, r7, #512 2389 0e48 A2F5E672 sub r2, r2, #460 2390 0e4c 1160 str r1, [r2] 2391 .loc 2 1001 10 2392 0e4e 07F50072 add r2, r7, #512 2393 0e52 A2F5E672 sub r2, r2, #460 2394 0e56 1268 ldr r2, [r2] 2395 .LBE283: 2396 .LBE282: 615:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 2397 .loc 1 615 15 discriminator 1 2398 0e58 B2FA82F2 clz r2, r2 615:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 2399 .loc 1 615 15 is_stmt 0 discriminator 2 2400 0e5c D2B2 uxtb r2, r2 2401 0e5e 42F02002 orr r2, r2, #32 2402 0e62 D2B2 uxtb r2, r2 2403 0e64 02F01F02 and r2, r2, #31 2404 0e68 0121 movs r1, #1 2405 0e6a 01FA02F2 lsl r2, r1, r2 2406 0e6e 1340 ands r3, r3, r2 615:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 2407 .loc 1 615 52 is_stmt 1 discriminator 2 2408 0e70 002B cmp r3, #0 2409 0e72 87D0 beq .L141 2410 0e74 CAE0 b .L121 2411 .L123: 2412 0e76 07F50073 add r3, r7, #512 2413 0e7a A3F5E873 sub r3, r3, #464 2414 0e7e 4FF08072 mov r2, #16777216 2415 0e82 1A60 str r2, [r3] 2416 .LBB284: 2417 .LBB285: 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 2418 .loc 2 988 4 2419 0e84 07F50073 add r3, r7, #512 2420 0e88 A3F5E873 sub r3, r3, #464 2421 0e8c 1B68 ldr r3, [r3] 2422 .syntax unified 2423 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 2424 0e8e 93FAA3F2 rbit r2, r3 2425 @ 0 "" 2 2426 .thumb ARM GAS /tmp/ccSuWkwR.s page 74 2427 .syntax unified 2428 0e92 07F50073 add r3, r7, #512 2429 0e96 A3F5EA73 sub r3, r3, #468 2430 0e9a 1A60 str r2, [r3] 2431 .loc 2 1001 10 2432 0e9c 07F50073 add r3, r7, #512 2433 0ea0 A3F5EA73 sub r3, r3, #468 2434 0ea4 1B68 ldr r3, [r3] 2435 .LBE285: 2436 .LBE284: 620:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 621:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 622:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 623:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** else 624:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 625:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Disable the main PLL. */ 626:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** __HAL_RCC_PLL_DISABLE(); 2437 .loc 1 626 9 discriminator 1 2438 0ea6 B3FA83F3 clz r3, r3 2439 .loc 1 626 9 is_stmt 0 discriminator 2 2440 0eaa DBB2 uxtb r3, r3 2441 0eac 03F18453 add r3, r3, #276824064 2442 0eb0 03F58413 add r3, r3, #1081344 2443 0eb4 9B00 lsls r3, r3, #2 2444 0eb6 1A46 mov r2, r3 2445 0eb8 0023 movs r3, #0 2446 0eba 1360 str r3, [r2] 627:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 628:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get Start Tick */ 629:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** tickstart = HAL_GetTick(); 2447 .loc 1 629 21 is_stmt 1 2448 0ebc FFF7FEFF bl HAL_GetTick 2449 0ec0 C7F8F801 str r0, [r7, #504] 630:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 631:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Wait till PLL is disabled */ 632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 2450 .loc 1 632 14 2451 0ec4 09E0 b .L143 2452 .L150: 633:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 634:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 2453 .loc 1 634 15 2454 0ec6 FFF7FEFF bl HAL_GetTick 2455 0eca 0246 mov r2, r0 2456 .loc 1 634 29 discriminator 1 2457 0ecc D7F8F831 ldr r3, [r7, #504] 2458 0ed0 D31A subs r3, r2, r3 2459 .loc 1 634 13 discriminator 1 2460 0ed2 022B cmp r3, #2 2461 0ed4 01D9 bls .L143 635:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 636:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_TIMEOUT; 2462 .loc 1 636 20 2463 0ed6 0323 movs r3, #3 2464 0ed8 99E0 b .L15 2465 .L143: 2466 0eda 07F50073 add r3, r7, #512 ARM GAS /tmp/ccSuWkwR.s page 75 2467 0ede A3F5EC73 sub r3, r3, #472 2468 0ee2 4FF00072 mov r2, #33554432 2469 0ee6 1A60 str r2, [r3] 2470 .LBB286: 2471 .LBB287: 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 2472 .loc 2 988 4 2473 0ee8 07F50073 add r3, r7, #512 2474 0eec A3F5EC73 sub r3, r3, #472 2475 0ef0 1B68 ldr r3, [r3] 2476 .syntax unified 2477 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 2478 0ef2 93FAA3F2 rbit r2, r3 2479 @ 0 "" 2 2480 .thumb 2481 .syntax unified 2482 0ef6 07F50073 add r3, r7, #512 2483 0efa A3F5EE73 sub r3, r3, #476 2484 0efe 1A60 str r2, [r3] 2485 .loc 2 1001 10 2486 0f00 07F50073 add r3, r7, #512 2487 0f04 A3F5EE73 sub r3, r3, #476 2488 0f08 1B68 ldr r3, [r3] 2489 .LBE287: 2490 .LBE286: 632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 2491 .loc 1 632 15 discriminator 1 2492 0f0a B3FA83F3 clz r3, r3 632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 2493 .loc 1 632 15 is_stmt 0 discriminator 2 2494 0f0e DBB2 uxtb r3, r3 2495 0f10 3F2B cmp r3, #63 2496 0f12 02D8 bhi .L145 632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 2497 .loc 1 632 15 discriminator 1 2498 0f14 2D4B ldr r3, .L162 2499 0f16 1B68 ldr r3, [r3] 2500 0f18 27E0 b .L146 2501 .L145: 2502 0f1a 07F50073 add r3, r7, #512 2503 0f1e A3F5F073 sub r3, r3, #480 2504 0f22 4FF00072 mov r2, #33554432 2505 0f26 1A60 str r2, [r3] 2506 .LBB288: 2507 .LBB289: 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 2508 .loc 2 988 4 is_stmt 1 2509 0f28 07F50073 add r3, r7, #512 2510 0f2c A3F5F073 sub r3, r3, #480 2511 0f30 1B68 ldr r3, [r3] 2512 .syntax unified 2513 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 2514 0f32 93FAA3F2 rbit r2, r3 2515 @ 0 "" 2 2516 .thumb 2517 .syntax unified 2518 0f36 07F50073 add r3, r7, #512 ARM GAS /tmp/ccSuWkwR.s page 76 2519 0f3a A3F5F273 sub r3, r3, #484 2520 0f3e 1A60 str r2, [r3] 2521 0f40 07F50073 add r3, r7, #512 2522 0f44 A3F5F473 sub r3, r3, #488 2523 0f48 4FF00072 mov r2, #33554432 2524 0f4c 1A60 str r2, [r3] 2525 .LBE289: 2526 .LBE288: 2527 .LBB290: 2528 .LBB291: 2529 0f4e 07F50073 add r3, r7, #512 2530 0f52 A3F5F473 sub r3, r3, #488 2531 0f56 1B68 ldr r3, [r3] 2532 .syntax unified 2533 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 2534 0f58 93FAA3F2 rbit r2, r3 2535 @ 0 "" 2 2536 .thumb 2537 .syntax unified 2538 0f5c 07F50073 add r3, r7, #512 2539 0f60 A3F5F673 sub r3, r3, #492 2540 0f64 1A60 str r2, [r3] 2541 .LBE291: 2542 .LBE290: 632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 2543 .loc 1 632 15 discriminator 8 2544 0f66 194B ldr r3, .L162 2545 0f68 5B6A ldr r3, [r3, #36] 2546 .L146: 2547 0f6a 07F50072 add r2, r7, #512 2548 0f6e A2F5F872 sub r2, r2, #496 2549 0f72 4FF00071 mov r1, #33554432 2550 0f76 1160 str r1, [r2] 2551 .LBB292: 2552 .LBB293: 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 2553 .loc 2 988 4 2554 0f78 07F50072 add r2, r7, #512 2555 0f7c A2F5F872 sub r2, r2, #496 2556 0f80 1268 ldr r2, [r2] 2557 .syntax unified 2558 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 2559 0f82 92FAA2F1 rbit r1, r2 2560 @ 0 "" 2 2561 .thumb 2562 .syntax unified 2563 0f86 07F50072 add r2, r7, #512 2564 0f8a A2F5FA72 sub r2, r2, #500 2565 0f8e 1160 str r1, [r2] 2566 .loc 2 1001 10 2567 0f90 07F50072 add r2, r7, #512 2568 0f94 A2F5FA72 sub r2, r2, #500 2569 0f98 1268 ldr r2, [r2] 2570 .LBE293: 2571 .LBE292: 632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 2572 .loc 1 632 15 discriminator 1 ARM GAS /tmp/ccSuWkwR.s page 77 2573 0f9a B2FA82F2 clz r2, r2 632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 2574 .loc 1 632 15 is_stmt 0 discriminator 2 2575 0f9e D2B2 uxtb r2, r2 2576 0fa0 42F02002 orr r2, r2, #32 2577 0fa4 D2B2 uxtb r2, r2 2578 0fa6 02F01F02 and r2, r2, #31 2579 0faa 0121 movs r1, #1 2580 0fac 01FA02F2 lsl r2, r1, r2 2581 0fb0 1340 ands r3, r3, r2 632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 2582 .loc 1 632 52 is_stmt 1 discriminator 2 2583 0fb2 002B cmp r3, #0 2584 0fb4 87D1 bne .L150 2585 0fb6 29E0 b .L121 2586 .L122: 637:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 638:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 639:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 640:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 641:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** else 642:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 643:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check if there is a request to disable the PLL used as System clock source */ 644:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) 2587 .loc 1 644 33 2588 0fb8 07F50073 add r3, r7, #512 2589 0fbc A3F5FE73 sub r3, r3, #508 2590 0fc0 1B68 ldr r3, [r3] 2591 0fc2 DB69 ldr r3, [r3, #28] 2592 .loc 1 644 9 2593 0fc4 012B cmp r3, #1 2594 0fc6 03D1 bne .L151 645:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 646:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_ERROR; 2595 .loc 1 646 16 2596 0fc8 0123 movs r3, #1 2597 0fca 20E0 b .L15 2598 .L163: 2599 .align 2 2600 .L162: 2601 0fcc 00100240 .word 1073876992 2602 .L151: 647:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 648:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** else 649:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 650:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Do not return HAL_ERROR if request repeats the current configuration */ 651:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** pll_config = RCC->CFGR; 2603 .loc 1 651 25 2604 0fd0 114B ldr r3, .L164 2605 .loc 1 651 20 2606 0fd2 5B68 ldr r3, [r3, #4] 2607 0fd4 C7F8F431 str r3, [r7, #500] 652:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #if defined(RCC_CFGR_PLLSRC_HSI_PREDIV) 653:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** pll_config2 = RCC->CFGR2; 654:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 655:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) || 656:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV)) ARM GAS /tmp/ccSuWkwR.s page 78 657:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #else 658:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 2608 .loc 1 658 13 2609 0fd8 D7F8F431 ldr r3, [r7, #500] 2610 0fdc 03F48032 and r2, r3, #65536 2611 .loc 1 658 78 2612 0fe0 07F50073 add r3, r7, #512 2613 0fe4 A3F5FE73 sub r3, r3, #508 2614 0fe8 1B68 ldr r3, [r3] 2615 0fea 1B6A ldr r3, [r3, #32] 2616 .loc 1 658 11 2617 0fec 9A42 cmp r2, r3 2618 0fee 0BD1 bne .L152 659:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL)) 2619 .loc 1 659 13 2620 0ff0 D7F8F431 ldr r3, [r7, #500] 2621 0ff4 03F47012 and r2, r3, #3932160 2622 .loc 1 659 78 2623 0ff8 07F50073 add r3, r7, #512 2624 0ffc A3F5FE73 sub r3, r3, #508 2625 1000 1B68 ldr r3, [r3] 2626 1002 5B6A ldr r3, [r3, #36] 658:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL)) 2627 .loc 1 658 90 discriminator 1 2628 1004 9A42 cmp r2, r3 2629 1006 01D0 beq .L121 2630 .L152: 660:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #endif 661:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 662:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_ERROR; 2631 .loc 1 662 18 2632 1008 0123 movs r3, #1 2633 100a 00E0 b .L15 2634 .L121: 663:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 664:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 665:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 666:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 667:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 668:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_OK; 2635 .loc 1 668 10 2636 100c 0023 movs r3, #0 2637 .L15: 669:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 2638 .loc 1 669 1 2639 100e 1846 mov r0, r3 2640 1010 07F50077 add r7, r7, #512 2641 .cfi_def_cfa_offset 8 2642 1014 BD46 mov sp, r7 2643 .cfi_def_cfa_register 13 2644 @ sp needed 2645 1016 80BD pop {r7, pc} 2646 .L165: 2647 .align 2 2648 .L164: 2649 1018 00100240 .word 1073876992 2650 .cfi_endproc ARM GAS /tmp/ccSuWkwR.s page 79 2651 .LFE131: 2653 .section .text.HAL_RCC_ClockConfig,"ax",%progbits 2654 .align 1 2655 .global HAL_RCC_ClockConfig 2656 .syntax unified 2657 .thumb 2658 .thumb_func 2660 HAL_RCC_ClockConfig: 2661 .LFB132: 670:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 671:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** 672:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @brief Initializes the CPU, AHB and APB buses clocks according to the specified 673:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * parameters in the RCC_ClkInitStruct. 674:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that 675:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * contains the configuration information for the RCC peripheral. 676:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @param FLatency FLASH Latency 677:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * The value of this parameter depend on device used within the same series 678:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency 679:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function 680:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * 681:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note The HSI is used (enabled by hardware) as system clock source after 682:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * start-up from Reset, wake-up from STOP and STANDBY mode, or in case 683:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * of failure of the HSE used directly or indirectly as system clock 684:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * (if the Clock Security System CSS is enabled). 685:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * 686:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note A switch from one clock source to another occurs only if the target 687:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * clock source is ready (clock stable after start-up delay or PLL locked). 688:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * If a clock source which is not yet ready is selected, the switch will 689:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * occur when the clock source will be ready. 690:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is 691:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * currently used as system clock source. 692:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @retval HAL status 693:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ 694:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) 695:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 2662 .loc 1 695 1 2663 .cfi_startproc 2664 @ args = 0, pretend = 0, frame = 120 2665 @ frame_needed = 1, uses_anonymous_args = 0 2666 0000 80B5 push {r7, lr} 2667 .cfi_def_cfa_offset 8 2668 .cfi_offset 7, -8 2669 .cfi_offset 14, -4 2670 0002 9EB0 sub sp, sp, #120 2671 .cfi_def_cfa_offset 128 2672 0004 00AF add r7, sp, #0 2673 .cfi_def_cfa_register 7 2674 0006 7860 str r0, [r7, #4] 2675 0008 3960 str r1, [r7] 696:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** uint32_t tickstart = 0U; 2676 .loc 1 696 12 2677 000a 0023 movs r3, #0 2678 000c 7B67 str r3, [r7, #116] 697:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 698:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check Null pointer */ 699:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(RCC_ClkInitStruct == NULL) 2679 .loc 1 699 5 ARM GAS /tmp/ccSuWkwR.s page 80 2680 000e 7B68 ldr r3, [r7, #4] 2681 0010 002B cmp r3, #0 2682 0012 01D1 bne .L167 700:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 701:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_ERROR; 2683 .loc 1 701 12 2684 0014 0123 movs r3, #1 2685 0016 54E1 b .L168 2686 .L167: 702:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 703:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 704:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check the parameters */ 705:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType)); 706:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** assert_param(IS_FLASH_LATENCY(FLatency)); 707:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 708:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* To correctly read data from FLASH memory, the number of wait states (LATENCY) 709:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** must be correctly programmed according to the frequency of the CPU clock 710:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (HCLK) of the device. */ 711:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 712:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Increasing the number of wait states because of higher CPU frequency */ 713:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(FLatency > __HAL_FLASH_GET_LATENCY()) 2687 .loc 1 713 17 2688 0018 894B ldr r3, .L199 2689 001a 1B68 ldr r3, [r3] 2690 001c 03F00703 and r3, r3, #7 2691 .loc 1 713 5 2692 0020 3A68 ldr r2, [r7] 2693 0022 9A42 cmp r2, r3 2694 0024 10D9 bls .L169 714:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 715:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ 716:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** __HAL_FLASH_SET_LATENCY(FLatency); 2695 .loc 1 716 5 2696 0026 864B ldr r3, .L199 2697 0028 1B68 ldr r3, [r3] 2698 002a 23F00702 bic r2, r3, #7 2699 002e 8449 ldr r1, .L199 2700 0030 3B68 ldr r3, [r7] 2701 0032 1343 orrs r3, r3, r2 2702 0034 0B60 str r3, [r1] 717:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 718:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check that the new number of wait states is taken into account to access the Flash 719:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** memory by reading the FLASH_ACR register */ 720:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(__HAL_FLASH_GET_LATENCY() != FLatency) 2703 .loc 1 720 8 2704 0036 824B ldr r3, .L199 2705 0038 1B68 ldr r3, [r3] 2706 003a 03F00703 and r3, r3, #7 2707 .loc 1 720 7 2708 003e 3A68 ldr r2, [r7] 2709 0040 9A42 cmp r2, r3 2710 0042 01D0 beq .L169 721:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 722:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_ERROR; 2711 .loc 1 722 14 2712 0044 0123 movs r3, #1 2713 0046 3CE1 b .L168 ARM GAS /tmp/ccSuWkwR.s page 81 2714 .L169: 723:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 724:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 725:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 726:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /*-------------------------- HCLK Configuration --------------------------*/ 727:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 2715 .loc 1 727 25 2716 0048 7B68 ldr r3, [r7, #4] 2717 004a 1B68 ldr r3, [r3] 2718 .loc 1 727 38 2719 004c 03F00203 and r3, r3, #2 2720 .loc 1 727 5 2721 0050 002B cmp r3, #0 2722 0052 08D0 beq .L170 728:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 729:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); 730:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 2723 .loc 1 730 5 2724 0054 7B4B ldr r3, .L199+4 2725 0056 5B68 ldr r3, [r3, #4] 2726 0058 23F0F002 bic r2, r3, #240 2727 005c 7B68 ldr r3, [r7, #4] 2728 005e 9B68 ldr r3, [r3, #8] 2729 0060 7849 ldr r1, .L199+4 2730 0062 1343 orrs r3, r3, r2 2731 0064 4B60 str r3, [r1, #4] 2732 .L170: 731:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 732:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 733:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /*------------------------- SYSCLK Configuration ---------------------------*/ 734:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 2733 .loc 1 734 25 2734 0066 7B68 ldr r3, [r7, #4] 2735 0068 1B68 ldr r3, [r3] 2736 .loc 1 734 38 2737 006a 03F00103 and r3, r3, #1 2738 .loc 1 734 5 2739 006e 002B cmp r3, #0 2740 0070 00F0CD80 beq .L171 735:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 736:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); 737:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 738:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* HSE is selected as System Clock Source */ 739:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 2741 .loc 1 739 25 2742 0074 7B68 ldr r3, [r7, #4] 2743 0076 5B68 ldr r3, [r3, #4] 2744 .loc 1 739 7 2745 0078 012B cmp r3, #1 2746 007a 37D1 bne .L172 2747 007c 4FF40033 mov r3, #131072 2748 0080 FB66 str r3, [r7, #108] 2749 .LBB294: 2750 .LBB295: 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 2751 .loc 2 988 4 2752 0082 FB6E ldr r3, [r7, #108] ARM GAS /tmp/ccSuWkwR.s page 82 2753 .syntax unified 2754 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 2755 0084 93FAA3F3 rbit r3, r3 2756 @ 0 "" 2 2757 .thumb 2758 .syntax unified 2759 0088 3B67 str r3, [r7, #112] 2760 .loc 2 1001 10 2761 008a 3B6F ldr r3, [r7, #112] 2762 .LBE295: 2763 .LBE294: 740:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 741:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check the HSE ready flag */ 742:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 2764 .loc 1 742 10 discriminator 1 2765 008c B3FA83F3 clz r3, r3 2766 .loc 1 742 10 is_stmt 0 discriminator 2 2767 0090 DBB2 uxtb r3, r3 2768 0092 3F2B cmp r3, #63 2769 0094 02D8 bhi .L174 2770 .loc 1 742 10 discriminator 1 2771 0096 6B4B ldr r3, .L199+4 2772 0098 1B68 ldr r3, [r3] 2773 009a 0FE0 b .L175 2774 .L174: 2775 009c 4FF40033 mov r3, #131072 2776 00a0 BB66 str r3, [r7, #104] 2777 .LBB296: 2778 .LBB297: 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 2779 .loc 2 988 4 is_stmt 1 2780 00a2 BB6E ldr r3, [r7, #104] 2781 .syntax unified 2782 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 2783 00a4 93FAA3F3 rbit r3, r3 2784 @ 0 "" 2 2785 .thumb 2786 .syntax unified 2787 00a8 7B66 str r3, [r7, #100] 2788 00aa 4FF40033 mov r3, #131072 2789 00ae 3B66 str r3, [r7, #96] 2790 .LBE297: 2791 .LBE296: 2792 .LBB298: 2793 .LBB299: 2794 00b0 3B6E ldr r3, [r7, #96] 2795 .syntax unified 2796 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 2797 00b2 93FAA3F3 rbit r3, r3 2798 @ 0 "" 2 2799 .thumb 2800 .syntax unified 2801 00b6 FB65 str r3, [r7, #92] 2802 .LBE299: 2803 .LBE298: 2804 .loc 1 742 10 discriminator 8 2805 00b8 624B ldr r3, .L199+4 ARM GAS /tmp/ccSuWkwR.s page 83 2806 00ba 5B6A ldr r3, [r3, #36] 2807 .L175: 2808 00bc 4FF40032 mov r2, #131072 2809 00c0 BA65 str r2, [r7, #88] 2810 .LBB300: 2811 .LBB301: 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 2812 .loc 2 988 4 2813 00c2 BA6D ldr r2, [r7, #88] 2814 .syntax unified 2815 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 2816 00c4 92FAA2F2 rbit r2, r2 2817 @ 0 "" 2 2818 .thumb 2819 .syntax unified 2820 00c8 7A65 str r2, [r7, #84] 2821 .loc 2 1001 10 2822 00ca 7A6D ldr r2, [r7, #84] 2823 .LBE301: 2824 .LBE300: 2825 .loc 1 742 10 discriminator 1 2826 00cc B2FA82F2 clz r2, r2 2827 .loc 1 742 10 is_stmt 0 discriminator 2 2828 00d0 D2B2 uxtb r2, r2 2829 00d2 42F02002 orr r2, r2, #32 2830 00d6 D2B2 uxtb r2, r2 2831 00d8 02F01F02 and r2, r2, #31 2832 00dc 0121 movs r1, #1 2833 00de 01FA02F2 lsl r2, r1, r2 2834 00e2 1340 ands r3, r3, r2 2835 .loc 1 742 9 is_stmt 1 discriminator 2 2836 00e4 002B cmp r3, #0 2837 00e6 71D1 bne .L179 743:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 744:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_ERROR; 2838 .loc 1 744 16 2839 00e8 0123 movs r3, #1 2840 00ea EAE0 b .L168 2841 .L172: 745:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 746:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 747:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* PLL is selected as System Clock Source */ 748:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 2842 .loc 1 748 30 2843 00ec 7B68 ldr r3, [r7, #4] 2844 00ee 5B68 ldr r3, [r3, #4] 2845 .loc 1 748 12 2846 00f0 022B cmp r3, #2 2847 00f2 37D1 bne .L180 2848 00f4 4FF00073 mov r3, #33554432 2849 00f8 3B65 str r3, [r7, #80] 2850 .LBB302: 2851 .LBB303: 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 2852 .loc 2 988 4 2853 00fa 3B6D ldr r3, [r7, #80] 2854 .syntax unified ARM GAS /tmp/ccSuWkwR.s page 84 2855 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 2856 00fc 93FAA3F3 rbit r3, r3 2857 @ 0 "" 2 2858 .thumb 2859 .syntax unified 2860 0100 FB64 str r3, [r7, #76] 2861 .loc 2 1001 10 2862 0102 FB6C ldr r3, [r7, #76] 2863 .LBE303: 2864 .LBE302: 749:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 750:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check the PLL ready flag */ 751:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 2865 .loc 1 751 10 discriminator 1 2866 0104 B3FA83F3 clz r3, r3 2867 .loc 1 751 10 is_stmt 0 discriminator 2 2868 0108 DBB2 uxtb r3, r3 2869 010a 3F2B cmp r3, #63 2870 010c 02D8 bhi .L182 2871 .loc 1 751 10 discriminator 1 2872 010e 4D4B ldr r3, .L199+4 2873 0110 1B68 ldr r3, [r3] 2874 0112 0FE0 b .L183 2875 .L182: 2876 0114 4FF00073 mov r3, #33554432 2877 0118 BB64 str r3, [r7, #72] 2878 .LBB304: 2879 .LBB305: 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 2880 .loc 2 988 4 is_stmt 1 2881 011a BB6C ldr r3, [r7, #72] 2882 .syntax unified 2883 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 2884 011c 93FAA3F3 rbit r3, r3 2885 @ 0 "" 2 2886 .thumb 2887 .syntax unified 2888 0120 7B64 str r3, [r7, #68] 2889 0122 4FF00073 mov r3, #33554432 2890 0126 3B64 str r3, [r7, #64] 2891 .LBE305: 2892 .LBE304: 2893 .LBB306: 2894 .LBB307: 2895 0128 3B6C ldr r3, [r7, #64] 2896 .syntax unified 2897 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 2898 012a 93FAA3F3 rbit r3, r3 2899 @ 0 "" 2 2900 .thumb 2901 .syntax unified 2902 012e FB63 str r3, [r7, #60] 2903 .LBE307: 2904 .LBE306: 2905 .loc 1 751 10 discriminator 8 2906 0130 444B ldr r3, .L199+4 2907 0132 5B6A ldr r3, [r3, #36] ARM GAS /tmp/ccSuWkwR.s page 85 2908 .L183: 2909 0134 4FF00072 mov r2, #33554432 2910 0138 BA63 str r2, [r7, #56] 2911 .LBB308: 2912 .LBB309: 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 2913 .loc 2 988 4 2914 013a BA6B ldr r2, [r7, #56] 2915 .syntax unified 2916 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 2917 013c 92FAA2F2 rbit r2, r2 2918 @ 0 "" 2 2919 .thumb 2920 .syntax unified 2921 0140 7A63 str r2, [r7, #52] 2922 .loc 2 1001 10 2923 0142 7A6B ldr r2, [r7, #52] 2924 .LBE309: 2925 .LBE308: 2926 .loc 1 751 10 discriminator 1 2927 0144 B2FA82F2 clz r2, r2 2928 .loc 1 751 10 is_stmt 0 discriminator 2 2929 0148 D2B2 uxtb r2, r2 2930 014a 42F02002 orr r2, r2, #32 2931 014e D2B2 uxtb r2, r2 2932 0150 02F01F02 and r2, r2, #31 2933 0154 0121 movs r1, #1 2934 0156 01FA02F2 lsl r2, r1, r2 2935 015a 1340 ands r3, r3, r2 2936 .loc 1 751 9 is_stmt 1 discriminator 2 2937 015c 002B cmp r3, #0 2938 015e 35D1 bne .L179 752:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 753:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_ERROR; 2939 .loc 1 753 16 2940 0160 0123 movs r3, #1 2941 0162 AEE0 b .L168 2942 .L180: 2943 0164 0223 movs r3, #2 2944 0166 3B63 str r3, [r7, #48] 2945 .LBB310: 2946 .LBB311: 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 2947 .loc 2 988 4 2948 0168 3B6B ldr r3, [r7, #48] 2949 .syntax unified 2950 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 2951 016a 93FAA3F3 rbit r3, r3 2952 @ 0 "" 2 2953 .thumb 2954 .syntax unified 2955 016e FB62 str r3, [r7, #44] 2956 .loc 2 1001 10 2957 0170 FB6A ldr r3, [r7, #44] 2958 .LBE311: 2959 .LBE310: 754:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } ARM GAS /tmp/ccSuWkwR.s page 86 755:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 756:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* HSI is selected as System Clock Source */ 757:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** else 758:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 759:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check the HSI ready flag */ 760:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 2960 .loc 1 760 10 discriminator 1 2961 0172 B3FA83F3 clz r3, r3 2962 .loc 1 760 10 is_stmt 0 discriminator 2 2963 0176 DBB2 uxtb r3, r3 2964 0178 3F2B cmp r3, #63 2965 017a 02D8 bhi .L188 2966 .loc 1 760 10 discriminator 1 2967 017c 314B ldr r3, .L199+4 2968 017e 1B68 ldr r3, [r3] 2969 0180 0DE0 b .L189 2970 .L188: 2971 0182 0223 movs r3, #2 2972 0184 BB62 str r3, [r7, #40] 2973 .LBB312: 2974 .LBB313: 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 2975 .loc 2 988 4 is_stmt 1 2976 0186 BB6A ldr r3, [r7, #40] 2977 .syntax unified 2978 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 2979 0188 93FAA3F3 rbit r3, r3 2980 @ 0 "" 2 2981 .thumb 2982 .syntax unified 2983 018c 7B62 str r3, [r7, #36] 2984 018e 0223 movs r3, #2 2985 0190 3B62 str r3, [r7, #32] 2986 .LBE313: 2987 .LBE312: 2988 .LBB314: 2989 .LBB315: 2990 0192 3B6A ldr r3, [r7, #32] 2991 .syntax unified 2992 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 2993 0194 93FAA3F3 rbit r3, r3 2994 @ 0 "" 2 2995 .thumb 2996 .syntax unified 2997 0198 FB61 str r3, [r7, #28] 2998 .LBE315: 2999 .LBE314: 3000 .loc 1 760 10 discriminator 8 3001 019a 2A4B ldr r3, .L199+4 3002 019c 5B6A ldr r3, [r3, #36] 3003 .L189: 3004 019e 0222 movs r2, #2 3005 01a0 BA61 str r2, [r7, #24] 3006 .LBB316: 3007 .LBB317: 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 3008 .loc 2 988 4 ARM GAS /tmp/ccSuWkwR.s page 87 3009 01a2 BA69 ldr r2, [r7, #24] 3010 .syntax unified 3011 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 3012 01a4 92FAA2F2 rbit r2, r2 3013 @ 0 "" 2 3014 .thumb 3015 .syntax unified 3016 01a8 7A61 str r2, [r7, #20] 3017 .loc 2 1001 10 3018 01aa 7A69 ldr r2, [r7, #20] 3019 .LBE317: 3020 .LBE316: 3021 .loc 1 760 10 discriminator 1 3022 01ac B2FA82F2 clz r2, r2 3023 .loc 1 760 10 is_stmt 0 discriminator 2 3024 01b0 D2B2 uxtb r2, r2 3025 01b2 42F02002 orr r2, r2, #32 3026 01b6 D2B2 uxtb r2, r2 3027 01b8 02F01F02 and r2, r2, #31 3028 01bc 0121 movs r1, #1 3029 01be 01FA02F2 lsl r2, r1, r2 3030 01c2 1340 ands r3, r3, r2 3031 .loc 1 760 9 is_stmt 1 discriminator 2 3032 01c4 002B cmp r3, #0 3033 01c6 01D1 bne .L179 761:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 762:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_ERROR; 3034 .loc 1 762 16 3035 01c8 0123 movs r3, #1 3036 01ca 7AE0 b .L168 3037 .L179: 763:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 764:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 765:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 766:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); 3038 .loc 1 766 5 3039 01cc 1D4B ldr r3, .L199+4 3040 01ce 5B68 ldr r3, [r3, #4] 3041 01d0 23F00302 bic r2, r3, #3 3042 01d4 7B68 ldr r3, [r7, #4] 3043 01d6 5B68 ldr r3, [r3, #4] 3044 01d8 1A49 ldr r1, .L199+4 3045 01da 1343 orrs r3, r3, r2 3046 01dc 4B60 str r3, [r1, #4] 767:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 768:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get Start Tick */ 769:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** tickstart = HAL_GetTick(); 3047 .loc 1 769 17 3048 01de FFF7FEFF bl HAL_GetTick 3049 01e2 7867 str r0, [r7, #116] 770:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 771:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 3050 .loc 1 771 11 3051 01e4 0AE0 b .L193 3052 .L194: 772:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 773:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) ARM GAS /tmp/ccSuWkwR.s page 88 3053 .loc 1 773 12 3054 01e6 FFF7FEFF bl HAL_GetTick 3055 01ea 0246 mov r2, r0 3056 .loc 1 773 26 discriminator 1 3057 01ec 7B6F ldr r3, [r7, #116] 3058 01ee D31A subs r3, r2, r3 3059 .loc 1 773 10 discriminator 1 3060 01f0 41F28832 movw r2, #5000 3061 01f4 9342 cmp r3, r2 3062 01f6 01D9 bls .L193 774:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 775:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_TIMEOUT; 3063 .loc 1 775 16 3064 01f8 0323 movs r3, #3 3065 01fa 62E0 b .L168 3066 .L193: 771:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 3067 .loc 1 771 12 3068 01fc 114B ldr r3, .L199+4 3069 01fe 5B68 ldr r3, [r3, #4] 3070 0200 03F00C02 and r2, r3, #12 771:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 3071 .loc 1 771 63 3072 0204 7B68 ldr r3, [r7, #4] 3073 0206 5B68 ldr r3, [r3, #4] 771:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 3074 .loc 1 771 78 3075 0208 9B00 lsls r3, r3, #2 771:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 3076 .loc 1 771 42 3077 020a 9A42 cmp r2, r3 3078 020c EBD1 bne .L194 3079 .L171: 776:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 777:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 778:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 779:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Decreasing the number of wait states because of lower CPU frequency */ 780:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(FLatency < __HAL_FLASH_GET_LATENCY()) 3080 .loc 1 780 17 3081 020e 0C4B ldr r3, .L199 3082 0210 1B68 ldr r3, [r3] 3083 0212 03F00703 and r3, r3, #7 3084 .loc 1 780 5 3085 0216 3A68 ldr r2, [r7] 3086 0218 9A42 cmp r2, r3 3087 021a 15D2 bcs .L195 781:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 782:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ 783:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** __HAL_FLASH_SET_LATENCY(FLatency); 3088 .loc 1 783 5 3089 021c 084B ldr r3, .L199 3090 021e 1B68 ldr r3, [r3] 3091 0220 23F00702 bic r2, r3, #7 3092 0224 0649 ldr r1, .L199 3093 0226 3B68 ldr r3, [r7] 3094 0228 1343 orrs r3, r3, r2 3095 022a 0B60 str r3, [r1] ARM GAS /tmp/ccSuWkwR.s page 89 784:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 785:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check that the new number of wait states is taken into account to access the Flash 786:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** memory by reading the FLASH_ACR register */ 787:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(__HAL_FLASH_GET_LATENCY() != FLatency) 3096 .loc 1 787 8 3097 022c 044B ldr r3, .L199 3098 022e 1B68 ldr r3, [r3] 3099 0230 03F00703 and r3, r3, #7 3100 .loc 1 787 7 3101 0234 3A68 ldr r2, [r7] 3102 0236 9A42 cmp r2, r3 3103 0238 06D0 beq .L195 788:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 789:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_ERROR; 3104 .loc 1 789 14 3105 023a 0123 movs r3, #1 3106 023c 41E0 b .L168 3107 .L200: 3108 023e 00BF .align 2 3109 .L199: 3110 0240 00200240 .word 1073881088 3111 0244 00100240 .word 1073876992 3112 .L195: 790:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 791:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 792:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 793:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /*-------------------------- PCLK1 Configuration ---------------------------*/ 794:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 3113 .loc 1 794 25 3114 0248 7B68 ldr r3, [r7, #4] 3115 024a 1B68 ldr r3, [r3] 3116 .loc 1 794 38 3117 024c 03F00403 and r3, r3, #4 3118 .loc 1 794 5 3119 0250 002B cmp r3, #0 3120 0252 08D0 beq .L196 795:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 796:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); 797:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); 3121 .loc 1 797 5 3122 0254 1D4B ldr r3, .L201 3123 0256 5B68 ldr r3, [r3, #4] 3124 0258 23F4E062 bic r2, r3, #1792 3125 025c 7B68 ldr r3, [r7, #4] 3126 025e DB68 ldr r3, [r3, #12] 3127 0260 1A49 ldr r1, .L201 3128 0262 1343 orrs r3, r3, r2 3129 0264 4B60 str r3, [r1, #4] 3130 .L196: 798:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 799:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 800:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /*-------------------------- PCLK2 Configuration ---------------------------*/ 801:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 3131 .loc 1 801 25 3132 0266 7B68 ldr r3, [r7, #4] 3133 0268 1B68 ldr r3, [r3] 3134 .loc 1 801 38 ARM GAS /tmp/ccSuWkwR.s page 90 3135 026a 03F00803 and r3, r3, #8 3136 .loc 1 801 5 3137 026e 002B cmp r3, #0 3138 0270 09D0 beq .L197 802:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 803:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); 804:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); 3139 .loc 1 804 5 3140 0272 164B ldr r3, .L201 3141 0274 5B68 ldr r3, [r3, #4] 3142 0276 23F46052 bic r2, r3, #14336 3143 027a 7B68 ldr r3, [r7, #4] 3144 027c 1B69 ldr r3, [r3, #16] 3145 027e DB00 lsls r3, r3, #3 3146 0280 1249 ldr r1, .L201 3147 0282 1343 orrs r3, r3, r2 3148 0284 4B60 str r3, [r1, #4] 3149 .L197: 805:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 806:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 807:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Update the SystemCoreClock global variable */ 808:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CF 3150 .loc 1 808 21 3151 0286 FFF7FEFF bl HAL_RCC_GetSysClockFreq 3152 028a 0146 mov r1, r0 3153 .loc 1 808 68 discriminator 1 3154 028c 0F4B ldr r3, .L201 3155 028e 5B68 ldr r3, [r3, #4] 3156 .loc 1 808 75 discriminator 1 3157 0290 03F0F003 and r3, r3, #240 3158 0294 F022 movs r2, #240 3159 0296 3A61 str r2, [r7, #16] 3160 .LBB318: 3161 .LBB319: 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 3162 .loc 2 988 4 3163 0298 3A69 ldr r2, [r7, #16] 3164 .syntax unified 3165 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 3166 029a 92FAA2F2 rbit r2, r2 3167 @ 0 "" 2 3168 .thumb 3169 .syntax unified 3170 029e FA60 str r2, [r7, #12] 3171 .loc 2 1001 10 3172 02a0 FA68 ldr r2, [r7, #12] 3173 .LBE319: 3174 .LBE318: 3175 .loc 1 808 94 discriminator 2 3176 02a2 B2FA82F2 clz r2, r2 3177 .loc 1 808 94 is_stmt 0 discriminator 3 3178 02a6 D2B2 uxtb r2, r2 3179 .loc 1 808 91 is_stmt 1 discriminator 3 3180 02a8 D340 lsrs r3, r3, r2 3181 .loc 1 808 63 discriminator 3 3182 02aa 094A ldr r2, .L201+4 3183 02ac D35C ldrb r3, [r2, r3] @ zero_extendqisi2 ARM GAS /tmp/ccSuWkwR.s page 91 3184 .loc 1 808 47 discriminator 3 3185 02ae 21FA03F3 lsr r3, r1, r3 3186 .loc 1 808 19 discriminator 3 3187 02b2 084A ldr r2, .L201+8 3188 02b4 1360 str r3, [r2] 809:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 810:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Configure the source of time base considering new system clocks settings*/ 811:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** HAL_InitTick (uwTickPrio); 3189 .loc 1 811 3 3190 02b6 084B ldr r3, .L201+12 3191 02b8 1B68 ldr r3, [r3] 3192 02ba 1846 mov r0, r3 3193 02bc FFF7FEFF bl HAL_InitTick 812:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 813:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_OK; 3194 .loc 1 813 10 3195 02c0 0023 movs r3, #0 3196 .L168: 814:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 3197 .loc 1 814 1 3198 02c2 1846 mov r0, r3 3199 02c4 7837 adds r7, r7, #120 3200 .cfi_def_cfa_offset 8 3201 02c6 BD46 mov sp, r7 3202 .cfi_def_cfa_register 13 3203 @ sp needed 3204 02c8 80BD pop {r7, pc} 3205 .L202: 3206 02ca 00BF .align 2 3207 .L201: 3208 02cc 00100240 .word 1073876992 3209 02d0 00000000 .word AHBPrescTable 3210 02d4 00000000 .word SystemCoreClock 3211 02d8 00000000 .word uwTickPrio 3212 .cfi_endproc 3213 .LFE132: 3215 .section .text.HAL_RCC_MCOConfig,"ax",%progbits 3216 .align 1 3217 .global HAL_RCC_MCOConfig 3218 .syntax unified 3219 .thumb 3220 .thumb_func 3222 HAL_RCC_MCOConfig: 3223 .LFB133: 815:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 816:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** 817:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @} 818:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ 819:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 820:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions 821:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @brief RCC clocks control functions 822:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * 823:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** @verbatim 824:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** =============================================================================== 825:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** ##### Peripheral Control functions ##### 826:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** =============================================================================== 827:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** [..] ARM GAS /tmp/ccSuWkwR.s page 92 828:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** This subsection provides a set of functions allowing to control the RCC Clocks 829:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** frequencies. 830:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 831:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** @endverbatim 832:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @{ 833:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ 834:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 835:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #if defined(RCC_CFGR_MCOPRE) 836:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** 837:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @brief Selects the clock source to output on MCO pin. 838:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note MCO pin should be configured in alternate function mode. 839:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @param RCC_MCOx specifies the output direction for the clock source. 840:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * This parameter can be one of the following values: 841:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8). 842:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @param RCC_MCOSource specifies the clock source to output. 843:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * This parameter can be one of the following values: 844:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected 845:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock 846:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock 847:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock 848:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock 849:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock 850:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock 851:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock 852:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @param RCC_MCODiv specifies the MCO DIV. 853:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * This parameter can be one of the following values: 854:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCODIV_1 no division applied to MCO clock 855:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCODIV_2 division by 2 applied to MCO clock 856:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCODIV_4 division by 4 applied to MCO clock 857:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCODIV_8 division by 8 applied to MCO clock 858:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCODIV_16 division by 16 applied to MCO clock 859:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCODIV_32 division by 32 applied to MCO clock 860:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCODIV_64 division by 64 applied to MCO clock 861:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCODIV_128 division by 128 applied to MCO clock 862:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @retval None 863:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ 864:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #else 865:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** 866:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @brief Selects the clock source to output on MCO pin. 867:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note MCO pin should be configured in alternate function mode. 868:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @param RCC_MCOx specifies the output direction for the clock source. 869:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * This parameter can be one of the following values: 870:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8). 871:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @param RCC_MCOSource specifies the clock source to output. 872:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * This parameter can be one of the following values: 873:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock 874:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO clock 875:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock 876:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock 877:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock 878:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock 879:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock 880:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @param RCC_MCODiv specifies the MCO DIV. 881:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * This parameter can be one of the following values: 882:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCODIV_1 no division applied to MCO clock 883:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @retval None 884:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ ARM GAS /tmp/ccSuWkwR.s page 93 885:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #endif 886:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) 887:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 3224 .loc 1 887 1 3225 .cfi_startproc 3226 @ args = 0, pretend = 0, frame = 40 3227 @ frame_needed = 1, uses_anonymous_args = 0 3228 0000 80B5 push {r7, lr} 3229 .cfi_def_cfa_offset 8 3230 .cfi_offset 7, -8 3231 .cfi_offset 14, -4 3232 0002 8AB0 sub sp, sp, #40 3233 .cfi_def_cfa_offset 48 3234 0004 00AF add r7, sp, #0 3235 .cfi_def_cfa_register 7 3236 0006 F860 str r0, [r7, #12] 3237 0008 B960 str r1, [r7, #8] 3238 000a 7A60 str r2, [r7, #4] 888:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** GPIO_InitTypeDef gpio; 889:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 890:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check the parameters */ 891:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** assert_param(IS_RCC_MCO(RCC_MCOx)); 892:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** assert_param(IS_RCC_MCODIV(RCC_MCODiv)); 893:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); 894:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 895:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Configure the MCO1 pin in alternate function mode */ 896:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** gpio.Mode = GPIO_MODE_AF_PP; 3239 .loc 1 896 18 3240 000c 0223 movs r3, #2 3241 000e BB61 str r3, [r7, #24] 897:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** gpio.Speed = GPIO_SPEED_FREQ_HIGH; 3242 .loc 1 897 18 3243 0010 0323 movs r3, #3 3244 0012 3B62 str r3, [r7, #32] 898:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** gpio.Pull = GPIO_NOPULL; 3245 .loc 1 898 18 3246 0014 0023 movs r3, #0 3247 0016 FB61 str r3, [r7, #28] 899:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** gpio.Pin = MCO1_PIN; 3248 .loc 1 899 18 3249 0018 4FF48073 mov r3, #256 3250 001c 7B61 str r3, [r7, #20] 900:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** gpio.Alternate = GPIO_AF0_MCO; 3251 .loc 1 900 18 3252 001e 0023 movs r3, #0 3253 0020 7B62 str r3, [r7, #36] 3254 .LBB320: 901:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 902:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* MCO1 Clock Enable */ 903:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** MCO1_CLK_ENABLE(); 3255 .loc 1 903 3 3256 0022 0F4B ldr r3, .L204 3257 0024 5B69 ldr r3, [r3, #20] 3258 0026 0E4A ldr r2, .L204 3259 0028 43F40033 orr r3, r3, #131072 3260 002c 5361 str r3, [r2, #20] 3261 002e 0C4B ldr r3, .L204 ARM GAS /tmp/ccSuWkwR.s page 94 3262 0030 5B69 ldr r3, [r3, #20] 3263 0032 03F40033 and r3, r3, #131072 3264 0036 3B61 str r3, [r7, #16] 3265 0038 3B69 ldr r3, [r7, #16] 3266 .LBE320: 904:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 905:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio); 3267 .loc 1 905 3 3268 003a 07F11403 add r3, r7, #20 3269 003e 1946 mov r1, r3 3270 0040 4FF09040 mov r0, #1207959552 3271 0044 FFF7FEFF bl HAL_GPIO_Init 906:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 907:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Configure the MCO clock source */ 908:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** __HAL_RCC_MCO1_CONFIG(RCC_MCOSource, RCC_MCODiv); 3272 .loc 1 908 3 3273 0048 054B ldr r3, .L204 3274 004a 5B68 ldr r3, [r3, #4] 3275 004c 23F0E062 bic r2, r3, #117440512 3276 0050 0349 ldr r1, .L204 3277 0052 BB68 ldr r3, [r7, #8] 3278 0054 1343 orrs r3, r3, r2 3279 0056 4B60 str r3, [r1, #4] 909:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 3280 .loc 1 909 1 3281 0058 00BF nop 3282 005a 2837 adds r7, r7, #40 3283 .cfi_def_cfa_offset 8 3284 005c BD46 mov sp, r7 3285 .cfi_def_cfa_register 13 3286 @ sp needed 3287 005e 80BD pop {r7, pc} 3288 .L205: 3289 .align 2 3290 .L204: 3291 0060 00100240 .word 1073876992 3292 .cfi_endproc 3293 .LFE133: 3295 .section .text.HAL_RCC_EnableCSS,"ax",%progbits 3296 .align 1 3297 .global HAL_RCC_EnableCSS 3298 .syntax unified 3299 .thumb 3300 .thumb_func 3302 HAL_RCC_EnableCSS: 3303 .LFB134: 910:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 911:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** 912:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @brief Enables the Clock Security System. 913:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note If a failure is detected on the HSE oscillator clock, this oscillator 914:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * is automatically disabled and an interrupt is generated to inform the 915:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * software about the failure (Clock Security System Interrupt, CSSI), 916:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * allowing the MCU to perform rescue operations. The CSSI is linked to 917:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector. 918:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @retval None 919:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ 920:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** void HAL_RCC_EnableCSS(void) ARM GAS /tmp/ccSuWkwR.s page 95 921:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 3304 .loc 1 921 1 3305 .cfi_startproc 3306 @ args = 0, pretend = 0, frame = 8 3307 @ frame_needed = 1, uses_anonymous_args = 0 3308 @ link register save eliminated. 3309 0000 80B4 push {r7} 3310 .cfi_def_cfa_offset 4 3311 .cfi_offset 7, -4 3312 0002 83B0 sub sp, sp, #12 3313 .cfi_def_cfa_offset 16 3314 0004 00AF add r7, sp, #0 3315 .cfi_def_cfa_register 7 3316 0006 4FF40023 mov r3, #524288 3317 000a 7B60 str r3, [r7, #4] 3318 .LBB321: 3319 .LBB322: 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 3320 .loc 2 988 4 3321 000c 7B68 ldr r3, [r7, #4] 3322 .syntax unified 3323 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 3324 000e 93FAA3F3 rbit r3, r3 3325 @ 0 "" 2 3326 .thumb 3327 .syntax unified 3328 0012 3B60 str r3, [r7] 3329 .loc 2 1001 10 3330 0014 3B68 ldr r3, [r7] 3331 .LBE322: 3332 .LBE321: 922:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)ENABLE; 3333 .loc 1 922 22 discriminator 1 3334 0016 B3FA83F3 clz r3, r3 3335 .loc 1 922 22 is_stmt 0 discriminator 2 3336 001a DBB2 uxtb r3, r3 3337 001c 03F18453 add r3, r3, #276824064 3338 0020 03F58413 add r3, r3, #1081344 3339 0024 9B00 lsls r3, r3, #2 3340 .loc 1 922 4 is_stmt 1 discriminator 2 3341 0026 1A46 mov r2, r3 3342 .loc 1 922 38 discriminator 2 3343 0028 0123 movs r3, #1 3344 002a 1360 str r3, [r2] 923:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 3345 .loc 1 923 1 3346 002c 00BF nop 3347 002e 0C37 adds r7, r7, #12 3348 .cfi_def_cfa_offset 4 3349 0030 BD46 mov sp, r7 3350 .cfi_def_cfa_register 13 3351 @ sp needed 3352 0032 5DF8047B ldr r7, [sp], #4 3353 .cfi_restore 7 3354 .cfi_def_cfa_offset 0 3355 0036 7047 bx lr 3356 .cfi_endproc ARM GAS /tmp/ccSuWkwR.s page 96 3357 .LFE134: 3359 .section .text.HAL_RCC_DisableCSS,"ax",%progbits 3360 .align 1 3361 .global HAL_RCC_DisableCSS 3362 .syntax unified 3363 .thumb 3364 .thumb_func 3366 HAL_RCC_DisableCSS: 3367 .LFB135: 924:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 925:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** 926:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @brief Disables the Clock Security System. 927:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @retval None 928:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ 929:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** void HAL_RCC_DisableCSS(void) 930:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 3368 .loc 1 930 1 3369 .cfi_startproc 3370 @ args = 0, pretend = 0, frame = 8 3371 @ frame_needed = 1, uses_anonymous_args = 0 3372 @ link register save eliminated. 3373 0000 80B4 push {r7} 3374 .cfi_def_cfa_offset 4 3375 .cfi_offset 7, -4 3376 0002 83B0 sub sp, sp, #12 3377 .cfi_def_cfa_offset 16 3378 0004 00AF add r7, sp, #0 3379 .cfi_def_cfa_register 7 3380 0006 4FF40023 mov r3, #524288 3381 000a 7B60 str r3, [r7, #4] 3382 .LBB323: 3383 .LBB324: 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 3384 .loc 2 988 4 3385 000c 7B68 ldr r3, [r7, #4] 3386 .syntax unified 3387 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 3388 000e 93FAA3F3 rbit r3, r3 3389 @ 0 "" 2 3390 .thumb 3391 .syntax unified 3392 0012 3B60 str r3, [r7] 3393 .loc 2 1001 10 3394 0014 3B68 ldr r3, [r7] 3395 .LBE324: 3396 .LBE323: 931:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)DISABLE; 3397 .loc 1 931 22 discriminator 1 3398 0016 B3FA83F3 clz r3, r3 3399 .loc 1 931 22 is_stmt 0 discriminator 2 3400 001a DBB2 uxtb r3, r3 3401 001c 03F18453 add r3, r3, #276824064 3402 0020 03F58413 add r3, r3, #1081344 3403 0024 9B00 lsls r3, r3, #2 3404 .loc 1 931 4 is_stmt 1 discriminator 2 3405 0026 1A46 mov r2, r3 3406 .loc 1 931 38 discriminator 2 ARM GAS /tmp/ccSuWkwR.s page 97 3407 0028 0023 movs r3, #0 3408 002a 1360 str r3, [r2] 932:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 3409 .loc 1 932 1 3410 002c 00BF nop 3411 002e 0C37 adds r7, r7, #12 3412 .cfi_def_cfa_offset 4 3413 0030 BD46 mov sp, r7 3414 .cfi_def_cfa_register 13 3415 @ sp needed 3416 0032 5DF8047B ldr r7, [sp], #4 3417 .cfi_restore 7 3418 .cfi_def_cfa_offset 0 3419 0036 7047 bx lr 3420 .cfi_endproc 3421 .LFE135: 3423 .section .text.HAL_RCC_GetSysClockFreq,"ax",%progbits 3424 .align 1 3425 .global HAL_RCC_GetSysClockFreq 3426 .syntax unified 3427 .thumb 3428 .thumb_func 3430 HAL_RCC_GetSysClockFreq: 3431 .LFB136: 933:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 934:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** 935:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @brief Returns the SYSCLK frequency 936:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note The system frequency computed by this function is not the real 937:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * frequency in the chip. It is calculated based on the predefined 938:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * constant and the selected clock source: 939:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) 940:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note If SYSCLK source is HSE, function returns a value based on HSE_VALUE 941:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * divided by PREDIV factor(**) 942:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note If SYSCLK source is PLL, function returns a value based on HSE_VALUE 943:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * divided by PREDIV factor(**) or HSI_VALUE(*) multiplied by the PLL factor. 944:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note (*) HSI_VALUE is a constant defined in stm32f3xx_hal_conf.h file (default value 945:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * 8 MHz) but the real value may vary depending on the variations 946:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * in voltage and temperature. 947:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note (**) HSE_VALUE is a constant defined in stm32f3xx_hal_conf.h file (default value 948:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * 8 MHz), user has to ensure that HSE_VALUE is same as the real 949:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * frequency of the crystal used. Otherwise, this function may 950:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * have wrong result. 951:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * 952:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note The result of this function could be not correct when using fractional 953:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * value for HSE crystal. 954:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * 955:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note This function can be used by the user application to compute the 956:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * baud-rate for the communication peripherals or configure other parameters. 957:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * 958:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note Each time SYSCLK changes, this function must be called to update the 959:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * right SYSCLK value. Otherwise, any configuration based on this function will be incorre 960:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * 961:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @retval SYSCLK frequency 962:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ 963:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** uint32_t HAL_RCC_GetSysClockFreq(void) 964:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 3432 .loc 1 964 1 ARM GAS /tmp/ccSuWkwR.s page 98 3433 .cfi_startproc 3434 @ args = 0, pretend = 0, frame = 40 3435 @ frame_needed = 1, uses_anonymous_args = 0 3436 @ link register save eliminated. 3437 0000 80B4 push {r7} 3438 .cfi_def_cfa_offset 4 3439 .cfi_offset 7, -4 3440 0002 8BB0 sub sp, sp, #44 3441 .cfi_def_cfa_offset 48 3442 0004 00AF add r7, sp, #0 3443 .cfi_def_cfa_register 7 965:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U; 3444 .loc 1 965 12 3445 0006 0023 movs r3, #0 3446 0008 FB61 str r3, [r7, #28] 3447 .loc 1 965 25 3448 000a 0023 movs r3, #0 3449 000c BB61 str r3, [r7, #24] 3450 .loc 1 965 38 3451 000e 0023 movs r3, #0 3452 0010 7B62 str r3, [r7, #36] 3453 .loc 1 965 51 3454 0012 0023 movs r3, #0 3455 0014 7B61 str r3, [r7, #20] 966:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** uint32_t sysclockfreq = 0U; 3456 .loc 1 966 12 3457 0016 0023 movs r3, #0 3458 0018 3B62 str r3, [r7, #32] 967:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 968:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** tmpreg = RCC->CFGR; 3459 .loc 1 968 15 3460 001a 294B ldr r3, .L221 3461 .loc 1 968 10 3462 001c 5B68 ldr r3, [r3, #4] 3463 001e FB61 str r3, [r7, #28] 969:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 970:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get SYSCLK source -------------------------------------------------------*/ 971:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** switch (tmpreg & RCC_CFGR_SWS) 3464 .loc 1 971 18 3465 0020 FB69 ldr r3, [r7, #28] 3466 0022 03F00C03 and r3, r3, #12 3467 .loc 1 971 3 3468 0026 042B cmp r3, #4 3469 0028 02D0 beq .L211 3470 002a 082B cmp r3, #8 3471 002c 03D0 beq .L212 3472 002e 3CE0 b .L220 3473 .L211: 972:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 973:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ 974:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 975:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** sysclockfreq = HSE_VALUE; 3474 .loc 1 975 20 3475 0030 244B ldr r3, .L221+4 3476 0032 3B62 str r3, [r7, #32] 976:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** break; 3477 .loc 1 976 7 ARM GAS /tmp/ccSuWkwR.s page 99 3478 0034 3CE0 b .L214 3479 .L212: 977:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 978:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ 979:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 980:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> POSITION_VAL(RCC_CFGR_PLL 3480 .loc 1 980 35 3481 0036 FB69 ldr r3, [r7, #28] 3482 0038 03F47013 and r3, r3, #3932160 3483 003c 4FF47012 mov r2, #3932160 3484 0040 BA60 str r2, [r7, #8] 3485 .LBB325: 3486 .LBB326: 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 3487 .loc 2 988 4 3488 0042 BA68 ldr r2, [r7, #8] 3489 .syntax unified 3490 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 3491 0044 92FAA2F2 rbit r2, r2 3492 @ 0 "" 2 3493 .thumb 3494 .syntax unified 3495 0048 7A60 str r2, [r7, #4] 3496 .loc 2 1001 10 3497 004a 7A68 ldr r2, [r7, #4] 3498 .LBE326: 3499 .LBE325: 3500 .loc 1 980 75 discriminator 1 3501 004c B2FA82F2 clz r2, r2 3502 .loc 1 980 75 is_stmt 0 discriminator 2 3503 0050 D2B2 uxtb r2, r2 3504 .loc 1 980 72 is_stmt 1 discriminator 2 3505 0052 D340 lsrs r3, r3, r2 3506 .loc 1 980 34 discriminator 2 3507 0054 1C4A ldr r2, .L221+8 3508 0056 D35C ldrb r3, [r2, r3] @ zero_extendqisi2 3509 .loc 1 980 14 discriminator 2 3510 0058 7B61 str r3, [r7, #20] 981:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV) >> POSITION_VAL(RCC_CFG 3511 .loc 1 981 49 3512 005a 194B ldr r3, .L221 3513 005c DB6A ldr r3, [r3, #44] 3514 .loc 1 981 35 3515 005e 03F00F03 and r3, r3, #15 3516 0062 0F22 movs r2, #15 3517 0064 3A61 str r2, [r7, #16] 3518 .LBB327: 3519 .LBB328: 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 3520 .loc 2 988 4 3521 0066 3A69 ldr r2, [r7, #16] 3522 .syntax unified 3523 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 3524 0068 92FAA2F2 rbit r2, r2 3525 @ 0 "" 2 3526 .thumb 3527 .syntax unified ARM GAS /tmp/ccSuWkwR.s page 100 3528 006c FA60 str r2, [r7, #12] 3529 .loc 2 1001 10 3530 006e FA68 ldr r2, [r7, #12] 3531 .LBE328: 3532 .LBE327: 3533 .loc 1 981 80 discriminator 1 3534 0070 B2FA82F2 clz r2, r2 3535 .loc 1 981 80 is_stmt 0 discriminator 2 3536 0074 D2B2 uxtb r2, r2 3537 .loc 1 981 77 is_stmt 1 discriminator 2 3538 0076 D340 lsrs r3, r3, r2 3539 .loc 1 981 34 discriminator 2 3540 0078 144A ldr r2, .L221+12 3541 007a D35C ldrb r3, [r2, r3] @ zero_extendqisi2 3542 .loc 1 981 14 discriminator 2 3543 007c BB61 str r3, [r7, #24] 982:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #if defined(RCC_CFGR_PLLSRC_HSI_DIV2) 983:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI) 3544 .loc 1 983 19 3545 007e FB69 ldr r3, [r7, #28] 3546 0080 03F48033 and r3, r3, #65536 3547 .loc 1 983 10 3548 0084 002B cmp r3, #0 3549 0086 08D0 beq .L217 984:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 985:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */ 986:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** pllclk = (uint32_t)((uint64_t) HSE_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul); 3550 .loc 1 986 18 3551 0088 0E4A ldr r2, .L221+4 3552 008a BB69 ldr r3, [r7, #24] 3553 008c B2FBF3F2 udiv r2, r2, r3 3554 .loc 1 986 16 3555 0090 7B69 ldr r3, [r7, #20] 3556 0092 02FB03F3 mul r3, r2, r3 3557 0096 7B62 str r3, [r7, #36] 3558 0098 04E0 b .L218 3559 .L217: 987:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 988:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** else 989:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 990:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ 991:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** pllclk = (uint32_t)((uint64_t) (HSI_VALUE >> 1U) * ((uint64_t) pllmul)); 3560 .loc 1 991 16 3561 009a 7B69 ldr r3, [r7, #20] 3562 009c 0C4A ldr r2, .L221+16 3563 009e 02FB03F3 mul r3, r2, r3 3564 00a2 7B62 str r3, [r7, #36] 3565 .L218: 992:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 993:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #else 994:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if ((tmpreg & RCC_CFGR_PLLSRC_HSE_PREDIV) == RCC_CFGR_PLLSRC_HSE_PREDIV) 995:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 996:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */ 997:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** pllclk = (uint32_t)((uint64_t) HSE_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul); 998:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 999:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** else 1000:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { ARM GAS /tmp/ccSuWkwR.s page 101 1001:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */ 1002:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** pllclk = (uint32_t)((uint64_t) HSI_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul); 1003:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 1004:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */ 1005:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** sysclockfreq = pllclk; 3566 .loc 1 1005 20 3567 00a4 7B6A ldr r3, [r7, #36] 3568 00a6 3B62 str r3, [r7, #32] 1006:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** break; 3569 .loc 1 1006 7 3570 00a8 02E0 b .L214 3571 .L220: 1007:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 1008:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ 1009:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** default: /* HSI used as system clock */ 1010:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 1011:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** sysclockfreq = HSI_VALUE; 3572 .loc 1 1011 20 3573 00aa 0A4B ldr r3, .L221+20 3574 00ac 3B62 str r3, [r7, #32] 1012:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** break; 3575 .loc 1 1012 7 3576 00ae 00BF nop 3577 .L214: 1013:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 1014:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 1015:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return sysclockfreq; 3578 .loc 1 1015 10 3579 00b0 3B6A ldr r3, [r7, #32] 1016:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 3580 .loc 1 1016 1 3581 00b2 1846 mov r0, r3 3582 00b4 2C37 adds r7, r7, #44 3583 .cfi_def_cfa_offset 4 3584 00b6 BD46 mov sp, r7 3585 .cfi_def_cfa_register 13 3586 @ sp needed 3587 00b8 5DF8047B ldr r7, [sp], #4 3588 .cfi_restore 7 3589 .cfi_def_cfa_offset 0 3590 00bc 7047 bx lr 3591 .L222: 3592 00be 00BF .align 2 3593 .L221: 3594 00c0 00100240 .word 1073876992 3595 00c4 0024F400 .word 16000000 3596 00c8 00000000 .word aPLLMULFactorTable 3597 00cc 00000000 .word aPredivFactorTable 3598 00d0 00093D00 .word 4000000 3599 00d4 00127A00 .word 8000000 3600 .cfi_endproc 3601 .LFE136: 3603 .section .text.HAL_RCC_GetHCLKFreq,"ax",%progbits 3604 .align 1 3605 .global HAL_RCC_GetHCLKFreq 3606 .syntax unified 3607 .thumb ARM GAS /tmp/ccSuWkwR.s page 102 3608 .thumb_func 3610 HAL_RCC_GetHCLKFreq: 3611 .LFB137: 1017:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 1018:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** 1019:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @brief Returns the HCLK frequency 1020:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note Each time HCLK changes, this function must be called to update the 1021:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * right HCLK value. Otherwise, any configuration based on this function will be incorrect 1022:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * 1023:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency 1024:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * and updated within this function 1025:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @retval HCLK frequency 1026:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ 1027:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** uint32_t HAL_RCC_GetHCLKFreq(void) 1028:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 3612 .loc 1 1028 1 3613 .cfi_startproc 3614 @ args = 0, pretend = 0, frame = 0 3615 @ frame_needed = 1, uses_anonymous_args = 0 3616 @ link register save eliminated. 3617 0000 80B4 push {r7} 3618 .cfi_def_cfa_offset 4 3619 .cfi_offset 7, -4 3620 0002 00AF add r7, sp, #0 3621 .cfi_def_cfa_register 7 1029:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return SystemCoreClock; 3622 .loc 1 1029 10 3623 0004 034B ldr r3, .L225 3624 0006 1B68 ldr r3, [r3] 1030:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 3625 .loc 1 1030 1 3626 0008 1846 mov r0, r3 3627 000a BD46 mov sp, r7 3628 .cfi_def_cfa_register 13 3629 @ sp needed 3630 000c 5DF8047B ldr r7, [sp], #4 3631 .cfi_restore 7 3632 .cfi_def_cfa_offset 0 3633 0010 7047 bx lr 3634 .L226: 3635 0012 00BF .align 2 3636 .L225: 3637 0014 00000000 .word SystemCoreClock 3638 .cfi_endproc 3639 .LFE137: 3641 .section .text.HAL_RCC_GetPCLK1Freq,"ax",%progbits 3642 .align 1 3643 .global HAL_RCC_GetPCLK1Freq 3644 .syntax unified 3645 .thumb 3646 .thumb_func 3648 HAL_RCC_GetPCLK1Freq: 3649 .LFB138: 1031:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 1032:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** 1033:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @brief Returns the PCLK1 frequency 1034:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note Each time PCLK1 changes, this function must be called to update the ARM GAS /tmp/ccSuWkwR.s page 103 1035:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * right PCLK1 value. Otherwise, any configuration based on this function will be incorrec 1036:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @retval PCLK1 frequency 1037:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ 1038:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** uint32_t HAL_RCC_GetPCLK1Freq(void) 1039:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 3650 .loc 1 1039 1 3651 .cfi_startproc 3652 @ args = 0, pretend = 0, frame = 8 3653 @ frame_needed = 1, uses_anonymous_args = 0 3654 0000 80B5 push {r7, lr} 3655 .cfi_def_cfa_offset 8 3656 .cfi_offset 7, -8 3657 .cfi_offset 14, -4 3658 0002 82B0 sub sp, sp, #8 3659 .cfi_def_cfa_offset 16 3660 0004 00AF add r7, sp, #0 3661 .cfi_def_cfa_register 7 1040:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ 1041:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_BIT 3662 .loc 1 1041 11 3663 0006 FFF7FEFF bl HAL_RCC_GetHCLKFreq 3664 000a 0146 mov r1, r0 3665 .loc 1 1041 54 discriminator 1 3666 000c 0B4B ldr r3, .L230 3667 000e 5B68 ldr r3, [r3, #4] 3668 .loc 1 1041 61 discriminator 1 3669 0010 03F4E063 and r3, r3, #1792 3670 0014 4FF4E062 mov r2, #1792 3671 0018 7A60 str r2, [r7, #4] 3672 .LBB329: 3673 .LBB330: 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 3674 .loc 2 988 4 3675 001a 7A68 ldr r2, [r7, #4] 3676 .syntax unified 3677 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 3678 001c 92FAA2F2 rbit r2, r2 3679 @ 0 "" 2 3680 .thumb 3681 .syntax unified 3682 0020 3A60 str r2, [r7] 3683 .loc 2 1001 10 3684 0022 3A68 ldr r2, [r7] 3685 .LBE330: 3686 .LBE329: 3687 .loc 1 1041 82 discriminator 2 3688 0024 B2FA82F2 clz r2, r2 3689 .loc 1 1041 82 is_stmt 0 discriminator 3 3690 0028 D2B2 uxtb r2, r2 3691 .loc 1 1041 79 is_stmt 1 discriminator 3 3692 002a D340 lsrs r3, r3, r2 3693 .loc 1 1041 49 discriminator 3 3694 002c 044A ldr r2, .L230+4 3695 002e D35C ldrb r3, [r2, r3] @ zero_extendqisi2 3696 .loc 1 1041 33 discriminator 3 3697 0030 21FA03F3 lsr r3, r1, r3 1042:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } ARM GAS /tmp/ccSuWkwR.s page 104 3698 .loc 1 1042 1 3699 0034 1846 mov r0, r3 3700 0036 0837 adds r7, r7, #8 3701 .cfi_def_cfa_offset 8 3702 0038 BD46 mov sp, r7 3703 .cfi_def_cfa_register 13 3704 @ sp needed 3705 003a 80BD pop {r7, pc} 3706 .L231: 3707 .align 2 3708 .L230: 3709 003c 00100240 .word 1073876992 3710 0040 00000000 .word APBPrescTable 3711 .cfi_endproc 3712 .LFE138: 3714 .section .text.HAL_RCC_GetPCLK2Freq,"ax",%progbits 3715 .align 1 3716 .global HAL_RCC_GetPCLK2Freq 3717 .syntax unified 3718 .thumb 3719 .thumb_func 3721 HAL_RCC_GetPCLK2Freq: 3722 .LFB139: 1043:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 1044:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** 1045:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @brief Returns the PCLK2 frequency 1046:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note Each time PCLK2 changes, this function must be called to update the 1047:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * right PCLK2 value. Otherwise, any configuration based on this function will be incorrec 1048:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @retval PCLK2 frequency 1049:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ 1050:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** uint32_t HAL_RCC_GetPCLK2Freq(void) 1051:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 3723 .loc 1 1051 1 3724 .cfi_startproc 3725 @ args = 0, pretend = 0, frame = 8 3726 @ frame_needed = 1, uses_anonymous_args = 0 3727 0000 80B5 push {r7, lr} 3728 .cfi_def_cfa_offset 8 3729 .cfi_offset 7, -8 3730 .cfi_offset 14, -4 3731 0002 82B0 sub sp, sp, #8 3732 .cfi_def_cfa_offset 16 3733 0004 00AF add r7, sp, #0 3734 .cfi_def_cfa_register 7 1052:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ 1053:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_BITN 3735 .loc 1 1053 11 3736 0006 FFF7FEFF bl HAL_RCC_GetHCLKFreq 3737 000a 0146 mov r1, r0 3738 .loc 1 1053 53 discriminator 1 3739 000c 0B4B ldr r3, .L235 3740 000e 5B68 ldr r3, [r3, #4] 3741 .loc 1 1053 60 discriminator 1 3742 0010 03F46053 and r3, r3, #14336 3743 0014 4FF46052 mov r2, #14336 3744 0018 7A60 str r2, [r7, #4] 3745 .LBB331: ARM GAS /tmp/ccSuWkwR.s page 105 3746 .LBB332: 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 3747 .loc 2 988 4 3748 001a 7A68 ldr r2, [r7, #4] 3749 .syntax unified 3750 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 3751 001c 92FAA2F2 rbit r2, r2 3752 @ 0 "" 2 3753 .thumb 3754 .syntax unified 3755 0020 3A60 str r2, [r7] 3756 .loc 2 1001 10 3757 0022 3A68 ldr r2, [r7] 3758 .LBE332: 3759 .LBE331: 3760 .loc 1 1053 81 discriminator 2 3761 0024 B2FA82F2 clz r2, r2 3762 .loc 1 1053 81 is_stmt 0 discriminator 3 3763 0028 D2B2 uxtb r2, r2 3764 .loc 1 1053 78 is_stmt 1 discriminator 3 3765 002a D340 lsrs r3, r3, r2 3766 .loc 1 1053 48 discriminator 3 3767 002c 044A ldr r2, .L235+4 3768 002e D35C ldrb r3, [r2, r3] @ zero_extendqisi2 3769 .loc 1 1053 32 discriminator 3 3770 0030 21FA03F3 lsr r3, r1, r3 1054:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 3771 .loc 1 1054 1 3772 0034 1846 mov r0, r3 3773 0036 0837 adds r7, r7, #8 3774 .cfi_def_cfa_offset 8 3775 0038 BD46 mov sp, r7 3776 .cfi_def_cfa_register 13 3777 @ sp needed 3778 003a 80BD pop {r7, pc} 3779 .L236: 3780 .align 2 3781 .L235: 3782 003c 00100240 .word 1073876992 3783 0040 00000000 .word APBPrescTable 3784 .cfi_endproc 3785 .LFE139: 3787 .section .text.HAL_RCC_GetOscConfig,"ax",%progbits 3788 .align 1 3789 .global HAL_RCC_GetOscConfig 3790 .syntax unified 3791 .thumb 3792 .thumb_func 3794 HAL_RCC_GetOscConfig: 3795 .LFB140: 1055:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 1056:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** 1057:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @brief Configures the RCC_OscInitStruct according to the internal 1058:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * RCC configuration registers. 1059:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that 1060:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * will be configured. 1061:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @retval None ARM GAS /tmp/ccSuWkwR.s page 106 1062:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ 1063:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) 1064:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 3796 .loc 1 1064 1 3797 .cfi_startproc 3798 @ args = 0, pretend = 0, frame = 16 3799 @ frame_needed = 1, uses_anonymous_args = 0 3800 @ link register save eliminated. 3801 0000 80B4 push {r7} 3802 .cfi_def_cfa_offset 4 3803 .cfi_offset 7, -4 3804 0002 85B0 sub sp, sp, #20 3805 .cfi_def_cfa_offset 24 3806 0004 00AF add r7, sp, #0 3807 .cfi_def_cfa_register 7 3808 0006 7860 str r0, [r7, #4] 1065:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check the parameters */ 1066:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** assert_param(RCC_OscInitStruct != NULL); 1067:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 1068:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Set all possible values for the Oscillator type parameter ---------------*/ 1069:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI \ 3809 .loc 1 1069 37 3810 0008 7B68 ldr r3, [r7, #4] 3811 000a 0F22 movs r2, #15 3812 000c 1A60 str r2, [r3] 1070:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI; 1071:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 1072:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 1073:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get the HSE configuration -----------------------------------------------*/ 1074:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP) 3813 .loc 1 1074 10 3814 000e 424B ldr r3, .L251 3815 0010 1B68 ldr r3, [r3] 3816 .loc 1 1074 15 3817 0012 03F48023 and r3, r3, #262144 3818 .loc 1 1074 5 3819 0016 B3F5802F cmp r3, #262144 3820 001a 04D1 bne .L238 1075:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 1076:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; 3821 .loc 1 1076 33 3822 001c 7B68 ldr r3, [r7, #4] 3823 001e 4FF4A022 mov r2, #327680 3824 0022 5A60 str r2, [r3, #4] 3825 0024 0EE0 b .L239 3826 .L238: 1077:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 1078:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON) 3827 .loc 1 1078 15 3828 0026 3C4B ldr r3, .L251 3829 0028 1B68 ldr r3, [r3] 3830 .loc 1 1078 20 3831 002a 03F48033 and r3, r3, #65536 3832 .loc 1 1078 10 3833 002e B3F5803F cmp r3, #65536 3834 0032 04D1 bne .L240 1079:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { ARM GAS /tmp/ccSuWkwR.s page 107 1080:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_OscInitStruct->HSEState = RCC_HSE_ON; 3835 .loc 1 1080 33 3836 0034 7B68 ldr r3, [r7, #4] 3837 0036 4FF48032 mov r2, #65536 3838 003a 5A60 str r2, [r3, #4] 3839 003c 02E0 b .L239 3840 .L240: 1081:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 1082:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** else 1083:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 1084:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_OscInitStruct->HSEState = RCC_HSE_OFF; 3841 .loc 1 1084 33 3842 003e 7B68 ldr r3, [r7, #4] 3843 0040 0022 movs r2, #0 3844 0042 5A60 str r2, [r3, #4] 3845 .L239: 1085:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 1086:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #if defined(RCC_CFGR_PLLSRC_HSI_DIV2) 1087:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_OscInitStruct->HSEPredivValue = __HAL_RCC_HSE_GET_PREDIV(); 3846 .loc 1 1087 39 3847 0044 344B ldr r3, .L251 3848 0046 DB6A ldr r3, [r3, #44] 3849 0048 03F00F02 and r2, r3, #15 3850 .loc 1 1087 37 3851 004c 7B68 ldr r3, [r7, #4] 3852 004e 9A60 str r2, [r3, #8] 1088:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #endif 1089:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 1090:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get the HSI configuration -----------------------------------------------*/ 1091:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION) 3853 .loc 1 1091 10 3854 0050 314B ldr r3, .L251 3855 0052 1B68 ldr r3, [r3] 3856 .loc 1 1091 15 3857 0054 03F00103 and r3, r3, #1 3858 .loc 1 1091 5 3859 0058 012B cmp r3, #1 3860 005a 03D1 bne .L241 1092:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 1093:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_OscInitStruct->HSIState = RCC_HSI_ON; 3861 .loc 1 1093 33 3862 005c 7B68 ldr r3, [r7, #4] 3863 005e 0122 movs r2, #1 3864 0060 1A61 str r2, [r3, #16] 3865 0062 02E0 b .L242 3866 .L241: 1094:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 1095:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** else 1096:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 1097:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_OscInitStruct->HSIState = RCC_HSI_OFF; 3867 .loc 1 1097 33 3868 0064 7B68 ldr r3, [r7, #4] 3869 0066 0022 movs r2, #0 3870 0068 1A61 str r2, [r3, #16] 3871 .L242: 1098:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 1099:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** ARM GAS /tmp/ccSuWkwR.s page 108 1100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> POSITION_VAL(RC 3872 .loc 1 1100 59 3873 006a 2B4B ldr r3, .L251 3874 006c 1B68 ldr r3, [r3] 3875 .loc 1 1100 64 3876 006e 03F0F803 and r3, r3, #248 3877 0072 F822 movs r2, #248 3878 0074 FA60 str r2, [r7, #12] 3879 .LBB333: 3880 .LBB334: 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 3881 .loc 2 988 4 3882 0076 FA68 ldr r2, [r7, #12] 3883 .syntax unified 3884 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 3885 0078 92FAA2F2 rbit r2, r2 3886 @ 0 "" 2 3887 .thumb 3888 .syntax unified 3889 007c BA60 str r2, [r7, #8] 3890 .loc 2 1001 10 3891 007e BA68 ldr r2, [r7, #8] 3892 .LBE334: 3893 .LBE333: 3894 .loc 1 1100 85 discriminator 1 3895 0080 B2FA82F2 clz r2, r2 3896 .loc 1 1100 85 is_stmt 0 discriminator 2 3897 0084 D2B2 uxtb r2, r2 3898 .loc 1 1100 44 is_stmt 1 discriminator 2 3899 0086 23FA02F2 lsr r2, r3, r2 3900 .loc 1 1100 42 discriminator 2 3901 008a 7B68 ldr r3, [r7, #4] 3902 008c 5A61 str r2, [r3, #20] 1101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 1102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get the LSE configuration -----------------------------------------------*/ 1103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) 3903 .loc 1 1103 10 3904 008e 224B ldr r3, .L251 3905 0090 1B6A ldr r3, [r3, #32] 3906 .loc 1 1103 17 3907 0092 03F00403 and r3, r3, #4 3908 .loc 1 1103 5 3909 0096 042B cmp r3, #4 3910 0098 03D1 bne .L244 1104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 1105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; 3911 .loc 1 1105 33 3912 009a 7B68 ldr r3, [r7, #4] 3913 009c 0522 movs r2, #5 3914 009e DA60 str r2, [r3, #12] 3915 00a0 0CE0 b .L245 3916 .L244: 1106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 1107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON) 3917 .loc 1 1107 15 3918 00a2 1D4B ldr r3, .L251 3919 00a4 1B6A ldr r3, [r3, #32] ARM GAS /tmp/ccSuWkwR.s page 109 3920 .loc 1 1107 22 3921 00a6 03F00103 and r3, r3, #1 3922 .loc 1 1107 10 3923 00aa 012B cmp r3, #1 3924 00ac 03D1 bne .L246 1108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 1109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_OscInitStruct->LSEState = RCC_LSE_ON; 3925 .loc 1 1109 33 3926 00ae 7B68 ldr r3, [r7, #4] 3927 00b0 0122 movs r2, #1 3928 00b2 DA60 str r2, [r3, #12] 3929 00b4 02E0 b .L245 3930 .L246: 1110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 1111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** else 1112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 1113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_OscInitStruct->LSEState = RCC_LSE_OFF; 3931 .loc 1 1113 33 3932 00b6 7B68 ldr r3, [r7, #4] 3933 00b8 0022 movs r2, #0 3934 00ba DA60 str r2, [r3, #12] 3935 .L245: 1114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 1115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 1116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get the LSI configuration -----------------------------------------------*/ 1117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION) 3936 .loc 1 1117 10 3937 00bc 164B ldr r3, .L251 3938 00be 5B6A ldr r3, [r3, #36] 3939 .loc 1 1117 16 3940 00c0 03F00103 and r3, r3, #1 3941 .loc 1 1117 5 3942 00c4 012B cmp r3, #1 3943 00c6 03D1 bne .L247 1118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 1119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_OscInitStruct->LSIState = RCC_LSI_ON; 3944 .loc 1 1119 33 3945 00c8 7B68 ldr r3, [r7, #4] 3946 00ca 0122 movs r2, #1 3947 00cc 9A61 str r2, [r3, #24] 3948 00ce 02E0 b .L248 3949 .L247: 1120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 1121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** else 1122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 1123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_OscInitStruct->LSIState = RCC_LSI_OFF; 3950 .loc 1 1123 33 3951 00d0 7B68 ldr r3, [r7, #4] 3952 00d2 0022 movs r2, #0 3953 00d4 9A61 str r2, [r3, #24] 3954 .L248: 1124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 1125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 1126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 1127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get the PLL configuration -----------------------------------------------*/ 1128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON) 3955 .loc 1 1128 10 ARM GAS /tmp/ccSuWkwR.s page 110 3956 00d6 104B ldr r3, .L251 3957 00d8 1B68 ldr r3, [r3] 3958 .loc 1 1128 15 3959 00da 03F08073 and r3, r3, #16777216 3960 .loc 1 1128 5 3961 00de B3F1807F cmp r3, #16777216 3962 00e2 03D1 bne .L249 1129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 1130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON; 3963 .loc 1 1130 37 3964 00e4 7B68 ldr r3, [r7, #4] 3965 00e6 0222 movs r2, #2 3966 00e8 DA61 str r2, [r3, #28] 3967 00ea 02E0 b .L250 3968 .L249: 1131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 1132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** else 1133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 1134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF; 3969 .loc 1 1134 37 3970 00ec 7B68 ldr r3, [r7, #4] 3971 00ee 0122 movs r2, #1 3972 00f0 DA61 str r2, [r3, #28] 3973 .L250: 1135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 1136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC); 3974 .loc 1 1136 52 3975 00f2 094B ldr r3, .L251 3976 00f4 5B68 ldr r3, [r3, #4] 3977 .loc 1 1136 38 3978 00f6 03F48032 and r2, r3, #65536 3979 .loc 1 1136 36 3980 00fa 7B68 ldr r3, [r7, #4] 3981 00fc 1A62 str r2, [r3, #32] 1137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMUL); 3982 .loc 1 1137 49 3983 00fe 064B ldr r3, .L251 3984 0100 5B68 ldr r3, [r3, #4] 3985 .loc 1 1137 35 3986 0102 03F47012 and r2, r3, #3932160 3987 .loc 1 1137 33 3988 0106 7B68 ldr r3, [r7, #4] 3989 0108 5A62 str r2, [r3, #36] 1138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #if defined(RCC_CFGR_PLLSRC_HSI_PREDIV) 1139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PREDIV = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV); 1140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #endif /* RCC_CFGR_PLLSRC_HSI_PREDIV */ 1141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 3990 .loc 1 1141 1 3991 010a 00BF nop 3992 010c 1437 adds r7, r7, #20 3993 .cfi_def_cfa_offset 4 3994 010e BD46 mov sp, r7 3995 .cfi_def_cfa_register 13 3996 @ sp needed 3997 0110 5DF8047B ldr r7, [sp], #4 3998 .cfi_restore 7 3999 .cfi_def_cfa_offset 0 ARM GAS /tmp/ccSuWkwR.s page 111 4000 0114 7047 bx lr 4001 .L252: 4002 0116 00BF .align 2 4003 .L251: 4004 0118 00100240 .word 1073876992 4005 .cfi_endproc 4006 .LFE140: 4008 .section .text.HAL_RCC_GetClockConfig,"ax",%progbits 4009 .align 1 4010 .global HAL_RCC_GetClockConfig 4011 .syntax unified 4012 .thumb 4013 .thumb_func 4015 HAL_RCC_GetClockConfig: 4016 .LFB141: 1142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 1143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** 1144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @brief Get the RCC_ClkInitStruct according to the internal 1145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * RCC configuration registers. 1146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that 1147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * contains the current clock configuration. 1148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @param pFLatency Pointer on the Flash Latency. 1149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @retval None 1150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ 1151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) 1152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 4017 .loc 1 1152 1 4018 .cfi_startproc 4019 @ args = 0, pretend = 0, frame = 8 4020 @ frame_needed = 1, uses_anonymous_args = 0 4021 @ link register save eliminated. 4022 0000 80B4 push {r7} 4023 .cfi_def_cfa_offset 4 4024 .cfi_offset 7, -4 4025 0002 83B0 sub sp, sp, #12 4026 .cfi_def_cfa_offset 16 4027 0004 00AF add r7, sp, #0 4028 .cfi_def_cfa_register 7 4029 0006 7860 str r0, [r7, #4] 4030 0008 3960 str r1, [r7] 1153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check the parameters */ 1154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** assert_param(RCC_ClkInitStruct != NULL); 1155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** assert_param(pFLatency != NULL); 1156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 1157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Set all possible values for the Clock type parameter --------------------*/ 1158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | 4031 .loc 1 1158 32 4032 000a 7B68 ldr r3, [r7, #4] 4033 000c 0F22 movs r2, #15 4034 000e 1A60 str r2, [r3] 1159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 1160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get the SYSCLK configuration --------------------------------------------*/ 1161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); 4035 .loc 1 1161 51 4036 0010 124B ldr r3, .L254 4037 0012 5B68 ldr r3, [r3, #4] 4038 .loc 1 1161 37 ARM GAS /tmp/ccSuWkwR.s page 112 4039 0014 03F00302 and r2, r3, #3 4040 .loc 1 1161 35 4041 0018 7B68 ldr r3, [r7, #4] 4042 001a 5A60 str r2, [r3, #4] 1162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 1163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get the HCLK configuration ----------------------------------------------*/ 1164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); 4043 .loc 1 1164 52 4044 001c 0F4B ldr r3, .L254 4045 001e 5B68 ldr r3, [r3, #4] 4046 .loc 1 1164 38 4047 0020 03F0F002 and r2, r3, #240 4048 .loc 1 1164 36 4049 0024 7B68 ldr r3, [r7, #4] 4050 0026 9A60 str r2, [r3, #8] 1165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 1166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get the APB1 configuration ----------------------------------------------*/ 1167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1); 4051 .loc 1 1167 53 4052 0028 0C4B ldr r3, .L254 4053 002a 5B68 ldr r3, [r3, #4] 4054 .loc 1 1167 39 4055 002c 03F4E062 and r2, r3, #1792 4056 .loc 1 1167 37 4057 0030 7B68 ldr r3, [r7, #4] 4058 0032 DA60 str r2, [r3, #12] 1168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 1169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get the APB2 configuration ----------------------------------------------*/ 1170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3U); 4059 .loc 1 1170 54 4060 0034 094B ldr r3, .L254 4061 0036 5B68 ldr r3, [r3, #4] 4062 .loc 1 1170 39 4063 0038 DB08 lsrs r3, r3, #3 4064 003a 03F4E062 and r2, r3, #1792 4065 .loc 1 1170 37 4066 003e 7B68 ldr r3, [r7, #4] 4067 0040 1A61 str r2, [r3, #16] 1171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 1172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get the Flash Wait State (Latency) configuration ------------------------*/ 1173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); 4068 .loc 1 1173 32 4069 0042 074B ldr r3, .L254+4 4070 0044 1B68 ldr r3, [r3] 4071 .loc 1 1173 16 4072 0046 03F00702 and r2, r3, #7 4073 .loc 1 1173 14 4074 004a 3B68 ldr r3, [r7] 4075 004c 1A60 str r2, [r3] 1174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 4076 .loc 1 1174 1 4077 004e 00BF nop 4078 0050 0C37 adds r7, r7, #12 4079 .cfi_def_cfa_offset 4 4080 0052 BD46 mov sp, r7 4081 .cfi_def_cfa_register 13 4082 @ sp needed ARM GAS /tmp/ccSuWkwR.s page 113 4083 0054 5DF8047B ldr r7, [sp], #4 4084 .cfi_restore 7 4085 .cfi_def_cfa_offset 0 4086 0058 7047 bx lr 4087 .L255: 4088 005a 00BF .align 2 4089 .L254: 4090 005c 00100240 .word 1073876992 4091 0060 00200240 .word 1073881088 4092 .cfi_endproc 4093 .LFE141: 4095 .section .text.HAL_RCC_NMI_IRQHandler,"ax",%progbits 4096 .align 1 4097 .global HAL_RCC_NMI_IRQHandler 4098 .syntax unified 4099 .thumb 4100 .thumb_func 4102 HAL_RCC_NMI_IRQHandler: 4103 .LFB142: 1175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 1176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** 1177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @brief This function handles the RCC CSS interrupt request. 1178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note This API should be called under the NMI_Handler(). 1179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @retval None 1180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ 1181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** void HAL_RCC_NMI_IRQHandler(void) 1182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 4104 .loc 1 1182 1 4105 .cfi_startproc 4106 @ args = 0, pretend = 0, frame = 0 4107 @ frame_needed = 1, uses_anonymous_args = 0 4108 0000 80B5 push {r7, lr} 4109 .cfi_def_cfa_offset 8 4110 .cfi_offset 7, -8 4111 .cfi_offset 14, -4 4112 0002 00AF add r7, sp, #0 4113 .cfi_def_cfa_register 7 1183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check RCC CSSF flag */ 1184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(__HAL_RCC_GET_IT(RCC_IT_CSS)) 4114 .loc 1 1184 6 4115 0004 064B ldr r3, .L259 4116 0006 9B68 ldr r3, [r3, #8] 4117 0008 03F08003 and r3, r3, #128 4118 .loc 1 1184 5 4119 000c 802B cmp r3, #128 4120 000e 04D1 bne .L258 1185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 1186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* RCC Clock Security System interrupt user callback */ 1187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** HAL_RCC_CSSCallback(); 4121 .loc 1 1187 5 4122 0010 FFF7FEFF bl HAL_RCC_CSSCallback 1188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 1189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Clear RCC CSS pending bit */ 1190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** __HAL_RCC_CLEAR_IT(RCC_IT_CSS); 4123 .loc 1 1190 5 4124 0014 034B ldr r3, .L259+4 4125 0016 8022 movs r2, #128 ARM GAS /tmp/ccSuWkwR.s page 114 4126 0018 1A70 strb r2, [r3] 4127 .L258: 1191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 1192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 4128 .loc 1 1192 1 4129 001a 00BF nop 4130 001c 80BD pop {r7, pc} 4131 .L260: 4132 001e 00BF .align 2 4133 .L259: 4134 0020 00100240 .word 1073876992 4135 0024 0A100240 .word 1073877002 4136 .cfi_endproc 4137 .LFE142: 4139 .section .text.HAL_RCC_CSSCallback,"ax",%progbits 4140 .align 1 4141 .weak HAL_RCC_CSSCallback 4142 .syntax unified 4143 .thumb 4144 .thumb_func 4146 HAL_RCC_CSSCallback: 4147 .LFB143: 1193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 1194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** 1195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @brief RCC Clock Security System interrupt callback 1196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @retval none 1197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ 1198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** __weak void HAL_RCC_CSSCallback(void) 1199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { 4148 .loc 1 1199 1 4149 .cfi_startproc 4150 @ args = 0, pretend = 0, frame = 0 4151 @ frame_needed = 1, uses_anonymous_args = 0 4152 @ link register save eliminated. 4153 0000 80B4 push {r7} 4154 .cfi_def_cfa_offset 4 4155 .cfi_offset 7, -4 4156 0002 00AF add r7, sp, #0 4157 .cfi_def_cfa_register 7 1200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* NOTE : This function Should not be modified, when the callback is needed, 1201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** the HAL_RCC_CSSCallback could be implemented in the user file 1202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ 1203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } 4158 .loc 1 1203 1 4159 0004 00BF nop 4160 0006 BD46 mov sp, r7 4161 .cfi_def_cfa_register 13 4162 @ sp needed 4163 0008 5DF8047B ldr r7, [sp], #4 4164 .cfi_restore 7 4165 .cfi_def_cfa_offset 0 4166 000c 7047 bx lr 4167 .cfi_endproc 4168 .LFE143: 4170 .text 4171 .Letext0: 4172 .file 3 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl ARM GAS /tmp/ccSuWkwR.s page 115 4173 .file 4 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl 4174 .file 5 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h" 4175 .file 6 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h" 4176 .file 7 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h" 4177 .file 8 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h" 4178 .file 9 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h" 4179 .file 10 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h" 4180 .file 11 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h" ARM GAS /tmp/ccSuWkwR.s page 116 DEFINED SYMBOLS *ABS*:00000000 stm32f3xx_hal_rcc.c /tmp/ccSuWkwR.s:21 .rodata.aPLLMULFactorTable:00000000 $d /tmp/ccSuWkwR.s:24 .rodata.aPLLMULFactorTable:00000000 aPLLMULFactorTable /tmp/ccSuWkwR.s:28 .rodata.aPredivFactorTable:00000000 $d /tmp/ccSuWkwR.s:31 .rodata.aPredivFactorTable:00000000 aPredivFactorTable /tmp/ccSuWkwR.s:35 .text.HAL_RCC_DeInit:00000000 $t /tmp/ccSuWkwR.s:41 .text.HAL_RCC_DeInit:00000000 HAL_RCC_DeInit /tmp/ccSuWkwR.s:252 .text.HAL_RCC_DeInit:00000130 $d /tmp/ccSuWkwR.s:262 .text.HAL_RCC_OscConfig:00000000 $t /tmp/ccSuWkwR.s:268 .text.HAL_RCC_OscConfig:00000000 HAL_RCC_OscConfig /tmp/ccSuWkwR.s:742 .text.HAL_RCC_OscConfig:00000310 $d /tmp/ccSuWkwR.s:745 .text.HAL_RCC_OscConfig:00000314 $t /tmp/ccSuWkwR.s:1290 .text.HAL_RCC_OscConfig:00000660 $d /tmp/ccSuWkwR.s:1294 .text.HAL_RCC_OscConfig:00000668 $t /tmp/ccSuWkwR.s:1740 .text.HAL_RCC_OscConfig:0000099c $d /tmp/ccSuWkwR.s:1744 .text.HAL_RCC_OscConfig:000009a8 $t /tmp/ccSuWkwR.s:2136 .text.HAL_RCC_OscConfig:00000c6c $d /tmp/ccSuWkwR.s:2138 .text.HAL_RCC_OscConfig:00000c70 $t /tmp/ccSuWkwR.s:2601 .text.HAL_RCC_OscConfig:00000fcc $d /tmp/ccSuWkwR.s:2604 .text.HAL_RCC_OscConfig:00000fd0 $t /tmp/ccSuWkwR.s:2649 .text.HAL_RCC_OscConfig:00001018 $d /tmp/ccSuWkwR.s:2654 .text.HAL_RCC_ClockConfig:00000000 $t /tmp/ccSuWkwR.s:2660 .text.HAL_RCC_ClockConfig:00000000 HAL_RCC_ClockConfig /tmp/ccSuWkwR.s:3110 .text.HAL_RCC_ClockConfig:00000240 $d /tmp/ccSuWkwR.s:3114 .text.HAL_RCC_ClockConfig:00000248 $t /tmp/ccSuWkwR.s:3430 .text.HAL_RCC_GetSysClockFreq:00000000 HAL_RCC_GetSysClockFreq /tmp/ccSuWkwR.s:3208 .text.HAL_RCC_ClockConfig:000002cc $d /tmp/ccSuWkwR.s:3216 .text.HAL_RCC_MCOConfig:00000000 $t /tmp/ccSuWkwR.s:3222 .text.HAL_RCC_MCOConfig:00000000 HAL_RCC_MCOConfig /tmp/ccSuWkwR.s:3291 .text.HAL_RCC_MCOConfig:00000060 $d /tmp/ccSuWkwR.s:3296 .text.HAL_RCC_EnableCSS:00000000 $t /tmp/ccSuWkwR.s:3302 .text.HAL_RCC_EnableCSS:00000000 HAL_RCC_EnableCSS /tmp/ccSuWkwR.s:3360 .text.HAL_RCC_DisableCSS:00000000 $t /tmp/ccSuWkwR.s:3366 .text.HAL_RCC_DisableCSS:00000000 HAL_RCC_DisableCSS /tmp/ccSuWkwR.s:3424 .text.HAL_RCC_GetSysClockFreq:00000000 $t /tmp/ccSuWkwR.s:3594 .text.HAL_RCC_GetSysClockFreq:000000c0 $d /tmp/ccSuWkwR.s:3604 .text.HAL_RCC_GetHCLKFreq:00000000 $t /tmp/ccSuWkwR.s:3610 .text.HAL_RCC_GetHCLKFreq:00000000 HAL_RCC_GetHCLKFreq /tmp/ccSuWkwR.s:3637 .text.HAL_RCC_GetHCLKFreq:00000014 $d /tmp/ccSuWkwR.s:3642 .text.HAL_RCC_GetPCLK1Freq:00000000 $t /tmp/ccSuWkwR.s:3648 .text.HAL_RCC_GetPCLK1Freq:00000000 HAL_RCC_GetPCLK1Freq /tmp/ccSuWkwR.s:3709 .text.HAL_RCC_GetPCLK1Freq:0000003c $d /tmp/ccSuWkwR.s:3715 .text.HAL_RCC_GetPCLK2Freq:00000000 $t /tmp/ccSuWkwR.s:3721 .text.HAL_RCC_GetPCLK2Freq:00000000 HAL_RCC_GetPCLK2Freq /tmp/ccSuWkwR.s:3782 .text.HAL_RCC_GetPCLK2Freq:0000003c $d /tmp/ccSuWkwR.s:3788 .text.HAL_RCC_GetOscConfig:00000000 $t /tmp/ccSuWkwR.s:3794 .text.HAL_RCC_GetOscConfig:00000000 HAL_RCC_GetOscConfig /tmp/ccSuWkwR.s:4004 .text.HAL_RCC_GetOscConfig:00000118 $d /tmp/ccSuWkwR.s:4009 .text.HAL_RCC_GetClockConfig:00000000 $t /tmp/ccSuWkwR.s:4015 .text.HAL_RCC_GetClockConfig:00000000 HAL_RCC_GetClockConfig /tmp/ccSuWkwR.s:4090 .text.HAL_RCC_GetClockConfig:0000005c $d /tmp/ccSuWkwR.s:4096 .text.HAL_RCC_NMI_IRQHandler:00000000 $t /tmp/ccSuWkwR.s:4102 .text.HAL_RCC_NMI_IRQHandler:00000000 HAL_RCC_NMI_IRQHandler /tmp/ccSuWkwR.s:4146 .text.HAL_RCC_CSSCallback:00000000 HAL_RCC_CSSCallback /tmp/ccSuWkwR.s:4134 .text.HAL_RCC_NMI_IRQHandler:00000020 $d /tmp/ccSuWkwR.s:4140 .text.HAL_RCC_CSSCallback:00000000 $t ARM GAS /tmp/ccSuWkwR.s page 117 UNDEFINED SYMBOLS HAL_GetTick HAL_InitTick SystemCoreClock uwTickPrio AHBPrescTable HAL_GPIO_Init APBPrescTable