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Author SHA1 Message Date
Kilian Bracher c5c4184d6b balancing update 2024-07-08 17:50:17 +02:00
1 changed files with 12 additions and 14 deletions
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Core/Src/ADBMS_Abstraction.c
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@ -131,27 +131,25 @@ uint8 amsAuxAndStatusMeasurement(Cell_Module* module) {
uint8 amsConfigBalancing(uint32 channels, uint8 dutyCycle) { uint8 amsConfigBalancing(uint32 channels, uint8 dutyCycle) {
uint8 buffer_a[PWM_GROUP_A_SIZE] = {}; uint8 buffer_a[PWM_GROUP_A_SIZE] = {};
uint8 buffer_b[PWM_GROUP_B_SIZE] = {}; uint8 buffer_b[PWM_GROUP_B_SIZE] = {};
CHECK_RETURN(readCMD(RDPWMA, buffer_a, CFG_GROUP_A_SIZE)); CHECK_RETURN(readCMD(RDPWMA, buffer_a, PWM_GROUP_A_SIZE));
CHECK_RETURN(readCMD(RDPWMB, buffer_b, CFG_GROUP_B_SIZE)); CHECK_RETURN(readCMD(RDPWMB, buffer_b, PWM_GROUP_B_SIZE));
if (dutyCycle > 0x0F) { // there are only 4 bits for duty cycle if (dutyCycle > 0x0F) { // there are only 4 bits for duty cycle
return 1; return 1;
} }
#warning fixme buffer_a[0] = ((channels & (1 << 0)) ? dutyCycle : 0) | ((channels & (1 << 1)) ? (dutyCycle << 4) : 0);
buffer_a[1] = ((channels & (1 << 2)) ? dutyCycle : 0) | ((channels & (1 << 3)) ? (dutyCycle << 4) : 0);
buffer_a[2] = ((channels & (1 << 4)) ? dutyCycle : 0) | ((channels & (1 << 5)) ? (dutyCycle << 4) : 0);
buffer_a[3] = ((channels & (1 << 6)) ? dutyCycle : 0) | ((channels & (1 << 7)) ? (dutyCycle << 4) : 0);
buffer_a[4] = ((channels & (1 << 8)) ? dutyCycle : 0) | ((channels & (1 << 9)) ? (dutyCycle << 4) : 0);
buffer_a[5] = ((channels & (1 << 10)) ? dutyCycle : 0) | ((channels & (1 << 11)) ? (dutyCycle << 4) : 0);
for (size_t i = 0; i < 16; i += 2) { buffer_b[0] = ((channels & (1 << 12)) ? dutyCycle : 0) | ((channels & (1 << 13)) ? (dutyCycle << 4) : 0);
if (i < 12) { // cells 0, 1 are in regbuffer[0], cells 2, 3 in regbuffer[1], ... buffer_b[1] = ((channels & (1 << 14)) ? dutyCycle : 0) | ((channels & (1 << 15)) ? (dutyCycle << 4) : 0);
buffer_a[i / 2] = ((channels & (1 << (i + 1))) ? (dutyCycle << 4) : 0) |
((channels & (1 << i)) ? dutyCycle : 0);
} else {
buffer_b[(i - 12) / 2] = ((channels & (1 << (i + 1))) ? (dutyCycle << 4) : 0) |
((channels & (1 << i)) ? dutyCycle : 0);
}
}
CHECK_RETURN(writeCMD(WRPWMA, buffer_a, CFG_GROUP_A_SIZE)); CHECK_RETURN(writeCMD(WRPWMA, buffer_a, PWM_GROUP_A_SIZE));
CHECK_RETURN(writeCMD(WRPWMB, buffer_b, CFG_GROUP_B_SIZE)); CHECK_RETURN(writeCMD(WRPWMB, buffer_b, PWM_GROUP_B_SIZE));
return 0; return 0;
} }