2 Commits

Author SHA1 Message Date
c5c4184d6b balancing update 2024-07-08 17:50:17 +02:00
537641a53a V1.0 2024-07-04 18:07:32 +03:00
4 changed files with 44 additions and 26 deletions

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@ -20,8 +20,6 @@ CCR * DUTY_CYCLE
CCR: 1/20 -> 500, 2/20 -> 1000
*/
#define POWERGROUND_FREQ 50
#define POWERGROUND_MAX_DUTY_CYCLE 0.1
#define POWERGROUND_MIN_DUTY_CYCLE 0.05
//#define BATTERY_COOLING_FREQ 20000
@ -29,5 +27,6 @@ void PWM_control_init(TIM_HandleTypeDef* powerground, TIM_HandleTypeDef* battery
void PWM_powerground_control(uint8_t percent);
void PWM_battery_cooling_control(uint8_t percent);
void PWM_set_throttle();
#endif /* INC_CHANNEL_CONTROL_H */

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@ -131,27 +131,25 @@ uint8 amsAuxAndStatusMeasurement(Cell_Module* module) {
uint8 amsConfigBalancing(uint32 channels, uint8 dutyCycle) {
uint8 buffer_a[PWM_GROUP_A_SIZE] = {};
uint8 buffer_b[PWM_GROUP_B_SIZE] = {};
CHECK_RETURN(readCMD(RDPWMA, buffer_a, CFG_GROUP_A_SIZE));
CHECK_RETURN(readCMD(RDPWMB, buffer_b, CFG_GROUP_B_SIZE));
CHECK_RETURN(readCMD(RDPWMA, buffer_a, PWM_GROUP_A_SIZE));
CHECK_RETURN(readCMD(RDPWMB, buffer_b, PWM_GROUP_B_SIZE));
if (dutyCycle > 0x0F) { // there are only 4 bits for duty cycle
return 1;
}
#warning fixme
buffer_a[0] = ((channels & (1 << 0)) ? dutyCycle : 0) | ((channels & (1 << 1)) ? (dutyCycle << 4) : 0);
buffer_a[1] = ((channels & (1 << 2)) ? dutyCycle : 0) | ((channels & (1 << 3)) ? (dutyCycle << 4) : 0);
buffer_a[2] = ((channels & (1 << 4)) ? dutyCycle : 0) | ((channels & (1 << 5)) ? (dutyCycle << 4) : 0);
buffer_a[3] = ((channels & (1 << 6)) ? dutyCycle : 0) | ((channels & (1 << 7)) ? (dutyCycle << 4) : 0);
buffer_a[4] = ((channels & (1 << 8)) ? dutyCycle : 0) | ((channels & (1 << 9)) ? (dutyCycle << 4) : 0);
buffer_a[5] = ((channels & (1 << 10)) ? dutyCycle : 0) | ((channels & (1 << 11)) ? (dutyCycle << 4) : 0);
for (size_t i = 0; i < 16; i += 2) {
if (i < 12) { // cells 0, 1 are in regbuffer[0], cells 2, 3 in regbuffer[1], ...
buffer_a[i / 2] = ((channels & (1 << (i + 1))) ? (dutyCycle << 4) : 0) |
((channels & (1 << i)) ? dutyCycle : 0);
} else {
buffer_b[(i - 12) / 2] = ((channels & (1 << (i + 1))) ? (dutyCycle << 4) : 0) |
((channels & (1 << i)) ? dutyCycle : 0);
}
}
buffer_b[0] = ((channels & (1 << 12)) ? dutyCycle : 0) | ((channels & (1 << 13)) ? (dutyCycle << 4) : 0);
buffer_b[1] = ((channels & (1 << 14)) ? dutyCycle : 0) | ((channels & (1 << 15)) ? (dutyCycle << 4) : 0);
CHECK_RETURN(writeCMD(WRPWMA, buffer_a, CFG_GROUP_A_SIZE));
CHECK_RETURN(writeCMD(WRPWMB, buffer_b, CFG_GROUP_B_SIZE));
CHECK_RETURN(writeCMD(WRPWMA, buffer_a, PWM_GROUP_A_SIZE));
CHECK_RETURN(writeCMD(WRPWMB, buffer_b, PWM_GROUP_B_SIZE));
return 0;
}

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@ -1,4 +1,6 @@
#include "PWM_control.h"
#include "stm32f3xx_hal.h"
#include <stdint.h>
uint8_t battery_cooling_status;
//uint32_t powerground1_CCR, powerground2_CCR, battery_cooling_CCR;
@ -13,29 +15,49 @@ TIM_HandleTypeDef* powerground, *battery_cooling;
void PWM_control_init(TIM_HandleTypeDef* pg, TIM_HandleTypeDef* bat_cool){
powerground_status = 0;
battery_cooling_status = 0;
powerground = pg;
battery_cooling = bat_cool;
HAL_TIM_PWM_Start(pg, TIM_CHANNEL_1); //TIM15CH1
HAL_TIM_PWM_Start(pg, TIM_CHANNEL_2); //TIM15CH2
HAL_TIM_PWM_Start(bat_cool, TIM_CHANNEL_3); //TIM1CH3
powerground = pg;
battery_cooling = bat_cool;
__HAL_TIM_SET_COMPARE(powerground, TIM_CHANNEL_1, 2000);
__HAL_TIM_SET_COMPARE(powerground, TIM_CHANNEL_2, 2000);
__HAL_TIM_SET_COMPARE(powerground, TIM_CHANNEL_1, 0);
__HAL_TIM_SET_COMPARE(powerground, TIM_CHANNEL_2, 0);
//PWM_powerground_control(0);
//__HAL_TIM_SET_COMPARE(battery_cooling, TIM_CHANNEL_3, 2000);
}
/*
controls the duty cycle of the fans by setting the CCR of the channel percent/100 = x/ARR
DUTYCYCLE = 40000 * X/100
*/
void PWM_powerground_control(uint8_t percent){
if (percent > 100) //something went wrong
return;
powerground_status = percent;
int ccr = 2000 + ((2000) * (percent/100.0));
__HAL_TIM_SET_COMPARE(powerground, TIM_CHANNEL_1, ccr);
__HAL_TIM_SET_COMPARE(powerground, TIM_CHANNEL_2, 2000 + ((2000) * (percent/100.0)));
__HAL_TIM_SET_COMPARE(powerground, TIM_CHANNEL_2, ccr);
//TIM15->CCR1 = (TIM15->ARR*POWERGROUND_MAX_DUTY_CYCLE-TIM15->ARR*POWERGROUND_MIN_DUTY_CYCLE) * (percent/100.0) + TIM15->ARR*POWERGROUND_MIN_DUTY_CYCLE;
}
void PWM_set_throttle(){
uint32_t timestamp = HAL_GetTick() + 5000;
while (timestamp > HAL_GetTick()) {}
__HAL_TIM_SET_COMPARE(powerground, TIM_CHANNEL_1, 4000);
__HAL_TIM_SET_COMPARE(powerground, TIM_CHANNEL_2, 4000);
timestamp = HAL_GetTick() + 2000;
while (timestamp > HAL_GetTick()) {}
__HAL_TIM_SET_COMPARE(powerground, TIM_CHANNEL_1, 2000);
__HAL_TIM_SET_COMPARE(powerground, TIM_CHANNEL_2, 2000);
timestamp = HAL_GetTick() + 1000;
while (timestamp > HAL_GetTick()) {}
}
void PWM_battery_cooling_control(uint8_t percent){}

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@ -74,8 +74,10 @@ State sm_update_precharge(){
case STATE_INACTIVE: // if CAN Signal 0000 0000 then immidiete shutdown
return STATE_DISCHARGE;
case STATE_PRECHARGE:
if (RELAY_BAT_SIDE_VOLTAGE-RELAY_ESC_SIDE_VOLTAGE < 100)
if (RELAY_BAT_SIDE_VOLTAGE-RELAY_ESC_SIDE_VOLTAGE < 100){
PWM_set_throttle();
return STATE_READY;
}
break;
case STATE_DISCHARGE:
return STATE_DISCHARGE;
@ -228,21 +230,18 @@ void sm_handle_ams_in(const uint8_t *data){
switch (data[0]) {
case 0x00:
if (state.current_state != STATE_INACTIVE){
PWM_powerground_control(0);
state.target_state = STATE_DISCHARGE;
}
break;
case 0x01:
if (state.target_state == STATE_INACTIVE || state.target_state == STATE_DISCHARGE){
PWM_powerground_control(0);
state.target_state = STATE_PRECHARGE;
} else if (state.target_state == STATE_ACTIVE){
PWM_powerground_control(0);
state.target_state = STATE_READY;
}
break;
case 0x02:
if (state.current_state == STATE_READY){
if (state.current_state == STATE_READY || state.current_state == STATE_ACTIVE){
PWM_powerground_control(data[1]);
state.target_state = STATE_ACTIVE; // READY -> ACTIVE
}