From c5c4184d6b011b3889dea4772cacc4efcbaabd23 Mon Sep 17 00:00:00 2001
From: kbracher <k.bracher@fasttube.de>
Date: Mon, 8 Jul 2024 17:50:17 +0200
Subject: [PATCH] balancing update

---
 Core/Src/ADBMS_Abstraction.c | 26 ++++++++++++--------------
 1 file changed, 12 insertions(+), 14 deletions(-)

diff --git a/Core/Src/ADBMS_Abstraction.c b/Core/Src/ADBMS_Abstraction.c
index 15b357f..fc9ce77 100644
--- a/Core/Src/ADBMS_Abstraction.c
+++ b/Core/Src/ADBMS_Abstraction.c
@@ -131,27 +131,25 @@ uint8 amsAuxAndStatusMeasurement(Cell_Module* module) {
 uint8 amsConfigBalancing(uint32 channels, uint8 dutyCycle) {
   uint8 buffer_a[PWM_GROUP_A_SIZE] = {};
   uint8 buffer_b[PWM_GROUP_B_SIZE] = {};
-  CHECK_RETURN(readCMD(RDPWMA, buffer_a, CFG_GROUP_A_SIZE));
-  CHECK_RETURN(readCMD(RDPWMB, buffer_b, CFG_GROUP_B_SIZE));
+  CHECK_RETURN(readCMD(RDPWMA, buffer_a, PWM_GROUP_A_SIZE));
+  CHECK_RETURN(readCMD(RDPWMB, buffer_b, PWM_GROUP_B_SIZE));
 
   if (dutyCycle > 0x0F) { // there are only 4 bits for duty cycle
     return 1;
   }
 
-  #warning fixme
+  buffer_a[0] = ((channels & (1 << 0)) ? dutyCycle : 0) | ((channels & (1 << 1)) ? (dutyCycle << 4) : 0);
+  buffer_a[1] = ((channels & (1 << 2)) ? dutyCycle : 0) | ((channels & (1 << 3)) ? (dutyCycle << 4) : 0);
+  buffer_a[2] = ((channels & (1 << 4)) ? dutyCycle : 0) | ((channels & (1 << 5)) ? (dutyCycle << 4) : 0);
+  buffer_a[3] = ((channels & (1 << 6)) ? dutyCycle : 0) | ((channels & (1 << 7)) ? (dutyCycle << 4) : 0);
+  buffer_a[4] = ((channels & (1 << 8)) ? dutyCycle : 0) | ((channels & (1 << 9)) ? (dutyCycle << 4) : 0);
+  buffer_a[5] = ((channels & (1 << 10)) ? dutyCycle : 0) | ((channels & (1 << 11)) ? (dutyCycle << 4) : 0);
 
-  for (size_t i = 0; i < 16; i += 2) {
-    if (i < 12) { // cells 0, 1 are in regbuffer[0], cells 2, 3 in regbuffer[1], ...
-      buffer_a[i / 2] = ((channels & (1 << (i + 1))) ? (dutyCycle << 4) : 0) |
-                         ((channels & (1 << i)) ? dutyCycle : 0);
-    } else {
-      buffer_b[(i - 12) / 2] = ((channels & (1 << (i + 1))) ? (dutyCycle << 4) : 0) |
-                                ((channels & (1 << i)) ? dutyCycle : 0);
-    }
-  }
+  buffer_b[0] = ((channels & (1 << 12)) ? dutyCycle : 0) | ((channels & (1 << 13)) ? (dutyCycle << 4) : 0);
+  buffer_b[1] = ((channels & (1 << 14)) ? dutyCycle : 0) | ((channels & (1 << 15)) ? (dutyCycle << 4) : 0);
 
-  CHECK_RETURN(writeCMD(WRPWMA, buffer_a, CFG_GROUP_A_SIZE));
-  CHECK_RETURN(writeCMD(WRPWMB, buffer_b, CFG_GROUP_B_SIZE));
+  CHECK_RETURN(writeCMD(WRPWMA, buffer_a, PWM_GROUP_A_SIZE));
+  CHECK_RETURN(writeCMD(WRPWMB, buffer_b, PWM_GROUP_B_SIZE));
 
   return 0;
 }