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Drivers/CMSIS/NN/Include/arm_nn_tables.h
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59
Drivers/CMSIS/NN/Include/arm_nn_tables.h
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/* ----------------------------------------------------------------------
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* Project: CMSIS NN Library
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* Title: arm_nn_tables.h
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* Description: Extern declaration for NN tables
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*
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* $Date: 17. January 2018
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* $Revision: V.1.0.0
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*
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* Target Processor: Cortex-M cores
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* -------------------------------------------------------------------- */
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/*
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* Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef _ARM_NN_TABLES_H
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#define _ARM_NN_TABLES_H
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#include "arm_math.h"
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/**
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* @brief tables for various activation functions
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*
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*/
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extern const q15_t sigmoidTable_q15[256];
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extern const q7_t sigmoidTable_q7[256];
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extern const q7_t tanhTable_q7[256];
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extern const q15_t tanhTable_q15[256];
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/**
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* @brief 2-way tables for various activation functions
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*
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* 2-way table, H table for value larger than 1/4
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* L table for value smaller than 1/4, H table for remaining
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* We have this only for the q15_t version. It does not make
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* sense to have it for q7_t type
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*/
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extern const q15_t sigmoidHTable_q15[192];
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extern const q15_t sigmoidLTable_q15[128];
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extern const q15_t sigmoidLTable_q15[128];
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extern const q15_t sigmoidHTable_q15[192];
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#endif /* ARM_NN_TABLES_H */
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1010
Drivers/CMSIS/NN/Include/arm_nnfunctions.h
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1010
Drivers/CMSIS/NN/Include/arm_nnfunctions.h
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File diff suppressed because it is too large
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202
Drivers/CMSIS/NN/Include/arm_nnsupportfunctions.h
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202
Drivers/CMSIS/NN/Include/arm_nnsupportfunctions.h
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/*
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* Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/* ----------------------------------------------------------------------
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* Project: CMSIS NN Library
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* Title: arm_nnsupportfunctions.h
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* Description: Public header file of support functions for CMSIS NN Library
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*
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* $Date: 13. July 2018
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* $Revision: V.1.0.0
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*
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* Target Processor: Cortex-M cores
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* -------------------------------------------------------------------- */
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#ifndef _ARM_NNSUPPORTFUNCTIONS_H_
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#define _ARM_NNSUPPORTFUNCTIONS_H_
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#include "arm_math.h"
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#include "arm_common_tables.h"
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//#include <cstring>
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/**
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* @brief Union for SIMD access of Q31/Q15/Q7 types
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*/
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union arm_nnword
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{
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q31_t word;
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/**< Q31 type */
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q15_t half_words[2];
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/**< Q15 type */
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q7_t bytes[4];
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/**< Q7 type */
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};
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/**
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* @brief Struct for specifying activation function types
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*
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*/
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typedef enum
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{
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ARM_SIGMOID = 0,
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/**< Sigmoid activation function */
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ARM_TANH = 1,
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/**< Tanh activation function */
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} arm_nn_activation_type;
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/**
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* @defgroup nndata_convert Neural Network Data Conversion Functions
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*
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* Perform data type conversion in-between neural network operations
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*
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*/
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/**
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* @brief Converts the elements of the Q7 vector to Q15 vector without left-shift
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* @param[in] *pSrc points to the Q7 input vector
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* @param[out] *pDst points to the Q15 output vector
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* @param[in] blockSize length of the input vector
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* @return none.
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*
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*/
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void arm_q7_to_q15_no_shift(const q7_t * pSrc, q15_t * pDst, uint32_t blockSize);
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/**
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* @brief Converts the elements of the Q7 vector to reordered Q15 vector without left-shift
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* @param[in] *pSrc points to the Q7 input vector
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* @param[out] *pDst points to the Q15 output vector
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* @param[in] blockSize length of the input vector
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* @return none.
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*
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*/
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void arm_q7_to_q15_reordered_no_shift(const q7_t * pSrc, q15_t * pDst, uint32_t blockSize);
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#if defined (ARM_MATH_DSP)
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/**
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* @brief read and expand one Q7 word into two Q15 words
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*/
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__STATIC_FORCEINLINE void *read_and_pad(void *source, q31_t * out1, q31_t * out2)
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{
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q31_t inA = *__SIMD32(source)++;
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q31_t inAbuf1 = __SXTB16(__ROR(inA, 8));
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q31_t inAbuf2 = __SXTB16(inA);
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#ifndef ARM_MATH_BIG_ENDIAN
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*out2 = __PKHTB(inAbuf1, inAbuf2, 16);
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*out1 = __PKHBT(inAbuf2, inAbuf1, 16);
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#else
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*out1 = __PKHTB(inAbuf1, inAbuf2, 16);
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*out2 = __PKHBT(inAbuf2, inAbuf1, 16);
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#endif
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return source;
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}
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/**
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* @brief read and expand one Q7 word into two Q15 words with reordering
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*/
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__STATIC_FORCEINLINE void *read_and_pad_reordered(void *source, q31_t * out1, q31_t * out2)
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{
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q31_t inA = *__SIMD32(source)++;
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#ifndef ARM_MATH_BIG_ENDIAN
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*out2 = __SXTB16(__ROR(inA, 8));
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*out1 = __SXTB16(inA);
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#else
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*out1 = __SXTB16(__ROR(inA, 8));
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*out2 = __SXTB16(inA);
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#endif
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return source;
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}
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#endif
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/**
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* @defgroup NNBasicMath Basic Math Functions for Neural Network Computation
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*
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* Basic Math Functions for Neural Network Computation
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*
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*/
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/**
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* @brief Q7 vector multiplication with variable output shifts
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* @param[in] *pSrcA pointer to the first input vector
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* @param[in] *pSrcB pointer to the second input vector
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* @param[out] *pDst pointer to the output vector
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* @param[in] out_shift amount of right-shift for output
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* @param[in] blockSize number of samples in each vector
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* @return none.
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*
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* <b>Scaling and Overflow Behavior:</b>
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* \par
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* The function uses saturating arithmetic.
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* Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.
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*/
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void arm_nn_mult_q15(
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q15_t * pSrcA,
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q15_t * pSrcB,
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q15_t * pDst,
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const uint16_t out_shift,
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uint32_t blockSize);
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/**
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* @brief Q7 vector multiplication with variable output shifts
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* @param[in] *pSrcA pointer to the first input vector
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* @param[in] *pSrcB pointer to the second input vector
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* @param[out] *pDst pointer to the output vector
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* @param[in] out_shift amount of right-shift for output
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* @param[in] blockSize number of samples in each vector
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* @return none.
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*
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* <b>Scaling and Overflow Behavior:</b>
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* \par
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* The function uses saturating arithmetic.
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* Results outside of the allowable Q7 range [0x80 0x7F] will be saturated.
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*/
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void arm_nn_mult_q7(
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q7_t * pSrcA,
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q7_t * pSrcB,
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q7_t * pDst,
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const uint16_t out_shift,
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uint32_t blockSize);
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/**
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* @brief defition to adding rouding offset
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*/
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#ifndef ARM_NN_TRUNCATE
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#define NN_ROUND(out_shift) ( 0x1 << (out_shift - 1) )
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#else
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#define NN_ROUND(out_shift) 0
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif
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